CP80 Hardware Manual PDF

CP80
Hardware Manual
CP80
Hardware Manual
LTX Corporation
LTX Park at
Westwood, Massachusetts 02090
June 1983
LTX Part #: 999-6020
12345678910
Some of the material presented in this manual has been reprinted with the
permission of the following companies:
Data General Corporation
Anelogic Corporation
Dataproducts Corporation
Mannesmsnn Ta!ly Corporation
Control Data Corporation
Intersil Systems Corporation
Spectra Logic Corporation
Custom Systems Inc

TABLE OF CONTENTS
SECTION TITLE PAGE
CHAPTER 1
INTRODUCTION AND OPERATING PROCEDURES
1,1 OBJECTIVE .......................... 1-1

1.2 INTRODUCTION ......................... 1-1
I .3 LTX77 POWERUP PROCEDURE ................... 1-3
1.4 BOOTING THE LTX OPERATING SYSTEM............... 1-4
1.5 MANUALLY BOOTING THE LTX OPERATING SYSTEM .......... 1-6
1,5.1 Manually Booting a Single Computer ............ 1-6
1.5.2 Manually Booting The "Slave" Computer .......... 1-7
1.6 LTX77 POWERDOWNPROCEDURE .................. 1-9
1.7 LTX SYSTEM SOFTWARE INSTALLATION PROCEDURE (TAPE TO DISK) . . 1-10
1.7 LTX SYSTEM SOFTWARE INSTALLATION PROCEDURE (TAPE TO DISK) DUAL. .
PROCESSOR .......................... 1-11
CHAPTER 2
AC DISTRIBUTION
2,1 INTRODUCTION ......................... 2-1

2.2 POWERDISTRIBUTION ...................... 2-3
2.2,1 Front Panel ....................... 2-5
2.2.2 Calibrator ........................ 2-6
2.3 BULKHEADCONNECTORS ..................... 2-6
CHAPTER 3
THEORY OF OPERATION
3.1 INTRODUCTION ......................... 3-1

3.2 SINGLE PROCESSOR CP80 .................... 3-2
3.3 THE NOVA3 .......................... 3-3
3.3.1 The NOVA3 CPU...................... 3-3
3.3.2 CPU Data Manipulation Logic ............... 3-5
3.3.3 CPU Control Logic ................... 3-7
3.3.4 Data Channel Breaks ................... 3-8
3,3.5 Memory Management Unit .................. 3-8
3.3,6 Floating Point Units I and 2 ............... 3-8
3.3.7 Multiply/Divide Unit ................... 3-8
3.4 DISK STORAGE ......................... 3-13
3.4,1 Single Computer Disk Structure .............. 3-13
3.4.2 Disk Controller Board ................. 3-13
3.4.3 Seeking ......................... 3-14
3.4.4 Reading and Writing ................... 3-14
3.5 THE TAPE DRIVE........................ 3-15
3.6 THE LTX CALIBRATION UNIT ................... 3-15
3.7 CP80 INTERFACE........................ 3-16
3,7,1 CPSO Burst Interface ................... 3-16
3.8 CP80 DATA BUS ........................ 3-18
3,9 SLOT SAVER II BOARD..................... 3-21
3.10 ARRAY PROCESSOR AP894 .................... 3-21
i
SECTION TITLE PAGE
3.11 PX81 OPTION ........................ 3-23
3.12 DUALCOMPUTER CP80...................... 3-23
3.12.1 Computer Hi erachy .................... 3-23
3.13 80 MBDISK.......................... 3-26
3.13,1 Dual Computer Disk Structure ............... 3-26
3.14 LINE PRINTER ......................... 3-26
3.15 MAGNETICTAPE UNIT ...................... 3-26
3.16 CALIBRATORUNIT ....................... 3-27
3.17 CP80 DUAL PROCESSOR DATA BUS................. 3-27
CHAPTER4
THE NOVA 3
4.1 INTRODUCTION........................ 4-1

4.1.1 The CPU ......................... 4-1
4.1 .2 Memory.......................... 4-1
4.1.3 ME128 .......................... 4-2
4.1.4 ME51 2 .......................... 4-2
4.1,5 The Memory Management Unit ................ 4-7
4.1 .6 The Multiply Divide Unit ................. 4-7
4.1.7 Floating Point Units I and 2 ............... 4-7
4.2 THE NOVA 3 CHASSIS...................... 4-7
4.2.1 The NOVABackplane .................... 4-7
4.3 THE NOVA3 POWER SUPPLY................... 4-11
4.3.1 Power Switch ....................... 4-11
4.3.2 Convenience Outlet .................... 4-11
4.3.3 AC-to-Unregul ated DC Conversion ............. 4-11
4.3.4 Power Fail Circuitry ................... 4-11
4.3.5 Auxiliary Voltage Generator ............... 4-13
4.3.6 Fuses .......................... 4-13
4.4 THE CONSOLE ......................... 4-15
4,5 NOVAFRONTPANEL OPERATION .................. 4-15
4.5.1 Lamps ......................... 4-15
4.5.2 Console Switches ..................... 4-16
CHAPTER 5
CDC 80 MEGABYTE MINI MODULE DISK
5.1 INTRODUCTION ......................... 5-1

5.2 DISK DIRECTORYSTRUCTURE ................... 5-3
5.2.1 Single Computer CP80................... 5-3
5.2.2 Dual Computer CP80.................... 5-3
5.3 EQUIPMENTDESCRIPTION.................... 5-3
5.3.1 Mini Module Assembly ................... 5-3
5.3.2 Frame Assembly ...................... 5-5
5.3.3 Logic Chassis ..................... 5-5
5.3.4 Front Panel ....................... 5-5
5.3.5 Disks ........................
.. 5-5
5.3.6 Fault/contro I Card ................... 5-6
5.3.7 Dual Channel Steering Card ................ 5-6
5.4 DISK ERROR WORDS ....................... 5-6
5.5 DISK POWER SUPPLY...................... 5-13
5.6 MOVING THE CDC DISK DRIVE .................. 5-17
i' 5.6.1 Securing The Disk .................... 5-17
5.7 DISK FORMATTING PROCEDURE .................. 5-22
5.8 DISK INITIALIZATION AND RELIABILITY PROCEDURE........ 5-23
ii
SECTION TITLE PAGE
5.9 CREATINGA DATA FILE BACKUPTAPE (DISK TO TAPE) ....... 5-27

5.10 CREATING AN LTX OPERATING SYSTEM BACKUP TAPE (DISK TO TAPE)· 5-30
5-11 CREATING AN LTX OPERATING SYSTEM BACKUP TAPE (TAPE TO TAPE). 5-31
CHAPTER 6
CP80 TAPE TRANSPORT
6I INTRODUCTION 6-1
6.2 THE TAPE TRANSPORT ...................... 6-1
6.3 TAPE PATH ELEMENTS ...................... 6-1
6.3.1 Read/Wri te Head ..................... 6-1
6.3,2 Capstan ......................... 6-1
6.3.3 Suction Tape Cleaner ................... 6-1
6.3.4 Tape Gui des ....................... 6-3
6.3·5 Vacuum Columns...................... 6-3
6.3.6 BOT/EOT Sensor ...................... 6-3
6.4 TAPE MARKERS ......................... 6-3
6.4.1 Beginning of Tape Marker ................. 6-3
6.4.2 End of Tape Marker .................... 6-3
6.5 TAPE DRIVE FRONTPANEL .................... 6-5
6.6 TAPE TRANSPORTPOWERDISTRIBUTION .............. 6-6
6.7 TAPE LOADINGPROCEDURES ................... 6-8
6.7.1 Loading a Tape ...................... 6-8
6.7.2 Unloading the Tape Transport ............... 6-10
6.7.3 Loading Backwards .................... 6-10
6.8 TAPE TRANSPORTMAINTENANCE .................. 6-11
CHAPTER 7
CP80 DASHER DISPLAY TERMINAL
7.1 INTRODUCTION ......................... 7-1

7.2 SLOTSAVERII ........................ 7-1
7.3 TERMINAL/CP80 CONNECTORS ................... 7-1
7.4 OVERVIEW ........................... 7-3
7.4.1 The Key Board ...................... 7-3
7.4.2 Video Monitor ...................... 7-3
7.4.3 The Video Board ..................... 7-3
7.4.4 Control Logic Board ................... 7-3
7.4.5 Memory Board ....................... 7-3
7.4.6 Asynchronous Interface Board ............... 7-4
7.5 DISPLAY TERMINALPOWERSUPPLY ................ 7-4
CHAPTER 8
CP80 LINE PRINTER OPTIONS
8.1 INTRODUCTION......................... 8-1

8.2 TALLY MT1602......................... 8-1
8,3 DATAPRODUCTS PRINTERS .................... 8-4
8.4 CP80 SYSTEMLINE PRINTER POWERSUPPLIES ........... 8-6
iii
S_.CTION TITLE PAGE
CHAPTER 9
THE CALIBRATOR
9.1 INTRODUCTION ......................... 9-1

9.2 THE CALIBRATOR ....................... 9-1
9.3 CALIBRATOR CALIBRATION.................... 9-2
9.3.1 First Level Calibration ................. 9-2
9.3.2 Second Level Calibration ................. 9-3
9.4 CALIBRATORREARPANEL .................. 9-4
9.5 CALIBRATOR DATA FILE INSTALLATION PROCEDURE ......... 9-6
9.5,1 Loading a Calibrator Data File From Tape ......... 9-6
9.5.2 Creating a Backup Calibrator Data File on Tape ...... 9-7
9.6 CALIBRATION PROCEDURE.................... 9-9
9.6.1 Measurement of LTX Calibration Reference Unit .... 9-9
9,6.2 Required Equipment For Calibration ............ 9-10
9.6.3 Calibration Conditions, Limits, Records ....... 9-11
9.6.4 Measurement Procedure .................. 9-13
9.6,5 Resistance Measurement ................. 9-14
9.6.6 Voltage Measurement ................... 9-17
9.6.7 Frequency Measurement ................. 9-19
CHAPTER 1 0
OPTIONAL ARRAY PROCESSOR
10,1 INTRODUCTION........................ 1 0-1

10.2 CP80 BURST INTERFACE .................. 10-1
iv
ILLUSTRATIONS
FIGURE TITLE PAGE
1-1 CP80 DUAL COMPUTER

SYSTEM .................. 1-2
1-2 NOVA3 CPU BOARDOUTLINE.................. 1-7
2-1 CP80 AC POWERDISTRIBUTION DIAGRAM.............. 2-1

2-2 CP80/TS80 AC DISTRIBUTION ................. 2-2
2-3 AC DISTRIBUTION BOX ..................... 2-4
2-4 CP80 FRONT PANEL SCHEMATIC.................. 2-5
2-5 CP80 LEFT AND RIGHT BULKHEADS................ 2-7
3-1 DUAL COMPUTERRACK DIAGRAM.................. 3-1

3-2 SINGLE COMPUTERBLOCK DIAGRAM ................ 3-2
3-3 DATA MANIPULATION AND CONTROL LOGIC INTERCONNECTIONS..... 3-3
3-4 NOVA 3 INTERNAL BUS STRUCTURE................ 3-4
3-5 DATA MANIPULATION LOGIC ................... 3-6
3-6 CPU CONTROLLOGIC ...................... 3-7
3-7 MMUFUNCTIONAL BLOCK DIAGRAM................. 3-9
3-8 FLOATING POINT UNIT BLOCK DIAGRAM .............. 3-10
3-9 MUL/DIV BLOCK DIAGRAM ................... 3-11
3-10 MMDBASIC FUNCTIONAL DIAGRAM................. 3-14
3-11 CP80 COMPUTERINTERFACE ................... 3-17
3-12 TERMINATORFEEDTHROUGH .................... 3-18
3-13 CP80 SINGLE COMPUTERDATA BUS ................ 3-19
3-14 CP80 DUAL COMPUTERBLOCK DIAGRAM............... 3-24
3-15 DUAL CP80 TAPE, DISK, AND PRINTER MUXING........... 3-25
3-16 LPT MUX BOARDBLOCK DIAGRAM ................. 3-28
3-17 TAPE MUX BOARD BLOCK DIAGRAM................. 3-29
3-18 CP80 DUAL COMPUTERDATA BUS ................. 3-30
4-1 NOVA3 SLOT LOCATIONS ..................... 4-3

4-2 "A" SIDE OF NOVA BACKPLANE.................. 4-8
4-3 "B" SIDE OF NOVA BACKPLANE.................. 4-9
4-4 INTERRUPT PRIORITY JUMPER INSTALLATION ............ 4-10
4-5 NOVAPOWERSUPPLY BLOCK DIAGRAM................ 4-12
4-6 NOVA 3 BACKPLANEFUSE LAYOUT................. 4-14
4-7 NOVA3 FRONTPANEL...................... 4-15
FIGURE TITLE PAGE
5-1 MINI MODULE HEAD/DISK CONFIGURATION ............. 5-1

5-2 MINI MODULEDISK ASSEMBLY.................. 5-2
5-3 MINI MODULEASSEMBLY ..................... 5-4
5-4 SWITCHESAND INDICATORS ................... 5-7
5-5 MMDDISK SLOT LOCATORDIAGRAM ................ 5-12
5-6 LOGIC CHASSIS BACKPANEL................... 5-12
5-7 DISK DRIVE POWERSUPPLY ................... 5-14
5-8 DISK DRIVE POWERSUPPLY ................... 5-15
5-9 POWERSUPPLY FUSE LOCATION.................. 5-16
5-10 DRIVE BELT REMOVALAND REPLACEMENT .............. 5-18
5-11 DRIVE MOTORLOCK SCREW .................... 5-19
5-12 ACTUATORSHIPPING LOCK.................... 5-20
5-13 SPINDLE LOCK GROUNDSPRING.................. 5-20
6-1 CP80 TAPE DRIVE UNIT ..................... 6-2

6-2 TAPE TRANSPORTBLOCK DIAGRAM................. 6-4
6-3 TAPE DRIVE FRONTPANEL.................... 6-5
6-4 TAPE DRIVE POWERSUPPLY ................... 6-7
6-5 TAPE THREADINGLAYOUT .................... 6-9
7-1 TYPICAL CP80 TERMINAL .................... 7-2

7-2 DISPLAY TERMINAL POWERSUPPLY ................ 7-5
7-3 CP80 TERMINAL BLOCK DIAGRAM ................. 7-6
7-4 SLOT SAVER II BOARDOUTLINE ................. 7-7
8-1 TALLY PRINTER OPTION.................... · 8-2

8-2 TALLY OPERATORCONTROLPANEL................. 8-3
8-3 DATAPRODUCTSPRINTER OPTION ................. 8-4
8-4 DATAPRODUCTSOPERATORCONTROLPANEL ............. 8-5
9-1 CALIBRATION FLOWCHART.................... 9-2

9-2 SECONDLEVEL CALIBRATION................... 9-3
9-3 LTX CP80 SYSTEMCALIBRATOR.................. 9-5
9-4 CALIBRATOR CONNECTIONDIAGRAM .............. 9-12
9-5 RESISTANCE MEASUREMENTDIAGRAM............ i . . . 9-16
9-6 PRIMARYPOTENTIOMETER .......... 9-18
9-7 REQUENCY
MEASUREMENT
SYSTEM
...... Z ZZliZZZlZ 919
1 0-1 AP894 ........................... 1 0-2
vi
TABLES
TAB
LE TITLE PAGE
2-1 CP80 CIRCUIT BREAKERS ................... 2-3
3-1 CP80 DEVICE CODES...................... 3-12

3-2 DATABUS PIN ASSIGNMENTS ................... 3-20
3-3 NOVA 3/AP890 INTERACTION................... 3-21
4-1 ADDRESSINGFOR INTERSIL ME128 MEMORY{0 TO 128K). ...... 4-4

4-2 ADDRESSINGFOR INTERSIL ME128 MEMORY{128 TO 256 K) ..... 4-5
4-3 ADDRESSINGFOR INTERSIL ME512 MEMORY(512K) ......... 4-6
4-4 NOVA3 FUSELIST....................... 4-13
5-1 READ DRIVE STATUSWORDBIT CHART............... 5-6

5-2 TRANSLATIONOF READ DRIVE STATUSBITS ............ 5-6
5-3 MMDSWITCHESAND INDICATORS ................. 5-8
5-4 MMDDIAGNOSTICFAULT CODES .................. 5-9
5-5 MMDFAULT/CONTROL CARD SWITCHES ............... 5-10
5-6 MMD DUAL CHANNEL STEERING CARD SWITCHES AND INDICATORS.... 5-10
5-7 MMDPOWERSUPPLYSWITCH................... 5-11
5-8 MMDDRIVE MOTORSWITCH .................... 5-12
5-9 FUSELIST .......................... 5-13
8-1 TALLY CONTROLSAND INDICATORS ................ 8-3

8-2 DATA PRODUCTSCONTROLSAND INDICATORS ............ 8-5
8-3 PRINTEROPTIONSFUSE LIST .................. 8-6
9-1 RESISTANCE MEASUREMENT

.................... 9-17
vii
Chapter I
Introduction
and
Operating Procedures
CHAPTER1
1.1 OBJECTIVE
The objective of this manual is to familiarize the user with the basic
components of the CP80 system. This basic understanding of the CP80 system is
intended to allow the user to: perform basic troubleshooting, isolate power
supply problems, replace/exchange major user-replaceable modules, identify
problems to the subassembly level and on peripherals, diagnosis and isolation of
problems related to modules included in LTX standard spares kits.
1.2 INTRODUCTION
The LTX77 Automatic Test System performs high-speed precision tests on

linear and analog/digital devices. Its speed, accuracy and reliability are due
chiefly to four characteristics of the system: powerful, high level software;
execution time-sharing; software calibration; and simplified system
troubleshooting through the extensive use of computer driven diagnostics.
Figure 1-1 illustrates the CP80 system and may be used as a guide in the
following text.
The theory behind LTX's test system is simple: computer programmed tests
are performed by test station components which force and measure voltage,
current, analog and digital signals, and timing signals. Different test
programs can be executed simultaneously on a time-sharing basis at up to four
test stations, depending on system configuration.
The CP80 computer records test data, distributes execution among test
stations, and processes instructions for controlling the hardware. The CP80 can
contain one or two Data General NOVA 3D minicomputers, a magnetic tape unit, an
80-megabyte disk drive, the LTX calibrator reference unit, and up to two array
processors. In addition to coordinating test programs, the computer allows
program writing in LTX-BASIC, program debugging, and the collection and
reduction of data. Test data can be stored on disk or magnetic tape, or output
to the system's line printer and CRT displays.
An LTX77 system may have up to eight test stations, each test station may
have I or 2 test heads. Test stations incorporate all the system's test
circuitry in three banks of modules. The computer time-shares execution among
the test stations. In this way, processing can continue at one test station
while non-processing activities continue at other test stations.
1-1
Figure 1-1 CP80 Dual Computer System
1-2
1.3 LTX77 POWER-UP PROCEDURE
1. Turn on power at the computer rack by pressing both 'STATION' and

'COMPUTER' rocker switches, located on the front of the cabinet to the 'ON'
position.
NOTE: On the CP80, the circuit breakers are behind the

right-hand door. If the CP80 'POWER ON' light does not go
on, be sure the main circuit breakers are in the 'ON'
position.
2. Check that the key switch on the right end of the NOVA 3 front panel is in
the 'ON' position (On the dual conputer CP80, make sure both keyswitches
are in the 'ON' position)
3. The 'ON-BRIGHT' switch on the front of the CRT console must be pulled ONB,
and the brightness set to an appropriate level. The switches on the back of
the CRT console must be set as follows.
Data rate: 9.6K

Parity: Half-way between odd and even
Mode: Line
4. On the newer CP80 systems the above switches have been permanently set by
LTX and it is not necessary for the user to be concerned with them.
5. The line cord on the CRT must be connected to an AC outlet (240 volts),
preferably the printer/display outlet on the side of the computer cabinet.
6. Each test station has a power switch on its front panel. Check that each
station's power switch is in the 'ON' position, and that the switch
indicators are lit.
7. Wait for the "READY" light on the front of the disk drive to light (This
can take up to 5 minutes under some circumstances). When it is lit, the
system is ready to be booted.
1-3
1.4 BOOTING THE LTX OPERATING SYSTEM
The LTX operating system is disk resident and can be loaded into the
computer memory when required by following the steps given below.
Before beginning this procedure, the computer and the disk drive must have
their power on, disk drive must be in the 'READY' mode and the LTX system
software must be resident on the disk. If the LTX operating system is not
resident on the disk, follow the appropriate software installation procedures.
1. Press down switches 0 through 15 on the front panel of the NOVA 3 {on dual
computer CP80's set switches 0 through 15 down on both the Master and Slave
computers).
2. Turn the 'Program Load' key on the front of the CP80 cabinet clockwise.
Computer Prompts Operator Responses
3. LTX OPERATING SYSTEM

DATE: (M/D/Y)? 6/23/83 [CR] (For example)
NOTE: When entering the date, either slashes or spaces may

be used between the feilds
4. TIME: {H:M:S)? 13:45:30 [CR] (For

example)
NOTE: When entering the time, Either colons or spaces

may be used between the fields. Respond using a 24-hour
clock. Seconds may be omitted.
On dual computer CP80 systems, the CRT of the slave

computer will print "LTX OPERATING SYSTEM" when the slave
computer has received the date and time from the master
computer.
5. LTX OPERATING SYSTEM XX/XX/XX

READY (No response required)
NOTE: On dual computer CP80 systems, the last message

will appear on the CRT of both the master computer and
the slave computer.
At this time the LTX operating system is loaded, and is prepared to accept
commands from the operator. The operating system commands are described in the
LTX77 Software Manual.
1-4
I .5 MANUALLY BOOTING THE LTX OPERATING SYSTEM
Occasionally, due to board swaps or damage the user may find himself having
to boot the LTX operating system using a NOVA CPU which does not have the
necessary P/L PROMs that facilitate the booting of the LTX operating system.
The following procedure is designed to allow the user to boot the LTX
operating system should such a situation occur.
1.5.1 Manually Booting a Single Processor
The following procedure will boot a single computer CP80 or the Master
computer in a Dual CP80. When booting a Dual Computer CP80 by this method the
Master computer must be booted first.
1. Elevate RESET on the NOVA 3 console.
2. Set data switches 0 thru 15 to octal 000376.
3. Elevate the MEMory EXAMine switch.
4. Set data switches 0 thru 15 to octal 601XX.
A. XX = 22 if you are booting from the tape drive.
B. XX = 27 if you are booting from the disk.
5. Elevate the MEMory DEPosit switch.
6. Set the data switches 0 thru 15 to octal 000377.
7. Press the DEPosit NEXT switch.
8. If you are booting from the disk you must:
A. Set the data switches 0 thru 15 to O.
B. Set the register select rotary switch to ACO.
C. Elevate the REGister DEPosit switch.
10. Elevate RESET.
11. Elevate START.
12. You then must enter the M/D/Y and H:M:S. The CRT will then display an
"R" prompt. At this point type @LTXSTART@ [CR] and answer the date
and time again. You should now see the "READY" prompt.
1-5
1.5.2 Manually Booting the Slave computer
NOTE: The Master computer must already be booted.
1. Elevate RESET on the NOVA console.
3. ELevate the MEMory EXAMine switch.
4. Set the data switches 0 thru 15 to octal 60127
5. Elevate the MEMory DEPosit switch.
7. Press the DEPosit NEXT switch.
8. Because you are booting from the disk:
A. Set the data switches 0 thru 15 to O.
B, Set the register select rotary switch to ACO.
C. Elevate the REGister DEPosit switch.
9. Set the data switches 0 thru 15 to 000376.
10. Set the register select rotary switch to P.C.
11. Elevate the REGister DEPosit switch.
12. Elevate RESET.
14. Press CONTinue.
15. The CRT will display "FILENAME ?" your response: JSYS [CR]
16. You then must enter the M/D/Y and H:M:S. The CRT will then display the
"R" prompt. At this point type @LTXSTART@ [CR] and the answer the
date and time again. You should now see the "READY" prompt.
1-6
B A
PROMA, U178 = 874 0085
PROMB, U179 = 874 0086
Figure 1-2. NOVA 3 CPU Board Outline
1-7
1.6 LTX77 POWERDOWNPROCEDURE
NOTE: The power down procedure will cause all programs being
executed at the test heads to be terminated no matter what
test sequence the system is in.
1. Push [CLEAR HEADS] (or [CTRL]K) on the keyboard.
2. Type "RELEASE DISK" on the keyboard. On dual computer CP80 systems, type
"RELEASE DISK" on a CRT for the master computer and a CRT for the Slave
computer. The CRTs will display "MASTER DEVICE RELEASED".
3. If a tape is loaded on the magnetic tape drive, press 'RESET', then

'UNLOAD', then 'OFF'
4. If the Data General line printer is on line, press the 'ON/OFF LINE' button
then the 'POWER ON' circuit breaker off.
6. If a Tally printer is on line, just press the AC power rocker switch to the
'OFF' position.
NOTE: If the TALLY printer is not OFF LINE at the time the
computer power is shut off, it will spew paper continuously
until it is powered down.
7. Press both 'STATION' and 'COMPUTER' rocker switches located on the computer
cabinet to 'OFF'
8. Turn the key switch on the NOVA 3 front panel to 'OFF', then press the
'STATION' rocker switch on the computer cabinet to 'OFF'.
1-8
1.7 LTX SYSTEM SOFTWARE INSTALLATION PROCEDURE (TAPE TO DISK)

FOR THE SINGLE COMPUTER CP80 WITH AN 80-MEGABYTE CDC DISK
This procedure clears the disk and loads it with the LTX system software
from tape. The 80-Megabyte disk does not need to be reformatted before a
routine installation of the LTX system software. If the software installation
is being done to recover from a fatal system error, the disk must be formatted
and initialized before implementing this procedure. Instructions for the
formatting and initializing of the disk are given in Chapter 5.
Caution
This procedure will destroy all files saved on the disk. It

is therefore imperative that all files which are not already
saved on tape be dumped to tape prior to following this
procedure. This includes the calibrator data file. Refer to
Chapter 5 for the procedure on how to build a system backup
tape.
1. Mount the LTX operating system tape onto the tape drive. If the tape has
already been mounted as part of a previous procedure, be sure that the tape
tape has been rewound to the beginning (the BOT light on the tape drive must
be lit)
2. Sat all switches on the NOVA 3 front panel to 0 (down).
3. Set the NOVA 3 switch 15 to I (up).
4. Turn the 'Program Load' key on the front of the CP80 cabinet clockwise.
NOTE: The operator now commences a dialogue with the system

via the CRT terminal. [CR] refers to the 'Carriage Return'
key.
5. FROM
MTO: 2 [CR]
6. FULL (F) OR PARTIAL (P OR CR)? F [CR]
7. INITIALIZING WHATDISK? DZO [CR]
8. DATE (M/D/Y)? Three 2-digit groups [CR]
9. TIME (H:M:S)? Three 2-digit groups

using 24-hour clock [CR]
10. R @LOADLTXSO0 [CR]
1-9
11. LOAD THE CALIBRATOR DATA FILE

AFTER COMPLETING THIS PROCEDURE
AND CALIBRATE ALL ACTIVE HEADS
STRIKE ANY KEY TO CONTINUE [CR]
12. MASTERDEVICE RELEASED Three 2-digit groups [CR]

LTX OPERATING SYSTEM
DATE (M/D/Y)?
13. TIME (H:M:S): Three 2-digit groups

15. Load the calibrator data file.
16. Run the LTX system checkers.
I .8 LTX SYSTEM SOFTWARE INSTALLATION PROCEDURE {TAPE TO DISK)

FOR THE DUAL COMPUTER CP80 WITH AN 80-MEGABYTE CDC DISK
This procedure clears the disk and loads it with the LTX system software
from tape. The 80-Megabyte disk does not need to be reformatted before a
routine installation of the LTX system software. If the software installation
is being done to recover from a fatal system error, the disk must be formatted
and initialized before implementing this procedure. Instructions for the
formatting and initializing of the disk are given in Chapter 5.
Caution

Chapter 5 for the procedure on how to build a system backup
tape.
1. Turn off the slave computer power switch.
2. Mount the LTX operating system tape onto the tape drive. If the tape has
already been mounted as part of a previous procedure, be sure that the tape
has been rewound to the beginning (the BOT light on the tape drive must be
lit).
3. Set all switches on both NOVA 3 front panels to 0 (down).
4. Set the master computer's switch 15 to I (up).
5. Turn the 'PROGRAM LOAD' key on the front of the CP80 cabinet clockwise.
I -10
NOTE: The operator now commences a dialogue with the system

via the CRT terminal, [CR] refers to the 'Carriage Return'
key.
6. FROM
MTO: 2 [CR]
7, FULL {F) OR PARTIAL {P OR CR)? F [CR]
8. INITIALIZING WHATDISK? DZO[CR]
9. DATE (M/D/Y)? Three 2-digit groups [CR]
10 TIME (H:M:S)? Three 2-digit groups

11, R QLOADLTX8ODO[ CR]
12. CLEAR SWITCHES ON BOTH COMPUTERS

AND REBOOT WITH KEY SWITCH THEN
LOAD THE CALIBRATOR DATA FILE TO
BOTH DZO AND SLAVE AND CALIBRATE
ALL ACTIVEHEADS. (No response required)
13. Turn on the slave computer power switch,
14. Set all switches on both computers to O.
15. Turn the 'Program Load' key on

the CP80 cabinet clockwise.

DATE {M/D/Y)? Three 2-digit groups [CR]
17. TIME (H:M:S): Three 2-digit groups


19. Load the calibrator data file.
20. Run the LTX system checkers and

calibration programs.
I -11
Chapter 2
AC Distribution
CHAPTER E
CP80 AC DISTRIBUTION
2.1 INTRODUCTION
Presented on the following pages ts the user supplied AC power and its
distribution through out the CP80 system. As shown in Figure 2-2, in CP80 based
systems each test atatton plugs individually into a EO0 to 240VAC power outlet.
Dtrect line supply ts made necessary because of the 30 Amp input which must be
properly distributed throughout the sy8tem.
The 120 VAC power line (Statton Zntarlook), which the CPSO steps down
from the line power inlet, is daisy ohatned from the CPSO cabinet to all the
test stations in the system. This line ia used to oontrol a relay to gate the
line power through to each station. Figure E-1 is a simplified block diagram of
the AC power distribution through the CP80.
CB2
_
· 15A
CB1
24VACI ' '

COILS m_
Figure 2-1. CPO0 AC Power Distribution Diagram
E-1
DISPLAY PRINTER
OR OR
PRINTER PRINTER
OUTLET OUTLET
208VAC NN_ 208VAC

I DISPLAY CP80 DISPLAY
120V OUT TO 120V OUT TO
STATION STATION
INTERNAL
208 ll) O
AC POWER INLET 208l0
CONTROL 30AOUTLET
FRONT i
I 1L_I 20A
OUTLET
ill, _'s_. _q_ll
FRONT
I _'_'
'" F1
208 lib 208 1(_
20AOUTLET 20AOUTLET
Figure E-2, CPSO/TS80AC Distribution
2-2
2.2 CP80 POWER DISTRIBUTION
The 208V 30A incoming power is supplied to the CP80 through a 250V/30A male
twist mount connector located on the right bulkhead of the CP80 (Figure 2-5).
The cabling and wall connection for this outlet are customer supplied.
The incoming power runs directly from the bulkhead connector to the
Transformer Box located on the bottom left side of the CP80 cabinet. The
Transformer Box then outputs both 240V and 120V to the AC Distribution Box.
All devices in the CP80 are connected to one central source known as the AC
Distribution Box (Figure 2-3). The AC Distribution Box is located just above the
Calibrator, at the bottom left side of the CP80.
The 24V for the front panel LEDs and the Station and Computer relays is
derived from stepdown transformers located in the CP80 Transformer Box.
There are five circuit breakers on the front of the AC Distribution Box
(Figure 2-3). Each circuit breaker is associated with a particular connector or
group of connectors. Table 2-1 details which connectors are associated with
which circuit breakers. This may be used in conjunction with the AC power
distribution diagram in Figure 2-1 for troubleshooting purposes.
Power from the AC Distribution Box branches out to all devices housed in
the CP80. The following sections describe each device individually and trace its
AC distribution from the AC Distribution Box.
TABLE 2-1. CP80 CIRCUIT BREAKERS
BREAKER(S) CONNECTOR(S) FUNCTION
CB1 P3, P4, P5, P6 TAPE240V, BULKHEAD 240V,

ARRAY PROC. 240V, FANS 240V
CB2 P7, P8, P9 DISK 240V, COMPUTER

240V,
PX81 240V
CB3 P2, PlO TRANSFORMER BOX120V,

BULKHEAD 120V
CB4 P11 CALIBRATOR

240V
CB5 P12 FRONT

PANEL
24V
2-3
CO
TAPE ARRAYPROC. DISK PX81 CALIB.
o_ 240V 240V 240V 240V 240V
TRANSFORMER
BOX 240V
BULKHEAD FANS COMPUTER BULKHEAD

TRANSFORMER 240V 240V 240V 120V FRONT
P Pl
P2 (_ P12
SIDE VIEW
CB5
CB4 CB3 CB2 CB1
FRONT VIEW
Figure 2-3. AC Distribution Box
2-4
2.2.1CP80 Front Panel
The CP80 front panel connector, P1, is supplied with 24VAC from the P12
connector on the AC Distribution Box. The 24VAC is used to energize the computer
relays and the station relay when S1 and S2 are depressed.
S1 is known as the computer power switch. When depressed, S1 causes the K2

and K3 relays to close, which connects P3 through P9 and P12 to the P1 connector
on the AC Distribution Box. The P1 connector carries 240VAC directly from the
Transformer Box. When energized, connectors P3 through P9 and P12 supply AC
power to: tape drive, bulkhead 240V array processor, fans, disk, computer,
PX81(if present), and the front panel respectively.
When the station or S2 switch is depressed K1 closes. When K1 closes, the

120VAC from the Transformer Box on P2 of the AC Distribution Box is gated on to
PlO of the AC Distribution Box. PlO supplies the Station 120VAC (Station
Interlock) to the left and right bulkheads.
NOTE: The Pll Calibrator AC connection is discussed in the

Calibrator section of this chapter.
P1 ? s2
m
N 24VAC I J Sl P2
COMPUTER
RELAY - - ] D.C.FAULT
STATION
RELAY PROG. LOAD
DIC GND.
STATION PWR LED

CALIB.
ON LED DIG.GND.
D.C.FAULT
LED In CPU1
SUPPLY ,r_,N
® PROG.LOAD
WHITE D.C. FAULT
Figure 2-4. CP80 Front Panel Schematic
2-5
CPSO AC DISTRIBUTION
2.2.2 Calibrator
The Calibrator power cable is connected directly to the Pll connector of

the AC Distribution Box. As can be seen in the AC power distribution diagram
(Figure 2-1), the AC power for Pll is picked off of the P1 connector before the
K2 and K3 relays. This allows power to be maintained to the Calibrator even when
the computer power switch is turned off. As long as the Calibrator power cord is
connected to the AC Distribution Box (Pll) and the CP80 input power is
maintained, the Calibrator will be on.
A stepdown transformer is connected to Pll and outputs a constant 24V to

P12 pin 7. From here the 24V is taken to P1 pin 7 on the CP80 front panel. This
24V illuminates an LED on the CP80 front panel called CALIBRATOR ON. This LED
displays the on/off status of the Calibrator unit.
2.3 BULKHEAD CONNECTIONS
With the exception of the 208V power wired directly into each test station,
all CP80 peripherals receive their AC power from the left and right hand side
bulkheads on the CP80. The left and right bulkheads receive their AC power
directly from the CPSO AC Distribution Box. The P4 connector of the AC
Distribution Box supplies bulkhead 120V, and the PlO connector supplies the
240V. Figure 2-5 illustrates the physical layout of the CP80 left and right
bulkheads. As discussed earlier, customer supplied incoming power is supplied to
the right bulkhead via the Input Power connector.
2-6
6
_1 DISPLAY
1
,11 DISPLAY
2
II II I CAL
I
D © © 0
_=_0,0
_,_
LINE 0 LINE 1 LINE 2

U
Lille3
RIGHT
I I I I
I CAL II I! II
DISPLAY
2
IIDISPLAY
1
I
_=_o_©
120V DISPLAY PRINTER240V
© PR R
LINE 3 LINE 2 LINE 1 LINE 0
LEFT
Figure 2-5. CP80 Left and Right Bulkheads
2-7
Chapter 3
Theory of Operation
CHAPTER 3
THEORYOF OPERATION
3.1 INTRODUCTION
The CPSO ia the Central Processor for the LTX77 system, The CPSO can
contain one or two Data General NOVA 3 minicomputers, a magnetic tape unit, an
80 megabyte disk drive, an LTX Calibrator reference unit, up to four CRT
terminals, a line printer and an optional Array Processor[s). In addition to
coordinating test programs, the computer allows programs to be written in
LTX-BASIC, program debugging, and the collection and reduction of date. Test
data can be stored on disk or magnetic tape, or output to the systemic line
printer or CRT displays.
The CPSO can support up to four teat stations. Each test station in turn
can support one or two test heads. The CP80 time-shares program execution
between test stations. In this way, processing can continue at one test station
while non-processing activities, such aa WAITs, can continue at other test
stations.
Th ·CPSO is contained in its own cabinet. To communicate with the test

stations in the system, a high speed data bus is used.
Figure 3-1 shows a CPSO Dual Computer configuration.
I I
NAGTAPE FRONTPANEL
ARRAYPROCESSOR
#l SLAVECOMPUTER
ARRAYPROCESSOR
#2
PX81
CDC 80 MB DISK
MASTER COMPUTER
_ AC DISTRIBUTION
BOX
TRANSORMER CALIBRATOR
BOX
FRONT
Figure 3-1· CPBD Rack Diagram (Dual Processor Configuration)
3-1
THEORY OF OPERATION
3.2 SINGLE COMPUTER CP80
There are two types of CP80 configurations available on the LTX77 system:
the single computer CP80 and the PX81 dual computer CP80. The dual computer CP80
will be discussed later on in this manual. Figure 3-2 is a block diagram of the
CP80 single computer
) ,_ ,_ RS232(4)
_ _ II
rT'-T-T-T_
PROCESSOR _ PROCESSOR -It
NOVA3 MEMORY
ARRAY ARRAY I i__
CONTROL
[] CONTROL
DISK0 ___ DISK CONSOLE I /
I I
MAG TAPE
_ s_,JITC,ES)
CONTROL
_F
0 I F.P.U.
1
F-1
0
MAG TAPE
Figure 3-2. CP80 Single Computer Block Diagram
3-2
THEORYOF 0PERATION
3.3 THE NOVA 3
The standard CPB0 computer ts · Data General NOVA 3. The NOVA 3 can be
configured wtth up to 512K of memory. LTX recommends no less than 128K, as some
of the checker end calibration programs require 128K memory aa a minimum. To
enhance operating speed end efficiency, the hardware for multiplication/division
end floating point era resident In the computer mainframe. Also resident in the
computer mainframe is a memory management unit (MHU). The HHU is responsible for
managing the LTX operating syetm end tts overlays as well as the Real Time Dtsk
Operating Systm (RDOS). The internal bussing structure which allows the CPU to
communicate with the above mentioned devices ts detailed tn Figure 3-4.
3.3.1 The NOVA 3 CPU
The CPU directs the operation of the elements in the computer syetm. Zt
selects the operations Performed and coordinates those operations. The CPU
transfers data to and from memory and peripherals end performs arithmetic and
logical operations. There are two general types or logic tn the CPU: Data
Manipulation Logic end Control Logic.
Figure 3-3 illustrates the NOVA 3 CPU end the electrical connections
between the control logic end the data manipulation logic.
JcPu 1
_1_ JCONTROL
: } iiii::i?:iiii!?;}:':!
i:[:'SvS TEM i ii:EL£MENi-:S_
:'!ii??Si:'iii "........
·' '"" :::::::::::::::::::::ALU
':': CONTROL
........
::': "::::::: ' ' :: :::: ::::: :':_1_
::::: :::: :_: ¥: ii:iii ::¥. i! i: ii :::i'liiSi:iSii_ALU
J ¢O-15_.
SYSTEM ELEMENTS ...........

ICONTROL TO SH.tERCONTROL _ DATA .:_._':: :i:?i:i:i:!:?
:i:!:
:JDATA<O-,5>
MUX CONTROL
._ i.i!!.:!, iii. i!!.:ii.i!i.!.ii.!!i.i i! CONTROL ................. :::: ....... .... .1_ MANIPULATIOI _ IVlADR
< 1-, 5>
LOGIC ,;" LOGIC I
(CL) · DRIVER CONTROL .1_=:3
:::::::::::::::::::::::::::::::::::
:: ::;::::!::.:::::::::::::::::::::..::::::.:::::::.:
...,,..(DML) _ MEM<0-15>
CARRY CONTROL - J
I
IR<8-*t 5._
I
MAR CONTROL J
CPU OML STATUS I
MEM<O. 15, I
:::::::::::::::::::::::::::::::::::::::
::;::;;'::;:,:::;' .; :;:.: ::;:'::.;:::;::':: ;;:: :;:' ::':::::;:: :; ::::::::::::::::::::::::::::::::::: .!!!:! ::!:!:i:!:i;:::'; I
I
_.J
Figure 3-3. Data Manipulation and Control Logic Znterconneotions
3-3
THEORY OF OPERATION
ob
_ o_
, I · , I !
z C
L
o
Z
1 2448
3-4
THEORY OF OPERATION
3.3.2 CPU Data Manipulation Logic
Data manipulation logic is the circuitry that performs operations on data.

It is composed of operational components and data paths. Operational components
consist of logic and registers. Data paths are electrical connections that
carry information among operational components within the data manipulation
logic and carry information into and out of the data manipulation logic.
The operational components of the data manipulation logic in the NOVA 3 CPU
are a register file (RF), an arithmetic/logic unit (ALU), a shifter, carry
logic, a 3:1 multiplexor, drivers and a memory address register (MAR).
The register file contains eight 16-bit registers that share a common
clock. The registers serve as four accumulators (ACO, AC1, AC2, AC3), a program
counter (PC), a stack pointer (SP), a frame pointer (FP), and an internal
working register (TEMP).
The ALU performs arithmetic and logical operations on a 16-bit 'A' input
and a 16-bit 'B' input to produce a 16-bit output and a 1-bit carry output.
The shifter performs shift operations on the ALU output 'ALU(O-15)' and a
shifter carry-in (SCI) to produce a 16-bit output 'SUM(O-15)' and a shifter
carry-out.
The carry logic manipulates the value of the carry input to the shifter
during the execution of an ALC instruction.
The 3:1 multiplexor places the contents of one of three inputs onto a
16-bit output when the proper control signals are asserted.
The drivers in the block diagram of the NOVA 3 CPU data manipulation logic
are AND gates with open collector transistor outputs that drive the 'MEM(O-15)',
'DATA(O-15)' and 'MADR(O-15)' lines by sinking current.
The memory address register holds the memory address that is currently
being driven onto 'MADR(O-15)'.
Figure 3-5 details the above discussion in block diagram form.
3-5
THEORY OF OPERATION
Ii'
<]>:
T
{,3
LU _ _t
om_0_ _1 f
(.Orr u3
I 5
_u _ .,-
_____5 c f_
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t-
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-- rq
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ea
CO
-_2 __ '
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II
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F
12449
3-6
THEORY OF OPERATION
3.3.3 CPU Control Logic
The control logic directs the data manipulation logic and system elements
(console, memory, MMU, mul/div, and peripherals) and coordinates their
operation. The control logic directs the data manipulation logic by selecting
the functions performed by the system logic and by loading registers at the
proper times. It directs system elements by asserting memory bus signals, I/O
bus signals, and control signals.
The CPU control logic is organized as shown in Figure 3-6. The box
labelled 'state flip-flops' represents flip-flops and registers whose outputs
can change only when clocked by the timing signal CPUCLK. State flip-flops
receive input from the combinatorial logic fed by the CPU data manipulation
logic and the feedback from combinatorial logic and ROMs fed by the outputs of
the state flip-flops.
During the time interval between one rising edge of CPUCLK and the next,
when the state flip-flops are asserting a unique set of outputs, a 'major state'
is said to exist. These outputs are used by the combinatorial logic and ROMs to
produce the control signals which control the CPU data manipulation logic and
the system elements during the current major state and the feedback to the state
flip-flops which affect the selection of the next major state.
CONTROLSIGNALS
·1_ TOCPU
DATA MANIPUL
ATIONLOGIC
(:D
CPLJ CLK
FROM CPlJ
DATA MANIPULA _ION LOGIC
Figure 3-6. CPU Control Logic
3-7
THEORY OF OPERATION
3.3.4 Data Channel Breaks
The NOVA 3 CPU is equipped with data channel facility for block transfers
of data between memory and data channel devices such as disk drive.
If the CPU receives a data channel request during the current major state,
the next two major states that are executed will be DCH major states, during
which a data channel transfer will occur, provided that a console function which
has not been pressed [other than STOP), a READ-MODIFY-WRITE cycle is not being
performed, a data channel transfer is not currently in progress, interrupt
requests are enabled (IRQENB=L).
3.3.5 Memory Management Unit
When the CPU accesses memory, it specifies the location to be accessed with
a 15-bit address. With this 15-bit address, the CPU may access 32,768 (32K)
distinct memory locations from 0 to 77777(octal). This 15-bit address is called
a logical address space.
The memory management unit option (MMU), shown in Figure 3-7, is an

extension of the CPU that translates every logical address to an 19-bit physical
address with no change in memory access time. With this 19-bit address, a CPU
with an MMU may access 512K distinct memory locations from 0 to 777777(octal).
This 19-bit address is called a physical address and the set of all such
addresses is called the physical address space.
The MMU performs this logical-to-physical address translation by replacing

the high order five bits of a logical address with the high order eight bits of
the corresponding physical address. The Iow order ten bits of a logical address
and its corresponding physical address are identical. This logical-to-physical
address translation expands the total address span available to the CPU even
though the CPU can access only a 32K memory range at a given time. The address
translation is performed such that for every logical address there is one and
only one physical address.
3.3.6 Floating Point Units I and 2
Floating point units I and 2 provide the NOVA with the capability of
manipulating decimal or non-integer numbers. FPU I and 2 accomplish this by
converting the standard NOVA 16 bit word into a 64 bit word. This "double
precision" word contains the sign bit (bit 1) the exponent (the next seven bits)
and the mantissa (the next 24 bits). Figure 3-8 is a block diagram of the FPU 1
and 2.
3.3.7 Multiply/Divide Unit
The Multiply/Divide unit (Mul/Div) is a circuit which provides hardware

implementation of multiply divide instructions. The Mul/Div unit contains data
manipulation logic and control logic which are extensions of the data
manipulation and control logic on the CPU. By controlling multiplication and
division via hardware rather than by software, processing speed is increased by
an order of magnitude. Figure 3-9 details the mul/div unit in block diagram
form.
3-8
THEORY OF OPERATION
_O READ
WRITe MAPSELECTION
___ SELECTION
(SEE fEXTI INPUTS'
(SEE TEXT) BCLOCK t3MAt_N
TION -']'"i TAR, : 8 ' OUTPUT I .
DA_TA 8 15 _" _1 IMAPEN
FDATOA DEV3SEL
DATA< 0 15 >
ENTRY FDATIA DEV2SEt
REGISTER DDRIVE
ALU · 06 '
f j_ 989 2C
MAP
DEFER
FDATOA (FROMCPU) DATA_ 0 t5
MMU
O_ V2SEI (FROM CPUl
I J 8MEMEN MUX
DATAO DATA1 DATAI© DATA15 MMU

: STATUS
LOGIC
IDM-'_ P_
989 1D4 IMAmNH
· { ii::?ZZ:
:Z:Z:
ZZ : Z ¸¸i̧
'MAP SELECTION INPUTS INCLUDE
FPDCH
ALUO SSEMAPB IFROM FPU) _ r- _ MMU TIMING
DADREB DEV2SEL / DATIB --I_ ISEE INTERRUPT
/
SSEADREN DEV3SEL IOPLS -4_
DATIA --_ TEXT) 'Il' ENABLE DISABLE
ALU6 PMAPB FROM I'O _ DATOA--I_ t -e_ SIGNALS

FPU DETECTION
BUS --1
(SEE DGC 015 0OO031)1 DATOB --_ READ WRITE
CLR _ _,- SELECTION
L DCHA _
DS---_--_')--a-
MMU
CONTROL
LOGIC
_
(SEE TEXT)
MAP SELECTION
SIGNALS'
FROM DEFERq _-_ ODRIVE

CPU DP2-_ 1 t_- DEV2SEL
MAREN-_- 1 _- DEV3SEL
CLOCK-,.
1 i_.M'---_
f 2cPuc_,_-,.
_.c_
_,,.1I I.,.-MA,_N
I-_,c_ocK
Figure 3-7. MMU Functional Block Diagram
3-9
THEORYOF OPEFIATION
O_SII
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J
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i C_
^ m
I
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u
Q2
*em,
e.
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H_ __il
li:i:lmvu,_, w _ I
:::: u - i-. x
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3- 10
THEORY OF OPERATION
8I_II
"::]:' Z:
:]i
z
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°8
_r
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3-11
THEORY OF OPERATION
When the NOVA addresses a device such as the mag tape or disk it does so
by number and not by name. Therefore each device in the CP80 system has its own
Device Code. Table 3-I lists the CP80 devices and their respective codes.
TABLE 3-I. CP80 DEVICE CODES
DEVICE CODE
MULTIPLY/DIVIDE UNIT (IN THE NOVA) I
MEMORY MANAGEMENT UNIT (IN THE NOVA) 2 AND 3
FLOATING POINT UNIT (IN THE NOVA) 76
MAG
TAPE
UNIT 22
KEYBOARD
(PRIMARY) 10
KEYBOARD
(SECONDARY) 50
DISPLAY
(PRIMARY) 11
DISPLAY
(SECONDARY) 51
LINEPRINTER 17
80 MEGA-BYTE
DISK 27
REAL
TIMECLOCK 14
RS232 30
LTXINTERFACE 25
ARRAY
PROCESSOR 53
3-12
THEORY OF OPERATION
3.4 DISK STORAGE
The CP80 contains 80 megabytes of fixed disk storage. After the required
formatting, approximately 67 megabytes of storage are available for use. Backup
copies of all programs can be saved on magnetic tape.
3.4.1 Single Computer Disk Structure
The single computer CP80 uses a two directory structure on its associated
disk drive. The main or system directory is known as DZO and houses all files
associated with software i.e. the LTX operating system, test programs etc. The
second directory is a sub-directory of DZO and is called DATA. The DATA
directory contains data files i.e. calibration data for test heads, and DLOG
files.
3.4.2 Disk Controller Board
A Spectrologic (LT× P/N 874-0306) or Custom Systems (LTX P/N 874-0305)

Xylogic controller is used as the interface between the NOVA computer and the
disk drive. The disk controller board is located in slot 8 of the NOVA computer.
In dual computer systems, each computer has its own disk controller board. To
function properly dual computer must use the same type of disk processor board.
The drive can communicate only with the controller. The interface board is
connected to the disk drive by two flat ribbon cables for a single channel unit
and by four flat ribbon cables for a dual channel unit. The controller issues
all commands to the drive. Tag bus signals define the basic type of operation
to be performed (Tag I is used as the cylinder address enable, Tag 2 is used as
the head address enable). Device bus out signals further modify or define basic
commands selected by the tag bus signals. In addition to the commands, the
controller sends write data, write clock, and power sequence information to the
drive. The drive sends various status signals to the controller via the device
bus in lines.
3 -13
THEORYOF OPERATION
3.4.3 Seeking
The drive must position the selected head over the desired location (es
commanded by the controller) on the disk surface before it writes or reads date.
This function is cai led seeking, end it is performed by a heed positioning
mechanism (actuator) under the direction of a microprocessor-control led device
eervo system.
3.4.4 Reading and Writing
The drive is capable of both writing data on and reading data from the disk
date surfaces. During · write operation, the drive receives date from the
controller, processes it, and writes it on the disk. During a read operation,
the drive recovers data from the disk, processes it, end transmits it to the
control ler.
The major functional areas of the drive are shown in Figure 3-10.
C_ r DRIVE
"' I I SEEK I
r,,, _j (MPU I
_] CON- I
COMMANDS _ / TROL) J
WRITE DATA AND CLOCK
POWER SEQUENCE
CONTROLLER
STATUS SIGNALS
t RD DATA AND CLOCK [_ WRITE

AND _/ HEi DS
SUPPLY I
Figure 3-10. HHD Basic Functional Diagram
3-14
THEORY OF OPERATION
3.5 THE TAPE DRIVE
The CPSO magnetic tape drive is a Data General 6020 Tape Transport. The
tape drive can accommodate all standard size tape reels, from 600 to 2400 feet.
The drive reads and writes at a speed of 75 inches per second and rewinds at a
speed of 200 inches per second. The 6020 tape transport uses a 9 track, NRZI,
800 bytes per inch format.
Magnetic tape fi_es are created by the LTX system by file number. The first
file on the tape is referred to as file zero and each subsequent file on the
tape will have an incremental file number.
3.6 THE LTX CALIBRATION UNIT
The LTX Calibrator is a transportable, temperature stabilized calibration

standard containing frequency, resistance and DC voltage calibration standards.
The Calibrator must be calibrated every six months. The standards used in the
calibration of the LTX Calibrator must be traceable to the National Bureau of
Standards. For convenience of our customers, several LTX facilities around the
United States are able to perform the calibration function.
The calibrator houses a series of 20 resistors in their own temperature

controlled environment. These resistors range in values from 20 ohms to
10,485,760 ohms in precise steps of two. When a resistance standard is needed,
the proper resistance value is built by connecting the needed resistors together
in series. In this way the LT× calibrator is able to compose any resistance
standard the system may call for.
The series resistors also play a part in building a reference voltage. When
a reference voltage is being built the resistor string acts as a voltage
divider. There are 2 initial voltages which may be selected by the system, IOOV
or 12.5V. Once the initial voltage has been selected then the proper resistor or
series of resistors is selected to divide the initial voltage down until the
needs of the system are met.
The LTX frequency standard is also generated from the calibrator unit.
Housed in its own oven inside the calibrator unit, the frequency standard
outputs the desired frequency via pin 36 of the LTX Data Bus. To obtain a
desired frequency a IOMHZ signal is fed into a divider which is capable of
dividing the IOMHZ signal downward in precise steps of two.
3-15
THEORY OF OPERATION
3.7 CP80 INTERFACE
The CP80 interface board is located in slot 9 of the NOVA mainframe. The
LTX system Data Bus originates from the CP80 Interface. All program commands
from the NOVA are loaded onto the Interface and are translated into system
signals. In turn all interrupts from the system are translated by the interface
into signals that can be recognized by the NOVA.
Besides interfacing the system to the NOVA, the CP80 interface performs
three other functions. There are three circuits resident on the CP80 Interface
board: Magnetic Tape Request, bootstrap circuit, and a power supply monitor
circuit.
The magnetic tape request circuit is the interface between the the dual
computers and the magnetic tape unit. This circuit is responsible for
maintaining orderly access to the single magnetic tape unit by the two resident
computers.
The bootstrap circuit is used to "boot" the system up by turning the

Program Load switch located on the front panel of the CP80. In the "master"
computer the bootstrap circuit simulates the sequential operation of the NOVA
front panel switches: RESET, PROGRAM LOAD. In the "slave" computer switch 2 of
the NOVA must be elevated for it to be "booted" up.
The power supply monitor circuit detects improper voltage due to supply
failure or fuse burnout. Voltages not available directly at slot 9 are
transmitted there by resistors wirewrapped into the computer backplane to the
CP80 interface. The supply monitor in either computer of a CP80 can illuminate
the front panel DC power fault LED, even if power to that computer is off.
Power off is equivalent to a DC fault.
Consult Figure 3-11 for a board outline of the CP80 Computer Interface.
3.7.1 CP80 Burst Interface Option
In systems requiring high speed data transmission, a special Burst

Interface option may be utilized in place of the standard CP80 Interface board.
The CP80 Burst Interface board incorporates all of the features of the standard
CP80 Interface board, with the added ability to transmit data at a much faster
rate than the standard interface.
3 -16
THEORY OF OPERATION
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3-17
THEORY OF OPERATION
3.8 CP80 DATA BUS
Inorder to send I MHZ data along the LTX Data Bus, a special ribbon cable
scheme is used. The Data Bus, which originates on the CP80 interface board, is
driven by open collector drivers in the NOVA. Each data line of the bus is
surrounded by an active (3V) and a passive (ground) line. The power supply for
the 3V is also located on the CP80 Interface Board. A 110 ohm characteristic
impedance is created by terminating the ends of the Data Bus with 110 ohm pull
up resistors which connect the data and the 3V lines. In turn the ground lines
are all connected together.
In the CP80 cabinet, bolted to the left and right hand side, are
feedthrough connectors (Figure 3-12) for the Data bus. As the name implies,
these connectors feed the Data Bus out to the test station. As stated earlier in
this section the LTX Interface card sits in the middle of the Data Bus and
channels the Data Bus out to the left and right side of the CP80. At the feed-
through connector, the Data Bus must either be fed through to a test station or
terminated with a 110 ohm terminator connector. If the Data Bus is not connected
to a test station or a terminator, the bus will be left floating and data on the
bus will not be valid.
From the CPSO feedthrough connector the data bus connects to the the feed
through connector of the test station. The feedthrough connector feeds the Data
Bus into the Station Controller of the Test Station. It is the job of the
Station Controller to decode station, module, and head addresses to determine if
this is the station being addressed, and if so, which module and/or head is
being addressed.
Figure 3-13 shows the CP80 single computer data bus in block diagram form.
Consult Table 3-2 for a pin out of the Data Bus cable.
50 PIN CONNECTOR I I 50 PIN CONNECTOR
110 OHM TERMINATING I

RESISTORS
I
F
I 50 PIN CONNECTOR
THIS CONNECTOR FAR SIDE
Figure 3-12. Terminator FeedThrough
3-18
THEORY OF OPERATION
CP80
PIN 36 CALIBRATOR
REFERENCE FREQUENCY
p41_ GROUND
SIDE SIDE
LEFT [ RIGHT
· COMPUTER
MASTER _-
CALIBRATOR
m m I m m m m m mm IIm m m mm m m i
F-" TS80 i i F I TS80 i ]
I I
CON- CON-
TROLLER TROLLER
k ..... L .... I
Figure 3-13. CP8O Single Computer Data Bus
3-19
THEORY OF OPERATION
TABLE 3-2
DATA BUS PIN ASSIGNMENTS
I cou.D 2 /', _
3 GROUND 4 DX
5 GROUND 6 D2
7' GROUND 8 D3
9 GROUND I0 D4
]! GROUND ]_ D--_
13 3v 14 ii_
15 3V 16 D?
17 3v 18 D-'8' _ ,&_
19 3v f
20 De
21 3v 22 Ol0
23 3V 24' Dll
27 3v 28 DJ2
29 3V 30
31 3v i ii i 32 D14
33 3v 34 bls _// */-_,_

35 3v 36 __ _ FREUJE_/_._/_-
37 3v 38 i
59 GROUND 40 READ
41 GROUND 42 WRITE DATA

43
....
GROUND ii
44 WRITE ADDRESS _
45 GROUND 46 POWER CLEAR
47 GROUND ,,,,, B
48 INTERRUPT
49 GROUND 50
3 - PO
THEORY OF OPERATION
3.9 SLOT SAVER II BOARD
Besides its Real Time Clock (RTC) and Terminal/Computer interface

capabilities, the Slot Saver II board carries four RS-232 interface ports.
The RS-232 ports perform asynchronous, serial intercommunication of ASCII
characters with any device which is compatibly equipped (9600 baud, no parity, 1
start bit, 2 stop bits and 8 data bits). The asynchronous controller section of
the Slot Saver II board performs all of the necessary character assembly and
disassembly for the transmission of serial bit streams to and from a user
supplied device. START and STOP bits are inserted or stripped away as needed.
Character buffering is also provided on both reception and transmission so that
the program has sufficient time to respond to each character without losing
input data or requiring the user to adjust the character transmission rate in
any way.
3.10 ARRAY PROCESSOR APB90
The LTX APB90 Array Processor is a high speed arithmetic computation unit
that can be added as an option to the CP80. It is intended for use in both CP80
single and dual computer systems. Dual computer systems may be configured with
two array processors. The AP890 peripheral adds a powerful computing capability
to the computer, enhancing the signal and data processing rates of the stand
alone computer. If only one array processor is present in a dual CP80, then only
the "master" or the "slave", will be connected to the array processor. It is
incumbent upon the programmer to know which computer is connected to the array
processor and to run the programs that require the use of the array processor on
the computer connected to the AP890.
The interaction between the NOVA and the AP890 occurs by both programmed
I/O (PIO) and Data Channel (DCH). A typical NOVA, AP890 interaction occurs as
fallows:
TABLE 3-3. NOVA/AP890 INTERACTION
TYPE OF I/O
STEP ACTION TRANSFER
I The NOVA loads the address of a Function Control Block PIO

(FCB), which resides in the NOVA memory, into a location
in the Array Processor Memory.
2 The NOVA announces its need for the Array Processor to PIO
perform a function by loading the "Perform Function"
message into the Array Processor Message Register, and
then interrupts the Array Processor.
3 The Array Processor responds to the interupt and fetches NA

the message from the Array Processor interface.
3- 21
THEORY OF OPERATION
TABLE 3-3 (cont'd)
TYPE OF I/O
STEP ACTION TRANSFER
4 The Array Processor retrieves the FCB address from the NA

Array Processor Data Memory.
5 The Array Processor accesses the FCB in the NOVA memory DCH
and transfers FCB the the Array Processor Data memory.
6 The Array Processor function specified in the FCB is NA

initiated and is executed based upon control information
stored in the FCB.
7 Any data required by the Array Processor function is DCH

retrieved by the Array Processor directly from the NOVA
memory. Likewise, any Array Processor function results to
the NOVA memory are placed there directly by the Array
Processor.
8 When the Array Processor function is completed, the Array DCH

Processor "marks" the FCB in the NOVA memory and checks
for another Array Processor function FCB chained to the
last one.
9 If another FCB is chained to the last one, the Array Pro- DCH
cessor retrieves it and the process described above
repeats itself, without an interupt from the NOVA.
10 If no further FCB is chained, the Array Processor places INTERRUPT

a "Function Done" message in to a designated register
and interrupts the NOVA.
11 When the interrupt is acknowledged, the NOVA may resume NOVA only
execution of a task that was suspended while awaiting the
Array Processor results, or it may set a flag to indicate
"Array Processor Done", which a subsequent NOVA task may
utilize as necessary.
12 Meanwhile, the Array Processor waits for another "Perform ARRAY

Function" message, and may continue to perform its ongoing PROCESSOR
operations.
3- 22
THEORY OF OPERATION
3.11 PX81 OPTION
The PX81 option includes everything (cables, software, boards, etc)

necessary to expand a single computer CP80 into a Dual computer CP80. Figure
3-15 details the interconnections between the computers and the single disk,
tape and printer units which must be shared between the dual computers.
3.12 DUAL COMPUTER CP80
As the name implies, the Dual CP80 is a CP80 with two NOVA 3 computers.
The dual computers can control up to sixteen test heads. The two computers
housed within the Dual CPSO must share the same disk drive, mag tape unit,
printer, and calibrator.
Figure 3-14 is a block diagram of a Dual CP80 unit.
3.12.1 Computer Hierachy
In a dual computer system, the computer in the lower rack of the CP80 is
known as the "Master" computer. The second or the computer in the upper position
is known as the "Slave". The "Master" computer controls test stations connected
to the right side of the CPSO and the "Slave" controls test stations connected
to the left side fo the CP80. Each computer may have up to eight test heads and
two CRTs associated with it.
3- 23
THEORYOF OPERATZON
ARRAY ARRAY
PROCESSOR PROCESSOR
CONTROL SWITCHES
CONSOLE
* l
iIPB DISK
CONTROL
- NOVA 3
C.P.U.
MEMORY
IPB I MAG TAPE
_1 CONTROL
F.P.U. II
PX81 _' ' ' ' 14

n_mh-_-r_ RS232(4)
SLOT SAVER
DISK
CONTROL
IPB
I iPB j_ L I
NOVA 3 MEr4ORY II
I-,
I
MAG TAPE
CONTROL
C.P.U.
CONSOLE
Jl
PROCESSOR PROCESSOR
CONTROL
F.P.U.
1
Figure 3-14. CP80 Duel Computer
3- 24
THEORY OF OPERATION
SLAVE MASTER Z
COMPUTER COMPUTER
I- - T - -I- -1 F I r- - l- - -I - --I
I I I I I I I I I I
ID C IT C IS S I I LPTMUX I Is S I T C I D C I
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DUALCHANNEL DRIVE TAPE
STEERING PRINTER INTER- DRIVE I
CARD FACE MUX
i
MUX POWER
NOTE' TO ALLOW TAPE DRIVE TO SWITCH CONTROL FROM ONE COMPUTER

TO THE OTHER YOU MUST TAKE TAPE DRIVE OFF LINE FOR 3 SEC. MIN.
Figure 3-15. Dual CP80 Tape, Disk, and Printer Muxing
3- 25
THEORY OF OPERATION
3.13 80 MB DISK
A single disk drive contains provisions to be shared by two computers.

Located in slot 8 of the master and slave computers is a disk controller board.
Each disk controller board is connected to its own Channel I/O card in the disk
logic chassis. The Channel I/O cards are connected to the Dual Steering card,
also located in the disk logic chassis. Since only one computer may use the disk
at any one time, the Dual steering card supervises the sharing of the disk.
3.13.1 Dual Computer Disk Structure
In a dual computer CP80 the disk space is divided into four directories.
There are two directories for each computer. The directories associated with the
"Master" computer are: DZO and DATA. As in the single processor system, DZO is
the main directory, with DATA being a sub set of this. The two directories
associated with the "Slave" computer are know as SLAVE and DATA. Like DZO,
SLAVE is the main directory with DATA being a sub-set of slave. Files may be
transferred between the DZO and SLAVE directories. Each DATA directory is
associated with a computer which is dedicated to a particular test head(s). DATA
directory files contain summary and calibration information which is specific to
a particular test head. Files from one DATA directory can not be transferred to
another without first being transferred to the source directory, then to the
destination directory, then to the destination DATA directory.
3.14 LINE PRINTER
A single line printer is shared between the two computers of a CP80 by

using an LTX-designed LPT MUX board. The LPT MUX board is plugged into the
power supply of the PX81 box located just below the slave computer. The LPT MUX
board allows the use of the printer if it determines the printer is not tied up
with some other task. Figure 3-16 is a block diagram of the LPT MUX board.
3.15 MAGNETIC TAPE UNIT
A single mag tape is shared between the two computers of a CP80 by using an
LTX-designed TAPE MUX board (Figure 3-17). The TAPE MUX board is mounted inside
the tape transport cabinet. A separate cable carries power (5 VDC) to the board
from the PX81 Box Power Supply Unit. The TAPE MUX board grants use of the
magnetic tape unit by a computer if the magnetic tape unit is not busy with the
other processor. Neither computer can successfully interrupt if the tape unit
is busy with some other task. Once a particular processor, whether it is the
master or slave, gains access to the tape unit, it maintains control of the tape
drive until the tape unit is taken off line. When the tape drive is placed back
ON LINE, each processor has an equal chance of gaining control of the tape unit.
The scheme of placing the tape drive first OFF LINE then ON LINE was devised to
help prevent the inadvertent writing of data from both processors on the same
tape.
3 - 26
THEORY OF OPERATION
3.16 CALIBRATOR UNIT
In Dual CPSO systems, only the master computer has direct access to the
Calibrator Unit. Control of the Calibrator by the slave computer is done through
the master computer via the Inter-Processor Bus. When the slave computer needs a
voltage or resistance standard, a request from the slave to the master computer
is made. In turn the master computer will then tell the Calibrator unit what
voltage or resistance standard is needed. When a frequency standard is required
by the slave computer a different scheme is used. Precision frequency standards
need a clean, controlled line. The lines used to carry the voltage and
resistance standards are not suited for frequency standards. The LTX data bus
with its high impedence pull down resistors and terminators is perfect for
carrying frequency standards. When the slave computer requests a frequency
reference it makes its request via the IPB to the master computer. The master
computer then tells the Calibrator to output a certain frequency. The Calibrator
ouputs this frequency via the Data Bus. As can be seen in Figure 3-18, the
Calibrator frequency output is connected to the slave computer by using special
Data Bus terminators which terminate all of the pins on the Data Bus except pin
36.
3.17 CP80 DUAL COHPUTER DATA BUS
In a dual computer CPSO, one data bus connects the left bulkhead
feedthrough/terminator, the calibrator, the master computer and a special data
bus terminator inside the CP80 rack; the other data bus connects the right
bulkhead feedthrough/terminator, master computer, and the special data bus
terminator. The special data bus terminator terminates all lines with 110 ohms
to 3 volts except pin 36, which is connected between both data busses, allowing
the calibrator reference frequency to be applied to all stations connected to
either computer. The special data bus terminator contains a standard
feedthrough for converting from dual to single computer operation.
3 - 27
THEORYOF OPERATION
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3 - 28
THEORY OF OPERATION
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Figure 3-17. TAPE 14UXBoard Blook Diagram
3- 29
THEORY OF OPERATION
m m m _ _ m m
CP80
m imm m m I m I m I
REFERENCE FREQUENCY
PIN 36 CALIBRATOR
_ , _-_o_
LEFT
I i RIGHT
SIDE SIDE
' COMPUTER
SLAVE IPB COMPUTER
MASTER k_
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m Imm m m m I m mm m m m ii mm m m m m
F' -- TS80 I .i, F '=' TS80 '==-I1
m CON-
TROLLER
STATION
'l I CON-
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L .... J L .... J
Figure 3-18. CP80 Dual Computer Data Bus
3- 30
Chapter 4
The Nova 3
CHAPTER 4
THE NOVA 3
4.1 INTRODUCTION
The unit that controls the data acquisition and manipulation functions in
the cPeO system is the Data General NOVA 3 computer.
The NOVA 3 consists of:
Central Processing Unit Two Floating Point Unit Boards

Multiply Divide Unit Front Panel
Memory Management Unit Power Supply
I or 2 Memory boards Chassis
The above named items are required to make the NOVA a functional processor.
To interface the NOVA to the cPeO system, the following boards, which are
discussed else where in this manual, serve as I/O and interface to the various
units of the cPeO.
Slot Saver II Array Processor Interface (optional)

Magnetic Tape Controller Disk Controller
LTX System Interface Inter Processor Bus (optional)
Figure 4-1 shows the slot locations of the boards housed in the NOVA
computer.
4.1.1 The CPU
The CPU directs the operation of the elements in the computer system. It
selects the operations they perform and coordinates those operations. The CPU
transfers data to and from memory and peripherals and performs arithmetic and
logic operations on data.
Peripherals under the direction of the CPU transfer information into and
out of the system, and store data within the system. A peripheral consists of a
controller, a device, and occasionally, an adapter. Peripheral controllers
communicate with the CPU via the NOVA (I/O) bus. Found on this bus is the disk
controller, the magnetic tape controller, the printer controller, and the Slot
Saver II.
4.1.2 Memory
Memory is used for storing and retrieving data. Data is transferred to and
from memory in 16-bit words. Though NOVA 3 computers can use semiconductor as
well as core memories, only the semiconductor type is utilized by the LTX
systems. Depending on the particular system, the NOVA 3 may have up to 512K
memo ry.
4-1
THE NOVA 3
There are 2 types of Intersil semiconductor memory boards available for the
CP80 system NOVA 3:ME128 128K and ME512 512K.
4.1 .3 ME128 (LTX P/N 874-0128)
The HE128 memory board is a semiconductor, 128K memory unit. A CP80 NOVA 3
may contain one or two of these boards for a maximum memory size of 256K. The
slot location for the ME!28 memory board(s) can be found in Fi§ure 4-1. The
ME128 memory array is organized into 8 rows by 17 columns of 16K dynamic RAMs.
This provides for a maximum storage capacity of 131,072 (128K) words, each being
16 bits wide. All circuitry for timing, control and refresh operations are
resident on the ME128 board. A DIP switch is located on the top of the memory
board for memory addressing. Consult Tables 4-1 and 4-2 for the proper switch
positions for your particular memory configuration.
4.1 .4 ME512 (LTX P/N 874-0129)
The ME512 memory board is a semiconductor, 512K memory unit. The ME512
memory board is available only on LTX systems. The CP80 NOVA 3 may contain only
one of these boards for a maximum memory size of 512K. The optional ME512 memory
board resides in slot 3 of the NOVA 3. The ME512 memory array is organized into
8 rows by 22 columns of 64K dynamic RAMs. This provides for a maximum storage
capacity of 524,288 (512K) words. Like the ME128 memory, the ME512 provides all
the necessary circuitry for control, timing, refresh and memory addressing. For
memory address DIP switch settings consult Table 4-3.
NOTE: In order to access all 512K memory of the ME512 pin A9

(XXMADR) must be externally jumpered to pin A9 of the mapping
unit. A special extended mapping unit must also be employed
to access all 512K of the ME512 memory.
4-2
THE NOVA 3
NOVA 3 MAIN FRAME
12 N3 FPU NO. 2
11 N3 FPU NO. 1
10 IPB (Optional)
9 LT× SYSTEM INTERFACE
8 DISK CARTRIDGECONTROL
7 MAGNETICTAPE CONTROL
6 ARRAY PROCESSORINTERFACE (Optional)
5 128K SC MEMORY(Optional)
4 LPT CONTROL - CRT CONTROL.- RTC
3 128K SC MEMORY (OPTIONAL- 512K)
2 MUL/DIV MMU
1 N3 CPU
Figure 4-1. NOVA 3 Slot Locations
4-3
THE NOVA 3
TABLE 4-1
ADDRESSING FOR INTERSIL ME128 MEMORY (0 TO 128K)
Starting Switch Setting °

cnm Address 128K 64K 32K I! 16K 8K 4K
0 0 0 0 0 0 0
4K 0 0 0 0 0 1
8K 0 0 0 0 1 0
12K 0 0 0 0 1 1
16K 0 0 0 1 0 0
20K 0 0 0 1 0 1
24K 0 0 0 1 1 0
28K 0 0 0 1 1 1
32K 0 0 1 0 0 0
36K 0 0 1 0 0 1
40K 0 0 1 0 1 0
44K 0 0 1 0 1 1
48K 0 0 1 1 0 0
52K 0 0 1 1 0 1
56K 0 0 1 1 1 0
60K 0 0 1 1 1 1
64K 0 1 0 0 0 0
68K 0 1 0 0 0 1
72K 0 1 0 0 1 0
76K 0 1 0 0 1 1
80K 0 1 0 1 0 0
84K 0 1 0 1 0 1
88K 0 1 0 1 1 0
92K 0 1 0 1 1 1
96K 0 1 1 0 0 0
lOOK 0 1 1 0 0 1
104K 0 1 1 0 1 0
108K 0 1 1 0 1 1
112K 0 1 1 1 0 0
116K 0 1 1 1 0 1
120K 0 1 1 1 1 0
124K 0 1 1 1 1 1
"1" = Switch "OFF" position

"_" = Switch "ON" position
4-4
THE NOVA 3
TAB LE 4-2
ADDRESSING FOR INTERSIL ME128 MEMORY (128 TO 256K)
_o
Oo
Starting Switch Settlng*
m Address 128K 64K 32K 16K 8K 4K
128K 1 0 0 0 0 0
132K 1 0 0 0 0 1
136K 1 0 0 0 1 0
140K 1 0 0 0 1 1
144K 1 0 0 1 0 0
148K 1 0 0 1 0 1
152K 1 0 0 1 1 0
156K 1 0 0 1 1 1
160K 1 0 1 0 0 0
164K 1 0 1 0 0 1
168K 1 0 1 0 1 0
172K 1 0 1 0 1 1
176K 1 0 1 1 0 0
180K 1 0 1 1 0 1
184K 1 0 1 1 1 0
188K 1 0 1 1 1 I
192K 1 1 0 0 0 0
196K 1 1 0 0 0 1
200K 1 1 0 0 1 0
204K 1 1 0 0 1 1
208K 1 1 0 1 0 0
212K 1 1 0 1 0 1
216K 1 1 0 1 I 0
220K 1 1 0 1 1 1
224K 1 1 1 0 0 0
228K 1 1 1 0 0 1
232K 1 1 1 0 1 0
236K 1 1 1 0 1 1
240K 1 1 1 1 0 0
244K 1 1 1 1 0 1
248K 1 I 1 1 1 0
252K 1 1 1 1 1 1
* "!" : Switch "OFF" position

"0" : Switch "ON" position
4-5
THE NOVA 3
TAB LE 4-3
ADDRESSING FOR INTERSIL ME512 MEMORY(512K)
SW
POS. ROW LOCATIONS (DECIMAL) LOCATIONS (OCTAL)
1 0 0 - 63K 000000-177777
2 1 64 - 127K 200000-377777
3 2 128 - 191K 400000-577777
4 3 192 - 255K 600000-777777
5 4 256 - 319K 1000000-1177777
6 5 320 - 383K 1200000-1377777
7 6 384 - 447K 1400000-1577777
8 7 448 - 511K 1600000-1777777
1 0
_
m ENABLED X /DISABLED
I--F-'mm
I-l_2
[--'1---14
¢["-F"I 5
F-'F"I7
F"I---'I8
LOC. 4C
4-6
THE NOVA 3
4.1.5 The Memory Management Unit
The MMU expands the CPU's memory address capability from 32K to 512K (note
that the CPU can only access a memory address span of 32K at any given time).
4.1 .6 The Multiply/Divide Unit
The multiply/divide circuit is additional logic which provides hardware

implementation of multiply and divide instructions.
4.1 .7 Floating Point Units I and 2
The Floating Point Unit is connected to the I/O bus of the CPU. It
consists of two modules, labelled Floating Point Unit I (FPU1) and Floating
Point Unit 2 (FPU2). Floating Point Unit I resides in slot 11 of the NOVA and
Floating Point Unit 2 resides in slot 12. Floating Point Units I and 2 are not
interchangeable and must be positioned in their designated slots. The LTX
operating system will not boot if it cannot find the floating point unit.
4.2 NOVA 3 CHASSIS
The NOVA 3 chassis supports twelve 15-inch square circuit boards, a power
supply board, and the console. The chassis holds the boards and console in fixed
positions, and facilitates electrical connections.
4.2.1 The NOVA Backplane
Each slot of the NOVA backplane has two PCB female edge connectors, which
mates with the male edge connector of the board to be inserted into the slot.
The contacts of the female edge connectors are connected to pins on the outside
of the backplane. The backplane consists of 2 pairs of fifty pins which
correspond to the contacts of the two edge connectors on the inside of the
backplane. The pins found on the left side are known as the "A" side pins and
the pins on the right ride are known as the "B" side pins. Figures 4-2 and 4-3
detail the "A" and "B" side pin connectors and the signals carried on them.
NOTE: If a board has been removed from the NOVA an interrupt

condition will be continually sensed . Figure 4-4 illustrates
how the pins of the backplane may be jumpered to defeat a
continuous interrupt due to an empty computer slot.
4-7
THE NOVA 3
_ GNO ;NO NNO GNO IBaNO DGO GND GNO

b__l ._, *SV +SV +SV +SV +._?V +SV +5V +SV
O_ _, _ FAIl -5¥ -SV -5V
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h.) RIM LICe3 RIM DGC3 LlCr_ UCC3
4b WRITE INN l I;LADRO M:IITEINN ZRADRO ZKADR0
or, SOO UDG UDO UOO UeIO SOO UOO UOO

USER Z/O )QtAORI$ USER Z/O )(I'U_I USER _ XNAI_ql U_SERZ/0 )(Itt[kql
_Q4ADR2 )Q4AORO XIdlAOR2 XNAORO _dADR2 _4AORO
BBACKUP BACKL,h
_ BACKUP BACKUP BACKUP BACKUP BACKUP BACKUP
41,
hal i SET DP1 t_ITE SET DP1 IldqITE
_
_ IRADRI IRE_ IRAORI
_O ;NO GND ;ND 6ND ;ND ONO ;NO GND
+VINN +VINH +VINH +VINN _¥INN +VINN +VINN +VINI(
f_ +VINN +VINH +VINN +VINN +VINH +VZNN +VINH +VINN
;ND GNO ;Nh eND ;ND ONO SOO eND
RA"EN ID(T SELECT1 PA"EN IDtTSELECT _ PAREN ID(T SELECT; PAREN EXT SELECT 4
_) mm.
INTA* "'IT*SELECT
INH _INTA WA--'_
INN SELECT )_0
%NTA RAZ-'-T
INN SELECT _
INTA INN SELECt'
WAX--V
DATIB I_d_ITE DATIB BIIRITE DATIB mdalT----_ DATI8 IIt_ITE
OATIA· SYI_ 4 DATTA mYNCEN DAT1A SYNCEN DATZA SYNCEN
_ z HO'-_ _'i HOL---'6 DS--T ·HOL**--_ m-T HOL--'T
_O DATOC* &U.IB DATOC ALUB DATOC OATOC
.j _. cu_ _Ab._ CL, I.RAO,2 CL, C_,
_ S'T_ _ _rr BnW _m eme_ _m*
OATIC B"E"EN DATIC Ig4EHEN DATZC B"E"EN DATZC IL'rdEHEN
_(_ DATOe nESET DATOB _SET DATOB RE_ OATOO R"G-_r
DATOA rmAmO
FETCH _
DATOA m_AUm
FET'_'_ _
OATOA i_OATOA
_ T LOAD CARNY _ LOAD C.tP4uly m'-"'_
_ T
T ZRADR2
ALUCAR_ItYIN mP
_ TRAm;
AU,ICARRYIN ml_
_
mRST "EPS mRST "EPS TOnS_ ZORST

,_ _8 _r _mAD_ D6_ amAm_ _' _8
IOPLS ALU--_ IOPLS _ IOPL$ II)PCS :1
_, mZVE.EH Xl2_B mZVE.EH _ _J
SEL----_
BCPUCLK ALU'-'-'_
_ SEL---'6
.CPUCLK _ _rL-6 _rC6
SE_ ALU_ gE-"_ k_"_----_ _
m DP_ A-OR m'_ XL_

_o srr DP'_ A_ SETmi A_
REAO .EH _N READ.Ell
_1_ _y[_[j5 IOUIOL SET TRAP IOUIOL
mm DCHPOm* DL_q*tl mHPOUT
, _ 0CHP_UT
+SV +SV
_EEDGEL +SV
GND +SV
ZNTPOLIT +5V
ZNTPIN +SV
ZNTPOUT _+SV +5V
ZNTPOUT
6ND GNO GND GNP ;=ND GND GNO GND
i' i"[ii! i CONSOLEEDGE CONNECTOR
2 4 6 8 10121416182022242628303234363840424446486052,545658 60
Ftgure 4-2. "A" Side of NOVA Backplane
4-8
THE NOVA 3
._ I_ GND GND GNO GND GND GNO GND GNO

_1_ ab +5V +SV +SV HSV +SV +SV *SV *5V
O_ _ EXT OSC CLOCK CLOCK 50/60 HZ CLOCK CLOCK
)' CO GND NAOR15 ;NO HADRIS N NADA15 GNO NA_
0 IHT XI4H KaLOR14 IHT llffl NAOR14 _ NAOR14'

HADIa13 MADA13
o
N MADR13 AUJCARRYOUT MADR15 AUJCARRYOUT
ab I_OR12 2_EN HADR12 EREN HADRII* MAOR12
o
NAOR11 _' tIAI_I 1 _ NAORI1 I_ORI 1 *
co ' NADI_IO _ NADIqIO DCHMO
NA_s E?f- PAmB E_ i NAORe'
NAm! OC..---'_ NAme DOd4'1 _Onll _ NAme*
NAOR7 NSP3 NADR7 NSP3 KAOA7 NADR71 _lg
NAi)18 P,SPO _OR8 IdSP2 _ NAO4qe*
--,_ NADAS I,ISPI NADAS NSPl NADA5 NA_I5*
NADR4 HT---"_
X NAiX14 _ _ _ : PAOIq4,,
NAOiq3 SHIRT 50 NADtq3 SHIFT SO t NADR3*
At.UA OCHO----'_ ALUA _ _
_0 NEWCARRY OCNXe NEW CARRY DCHT _CHZ OCHX

_) _ OV FLO _ OV ILO OV FIO OV IcLO
NADn_ n_Ne* HADR; _m _ _ NAm,-,*
+V lrNHP PN_ITY .tV TNIeP PARITY +V INHP PA_ *V INHP JS'J]Bi'['IrV
GNO AUTO 0140 AUTO GNO GNO
NSPO OEFER NBPO O_IDER

CSTOP RESTAHTEN
DATA'IHT DATA7T 'UTA t4 DATA7 TA1-'--4
fif, DATA7 _TAld DATA'"--7-
BATAIIT DAT&ST DATA11 DATA_ MTA¶I DATA"'-'_ DATAt'--'--_
DA?AlIT DATAIEr I OATAII DATAIE OA?'"--_ DATAI_ OATA-----8 T_
N_ DATAOT OATA4T i DA'-T'AO _?i4 G_T_ OATA"--4' DATAO DATA"----4
C_ OATA13T OATAOT I DA_ DATAll DATAI'-'-_ DATA'-'"_ DATAI3 DAT'"'""_
: DATA151' BATAIT BATAt'"_'S OATA"_ DATA1--'-'5 DATA1 OATA1S DATA"---_
HEmS
_m4 n_ LOAD
C8 NEN,t----"_
idEidl"-'""_ NI_
NC.
NENI---'-_ S"'--'%
NE.I
_
N_N14
NEN12 NEN1---'_ NEN12 NEH13 I_NI'""_ NEN13 '''''-%
I¢EN12 NEH13*
._ .EH_I OATA,1T NEm_ D_TA_ NE_------T DATA_ _ _

14_'10 DATAIOT _ OATAIO NEHI"_' DATAtO _ _ -d
_o OND _ ONO _LF_J eNO _ "NO
_TA2T C_f_XNST OATAI_ _" _ -BV _ HSV
CON_Q _
_ _VZNHP __ _
VZ.HP _
NE--_ -'--&
HEN4
_mp HE_'
_*
_o _ NEH'"--_ _ _ _ _ '--t't't't't't't't't_F NEH"_.
_ _ ;NO _ .NO _ m NENO'--'_ GdO
GNO NApE_'_ _NO NAPEN eNO GNO
CARRY DATA6T _ DATA" MTA6
+SV +51/ .FSV +SV +BY +SV +SV +SV
GNO gNO 8NO GNO 8NO 6NO _NO GND
Figure 4-3. "B" Btde of NOVABackplane
4-9
THE NOVA 3
3 _ _ 93 95 97 9g 3 _ "_ 93 95 97 99
A-SIDE _ B-SIDE
2 4 94 96 98 100 2 4 95 94 96 98 100
I I I I
NOVA 3 BACKPANEL(as you face it)
Priority jumpers must be installed across any slot not containing

a board, (from pins 93 to 94 and 95 to 96).
Figure 4-4. Interrupt Priority Jumper Installation
4 -10
THE NOVA 3
4.3 NOVA 3 POWER SUPPLY
The NOVA 3 power supply resides in slot 0 of the computer chassis (Figure
4-5). The NOVA 3 power supply cord plugs directly into P8 of the AC
Distribution Box. The power supply has the following main components:
A power switch
A convenience outlet
Circuitry that performs AC-to-unregulated DC conversion
Circuits to generate voltages- +15V, +18V, +5V, -5V, +14V
Power fail circuitry
Circuitry that generates auxiliary voltages
4.3.1 Power Switch
The power switch connects and disconnects AC line power from the power
supply. It is mounted on the console. For 100 and 120 volt operation, the
power switch simultaneously connects and disconnects both the AC hot line and
the AC return line.
4.3.2 Convenience Outlet
A convenience outlet mounted on the rear of the chassis provides AC power

at line voltage whenever the chassis power is turned on. The outlet is
protected from overloading by the AC line fuse.
4.3.3 AC-to-Unregulated DC Conversion
The power supply elements needed to perform AC-to-unregulated conversion

are labelled "+30 VNR" in the block diagram. The conversion is performed as
follows:
When the power switch is in its ON or LOCK position, AC power is

applied to an AC line filter. The line filter prevents undesirable
transients generated by the AC source from further transmission along the AC
input line. Line filtered AC is then applied to the input of a step-down
transformer. The output AC voltage of this transformer is changed to
pulsating DC voltage by a full-wave bridge rectifier. This rectifier feeds
a capacitor filter which smooths the pulsating DC voltage to produce +30
VNR, an unregulated power signal.
4.3.4 Power Fail Circuitry
The power fail circuitry monitors the voltages across the +5V, +5VBB, +14V,
and +30 VNR filter capacitors to determine when power is failing. The power
fail circuitry produces two outputs: PWR FAIL and PWR OK.
When the power supply is turned on, PWR FAIL remains at a Iow voltage level
until +30 VNR is within its normal operating range. PWR OK remains at a LOW
level until +14V, +5V, and +5VBB are within their normal operating ranges.
4-11
THE NOVA 3
E
g]
o
0
...a
r.t)
L
m
o
n
>
0
z
- ¢
=
_ °°
" 1...........-]
>:- [ I
_ g g
: 1 I
o___ _1
,_, - __
L_. .............. __J
Figure 4-5. NOVA Power Supp y Block Diagram
4 -12
5.5 DISK POWERSUPPLY
The AC power cord from the CDC 80 mega-byte disk power supply,{Figure 2-3)
plugs directly into P7 of the AC Distribution Box. The disk power supply then
distributes the AC power to the drive motor, fans and the DC power supply. All
of the DC voltages are protected by fuses located on the power supply. The DC
power supply provides all of the DC power used within the disk unit. Basic logic
circuits are all +/- 5 volts. The +/- 24 volt circuits are used for the servo,
fault circuits, drive motor brake , and motor start circuits.
5.5.1 Test Points
There are numerous test points located throughout the CDC 80 MB disk drive
for a complete listing of these test points, their function and how they may be
used in troubleshooting the CDC disk drive, consult the CDC MINI MODULE DRIVE,
HARDWARE MAINTENANCE MANUAL provided with your system.
TABLE 5-9 CDC 80 MEGA-BYTE DISK FUSE LIST
FUSE TYPE USE LOCATION
5A 250V MTH Line 240V Power supply

7A 32V AGC +7V Switched Power supply
7A 32V AGC -7V Switcted Power supply
5A 32V AGC +24V Switched Power supply
5A 32V AGC -24V Switched Power supply
5--13
_o -5 V ADJ
CD
+5 V AI)J
FUSE
(Fl)
__,_' THERMOSTAT
(Si)
%% t9
CIRCUIT
BREAKER POWER
(CB 1) SUPPLY
AC
POWER CABLE
Figure 5-7. CDC 80 Megabyte Disk Drive Power Supply
5 -14
CDCSO HEGABYTENZN/NODULE DZSK
[] []
_ _ od
e.
0
.la
f,.
(D
B
0
D.
m
v._
cr P'l
o_ -- _
**=* ·
[] [] ,-
· > _ U.
W_
u_>o
411: o
m_
6 /
[] []
12110
-5-15
CDC 80 MEGABYTE MINI MODULEDISK
-24 V FUSE +24 V FUSE CONNECTOR

(f5) (F2) J12
oSl:::: _z v
+5 V FUSE (F3)'
Fl:
POWER SUPPLY
AC FUSE
o
0
Figure 5-9. Power Supply Fuse Locations
5 -16
5.6 MOVING THE CDC DISK DRIVE
From time to time it may become necessary to relocate the CP80 cabinet.
Each time the CP80 is moved the following preparations MUST be performed before
the CDC disk drive is moved, to prevent any serious damage being done to the
drive and its fixed disks.
5.6.1 Securing the Disk
Caution
During this procedure do not allow the spindle to rotate in any

direction other than that shown in Figure 5-10.
1. Remove disk drive top and bottom covers.
2. Lock actuator by rotating actuator shipping lock to lock position. See

Figure 5-12.
Caution
Failure to lock the actuator before moving the disk drive will
result in damage to the disk surface.
3. Remove the motor drive belt by pushing drive motor forward until
the drive belt falls off.
4. Lock the drive motor:
On newer units see Figure 5-11.
On older units see Figure 5-11.
5. Position the spindle lock and ground spring by loosening the attaching
screws and sliding the assembly forward until the "pin" rests securely
in the "spindle lock notch". See Figure 5-13.
5-17
ovo
oo
ROTATE SPINDLE ONLY IN
DIRECTION SHOWNBY ARROW. DRIVE
BELT
Figure 5-10. Drive Belt Removal and Replacement
5-18
MOTOR SHIPPING MOTOR

LOCK SCREW
'_ PLATE
MOUNT
I
OLDER UNITS
TAPPED
SCREW
SELF-LOCKING NUT
MOTOR
LOCK MOTOR
MOUNT
PLATE
WASHER
NEWER UNITS
MOTOR SHIPPING
LOCK
Figure 5-11. Drive Motor Lock Screw
5 -19
,_ MINI ACTUATOR
MODULE SHIPPINGLOCK
\ x
X
IA X___LOCKED
Figure 5-12. Actuator Shipping Lock
SPINDLE
._ LOCK
i_ NOTCH
E /
sPmD,
PULLEY / II I \% ATTACHING
_'--_-'-/__---------q
_ SPmDLE
LOCK"
PIN
Figure 5-13. Spindle Lock and Ground Spring
5 -20
I I
REAR OF CARD
I I
7 OFF
6 OFF
5 ON
4 OFF
3 ON
2 OFF
1
8 OFF
OFF
7 OFF
6 ON
5 ON
4 OFF
3 OFF
2 OFF
1
8 OFF
OFF
7 OFF
6 ON
5 OFF
4 OFF
3 ON
2 ON
1 OFF
8 ON
Figure 5-14. Spectral ogi cs Disk Controller Board
5- 21
5.7 DISK FORMATTING PROCEDURE FOR THE 80 MEGABYTE DISK
The 80 Megabyte disk formatter program is used to format the disk prior to
disk initialization and the LTX system software installation. To execute this
program you will need the 'DTOS REV. 8.1.1' diagnostic tape.
NOTE: There are two types of controllers for the 80 Megabyte

disk drive -- Spectra and Xylogics. Determine the type of
controller in your system in order to give the appropriate
response in step 10 of the procedure below.
Caution

Chapter I for the procedure on how to build a system back-up
tape.
On single computer CP80 systems:
1. Set all switches on the NOVA front panel to 0 (down).
2. Mount a "DTOS REV. 8.1.1" diagnostic tape on the tape drive.
3. Set switch 15 on the NOVA front panel to a I (up).
4. Turn the program load key on the CP80 front panel, clockwise.
On the CP80 dual-computer systems:
1. Turn off the slave computer power switches.
2. Set all the switches on the master computer front panel to 0

(down).
3. Mount a 'DTOS REV. 8.1.1' diagnostic tape on the tape drive.
4. Set the master computer switch 15 to I (up).
5. Turn the 'Program Load' key on the front of the CP80 cabinet
clockwise.
At this point, the system performs a multiple-phase test cf the

general computer functionality. As each phase of the test is
completed, another character of the sequence 'TESTOK' is displayed on
the CRT. If all phases of the test are completed successfully, the
CRT will display "TESTOK". If the CRT display shows only part of the
"TESTOK" message, it indicates a probable failure in the first 32K of
memory.
5 -22
If 30 seconds elapse with no display on the CRT, several problems are

possibl e:
1. The tape is bad.
2. The tape drive is bad.
3. The CRT, Slotsaver II, Memory, or the CPU is bad.
Following the display of "TESTOK", the system will display a series

of prompts on the CRT. The computer prompts and the appropriate
operator responses follow.
6. CPUTYPE; NOVA (no response required)
7. CPU TYPE IS NOVAIII (no response required)
8. TOP OF MEMORY= 077777

HIDTOS VERSION 8.1
9. * LOAD
ZDKP
FMTR
10. SET SWPAK AS PER SECT 8.0'

ORHIT [CR] TO CONTINUE I [CR]
If printed output
is desired, type 5
following the 1, then
hit [CR]
11. CONTROLLER (SPECTRA=O XYLOGICS=I) Type 0 or 1, as appropriate

for your system.
12. # OF PASSES TO FORMATCOMPLETION? 6
NOTE: LTX recommends 6 passes of this program to truly

test the disk.
* According to the switch settings described in LTX DTOS Rev.

8.1 .1 under "Moving Head Disk Reliability.
5 - 23
13. UNITNUMBERS 0 [CR]
14. 80 OR160 MEGABYTES

? 80 [CR]
UNIT: 0
15 o FORMAT DONE
HALT ENCOUNTERED
&
@ (No responserequired)
NOTE: When the message 'FORMAT DONE' appears on the CRT

screen, the program will be in the process of formatting the
disk pack. The program will print the rest of the prompts
when it come to a normal end.
5 - 24
5.8 DISK INITIALIZATION , AND RELIABILITY CHECKING PROCEDURE

FOR THE 80 MEGABYTE DISKS
The 80 Megabyte disk formatter and initialization programs are used to

format and initialize the disk prior the the LTX system software installation
procedure, To execute these programs you will need the 'BO Megabyte Disk
Diagnostics' tape and the 'LTX System Software' tape.
NOTE: There are two types of controllers for the 80

Megabyte CDC disk drive -- Spectra and Xylogics. Determine
the type of controller in your system before you start the
procedure below.
Caution

Chapter I for the procedure on how to build a system back-up
tape.
1. Mount the 'LTX SYSTEM SOFTWARE' tape onto the tape drive.
2. Set all switches on the master computer to 0 (down). Set switch 15 to

I (up).
3. Turn the "Program Load" key on the CP80 cabinet clockwise.
4. FROM
MTO: 4 [CR]
5. DISK INITIALIZER - REV 99.99

LTX DISK DRIVE MODEL NUMBER
(DKIO or DK80)? DK80[CR]
6. MMD (80-MEGABYTE) DRIVE TYPE

DISKUNIT? DZO[CR]
7. COMMAND? FULL[CR]
COMMAND DESTROYS ANY PREVIOUS RDOS
DISK STRUCTURE. RDOS INIT/F MUST BE
DONE ON DISK AFTER COMMAND.
TYPE CONTROL-A NOW TO ABORT WITHOUT
LOSS
8. NUMBEROF PATTERNSTO RUN (1-5)? 5 [CR]
5- 25
At this point the system will check every storage location on the disk by
writing and reading back 5 different bit patterns in each location. This
process takes about 60 minutes. Each pattern will be identified on the CRT,
following which will be a list of the bad blocks encountered and reassigned
during that part of the test. Each bad block on the disk is the equivalent of
256 words of memory. The same bad block may be found on multiple patterns. The
bad block table generated by this procedure does not eliminate the need to enter
the bad blocks from the bad block table which accompanies the disk.
9. DO YOU WISH TO DECLAREANY YES [CR]

BLOCKS BAD THAT ARE NOT ALREADY
IN THE BAD BLOCK TABLE?
NOTE: A bad block table accompanies every 80 Megabyte disk.

The major headings of the bad block table appear as
follows:
( ..... DEC.... ) ( .... OCT.... ) (-----DEC ..... )
Under 'OCT' are four columns: 'CYL', 'HEAD', 'SECT',

'BLOCK'. The numbers in the columns labelled 'BLOCK' are the
bad block numbers which must be entered.
10. BAD BLOCK NUMBER

(TYPE RETURNTO STOP)? 999999 [CR]

(TYPE RETURNTO STOP)? 999999 [CR]

(TYPE RETURNTO STOP) [CR]
13. DO YOU WISH TO DECLARE ANY MORE

BLOCKS BAD? NO[CR]
14. REMAP AREA SIZE IS XX BLOCK(S)

LONG WITH XX BLOCK(S) ALREADY IN
USE FRAME SIZE IS XX
FULL DISK INIT COMPLETE. (No response required)
15. COMMAND? STOP[CR]
16. Now turn the 'PROGRAM LOAD' key on the CP80 cabinet clockwise
17. FROM
MTO: 5 [CR]
18. BOOTSTRAP DEVICE SPECIFIER? DZO [CR]
19. INSTALL BOOTSTRAP(Y OR N)? Y
20. DONE
5 - 26
5.9 LTX FILE BACKUP PROCEDURE FOR AN BO MEGABYTE DISK DRIVE (DISK TO TAPE)
This procedure creates a system backup tape by dumping the disk resident
files of an LTX system with an 80 Megabyte disk drive onto the magnetic tape
drive. It should be performed as a precautionary measure to protect data
against any mishap. A system backup tape should be made before undertaking any
procedure that will destroy all files on the disk -- such as formatting and
initializing of the disk with LTX system software -- if it is desired to save
the information contained on the disk.
Caution
The following procedure WILL NOT save the LTX Operating System. To
create a back-up tape for the LTX Operating System consult Section
5.10.
1. Mount a 2,400 ft. magnetic tape onto the tape drive.
2. Press the tape drive front panel switch 'LOAD/UNLOAD' to LOAD

position, then the 'ON-LINE/RESET' switch to ON-LINE.
3. The LTX operating system will come up with the 'READY' prompt
on the CRT, signifying that it is ready to accept commands via the
keyboard.
4. When the 'READY' prompt appears, enter the following commands on the
primary CRT of your system, or the primary CRT of the slave computer
in a dual computer configuration.
a. READY TRANSFER/V -.- [CR] *
b. INPUT FROM (D=DISK, T=TAPE) D [CR]
c. DIRECTORY (S=SYSTEM, OR NAHE)? S [CR]
d. OUTPUT TO (D=DISK, T=TAPE,

C=CRT, P=PRINTER)? T [CR]
e. WHERE (B=BEGIN, E=END, OR

FILE NUMBER)? 0 [CR]
f. RELEASE AFTER TRANSFER (Y OR N) Y [CR] (single processor)

N [CR] (dual processor)
5- 27
In a single computer CP80 system, the before-mentioned commands

cause the computer to transfer from the disk to File 0 of the
magnetic tape all files contained in the System directory and its
associated Data sub-directory. After the data transfer is
completed, the transaction terminates.
In a dual computer CP80 system, this sequence of commands will

cause the s_ave computer to transfer from the disk to File 0 of the
magnetic tape all files contained in the slave computer's System
directory and its associated Data sub-directory.
Proceed to Step 5 for the transfer of files in the master computer's

DZO directory and the associated Data sub-directory.
5. Mount a new 2,400 ft. magnetic tape on the tape drive and place it
ON-LINE as in Step 2 above. Enter the following commands on the
master computer:
a. READY TRANSFER/V -.- [CR] *
b. INPUT FROM (D=DISK, T=TAPE) D [CR]
c. DIRECTORY (S=SYSTEM, OR NAME)? S [CR]
d. OUTPUT TO {D_DISK, T=TAPE,

C=CRT, P=-PRINTER)? T [CR]
e. WHERE (B=BEGIN, E=END, OR

FILE NUMBER)? I [CR]
f. RELEASE AFTER TRANSFER (Y OR N) Y [CR]
g. READY
When transferring files from the 80 Megabyte disk drive onto s magnetic
tape, make sure to install a long (2,400 ft.) tape on the tape drive. If
you are dealing with a dual computer system and an excessively full disk
you may find it impossible to transfer both the slave and master files on
the same tape. It is a good practice to always use two long tapes for a
dual processor system backup.
* Append the '/L' option to the TRANSFER command (TRANSFER/V/L) to obtain a

hard copy listing of all the files transferred from disk to tape.
5- 28
CDC 80 MEGABYTEMINI _IODULEDISK
When the READY prompt reappears, the file transfer operation for a dual
computer system is completed. The files are organized in the fol lowing
manner:
Tape File Organization
Single Computer I Dual Computer
MTO:O System directory files I MTO:O System directory files

Data sub-directory files I Data sub-directory files
I (slave computer)
I
I MTO'I DZO directory files
I Data directory files
I (master computer)
5- 29
5.10 CREATING AN LTX OPERATING SYSTEM BACKUP (DISK TO TAPE)
The following procedure will create an exact duplicate of the LTX Operating
System resident on disk at the time of this procedure's execution. This
procedure should be performed as a precautionary measure to protect the
operating system from any mishap.
1. Mount a 2,400 ft. magnetic tape onto the tape drive.
2. Press the tape drive front panel switch 'LOAD/UNLOAD' to

the LOAD position, then the 'ON-LINE/RESET' switch to ON-LINE.
keyboard. Then proceed as follows:
COMPUTER
PROMPTS OPERATORRESPONDS
a. READY CALLCLI
b. R LaCOPYLTX@
The LTX Operating System should now be loading onto the

tape, when finished, to get back into the LTX Operating
system from CLI, proceed as follows:
c. R POP
d. READY
With the "READY" prompt now displayed, the operator has

successfully created a back-up operating system tape and
may now continue with what ever task may be at hand.
5- 30
5.11 CREATING AN OPERATING SYSTEM BACKUP (TAPE TO TAPE)
The following procedure will create an exact duplicate of the LTX Operating
System resident on a tape.
1. Mount a operating system magnetic tape onto the tape drive.
2. Press the tape drive front panel switch 'LOAD/UNLOAD' to

the LOAD position, then the 'ON-LINE/RESET' switch to ON-LINE.
keyboard. Then proceed as follows:
COMPUTER
PROMPTS OPERATOR
RESPONDS
a. READY CALL
CLI
b. R aSYSTAPE@
c. LOADAN LTX OPERATING (This should have al ready

SYSTEMTAPE, THENTYPE been done in steps 1,2 and 3.
ANY KEY TO CONTINUE
The computer should now be reading the operating system tape mounted on
the tape drive unit.
d. LOADA BLANKTAPE ONTO {Remove the op system

THE SYSTEM,THENTYPE tape frome the tape drive
ANY KEY TO CONTINUE. mount a blank tape, then
follow Steps 2 and 3.)
The computer should now be writing the data it read from the system tape
on to the blank tape.
e. TO MAKE ANOTHER OPERATING

SYSTEM TAPE, TYPE Y FOLLOWED
BY A [CTRL]-Z. OTHERWISE, TYPE
N FOLLOWED BY A [CTRL]-Z.
If Y[CTRL]-Z is selected the computer prompt will return the operator

to Step "d.". If N[CTRL]-Z is selected then proceed as follows:
f. R POP
g. READY
With the "READY" prompt now displayed, the operator has successfully
created a copy(s) of the LTX Operating System tape and may continue
with what ever task may be at hand.
5--31
Chapter 6
CP80 Tape Transport

CHAPTER 6
CP80 TAPE TRANSPORT
6.1 INTRODUCTION
The magnetic tape unit on the CP80 is used for backup purposes, and the
initial loading of the LTX operating system. As a saftey precaution, a backup
tape should be made every 24 hours of everything that has been loaded on to the
system disk. In doing so you are assured of only losing a minimum of material
should the system disk fail. Figure 6-1 is a typical LTX77 system tape drive.
6.2 THE TAPE TRANSPORT
The standard LTX77 system magnetic tape transport is the Data General 6021.
The 6021 transports are 75 ips, vacuum column drives which use a half inch, 9
track format. Data is recorded in IBM-compatible Non Return to Zero Inverted
(NRZI) format at 800 bpi. A block diagram of the tape transport unit can be
found in Figure 6-2.
6.3 TAPE PATH ELEMENTS
The BOT and EOT sensor, tape guides and the suction tape cleaner attach
directly to the transport casting. The surface of the suction tape cleaner and
the transcription head is all that touches the recording surface of the tape.
A diagram of the tape path and tape threading can be seen in Figure 6-4.
6.3.1 Read/Write Head
The read/write or transcription head assembly, is a 9 track, read-after-

write, magnetic head. The read after write assembly allows for instant
verification of data transcribed onto the tape.
6.3.2 Capstan
All tape motion is initiated and controlled by the capstan and its servo
system. Motion commands from the tape subsystem controller and from the
transports own control system cause the capstan to move forward or backward at
75 ips for a read/write and 200 ips for rewind.
6.3.3 Suction Tape Cleaner
As the tape moves in a forward direction, just before it passes over the
read/write heads, the tape is cleaned of any dust and tape debris by a suction
device. The cleaner is connected to the vacuum system and is vented along with
any dirt it may remove from the tape, through the back of the transport via one
of the cooling fans.
6-1
CP80 TAPE TRANSPORT
CAPSTAN
READ/WRITE
_'_ HEADS
PHOTODETECTOR
SUCTION
TAPE
CLEANER
VACUUM
COLUMNS
!i!_i!iii!ijlj,
Figure 6-1. CP80 Tape Drive Unit
6-2
CP80 TAPE TRANSPORT
6.3.4 Tape Guides
There are two types of tape guides on the CP80 tape transport: noroller
guides, of which there are two and roller head guides of which there are four.
The two nonroller head guides stabilize the tape as it enters the vacuum
columns. The four roller guides provide large radius, Iow friction guides for
abrupt direction changes in the tape path.
6.3.5 Vacuum Column
Because of the high acceleration of the capstan, if it were not for the
vacuum columns, tape damage could occur with every start and stop of the tape
transport. Tape is gently pulled into the columns by their internal vacuums.
Each reel motor is associated with a vacuum column and a servo system that
strives to keep the tape loop in each column positioned near the center of that
column.
6.3.6 BOT/EOT Sensor
The beginning of tape and the end of tape sensors contain two LEDs and two
phototransistors in a sealed assembly. Each LED is paired with a phototransistor
and scans half the width of the tape for BOT or EOT markers. When a marker
passes a sensor, the marker reflects the light of the LED back on to the
phototransistor. The phototransistor then signals the tape transport control
logic that an EOT or a BOT has just been sensed, and the appropriate action is
taken by the controller.
6.4 TAPE MARKERS
There must be some blank, unused portion of tape at both the beginning and
the end of each tape. This blank portion, or leader, is used to thread the tape
through the tape drive. The leader takes all the abuse of being handled, thus
saving the "data" portion of the tape. There are reflective pieces of material
at the beginning and end of each tape. This reflective material signifies the
beginning (or end) of the leader and the end (or beginning) of usable data.
These markers are placed on the uncoated (shiny) side of the tape.
6.4.1 Beginning of Tape Marker
The beginning of tape marker (BOT) is a reflective strip placed along one
edge of the tape. The transport uses it as an absolute reference point in
determining the beginning of the "DATA" portion of the tape.
The BOT marker is placed approximately ten feet from the physical beginning
of the tape. This allows enough leader for threading. The marker must be
parallel to, and not more than 0.03 inches from, the edge of the tape closest to
you when the reel is mounted on the tape transport.
6.4.2 End of Tape Marker
The EOT marker serves the same purpose as the BOT only for the other end of
the tape. The reflective marker is placed about 25 feet from the end of the
tape.
6-3
CP80 TAPE TRANSPORT
TAPE MOVING
--O CONTROLS
PO ·
co
CONTROLLER CONTROL MOTION CAPSTAN

L_S AND ORIVER
TO/FROM i _ -' RAMP
CAPSTAN
STATU_
SIGNALS
J,/
READ-AFTER-
HEAD
SENSING HOLE
LOAD
I FIqON
R_HT ,_
VACUUM COL_
COLUMN · /
S_ERVO
SYSTEM VACUUM
DISABLE
OPERATORS ._
PANEL
READ PEAX
AND THRESH
DETECTK)N
DATA
WRITE WR STROBE HJU_OLING
DRIVERS ELECTRONICS
LEFT VACUUM COLUMN

TRANSDUCER iSUPPLY
REEL SERVO) DESKEW
BUFFERS
TO FROM TAPE -- RD STR --
CONTROLLER READ DATA BUS
f WRITE DATA BUS
IR6
GAP AND
DELAY 1 -- DELAY TIMERS
DEN SEL
SEND CLK_
Figure 6-2. Tape Transport Block Diagram
6-4
CP80 TAPE TRANSPORT
6.5 TAPE DRIVE FRONT PANEL
Figure 6-3 shows the various switches and indicators on the CP80 tape drive
front panel. Use Figure 6-3 as a reference for the following discussion on the
tape drive front panel.
Figure 6-3. CPSO Magnetic Tape Unit Front Panel
READY - This indicator lights up when, the power is on, tape transport is
on line, and if the tape transport is ready to receive and execute the commands
of the program.
WRITE LOCK - This indicator lights if no write enable ring is on the supply
reel.
EOT (End of Tape) - This indicator turns on when the photodetector senses
EOT reflective marker. The indicator remains lit until: the program sends a
rewind command, the rewind button on the front panel is pressed, or if the
program sends a command to space in the reverse direction, past the EOT marker
to the beginning of tape marker.
BOT (Beginning Of Tape) - This indicator turns on when the photodetector

senses the BOT (Beginning Of Tape) reflective marker. The indicator stays on
until the tape moves away from this point.
POWER- When this switch is in the ON position, the tape drive is powered
up and the indicator is lit.
LOAD/UNLOAD - This switch is used to load and unload the mag tape unit.
This switch is only used when the tape drive is off line.
After properly threading the tape, put this switch in the LOAD position and
the tape will advance to the BOT position.
When removing a tape reel, put the switch in the UNLOAD position to rewind
the tape to the BOT position. When the tape has stopped at the BOT position,
depress the switch to the UNLOAD position and hold it down until the tape has
completely rewound on to the supply tape.
6-5
CP80 TAPE TRANSPORT
ON LINE/RESET - When a tape has been properly loaded to the BOT marker, put
this rocker switch in the ON LINE position. In doing so you will be putting the
tape drive in the ON LINE mode and the READY indicator will light up. At this
point the tape transport is ready to receive programmed commands.
When the tape transport is ON LINE the only tape transport front panel
controls that are active are the POWER and RESET switches.
When the RESET half of the rocker switch is depressed the tape transport
goes off line, the tape stops, and the tape transport logic is reset.
REWIND - When the tape transport is off line this button is used to move
the tape backwards at a high speed to the BOT marker.
SELECT - In the LTX77 system this eight position (0-7) switch is always set
to zero (0). The standard system computer can handle up to eight tape drives.
The select switch identifies the tape transport to the computer. In the LTX
system, because there is only one tape drive, this switch should always be set
to O.
6.6 TAPE TRANSPORT POWER DISTRIBUTION
The tape transport power cord plugs into connector P3 of the AC

Distribution Box. Figure 6-4 shows the major components of the power supply and
distribution system. The AC input is shown at the left and the regulated DC
outputs appear at the right. AC power is fused and filtered and connected to the
AC relay module. The module produces a Iow level DC control for the panel
mounted power switch. The switched control voltage energizes a solid state relay
that connects the AC power to the Constant Voltage Transformer (CVT) and cooling
fan. A second remote module routes power to the vacuum pump. It obtains its
control voltage from the +5 VDC regulated output.
The CVT outputs are rectified and filtered, and provide 7 coarsely
regulated DC voltages. The rewind logic controls a switch that allows the +/- 20
volt outputs to over ride the +/- 12 volt outputs: this provides increased
voltage to the Capstan and reel motors during a rewind operation. Preloaded
resistors stablize the CVT under light load conditions. A five pole DC circuit
breaker prevents execssive current flow on the + 12 and +20 volt outputs, and a
three pole breaker protects the +15 and +8 volt outputs. Four linear series pass
regulators provide additional operating voltages for the drive circuits. An
overvoltage crowbar opens the three pole breaker if the +5 volt output exceeds a
preset limit.
6-6
CP80 TAPE TRANSPORT
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6-7
CP80 TAPE TRANSPORT
6.7 TAPE LOADING PROCEDURES
When loading magnetic tape touch the tape on the leader areas only. Do not
allow the tape to twist in the tape path, drag on the floor, or come in contact
with dirt or grease. When a reel is placed on the supply hub, do not press the
flanges of the reel. Exert any necessary pressure on the center ring of the
reel.
When you are ready to load a tape, first find out whether the tape is to be
written on. If so, insert the write-enable ring in the circular groove on the
back of the mag tape reel. If properly installed, the WRITE LOCK indicator on
the front panel will NOT be lit. If the tape is not to be written on, insure
that the write enable ring is removed from the tape. This will cause the WRITE
LOCK indicator on the front panel to light up.
6.7.1 To Load a Tape
1. Slide the supply reel over the supply hub so that the write enable ring or
the groove provided for the ring is towards the tape transport.
2. Secure the reel by pushing the center hold down knob, or in older drives,
by pushing the locking lever in the center of the hub. Insure that the
the lever is flush with the hub.
3. Check the status of the WRITE LOCK indicator. If reel is supposed to be

write protected, the light should be lit.
4. Holding the tape by the leader, thread the tape through the tape transport
as shown in Figure 6-5. Make sure tape lies flat across the vacuum columns
and winds onto the takeup reel in the correct direction.
Press the LOAD switch. The tape will be drawn midway up the vacuum columns
and will move forward until BOT is sensed by the photodetector. If the BOT
is not found within approximately seven seconds, the tape will rewind
until the tape is pulled completely off the tape reel.
6. Once the tape has advanced to the BOT position depress the ON LINE switch.
The ON LINE and READY indicators will then light. The tape transport is
now on line and ready to accept programmed commands.
6-8
CP80 TAPE TRANSPORT
Takeup
Reel
Supply
Reel
x_ _X ' _,
Figure 6-5. Tape Threading Layout
6-9
CPBO TAPE TRANSPORT
6.7.2 Unloading The Tape Transport
Always unload the mag tape on to the supply reel before the system is
powered down. To unload the mag tape and shut down the mag tape system, proceed
as follows:
NOTE: When using the tape drive via LTX operating system
commands the operator will be forced to indicate whether or
not the tape is to be released (rewound) at the end of a
command sequence. If it is desirable to remove a tape which
is not at BOT, the "RELEASE TAPE" command should be issued
at the console. This procedure insures the proper resetting
of the mag tape logic circuits.
1. Depress the RESET switch, which places the tape unit off line. Then press
UNLOAD. The UNLOAD switch will cause the tape to rewind to the BOT and drop
out of vacuum columns.
2. When the tape has reached the BOT, depress and hold down the UNLOAD switch
until the tape has completely unwound onto the supply tape.
3. Remove the tape from the tape transport.
4. If you are finished using the tape transport, press the POWER switch to the
OFF position
6.7.3 Loading Backwards
If a programming error causes the tape to go past the End Of Tape marker
and off the supply reel, proceed as follows:
1. Rethread the tape back on to the supply reel following the path shown in
Figure 6-5.
2. Press and hold down the UNLOAD switch while using light pressure on the
center of the upper reel to slow it down slightly, thus preventing the tape
the tape from cascading on to the floor.
3. When approximately 25 feet of tape has been rewound on to the supply reel,
press RESET then press LOAD.
4. As soon as the tape has moved into the vacuum columns and starts to move
forward, quickly press RESET.
5. Now press REWIND. This will return the tape to the BOT.
6-10
CP80 TAPE TRANSPORT
6.8 CLEANING THE TAPE TRANSPORT
If the tape transport is to function properly, it must be kept clean. Ail

tape path surfaces, EXCEPT THE CAPSTAN, may be cleaned with a 90% solution or
stronger of isopropyl alcohol, applied with a cotton tipped applicator. The
following is a schedule for cleaning the tape transport.
6.8.1 After Every Eight Hours of Use
1. Clean the heads, guides and suction tape cleaner.
2. With a lint free cloth and 90% solution or stronger of isopropyl alcohol
clean the vacuum columns and plastic cover. Be sure not to leave behind any
lint or shreds of cloth.
3. With water and a clean cloth, wipe and rotate the capstan. Do this until
you no longer pick up any residue on the clean parts of the cloth.
4. Scrub and rotate each of the 4 rotating tape guides until you no longer
pick up any residue on the cloth.
6.8.2 Every Month (After 200 Hours of Use)
1. Dust the entire transport surface.
6 -11
Chapter 7
CPSO Dasher Display Terminal

CHAPTER 7
7.1 INTRODUCTION
The LTX77 system terminal consists of of six major hardware components:
Keyboard Video
Video Monitor Control
Asynchronous Interface Memory
All components except the keyboard are contained in a free standing swivel
mounted cabinet, the keyboard is attached to the video display by a four-foot
cable connected to the back panel. The CP80 terminal is set up by LTX as a 20ma
current loop device
A single processor CP80 can support up to two terminals, a dual processor

CP80 may have as many as four terminals. Because the terminals are set up as a
20ma current loop any terminal ports not connected to a terminal must be
jumpered with a special LTX "dummy" plug.
7.2 SLOT SAVER II
The Slot Saver II board, which is the interface between the NOVA and the
Display Terminal(s), resides in slot 4 of the NOVA. The Slot Saver II selects
the 20ma current loop and 9600 baud rate options for the Display Terminal(s).
The Real Time Clock (RTC) and line printer interface are contained on the Slot
Saver II board. As can be seen in the Slot Saver II board outline in Figure
7-4, the Slot Saver II also has four RS232 multiplexed channels that may be
used.
7.3 TERMINAL/CP80 CONNECTORS
The output from the terminal is brought into the CP80 via a 36 pin cable.
In single processor systems this cable is brought into the CP80 on the right
bulkhead. Systems having only one terminal will use the bulkhead connector
marked "DISPLAY 1". As might be expected, if two terminals are used, the second
terminal is connected to the bulkhead connector marked "DISPLAY 2". In dual
computer systems, the terminals associated with the "Master" computer are
connected to the right bulkhead, and the terminals associated with the "Slave"
computer are connected to the left bulkhead.
7--1
ON/BRIGHT
COMND
RUN GATE BUFFR EDIT DIS TRAP
POWER LINE
_ FUSE
Figure 7-1. Typical CP80 Terminal
7-2
7.4 OVERVIEW
The following is a brief description of the components of the terminal.

The terminal and its interactions are represented in block diagram form in
Figure 7-3.
7.4.1 The Keyboard
The CP80 terminal keyboard is the manual data input device for the system.
The keyboard consists of a typewritter style keypad for data entry, a screen
management keypad for curser control, a numeric keypad, and a user function key
pad. The user function keypad is defined by the LTX operating system and
consists of the following functions: RUN, GATE, Command Buffer EDIT, DISplay,
and TRAP (Figure 7-1). These functions are discussed in the LTX Software
manual.
7.4.2 Video Monitor
The Video Honitor CRT measures 12 inches diagonal ly, with a format of 24
lines by 80 characters per line. The Video Monitor baud rate has been set by LTX
for 9600, there is no parity, and the CRT displays upper case characters only.
Power on/off and screen brightness are control led by a front panel switch
(Figure 7-1).
7.4.3 The Video Boa rd
The Video Monitor consists of a CRT Controller, timing/display logic,

character generator/attribute logic and a video memory. Characters generated by
the Video Board are displayed on the CRT in a 10 x 7 dot matrix. The Video
Board is located in the first board slot to the right of the CRT.
7.4.4 Control Logic Board
The Control Logic Board is located in the second board slot to the right of
the CRT. The Control Logic Board is responsible for determining whether a
character typed on the keyboard is a control or display character. A control
character being a non-displayed character which executes some function (such as
"BLINK ON") with in the DASHER terminal. Curser control is also performed in the
Control Logic Board.
7.4.5 Memory Board
The terminal Memory Board, as the name implies, is responsible for the
storage of characters being displayed on the CRT. The memory board is a 1920
character Dynamic RAM. The 1920 character Dynamic RAM accommodates the 24 line
by 80 character format of the Video Display. The Memory Board is located in the
second slot from the right of the CRT.
7-3
CPSO DASHER DISPLAY TERMINAL
7.4.6 The Asynchronous Interface Board
The Asnchronous Interface board is the communication module of the

terminal. This board controls all of the communication between the terminal and
the NOVA computer. The Asnchronous Interface also translates the serial I/O
from/to the NOVA to the terminal's parallel internal bus. The Asnchronous
Interface Board is located in the fourth board slot to the right of the CRT
7.5 CP80 DISPLAY TERMINAL POWER SUPPLY
The CP80 Display Terminal(s) power supply cords connect directly to either
the left or right CP80 bulkhead connectors. The display power cord plugs into
the the back of the display terminal. Located next to the display power cord on
the back of the display is an AC line fuse. In terminals configured for 208V
this fuse will be rated for 1/2 amp, in 115V terminals this fuse will be rated
for I amp. To determine whether your terminal has been set up for 208V or 115V,
you may remove the plate which supports the incoming power cord and line fuse.
Behind this plate is a small snap-in module. For the system to be set up to the
desired voltage, the snap-in module must be inserted into place in such a way
that the etched on voltage rating that is required is facing out and can be read
by whomever is inserting the module.
The Power Supply provides the required operating voltages for the Processor
board, Video board, and Video Monitor. The Power Supply is located on the inside
rear panel of the display.
As can be seen in Figure 7-2, the terminal power supply generates four
voltages: +5VDC, -12VDC, +15VDC, and a Iow voltage AC to the video monitor.
7-4
CPBODASHERDI_:)LAY TEI_INAL
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7-6
I I I I
._ 0 o TO SET THE 4 CHANNEL I="_'1_ llSeS
._ DATA (NOT CURRENTLOOP) LOgeS

$
_>
[}_ 0lZr MULTIPLEXER

LINE 1 - SJ715
_
AS SERIAL
- OPEN
LINE 2 - SJBD5 - OPEN

sosrs _-ID [_ I _ I_0lBrs
stZe__.lO[_
s0zes_k._j=
OLZPS
t0zrs
00LPS
LINE3 - SJB15
- OPEN TO SET THE 4 CHANNEL
(NOT CURRENT LOOP)

_] MULTIPLEXER ASRS232
LINE 0 - SJ700 - OPEN
LINE 1 - SJ710 - OPEN

SJ701
SJ711 - CLOSED
- CLOSED
SJ801 - CLOSED
LINE
LINE 3
2-- SJ810
SJ800 -
- OPEN
OPEN
SJ811 - CLOSED
CLOSE SWITCH 2
_< TO SETBAUDRATE FOR4 CHANNEL

.__D o0_
_ FORCRT1
CLOSE AND2
SWITCH2 MULTIPLEXER
TO SETBAUDTO
RATE
o TO9600 BAUD 9600BAUD
_,_ _-_ 21 =
= 19.2K
9600 I2 = 19.2K
= 9600
oo ,---,
0 _< 3 = 4800 3 : 4800
O0
U 0_
4= 2400
5: 1200
6= 600
4 : 2400
5 = 1200
6 = 300
_ _< 8 : 110 8 : 110

_<_ 7: 150 7 : 150
o _o Z Z Z :_ -
j 0 7 o 7 o$ D:
( > [ _ 1_J3 I LB] E 3Nil g 3Nil l 3Nil 0 3Nil [ /<./1 -j
* TO SET SECOND CRT SERIAL *** TO SET SECOND CRT SERIAL

PORT DEVICE CODE 50/51 PORT TO DEVICE CODE 50/51
AS A CURRENT LOOP J302 - OUT
J310- OUT J303- IN
J311- IN J304- OUT
J312-IN J305-IN
J306 - IN
NOTE: 303, 305, AND 306
** TO SET CRT SERIALPORT 1 ARE ALREADYJUMPERED
DEVICE CODE lO/ll AS A ON THE BACK SIDE OF
CURRENTLOOP DEVICE CIRCUITBOARDUSING
J204- OUT FOILJUMPERS
J205 - IN
J210 - IN
NOTE: LINE PRINTER DEVICE CODE IS SET BY SOFTWARE
Figure 7-4. Slot Saver II Board Outline
7-7
CRT1 CRT2
-5V -5V
1
3 GROUND GROUND
3
DATAOUTTTO DATAOUTTTO
5 +15V I -I_15V
5
7 7
9 9
Ipl- ! DLATAIN 11_

ee · eeeeell
I
1 77 83
85 _ 1
· · · ee eec e e e ·I e · · eee e e · · ee ·
6 100
A B
NOTE: If any CRT is not connected to the CP80, a shorting

plug MUST be placed on the CRT connection on the CP80 side.
The shorting plug will short pin 3 to pin 11 as shown above.
Figure 7-5. CRT I and 2 to Slot Saver II Wiring Diagram
7-8
Chapter 8
CPSO Line Printer Options

CHAPTER 8
CP80 LINE PRINTER OPTIONS
8.1 INTRODUCTION
There are several line printer options available for the CP80. This
Chapter provides a brief description of some of the more common printers used by
LTX. For a more detailed look at the printer option used on your system, consult
the vendor manual provided with the system.
The printer can receive its AC power from either the left or right bulkhead
connector marked PRINTER (Figure 2-5). Like the AC connector, the printer I/O
cable may be connected to either the left or right bulkhead. The I/O cable
connector is labeled PRINTER.
8.2 TALLY MT1602
The TALLY MT1602 series printer is a desk top serial printer. The MT1602
prints 200 characters-per-second bidirectionally. In bidirectional printing, the
printhead prints a line in a given direction, moves to the nearest end of the
next line to be printed, and prints that line. Up to 132 characters can be
printed on one line using a 10 character per inch format. Because the CRT of the
LTX system terminal is only capable of displaying 80 characters per line, the
line printer uses only 80 character spaces per line.
Paper movement for the TALLY printer is controlled by two dual path
tractors which adjust to accommodate varying paper widths. When the printer is
in the RECEIVE mode and out of paper, a sensor switch activates an audible
alarm and the PAPER OUT indicator. The printer can not be enabled when it is out
of paper.
An inked fabric ribbon is contained in a replaceable cartridge. The

continuous loop ribbon is driven automatically in conjunction with carriage
motion.
The TALLY MT1602 printer is a non Data Channel device. The standard LTX
Slot Saver II controller is used by the NOVA computer to "talk" the computer
over its universal I/O cable.
8-1
CP80 PRINTER OPTIONS
., ,-
Figure 8-1. TALLY NT1602 Printer Option
8-2
Ac
PowE ORMELENGTH ER
800 _ XMOD 1 LF /
_j
OFF MODE
2 FF _) PAu_
Figure 8-2. TALLY MT1602 Operator Control Panel
TABLE 8-1
CONTROLS AND INDICATORS
INDEX CONTROL
NO. INDICATOR FUNCTION
I POWER ON/OFF The printer's main power control. Illuminates POWER

ON indicator. Allow 10 second interval between power
ON and power OFF.
2 PRINT SWITCH ON, printer ON LINE, OFF, printer OFF LINE
3 FORM LENGTH Allows operator to enter form length information.

The 2 thumbwheel switches have a range from 0 to 99
4 LINE FEED/ Momentary movement of this switch will advance the

FORM FEED paper one line or to the next top of form (TOF). By
holding switch in either position, LINE FEED or
FORM FEED will be continuous. Print switch must be
in the OFF LINE condition for LF and FF to be used.
5 POWER ON Illuminates when power is applied to printer.
6 PRINT INDICATOR Illuminates when Print switch in ON LINE position.
7 PAPER OUT Illuminates when there is only 3 inches of paper

left in the paper supply.
8-3
8.3 DATAPRODUCTS PRINTERS
There are three DATAPRODUCTS printer options available for the CP80 system:
2230, 2260, B600. The difference between the three printer options is the number
of lines per minute they print, and how they print characters. The 2230 is an
impact printer and prints 300 lines per minute. The 2260 is also an impact
printer but prints 600 lines per minute. The D600 is a band type printer and
prints 600 lines per minute.
Like the TALLY printer, the DATAPRODUCTS printer can print 132 characters
per line, but because the LTX display terminal only uses 80 characters per line,
only 80 characters per line are printed by the printer.
The tape format option on the DATAPRODUCTS printer is not used by LTX
therefore the tape format light on the control front panel of the printer will
always be illuminated. The fact that this light is on should be ignored by the
user,
The DATAPRODUCTSprinters are Data Channel [DCH) devices and use the
standard LTX Slot Saver II interface. Figure 8-3 is a typical DATAPRODUCTS
printer configuration.
Figure 8-3. DATAPRODUCTS B600 Printer (LP-77)
8-4
] 6
2 7
9
x
4 0
Figure 8-4. DATAPRODUCTS Operator Control Front Panel
TABLE 8-2 CONTROLS AND INDICATORS
INDEX CONTROL
1 POWER Illuminates when power is on.
2 ALARM/CLEAR Illumates during power up or during fault condition.

switch/in- Pressing the ALARM CLEAR switch clears printer logic.
dicator
3 ON/OFF LINE Illuminates when printer is on line. Pressing the switch

switch/in- alternately places the printer on and off line.
dicator
4 LINES per Allow operator to select either 6 or 8 lines per inch

inch switch vertical printing density.
5 TEST switch Three position switch alllows exercising of self test

function. See operator's guide.
6 PHASE Used to maintain equal printing density on left and

control right side of characters.
7 PAPER STEP When actuated, advances paper one line. Printer must be
switch OFF LINE for switch to be active.
8 TOP OF FORM When actuated, advances paper to the top of the next
switch Printer must be OFF LINE for switch to be active.
8-5
CPBO PRINTER OPTIONS
TABLE 8-2 CONTINUED
INDEX CONTROL
9 STATUS Alphanumeric display indicates printer status. Indicates

indicator operation being performed or current fault.
10 COPIES Variable control which al lows printing for single or

control multi-part forms.
For a detailed description of the DATAPRODUCTS printer used on your system,

consult the DATAPRODUCTS manuals provided with your LTX system.
8.4 CPBO System Line Printer Power Supply
Several line printer options are available to the user on the CP80 system.
Because of the extreme differences in their power supplies, individual printer
power supplies will not be covered here. The only descriptions of the CP80 line
printer AC power will be confined to the fact that the AC power for the
printer(s) is supplied through the left and/or right bulkheads. For a detailed
description of your system line printer, consult the printer vendor manual
supplied by LTX.
TABLE 8-3
CP80 PRINTER FUSE LIST
FUSE TYPE USE LOCATION
Tally 1/4A 32V 3AG (Fl) 25V Internal Isolation Board
lA 250V AGC (Fl) 120V Internal Back (Inside)

Data 0.lA 250V AGC Static elim. (60Hz) Back (Inside)
Products or
0.15A 250V AGC Static elim. (50Hz) Back (Inside)
8-6
Chapter 9
The Calibrator
CHAPTER 9
CP80 CALIBRATOR
9.1 INTRODUCTION
The Calibrator is a 19 inch rack-mounted unit located in the lower right

hand section of the CP80. The Calibrator contains the voltage, resistance and
frequency standards for the LTX77 system.
The Calibrator unit is an oven type device which maintains a constant

temperature for the standards housed inside. As described in Chapter 2, the
Calibrator is wired in such a way that even though system power may be off, as
long as the input power is still applied to the system, the Calibrator will
remain on. This is done so that the user will not have to wait for the
Calibrator oven to come up to temperature.
The LTX77 system does not require the presence of a calibrator box while
testing components. The components within the Calibrator are used only when the
system is being calibrated. Removing and replacing the Calibrator does not alter
machine throughput.
LTX recommends that, in order to maintain the accuracy of the LTX77 system,
the calibrator reference unit must be recalibrated every six months. This should
be done according to the procedures outlined later on in this Chapter.
9.2 THE CALIBRATOR
As mentioned above, the Calibrator contains voltage, resistance and

frequency standards. There are twenty precision resistors ranging from 20 ohms
to 10,485,760 ohms in precise steps of two. There are twenty crystal controlled
frequencies from IOMHZ downwards in steps of two. The voltage references are
broken up into two groups. The first group has 24 voltages, 12 positive and 12
negative, in binary steps from IOOV down to 48.828 millivolts. The second set
is comprised of 24 voltages also. This series runs from 12.5V to 6.1035
millivolts. The Calibrator maintains all of these references in its temperature
controlled oven.
9-1
CP80 CALIBRATOR
9.3 CALIBRATOR CALIBRATION
9.3.1 First Level Calibration
Before installation, each calibrator is tested in a metrology lab. At the

metrology lab each resistance, and signal output is measured against laboratory
standards traceable to the National Bureau of Standards. From these measurements
an error table is prepared. This error table is then entered onto tape and the
tape is then loaded onto the LTX77 system disk.
Maintaining the error file constitutes the first level of system

calibration. The published accuracy specifications of the LTX77 system are based
on recalibrating every six months.
m CALIBRATOR METROLOGY LAB

UNIT LAB STANDARDS
OVEN ERROR TABLE
CALIBRATION TAPE
DISK IN COMPUTER STATION
Figure 9-1. Calibration Flow Chart
9-2
CP80 CALIBRATOR
9.3.2 Second Level Calibration
The Metrimax, which is housed in the test station, is used for the second
level of the LTX77 system calibration. The Metrimax (MM) is a 19 bit A/D
converter with binary gain ranges. It can measure DC voltage directly, do point
sampling, make peak-to-peak measurements, and provide a variety of null-based
and averaging measurements
m CALIBRATOR _ METRIMAX
UNIT 1
MASTERCAL NOVA CALIBRATION

TABLEON _ MEMORY .r ROUTINE
DISK (CALPROG ONLY)
I CAL FILE ON DISK I-.,

-'MM CAL TABLE
Figure 9-2. Second Level Calibration
9-3
CP80 CALIBRATOR
2 3 4 6 5 7
Figure 9-3. LTX CP80 System Calibrator
9-5
CP80 CALIBRATOR
9.5 CALIBRATOR DATA FILE INSTALLATION PROCEDURE
The calibrator data file is a list of 69 calibration constants that have

been measured for a single LTX calibrator. It bears the filename 'CALDAT9999',
where '9999' is used as an example for the serial number of the calibrator whose
constants it contains. ('9999' may be from I to 4 digits long. Leading O's are
excluded.
Ex.: CALDAT49
The LTX77 system requires that the data file for the calibrator which is
installed in its computer cabinet be available on the disk in the 'DATA
DIRECTORY'. The source of the calibrator date file is the tape which is shipped
with each newly calibrated calibrator. The contents of that tape must be loaded
onto the disk under any of the following circumstances:
1. Immediately after the LTX software is installed, as described in

Chapter 1
2. Whenever a new calibrator is installed in the system.
3. Whenever, as a result of programmer or operator error, the

calibrator data file on disk is destroyed.
Caution
It is imperative that with each installation, care in the

handling of the calibrator data file tapes is taken. They
serve as the principal backup for the calibrator data files
on their system's disks. Should a calibrator data tape be
damaged, lost or otherwise rendered useless, the procedure
described in section 9.5.2 should be used to immediately
recreate a backup tape.
9.5.1 Loading a Calibrator Data File From Tape
A. Mount the tape containing the appropriate calibrator data file onto
the tape drive, and put the tape drive 'ON LINE'.
B. Load the calibrator data file onto the disk using the following
command sequence.
9-6
CP80 CALIBRATOR
computer Prompts Operator Responses
1. READY TRANSFER/V/R CALDAT9999 [CR]
2. INPUT FROM (D=DISK, T=TAPE)? T [CR]
3. FROM (B=BEGIN), OR FILE NUMBER)? B [CR]
4. RELEASE AFTER TRANSFER (Y OR N)? Y [CR]
5. OUTPUT TO (D=DISK, C=CRT, D [CR]

P=PRINTER)?
6. DIRECTORY (S=SYSTEM, OR NAME)? DATA [CR]
7. CALDATXXXX
On dual-computer CP80 systems, you must go to a terminal controlled by

the other computer and repeat Steps 1-7.
9.5.2 Creating a Backup Calibrator Data File on Tape
A. Mount the tape which is to contain the calibrator data file on the
tape drive, and put the tape drive 'ON LINE'.
B. Store the calibrator data file on the tape using the following
command sequence. (Note that 'CALDAT49' is used below only as an
example. The final characters of the filename should be the I to 4
digit serial number of the calibrator actually in the system.}
1. READY TRANSFER/V/R CALDAT49 [CR]
2. INPUT FROM (D=DISK, T=TAPE)? D [CR]
3. DIRECTORY (S=SYSTEM, OR NAME}? DATA [CR]
4. OUTPUT TO (D=DISK, T=TAPE,

C=CRT, P=PRINTER)? T [CR]
5. WHERE (B=BEGIN, E=END, OR

FILE NUMBER)? B [CR]
9-7
CP80 CALIBRATOR
6. RELEASEAFTER TRANSFER(Y OR N)? Y [CR]
7. CALDAT49
READY (No responserequired)
C. Label the tape. Store it safely away where it will be available at

any future time when that calibrator data file must be instal led
again (such as after instal lation of the next release of the new
LTX system software),
9-8
CP80 CALIBRATOR
9.6 CALIBRATION PROCEDURE
9.6.1 Measurement of LTX Calibration Reference Unit
LTX recommends that in order to maintain the accuracy of the LTX77

software calibration system, the calibration reference unit be recalibrated
every six months. This should be done using the procedure outlines in the
following pages, whether at an outside calibration laboratory or an in-house
NBS traceable lab.*
The essential part of calibrator measurement and recalibration is the

measuring of the calibration system's internal DC voltages, resistance
standards and its 10 MHz frequency standard. These standards are contained in
a temperature-stabilized oven in the calibrator reference unit, located in the
lower part of the right side of the computer rack. Figure 9-4 shows how the
calibrator is connected to the test stations via the station CAL bus. All
measurements should be made with the calibrator reference unit disconnected
from both the CAL bus and the data bus.
LTX uses measured values for these standards to prepare the calibrator
data file which enables each calibration reference unit to act as the reference
for LTX77 software calibration. Due to the high precision of the reference
standards, there are some measurement procedures which will not give accurate
results:
Measuring the calibrator's DC voltages with a conventional DVM

or voltage divider/potentiometer would result in substantial
errors, due to the considerable source impedances of the voltages
to be measured.
The reference unit's four-terminal resistance standards are

connected to the measuring terminals (the black and red banana
connectors at the back of the reference unit box) through switch
contacts and lead resistances which are beyond the range of
four-wire-lead-compensated bridges.
Inadequate resolution and time base stability prohibit the use of

crystal-controlled frequency counters for the measurement of the
frequency standard.
* LTX offers an exchange calibration service. Contact your nearest field

service office for details.
9-9
CP80 CALIBRATOR
9.6.2 Required Equipment For LTX Calibrator Calibration
1. Primary voltage potentiometer system with 100 volt input divider
Julie Research Labs PVP - 1000C 4ppm Accuracy

(or equiv.) VDR - 307 0.1 ppm Resolution
SCO - 106
ND - 106
2. Adjustable Voltage Source
Fluke 343 A O-IO00V

(or equivalent) O-25mA
_.0002% Regulation
.1 ppm Resolution
3. Adjustable Voltage Source
Fluke 341 A O-IOOV

(or equivalent) O-25mA
_.O005%/HR Stability
4. Standard Resistor Set
Guildline Model 9330 Four Terminal

(or equivalent) .O01%/Year
10 Ohm, 100 Ohm, 1K Ohm, 2 ppm/°C
1OK Ohm, lOOK Ohm 0.1 Watt
5. Guarded DC Null Detector
Julie Research Labs 0.2 microvolt sensitivity

(or equivalent) ND-lO6 300V Isolation
6. Frequency Measurement System
Rhode and Schwartz Rubidium Oscillator XSRM

(or equivalent) Phase Comparator XSRM-Z3
Power Supply XSRM-Z
-11
2x10 /Month Stability
7. Miscellaneous
Low Thermal EMF copper wire with teflon insulation. BNC cable
with 50 Ohm terminator.
9 -10
CP80 CALIBRATOR
9.6.3 Calibration Conditions, Limits, Records
1. Environmental Conditions:
Temperature 23°C +_ 3°C

Relative Humidity Less than 70%
2. Acceptance Limits: (Deviation from nominal)
+_0.15% _+0.02 Ohm Resistance
+0.15% +_0.2rev Vol tags
+5X10-7 Frequency
Stability/6 mos. +_0.01% +_0.2mV Voltage

+0.01% +-0.02 Ohm Resistance
-7
+1xlO Frequency
3. Records:
A. Record each measurement on the calibration measurement data sheet.
B. Indicate polarity of voltage measurements.
C. Data must be clearly legible with decimal point location as indicated

on the form.
D. Fill all spaces on the form. Enter leading zeros if required.
4. Data Entry:
A. On any head of any LTX system, run the calibrator data entry program
CALDATA.LX. Enter the data from the measurement data sheet as
instructed by the program.
B. Return the completed measurement data sheet to LTX Systems

Engineering for advice and consultation. By returning the data sheet to
LTX a calibrator history can be developed.
9 -11
CP80 CALIBRATOR
FRONT
COMPUTER
RACK
OUTPUTA OUTPUTB
CAL CAL
F ]A2 STATION STATION F::t
A1
CALI
AC_AL
X_ IMMII I M_ __LI
b:ICA
L LJCAL
A1 A2
CAL CAL
F 1A2 STATION STATION F -I
A1
CALI
I ICAL
_CAL _--_
CAL
A1 A2
Figure 9-4. Calibrator Connection Diagram
9-12
CP80 CALIBRATOR
9.6.4 Measurement Procedure
I. Plug the calibrator into AC power. Note that the lower connector is for
115V +_15% 50-60Hz, and the upper connector is for 230V +--15% 50-60Hz.
2. Turn the power on and wait until the NG light is extinguished and both OK
lights are on, then wait an additional hour.
3. Set the AC/DC switch to the AC position. Push all the other toggle
switches up, and push the LOAD button. Push all the toggles down, and push
the LOAD button again. Repeat with the AC/DC switch at the DC position.
4. Refer to the calibration measurc:ment data sheet. Set the switch settings
to those tabulated for the 20 nominal value, push the LOAD button. Measure
the resistance using the method described under "Resistance Measurement"
Record the measured value on the CMO sheet.
5. Measure and record each resistance value tabulated on the CMD sheet. (See
"Resistance Measurement".)
6. Measure and record each of the voltage values tabulated on the CMD sheet.
(See "Voltage Measurement".)
7. Measure and record the IOMHz output signal. (See "Frequency Measurement")
9-13
CP80 CALIBRATOR
9.6.5 Resistance Measurement
1. Connect equipment as shown in Figure 9-5. Use only Iow thermal EMF
copper wi re.
2. The LOF (Low Force) terminal of the calibrator must be connected to

power line ground (earth). No other signal common point in the system
may be grounded.
3. s. Wire exactly ss shown in Figure 9-5. Substantial errors will result

if the current wires are not separate from the voltage sense wires.
b. Do not install a switch or other remote terminal device connected to

the voltage points El, E2, or E3.
c. The positive input wire of the null detector sheuld be shielded. The
detector should be shielded. The shield should be insulated from the
conductor and from ground, and connected to the Guard terminal of the
null detector. The Guard terminal should be connected to the input
of the null detector. Leakage resistance as Iow as 10 ohms will shunt
the resistor under test if not properly guarded.
4. Thermal EMF Correction:
a. With the positive terminal of volt source I disconnected,connect

the null detector to EI.
b. Set the potentiometer to measure less than I volt, and set the
calibrator to the nominal 20 output. Measure the voltage at E
and record it on the resistance work sheet (page 4 of the CMD
sheet) as E1A.
c. Repeat at nominal resistance settings up to 20.48K Ohm.
NOTE: Above 20.48K Ohm, EIA may be considered to be zero.
5. To measure E1B , E2, E3:

s. Set voltage source I (Fluke 341A) to the nominal value in Table 9-1.
b. Set voltage source 2 (Fluke 343A) to the nominal value of E1B, E2, or
E3-
c. Connect the null detector and adjust voltage source 2 for a null
indication.
d. Measure the absolute value of volt source 2 with the primary

potentiometer system. Use the input range of the primary
potentiometer which will give maximum resolution.
e. Apply calibration correction factors to the result obtained in D.
f. Record the value of E1B on the resistance work sheet.
9-14
CP80 CALIBRATOR
6. To calculate resistance value: EI=(E1B- E1A)
a. Measure E3, E2, E1B, then E again. Verify that voltage source I has
not changed during the measurement period.
b. Use the calibrated value of the standard resistor and the corrected
value of E 1, E2, and E 3.
E1
RX -
(
E3- E2 )
RSTD
NOTE:
Use the corrected value of E from the work sheet.
9 -15
CP80 CALIBRATOR
hi m
_ W
4- I
h.i
\
- ,_I- i- _ z E
m X
-m- (D o uJ .em
.u I1'
' 4J
,
I
_ ,'3, _ E
m
O _.
/f,.
! ,
! .+.
! ._ ,..._"_-"_ ..,
---J ' I_1___ a3

--- _ _,-,zo=,=
(%1' II 4=1
CO
_z x ffi
0::: 'F_
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...J _
z _ I
° g _ ,-
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oo ,;, o
_-§_
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0 _ m
12217
9-16
CP80 CALIBRATOR
TABLE 9-1. RESISTANCE MEASUREMENT
I
Calibrator Volt E Standard
Nominal Source 1 Nominal Resistor
Resistance Setting Value
20 0.5 Volt .3333V 10

40 0.5 Volt .400V 10
80 I Volt .4444V 100
160 I Volt ! .6153V 100
320 3 Volts .7619V 100
640 3 Volts 1.1701V 1K
1.28K 3 Volts 1.684V 1K
2.56 10 Volts 2.157V 1K
5.12 10 Volts 3.386V 1OK
10.24 10 Volts 5.059V 1OK
20.48 30 Volts 6.719V 1OK
40.96 30 Volts 24.11V 1OK
81.92 100 Volts 13.509V lOOK
163.84K 100 Volts 62.098V lOOK
327.68K 100 Volts 76.618V lOOK
9.6.6 Voltage Measurement
1. Remove the standard resistor and voltage source I (Fluke 341A).
2. Set voltage source 2 (Fluke 343A) to the nominal calibrator output

voltage from the "Nominal" column of the CMD sheet.
3. Connect the null detector to E , and adjust voltage source 2 for null.
4. Measure voltage source 2 (absolute value) with the primary

potentiometer and apply calibration correction.
Calibrator output = Voltage source 2
5. Calibrator output voltage less than I volt may be measured directly by

the potentiometric input of the primary potentiometer.
NOTE:
Do not connect the I volt "volt box" input directly to the

calibrator output. See Figure 9-6.
6. Reverse the polarity of voltage source 2 and switch the potentiometer

to V.B. to measure the negative outputs of the calibrator.
9-17
CP80 CALIBRATOR
_-wn
00_
-Jmo
/0__ zo
o
1¢)
0
,-.,
m
02 o
>
Oo 0 0
D_.. 0
_-- 1.0 L
-- Ili
xF--- 0©
- _'
E
OC_ o
_,,, 0_o _-
,..n_
ot w 0 T--,
4._
m
> O- o
0 I'-- _,
o _
_o
S
o
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&
t_
-
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o.
Oz > > -
f.,..9 r'_
,f,
/01 m
r
mx OIm
z_ 0+_-
00 "'
t'_
0.-.· OI >
O_
bdo_._ _j _ 0
I---- _
0 I.-.-
m_ 0+_
r'r' 0..
F,z
12218
9-18
CP80 CALIBRATOR
9.6.7 Frequency Measurement
1. Set the AC/DC switch on the calibrator to AC.
2. Set switch 10 UP, all others DOWN. Push the LOAD button·
3. Connect the calibrator AC output {BNC connector) to the frequency

measurement system, as shown in Figure 9-7.
NOTE:
The 50 Ohm terminator is required at the phase comparator
input terminal.
4. Determine and record the calibrator oscillator frequency within

I X 10 -9
5 MHZ STD SIGNAL
XSRM XSRM-Z XSRM-Z$

RUBIDIUM OSCILLATOR POWER SUPPLY PHASE COMPARATOR
ti III I I I
0
\ /
0 -'(D ,o M.z
5M.z 0 _ 05o_n_
/% TERMINATOR
CALIBRATOR OUTPUT
I0 MHZ
Figure 9-7. Frequency Measurement System
9-19
CP80 CALIBRATOR
CALIBRATOR MEASUREMENT DATA
Date: Serial #:
Time of Measurement: Measured by:
Location:
Resistance Standard:
Last Calibrated:
Voltage Standard:
Last Calibrated:
Frequency Standard:
Last Calibrated:
Measurements Traceable To:
Ambient Temperature: Relative Humidity:
R Light On X Light On NGLight Off
Time Waited After NG Light Off
Measurements Certified By:
9-20
CP80 CALIBRATOR
CALIBRATOR MEASUREMENT DATA SHEET
Date:
Serial #:
Switches Indicated are UP:
i_ DC 0 I 2 10 11112 13 14 15 Nominal Actual Test

I
I DC 20_* *I 1
2 DC 15 40_* * 2
3 DC 14 80F_
* * 3
4 DC 1415 160_ 4
5 DC 13 320_ 5
6 DC 13 15 640_ 6
7 DC 1314 1280_ 7
8 DC 131415 2560_ 8
9 DC 12 5120_ 9
10 DC 12 15 10240_ 10
11 DC 12 14 20480_ 11
12 DC 12 1415 40960_ 12
13 DC 1213 81920_ 13
14 DC 1213 15 163840_l 14
15 DC 121314 327680_ 15
21 DC 1 12 1415 +100
V + 21
22 DC i 12 14 +50V 22
23 DC i 12 15 +25V 23
24 DC I 12 +12.5
V 24
25 DC 1 131415 +6.25
V 25
26 DC i 1314 +3.125
V 26
27 DCi I 13 15 +1.
5625
V 27
28 DC i 13 +.78125
V 28
29 DC i 1415 +.390625
V 29
4
30 DC i 14 +.195313
V 30
31 DC I 15 +.097656
V 31
32 DC I +.048828
V 32
33 DC0 i 12 1415 -100
V 33
34 DC0 i 12 14 -50V 34
35 DC0 1 12 15 -25V 35
Indicate Polarity--
9-21
CP80 CALIBRATOR
CALIBRATOR MEASUREMENT DATA SHEET
Date:
Serial #:
Indicate Polarity-
3_66
DC0 i 12 Nomi
na
1V -
-12.5 Actual Test
36
37 DC!O1 131415 -6.25
V 37
38 DC0 i 1314 -3.
125V 38
39 DC0 I 13 15 -1.
5625
V 39
L
40 DC0 I 13 -.78125
V 40
i41 DC0 i 1415 -.390625
V 41
42 DC0 i 14 -.195313
V 42
43 DC0 1 15 -.097656
V 43
!44 DC0 i -.048828
V 44
45 DC i 2 12 1415 +12.5
V 45
46 DC 1 2 12 14 +6.25
V 46
47 DC i 2 12 15 +3.125
V 47
48 DC 1 2 12 +1.
5625
V 48
!49 DC I 2 131415 +.78125
V 49
50 DC i 2 1314 +.390625
V 50
51 DC I 2 13 15 +.195313
V 51
52 DC 1 2 13 +.097656
V · 52
53 DC i 2 1415 +.048828
V !
53
m54 DC I 2 14 +.024414
V !
54
55 DC 1 2 15 +.012207
V 55
56 DC i 2 +.006103
V 56
57 DC0 i 2 12 14)15 -12.5
V L 57
58 DC0 i 2 12 14 -6.25
V I 58
59 DC0 I 2 12 15 -3.
125V 59
60 DC0 i 2 12 -1.5625
V 60
61 DC0 i 2 131415 -.78125
V 61
62 DC0 1 2 1314 -.390625
V 62
63 DC0 1 2 13 15 -.195313
V 63
64 DC0 1 2 13 -.097656
V 64
65 DC0 1 2 1415 -.048828

V m 65
66 DCiO1 2 14 -.024414
V , 66
67 DC0 1 2 15 -.012207
V 67
)
68 DClO
I 2 -.006103V 68
69 ACi 10 10000000 HZ ' i 169
Enter leading zero if required._
9-22
CP80 CALIBRATOR
RESISTANCE WORK SHEET
Date:
Serial #:
Nominal EiA EIB E1 corrected Calibrated

(ThermalOffset) (VoltageDrop) (EIB- EIA) value of R std.
20_
40_
80_
160_
320_
640_
1280_
2650_
5120_
10240_
20480_
40960_
81920_
163840_
327680_
9-23
Chapter 10
Optional Array Processor

CHAPTER 1 0
CP80 OPTIONAL ARRAY PROCESSOR
10.1 INTRODUCTION
The LTX77 system has an optional model AP894 Array Processor which performs
calculations involving arrays many times faster than they could be executed by
the NOVA. The arrays to be used in the calculations must be created and filled
within an LTX-BASIC program.
The CP80 optional Array Processor is a 19 inch rack mounted unit housed
just below the the magnetic tape unit. In Dual computer CP80 systems two Array
Processors may be used. When an Array Processor is present in a system, it is
associated with only one computer. Should a CP80 Dual Computer system be
configured with only one Array Processor, only one of the computers, either the
"Slave" or the "Master" can communicate with the Array Processor. It is
incumbent upon the programmer to determine which of the two computers is
connected to the AP894, and to assure that test programs which rely on the AP894
for computations are run only on that computer.
NOTE
Special jumpers are required on the backplane of the NOVA

when an Array Processor is installed. These jumpers differ
according to NOVA memory size. Should the user change the
memory configuration of a system which uses an Array
Processor, contact LTX Field Service.
As discussed in Chapter 2, the Array Processor{s) plug directly into P5 of

the AC Distribution Box.
The CP80 Array Processor Interface, which allows the NOVA to communicate
with the AP894 over an I/O cable, is found in slot 6 of the NOVA.
10.2 CP80 BURST INTERFACE
It is recommended that systems incorporating array processors also include

the CP80 Burst Interface. The Burst Interface will allow significant improvement
in data transfer rates between the test station and the computer. Located in
slot 9 of the NOVA, the Burst Interface replaces the CP80 Interface board.
10-1
CP80 OPTIONAL ARRAY PROCESSOR
Figure 10-1. AP894 Showing Status Register Indicators
10-2
LTX TECHNICAL PUBLICATIONS PRICE LIST 6/15/83
DOCUMENTATION PACKAGES. [,TX PARTNO. I UNIT PRICE

LTX77 MAINTENANCEPACKAGE- (includes 999-2010 $ 100 per set
CP80 & Test Station manuals, DTOS
Diagnostic manual, LTX Diagnostic
Programs, & LTX-BASIC Pocket Guide)
LTX77 APPLICATIONS PACKAGE- (includes 999-2020 $ 100 per set
LTX Software Manual, LTX Diagnostic
Programs, & LTX-BASIC Pocket Guide)
DATA GENERALDOCUMENTATIONPACKAGE 999-2050 $ 125 per set
(includes all D.G. manuals below)
LTXMANUALS I LTXPARTNO, I UNIT PRICE

LTX77HARDWARE MANUAL 999-6010 $ 50 each
TS88 HARDWAREMANUAL 999-6100 $ 50 each
LTX DIAGNOSTICPROGRAMS 999-6120 $ 25 each
LTX77SOFTWARE MANUAL 999-6210 $ 75 each
DTOS 999-6220 $ 25 each
LTX-BASICPOCKETGUIDE 999-6230 $ 5 each
DX90SOFTWARE MANUAL 999-6500 $ 50 each
DX90 MAINTENANCEMANUAL 999-6510 $ 50 each
DX89MANUAL 999-6410 $ 50 each
CX80MANUAL 999-6420 $ 50 each
LX84 LASER MANUALVOLUMESI & II & III 999-6430 $100 per sat
FBI700 APPLICATIONS MANUAL I 999-0001 I $ 25 each

FBI780 APPLICATIONSMANUAL I 999-0004 I $ 25 each
2910/11 TEST PACKAGE I 999-0005 I $ 25 each
STANDARDAPPLICATIONS PACKAGES(IND.) I 999-0006 I N/A
PRODUCTENGINEERSHANDBOOK I 999-4010 I $ 25 each
DATA GENERAL MANUALS I LTX PART NO, I UNIT PRICE

NOVA3 TECHMANUAL 999-6801 $ 10 each
NOVA 3 IPB 999-6802 $ 10 each
NOVA3 SCHEMATICS VOL I 999-6803 $ 10 each
CRT DISPLAY SCHEMATICSVOLUMEII 999-6804 $ 10 each
TAPE DRIVE SCHEMATICSVOLUMEIII 999-6805 $ 10 each
RDOS/DOSCLI 999-6806 $ 10 each
SUPEREDIT 999-6807 $ 10 each
6020 TAPEFS PROCEDURES 999-6808 $ 10 each
6020 TAPEIPB 999-6809 $ 10 each
6052 DISPLAYTECH. REFERENCE 999-6810 $ 10 each
6052 DISPLAY IPB 999-6811 $ 10 each
6052 DISPLAYTECH. MANUAL 999-6812 $ 10 each
COMPONENTS GUIDE 999-6813 $ 10 each
6020 TAPE TRANSPORTTECH. MANUAL 999-6814 $ 10 each
MISCELLANEOUSMANUALS . J LTX PART NO, I UNIT PRICE

CDCMINI MODULE DRIVE THEORY 999-6851 $ 10 each
CDC MINI MODULEDRIVE MAINTENANCE 999-6852 $ 10 each
CUSTOM SYSTEMSSLOTSAVERII 999-6861 $ 10 each
CUTSOMSYSTEMSMEMORYEXPANSIONUNIT 999-6862 $ 10 each
INTERSIL SEMICONDUCTORMEMORYMANUAL 999-6871 $ 10 each
SPECTRA10 REFERENCE MANUAL 999-6881 $ 10 each
* These manuals are not yet available.

I
I LTX CORPORATION
LTX Park et University Avenue
I Weatwood, MA 02090
I TECHNICAL PUBLICATIONS ORDERFORM
I
j Name:
Title:
I
Company:
I Mai I Stop:
I Company
Add reas:
UNIT QUANTITY TOTAL

MANUALTITLE LTX PART NO. PRICE REQUESTED PRICE
I CHECK ENCLOSEDFOR THE FOLLOWINGAMOUNT $
I NOTE: All orders MUST be accompanied by a check.
I
i
I
!
LTX Park at University Ave,
L__( Westwood,
LTX MA02090
CORPORATION TWX:617-329-7550
Phone: 710-348-6621
ADDITIONAL LTX OFFICES
LTXCorporation LTXCorporation
LTX Park at University Avenue 508 Southway Boulevard East
Westwood, MA 02090-2306 I(okomo, IN 46902-3820
Phone: [617) 329-7550; FAX: (617) 329-8664 Phone: 317-455-2010
LTX Corporation* LTX Europe, Ltd.*

2330 Welsh Avenue LTX House, Church Street
Santa Clara, CA 95051-1367 Woking, Surrey GU21 1HA; United Kingdom
Phone: 408-727-1212; TWX: 910-338-0253 Phone: 4862-22322; TLX: 851-859-105 LTXEURG
FAX: (4(]8 ] 748-9537
LTX (France), S.A.*
LTX Corporation 9 Avenue
St. deHour;
DianeFrance
94180
2425
Suite North Central Expressway Phone: 1-889-5240; TI.X: 842-212-056 LTXFRAN
432
Richardson, TX 75080-2714
Phone: 214-680-0825; TWX: 73364 KPSASI DAL Attn:33T LTX (DeuTschland) GmbH*
Alfelder Strasse 56
LTX Corporation 3208 Hi I desheim; Federal Rep. of Germany

807 Winter Wood Drive Phone: 5121-41051; TLX: 841-927-176 LTXHID
Matthews, NC 28105
Phone: 704-847-0475 LTX (Deutschland) GmbH*
Hans-PinseI-Strasse 9-10
LTX Corporation 8013

Phone:Haar Bei Muenchen; Federal RepubLTXMD
I ic of Germany
8946-4027; TLX: 841-521-6887
2300 Maitland Center Parkway
Suite 125
Mai t Iand, FL 32751-4150 LTX Japan Company, Ltd.*

Phone: 305-660-2848; TWX: 810-853-0301 LXFL MAIT P.O. Box 6068 Shinjuku Bldg.
2-4-1 Nishi Shinjuku
LTX Corporation Shinjuku-ku, Tokyo 160; Japan
3200 North Hoyden Road Phone: 03-342-1488; TWX: 2324104 LTXKKJ
Suite 100
Sccttsdale, AZ 85251-6625 LTX Corporation, Southeast Asia Support Center

Phone: 602-945-0322 ; TYD(: 910-950-1316 LTX Corporation Seasi8
FAX: 602-945-0221 5000 Ang Mo Kio Ave 5, #04-09
LTX Corporation Singapo re OF
2056
REPUBLIC SINGAPORE
1030 West Higgins Road Phone: [65) 4818480 TWX: RS 34133 LTXSEA
Suite 107
Hoffman Estates, IL 60195-3206
Phone: 312-662-1602; TWX: 910-997-0125 _Tratning and Services Support Centers
U.S. SALES REPRESENTATIVES
AWl,Inc. L&MSales
1495 Garden of the Gods Road, Suite 108 4 Glen Street
Colorado Springs, SO 80907 Marlboro, MA 01752
Phone: 303-594-0545 Phone: 617-481-1910; TWX: 710-347-0154
AWl, Inc. L&M Sales

405 Southwey Boulevard East; Suite 207 1209 Clearfield Read
Kokeme, IN 46901 Nazareth, PA 18064
Phone: 317-453-7671; TWX: 272-328 AWI KOKO Phone: 215-759-9534; TVO(: 510-651-2625
AWl,Inc. Microtek Sales

616 Hardin Street 22762 Aspen Street, Suite 210
Findlay, OH 45840 El Toro, CA 92630
Phone: 419-424-1954 Phone: 714-770-3059; TWX: 910-595-2508
INTERNATIONAL SALES REPRESENTATIVES
Electronic Instruments nv-sa Yeonil Co., Ltd.

101 Avenue Siegers #498-5, Depsi pri-Dong Dongdaemoon-ku
1200 Brussels; Belgium K.P.O. Box 1437
Phones: 02-770-55-00/762-77-53; TLX: 21981 JCLAES B Seoul, Korea
Phone: 244-0475 or 244-6745; TLX: 787-241-23
Negocios De Telecomunicacion y Electronica SA

Dracena 38 Macrotek AB
Madrid 16; Spain Vallingbyvegen 212 Box 43
Phone: 457-70-04; TLX: 843-463 76 16211 Val lingby; Sweden
Phone: 08-87 94 90; TLX: 12543
Dott. lng. Guiseppe De Mico S.P.A.

Viale vittoria Veneto 8, Cassina De'Pecchi
20060 Milano; Italy
Phones: 95-20-551/39-95-20-651; TLX: 330869
Printed in U.S.A.
LTX CORPORATION
LTX Park at University Avenue
Westwood, MA 02090

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CP80

LTX Part #: 999-6020

Data General Corporation

Mannesmsnn Ta!ly Corporation

Control Data Corporation

Intersil Systems Corporation

Spectra Logic Corporation

Custom Systems Inc

SECTION TITLE PAGE

1,1 OBJECTIVE .......................... 1-1

2,1 INTRODUCTION ......................... 2-1

3.1 INTRODUCTION ......................... 3-1

4.1 INTRODUCTION........................ 4-1

5.1 INTRODUCTION ......................... 5-1

5.9 CREATINGA DATA FILE BACKUPTAPE (DISK TO TAPE) ....... 5-27

7.1 INTRODUCTION ......................... 7-1

8.1 INTRODUCTION......................... 8-1

9.1 INTRODUCTION ......................... 9-1

10,1 INTRODUCTION........................ 1 0-1

FIGURE TITLE PAGE

1-1 CP80 DUAL COMPUTER

2-1 CP80 AC POWERDISTRIBUTION DIAGRAM.............. 2-1

3-1 DUAL COMPUTERRACK DIAGRAM.................. 3-1

4-1 NOVA3 SLOT LOCATIONS ..................... 4-3

5-1 MINI MODULE HEAD/DISK CONFIGURATION ............. 5-1

6-1 CP80 TAPE DRIVE UNIT ..................... 6-2

7-1 TYPICAL CP80 TERMINAL .................... 7-2

8-1 TALLY PRINTER OPTION.................... · 8-2

9-1 CALIBRATION FLOWCHART.................... 9-2

2-1 CP80 CIRCUIT BREAKERS ................... 2-3

3-1 CP80 DEVICE CODES...................... 3-12

4-1 ADDRESSINGFOR INTERSIL ME128 MEMORY{0 TO 128K). ...... 4-4

5-1 READ DRIVE STATUSWORDBIT CHART............... 5-6

8-1 TALLY CONTROLSAND INDICATORS ................ 8-3

9-1 RESISTANCE MEASUREMENT

The LTX77 Automatic Test System performs high-speed precision tests on

Figure 1-1 CP80 Dual Computer System

1.3 LTX77 POWER-UP PROCEDURE

1. Turn on power at the computer rack by pressing both 'STATION' and

NOTE: On the CP80, the circuit breakers are behind the

Data rate: 9.6K

1.4 BOOTING THE LTX OPERATING SYSTEM

Computer Prompts Operator Responses

3. LTX OPERATING SYSTEM

NOTE: When entering the date, either slashes or spaces may

4. TIME: {H:M:S)? 13:45:30 [CR] (For

NOTE: When entering the time, Either colons or spaces

On dual computer CP80 systems, the CRT of the slave

5. LTX OPERATING SYSTEM XX/XX/XX

NOTE: On dual computer CP80 systems, the last message

I .5 MANUALLY BOOTING THE LTX OPERATING SYSTEM

1.5.1 Manually Booting a Single Processor

1. Elevate RESET on the NOVA 3 console.

2. Set data switches 0 thru 15 to octal 000376.

3. Elevate the MEMory EXAMine switch.

4. Set data switches 0 thru 15 to octal 601XX.

A. XX = 22 if you are booting from the tape drive.

B. XX = 27 if you are booting from the disk.

5. Elevate the MEMory DEPosit switch.

6. Set the data switches 0 thru 15 to octal 000377.

7. Press the DEPosit NEXT switch.

8. If you are booting from the disk you must:

A. Set the data switches 0 thru 15 to O.