Analog Integrated Circuits and Signal Processing

Lossless grounded admittance simulator using OTRA

--Manuscript Draft--

Manuscript Number: ALOG-D-18-00503R1

Full Title: Lossless grounded admittance simulator using OTRA

Article Type: Mixed Signal Letter

Keywords: Inductance simulator; FDNR simulator; Capacitance simulator; Operational

transresistance amplifier; integrated circuit

Corresponding Author: Sajal K. Paul, Ph.D.

Indian Institute of Technology (ISM)
DHANBAD, JHARKHAND INDIA

Corresponding Author Secondary

Information:

Corresponding Author's Institution: Indian Institute of Technology (ISM)

Corresponding Author's Secondary

Institution:

First Author: Bal Chand Nagar, Ph.D.

First Author Secondary Information:

Order of Authors: Bal Chand Nagar, Ph.D.

Sajal K. Paul, Ph.D.

Order of Authors Secondary Information:

Funding Information:

Abstract: In this paper, a generalized admittance simulator is presented. The proposed circuit
uses two operational transresistance amplifiers (OTRAs), one voltage buffer and three
passive components. The proposed generalized admittance simulator can realize three
simulators namely lossless grounded positive inductance simulator, frequency
dependent negative resistance (FDNR) simulator and capacitance simulator/multiplier
without any matching constraint. The non-ideality analysis of the circuit is also given.
The workability of the proposed admittance simulator is shown through the
implementation of second order band pass filter using inductance simulator, second
order low pass filter using FDNR and variable capacitance low pass filter using
capacitance multiplier. PSPICE simulation results are included to verify theory.

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Response to Reviewer Comments

Responses to reviewers’ comments

Reviewer #2:
First of all may I gratefully appreciate your invaluable suggestions/comments in improving the
quality of our article. The responses to your observations and suggestions are as follows:

1. Page-12, line-2 there seems some typo error, please modify.

Response: As per your advice typo errors has been modified in the revised manuscript.
[Section 5, page 12, line below equation (30)]

The authors are gratefully appreciating your invaluable comments and believe that your kind
contributions have certainly helped us to enhanced the quality of the manuscript.

Yours sincerely
Sajal K. Paul
Reviewer #3:
First of all may I gratefully appreciate your invaluable suggestion/comments in improving the
quality of our article. The responses to your observations and suggestions are as follows:

1. The proposed study is related to a circuit using the transresistance amplifier and presents an
admittance simulator circuit on the basis of the rule deux ex machina. No systematic synthesis
technique is provided. Additionally, the analysis of the proposed circuit is limited to the
statement that the routine analysis of the circuit gives the desired effect. However, it would be
interesting what models were used and what simplifications were made.
Response: As per your advice, the analysis of the proposed circuit of Fig. 2 is given below:

Fig. 2 The proposed lossless grounded admittance simulator

The input currents of OTRA1 are given by
𝐼𝑛1 = 𝐼𝑖𝑛 (1)
𝐼𝑝1 = 𝑉0 𝑌2 (2)
In an OTRA ideally, the Rm approaches infinity and hence forces input currents Ip and In to be
equal. Hence we can write
𝐼𝑝1 = 𝐼𝑛1 (3)
𝐼𝑖𝑛 = 𝑉0 𝑌2 (4)

Similarly, from OTRA2 we can get

𝑉𝑖𝑛 𝑌1 = 𝑉0 𝑌3 (5)

From (4) and (5), we get the expression for the input admittance as
𝐼𝑖𝑛 𝑌1 𝑌2
𝑌𝑖𝑛 = = (6)
𝑉𝑖𝑛 𝑌3
2. P.S. In the study we have two Figure 2 and no one Figure 3.
Response: Yes, this is typo mistake. As per your advice the Figure numbers have been modified
in revised manuscript. [Section 2, page 4 (Fig. 2) and page 6 (Fig. 3)]

The authors are gratefully appreciating your invaluable comments and believe that your kind
contributions have certainly helped us to enhanced the quality of the manuscript.

Yours sincerely
Sajal K. Paul
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Lossless grounded admittance simulator using OTRA

1
2
3
Bal Chand Nagar1 and Sajal K. Paul2
4
1
5 Department of Electronics & Communication Engineering, National Institute of Technology Patna, Ashok
6
Rajpath Patna, Bihar, India, 800005.
7
2
8 Department of Electronics Engineering, Indian Institute of Technology (Indian School of Mines), Dhanbad,
9
10 Jharkhand, India, 826004.
11 sajalkpaul@rediffmail.com, balchandnagar@gmail.com
12
13
14 Abstract: In this paper, a generalized admittance simulator is presented. The proposed circuit uses two
15
16 operational transresistance amplifiers (OTRAs), one voltage buffer and three passive components. The proposed
17 generalized admittance simulator can realize three simulators namely lossless grounded positive inductance
18
19 simulator, frequency dependent negative resistance (FDNR) simulator and capacitance simulator/multiplier
20 without any matching constraint. The non-ideality analysis of the circuit is also given. The workability of the
21
22 proposed admittance simulator is shown through the implementation of second order band pass filter using
23 inductance simulator, second order low pass filter using FDNR and variable capacitance low pass filter using
24
25 capacitance multiplier. PSPICE simulation results are included to verify theory.
26
27
28 Keywords: Inductance simulator, FDNR simulator, Capacitance simulator, Operational transresistance
29 amplifier, Integrated circuit.
30
31
32 1. INTRODUCTION
33
34 Recently, a lot of effort has been devoted by researchers to the design of the operational transresistance
35
amplifier (OTRA) and circuit based on it. The ideal OTRA is insensitive to parasitic capacitances due to
36
37 internally grounded input terminals. It can provide a high gain, high bandwidth and slew rate unlike traditional
38
operational amplifier [1-6]. Literature survey reveals that an OTRA is used for a number of signal generation
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40 and processing applications such as active simulators [7-16], oscillators [17, 18], filters [19], multivibrators [20],
41
schmitt trigger [21], PID controller [22] and rectifiers [23] etc.
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43 Active simulators such as inductors, frequency dependent negative resistors (FDNRs) and capacitance
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45 simulators/multipliers are useful elements for designing a wide range of circuits such as active filters,
46 oscillators, phase shifters, cancellation of parasitic element and impedance matching. During the last few years
47
48 many active simulators are proposed using OTRAs [7-16]. Most of these are inductance simulators. Only few
49 simulators [11, 12] are multi-functional. All these simulators use matching constraints and more than three
50
51 passive components.
52 In this paper a new lossless grounded general multi-functional simulator is presented. This circuit can be
53
54 used to implement lossless grounded inductance, FDNR and capacitance simulators without any matching
55 constraint with minimum passive components. The proposed admittance simulator uses only two OTRAs, one
56
57 buffer and three passive components (either two resistors and one capacitor or two capacitors and one resistor).
58 The proposed admittance simulator is simulated in PSPICE using CMOS based OTRA. Various application
59
60 examples are included to confirm the theoretical proposition.
61
62 1
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64
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 The organization of the paper starts with this Section 1, where introduction is given. The description of
1 active building block and proposed lossless grounded admittance simulator as a lossless grounded positive
2
3 inductor, FDNR and capacitance simulators are presented in Section 2. The effects of non-ideality of OTRA on
4 admittance simulator are discussed in Section 3. The simulation results with an application example for each
5
6 simulator are presented in Section 4 followed by Section 5 where experimental verification for use of inductor
7 simulator is given. Comparative study of proposed simulator with other OTRA based reported circuits are
8
9 presented in Section 6 followed by conclusion in Section 7.
10
11
12 2. PROPOSED CIRCUIT
13
The OTRA is a three-port building block and the symbol is given in Fig. 1(a), and its terminal equations
14
15 can be given as
16
17 V p   0 0 0  I p 
    
18 Vn    0 0 0   I n  (1)
19 V   Rm  Rm 0   I 0 
20  0
21 where Rm is dc transresistance gain of OTRA. Ideally, the R m, approaches infinity; hence the use of OTRA in
22
23 the external negative feedback will force the input currents, Ip and In, to be equal. Among the MOS based high
24 performance OTRA realizations available in literature, the structure used for simulation is shown in Fig. 1(b)
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26 [3, 4]. On the other hand OTRA can be implemented using commercially available IC (AD844AN) [5, 6] as
27 shown in Fig. 1(c).
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37 (a)
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54 (b)
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 1
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(c)
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21 Fig. 1 OTRA: (a) Ideal model (b) Internal structure using CMOS CMOS (c) Implementation using CFOA IC
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(AD844AN) [5]
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25
26 The proposed simulator topology using two OTRAs, one voltage follower (VF) and three passive
27 components is shown in Fig. 2. The routine analysis of the circuit is given below.
28
29 The input currents of OTRA1 are given by
30
𝐼𝑛1 = 𝐼𝑖𝑛 (1)
31
32 𝐼𝑝1 = 𝑉0 𝑌2 (2)
33
34 In an OTRA ideally, the Rm approaches infinity which forces input currents Ip and In to be equal. Hence we can
35 write
36
37 𝐼𝑝1 = 𝐼𝑛1 (3)
38 𝐼𝑖𝑛 = 𝑉0 𝑌2 (4)
39
40 Similarly, from OTRA2, we can get
41
𝑉𝑖𝑛 𝑌1 = 𝑉0 𝑌3 (5)
42
43 From (4) and (5), we get the expression for the input admittance as
44 𝐼 𝑌1 𝑌2
45 𝑌𝑖𝑛 = 𝑉𝑖𝑛 = 𝑌3
(6)
𝑖𝑛
46
47 It is shown in the following sections that the proper choice of Y1, Y2 and Y3 results lossless inductor, FDNR and
48
grounded capacitor simulators. It is also noting that floating resistors can easily be implemented using two
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50 NMOS transistors working in the linear region with complete nonlinearity cancellation, because OTRA input
51
terminals are virtually grounded [3]. It is also seen that each proposed circuit employs floating capacitor, but
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53 they can be easily realized with a current IC process that offers double poly (poly1-poly2) or metal-insulator-
54
metal (MIM) capacitor or metal-oxide-metal (MOM) capacitor [24, 25].
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62 3
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 1
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17 Fig. 2 The proposed lossless grounded admittance simulator
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20 2.1 Lossless grounded positive inductor
21
22 The proposed lossless grounded positive inductor simulator is obtained by selecting Y 1 and Y2 as resistors and
23 Y3 as a capacitor as shown in Fig. 3(a) which results the following expression for the input admittance:
24
25 1
26 Yin  (7)
sC1 R1 R2
27
28 Thus, the circuit realizes a lossless grounded inductor simulator whose value is given by
29
30 Leq  C1 R1 R2 (8)
31
The sensitivity of Leq to the variation in passive components is given by
32
33 SC1eq  S R1eq  S R2eq  1
L L L
(9)
34
35
36 It shows that the sensitivity of the proposed circuit is low. It is also observed that the value of inductance can
37 easily be tuned with R1 and/or R2.
38
39 2.2 Lossless grounded positive FDNR
40
41 The proposed lossless grounded positive FDNR simulator is obtained by selecting Y1 and Y2 as capacitors and
42 Y3 as a resistor and the corresponding circuit is shown in Fig. 3(b). The input admittance Yin of the circuit is
43
44 given by the following equation:
45
46 Yin  s 2 C1C2 R1 (10)
47 Thus, the circuit realizes a lossless grounded FDNR whose value is given by
48
49 Deq  C1C2 R1 (11)
50
51 The sensitivity of Deq to the variation in passive componnts is given by
52
SC1eq  SC2eq  S R1eq  1
D D D
53 (12)
54
55 It shows that the sensitivity of the proposed circuit is low, and the value of Deq can easily be controlled by R1.
56
57 2.2 Lossless grounded positive capacitance simulator/multiplier
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59 The proposed lossless grounded capacitance simulator is obtained by two ways first by choosing Y 1 as a
60 capacitor and Y2 and Y3 as resistors and the second way is by choosing Y2 as a capacitor and Y1 and Y3 as
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62 4
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 resistors and the corresponding circuits are shown in Figs. 3(c) and 3(d) respectively. The input admittance Y in
1 of the circuit of Fig 3(c) results:
2
3 R3
Yin1  sC1 (13)
4 R2
5
6 Thus, the circuit realizes a lossless grounded capacitance simulator/multiplier whose value is given by
7
R3
8 Ceq1  C1 (14)
9 R2
10
11 The sensitivity of Ceq1 to the variation in passive components is given by
12
SC1eq1  S R3eq1  1 , S R2eq1  1
C C C
13 (15)
14
15 Similarly the capacitance obtained for the circuit of Fig. 3(d) is
16
17 R3
18 Ceq 2  C2 (16)
R1
19
20 and the corresponding sensitivities are
21
22
SC2eq 2  S R3eq 2  1 , S R1eq 2  1
C C C
23 (17)
24
It is clear that the multiplication factor of capacitor simulator can easily be varied by resistances and also
25
sensitivity is found to be low whose magnitude is unity.
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45 (a) (b)
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18 (c) (d)
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20 Fig. 3 Proposed lossless grounded simulator: (a) Inductance; (b) FDNR; (c) Capacitance multiplier-I; (d)
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22 Capacitance multiplier-II
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25
3. NON-IDEALITY ANALYSIS
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27 In this section, the effect of the non-ideal transresistance gain (Rm) in the OTRA on the proposed admittance
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29 simulator is discussed. Till now, analysis has been done assuming ideal OTRA (infinite and frequency
30 independent Rm). However, practically the Rm is a frequency dependent finite value. Considering the single pole
31
32 model, the Rm can be expressed as:
33
34  
35  R 
36 Rm  s    m 0  (18)
1 s 
37   
38  0 
39 Where Rm0 is the dc value of transresistance gain. At high frequency, the R m(s) reduce to
40
41
 1   1 
42 Rm  s    , where C p     parasitic capacitance.
 sC 
(19)
43  p  Rm 00 
44
45 The analysis of the proposed admittance simulator circuit (Fig. 2) taking non-ideality effect into account yields a
46
modified expression for Yin(s) as,
47
48
Y1Y2  uc1  s 
49 Yin  , (20)
50 Y3  uc 2  s 
51
52 where  uc1  s  and  uc 2  s  are the uncompensated error function and are expressed as
53
54
 sC p1   sC p 2 
55  uc1  s    1   , and  uc 2  s   1  , (21)
56  Y2   Y3 
57
58 Where Cp1 and Cp2 are Cp of two OTRAs. The errors  uc1  s  and  uc 2  s  appears in the admittance simulator
59
60 topology of Fig. 2 at high frequency may be eliminated (compensated) by employing a modified topology. High
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62 6
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 frequency passive compensated topology of the simulated admittance with two additional elements Yp1 and Yp2
1 is shown in Fig. 4. Routine analysis results
2
Y1Y2  c1  s 
3
4 Yin  , (22)
5 Y3  c 2  s 
6
7 where  c1  s  and  c 2  s  are the compensated error function and are expressed as
8
9
  Yp1  sC p1    Yp 2  sC p 2  
10  c1  s   1     , and  c 2  s   1    , (23)
11   Y2     Y3  
12
13 The inspection of (23) suggests that Yp1  sC p1 and Yp 2  sC p 2 reduces  c1  s  and  c 2  s  to 1, and hence (22)
14
15 reduces to (6). It implies that the effect of single pole model of Rm can thus be eliminated by connecting a
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capacitors having value Cp1 and Cp2 in place of Yp1 and Yp2. The above result is applicable for all the realize
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18 simulators namely lossless grounded positive inductance simulator, FDNR simulator and capacitance simulator
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20 by proper choice of Y1, Y2 and Y3.
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41 Fig. 4 High frequency compensation
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45 4. SIMULATION RESULTS AND APPLICATION EXAMPLES
46 The workability of the proposed admittance simulator is simulated using PSPICE simulator in 180nm CMOS
47
48 technology. The aspect ratios of PMOS and NMOS transistors are given in Table 1 and supply voltages used are
49 VDD = –VSS = 0.9 V and VB = ‒ 0.3V. There are many MOS based voltage followers (VF) available in
50
51 literature. In Ref. 26, the MOS based VF is used for simulation with supply voltages V DD = ‒VSS = 0.9 V, the
52 bias voltage VB = ‒ 0.3 V and the aspect ratios of the M 1 and M2 transistors as 260µm/0.52µm and
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54 169µm/0.52µm respectively.
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 Table 1 Aspect ratios of MOS transistors of the OTRA in Fig. 1(b)
1
2
3 Transistor W(µm)/L(µm)
4 M1-M3 36/0.9
5 M4 3.6/0.9
6
7 M5, M6 10.8/0.9
8 M7 3.6/0.9
9 M8-M11 18/0.9
10
11 M12, M13 36/0.9
12 M14 18/0.18
13
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15 To design an inductance of 1mH the passive components of R 1 = R2 = 1 kΩ and C1= 1nF are used. The
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17 simulated impedance magnitude for 1mH inductance is shown in Fig. 5. It is found that inductance value
18 remains within ±10% in the frequency range of 1kHz–9.8MHz. Similarly, to implement an FDNR of 1fFs
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20 (femto-farad-second) the passive elements of C1 = C2 = 1nF and R1 = 1kΩ are used. The simulated magnitude
21
for 1fFs FDNR is shown in Fig.6. It is observed from Fig. 6 that the FDNR operates properly upto 12MHz.
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23 Similarly to implement a capacitance simulator/multiplier of 1nF the passive elements of C 1 = 1pF, R2 = 100kΩ
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and R3 = 100Ω are used. The simulated magnitude for 1nF capacitance is shown in Fig. 7. It is observed from
25
26 Fig. 7 that the capacitance simulator operates properly upto 9MHz. The total power consumption of the
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28 proposed circuit is found to be 833µW.
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45 Fig. 5 Inductance response for Leq = 1mH
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18 Fig. 6 FDNR response for Deq = 1fFs
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35 Fig. 7 Capacitance multiplier response for Ceq1 = 1nF
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4.1 Second order band pass filter (BPF) using simulated inductor
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41 A BPF shown in Fig. 8(a) is implemented using proposed inductor simulator. The transfer function computed
42
for BPF is given as
43
44
45 s
V0  s  CB RB
T s 
46
 (24)
47 Vi  s  s 2  s  1
48 CB RB Leq CB
49
From (24) the pole frequency ( 0 ), bandwidth ( 0
50
51
Q ) and quality factor (Q) can be expressed as
52
53 1 0 1 CB
54 0  ,  , and Q  RB (25)
Leq CB Q CB RB Leq
55
56
The performance of the BPF of Fig. 8(a) is verified using the inductor simulator topology of Fig. 3(a) for
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58 a design having a pole frequency of 159kHz for Q = 1 with RB = 1kΩ, CB = 1nF and Leq = 1mH (R1 = R2 = 1 kΩ
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62 9
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 and C1= 1nF). The frequency response of the BPF is shown in Fig. 8(b). Simulated value of pole frequency is
1 found to be 158.86kHz which is close to the theoretical value.
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33 Fig. 8 BPF: (a) Using inductance simulator; (b) Frequency response
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35 4.2 Second order low pass filter (LPF) using simulated FDNR
36 A second order LPF shown in Fig. 9(a) is constructed using proposed FDNR simulator. The transfer function
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38 obtained for LPF is given as
39
40 1
41 V s Deq RL
42 T s  0  (26)
43 Vi  s  s 2  s  1
44 CL RL Deq RL
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46 From (26) the pole frequency ( 0 ), bandwidth ( 0 Q ) and quality factor (Q) can be expressed as
47
48
1 0 1 RL
49 0  ,  , and Q  CL (27)
50 Deq RL Q CL RL Deq
51
52 where Deq  C1C2 R1 .
53
54 The performance of the LPF of Fig. 9(a) of is verified using the FDNR topology of Fig. 3(b) for a design
55
56 having a pole frequency of 159kHz for Q = 1 with R L = 1kΩ, CL = 1nF and Deq = 1fFs (C1 = C2 = 1nF and R1 =
57 1kΩ). The frequency response of the LPF is shown in Fig. 9(b). Simulated value of pole frequency is 159.2kHz,
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59 which agrees closely with theoretical value.
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62 10
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8 (a)
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25 Fig. 9 LPF: (a) Using FDNR simulator; (b) Frequency response
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27 4.3 First order low pass filter (LPF) using simulated capacitance simulator
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29 A first order LPF shown in Fig. 10(a) is constructed using proposed capacitance simulator. The transfer function
30 obtained for LPF is given as
31
32 V0  s  1
33 T s   (28)
34 Vi  s  1  sCeq1 RL
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36 From (28) the pole frequency ( 0 ) can be expressed as
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38 R
1
39 0  , where Ceq1  C1 3 (29)
40 Ceq1 RL R2
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42 The performance of the LPF of Fig. 10(a) is verified using the capacitance simulator/multiplier-I topology
43 of Fig. 3(c) for a design having a pole frequency of 159kHz with RL = 1kΩ, Ceq1 = 1nF (C1 = 1pF, R2 = 100kΩ
44
45 and R3 = 100Ω). The frequency response of the LPF is shown in Fig. 10(b). Simulated value of pole frequency
46 (158.92kHz) agrees closely with the theoretical value.
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15 (b)
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17 Fig. 10 LPF: (a) Using capacitance simulator/multiplier; (b) Frequency response
18
19
20 5. EXPERIMENTAL VERIFICATION
21 The functionality of the proposed topology is also verified experimentally for the inductance simulator with an
22
23 application example of LC oscillator. An LC oscillator can be realized using the proposed lossless grounded
24 inductor simulator (Leq) of Fig. 3(a), which is shown in Fig. 11. The characteristics equation obtained for the LC
25
26 oscillator is obtained as
27
s 1
28
29
s2   RO1  RO 2  RO 3   0 (30)
CO1 RO1 RO 2 Leq CO1
30
31 For which the condition of oscillation (CO) and frequency of oscillation (FO) are obtained as
32
33 CO: RO1  RO 2  RO 3 (31)
34
35 1
36 FO: 0  (32)
Leq CO1
37
38 The experimental verification of the LC oscillator of Fig. 11 is done using the OTRA realization of
39
40 commercially available CFOA IC AD844AN [5, 6] of Fig. 1(c). The voltage follower (VF) has been
41
implemented using a CFOA. The DC bias supply of the CFOA IC AD844AN is chosen as ±5V and the
42
43 component values are chosen for the circuit of Fig. 11 as R O1 = 1kΩ, RO2 = 1kΩ, RO3 = 2kΩ, CO1 = 1nF and
44
Leq = 1mH (R1 = R2 = 1 kΩ and C1= 1nF). Theoretically calculated frequency for chosen component values is
45
46 159 kHz. The experimental waveform obtained on the oscilloscope is shown in Fig. 12. The observed FO is
47
48 found to be 158.20 kHz, which is in close agreement to theoretically calculated value of 159 kHz.
49
50
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62 12
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 Fig. 11 LC oscillator
1
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6
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8
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21
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23 Fig. 12 Experimental result of the LC oscillator
24
25
26
27 6. COMPARISON
28
29 Many grounded active inductors, FDNRs and Capacitance simulators using OTRA are available in literature [7-
30 16]. The comparisons of these simulators are given in Table 2. The inspection of Table 2 reveals that most of the
31
32 literatures based on OTRA simulate only inductance [7-10, 13-15]. The work in Ref. 11, uses one less number
33 of OTRA in count in comparison to the proposed one, however it simulates only inductance (L eq) and FDNR
34
35 and uses one excess passive component and also requires passive components matching in contrast to the
36 proposed one. Although, the work in Ref.12, uses same number of active building blocks (ABBs), it uses three
37
38 excess passive components for realization of Leq, FDNR and Ceq in contrast to the proposed one. The work in
39 Ref. 16 implements only FDNR and requires passive components matching; moreover it uses five passive
40
41 components in contrast to three in the proposed circuits.
42
43 Table 2 A comparison of lossless grounded simulators using OTRA
44
Reference No of ABBs No. of Passive Realization Passive component
45
46 components (R/C) (Leq, FDNR, Ceq) matching required
47
48
Ref.7 [Fig.6] OTRA=2 6 (5/1) Leq Yes
49
50
51 Ref. 8 [Fig.2c] OTRA=2 6 (5/1) Leq Yes
52
53 Ref. 9 OTRA = 1 6 (5/1) -Leq Yes
54
55
56 Ref. 10 OTRA=2 6 (5/1) Leq Yes
57
58 Ref. 11 OTRA=1, VF = 1 4 (2/2) Leq Yes
59
60
61
62 13
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 4 (2/2) FDNR Yes
1
2 Ref. 12 OTRA=2, VF = 1 6 (5/1) Leq Yes
3
4 [Fig. 4] 6 (4/2) FDNR Yes
5
6 6 (5/1) Ceq Yes
7
8
Ref. 13 OTRA = 1 5 (3/2) Leq Yes
9
10
11 Ref. 14 OTRA = 1 5 (4/1) -Leq Yes
12
13 Ref. 15 OTRA = 1 4 (3/1) -Leq Yes
14
15
16 Ref. 16 OTRA = 1 5(2/3) FDNR Yes
17
18 Proposed OTRA=2, VF = 1 3 (2/1) Leq No
19
20 3 (1/2) FDNR No
21
22 3 (2/1) Ceq No
23
24
25
26
27 7. CONCLUSION
28 In this paper, a generalized admittance simulator is proposed. This can be used to implement lossless grounded
29
30 inductor, FDNR and capacitance simulators with minimum passive components and without any matching
31 constraint. The proposed admittance simulator employs two OTRAs, one buffer and three passive components.
32
33 To demonstrate the practical use of the proposed circuit, some application examples (second order band pass
34 filter using inductance simulator, second order LPF using FDNR and first order LPF using capacitance
35
36 multiplier) have been included. It is also found that the non-linearity error may be eliminated at high frequency
37 by passive compensation. The propose circuit offers some advantageous features such as: (i) no matching
38
39 constraint, (ii) minimum passive components, (iii) low passive sensitivity, and (iv) low power consumption.
40 Simulation and experimental results verify the theoretical propositions.
41
42
43
REFERENCES
44
45 1. Chen, J. J., Tsao, H. W., & Chen, C. C. (1992). Operational transresistance amplifier using CMOS
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48 2. Chen, J. J., Tsao, H. W., Liu, S. I., & Chiu, W. (1995). Parasitic-capacitance-insensitive current-mode filters
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56 amplifier (OTRA). Frequenz, 60(3-4), 70-76.
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3 8. Cam, U., Kacar, F., Cicekoglu, O., Kuntman, H., & Kuntman, A. (2004). Novel two OTRA-based grounded
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6 9. Kilinc, S., Salama, K. N., & Cam, U. (2006). Realization of Fully Controllable Negative Inductance with
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9 10. Pandey, R., Pandey, N., Paul, S. K., Singh, A., Sriram, B., & Trivedi, K. (2011). New topologies of lossless
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17 12. Gupta, A., Senani, R., Bhaskar, D. R., & Singh, A. K. (2013). New OTRA-based generalized impedance
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20 13. Pandey, R., Pandey, N., Paul, S. K., Singh, A., Sriram, B., & Trivedi, K. (2014). Novel grounded inductance
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23 14. Ghosh, M., & Paul, S. K. (2014). Design of lossless grounded negative inductance simulator using single
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26 15. Nagar, B. C., & Paul, S. K. (2016). Negative inductance simulator using OTRA. Proc. IEEE Int. Conf. on
27 Microelectronics, Computing and Communications, NIT Durgapur, India, 2016, 1–3,
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29 doi:10.1109/MicroCom2016.7522486.
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32 Analog Integrated Circuits and Signal Processing, 92, 507–517.
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17. Said, L. A., Radwan, A. G., Madian, A. H., & Soliman, A. M. (2015). Fractional order oscillators based
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35 on operational transresistance amplifiers. Int. J of Electronics and Communications (AEU), 69, 988–
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37 1003.
38 18. Nagar, B. C., & Paul, S. K. (2016). Voltage mode third order quadrature oscillators using OTRAs. Analog
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40 Integrated Circuits and Signal Processing, 88, 517–530.
41 19. Chang, Chun-Ming, & Swamy, M. N. S. (2013). Analytical synthesis of odd/even nth order elliptic cauer
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43 filter structures using OTRAs. Int. J of Circuit Theory and Applications, 41, 1248–1271.
44 20. Lo, Y. K. Lo, & Chien, H. C. (2006). Current-Mode Monostable Multivibrators using OTRAs, IEEE
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46 Transactions on Circuits and Systems-II, 53, 1274–1278.
47 21. Lo, Y. K. Lo, & Chien, H. C., & Chiu, H. J. (2010). Current-input OTRA Schmitt trigger with dual
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49 hysteresis modes. International Journal of Circuit Theory and Applications, 38, 739–746.
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22. Pandey, R., Pandey, N., Chitranshi, S., & Paul, S. K. (2015). Operational transresistance amplifier based PID
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52 Controller. Advances in Electrical and Electronic Engineering, 13, 171–180.
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23. Chien, Hung-Chun (2016). Switch-Controllable full phase operation precision half wave rectifier using a
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55 single OTRA. Journal of Circuits, Systems, and Computers, 25, 1–21.
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58 IEEE Press, New York.
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1 voltage conveyor and MOSFET based electronic resistors. Radioengineering, 20, 10-18.
2
3 26. Yucel, F., & Yuce, E. (2015). A new voltage-mode multifunctional filter using only two voltage followers
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Author Biographies Click here to access/download;Author Biographies;Author
Biographies_1 October 2018.docx

Bal Chand Nagar is currently working as Assistant Professor in the Department of Electronics and
Communication Engineering, NIT Patna, Bihar, India. He did her B.E. (ECE) from MIT Mandsaur (RGPV,
Bhopal), MP, India, M.Tech. (Microelectronics & VLSI Design) from SGSITS Indore (RGPV, Bhopal), MP,
India, and Ph.D. from IIT(ISM) Dhanbad, JH, India. He has served, SVCE Indore, AITR Indore in various
capacities. His research interests include Analog/Digital VLSI Circuit Design. He has published papers in
International, National Journal of repute and Conferences. He is life member of IETE, ISTE, IEI and student
member of IEEE for last 4 years.

Sajal K. Paul did his B.Tech., M.Tech., and Ph.D. in Radio Physics and Electronics from the Institute of Radio
Physics and Electronics, University of Calcutta. He has served Webel Telecommunication Industries, Kolkata;
Indira Gandhi National Open University (IGNOU), Kolkata; Advanced Training Institute for Electronics &
Process Instrumentation (ATI-EPI), Hyderabad; North Eastern Regional Institute of Science &
Technology(NERIST), Nirjuli and Delhi College of Engineering(DCE), Delhi in various capacities. He has
served the Department of Electronics Engineering, Indian Institute of Technology (Indian School of Mines),
Dhanbad as Head of the Department, Dean (Faculty) and at present Professor of the same department. His
research interest includes Microelectoncic Devices, Electronic Properties of Semiconductor and Bipolar and
MOS Analog Integrated Circuits. Dr. Paul has more than 115 research publications in International and
National journals of repute and conferences.