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FEATURES DESCRIPTION
nn AEC-Q100 Qualified for Automotive Applications The LTC®6813-1 is a multicell battery stack monitor that
nn Measures Up to 18 Battery Cells in Series measures up to 18 series connected battery cells with
nn 2.2mV Maximum Total Measurement Error a total measurement error of less than 2.2mV. The cell
nn Stackable Architecture for High Voltage Systems measurement range of 0V to 5V makes the LTC6813-1
nn Built-In isoSPI™ Interface suitable for most battery chemistries. All 18 cells can be
nn 1Mb Isolated Serial Communications measured in 290µs, and lower data acquisition rates can
nn Uses a Single Twisted Pair, Up to 100 Meters be selected for high noise reduction.
nn Low EMI Susceptibility and Emissions
nn Bidirectional for Broken Wire Protection
Multiple LTC6813-1 devices can be connected in series,
nn 290µs to Measure All Cells in a System
permitting simultaneous cell monitoring of long, high
nn Synchronized Voltage and Current Measurement
voltage battery strings. Each LTC6813-1 has an isoSPI
nn 16-Bit Delta-Sigma ADC with Programmable
interface for high speed, RF immune, long distance com-
3rd Order Noise Filter munications. Multiple devices are connected in a daisy
nn Engineered for ISO 26262-Compliant Systems chain with one host processor connection for all devices.
nn Passive Cell Balancing Up to 200mA (Max) with This daisy chain can be operated bidirectionally, ensuring
Programmable Pulse‑Width Modulation communication integrity, even in the event of a fault along
nn 9 General Purpose Digital I/O or Analog Inputs the communication path.
nn Temperature or Other Sensor Inputs The LTC6813-1 can be powered directly from the bat-
nn Configurable as an I2C or SPI Master tery stack or from an isolated supply. The LTC6813-1
nn 6µA Sleep Mode Supply Current
includes passive balancing for each cell, with individual
nn 64-Lead eLQFP Package
PWM duty cycle control for each cell. Other features
include an onboard 5V regulator, nine general purpose
APPLICATIONS I/O lines and a sleep mode, where current consumption
is reduced to 6µA.
nn Electric and Hybrid Electric Vehicles
All registered trademarks and trademarks are the property of their respective owners. Protected
nn Backup Battery Systems by U.S. patents, including 8908779, 9182428, 9270133.
nn Grid Energy Storage
nn High Power Portable Equipment
1.0
+ 0.5
CELL 18
+ ISOLATED 0
CELL 17 DATA WITH
• LTC6813-1
• WIRE BREAK –0.5
• PROTECTION
CELL 2
+ –1.0
CELL 1
+ –1.5
68131 TA01a
–2.0
–50 –25 0 25 50 75 100 125
TEMPERATURE (°C)
68131 TA01b
Rev. A
Rev. A
CSB (IMA)*
Total Supply Voltage
SCK (IPA)*
SDO (NC)*
SDI (NC)*
ISOMD
V+ to V–............................................................. 112.5V
DRIVE
VREF1
VREF2
IBIAS
DTEN
ICMP
V–**
WDT
IMB
IPB
V–
Supply Voltage (Relative to C12)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
V+ to C12................................................................50V
Input Voltage (Relative to V–)
V+ 1 48 VREG
C0............................................................. –0.3V to 6V C18 2 47 GPIO9
C18..........................–0.3V to MIN (V+ + 5.5V, 112.5V) S18
C17
3
4
46
45
GPIO8
GPIO7
C(n), S(n)........................ –0.3V to MIN (8 • n, 112.5V) S17 5 44 GPIO6
C16 6 43 GPIO5
IPA, IMA, IPB, IMB............ –0.3V to VREG + 0.3V, ≤ 6V S16 7 42 GPIO4
DRIVE....................................................... –0.3V to 7V C15 8 65 41 GPIO3
S15 9 V– 40 GPIO2
All Other Pins............................................ –0.3V to 6V C14 10 39 GPIO1
ORDER INFORMATION
AUTOMOTIVE PRODUCTS**
MSL SPECIFIED JUNCTION
TRAY (160PC) TAPE AND REEL (1500PC) PART MARKING* PACKAGE DESCRIPTION RATING TEMPERATURE RANGE
LTC6813ILWE-1#3ZZPBF LTC6813ILWE-1#3ZZTRPBF LTC6813LWE-1 64-Lead Plastic eLQFP 3 –40°C to 85°C
LTC6813HLWE-1#3ZZPBF LTC6813HLWE-1#3ZZTRPBF LTC6813LWE-1 64-Lead Plastic eLQFP 3 –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models
are designated with a #3ZZ suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog
Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.
Rev. A
Rev. A
Rev. A
Rev. A
Rev. A
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 4: These timing specifications are dependent on the delay through
may cause permanent damage to the device. Exposure to any Absolute the cable, and include allowances for 50ns of delay each direction. 50ns
Maximum Rating condition for extended periods may affect device corresponds to 10m of CAT5 cable (which has a velocity of propagation of
reliability and lifetime. 66% the speed of light). Use of longer cables would require derating these
Note 2: The ADC specifications are guaranteed by the Total Measurement specs by the amount of additional delay.
Error specification. Note 5: These specifications do not include rise or fall time of SDO. While
Note 3: The ACTIVE state current is calculated from DC measurements. fall time (typically 5ns due to the internal pull-down transistor) is not a
The ACTIVE state current is the additional average supply current into concern, rising-edge transition time tRISE is dependent on the pull-up
VREG when there is continuous 1MHz communications on the isoSPI ports resistance and load capacitance on the SDO pin. The time constant must
with 50% data 1’s and 50% data 0’s. Slower clock rates reduce the supply be chosen such that SDO meets the setup time requirements of the MCU.
current. See Applications Information section for additional details.
Rev. A
0 0 0
4 0.7 0.7
PEAK NOISE (mV)
NUMBER OF PARTS
PEAK NOISE (mV)
6 15 15
5
4 10 10
3
2 5 5
1
0 0 0
0 1 2 3 4 5 –50 –30 –10 10 30 50 –75 –50 –25 0 25 50 75
INPUT (V) CHANGE IN GAIN ERROR (ppm) CHANGE IN GAIN ERROR (ppm)
68131 G07 68131 G08 68131 G09
Rev. A
0.5
4 –30
0
3 –40
–0.5
2 –50 –1.0
1 –60 –1.5
–2.0
0 –70 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
–50 –25 0 25 50 75 100 125 150 175 200 10 100 1k 10k 100k 1M
VREG (V)
CHANGE IN GAIN ERROR (ppm) INPUT FREQUENCY (Hz) 68131 G12
68131 G10
26Hz 2kHz 14kHz
422Hz 3kHz 27kHz
1kHz 7kHz
Measurement Error vs Common
68131 G11
0 0 0
Measurement Error Due to a VREG Measurement Error Due to a V+ Measurement Error CMRR vs
AC Disturbance AC Disturbance Frequency
0 0 0
VREG(DC) = 5V V+ DC = 59.4V VCM(IN) = 5VP-P
V
–10 REG(AC)
= 0.5VP-P –10 V+ AC = 5VP-P –10 NORMAL MODE CONVERSIONS
1BIT CHANGE < –70dB 1BIT CHANGE < –90dB
–20 V –20
–20 REG GENERATED FROM
–30 DRIVE PIN, FIGURE 32 –30
REJECTION (dB)
Rev. A
Cell Measurement Error Range vs GPIO Measurement Error vs Input Measurement Time vs
Input RC Values RC Values Temperature
5 20 2.50
TIME BETWEEN MEASUREMENTS > 3RC 18-CELL NORMAL MODE CONVERSIONS
16 2.45
12
–5 0 2.30
–4 2.25
–8 C = 1nF
–10 C = 10nF 2.20
–12 C = 100nF
100nF VREG = 4.5V
10nF –16 C = 1μF 2.15 VREG = 5V
1µF C = 10μF VREG = 5.5V
–15 –20 2.10
100 1k 10k 1 10 100 1k 10k –50 –25 0 25 50 75 100 125
INPUT RESISTANCE, R (Ω) INPUT RESISTANCE, R (Ω) TEMPERATURE (°C)
68131 G19 68131 G20 68131 G21
125°C
70 85°C
25°C 1.5
7
65 0°C
–40°C 1.4
6 60
1.3
55
5
125°C 1.2 125°C
50
85°C 85°C
4 25°C 1.1 25°C
45
0°C 0°C
–40°C –40°C
3 40 1.0
10 20 30 40 50 60 70 80 90 10 20 30 40 50 60 70 80 90 10 20 30 40 50 60 70 80 90
V+ (V) 68131 G22
V+ (V) 68131 G23
V+ (V) 68131 G24
16.5
3.003
3.140
3.002
16.0
3.135 3.001
VREF1 (V)
VREF2 (V)
3.125 2.999
15.0
125°C 2.998
3.120
85°C 2.997
14.5 25°C
0°C 3.115 2.996
–40°C
14.0 3.110 2.995
10 20 30 40 50 60 70 80 90 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
V+ (V) TEMPERATURE (°C) TEMPERATURE (°C)
68131 G25 68131 G26 68131 G27
Rev. A
VREF2 VREG Line Regulation VREF2 V+ Line Regulation VREF2 Load Regulation
400 100 200
IL = 0.6mA 125°C VREG GENERATED FROM V+ = 59.4V
320 85°C 80 DRIVE PIN, FIGURE 32 VREG = 5V
25°C 0
240 –40°C 60
VREF2 Thermal Hysteresis, Hot VREF2 Thermal Hysteresis, Cold VREF2 Change Due to IR Reflow
15 15 5
TA = 85°C TO 25°C TA = –40°C to 25°C
NUMBER OF PARTS
NUMBER OF PARTS
NUMBER OF PARTS
10 10
3
2
5 5
0 0 0
–125–100 –75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 –300 –200 –100 0 100 200 300
CHANGE IN VREF2 (ppm) CHANGE IN VREF2 (ppm) CHANGE IN VREF2 (ppm)
68131 G31 68131 G32 68131 G33
15 –40°C –30
5.7 –40
VDRIVE (V)
10
–50
5.6 5
–60
0 –70 125°C
5.5 –80 85°C
–5 25°C
–90 0°C
V+ = 59.4V –40°C
5.4 –10 –100
–50 –25 0 25 50 75 100 125 15 30 45 60 75 90 0.01 0.1 1
TEMPERATURE (°C) V+ (V) IOUT (mA)
68131 G34 68131 G35 68131 G36
Rev. A
2.01 2.005
IBIAS PIN VOLTAGE (V)
IBIAS PIN VOLTAGE (V)
6
2.00 2.000
5
4
1.99 1.995
3
WRITE
READ
2 1.98 1.990
0 200 400 600 800 1000 –50 –25 0 25 50 75 100 125 0 200 400 600 800 1000
isoSPI CLOCK FREQUENCY (kHz) TEMPERATURE (°C) IBIAS CURRENT, IB (µA)
68131 G43 68131 G44 68131 G45
Rev. A
5.0
22 22
4.5
21 21
4.0
20 20
3.5
19 19
VA = 1.6V 3.0
VA = 1V IB = 100μA IB = 100μA
VA = 0.5V IB = 1mA IB = 1mA
18 18 2.5
0 200 400 600 800 1000 –50 –25 0 25 50 75 100 125 0 0.5 1 1.5 2
IBIAS CURRENT, IB (µA) TEMPERATURE (°C) PULSE AMPLITUDE, VA (V)
68131 G46 68131 G47 68131 G48
3 PARTS
0.54 0.54
0.52 0.52
0.50 0.50
0.48 0.48
0.46 0.46
VICMP = 0.2V
VICMP = 1V
0.44 0.44
2.5 3 3.5 4 4.5 5 5.5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
RECEIVER COMMON MODE, VCM (V) ICMP VOLTAGE (V)
68131 G49 68131 G50
250 GUARANTEED
0.54
WAKE-UP REGION
0.52 200
0.50 150
0.48 100
0.46 50
VICMP = 0.2V
VICMP = 1V
0.44 0
–50 –25 0 25 50 75 100 125 0 100 200 300 400 500 600
TEMPERATURE (°C) WAKE-UP DWELL TIME, TDWELL (ns)
68131 G51 68131 G52
Rev. A
Rev. A
C17 GPIO7
4 CSB (IMA) 45
C12
C11
P + SCK (IPA)
S17 16 LOGIC GPIO6
C10 7-CELL ADC2 DIGITAL SERIAL
5 AND SDO (NC) 44
MUX FILTERS PORT A
C9 MEMORY
C8
M – SDI (NC)
C16 GPIO5
6 C7 43
S16 GPIO4
7 42
P + GPIO AND
C6 16 I2C
C15 C5 ADC1 GPIO3
8 C4 7-CELL 41
C3 MUX M –
S15 C2 GPIO2
9 40
C1 WDT ISOMD
C0 TEMP
GPIO1
10 C14 VREF2 39
SC GPIO[9:1]
VREG
S14 18 BALANCE FETs VREGD C0
11 P 38
S(n)
AUX
C13 MUX S1
12 37
M
C(n–1)
S13 C1
13 C18 36
DIE 2ND VREF2
C12 TEMP REFERENCE S2
14 TEMPERATURE 35
REGULATORS
DISCHARGE SC
S12 DTEN V+ C2
15 TIMER 1ST 34
LDO2 VREF1
REFERENCE
DRIVE S3
C11 WATCH DOG
16 WDT V+ 33
TIMER
C0 LDO1 VREGD
POR
Rev. A
Rev. A
SLEEP IDLE
WD TIMEOUT WAKE-UP
AND DTEN = 0 WAKE-UP SIGNAL WAKE-UP SIGNAL
SIGNAL
(tSLEEP) IDLE TIMEOUT (CORE = SLEEP) (CORE = STANDBY)
(tWAKE)
DCTO REACHES 0 (tIDLE) (tWAKE) (tREADY)
WD TIMEOUT WD TIMEOUT
AND DTEN = 0 & DTEN = 1
EXTENDED
(tSLEEP) STANDBY BALANCING
WAKE-UP READY
REFON = 0
REFON = 1 SIGNAL (tWAKE)
(tREFUP) ADC
EVERY 30s NO ACTIVITY ON TRANSMIT/RECEIVE
COMM & DTM=1 isoSPI PORT
REFUP ADC (tREFUP)
COMMAND WAKE-UP
SIGNAL ACTIVE
CONV DONE (tWAKE) CONV NOTE: STATE TRANSITION
(REFON = 0) DONE DELAYS DENOTED BY (tX)
WD TIMEOUT CONV DONE DTM 68131 F01
isoSPI STATE DESCRIPTIONS The power consumption varies according to the opera-
tional states. Table 1 and Table 2 provide equations to
Note: The LTC6813-1 has two isoSPI ports (A and B), for approximate the supply pin currents in each state. The
daisy-chain communication. V+ pin current depends only on the Core state. However,
the VREG pin current depends on both the Core state and
IDLE State isoSPI state, and can, therefore, be divided into two com-
The isoSPI ports are powered down. ponents. The isoSPI interface draws current only from
the VREG pin.
When isoSPI Port A or Port B receives a WAKE-UP signal
(see Waking Up the Serial Interface), the isoSPI enters IREG = IREG(CORE) + IREG(isoSPI)
the READY state. This transition happens quickly (within In the SLEEP state, the VREG pin will draw approximately
tREADY) if the Core is in the STANDBY state. If the Core is 3.1μA if powered by an external supply. Otherwise, the
in the SLEEP state when the isoSPI receives a WAKE-UP V+ pin will supply the necessary current.
signal, then it transitions to the READY state within tWAKE.
Table 1. Core Supply Current
READY State STATE IVP IREG(CORE)
VREG = 0V 6.1µA 0µA
The isoSPI port(s) are ready for communication. The SLEEP
VREG = 5V 3µA 3.1µA
serial interface current in this state depends on the sta-
STANDBY 14µA 35µA
tus of the ISOMD pin and RBIAS = RB1 + RB2 (the external
REFUP 550µA 900µA
resistors tied to the IBIAS pin).
MEASURE 950µA 15mA
If there is no activity (i.e., no WAKE-UP signal) on Port
A or Port B for greater than tIDLE, the LTC6813-1 goes to Table 2. isoSPI Supply Current Equations
the IDLE state. When the serial interface is transmitting or isoSPI ISOMD
STATE CONNECTION IREG(isoSPI)
receiving data, the LTC6813-1 goes to the ACTIVE state.
IDLE N/A 0mA
ACTIVE State VREG 2.2mA + 3 • IB
READY
V– 1.5mA + 3 • IB
The LTC6813-1 is transmitting/receiving data using one
or both of the isoSPI ports. The serial interface con- ⎛ 100ns ⎞
sumes maximum power in this state. The supply current Write: 2.5mA + ⎜ 3 + 20 • •IB
VREG ⎝ t CLK ⎟⎠
increases with clock frequency as the density of isoSPI
⎛ 100ns • 1.5 ⎞
pulses increases. ACTIVE Read: 2.5mA + ⎜ 3 + 20 • •IB
⎝ t CLK ⎟⎠
POWER CONSUMPTION V–
⎛ 100ns ⎞
1.8mA + ⎜ 3 + 20 • •IB
The LTC6813-1 is powered via two pins: V+ and VREG. ⎝ t CLK ⎟⎠
The V+ input requires voltage greater than or equal to
the top cell voltage minus 0.3V, and it provides power to
Rev. A
1.0
The ADCV command initiates the measurement of the
0.9
NORMAL MODE
FILTERED MODE
battery cell inputs, pins C0 through C18. This command
0.8
has options to select the number of channels to measure
0.7 and the ADC mode. See the section on Commands for the
PEAK NOISE (mV)
68131 F03
Table 5. Conversion and Synchronization Times for ADCV Command Measuring All 18 Cells in Different Modes
CONVERSION TIMES (IN μs) SYNCHRONIZATION TIME (IN μs)
MODE t0 t1M t2M t5M t6M t6C tSKEW2
27kHz 0 58 104 244 291 1,121 233
14kHz 0 87 163 390 466 1,296 379
7kHz 0 145 279 681 815 2,343 670
3kHz 0 261 512 1,263 1,513 3,041 1,252
2kHz 0 494 977 2,426 2,909 4,437 2,415
1kHz 0 960 1,908 4,753 5,702 7,230 4,742
422Hz 0 1,890 3,770 9,408 11,287 12,816 9,397
26Hz 0 29,818 59,624 149,044 178,851 201,325 149,033
tREFUP
SERIAL ADCV + PEC
INTERFACE
MEASURE
ADC3 CALIBRATE
C16 TO C15
MEASURE
ADC2 CALIBRATE
C10 TO C9
MEASURE
ADC1 CALIBRATE
C4 TO C3
t0 t1M t1C
68131 F04
Rev. A
tCYCLE
tREFUP tSKEW
SERIAL ADAX + PEC
INTERFACE
ADC3
ADC2
Figure 5. Timing for ADAX Command Measuring All GPIOs and 2nd Reference
Rev. A
Auxiliary (GPIO) Measurements with Digital Measuring Cell Voltages and GPIOs (ADCVAX
Redundancy (ADAXD Command) Command)
The ADAXD command operates similarly to the ADAX The ADCVAX command combines eighteen cell measure-
command except that an additional diagnostic is per- ments with two GPIO measurements (GPIO1 and GPIO2).
formed using digital redundancy. PS[1:0] in Configuration This command simplifies the synchronization of battery
Register Group B must be set to 0 or 1 during ADAXD to cell voltage and current measurements when current sen-
enable redundancy. See the ADC Conversion with Digital sors are connected to GPIO1 or GPIO2 inputs. Figure 6
Redundancy section. illustrates the timing of the ADCVAX command. See the
section on Commands for the ADCVAX command format.
The execution time of ADAX and ADAXD is the same.
The synchronization of the current and voltage measure-
ments, tSKEW1, in Fast mode is within 194μs.
Table 8 shows the conversion and synchronization time
for the ADCVAX command in different modes. The total
conversion time for the command is given by t8C.
tCYCLE
tSKEW1
tREFUP tSKEW1
SERIAL ADCVAX + PEC
INTERFACE
Rev. A
DATA ACQUISITION SYSTEM DIAGNOSTICS Power Supply (VA) and the Digital Power Supply (VD).
The battery monitoring data acquisition system is com- These parameters are described in the section below.
prised of the multiplexers, ADCs, 1st reference, digital All the 8 ADC modes described earlier are available for
filters and memory. To ensure long term reliable perfor- these conversions. See the section on Commands for
mance there are several diagnostic commands which can the ADSTAT command format. Figure 7 illustrates the
be used to verify the proper operation of these circuits. timing of the ADSTAT command measuring all 4 internal
device parameters.
Measuring Internal Device Parameters (ADSTAT Table 9 shows the conversion time of the ADSTAT com-
Command) mand measuring all 4 internal parameters. t4C indicates
The ADSTAT command is a diagnostic command that the total conversion time for the ADSTAT command.
measures the following internal device parameters: Sum
of all Cells (SC), Internal Die Temperature (ITMP), Analog
tCYCLE
tSKEW
tREFUP
SERIAL ADSTAT + PEC
INTERFACE
ADC3
ADC2
Rev. A
Sum of Cells Measurement: The Sum of All Cells mea- The value of VREG is determined by external components.
surement is the voltage between C18 and C0 with a 30:1 VREG should be between 4.5V and 5.5V to maintain accu-
attenuation. The 16-bit ADC value of Sum of Cells mea- racy. The value of VREGD is determined by internal compo-
surement (SC) is stored in Status Register Group A. Any nents. The normal range of VREGD is 2.7V to 3.6V.
potential difference between the C0 and V– pins results in
an error in the SC measurement equal to this difference. Measuring Internal Device Parameters with Digital
From the SC value, the sum of all cell voltage measure- Redundancy (ADSTATD Command)
ments is given by: The ADSTATD command operates similarly to the ADSTAT
Sum of All Cells = SC • 30 • 100µV command except that an additional diagnostic is per-
formed using digital redundancy. PS[1:0] in Configuration
Internal Die Temperature: The ADSTAT command can
Register Group B must be set to 0 or 1 during ADSTATD to
measure the internal die temperature. The 16-bit ADC
enable redundancy. See the ADC Conversion with Digital
value of the die temperature measurement (ITMP) is
Redundancy section.
stored in Status Register Group A. From ITMP, the actual
die temperature is calculated using the expression: The execution time of ADSTAT and ADSTATD is the same.
Internal Die Temperature (°C) =
ADC Conversion with Digital Redundancy
100 µV
ITMP • °C – 276°C Each of the three internal ADCs contains its own digital
7.6mV
integration and differentiation machine. The LTC6813-1
Power Supply Measurements: The ADSTAT command is also contains a fourth digital integration and differentiation
also used to measure the Analog Power Supply (VREG) machine that is used for redundancy and error checking.
and Digital Power Supply (VREGD). The 16-bit ADC value All of the ADC and self test commands, except ADAX
of the analog power supply measurement (VA) is stored in and ADSTAT, can operate with digital redundancy. This
Status Register Group A. The 16-bit ADC value of the digi- includes ADCV, ADOW, CVST, ADOL, ADAXD, AXOW, AXST,
tal power supply measurement (VD) is stored in Status ADSTATD, STATST, ADCVAX and ADCVSC. When per-
Register Group B. From VA and VD, the power supply forming an ADC conversion with redundancy, the analog
measurements are given by: modulator sends its bit stream to both the primary digital
Analog Power Supply Measurement (VREG) = machine and the redundant digital machine. At the end
VA • 100µV of the conversion the results from the two machines are
compared. If any mismatch occurs then a value of 0xFF0X
Digital Power Supply Measurement (VREGD) = (≥6.528V) is written to the result register. This value is
VD • 100µV
Rev. A
Rev. A
Table 11. Conversion and Synchronization Times for ADCVSC Command in Different Modes
SYNCHRONIZATION
CONVERSION TIMES (IN μs) TIME (IN μs)
MODE t0 t1M t2M t3M t4M t5M t6M t7M t7C tSKEW
27kHz 0 58 104 151 205 259 306 352 1,331 147
14kHz 0 87 163 238 321 404 480 556 1,534 235
7kHz 0 145 279 413 554 695 829 963 2,756 409
3kHz 0 261 512 762 1,020 1,277 1,527 1,778 3,571 758
2kHz 0 494 977 1,460 1,950 2,441 2,924 3,407 5,200 1,456
1kHz 0 960 1,908 2,857 3,812 4,768 5,717 6,665 8,458 2,853
422Hz 0 1,890 3,770 5,649 7,536 9,423 11,302 13,181 14,974 5,645
26Hz 0 29,818 59,624 89,431 119,245 149,059 178,866 208,672 234,902 89,427
Rev. A
tREFUP
SERIAL ADOL + PEC
INTERFACE
MEASURE CALIBRATE
ADC3
C13TO C12 C13 TO C12
MEASURE CALIBRATE
ADC1
C7 TO C6 C7 TO C6
68131 F09
Rev. A
PULSE DENSITY
MODULATED
BIT STREAM
ANALOG 1-BIT
MUX
INPUT MODULATOR 1 DIGITAL RESULTS
FILTER 16 REGISTER
Rev. A
The CLRCELL command clears Cell Voltage Register The above algorithm detects open wires using normal
Groups A, B, C, D, E and F. All bytes in these registers are mode conversions with as much as 10nF of capacitance
set to 0xFF by CLRCELL command. remaining on the LTC6813-1 side of the open wire.
However, if more external capacitance is on the open C pin,
The CLRAUX command clears Auxiliary Register then the length of time that the open wire conversions are
Groups A, B, C and D. All bytes in these registers, except ran in steps 1 and 2 must be increased to give the 100μA
the last four registers of Group D, are set to 0xFF by current sources time to create a large enough difference
CLRAUX command. for the algorithm to detect an open connection. This can
The CLRSTAT command clears Status Register Groups A be accomplished by running more than two ADOW com-
and B except the REV and RSVD bits in Status Register mands in steps 1 and 2, or by using filtered mode conver-
Group B. A read back of REV will return the revision code sions instead of normal mode conversions. Use Table 14
of the part. RSVD bits always read back 0s. All OV and to determine how many conversions are necessary:
UV flags, MUXFAIL bit, and THSD bit in Status Register Table 14.
Group B and also in Auxiliary Register Group D are set NUMBER OF ADOW COMMANDS
to 1 by CLRSTAT command. The THSD bit is set to 0 after REQUIRED IN STEPS 1 AND 2
EXTERNAL C PIN
RDSTATB command. The registers storing SC, ITMP, VA CAPACITANCE NORMAL MODE FILTERED MODE
and VD are all set to 0xFF by CLRSTAT command. ≤10nF 2 2
100nF 10 2
Open Wire Check (ADOW Command) 1μF 100 2
The ADOW command is used to check for any open wires C 1 + ROUNDUP (C/10nF) 2
between the ADCs of the LTC6813-1 and the external
cells. This command performs ADC conversions on the Auxiliary Open Wire Check (AXOW Command)
C pin inputs identically to the ADCV command, except The AXOW command is used to check for any open wires
two internal current sources sink or source current into between the GPIO pins of the LTC6813-1 and the external
the two C pins while they are being measured. The pull- circuit. This command performs ADC conversions on the
up (PUP) bit of the ADOW command determines whether GPIO pin inputs identically to the ADAX command, except
the current sources are sinking or sourcing 100μA. internal current sources sink or source current into each
The following simple algorithm can be used to check for GPIO pin while it is being measured. The pull-up (PUP) bit
an open wire on any of the 19 C pins: of the AXOW command determines whether the current
sources are sinking or sourcing 100μA.
1. Run the 18-cell command ADOW with PUP = 1 at least
twice. Read the cell voltages for cells 1 through 18 Thermal Shutdown
once at the end and store them in array CELLPU(n).
To protect the LTC6813-1 from overheating, there is a
2. Run the 18-cell command ADOW with PUP = 0 at least thermal shutdown circuit included inside the IC. If the
twice. Read the cell voltages for cells 1 through 18 temperature detected on the die goes above approxi-
once at the end and store them in array CELLPD(n). mately 150°C, the thermal shutdown circuit trips and
3. Take the difference between the pull-up and pull-down resets the Configuration Register Groups and S Control
measurements made in above steps for cells 2 to 18: Register Group (including S control bits in PWM/S Control
CELL∆(n) = CELLPU(n) – CELLPD(n). Register Group B) to their default states. This turns off all
Rev. A
VREG
LTC6813-1
DCTEN
TIMEOUT 1
EN DTEN
DCTO ≠ 0
DISCHARGE
TIMER
OSC 16Hz CLK RST
2
(POR OR WRCFGA DONE OR TIMEOUT)
RST1
(RESETS DCTO, DCC) WDTRST && ~DCTEN
WDT
RST2
(RESETS REFUP, GPIO, VUV, VOV)
WDTPD
WATCHDOG
WDTRST
TIMER
OSC 16Hz CLK
RST
Table 16.
WATCHDOG TIMER DISCHARGE TIMER
DTEN = 0, DCTO = XXXX Resets CFGAR0-5, CFGBR0-1 and SCTRL When It Fires Disabled
DTEN = 1, DCTO = 0000 Resets CFGAR0-5, CFGBR0-1 and SCTRL When It Fires Disabled
DTEN = 1, DCTO != 0000 Resets CFGAR0-3 and GPIO Bits in CFGBR0 When It Fires Resets CFGAR4-5, SCTRL and Remainder of CFGBR0-1
When It Fires
Rev. A
Rev. A
The default values of the PWM control settings (located disable PWM discharge. With this feature, the host can
in PWM Register Group and PWM/S Control Register write the undervoltage threshold to the desired discharge
Group B) are all 1s. Upon entering sleep mode, the PWM level and use the discharge timer monitor to discharge
control settings will be initialized to their default values. all, or selected, cells (using either constant discharge or
PWM discharge) down to that level.
DISCHARGE TIMER MONITOR During discharge timer monitoring, digital redundancy
The LTC6813-1 has the ability to periodically monitor checking will be performed on the cell voltage measure-
cell voltages while the discharge timer is active. The host ments. If a digital redundancy failure occurs, all DCC bits
should write the DTMEN bit in Configuration Register will be cleared.
Group B to 1 to enable this feature.
When the discharge timer monitor is enabled and the I2C/SPI MASTER ON LTC6813-1 USING GPIOs
watchdog timer has expired, the LTC6813-1 will per- The I/O ports GPIO3, GPIO4 and GPIO5 on LTC6813-1
form a conversion of all cell voltages in 7kHz (Normal) can be used as an I2C or SPI master port to communi-
mode every 30 seconds. The overvoltage and undervolt- cate to an I2C or SPI slave. In the case of an I2C master,
age comparisons will be performed and flags will be set GPIO4 and GPIO5 form the SDA and SCL ports of the I2C
if cells have crossed a threshold. For any undervoltage interface, respectively. In the case of a SPI master, GPIO3,
cells the discharge timer monitor will automatically clear GPIO4 and GPIO5 become the CSBM, SDIOM and SCKM
the associated DCC bit in Configuration Register Group ports of the SPI interface respectively. The SPI master on
A or Configuration Register Group B so that the cell will LTC6813-1 supports SPI mode 3 (CHPA = 1, CPOL = 1).
no longer be discharged. Clearing the DCC bit will also
Rev. A
Rev. A
SDA (GPIO4)
BLANK NACK
SCL (GPIO5)
SDA (GPIO4)
START ACK
SCL (GPIO5)
SDA (GPIO4)
STOP
SCL (GPIO5)
SDA (GPIO4)
NO TRANSMIT
SCL (GPIO5)
tCLK t4 t3
(SCK)
SCKM (GPIO5)
SDIOM (GPIO4)
SCKM (GPIO5)
SDIOM (GPIO4)
SCKM (GPIO5)
Rev. A
0001
0010
0011
0100
0101
0110
0111
1XXX
Rev. A
Timing LTC6813-1
timing is depicted in Figure 16. The maximum data rate Figure 15. 4-Wire SPI Configuration
is 1Mbps; however the device is tested at a higher data
rate in production in order to guarantee operation at the
maximum specified data rate.
Rev. A
SCK
SDI D3 D2 D1 D0 D7…D4 D3
t5
CSB
t8
SDO D4 D3 D2 D1 D0 D7…D4 D3
68131 F16
PREVIOUS COMMAND CURRENT COMMAND
LTC6813-1
WAKE-UP
CIRCUIT
(ON PORT A/B)
Tx • 20 • IB IP
Tx = +1
• •
SDO Tx = 0
LOGIC RM
IM
AND Tx = –1
MEMORY SDI
PULSE
SCK ENCODER/
DECODER Rx = +1
+
CSB Rx = 0
Rx = –1 IB IBIAS
–
+ 2V
1V • RB2
– RB1
COMPARATOR THRESHOLD = ICMP
RB1 + RB2
0.5X
RB2
68131 F17
Rev. A
in the daisy chain does not use Port B, and it should be IMA
terminated into RM. Figure 18 shows the simplest port V–
GNDD
connections possible when the microprocessor and the LTC6813-1 V–
IBIAS GNDD
ure capacitors are used to couple signals between the ISOMD
LTC6813-1s. VREG
NC
NC
isoSPI. IBIAS
ISOMD
GNDC
the 1st LTC6813-1 PCB, use the LTC6820 support IC. IPA
ISOMD
Using a Single LTC6813-1 NC
NC
When only one LTC6813-1 is needed, it can be used as VREG
(2k to 20k) is required for IBIAS. Do not tie IBIAS directly CSB
V–
to VREG or V–. Finally, IPB and IMB should be terminated LTC6813-1 V–
CS CLK
SDI
VREG
VDDA
68131 F18
• •
IPB
IMB
IPA
• •
IMA
V–
LTC6813-1 V– GNDD
ICMP
IBIAS GNDD
ISOMD
VREG
IPB • •
IMB
IPA
IMA • •
V–
LTC6813-1 V– GNDC
ICMP
IBIAS GNDC
ISOMD
VDDA
LTC6820 MPU
VREG
MSTR MOSI MOSI
GNDA IBIAS MISO MISO
ICMP SCK CLK
• • GNDA GND CSB CS VDD
IPB
IMB POL VCCO
IPA PHA EN
• • • •
IMA IP SLOW
V– IM VCC
LTC6813-1 V– GNDB
ICMP
IBIAS GNDB
ISOMD
VREG
68131 F19
IBIAS GNDB
ISOMD
VREG
68131 F20
VDDA
VDD
IPB IMB SCK CSB V– V– ICMP IBIAS WDT ISOMD SDO SDI
LTC6813-1
68131 F21
Rev. A
R B2
VICMP = 2V • = IB • R B2 = 603mV The receiver is designed to detect each of these isoSPI
R B1 + R B2
pulse types. For successful detection, the incoming
VTCMP = 0.5 • VICMP = 302mV isoSPI pulses (CSB or data) should meet the following
requirements:
In this example, the pulse drive current IDRV will be 10mA,
and the receiver comparators will detect pulses with IP– 1. t1/2PW of incoming pulse > tFILT of the receiver and
IM amplitudes greater than ±302mV. 2. tINV of incoming pulse < tWNDW of the receiver
If the isolation barrier uses 1:1 transformers connected The worst-case margin (margin 1) for the first condition
by a twisted pair and terminated with 120Ω resistors on is the difference between minimum t1/2PW of the incom-
each end, then the transmitted differential signal ampli- ing pulse and maximum tFILT of the receiver. Likewise, the
tude (±) will be: worst-case margin (margin 2) for the second condition is
R the difference between minimum tWNDW of the receiver
V A = IDRV • M = 0.6V
2 and maximum tINV of the incoming pulse. These timing
relations are illustrated in Figure 22.
(This result ignores transformer and cable losses, which
may reduce the amplitude). A host microcontroller does not have to generate isoSPI
pulses to use this 2-wire interface. The first LTC6813-1 in
isoSPI Pulse Detail the system can communicate to the microcontroller using
the 4-wire SPI interface on its Port A, then daisy chain to
Two LTC6813-1 devices can communicate by transmitting other LTC6813-1s using the 2-wire isoSPI interface on its
and receiving differential pulses back and forth through an Port B. Alternatively, the LTC6820 can be used to translate
isolation barrier. The transmitter can output three voltage the SPI signals into isoSPI pulses.
levels: +VA, 0V and –VA. A positive output results from
Rev. A
–1 PULSE
Operation with Port A Configured for SPI Table 28. Port A (Slave) isoSPI Port Function
When the LTC6813-1 is operating with Port A as a SPI RECEIVED PULSE INTERNAL SPI
(ISOMD = V–), the SPI detects one of four communica- (PORT A isoSPI) PORT ACTION RETURN PULSE
tion events: CSB falling, CSB rising, SCK rising with SDI Long +1 Drive CSB High None
= 0 and SCK rising with SDI = 1. Each event is converted Long –1 Drive CSB Low
into one of the four pulse types for transmission through Short +1 1. Set SDI = 1 Short –1 Pulse
2. Pulse SCK if Reading a 0 Bit
the daisy chain. Long pulses are used to transmit CSB
Short –1 1. Set SDI = 0 (No Return Pulse if not in READ
changes and short pulses are used to transmit data, as 2. Pulse SCK Mode or if Reading a 1 Bit)
explained in Table 27.
Table 27. Port B (Master) isoSPI Port Function The slave isoSPI port never transmits long (CSB) pulses.
COMMUNICATION EVENT TRANSMITTED PULSE Furthermore, a slave isoSPI port will only transmit short
(PORT A SPI) (PORT B isoSPI) –1 pulses, never a +1 pulse. The master port recognizes
CSB Rising Long +1 a null response as a logic 1.
CSB Falling Long –1
SCK Rising Edge, SDI = 1 Short +1 Reversible isoSPI
SCK Rising Edge, SDI = 0 Short –1
When the LTC6813-1 is operating with Port A configured
for isoSPI, communication can be initiated from either
Operation with Port A Configured for isoSPI Port A or Port B. In other words, LTC6813-1 can config-
ure either Port A or Port B as slave or master, depending
On the other side of the isolation barrier (i.e., at the other on the direction of communication. The reversible isoSPI
end of the cable), the 2nd LTC6813-1 will have ISOMD = feature permits communication from both directions in
VREG so that its Port A is configured for isoSPI. The slave a stack of daisy-chained devices. See Figure 23 for an
isoSPI port (Port A or B) receives each transmitted pulse example schematic. Figure 24 illustrates the operation of
and reconstructs the SPI signals internally, as shown in reversible isoSPI.
Table 28. In addition, during a READ command this port
may transmit return data pulses.
Rev. A
• •
IPB
IMB
IPA
• •
IMA
V–
LTC6813-1 V– GNDD
ICMP
IBIAS GNDD
ISOMD
NC
NC
VREG
IPB • •
LTC6820
IMB
MSTR MOSI
IPA
GNDA IBIAS MISO
IMA • •
ICMP SCK
V–
GNDA GND CSB
LTC6813-1 V– GNDC
POL VCCO
ICMP MPU
PHA EN
IBIAS GNDC CS2
• • IP SLOW
MOSI
ISOMD
IM VCC
MISO
NC
CLK
NC LTC6820
VREG CS1
MSTR MOSI VDD
IPA PHA EN
• • • • VDDA
IMA IP SLOW
V– IM VCC
LTC6813-1 V– GNDB
ICMP
IBIAS GNDB
ISOMD
NC
NC
VREG
68131 F23
READY STATE
68131 F24
When LTC6813-1 is in SLEEP state, it will respond to a irrespective of the current state of the ports. This can be
valid WAKE-UP signal on either Port A or Port B. This is done by sending a long –1 isoSPI pulse on the master port
true for either configuration of the ISOMD pin. after a time delay of tBLOCK from the last isoSPI signal that
was transmitted by the part. Any long isoSPI pulse sent to
If the WAKE-UP signal was sent on Port A, LTC6813-1
the master port inside tBLOCK is rejected by the part. This
transmits a long +1 isoSPI pulse (CSB rising) on Port B
ensures the LTC6813-1 cannot switch ports because of
after the isoSPI is powered up. If the WAKE-UP signal was
signal reflections from poorly terminated cables (<100m
sent on Port B, LTC6813-1 powers up the isoSPI but does
cable length).
not transmit a long +1 isoSPI pulse on Port A.
When LTC6813-1 is in READY state, communication can Timing Diagrams
be initiated by sending a long –1 isoSPI pulse (CSB fall- Figure 25 shows the isoSPI timing diagram for a READ
ing) on either Port A or Port B. The LTC6813-1 automati- command to daisy-chained LTC6813-1 parts. The ISOMD
cally configures the port that receives the long –1 isoSPI pin is tied to V– on the bottom part so its Port A is config-
pulse as the slave and the other port is configured as the ured as a SPI port (CSB, SCK, SDI and SDO). The isoSPI
master. The isoSPI pulses are transmitted through the signals of three stacked devices are shown labeled with
master port to the rest of the devices in the daisy chain. the port (A or B) and part number. Note that ISO B1 and
In ACTIVE state, the LTC6813-1 is in the middle of com- ISO A2 is actually the same signal, but shown on each
munication and CSB of the internal SPI port is low. At end of the transmission cable that connects Parts 1 and 2.
the end of communication a long +1 pulse (CSB rising) Likewise, ISO B2 and ISO A3 is the same signal, but with
on the SLAVE port returns the part to the READY state. the cable delay shown between Parts 2 and 3.
Although it is not part of a normal communication routine, Bits WN–W0 refer to the 16-bit command code and the
the LTC6813-1 allows ports A and B to be swapped inside 16-bit PEC of a READ command. At the end of Bit W0,
the ACTIVE state. This feature is useful for the master con- the three parts decode the READ command and begin
troller to reclaim control of the slave port of LTC6813‑1 shifting out data, which is valid on the next rising edge
Rev. A
CSB t7 t6 t5
t1
SDI t2
tCLK
SCK t4 t3
t8
t11
tRISE
SDO Xn Xn-1 Z0
t10 t9 t10
Wn W0 Yn Yn-1
ISO B1
Wn W0 Yn Yn-1
ISO A2
tRTN
tDSY(CS) tDSY(CS)
tDSY(D)
Wn W0 Zn Zn-1
ISO B2
Wn W0 Zn Zn-1
ISO A3
69131 F25
0 1000 2000 3000 4000 5000 6000
Rev. A
REJECTS COMMON
MODE NOISE
CSB OR IMA
SCK OR IPA
VWAKE = 200mV
|SCK(IPA) - CSB(IMA)|
tDWELL= 240ns
WAKE-UP
RETRIGGERABLE
CSB OR IMA tDWELL = 240ns tIDLE = 5.5ms WAKE-UP
SCK OR IPA DELAY ONE-SHOT 68131 F26
Rev. A
Rev. A
I/P
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
68131 F27
Rev. A
SCK
SDO
68131 F28
CSB
SCK
SDO
Rev. A
SCK 1 2 N
SDO
68131 F30
CSB
SCK 1 2 N
SDO
68131 F31
CONVERSION DONE
Rev. A
Command Format: The format for the commands is shown in Table 35. CC[10:0] is the 11-bit command code. A list of
all the command codes is shown in Table 36. All commands have a value 0 for CMD0[7] through CMD0[3]. The PEC
must be computed on the entire 16-bit command (CMD0 and CMD1).
Table 35. Command Format
NAME RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CMD0 WR 0 0 0 0 0 CC[10] CC[9] CC[8]
CMD1 WR CC[7] CC[6] CC[5] CC[4] CC[3] CC[2] CC[1] CC[0]
Rev. A
Rev. A
Rev. A
Rev. A
Rev. A
Rev. A
Rev. A
Rev. A
Rev. A
Rev. A
120V
V+ VREG
1 48
C18 GPIO9
2 47
S18 GPIO8
3 46
C17 GPIO7
4 45
S17 GPIO6
5 44
24V
C16 GPIO5
6 43
S16 GPIO4
7 42
C15 GPIO3
8 41
LTC6813-1 GPIO2
S15
9 40
GPIO1
10 C14 39
S14 C0
11 38
24V
C13 S1
12 37
S13 C1
13 36
C12 24V S2
14 35
C11 S3
16 33
100Ω
CELL2 C2
BSS308PE 3.3k
S2
33Ω
10nF LTC6813-1
100Ω
CELL1 C1
BSS308PE 3.3k
S1
33Ω
10nF
100Ω
C0
10nF
BATTERY V– V–
100Ω
CELL2 C2
BSS308PE 3.3k
S2
33Ω
C * LTC6813-1
100Ω
CELL1 C1
BSS308PE 3.3k
S1
33Ω C
*
100Ω
C0
C
*
BATTERY V– V–
68131 F35
*6.8V ZENERS RECOMMENDED IF C ≥ 100nF
Rev. A
5 5
CELL MEASUREMENT ERROR (mV)
0 0
–5 –5
–10 –10
100nF 100nF
10nF 10nF
1µF 1μF
–15 –15
100 1k 10k 100 1k 10k
INPUT RESISTANCE, R (Ω) INPUT RESISTANCE, R (Ω)
68131 F36a 68131 F36b
(b) ADCV (C1/C7/C13) DELAY 6Τ ADCV (ALL CELLS) CNV TIME RDCVA-F
(c) ADCV (ALL CELLS) CNV TIME RDCVA-F ADCV (C1/C7/C13) DELAY 6τ
68131 F37
S(n)
balancing to correct large SOC imbalances in short peri-
CFILTER ods of time. The excessive heat created during balancing
RFILTER
C(n – 1)
generally limits the balancing current. In large capacity
battery applications, if short balancing times are required,
(a) Internal Discharge Circuit an active balancing solution should be considered. When
choosing a balance resistor, the following equations can
C(n) LTC6813-1 be used to help determine a resistor value:
BSS308PE
+ 3.3k
Balance Current =
S(n) %SOC_Imbalance • Battery Capacity
Number of Hours to Balance
RDISCHARGE
C(n – 1) Balance Resistor =
68131 F38
Nominal Cell Voltage
(b) External Discharge Circuit
Balance Current
Figure 38. Internal/External Discharge Circuits
Rev. A
Rev. A
Rev. A
RFILTER LTC6813-1
C(n)
+ RDISCHARGE 1k
S(n)
CFILTER
RFILTER
C(n–1)
+ 3.3k
S(n)
RDISCHARGE2
RFILTER
C(n–1)
68131 F40
Rev. A
/************************************
Copyright 2012 Analog Devices, Inc. (ADI)
Permission to freely use, copy, modify, and distribute this software for any purpose with or
without fee is hereby granted, provided that the above copyright notice and this permission
notice appear in all copies: THIS SOFTWARE IS PROVIDED “AS IS” AND ADI DISCLAIMS ALL WARRANTIES
INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL ADI BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM ANY
USE OF SAME, INCLUDING ANY LOSS OF USE OR DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
OR OTHER TORTUOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
***************************************/
int16 pec15Table[256];
int16 CRC15_POLY = 0x4599;
void init_PEC15_Table()
{
for (int i = 0; i < 256; i++)
{
remainder = i << 7;
for (int bit = 8; bit > 0; --bit)
{
if (remainder & 0x4000)
{
remainder = ((remainder << 1));
remainder = (remainder ^ CRC15_POLY)
}
else
{
remainder = ((remainder << 1));
}
}
pec15Table[i] = remainder&0xFFFF;
}
}
unsigned int16 pec15 (char *data , int len)
{
int16 remainder,address;
remainder = 16;//PEC seed
for (int i = 0; i < len; i++)
{
address = ((remainder >> 7) ^ data[i]) & 0xff;//calculate PEC table address
remainder = (remainder << 8 ) ^ pec15Table[address];
}
return (remainder*2);//The CRC15 has a 0 in the LSB so the final value must be multiplied by 2
}
Rev. A
ISOLATION BARRIER
(MAY USE ONE OR TWO TRANFORMERS)
0.8
is recommended. The circuit example in Figure 43 shows
0.6
the use of common mode chokes (CMC) to add common
0.4 mode noise rejection from transients on the battery lines.
The use of a center tapped transformer will also provide
0.2 additional noise performance. A bypass capacitor con-
0
nected to the center tap creates a low impedance for com-
1 10 100 mon mode noise (Figure 43b). Since transformers without
CABLE LENGTH (METERS)
68131 F42 a center tap can be less expensive, they may be preferred.
Figure 42. Data Rate vs Cable Length In this case, the addition of a split termination resistor
and a bypass capacitor (Figure 43a) can enhance the
of cable delay. For longer cables, the minimum timing isoSPI performance. Large center tap capacitors greater
parameters may be calculated as shown below: than 10nF should be avoided as they may prevent the
tCLK, t6 and t7 > 0.9μs + 2 • tCABLE (0.2m per ns) isoSPI common mode voltage from settling. Common
mode chokes similar to those used in Ethernet or CANbus
Implementing a Modular isoSPI Daisy Chain applications are recommended. Specific examples are
provided in Table 59.
The hardware design of a daisy-chain isoSPI bus is identi-
cal for each device in the network due to the daisy-chain An important daisy chain design consideration is the num-
point-to-point architecture. The simple design as shown in ber of devices in the isoSPI network. The length of the
Figure 41 is functional, but inadequate for most designs. chain determines the serial timing and affects data latency
The termination resistor RM should be split and bypassed and throughput. The maximum number of devices in an
with a capacitor as shown in Figure 43. This change pro- isoSPI daisy chain is strictly dictated by the serial timing
vides both a differential and a common mode termination, requirements. However, it is important to note that the
and as such, increases the system noise immunity. serial read back time, and the increased current consump-
tion, might dictate a practical limitation.
IP
XFMR For a daisy chain, two timing considerations for proper
100pF 49.9Ω 100µH CMC
• • operation dominate (see Figure 25):
•
1. t6, the time between the last clock and the rising chip
•
10nF 51Ω
IM 10nF equations for these times are below:
V–
t5 > (#devices • 70ns) + 900ns
68131 F43
(b)
t6 > (#devices • 70ns) + 950ns
Figure 43. Daisy Chain Interface Components
Rev. A
IPB
49.9Ω
LTC6813-1
10nF
49.9Ω
GNDD
IMB
1k 1k
IBIAS
ICMP GNDD
IPA
49.9Ω
10nF
49.9Ω GNDD
GNDD 10nF*
V– IMA
•
GNDD
•
10nF*
GNDC
IPB
49.9Ω
LTC6813-1
10nF
49.9Ω
GNDC
IMB
1k 1k
IBIAS
ICMP GNDC
IPA
49.9Ω
10nF
49.9Ω GNDC
GNDC 10nF*
V– IMA
•
GNDC
•
10nF*
GNDB
IPB
49.9Ω
LTC6813-1
10nF
49.9Ω
GNDB
IMB
1k 1k
IBIAS
ICMP GNDB LTC6820
IPA • • IP
49.9Ω 10nF* 10nF* 49.9Ω 1k 1k
IBIAS
10nF 10nF ICMP
49.9Ω GNDB GNDA 49.9Ω GNDA
GNDB GNDA
V–
IMA IM V–
ACT45B-101-2P-TL003
IPB
LTC6813-1 49.9Ω 10nF 10nF
•
•
49.9Ω 10nF
GNDB
IMB
1k 1k
IBIAS
ICMP GNDB
IPA
49.9Ω 10nF
V– 49.9Ω
GNDB
IMA
GNDB ACT45B-101-2P-TL003
IPB
LTC6813-1 49.9Ω 10nF 10nF
•
•
49.9Ω 10nF
GNDA
IMB
1k 1k
IBIAS
ICMP GNDA
IPA
49.9Ω 10nF
V– 49.9Ω
GNDA
IMA
GNDA
68131 F45
Rev. A
IPB
• •
LTC6813-1 49.9Ω 10nF*
10nF
49.9Ω GNDB
GNDB
IMB
1k 1k
IBIAS
ICMP
IPA IP
• •
LTC6820
49.9Ω 10nF* 49.9Ω
1k 1k
IBIAS
10nF 10nF ICMP
10nF* GNDA
49.9Ω GNDB 49.9Ω
GNDB GNDA GNDA
V– IMA IM V–
GNDB GNDA
* IF TRANSFORMER BEING USED HAS A CENTER TAP, IT SHOULD BE BYPASSED WITH A 10nF CAP 68131 F46
Figure 46. Interfacing an LTC6813-1 with a μC Using an LTC6820 for Isolated SPI Control
Rev. A
Rev. A
V+ V+
C18 C18
S18 S18
C17 C17
S17 S17
C16 C16
S16 S16
C15 C15
S15 S15
C14 C14
S14 S14
C13 C13
S13 S13
C12 C12
S12 S12
C11 C11
S11 S11
C10 C10
S10 S10
16-CELL C9 LTC6813-1 14-CELL C9 LTC6813-1
MODULE S9 MODULE S9
C8 C8
S8 S8
C7 C7
S7 S7
C6 C6
S6 S6
C5 C5
S5 S5
C4 C4
S4 S4
C3 C3
S3 S3
C2 C2
S2 S2
C1 C1
S1 S1
C0 C0
V– V–
68131 F47
LEM DHAB
A
CH2 ANALOG → GPIO2
B
VCC 5V
C
GND ANALOG_COM → V–
D
CH1 ANALOG0 → GPIO1
68131 F48
Figure 48. Interfacing a Typical Hall-Effect Battery Current Sensor to Auxiliary ADC Inputs
Rev. A
VTEMPx (% VREF2)
10k
cell voltage and cell current measurements. 60
VTEMP 50
NTC 40
READING EXTERNAL TEMPERATURE PROBES 10k AT 25°C
30
V–
Figure 49 shows the typical biasing circuit for a negative 20
Rev. A
ADG728 –
ANALOG9 S1 VDD 100Ω
ANALOG10 S2 GND LTC6255 GPIO1
ANALOG11 S3 A0 + 68131 F50
ANALOG12 S4 A1 10nF
ANALOG13 S5 SCL
ANALOG14 S6 SDA
ANALOG15 S7 D
ANALOG16 S8 RESET
Rev. A
10.15 – 10.25
7.50 REF
64 49
1 48
0.50 BSC
5.74 ±0.05
7.50 REF
0.20 – 0.30
10.15 – 10.25
5.74 ±0.05
16 PACKAGE OUTLINE 33
17 32
1.30 MIN
12.00 BSC
10.00 BSC 5.74 ±0.10
64 49 49 64
SEE NOTE: 3
1 48 48 1
12.00 BSC
16 33 33 16
C0.30 – 0.50
17 32 32 17
BOTTOM OF PACKAGE—EXPOSED PAD (SHADED AREA) 1.60
11° – 13° 1.35 – 1.45 MAX
R0.08 – 0.20 GAUGE PLANE
0.25
0° – 7°
SECTION A – A
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS 3. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
2. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH 4. DRAWING IS NOT TO SCALE
SHALL NOT EXCEED 0.25mm (10 MILS) BETWEEN THE LEADS AND
MAX 0.50mm (20 MILS) ON ANY SIDE OF THE EXPOSED PAD, MAX 0.77mm
(30 MILS) AT CORNER OF EXPOSED PAD, IF PRESENT
Rev. A
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For more by
is granted information www.analog.com
implication or otherwise under any patent or patent rights of Analog Devices. 87
LTC6813-1
TYPICAL APPLICATION
100Ω
100nF 10nF
100Ω
V+ DRIVE NPN
10Ω
C18 VREG 1μF
+ C18 100nF
3.7V 33Ω
S18 VREF1
1μF
10Ω
C17
+ C17 100nF VREF2
3.7V 33Ω
S17 1μF
CELL3
TO CELL16 IPB
•
•
CIRCUITS LTC6813-1 100Ω
10Ω
C2 IMB
100nF
+ C2 33Ω IPA
3.7V S2
•
•
10Ω 100Ω
C1
100nF IMA
+ C1 33Ω 1k 1k
3.7V S1 IBIAS
10Ω
C0 ICMP
–
V ISOMD VREG
68131 TA02
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC6811-1/ 4th Generation 12-Cell Battery Stack Measures Cell Voltages for Up to 12 Series Battery Cells. Daisy-Chain Capability Allows
LTC6811-2 Monitor and Balancing IC Multiple Devices to Be Connected to Measure Many Battery Cells Simultaneously Via the
Built-In 1MHz, 2-Wire Isolated Communication (isoSPI). Includes Capability for Passive Cell
Balancing.
LTC6820 isoSPI Isolated Communications Provides an Isolated Interface for SPI Communication Up to 100 Meters, Using a Twisted
Interface Pair. Companion to the LTC6804, LTC6806, LTC6811, LTC6812 and LTC6813.
LTC6812-1 4th Generation 15-Cell Battery Stack Measures Cell Voltages for Up to 15 Series Battery Cells. The isoSPI Daisy-Chain Capability
Monitor and Balancing IC Allows Multiple Devices to Be Interconnected to Measure Many Battery Cells Simultaneously.
The isoSPI Bus Can Operate Up to 1MHz and Can Be Operated Bidirectionally for Fault
Conditions, Such As a Broken Wire or Connector. Includes Internal Passive Cell Balancing
Capability of Up to 200mA.
Rev. A
88
03/19
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For more information www.analog.com ANALOG DEVICES, INC. 2018-2019