P
P
L
L
L
L
F
F
r
r
e
e
q
q
u
u
e
e
n
n
c
c
y
y
S
S
y
y
n
n
t
t
h
h
e
e
s
s
i
i
z
z
e
e
r
r
s
s
:
:
P
P
h
h
a
a
s
s
e
e
N
N
o
o
i
i
s
s
e
e
I
I
s
s
s
s
u
u
e
e
s
s
a
a
n
n
d
d
W
W
i
i
d
d
e
e


b
b
a
a
n
n
d
d
L
L
o
o
o
o
p
p
s
s
Thesis work
March J996  June J999
Coaboration
contract between
Phips
Semiconductors Caen
&
INSA de Lyon
0DULQDGH4XHLUR]7DYDUHV
N
o
d’ordre: 99 ISAL 086 Année 1999
THESE
présentée
DEVANT L’INSTITUT NATIONAL DES SCIENCES APPLIQUEES DE LYON
pour obtenir
LE GRADE DE DOCTEUR
FORMATION DOCTORALE: Dispositifs de l’électronique intégrée
ECOLE DOCTORALE: Electronique, Electrotechnique, Automatique (EEA)
par
Marina, de Queiroz Tavares
SYNTHETISEUR DE FREQUENCE A BOUCLE DE VERROUILLAGE DE PHASE:
ETUDE DU BRUIT DE PHASE ET DE BOUCLES A LARGE BANDE
Soutenue le 09/Décembre/1999 devant la Commission d’Examen
Jury
RichardGRISEL Professeur  Université Picardie rapporteur
MichielSTEYAERT Professeur  K.U. Leuven rapporteur
JeanPierreCHANTE Professeur  INSA de Lyon directeur
BrunoALLARD Maître de Conférences  INSA de Lyon examinateur
PhilippeKLAEYLE Ingénieur  Philips Semiconductors  Caen examinateur
EduardStikvoort Chercheur  ingénieur – Philips Nat.Lab. – Eindhoven examinateur
Cette thèse a été préparée chez Philips Semiconductors – Caen, en collaboration avec le
Laboratoire CEGELY de l’INSA de Lyon
Title: PLL Frequency Synthesizers:
Phase Noise Issues and Wide Band Loops
Keywords: frontend/ tuners / PLL / phase noise / stability / gmC oscillators
Abstract:
PLL frequency synthesizers are widely used in telecommunication receivers and transmitters, as
part of the frequency conversion block. They consist of a tunable oscillator and a programmable
phase controlling loop.
Current tendencies in PLL development focus noise performance and a higher integration level.
The first is connected to the new digital modulation techniques, often demanding a higher CNR
in the signal chain. And the second concerns a global trend towards smaller and more compact
systems.
This thesis discusses and develops PLL system models to study stability and noise aspects. The
model results are employed in IC and application design, being confirmed via measurements.
The stability approach investigates the robustness of the PLL system, typically working with
very large gain variations. A topdown system to circuit approach, studies noise generation and
transmission. Finally testchip realizations of PLLs with fully gmC integrated oscillators are
presented.
The thesis was conducted within the context of a collaboration between the CEGELYINSA de
Lyon and Philips Semiconductors, more specifically in the production and development centre of
Caen.
PhD student:
Marina de Queiroz Tavares
Advisor:
Prof. JeanPierre Chante
Director of the CEGELY laboratory
ii PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Contents:
Index ii
List of figures v
List of Tables viii
List of symbols and abbreviations ix
Preface xiv
1. Introduction 1
1.1. The frontend in a telecommunication receiver 2
1.2. The frontend in TV broadcasting 3
1.3. Current tendencies: low noise and higher integration 9
1.4. PLL systems : different application contexts 14
1.5. PLL frequency synthesizers constituting blocks and nomenclature 15
1.5.1. VCO 16
1.5.2. Dividers 17
1.5.3. Phase Detector – Charge Pump 17
1.5.4. Loop Filter 19
2. PLL Phase Model and Loop Filter calculation 21
2.1. Phase Model for PLL synthesizers 22
2.1.1. Requirements in the Time and Frequency Domain 24
2.1.2. SecondOrder Loop 26
2.1.3. Third and Fourth Order Loop 28
2.2. Algorithm for Loop Filter Calculation 34
2.2.1. Nominal Design 34
2.2.2. Robust design including Gain Variation and 3
rd
Pole compensation 36
2.2.3. Summary steps and numerical example 40
3. Application Related Constraints 43
3.1. Reference Breakthrough 44
3.2. VCO Noise Representation and Phase Noise Units 46
3.3. Optimum Closed Loop Bandwidth 50
3.4. PLL Closed Loop Bandwidth 52
3.4.1. w
3dB
derivation from B
RL
(s) 53
3.4.2. w
3dB
derivation from w
as
59
3.5. Maximum Phase Jitter 61
3.6. Gain Stability Boundary 65
Contents iii
4. Active Loop Filters: AC & disturbances issues 69
4.1. Nonideal Filter Impedances 70
4.1.1. Fully 3
rd
order passive filter 71
4.1.2. Amplifier AC characteristics 72
4.1.3. Amplifier with single pole 74
4.1.4. Numerical example 76
4.1.5. Input impedance: Zin 79
4.1.6. Summary of AC boundaries for filter design 80
4.2. Disturbances and Noise Propagation 80
4.2.1. Random Electrical Noise 81
4.2.2. Supply Disturbances 82
4.2.3. Amplifier Noise 82
4.2.4. Filter Components Noise 83
4.2.5. Transfer functions table 84
4.2.6. Simulation Example 85
5. Limitations of the LTI Phase Model 89
5.1. Threestate comparator: frequency and phase detector 91
5.1.1. Minimum phase deviation range 92
5.2. DC range limitations 94
5.2.1. Loop filter time domain response 94
5.2.2. Numerical examples and design considerations 96
5.3. Lock convergency approaches 99
5.3.1. Frequency approach 100
5.3.2. Phase approach 103
5.3.3. Comparing the frequency and phase approaches: 105
5.4. Discrete trasfers for the PLL Phase Model 109
5.4.1. The sampler 109
5.4.2. The holder 111
5.4.3. Continuous equivalent with transmission delay 114
6. Phase Noise: theoretical to practical approach 119
6.1. Electrical Noise: random sources representation & measurements 120
6.1.1. Electrical noise as a random process 121
6.1.2. Measuring Phase Noise 123
6.2. Phase Noise Notations 125
6.2.1. Interchanging Modulation Types 125
6.2.1.1. Angular modulation 127
6.2.2. Phasors Notations 128
6.2.3. Slope approach 133
6.3. Large Signal Linearization 135
6.3.1. Time and Frequency representation 135
6.3.2. Linear Time Variable transfer 136
iv PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
7. Phase Noise in the PLL context 141
7.1. Translating the SNF into phase, time, voltage and current noise 143
7.2. Sampling effects: SNF x f
cp
147
7.2.1. Narrow bandwidth noise sources 149
7.2.2. Large bandwidth noise sources 151
7.3. Detailing noise sources in different PLL blocks 154
7.3.1. Dflip flop 154
7.3.2. Charge Pump 158
7.4. Behavioural Models 159
7.4.1. Frequency domain 159
7.4.2. Time domain 160
7.5. Implementation Loss due to Phase Deviations 162
7.5.1. Signal to noise ratio and implementation loss 163
7.5.2. Digital Demodulator: clock and carrier recovery loops 167
8. Testchips Realized 169
8.1. GmC oscillator 170
8.1.1. Structure 171
8.1.2. Results 172
8.2. TC2 : MixerOscillatorPLL circuit for satellite direct conversion 173
8.2.1. Double Loop Synthesizer 173
8.2.2. TC2 structure 175
8.2.3. TC2: results 177
8.3. TC3 : single PLL plus QCCO circuit 180
8.4. Comparative analysis: phase jitter and implementation loss 183
8.4.1. Configurations compared 183
8.4.2. Conditions for the simulations 184
8.4.3. Results and conclusions 187
9. Conclusion 191
Bibliography 193
List of Figures v
List of figures
Chapter 1
Figure 1.1 Communication transceiver: TX and RX systems 2
Figure 1.2 Heterodyne Receiver _ Terrestrial TV Frontend 4
Figure 1.3 DVB Satellite transmission modes 6
Figure 1.4 Satellite Receiver Frontend: heterodyne and ZIF architectures 7
Figure 1.6 Local Oscillator Spectral Purity X SNR 9
Figure 1.7 Carrier Spectrum 10
Figure 1.8 QPSK constellation + phase deviation 11
Figure 1.9 Phase Noise requirements 12
Figure 1.10 PLL frequency synthesizer: block diagram 16
Figure 1.11 VCO and tunable resonator 16
Figure 1.12 Phase Detector & Charge Pump block diagram 18
Figure 1.13 Phase detector & Charge pump: transfer and state machine 19
Chapter 2
Figure 2.1 PLL linear Phase Model 23
Figure 2.2 V
tune
time response for a frequency step 25
Figure 2.3 Locked VCO output spectrum 25
Figure 2.4 3
rd
order Loop Filter Impedance 29
Figure 2.5 4
th
order PLL: Open and Closed Loop Bode Plots 31
Figure 2.6 4
th
order PLL: Root Locus diagram 31
Figure 2.7 Gain Variation X Stability in Bode Plots 33
Figure 2.8 The influence of r
21
in the gainbandwidth variation 36
Figure 2.9 Numerical example of robust filter design 42
Chapter 3
Figure 3.1 BB noise representation of the VCO 47
Figure 3.2 Free running VCO power spectrum density 49
Figure 3.3 PSD of a VCO locked by a PLL 49
Figure 3.4 Peaking X Optimum Closed Loop bandwidth 50
Figure 3.5 Combined Spectrum: PLL + VCO noise contributions 52
Figure 3.6 Rootlocus for w
3dB
location 58
Figure 3.7 Rootlocus for was location 60
Figure 3.8 Optimizing Total Phase Deviation 63
Figure 3.9 Maximum SSB noise requirement 64
Chapter 4
Figure 4.1 Active Loop Filter 70
Figure 4.2 Fully 3
rd
order passive filter impedance 72
Figure 4.3 Active Filter AC model 73
Figure 4.4 Loop rootlocus with active filter 75
Figure 4.5 Active Filter example: Bode plots 77
Figure 4.6 Active filter: input impedance 79
vi PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Figure 4.7 Supply disturbances 82
Figure 4.8 Amplifier noise 83
Figure 4.9 Filter components noise 83
Figure 4.10 Noise simulation schematic 85
Figure 4.11 Noise simualtion results 86
Chapter 5
Figure 5.1 Phasedetector & Charge Pump transfer 91
Figure 5.2 Maximum Phase Detection Range & Cycle slips 92
Figure 5.3 Condition for unlimited frequency tracking range 93
Figure 5.4 Loop Filter: time response for current pulses 94
Figure 5.5 Time response through normalized functions 96
Figure 5.6 Convergence towards lock: phase deviation sequence 99
Figure 5.7 Frequency approach convergence criterion 103
Figure 5.8 Phase approach convergence criterion 104
Figure 5.9 Comparing frequency and phase approaches 105
Figure 5.10 Convergence approaches X leadlag spacing r
21
107
Figure 5.11 Convergence approaches X gain variation 108
Figure 5.12 Discrete model for digital blocks 110
Figure 5.13 Discrete phase detector input: ∆ϕ
n
111
Figure 5.14 Charge Pump DAC output 112
Figure 5.15 Continuous equivalent with transmission delay 114
Figure 5.16 Frequency and Time response for the continuous+delay model 115
Chapter 6
Figure 6.1 Spectrum Analyzer Output 124
Figure 6.2 FM & PM carriers 128
Figure 6.3 SSB superposed noise: AM + PM decomposition (phasor) 129
Figure 6.4 Superposed Noise: AM + PM decomposition (spectrum) 130
Figure 6.5 Phase modulated carrier by DSB superposed noise 131
Figure 6.6 Phase deviation from DSB sidebands 132
Figure 6.7 Slope approach: voltage & time deviations 133
Figure 6.8 Periodic transfer determined by a large signal 136
Figure 6.9 Large Signal Transfer: ideal and hyperbolictangent limitations 138
Chapter 7
Figure 7.1 PLL block diagram with signal+noise inputs 142
Figure 7.2 Noise Transfer Slopes 143
Figure 7.3 Synthesizer Noise Floor 144
Figure 7.4 Sampled Loop Model 148
Figure 7.5 Large bandwidth noise folding 152
Figure 7.6 DFF plus superposed noise in the clock input: time domain signals 155
Figure 7.7 DFF plus superposed noise in the clock input: frequency domain signals 155
List of Figures vii
Figure 7.8 Charge Pump current noise levels within one period 158
Figure 7.9 Behavioural model for AC and noise simulations 160
Figure 7.10 Behavioural model for transient simulations 161
Figure 7.11 Digital Demodulator and Decoder 162
Figure 7.12 Noise Power added by the LO sidebands 164
Figure 7.13 Behavioural Model of the Carrier Recovery loop 167
Chapter 8
Figure 8.1 GmC integrated oscillator 171
Figure 8.2 Double loop MOPLL: block diagram 174
Figure 8.3 Block diagram of TC2 176
Figure 8.4 Photo of a testchip TC2 177
Figure 8.5 TC2 _ inloop spectrum for N1=7 and f
cp1
=300Mhz 179
Figure 8.6 TC2 _outofloop spectrum for N1=6 and f
cp1
=300MHz 179
Figure 8.7 TC3 _ single low noise PLL plus QCCO 181
Figure 8.8 Simulation result for the SSB phase noise _ linear scale 182
Figure 8.9 Spectra for ∆f
step
=125kHz and f
lo
=900MHz 186
Figure 8.10 Phase noise simulation for DL+QCCO with and without demodulator 186
viii PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
List of tables
Chapter 1
Table 11 DVB standards: bandwidth and modulation types 10
Chapter 2
Table 21 2
nd
order filter: Phase Margin Variation for w
ol
∈ [ w
z1
, w
p2
] 37
Table 22 3
rd
order filter: Phase Margin Variation for w
ol
∈ [ w
z1
, w
p2
] 38
Table 23 3
rd
order filter : Open Loop Bandwidth recentering 39
Chapter 3
Table 31 Comparing the denominators of B(s) and B
RL
(s) 54
Table 32 Rootlocus approach for w
cl
: parameters of B
RL
(s) 58
Table 33 Gain Stability Boundary 65
Table 34 Maximum Normalized Gain Variation 66
Chapter 4
Table 41 Fully 3
rd
order passive filter: ∆PhM and ∆GM 72
Table 42 Active Filter example: Phase Margin degradation 78
Table 43 Disturbances transfer functions 84
Table 44 Noise sources voltage spectrum density 87
Chapter 6
Table 61 Phase Modulated Carrier 126
Table 62 Phase Noise X CNR 132
Chapter 7
Table 71 Data sheet points from: TSA5059  low noise PLL 145
Table 72 The influence of fcp change for narrow band noise 151
Table 73 The influence of fcp change for large band noise 153
Table 74 Implementation Loss X Phase deviations 166
Chapter 8
Table 81 Measurements of the frequency coverage of the QCCO 172
Table 82 Double Loop: minimum step and comparison frequencies. 175
Table 83 Parameters of the two zeroIF configurations being compared 183
Table 84 Parameters and outputs for comparative analysis 184
Table 85 Settings of the demodulator block 185
Table 86 Phase Jitter and implementation loss for r
s
=30Msps and f
LO
= 2,2GHz 188
Table 87 Phase Jitter and implementation loss for r
s
=3Msps and ∆f
step
= 125kHz 188
Table 88 Margin for degradations in the oscillators phase noise performance 189
List of Symbols and Abbreviations ix
List of Symbols and Abbreviations
Symbols
α: gain of the open loop transfer function [A.Hz/V]
α
n
: nominal gain value for loop filter calculation [A.Hz/V]
α
npf
: nominal gain value after the compensation wrt the postfilter [A.Hz/V]
δϕ
i
: phase noise density [rad/sqrt(Hz)]
δi
i
: current noise density [A/sqrt(Hz)]
δt
i
: time noise density [s/sqrt(Hz)]
δv
i
: voltage noise density [V/sqrt(Hz)]
∆ϕ: phase deviation or phase error [rad]
∆ϕ
n
(nT): phase deviation as a discrete variable [rad]
∆Ψ
n
(w): Fourier transform of ∆ϕ
n
(nT)
∆ϕ
p
: peak value of a phase deviation [rad]
∆f
step
: minimum tuning step of a synthesizer [Hz]
ϕ
div
: phase of the main divider output [rad]
ϕ
e
: phase error at the phase detector input [rad]
ϕ
m
: phase of the single tone modulating signal v
m
(t) [rad]
ϕ
n
: phase of the single tone noise component v
n
(t) [rad]
ϕ
osc
: phase of the controlled oscillator [rad]
ϕ
ref
: phase of the reference input [rad]
ξ: ksi, damping factor, dimensionless
σ
ϕ
: total phase deviation [rad or °]
τ: time delay [s]
τ
rst
: time delay for the reset of the phase detector [s]
θ
n
(t): phase modulating noise
A
c
: amplitude of the carrier signal [V]
A
m
: amplitude of the modulating signal [V]
a
n
(t): amplitude modulating noise
A
n
: amplitude of a single tone noise component, v
n
(t) [V]
A
s
: amplitude of the spurious sidebands wrt the carrier amplitude [dBc]
B(s): closed loop transfer function ϕ
osc
/ϕ
ref
, dimensionless
B
RL
(s): approximation of B(s) derived from the root locus
B
vco
(s): closed loop transfer function ϕ
osc
/v
nvco
[rad/V]
B
vcoBPF
(s): bandpass filter approximation for B
vco
(s) [rad/V]
B
3LPF
(s): 3
rd
order lowpass filter approximation for B(s)
D
B
(s): denominator of the closed loop transfer function B(s)
D
G
(s): denominator of the transconductance of the loop amplifier
D
s
(s): denominator of Z
s
(s)
F(s): loop filter transfer function in Laplace variable [Ω]
f
i
: intersection frequency for the PLL and VCO noise asymptotes [Hz]
f
c
: carrier frequency [Hz]
f
cl
: bandwidth of the closed loop transfer function B(s) [Hz]
x PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
f
cp
: comparison frequency at the phase detector [Hz]
f
j
, F
j
: frequency of j [Hz]
f
m
: frequency of the modulating signal [Hz]
f
n
: frequency of a single tone noise component, v
n
(t) [Hz]
f
no
: offset frequency of v
n
(t) wrt the carrier [Hz]
f
offset
: frequency increment with respect to the frequency of a reference signal [Hz]
f
ol
: zerocrossing frequency for the open loop transfer function H(s) [Hz]
f
oln
, f
olnpf
: frequencies related to w
oln
and w
olnpf
[Hz]
f
osc
: frequency of the controlled oscillator [Hz]
f
recover
: intersection between flicker and white noise contributions of a transistor [Hz]
f
p2
, f
p3
: frequencies of 2
nd
and 3
rd
poles of the loop filter [Hz]
f
z1
: frequency of the zero of the loop filter [Hz]
f
3dB
: 3dB attenuation frequency for the closed loop transfer function B(s) [Hz]
G
ChPZOH
(s): transfer function of the charge pump as a ZOH [A/rad]
G
ChPpw
(s): transfer function of the charge pump as a holder with T
w
delay [A/rad]
g
frap
: function expressing the maximum f
cl
, derived from the frequency approach
g
phap
: function expressing the maximum f
cl
, derived from the phase approach
gm: transconductance [Ω
1
]
Gmo: DC value of the transconductance of the loop amplifier
Gvo: DC value of the voltage gain of the loop amplifier
g(x,r
21
): function expressing the time response of v
tune
, dimensionless
h
PLS
(t), H
PLS
(f): transfer function related to a periodic large signal
H(s): open loop transfer function ϕ
div
/ϕ
e
, dimensionless
I
average
: average current at the output of the charge pump [A]
I
cp
: charge pump current [A]
I
leakage
: leakage current at the tuning input [A]
I
ZOH
(w), i
ZOH
(t): output of the charge pump for a ZOH approach [A]
I
pw
(w), i
pw
(t): output of the charge pump with a delay equals T
w
[A]
i
ni
, I
ni
: current noise density from component i [A/sqrt(Hz)]
K
ϕ
: sensitivity of the phase detector plus charge pump comparator [A/rad]
K
cco
: frequency sensitivity of a currentcontrolled oscillator [Hz/A]
K
o
: VCO frequency sensitivity [rad/(s.V)]
Kvco: VCO frequency sensitivity [Hz/V]
L(f), L
dB
(f): singleside band phase noise [1/Hz, dBc/Hz]
L
pll
(f): L(f) in the inloop zone of a locked VCO spectrum [dBc/Hz]
L
vco
(f): L(f) of the freerunning oscillator [dBc/Hz]
n
lim
: aliasing factor related to the sampling of large bandwidth noise, dimensionless
N: PLL main divider ratio, dimensionless
N
pll
: noise of the PLL as a phase noise density [rad/sqrt(Hz)]
N
s
(s): numerator of Z
s
(s)
PhM: phase margin for a open loop transfer function [°]
p: normalized time deviation T
d
/T
cp
Q: charges [C]
V
tune
: tuning voltage for the VCO [V]
List of Symbols and Abbreviations xi
R
J
(τ): autocorrelation function of the random process J
R
pu
: pullup resistor in an active loop filter [Ω]
r
pf
: postfilter factor for the compensation of α
n
and w
oln
r
21
: 2
nd
pole to zero ratio for loop filter
r
31
: 3
rd
pole to zero ratio for loop filter
S
ϕ
(f), S
ϕdB
(f): mean square phase fluctuation power [rad
2
/Hz, dBc/Hz]
S
J
(f): power spectrum density of J
T
cp
: comparison period [s]
T
d
: delay or time interval between the two inputs of the phase detector [s]
T
p2
, T
p3
, T
z1
: time constants related to the zero and poles of the loop filter [s/rad]
V
d
(s), v
d
(t): voltage disturbance signal [V]
v
M
(t): tuning voltage for a 2
nd
order filter impedance [V]
v
ni
, V
ni
: voltage noise density from component i [V/sqrt(Hz)]
v
n
(t): single tone noise component [V]
v
nf
: voltage noise density from the loop filter at the input of the VCO [V/sqrt(Hz)]
v
nvco
: inherent noise of the VCO as a voltage noise source [V/sqrt(Hz)]
w: angular frequency [rad/s]
w
a
: pole of the loop amplifier [rad/s]
w
as
: intersection frequency for the asymptotes of the root locus [rad/s]
w
c
: angular frequency of the carrier signal [rad/s]
w
cl
: bandwidth of the closed loop transfer function B(s) [rad/s]
w
cp
: angular comparison frequency [rad/s]
w
n
: natural frequency [rad/s]
w
ol
: zerocrossing angular frequency for the open loop transfer function H(s) [rad/s]
w
oln
: nominal value of w
ol
for loop filter calculation [rad/s]
w
olnpf
: nominal value of w
ol
after the compensation wrt the postfilter [rad/s]
w
p2
, w
p3
, w
z1
: angular frequencies related to the zero and poles of the loop filter [rad/s]
w
s
: sample angular frequency [rad/s]
w
3dB
: angular frequency related to f
3dB
[rad/s]
x: bandwidth ratio f
oln
/f
cp
Z
F
(s), Z
filter
(s): impedance of the loop filter [Ω]
Z
Fa
(s): impedance of the active loop filter [Ω]
Z
Fai
(s): impedance of the active loop filter with a nonideal input impedance [Ω]
Z
F3
(s): full 3
rd
order impedance of the loop filter [Ω]
Z
in
: input impedance [Ω]
Z
s
(s): series version for the leadlag filter impedance [Ω]
Z
o
: output impedance [Ω]
Z
p
(s): parallel version for the leadlag filter impedance [Ω]
Z
3
(s): postfilter impedance [Ω]
Z
3u
(s): impedance of the postfilter in parallel to the pullup resistor [Ω]
xii PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Abbreviations
AC: alternate current, refers to small signal frequency domain models
(commonly named AC models in analog simulations)
ADC: analog to digital converter
AGC: automatic gain control
AM: amplitude modulation
BB: base band
BiCMOS: IC founding process with both BJT and CMOS devices
BPF: bandpass filter
bw: bandwidth
CMOS: complementary metaloxidesemiconductors
CNR: carrier to noise ratio
DAB: digital audio broadcasting
DAC: digital to analog converter
DBS: direct broadcast satellite
DC: direct current, refers to the quiescent state of a circuit
DDS: direct digital synthesis
DFF: Dtype flip flop
DSB: doubleside band
DVB: digital video broadcasting
ft: frequency of unity current gain for a transistor
FM: frequency modulation
GmC: transconductance and capacitor integrator for a ring oscillator
IC: integrated circuit
IF: intermediate frequency
I/Q: in phase and quadrature signals
I
2
C: bidirectional 2wire bus for interIC programming and control
LC: inductor and capacitor resonator
LHP: left hand plane in a sspace (Laplace transform)
LNA: low noise amplifier
LO: local oscillator
LPF: low pass filter
LTI: linear time invariable system
MCPC: multichannel per carrier
MOPLL: mixeroscillator plus phaselockedloop circuit
NPN: ntype bipolar junction transistor
OFDM: orthogonal frequency division multiplexing, type of multicarrier modulation
PLL: phase locked loop
PM: phase modulation
PMOS: Pchannel metaloxidesemiconductor
PNP: ptype bipolar junction transistor
PSD: power spectrum density
PWM: pulse width modulation
QAM: quadrature amplitude modulation, type of digital modulation
QCCO: quadrature current controlled oscillator
List of Symbols and Abbreviations xiii
QPSK: quadrature phaseshift keying, type of digital phase modulation
RBW: resolution bandwidth in a spectrum analyzer
RF: radio frequency
RHP: right hand plane in a sspace (Laplace transform)
RX: receiver in a telecommunication system
SAW: surface acoustic wave filters
SCPC: singlechannel per carrier
SDD: satellite demodulator and decoder
SNF: synthesizer noise floor
SNR: signal to noise ratio
SSB: singleside band
sqrt: square root
TC2, TC3: testchips #2 and #3
TDM: time division multiplexing
TR: transient analysis in analog simulation
TV: television
TX: transmitter in a telecommunication system
VHF: very high frequency, television broadcasting band
UHF: ultra high frequency, television broadcasting band
VCO: voltage controlled oscillator
V/I: voltage to current converter
VSB: vestigial side band, type of modulation
wrt: with respect to
WSS: wide sense stationary, property of some stochastic processes
Xosc: crystal oscillator
ZIF: zeroIF receiver, architecture of a frontend
ZOH: zero order holder
3W: unidirectional 3wire bus for interIC programming
xiv PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Preface
The central issue of this thesis is the stability and noise performance of PLL frequency
synthesizers.
Frequency synthesizers are a common block of the frontend of RF telecommunication systems.
In particular, PLL synthesizers are extensively used for their programming flexibility, ease of
integration and low production cost.
We focus on the context of TV broadcasting tuners, where the new standards of digital
modulation broadcasting (DVB) which are appearing, and the continuous trend for higher
integration levels, are bringing new issues for IC design and application.
Most of the thesis dissertation is concerned with models: calculations and behavioural simulation
tools, which were developed to support the activities of design and engineering for the integrated
circuits in frequency synthesizers.
The design of a monolithic mixeroscillator and PLL synthesizer is also presented and used as a
practical example to compare the simulations and calculation tools with measurement results.
Chapter one introduces the context of the TV tuner and the current tendencies in architecture
and IC requirements. These tendencies point to low phase noise synthesizers, implemented in
very monolithic architectures with integrated oscillators. The constituent blocks of the PLL
synthesizer are presented, describing their basic functionality.
Chapter two studies the stability and robustness of a phaselocked loop in a tuner application,
where the gain parameters vary within a large range. An algorithm for the loop filter calculation
is developed. It allows a systematic and consistent approach to combine the IC parameters and
the filtering requirements.
Application constraints related to phase deviations and reference breakthrough are discussed in
the light of this algorithm, in chapter three. This is the beginning of a topdown analysis about
the phase noise in the local oscillator (LO) signal. The noise performances of the PLL and the
VCO are adjusted by centering the closed loop bandwidth of the feedback. An example of phase
jitter optimization for a satellite synthesizer is discussed.
Chapter four examines the active loop filter configurations and continues the noise analysis, in
a first example that descends to a circuit implementation level. The AC characteristics of the
filter amplifier exemplify the first nonideal aspects of the phase model of the PLL.
In chapter five we continue to discuss other limitations of the linear time invariable model of the
frequency synthesizer. They concern the maximum feedback bandwidth for a loop that is
partially discrete, and the maximum comparison frequency that still guarantees the frequency
tracking behaviour of the tristate phase detector. A discrete time domain approach is compared
to a continuous frequency model with an equivalent delay.
Chapter six presents the theoretical basis of the generation of phase noise, and discusses
different possibilities of notation that are compared to measurement and simulation tools. The
relationships among the different notations are explored. The assumptions of a narrow band FM
modulation and a periodic steady behaviour are combined, in order to develop a linear time
variable transfer for the noise.
List of Symbols and Abbreviations xv
In chapter seven, the phase noise issue is detailed to the circuit level, by an analysis of the noise
performance of the different constituent blocks of the PLL. The parameters that can distinguish
the dominant noise sources in measurements are identified, and two simulation examples are
presented. Furthermore we discuss behavioural models to mix system and circuit descriptions in
simulations. We also present considerations about the implementation loss in the receiver due to
the phase deviations in the LO signal. Practical examples, simulations and measurements, are
presented in chapter eight, where these analytical tools are used to design and evaluate two
testchips. The testchip designs are briefly presented, they contain a PLL and a monolithic GmC
oscillator that covers the satellite band L (950MHz to 2150MHz). Testchip TC2 is part of a
double synthesizer with a comparison frequency that goes up to 330MHz, with an inloop noise
in the order of –108dBc/Hz. Testchip TC3 explores the maximum bandwidth of a single loop
PLL and confirms the theoretical approach of chapter five. Finally we compare the spectra of
two synthesizers: a single loop PLL plus an LC oscillator and a double loop synthesizer plus a
GmC oscillator, both for a QPSK near zeroIF receiver. The comparison refers to the allocation
of implementation loss in a tuner, due to the phase deviations in the LO. Two examples of high
and low bit rate channels are discussed, and the margin for production for the most critical
parameters is calculated.
This thesis was developed in the industrial site of Philips Semiconductors in Caen, Normandie,
France. It was part of a collaboration contract between Philips Semiconductors and the INSA de
Lyon, or more specifically the electrical engineering laboratory CEGELY.
I would like to thank all of the colleagues within Philips Caen and Philips Eindhoven for their
help and support.
Caen, June 99,
Marina de Queiroz Tavares
Chapter 1 / Introduction 1
Contents:
1 Introduction 1
1.1 The frontend in a telecommunication receiver.........................................................................................2
1.2 The frontend in TV broadcasting .............................................................................................................3
1.3 Current tendencies: low noise and higher integration.............................................................................9
1.4 PLL systems : different application contexts .........................................................................................14
1.5 PLL frequency synthesizers constituting blocks and nomenclature.......................................................15
1.5.1 VCO...............................................................................................................................................16
1.5.2 Dividers..........................................................................................................................................17
1.5.3 Phase Detector – Charge Pump......................................................................................................17
1.5.4 Loop Filter .....................................................................................................................................19
Figures:
Figure 1.1 Example of a communication transceiver: TX and RX systems................................................2
Figure 1.2 Heterodyne Receiver _ Terrestrial TV Frontend.......................................................................4
Figure 1.3 DVB Satellite transmission modes...............................................................................................6
Figure 1.4 Satellite Receiver Frontend: heterodyne and ZIF architectures...............................................7
Figure 1.5 Local Oscillator Spectral Purity X SNR .....................................................................................9
Figure 1.6 Carrier Spectrum........................................................................................................................10
Figure 1.7 QPSK constellation + phase deviation........................................................................................11
Figure 1.8 Phase Noise requirements ..........................................................................................................12
Figure 1.9 PLL frequency synthesizer: block diagram..............................................................................16
Figure 1.10 VCO and tunable resonator.......................................................................................................16
Figure 1.11 Phase Detector & Charge Pump block diagram......................................................................18
Figure 1.12 Phase detector & Charge pump: transfer and state machine .................................................19
Tables:
Table 11 DVB standards: bandwidth and modulation types......................................................................10
1 Introduction
In this chapter we locate the context of this thesis by introducing basic aspects and innovation
tendencies for the frontends of TV broadcasting receivers.
This thesis focuses on the frequency synthesizer block, which is a constituent part of the
frontend.
PLL frequency synthesizers are a common element of different telecommunication receivers that
are produced on a large scale. This choice is connected to their compactness and low cost, both
of which are continuously improved by larger integration levels.
Furthermore, emerging digital modulation techniques are imposing new requirements on this
block, which carries out the frequency conversion of the input data.
Finally, we shortly describe the constituent elements of the PLL synthesizer, so as to present
their functionality and general structure.
2 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
1.1 The frontend in a telecommunication receiver
Communication and transport are probably the key technological fields that most changed daily
life in the 20th century. Our world became smaller, because it may be rapidly crossed by waves
and engines taking information and people worldwide.
The term communication system is employed here to include transceivers that convert data into
electromagnetic waves (transmitters_TXs) and the other way around (receivers_RXs), in order to
transmit this data through a fast moving media such as air, metallic cables, optical fibers and
others.
The TX and RX have two basic parts, namely:
• Backend: data processor and (de)modulator;
• Frontend: frequency translator and selectivity.
The first one is in charge of transforming data into a convenient manageable electrical signal
that is later transposed into a well defined frequency window (channel) by the second.
i
Figure 1.1 Example of a communication transceiver: TX and RX systems
The spread of communication systems relies on the advance of modulation techniques, digital
signal treatment and RFfrequency electronics. The first two greatly increased the amount and
quality of transmitted information, and the last one enabled the utilization of an increasing range
of the frequency spectrum.
However this spectrum range is limited by the physical properties of the conducting materials
and the maximum working frequencies of the electronic devices employed. So further
exploitation of this already crowded spectrum depends on a greater compaction of modulated
data, or capacity to share the same frequency range (spread spectrum modulations).
Occupying narrower frequency bands with higher information density decreases the margin for
signal degradation in the up and down conversion of the data in the TX and RX systems. In other
words, modulation types with increasing bandwidth efficiency require higher signaltonoise
ratio (SNR) for a correct reception.
i
There are also communication systems that use base band transmissions, i.e. the data is directly transmitted after
modulation, without being frequency translated. However the applications are usually restricted by their maximum
data flow.
Frontend Backend
input
data
data processor
+
Modulator
Up
Conversion
output
data
Demodulator
+
data processor
Down
Conversion
+
Selectivity
Chapter 1 / Introduction 3
Up and down conversions are carried out by mixing data signals with carrier signals in TXs, or
by mixing channels with carrier signals in RXs. Therefore the loss of quality due to this
operation depends on the mixer and carrier qualities.
Mixer performance is usually specified in terms of conversion gain, noise figure and linearity
parameters, amongst others. There is a compromise between the parameters of gain on one side
and linearity and noise figure on the other. This compromise has to be solved in combination
with the specifications of the filtering and amplification stages, taking into account the
constraints of consumption and signal quality.
The carrier signal performance includes factors such as frequency tunability and spectrum purity.
The frequency tunability refers to the coverage of a frequency range, with a certain resolution or
minimum variation step. The carrier spectrum quality is often defined by a carriertonoise ratio
(CNR), specified in accordance to the modulation nature and SNR requirements of the data
signal.
Carrier signal generation can be split into three basic types:
 Direct digital synthesis (DDS), using sine lookup tables, accumulators and digital clocks.
They are often limited in speed and quality by the maximum clock frequency. Thus, they are
more frequently employed in bandbase (BB), or intermediatefrequency (IF) stages; mainly
after analogtodigital data conversion (ADC).
 Mixerdivider chains, combining an ensemble of reference oscillators, through frequency
conversion and filtering. Increasing the precision and the frequency range is a trade off with
size, integrability and power consumption. They are often bulky systems that become hardly
integrable as the number of reference sources increases. For nonintegrated systems, the
advantage of keeping the spectral purity of the sources may be decisive.
 Feedback loops with a reference source and a programmable counter block to sweep the
frequency range of a tunable oscillator. Phaselocked loop types are the most widespread in
transceiver applications. Integrability and low cost are the main advantages, but settling times
are elevated compared to methods of direct synthesis.
A wide span of systems of hybrid generation combine the basic types above to explore the
advantages of each architecture. They may be generally called multiloop architectures, as they
compose the carrier signal through two or more loops in different concatenated and/or interlaced
structures.
The scope of the present work is centered around PLL frequency synthesizers for terrestrial and
satellite TV receivers. Stability and noise issues are discussed and applied to single and double
loop architectures.
The models developed for stability and disturbance are certainly useful for other PLL
applications, but the issues and numerical examples are oriented by the primary context.
1.2 The frontend in TV broadcasting
The block schematic below represents a heterodyne receiver, detailing the elements of the
selectivity and frequency conversion stages.
ii
ii
The denomination heterodyne or superheterodyne, is given to receivers working with two distinct amplification
and filtering sections prior to demodulation.
4 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Figure 1.2 Heterodyne Receiver _ Terrestrial TV Frontend
(1) 1
st
RF filter: large bandwidth filtering plus impedance adaptation between antenna and preamplifier;
(2) RF preamplifier: 1
st
amplification stage (keeping SNR), plus buffer avoiding f
osc
leakage towards the antenna input;
(3) double RF filter: middle bandwidth filtering, rejecting image channel and also blocking VCO signal ;
(4) Mixer: frequency conversion kernel: conversion gain, linearity and noise figure constraints;
(5) Local Oscillator (LO) + PLL tuning system: carrier generator for downconversion, and frequency tuning for oscillator and input filters tracking;
(6) IF preamplifier: gain prior to selective filtering to keep minimum SNR;
(7) IF filter: fixed frequency very selective filtering (SAW filter);
(8) IF signal treatment: amplification, demodulation and signal level detector.
TUNE
(5)
(1) (2) (3) (4) (6) (7) (8)
BB
output
data
V
AGC
V
tune
VCO
or
LO
PLL
video
&
audio
demod.
Level
detector
RF stage IF stage
Chapter 1 / Introduction 5
In figure 1.2 the incoming signal is initially modulated at the channel or RF frequency, where a
primary rough selection is carried out by filters (1) and (3). After the first frequency down
conversion, the input data appears around the IF, and passes a sharper selectivity stage
represented by filter (7). A convenient amplification level is assured by an automatic gain control
(AGC) loop, with an amplitude sensor at the BB stage.
The elements constituting the tuner are indicated by the dotted arrow. In a TV set the tuner is
easily recognized by its metallic screening box, used for RF isolation.
The sequence of filtering, mixing and amplification blocks reflects an important tradeoff
between selectivity and frequency tunability. For elements with a frequency dependent
behaviour, these characteristics usually oppose each other. Therefore the RF stages covering the
whole input frequency range are necessarily less selective than the IF stage, working at a fixed
frequency.
RF filters and oscillator are constructed with similar resonant circuits, assuring the correlation of
their frequency variation, also named tracking characteristic or matched filteroscillators.
The frequency tuning of the RF stages is made by the PLL block. It contains a feedback control
system, comparing the RF oscillator to a reference crystal oscillator. The frequency variability is
guaranteed by programmable counters interpolated in the control loop.
The work in this thesis deals with stability and noise aspects of the PLL plus RF oscillator
ensemble, correlating their specifications and design constraints to the tuner application
requirements. The tuner architectures and the issues studied are focused on the TV reception
context, for both terrestrial and satellite applications.
In fact figure 1.2 represents a terrestrial tuner architecture, with the following typical values of
RF and IF frequencies and bandwidths:
i
• RF input, channel frequency range divided in three bands:
 VHF I: 47 MHz  140 MHz
 VHF III: 140 MHz  400 MHz
 UHF: 400 MHz  860 MHz
The input amplifier, filtering and mixing stages are often doubled, having one set specific
for the reception of the VHF bands, and the other for UHF.
• Most standards work with: F
vco
= F
RF
+ F
IF
and IF typically within the range : 39 MHz  55 MHz
The choice of F
vco
larger than F
RF
reduces the relative tuning range (f
max
/f
min
) of the local
oscillator. The highest possible IF value is chosen, to ease the filtering of the image channel,
but usually outside the reception bands, to avoid direct coupling between the RF input and the
IF output.
• Channel bandwidth: 6 MHz  8 MHz
Most of the channel bandwidth is occupied by the video information. The audio is
transmitted through a modulated subcarrier that is placed in the high end of the channel
bandwidth, between 4 and 6 MHz.
• The bandwidths of bandpass filters (1) and (3) vary significantly amongst the different
applications. For instance, filter (3) may present a bandwidth between 7 and 25 MHz. The
rejection of this same filter for the image channel is in the order of 60 dB.
Filter (7) presents a sharp selectivity for the neighbouring frequencies, and a bandwidth in
the order of 5MHz.
• The AGC dynamic for the amplifying blocks of the tuner is generally between 40 and 50 dB,
with another 60 dB controllable amplification capacity in the demodulator.
i
The frequency values indicated for the terrestrial and satellite applications are just a rough range, close to the most
common standards. There are several standards with different values for RF, IF and channel width.
6 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
For analog standards, the minimum SNR at the IF output is in the order of 55dB, to start
causing visible errors in the video reception.
Satellite tuners have a slightly different architecture, as shown in figure 1.4.
The RF transmission bandwidth, Kuband, is rather elevated, which imposes a first frequency
conversion close to the antenna, in order to support the losses through the cable binding the
antenna and the RX frontend.
• 1
st
RF at the antenna input, Kuband: 10.7 GHz  12.75 GHz ;
• Constant LO frequency downconverting block: LNA (low noise amplifier)
Due to the strong attenuation between the satellite and the RX antennas, this block has tight
noise figure requirements;
• 2
nd
RF at LNA output, band L : 950 MHz  2150 MHz .
The older analog standards, (DBS  Direct Broadcast Satellite), use FM modulated channels with
a bandwidth varying between 27 and 36 MHz.
The more recent digital norms, (satellite DVB – Digital Video Broadcasting), have different
channel compositions, using multiplexing in frequency and time domain (see figure 1.3). In this
case we prefer to refer to the frequency spacing as the transponder bandwidth, regarding the
ensemble of signals transmitted by a single amplifier in a determined frequency window.
• Transponder bandwidth: 33 MHz – 36MHz ;
• MCPC (multichannel per carrier): single modulation package multiplexing in time
(TDM) up to 8 TV channels transmitted in a bit
flow with rates around 55 Mbps;
• SCPC (singlechannel per carrier): several narrow bandwidth channels splitting the
transponder spacing;
• Multicast (analog+digital channels): a standard analog FM channel of 27 MHz
bandwidth multiplexed in frequency with a 9MHz
wide digital channel, transmitted with a power
level 13dB below the analog channel.
Figure 1.3 DVB Satellite transmission modes
The first RX systems for QPSK channels used a double IF heterodyne architecture, with the
following intermediate frequencies:
• 1
st
IF: 460 MHz – 480 MHz; with 1
st
LO: F
vco1
= F
RF
+ F
IF1
• 2
nd
IF: 70 MHz, and a downmixing stage with a LO containing 2 outputs in quadrature.
The choice of the 2
nd
IF was connected to the availability of SAW filters with Nyquist slope at
this frequency. The demodulation and decoding are performed by a digital IC, whose ADC input
is connected to the bandbase output of last mixing stage.
The last LO converting the data to the base band has quadrature outputs, splitting the output data
in I (in phase) and Q (quadrature) outputs.
36MH
MCPC SCPC Multicast
QPSK QPSK FM QPSK
13dB
Chapter 1 / Introduction 7
Figure 1.4 Satellite Receiver Frontend: heterodyne and ZIF architectures
V
AGC
V
tune
SAW
V
AGC
I
Q
BB
output
data
RF stages
V
tune
heterodyne receiver F
vco
= F
IF
+ F
RF
F
IF
~ 470 MHz
2
nd
1
st
RF
V
AGC
IF and/or BB
LNA
down
converter
Nearzero IF receiver F
vco
= F
RF
BB
output
data
Satellite demod. & decoder
(SDD)
V
tune
VCO
PLL
90°
Demo
dulator
Level
detector
VCO
PLL
I
Q
90°
carrier
&
clock
recovery
forward
error
correction
ADC
&
filters
Level
detector
8 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
In more recent systems the Nyquist filtering is integrated in the digital IC realizing the
demodulation and signal decoding. Thus an intermediate heterodyne architecture uses a single IF
(similar to the 1
st
IF above) and a quadrature LO at this IF frequency (see upper half of figure
1.4).
Finally the latest satellite tuner ICs are concentrating in a monodyne, nearzero IF architecture
(see lower half of figure 1.4). There is one single stage of frequency translation between the 2
nd
RF (band L) and the BB output.
It is certainly an architecture allowing greater compactness and economy in external
components, but also increasing the performance constraints for the integrated blocks and the
surrounding application.
The advantages are connected to the suppression of the IF stage and the replacement of the SAW
– BPF by a discrete and cheaper LPF. Besides, the rejection of the image channel (which is now
the selected channel but with a spectrum reversion) can be replaced by a proper output form,
containing the necessary information to distinguish the two superposed spectra. The I and Q
outputs have this convenient format, and furthermore they are adapted to the demodulation of the
QPSK modulated data.
The limitations are connected to the performance of several blocks such as:
 the quadrature LO, which now works in the band L, and needs to fulfill the conditions of
minimum mismatches in amplitude (<0.5dB) and quadrature (<3°);
 the matching of the I/Q stages in BB;
 the isolation and linearity of the RF amplifiers and mixers.
In fact the monodyne RX is especially sensitive to coupling between the RF and LO signals (in
this case at the same frequency) and to interference generated by intermodulation products of
even orders (appearing at low frequencies).
The nomenclature nearzero IF stress the fact that the LO signal is not locked to the RF input, but
is programmed to a frequency close to the RF carrier. The precision is also limited by the
minimum allowable tuning step in the LO controlling loop. The difference between the output
spectrum and a real BB signal are recovered by the digital demodulator in the so called, carrier
recovery loop.
Figure 1.4 illustrates block schematics of a heterodyne, single IF, and a nearzero IF (named ZIF
or zeroIF for short) receivers. In both configurations the AGC dynamic range, for the tuner, is to
the order of 50 dB. The bandwidths of the filters are greatly dependent on the application. The
minimum SNR at the base band output will depend on the maximum biterror rate that can be
corrected by the signal decoder. A maximum biterror rate (BER) of 10
4
is usually acceptable
for most decoders, and it implies a minimum SNR of 11.4dB for QPSK modulated data
[Sinde98a].
We can note the large difference of the minimum SNR for the reception of analog terrestrial TV
signals and the satellite digitally modulated ones. However the latter suffers from much larger
attenuation in the transmission path, and it would not be feasible to work with such high SNR as
in the terrestrial systems.
Another important difference between the terrestrial and satellite applications, besides their
frequency ranges, is the constraint for the filtering of the neighbouring channels.
Satellite transmitted channels have the same power levels at the RX input, as they come from a
common TX source.
In terrestrial transmission, neighbouring channels may come from different TXs and
consequently their incoming power vary greatly according to the TX and RX “line of sight”.
Chapter 1 / Introduction 9
The “line of sight” concerns the distance and blocking obstacles, causing attenuation and
reflection of the transmitted signal.
i
Figure 1.5 illustrates the importance of the carrier spectral purity for the proper reception of
neighbouring channels with different input power.
Figure 1.5 Local Oscillator Spectral Purity X SNR
The channel with lower input power, centered around f
ch2
, is degenerated by an adjacent channel
down converted by a noisy local oscillator.
This example introduces the idea that the tuner requirements, with respect to selectivity and SNR
degradation, may be translated to corresponding specifications for the frequency synthesizer
block.
From now on, we concentrate our attention on the frequency synthesizer block, marked by a gray
rectangle in the frontend schematics (figures 1.2 and 1.4).
In the next section we discuss some current tendencies in the development of tuner ICs, relating
the new requirements to the emerging digital broadcasting systems.
1.3 Current tendencies: low noise and higher integration
Current trends in the tuner circuit developments are bound to the developing standards using
digitally modulated signals, and to the continuous demand for higher integration levels.
Nowadays, tuners often have one single integrated circuit (IC), a MOPLL, including the PLL,
mixeroscillator and IF amplifier blocks. This level of integration is the result of a continuous
miniaturization that combines the functionality of several ICs and also integrates parts of
previously discrete circuitry.
Furthermore the more recent digital standards, based on phase modulation techniques and/or
using closely spaced multicarriers, are imposing new constraints on the CNR of the local
oscillator. Therefore from the basic requirements of the frequency synthesizer concerning the
tuning range and the resolution, other more strict parameters of spectral purity are added.
i
Signal reflection causes multipath reception, where different phase delayed versions of the input signal reach the
RX. Specially for strongly attenuated signals this is an important drawback, decreasing the SNR and adding noise
which is correlated to the signal.
IF RF
LO
f
ch1
f
ch2
f
lo
f
lo
f
ch1
f
lo
f
ch2
10 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Figure 1.5 sketches the pollution of the input RF signal by the spectral dispersion of the local
oscillator. The spectral purity is largely discussed during this work, and in the PLL synthesizer
context we will see that it is directly associated to the phase noise in the carrier signal. Therefore
the specifications of phase noise in the output of a local oscillator, are a translation of the CNR
required for the reception. These specifications also depend on the modulation type and on the
selectivity of the input filtering stages.
Analog terrestrial TV standards use vestigial sideband (VSB) modulation and FM for the video
information and either FM and AM signals for audio. In satellite applications the analog
standards use FM signals, needed for their robustness with respect to amplitude distortions.
When talking about SNR, we concentrate on the video signal because of its larger amount of
information compared to the audio signal. Besides the video signal needs higher signal quality
for an interferencefree (or errorfree) reception.
In particular for FM signals, the noise added by a local oscillator with 1/f
2
power sidebands (as
represented in figure 1.6) is demodulated at the output as a flat, white distributed noise
interfering in the output data. Therefore in the FM context, noise specifications are often bound
to the free running, or outofloop, carrier spectrum, transmitted by the VCO intrinsic noise.
Figure 1.6 Carrier Spectrum
Digital video broadcasting standards and services have undergone great expansion recently. In
Europe the DVBS, DVBC, DVBT and DAB describe the norms of video and audio
transmissions through satellite, cable and terrestrial or offair systems.
DVBS DVBT DVBC DAB
Basic
modulation
principle
Single carrier
QPSK modulated
Multiple carrier OFDM
subcarriers modulation:
QAM16 or QAM64
Single carrier
MQAM modulated
(M=16, …64, 256)
Multiple carrier OFDM
subcarriers modulation:
DQPSK
Number of
subcarriers
& frequency
spacing
_ 1705 / 6817
mode: 2k / 8k
∆f= 4.47kHz / 1.12kHz
_ 193/ 385/ 769 /1537
mode: 1 / 1.5 / 2 / 3
∆f= 8kHz /…/ 1kHz
Signal
bandwidth
Not fixed, e.g.:
33MHz – 36MHz 7.61MHz
Not fixed, e.g.:
7.9MHz 1.536MHz
Gross data
rates [Mbps]
Not fixed, e.g.:
51.60 10.80 – 39.27
Not fixed, e.g.:
34.37 2.304
Frequency
ranges
10.7 – 12.75GHz
2
nd
RF:
950 – 2150MHz
VHF I
VHF III
UHF
VHF I
VHF III
UHF
Slots within:
VHF III
Band L
Table 11 DVB standards: bandwidth and modulation types
Programmable
&
tunable range
N.f
cp
f [Hz]
P(f)
single
sideband
phase noise
f
osc
f [Hz]
Chapter 1 / Introduction 11
The DAB system, initially imagined for audio transmission only, has developed into a
multimedia standard (DMB), showing important advantages for mobile applications when
compared to the DVBT.
All these standards have source coding algorithms based on MPEG2. Table 11 [Roma97]
presents a short overlook of these standards.
The first digital broadcasting services available were the single carrier ones, requiring simpler
TX and RX. Nowadays there are also DAB radio and data transmission services, and the first
consumer DVBT systems are currently being tested.
The minimum signal to noise ratios vary in accordance to the bandwidth efficiency of the
different types of modulation and coding. For example, for a maximum BER of 10
4
, the SNR of
a DVBC channel in QAM 64 is 24.3 dB, and in QAM 256 it equals 30.2 dB
[Sinde98a], which is considerably higher than the SNR for the QPSK channel.
The underlying modulation principles are either phase or phase and amplitude based. Thus with
respect to the sensitivity of the local oscillator to the CNR, we may expect that the phase
accuracy of the carrier becomes relevant.
Indeed, the specifications for the LO spectrum become very tight. For example, tuner
constructors ask for the following phase noise performances: for QPSK receivers a maximum
total phase deviation under 2°; or for OFDM receivers a single sideband (SSB) phase noise
lower than –80dBc/Hz at a frequency offset of 1kHz.
However, most of these specifications are empirically determined, and they strongly depend on
the application used for the measurements.
More formally, these specifications can be derived from the allocation of implementation losses
within the system. For DVB standards, the implementation losses due to the phase deviations of
the LO signal should be kept below 0.2 dB [Sinde98a]. This requirement can be translated into a
total phase deviation brought by the synthesized carrier. Nevertheless, the relationship between
the implementation loss and the LO phase deviation depend on the characteristics of the
demodulator used in the reception.
Therefore the specification for phase deviations, either as a total value in degrees or as a
maximum SSB level at a certain offset, reflects the sensitivity of the ensemble, frontend plus
demodulator, to a certain noise spectrum shape.
The optimization of the phase deviation in the LO signal is one of our central subjects that is
progressively discussed in the following chapters. At this point, we give a first glance of the
issue with figures 1.7 and 1.8.
In figure 1.7 we sketch the influence of
phase noise in a QPSK constellation,
showing that phase deviations directly
increase the occurrence of errors in bit
detection.
Figure 1.7 QPSK constellation + phase deviation
QPSK
constellation
∆ϕ
12 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
The total phase deviation can be calculated integrating the sidebands of the LO spectrum, as
shown in figure 1.8.a. The lower and upper limits of the integral are determined by the
demodulator and channel bandwidth parameters.
Figure 1.8 continues the zoom around f
osc
started in figure 1.6. It shows noise specifications that
may concern the intrinsic behaviour of the oscillator (out of loop SSB phase noise) or the PLL
blocks (in loop SSB phase noise), used to tune the oscillator frequency.
Figure 1.8.a Figure 1.8.b
Figure 1.8 Phase Noise requirements
For multicarrier standards, the noise specifications are eventually determined by a maximum
threshold for the level of the sidebands, for offsets that are comparable to the frequency spacing
between subcarriers.
Figure 1.8.b shows two carrier spectra with different noise performances, and it also indicates a
SSB phase noise limit for two different frequency offsets(f
off1
and f
off2
).
The dotted line spectrum presents a better oscillator performance than the solid line spectrum.
However as the offset frequency of the noise specifications decreases, it becomes harder to fulfill
this requirement by relying only on the oscillator characteristics.
The solid line spectrum shows an option where the inloop (PLL related) noise performance is
adapted to the CNR specification at both offsets: f
off1
and f
off2
. In practice this situation appears
in two contexts:
• very strict noise performances related to modulation types with compact data representation
in narrow bandwidths or using multicarriers closely spaced to each other. In TV
broadcasting the OFDM (Orthogonal Frequency Division Multiplexing) standard has the
most strict specifications concerning the local carrier spectral purity.
• oscillators with a poor intrinsic noise performance, but associated to low noise PLL. This
situation is often encountered when using completely integrated oscillators.
The second situation sends us back to the trend for higher integration levels.
Currently, most of the controllable LOs are based on a resonant amplifier with an external
resonator.
The large frequency range of the TV applications limits the possibility of integrating the resonant
circuit, as occurs in narrow band reception systems, like mobile telephones. Therefore other
oscillator structures, like ring or relaxation, have to be tried.
f
off1
f
off2
……
fmin fmax
f
osc
f [Hz]
f
offset
in loop
SSB
phase noise
out of loop
SSB
phase
∆ϕ
2
/2
Chapter 1 / Introduction 13
The drawbacks of these other structures are: their poorer phase noise performance as compared
to LC resonators with high quality factors, and the impossibility to track the LC matched filters
in the input stages of the tuner.
The advantages appear mostly in the zeroIF configurations, where a totally integrated oscillator,
with no LC resonator, increases the robustness to RF interference.
Therefore the integration tendency forces architectural modifications in the tuner. The absence of
external tracking filters can be more easily coped with in satellite receivers, where the uniform
input level enables a feasible compromise between selectivity and linearity requirements.
ii
Furthermore, it is also in satellite applications that we see more and more frontend receptors
using direct conversion, or ZIF receivers. Direct conversion schemes have new constraints
related to the suppression of the IF stage. The AGC dynamics in the RF and BB parts have to
replace the previous IF dynamics while preserving the linearity and noise figure properties.
Coupling interactions between the local oscillator and the RF input signal (now in the same
frequency), have to be controlled to reduce the signal degeneration by “selfreception” or “self
demodulation”.
These constraints brought an additional interest to a completely integrated oscillator suffering
form less external coupling problems. The integrated oscillators may also be piloted by a second
oscillator with an external resonator but working at a different frequency; or in other words, a
multiloop synthesizer.
The use of an integrated oscillator covering a large tuning range often brings an inherent
degradation of the oscillator spectral purity. Thus achieving strict phase noise requirements
becomes obligatory for the PLL circuitry.
In fact, figure 1.8 showed that the noise requirement imposes a compromise between the PLL
and the VCO noise performances. Furthermore the variable parameter adapting these
performances is the loop bandwidth, which unfortunately is not independent of other parameters
such as loop gain, comparison frequency, minimum tuning step and DC tuning range.
In summary the following topics, that are closely related to the evolution of an analog carrier
generation for RX frontends, are guiding the issues studied in this work:
Noise and stability treatments for large bandwidth and low phase deviation PLL synthesizers in tuner
applications;
Low Phase Deviation: the VCO spectrum has to be optimized for minimum phase deviations in
accordance to the new digital modulation standards (DVB standards: QPSK, QAM, OFDM).
A combination of PLL and VCO noise performances are the IC parameters that can be specified
to fullfil this specification. The PLL bandwidth is the compensation variable between the
performances of these two circuits.
As the improvement in coverage+selectivity of the VCOs attains a limit, the noise quality of the
PLLs starts to be an issue. Nevertheless, to rely on the PLL characteristics, we need to control
the closed loop bandwidth, and learn about the constraints that limit the PLL bandwidth.
Furthermore, for solutions with integrated oscillators, multiloop schemes with large PLL
bandwidths are required.
PLL synthesizers in tuners have to cope with large variations in gain parameters, in an application
context that is not very flexible. So the most natural and inexpensive point for optimization is a careful
fitting of the loop filter.
The three issues above are completely entangled with each other since the optimization of the
spectrum suggests bandwidth constraints that have to be guaranteed within the whole gain
interval.
ii
Another option to the input filtering is to integrated selectivity stages with structures that are matched to the
integrated oscillator. However this option is quite challenging for the aspects of power consumption and RF
isolation.
14 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
These issues are the conducting line through the sequence of practical and theoretical points
tackled in this work.
In the next sections a short listing of PLL applications precedes a description of the constituting
blocks of a PLL synthesizer.
1.4 PLL systems : different application contexts
Phase locked loops are feedback systems containing at least a controllable oscillator and a phase
detector. The phase detector is the comparing element between a variable or steady input and the
driven oscillator element. Frequently there is also a filter before the input of the oscillator,
determining the bandwidth of the feedback action.
The first PLL applications were synchronous receptors for coherent demodulation, and the first
industrial use on a large scale appears within the TV market (in the 50’s), for the synchronization
of horizontal and vertical scans. In particular for PLL synthesizers, the first patents appeared in
the 70’s.
The application contexts are widespread in areas such as: communications, radar, telemetry,
command, time and frequency control, ranging and instrumentation systems.
However with respect to their functionality there are mainly three areas:
• Carrier Tracking and Synchronization;
• Coherent Demodulation of Digital and Analog Signals;
• Frequency Synthesis.
In the first two, the phase detector receives a variable input, from which one tries to extract either
a carrier or the information that modulates the input signal. In the third, the oscillator is coupled
to a fixed reference, in order to transfer to this, frequency and phase properties of the reference
signal.
This division is also related to the PLL functioning modes: acquisition, tracking, and, locked or
synchronous mode.
The acquisition mode refers to the interval during which the loop wanders within its tuning
range, searching to follow the input, but still not locked to it. The tracking mode concerns the
function of the PLL when it follows a non constant input, whose variations have to be tracked
within the tuning range. Finally, the locked mode refers to synthesizers with a constant input.
Some different investigation issues are seen in association with the fields of application above:
• in coherent demodulators: cycle slips, limits of tracking,… .
These are phenomena described in the time domain with complicated nonlinear
behaviour and modeling;
• in synthesizers: noise performances, locking time, stability, aided acquisition. Usually
described in linear, frequency domain representations.
• in general: aspects concerning the increasing integration level of the PLL blocks, with
lower power consumption, higher working frequencies, and in combination with
other analog and digital blocks. This last point concerns the generation and sensitivity
to interference in the supplies and in the substrate (for integrated blocks that share a
common substrate and/or common supplies).
The phase detector, such as the comparator block in the feedback system, specifies many
characteristics of the control loop. It is not unusual to classify a PLL with respect to the type of
Chapter 1 / Introduction 15
the phase detector. There are numerous references discussing the different types of phase
detectors. A general insight of different PLL applications can be found in [Wola91], and a more
specific description focused on the synthesizer context is made in [Craw94].
We would like to enumerate some phase detection principles relating their characteristics of
memory or tracking to their respective applications:
• Mixers: nonlinear element outputting the sum and difference of the frequencies of
the input tones. A low pass filter is used to select the difference portion.
The output, which represents the phase error, may depend on the amplitude of the
input signals. The tracking range is limited by the sinus periodicity.
This structure is often reserved to applications with a critical phase noise
requirement, or with very high input frequencies.
• Samplers: nonlinear element bringing a high frequency component to base band by
aliasing with a known input tone.
It has also a limited tracking range due to the ambiguity of the folded elements
coming from different harmonics of the input signals. Its advantage is related to the
possibility of extremely fast lock intervals.
• ExclusiveOR: very similar properties with the mixer type with a digital logical
implementation.
• Twostate detectors: logical implementation containing two memory nodes, or a flip
flop, for set and reset states. The tracking zone is expanded with respect to the
previous memoryless types.
• Threestate phase and frequency detectors: two flipflops and an asynchronous reset
return. The tracking zone is unlimited allowing frequency and phase error correction.
It is the common type used in PLL synthesizers. The threestate phase/frequency
detector and its tristate implementation are discussed in the following section.
We close this section with the remark that the limited tracking solutions are mostly adapted to
low SNR loops, where the phase detector has to average a carrier or signal information mixed
with important noise levels, such as in carrier and clock recovery applications. In such
conditions, a memory phase detector would have difficulty to attain lock, due to the strong
deviations it would suffer in the presence of high noise levels; or in other words, due to its
absence of error averaging.
1.5 PLL frequency synthesizers constituting blocks and nomenclature
From now on we treat exclusively the frequency synthesizer PLL. The block schematic of figure
1.9 introduces the basic constituting elements and their nomenclature.
The input is a crystal oscillator with a very selective output, related to an external quartz
resonator. The input frequency may be changed by programming different ratios in the reference
divider; thereby choosing the frequency at the input of the phase detector: f
cp
(comparison
frequency).
The phase detector is a threestate type, with a current output block, named a charge pump. The
loop filter has an impedance magnitude, and it translates the current information into the tuning
voltage input for the VCO.
The programmable divider, that is interpolated between the VCO and the phase detector, fixes
the ratio between f
cp
and the LO frequency. Therefore the dividing ratios also determine the
coverage of the tuning range of the synthesizer.
16 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
In addition, there are auxiliary service blocks, such as switches and analogtodigital converters
(ADC), that are used to command the functioning of the filtering and amplifying elements within
the tuner.
Figure 1.9 PLL frequency synthesizer: block diagram
The following sections give further details about some central blocks of the frequency
synthesizer.
1.5.1 VCO
The VCO is often a resonant amplifier that contains a tunable band pass filter (BPF) and a gain
device. The active device amplifies the inherent noise sources that are filtered by the resonator,
before they are fed back to the amplifier input.
The selectivity is then determined by the resonator. Usually, the resonant circuit is a second
order LC structure with a tunable capacitance, composed by capacitors and varicaps.
Figure 1.10 VCO and tunable resonator
In figure 1.10, the ground signal just indicates the DC biasing of the varicap. Often, a large
resistor or inductor is added for this DC connection.
The series capacitance C
p
(padder) is chosen as a compromise between the diode capacitance
ratio (C
max
/C
min
) and the quality factor (Q) of the resonant circuit . A minimum C
max
/C
min
is
C
p
R
V
tune
L
p
C
t
C
d
f
cp
Programming
input
LO
output
Crystal
Oscillator
Reference
Divider
Phase
Detector
Charge
Pump
Loop
Filter
Voltage
Controlled
Oscillator
(VCO)
Main
Divider
BUS
Biasing
&
Service
Blocks
Chapter 1 / Introduction 17
required to cover the whole tuning frequency range, whereas the quality factor determines the
phase noise performance of oscillator.
C
p
values larger than C
max
tend to be transparent for the capacitance variation. However smaller
values may be needed to improve the quality factor. This improvement is achieved by the serial
association of the varicap, with a poorer Q, with a fixed capacitor that has a better Q.
The parallel capacitor C
t
assures a minimum capacitance value and it may be added to
compensate for the changes in temperature of the IC input impedance.
The structure described above corresponds to a resonance oscillator, which is the most common
type of VCO that is encountered in frequency synthesizers for TV tuners. For other PLL
applications working with smaller tuning ranges, it is not unusual to also find ring and relaxation
oscillators, that are tuned by a variable biasing current or voltage. In chapter 8, we discuss
another controllable oscillator structure based on cascaded integrator stages.
1.5.2 Dividers
The dividers, both reference and main, are cascaded structures composed of flipflops and
combinatory logical ports. Basically we may distinguish two structures:
• prescaler structure: composed of divideby2 or swallow cells;
• shift counter.
The prescaler is normally at the input stage, and it works with the higher frequencies. It may be
fully programmable or not, depending on the limitations of frequency and sensitivity in the input
of the main divider.
The swallow cells are an extension of divideby2 cells, containing two extra latches and some
logic ports. This additional part receives a second data and a synchronizing input that commands
the “swallowing” of an extra clock pulse. Therefore the swallow cell can count 2+1, and the +1
pulse is commanded by the 2
nd
synchronizing input. Several swallow cells may be connected in
series, working with a common clock and a common 2
nd
synchronizing input which is shifted
forward between adjacent cells. In this manner the swallow cascade may count all the integers
within the interval: [ (2
n
) , (2
n+1
– 1) ] ; where n is the number of cascaded swallow cells.
The reference divider usually has a limited set of dividing ratios, and it is implemented with only
divideby2, or divideby2 plus swallow cells.
The main divider often combines the prescaler with a serial counter. This counter works with
lower frequencies, but it has no minimum count. The association of these two structures allows
for continuous counting between : [ (2
n
) , (2
n+m+1
– 1) ] ; with n defined above, and m the
number of flipflops in the shift counter.
It is important to remark that the output of both main and reference dividers, is in fact the
transcription of one pulse from the input signal, enabled by a programmable counter. In low
noise synthesizers, this output is often resynchronized with the input signal in order to copy its
phase accuracy; or in other words, to eliminate the time jitter introduced by the divider cells.
1.5.3 Phase Detector – Charge Pump
The phase detector and charge pump comparator is a three state phase/frequency detector. This
means that it can recover both phase and frequency differences within the VCO + PLL tunable
and programmable range.
As mentioned in section 1.4 the threestate phase detector has 2 memory nodes, which separately
track the two input phases. Figure 1.11 shows a block diagram of the ensemble.
18 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Figure 1.11 Phase Detector & Charge Pump block diagram
The Ref. (reference) input comes from the reference divider, and the Var. (variable) input from
the main divider. The rising edges of the input signals command the DFF outputs which in turn
command the switches of the sinking and sourcing current sources. When the two outputs are
equal to one, an asynchronous reset reinitializes the detector. In this manner phase differences of
up to t 2π are detected, with an average current output that is linearly proportional to the input
phase difference.
The sourcing and sinking sources have a programmable current value that is called charge pump
current, or I
cp
.
This phase detector with two DFFs, is not capable of distinguishing phase differences with a
module above 2π. So, when the module of the phase difference exceeds 2π, the phase detector
will slip one cycle and fall into a new linear zone around +2π or 2π.
Figure 1.12 represents the transfer, output average current for input phase deviation.
Note that the transfer is periodic over 2π, and that two shifted linear regions superpose each
other in every 2π interval.
The phase detector behaviour for phase deviations with a module smaller than 2π, is represented
by a single valued linear function with an input range: [2π, 2π]. The thick central line in figure
1.12 represents this function, and the slope of the transfer is called K
ϕ
, the phase detector
sensitivity.
Reference [Wola91] makes an interesting representation of different phase detectors, explaining
their functioning through logical state machines. The state machine of our threestate phase
detector is pictured on the right side of figure 1.12.
The delay interval of the assynchronous reset causes the existence of an intermitent 4
th
state
(Off’), during which both current sources are active. This state is usually transparent for the
transfer function, since ideally the sum of both currents equals zero. Functionally this delay
avoids a change in K
ϕ
for small input phase differences.
iii
iii
Charge pump circuitry has often slower settingup times than the asynchronous reset in the DFFs. Thus small
phase differences would be masked if the switching on interval was to small to guarantee that the current sources
attained their nominal output value. This phenomena is called deadzone.
programmable
input for I
cp
output tuning
voltage
1
Ref
D Qref
CK
R
Var
loop filter
impedance
delay
τ
rst
1
R
CK
D Qvar
Chapter 1 / Introduction 19
]
]
]
·
rad
A
I
K
cp
π
ϕ
2
(1.1)
Figure 1.12 Phase detector & Charge pump: transfer and state machine
The Off state is also called highimpedance or tristate, which explains the nomenclature tristate
detector. Tristate detectors can also be implemented with a voltage output. In this case the DFF
outputs command switches that short circuit the output to nodes with a fixed voltage value (low
impedance points such as vcc and gnd). However, the advantage of the current output becomes
clear with a capacitive loop impedance, because with the charge pump output a fixed current
value charges the filter capacitors with a constant dv/dt and K
ϕ .
1.5.4 Loop Filter
The loop filter is the main subject of chapters 2 and 4, while discussing stability and noise
concepts. It is a low pass filter (LPF) using either a passive (with no DC shift) or an active
solution. The active filters use a high gain amplifier with a large DC output range, in order to
increase the tuning range.
This chapter introduced the context of the present study, PLL frequency synthesizers, in a top
down approach.
The frontend of terrestrial and satellite TV receivers was discussed, identifying the tendencies for
innovation, that are bound to the new broadcasting standards (DVB) and to the continuous
demand for higher integration levels.
The investigation issues that orient this work were presented and related to the changes in the
tuner architecture.
The constituent blocks of the PLL synthesizer were also presented.

I
I
average
[A]
I
cp
∆ϕ
[rad]
4π 2π 0 2π 4π
τrst
Var
Ref
Ref
Sourcing
Qref =1
Qvar =0
Var
Sinking
Qref =0
Qvar =1
Off
Qref=Qvar=0
Off ’
Qref=Qvar=1
Var
Ref
20 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Chapter 2 / Phase Model for PLL Synthesizers 21
Contents:
2. PLL Phase Model and Loop Filter calculation 21
2.1. Phase Model for PLL synthesizers.......................................................................................................... 22
2.1.1. Requirements in the Time and Frequency Domain ....................................................................... 24
2.1.2. SecondOrder Loop ....................................................................................................................... 26
2.1.3. Third and Fourth Order Loops...................................................................................................... 28
2.2. Algorithm for the Loop Filter Calculation.............................................................................................. 34
2.2.1. Nominal Design............................................................................................................................. 34
2.2.2. Robust design including Gain Variation and 3
rd
Pole compensation............................................. 36
2.2.3. Summary of steps and numerical example .................................................................................... 40
Figures:
Figure 2.1 Linear Phase Model for a PLL ................................................................................................... 23
Figure 2.2 V
tune
time response for a frequency step...................................................................................... 25
Figure 2.3 Locked VCO output spectrum..................................................................................................... 25
Figure 2.4 3
rd
order Loop Filter Impedance................................................................................................. 29
Figure 2.5 4
th
order PLL: Open and Closed Loop Bode Plots ..................................................................... 31
Figure 2.6 4
th
order PLL: Root Locus diagram............................................................................................ 31
Figure 2.7 Gain Variation X Stability in Bode Plots .................................................................................... 33
Figure 2.8 The influence of r
21
in the gainbandwidth variation................................................................ 36
Figure 2.9 Numerical example of robust filter design.................................................................................. 42
Tables:
Table 21 2
nd
order filter: Phase Margin Variation for w
ol
∈ [ w
z1
, w
p2
] ............................................... 37
Table 22 3
rd
order filter: Phase Margin Variation for w
ol
∈ [ w
z1
, w
p2
]................................................ 38
Table 23 3
rd
order filter : Open Loop Bandwidth recentering................................................................... 39
2 PLL Phase Model and Loop Filter calculation
A linear time invariant (LTI) model for the PLL synthesizer is used to study frequency and time
domain characteristics.
The 2
nd
order loop is analyzed through standard dynamic parameters ξ and w
n
.
A new notation is introduced to study the 3
rd
and 4
th
order loops, exploiting stability and
robustness aspects.
The study is constantly linked to the tuner application context, through qualitative discussions
and numerical examples.
22 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
We start our study of PLL synthesizers presenting a linear phase model that simply and
efficiently describes most of the system behaviour around a locked condition. The linear
description is related to specifications in the time and frequency domain by using a standard
notation for a 2
nd
order lowpass filter, in terms of its natural resonance frequency (w
n
) and
damping factor (ξ). The description is enlarged to treat systems of a higher order. We introduce a
new notation in terms of the spacing between the zeros and poles of the transfer function of the
loop filter. The new notation is used to develop an algorithm to calculate loop filters that respond
to stability constraints in a large range of gain variation. The robustness of the method is
exemplified by numerical examples.
2.1 Phase Model for PLL synthesizers
From this chapter on, we focus on the phase locked loops for frequency synthesis, with the
following constituent blocks: programmable dividers, phase detector based on flipflops, and tri
state charge pump. We abbreviate it to PLL. In this nomenclature, the VCO block is not included
in the PLL.
A topdown approach is proposed starting with behavioural models that give an insight into
frequency and time domain characteristics. These models are based on a phase representation of
a PLL.
The phase representation concerns all logic signals that are inputs of edge triggered blocks.
These signals carry phase information that is related to the time interval (T) between similar
edges. We may also define an average or initial time interval (T
c
) and frequency (f
c
= 1/ T
c
),
and, a phase variation with respect to these.
Using the phase variation as the model parameter amounts to a baseband equivalent
representation, with phase modulating inputs and carrier f
c
.
The charge pump is replaced by a constant, average current to a phase deviation slope, with the
same sensitivity as a pulse width modulation block (PWM). This linear average sensitivity is
valid for phase differences smaller than 2π, as seen in section 1.5.3 .
In fact we seek a simple model where continuous linear time invariant (LTI) tools may be
applied. Such a representation is equivalent to the small signal AC models used for circuit
simulation. In our case its main limitations are the absence of DC range boundaries and the
removal of the discrete nature of the digital blocks (phase detector and dividers). These
characteristics are assessed later with additional modeling in chapter 5 .
For the moment, we consider that the PLL bandwidth is small enough compared to the phase
detector comparison frequency, and we suppose that this AC description is valid within the
whole DC range that may be swept.
The baseband phase model in Laplace transform is shown in the block diagram of figure 2.1,
with:
[ ]
[ ]
V
Hz
K
V
Hz rad
K
K
V d
f d
V d
w d
K
vco
o
vco
tune
osc
tune
osc
o
·
⋅
·
⋅ · ⋅ · · K π π 2 2
and K
ϕ
defined in equation (1.1)
Chapter 2 / Phase Model for PLL Synthesizers 23
Figure 2.1 Linear Phase Model for a PLL
The phase detector is replaced by an adder that continuously evaluates the phase difference
between the reference input and the divider output. This phase difference is transformed in an
average charge pump current, represented by the block with a sensitivity K
ϕ
.
The loop filter impedance, F(s), converts this current in V
tune
and the oscillator is depicted by its
frequency slope associated with an integrator.
The VCO is a frequency modulator with a voltage input and frequency selectivity determined by
its resonant circuit. Our applications use a second order LC resonator that is equivalent to an
integrator in a base band representation.
The linear approximation that allows the calculation of FM components by their peak phase
deviation, is valid for phase deviations considerably smaller than π.
Therefore ϕ
osc
(VCO output phase) is a valid approximation of the ratio:
modulated sideband amplitude divided by carrier amplitude,
for frequency modulating components with A
m
/f
m
<< π
i
where A
m
and f
m
indicate the amplitude and frequency of the modulating tone.
We define H(s) and B(s), as the open and closed loop transfers respectively.
s
F
s
s F
N
Kvco Icp
N s
K
s F K s H
o
ref
div
(s) ) ( 1
) ( ) ( ⋅ · ⋅
⋅
· ⋅ ⋅ ⋅ · · α
ϕ
ϕ
ϕ
(2.1)
with α, the open loop gain:
N
Kvco Icp ⋅
· α
) (
) (
) ( 1
) (
) (
s F s
s F
N
s H
s H
N s B
ref
osc
⋅ +
⋅
⋅ ·
+
⋅ · ·
α
α
ϕ
ϕ
(2.2)
It is convenient to split the filter impedance into two polynomials representing its zeros and
poles.
i
More detailed discussions of the narrow band FM context are made in sections 3.1 and 6.2.
for open loop
VCO
ϕ
osc
[rad]
+

Phase Detector
Charge Pump
Loop
Filter
Iaver
[A]
ϕ
div
[rad]
V
tune
[V]
ϕ
e
[rad]
ϕ
ref
[rad]
K
ϕ
F(s) K
o
/s
1/ N
24 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
) ( ) (
) (
) (
) (
) (
) (
) (
) (
) (
s N s D s
s N
N s B
s D s
s N
s H
s D
s N
s F
F F
F
F
F
F
F
⋅ + ⋅
⋅
⋅ ·
⋅
⋅
·
⇒ ·
α
α
α
Then we may see that B(s) have the same zeros as H(s), and, their poles are equal to H(s) for
α=0 (no feedback gain), and gradually change as α increases. This idea is very clearly
represented by the rootlocus diagram discussed in 2.1.3.
2.1.1 Requirements in the Time and Frequency Domain
The PLL system performances: locking time, step response overshoot, spurious rejection,
stability, closed loop bandwidth and peaking, need to be translated into transfer function
characteristics to guide the design of the control function (loop filter). A summary of these
specifications can be represented by time and frequency response envelopes, as shown in figures
2.2 and 2.3.
Let us choose two measurable signals for these envelopes such as V
tune
and the oscillator
spectrum.
The time response (figure 2.2) corresponds to a frequency change, like a step input for f
ref
, or a
ramp input for ϕ
ref
. Most often however, the frequency change is made by reprogramming the
main divider ratio, N.
The following parameters are indicated in the time response:
• v
initial
/ v
final
: initial and final values corresponding to the step input;
• M
p
: overshoot, normalized difference between maximum value and final
value;
• t
rise
: rise time with respect to a “y” fraction of the transition step;
• t
settling
: settling time for error within an acceptable x% variation around v
final
.
The frequency response (figure 2.3) represents the output spectrum of a VCO in lock mode. The
parameters indicating the frequency domain specifications are:
• P
carrier
: carrier output power;
• A
S
: comparison frequency suppression with respect to P
carrier
;
• (P
carrier
A
S
): spurious amplitude;
• f
o
: oscillator frequency;
• bw
cl
: closed loop bandwidth, or –3dB point with respect to the close in
spectrum;
• maximum peaking: maximum sideband value with respect to the closein spectrum.
The specifications indicated in the time and frequency envelopes are the guiding issues discussed
in the following sections.
Chapter 2 / Phase Model for PLL Synthesizers 25
Figure 2.2 V
tune
time response for a frequency step
Figure 2.3 Locked VCO output spectrum
We start with the time requirements that may be directly related to a standard 2
nd
order
characteristic equation. Later, we introduce a convenient notation for the 3
rd
and 4
th
order
systems, and a loop filter design algorithm to guarantee a robust stable functioning.
The frequency envelope is a combination of the PLL and the VCO performances. In this chapter
we focus on the PLL characteristics. Later, in chapter 3, the complete frequency envelope is
discussed, taking into account the inherent noise performance of the VCO. All the following
chapters use the filter notation and design tools developed in the present chapter.
v
initial
t (s)
(y).(v
final
v
initial
) + v
initial
(1+Mp).v
final
v
final
V
tune
(t) = f
o
(t)/K
vco
[V]
t
rise
t
settling
3dB
Power Spectrum Density (PSD)
[dB]
maximum
peaking
P
carrier
A
S
P
carrier
f
osc
+ bw
cl
f
osc
f
osc
+ f
cp
f (Hz)
26 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
2.1.2 SecondOrder Loop
We start searching for the simplest filter that would present a time response with the form
indicated in figure 2.2.
As a matter of fact, an allpass filter (simple resistor) combined with the oscillator pole would
already present a lowpass filter behaviour for the overall loop.
However for a PLL with a phase detectorcharge pump comparator, it is useful to guarantee that
a frequency step is perfectly followed, having a final phase error that tends to zero.
ii
In our phase model the zero final error for a phase ramp input implies an H(s) with two pure
integrators.
One integrator is intrinsic to the VCO phase representation, and the other must be included in the
loop filter, F(s).
A feedback system with two integrators and no zero would be an oscillator, frequency controlled
by the loop gain, so we must also include a zero in F(s) for stability reasons. Therefore the
simplest form of F(s) is:
C s
T s
s F
⋅
⋅ +
·
1
) (
;
which corresponds to the impedance of a RC series branch, with T=R.C s/rad.
The open and closed transfer functions for the resulting 2
nd
order PLL are:
( )
( )
.
) (
) (
1
1
) ( ) (
) (
) (
;
) (
) ( 1
) (
2
2
s D
s N
T s
C
s
T s N
s N s D s
s N
N s B
s D
s N
C s
T s
s H
B
B
F F
F
F
F
·
+ ⋅ + ⋅
⋅ + ⋅
·
⋅ + ⋅
⋅
⋅ ·
⋅
·
⋅
⋅ + ⋅
·
α
α
α
α α
Comparing D
B
(s) to a standard 2
nd
order equation, with w
n
,undamped natural frequency, and ξ,
damping factor, results in:
( ) ( )
C
w
R
w
C
w
s
w
s
T s N
T s
C
s
T s N
s B
n
n
n n ⋅
⋅
·
⋅ ⋅
·
·
+
,
`
.
 ⋅
⋅ +
,
`
.

⋅ + ⋅
÷→ ←
+ ⋅ + ⋅
⋅ + ⋅
·
α
ξ
α
ξ
α
ξ
α
2 2
1
2
1
1
1
2
2
2
L ) (
(2.3)
ii
Otherwise the error response stabilizes around ϕ
efinal
, which implies that even in lock, the charge pump is still
injecting an average current (K
ϕ
. ϕ
efinal
), which may increase significantly the reference spurious.
Iin
Vout
R
C
Chapter 2 / Phase Model for PLL Synthesizers 27
The advantage of this ξ, w
n
representation is its direct relation to frequency and time responses.
For instance the unitary step response of 1/D
B
(s) is:
( )
( ) ( )
,
`
.

⋅ ⋅ + ⋅ ⋅ − ÷→ ←
+ + ⋅
·
⋅
⋅ −
t w
w
t w e
w s w s s
w
s D s
d
d
d
t
n n
n
B
sin cos 1
2
) (
1
2 2
2
σ
ξ
σ
{ ¦
{ ¦
Im 1
1
2 , 1
2 , 1
2
2
2 , 1
s Re w
s w w
w j w j w s
n
n d
d n n
· ⋅ ·
· − ⋅ ·
⋅ t − · − ⋅ ⋅ t ⋅ − ·
ξ σ
ξ
σ ξ ξ
where overshoot and settling time can be derived as functions of w
n
and ξ.
Using the same variables, w
d
and σ, we find a similar step response for B(s):
( )
( )
( ) ( )
¹
¹
¹
'
¹
¹
¹
¹
'
¹
,
`
.

⋅ − ⋅ − ⋅ · ÷→ ←
+ + ⋅
+
⋅ ·
⋅ −
t w
w
t w e N t y
w s w s s
s w w
N
s
s B
d
d
d
t
n n
n n
sin cos 1 ) (
2
2
2 2
2
σ
ξ
ξ
σ
(2.4)
The integration property of the Laplace transform can be applied to equation (2.4) to derive the
ramp response of B(s). We may also recognize that y(t) represents the derivative of ϕ
osc
(t) for the
ramp input, which is the oscillator instantaneous frequency: 2π.f
osc
(t), or V
tune
(t).K
o
.
Therefore the time response of the 2
nd
order loop is simply fitted in its envelope requirement
through a convenient choice of σ and w
d
, or ξ and w
n
.
Next, the values of the filter components are evaluated with expressions (2.3) using ξ, w
n
and the
open loop gain, α.
Let us now consider the frequency domain envelope.
Some aspects of the output spectrum may be obtained from the frequency response of the closed
loop, B(jw).
The oscillator output spectrum results from a combination of the PLL and VCO frequency
responses. The PLL response is given by B(jw), and the input is the overall phase disturbances
due to the PLL blocks, represented at the input of the phase detector.
The 1
st
order filter, with a single integratorzero, has a B(jw) close to a low pass filter (LPF),
with a 20dB/dec attenuation for w>>w
n
, and a resonant peak inversely proportional to ξ.
Hence the choices of w
n
and ξ, are a compromise between the time and frequency domain
specifications.
Generally the resonant peak should be kept to its minimum, since it increases noise presence at
the output, and it indicates the system is approaching instability. Typically ξ is kept above 0.7.
The choice of the bandwidth, w
n
, depends on many parameters. We have already seen the rise
time and settling time in V
tune
time response, and through the following chapters we tackle other
parameters, such as:
: roots of D
B
(s)
: damped natural frequency
: exponential envelope factor
28 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
• comparison frequency (f
cp
), requirement of spurious suppression, VCO freerunning noise
performance, maximum phase change for small frequency steps, and microphony and other
interference robustness.
These questions belongs to quite different contexts, from the VCO output spectrum to a broader
context including requirements from the application environment and from the demodulator
block.
At the moment we can state a 1
st
rule of thumb, common to synthesizer applications that use w
n
in the range:
10 30
cp
n
cp
w
w
w
≤ ≤
So far we have discussed ξ and w
n
choices for a unique, unchanging open loop gain (α) value.
However we need to keep in mind that α can vary a lot in certain synthesizer applications and
this variation needs to be accommodated by the filter dimensioning.
In these terms the 2
nd
order PLL is very convenient since it only imposes a minimum gain value
related to a minimum ξ, and elsewhere it is convergent.
Nevertheless, its attenuation for high frequency (w>>w
n
) is often not enough to suppress the
reference spurious to a satisfactory level. In addition the closed loop transfer B(s) for a 2
nd
order
loop leaves the phase noise contribution of the PLL visible within a 20dB/dec slope, which is
equal to the slope of the VCO intrinsic noise. This means that a poor noise performance of the
PLL would be visible even for frequencies above the closed loop bandwidth.
Indeed, most tuner synthesizers use 3
rd
order loop filters, resulting in a 4
th
order PLL.
As we evolve towards higher order loops, the closed loop transfers are not so easily perceived as
the second order B(s), because their characteristic function, D
B
(s), is not directly factorable in 2
nd
or 1
st
order polynomials.
Thus, before discussing further aspects of the frequency envelope requirements we introduce
some stability concerns in the 3
rd
and 4
th
order loops.
Since we treat fairly simple systems with no zeros or poles in the right hand plane (on a Splane),
the stability may be unambiguously analyzed by the open loop frequency response parameters:
phase margin (PhM) and gain margin (GM).
2.1.3 Third and Fourth Order Loops
Before we may examine the stability conditions of a 3
rd
or 4
th
order PLL, we need to introduce
the corresponding loop filter impedance, and the resulting open and closed loop frequency
responses.
As mentioned in the previous section, most synthesizer applications use a 2
nd
or 3
rd
order loop
filter, in order to achieve the necessary outofloop rejection.
These filters are implemented with additional resistors and capacitors, introducing one or two
extra poles at frequencies higher than the zero frequency. The pole at the origin is preserved to
fulfill the steady error condition discussed in 2.1.2.
The following notation is adopted for the zeros and poles, frequencies and time constants:
π π 2 2
1
1
1
1
z
z
z
w
T
f ·
⋅
· : with f
z1
and T
z1
, zero frequency [Hz] and time constant [s/rad];
Chapter 2 / Phase Model for PLL Synthesizers 29
π π 2 2
1
2
2
2
p
p
p
w
T
f ·
⋅
· and
π π 2 2
1
3
3
3
p
p
P
w
T
f ·
⋅
·
for the 2
nd
and 3
rd
poles, remembering that the 1
st
pole is a pure integrator with f
p1
= 0 Hz.
The resulting 3
rd
order filter is:
( )
( ) ( )
3 2
1
1 1
1
) (
p p
z
T s T s s
T s k
s F
⋅ + ⋅ ⋅ + ⋅
⋅ + ⋅
· (2.5)
A second order filter is obtained if either f
p2
or f
p3
tend to infinity. By convention our 2
nd
order
filter has a finite f
p2
, and a T
p3
= 0.
The two RC filter configurations below have approximately this transfer function as impedance:
Figure 2.4 3
rd
order Loop Filter Impedance
The filter impedances, Z
s
and Z
p
, are calculated as independent 2
nd
order terms, supposing that
the approximations: Z
3
>> Z
p
, and Z
3
>> Z
s
are valid.
These approximations are made to keep a transfer with real factorable poles, which greatly
simplify the filter design. Its accuracy holds for f
p3
>> f
p2
.
iii
( )
( )
]
]
]
+
⋅
⋅ ⋅ + ⋅ + ⋅
⋅ ⋅ +
· ·
2 1
2 1
1 2 1
1 1
1
1
C C
C C
R s C C s
C R s
I
V
Z
in
M
p
;
( )
( )
2 1 1
2 1 1
1
1
C R s C s
C C R s
I
V
Z
in
M
s
⋅ ⋅ + ⋅ ⋅
+ ⋅ ⋅ +
· · ; and,
3 3 3 3
1
1
1
Z C s C R s V
V
M
out
⋅ ⋅
·
⋅ ⋅ +
·
Z
p
and Z
s
are composed of an integrator plus a leadlag, zeropole, pair.
The single pole low pass filter (LPF), associated with Z
3
, is often called a postfilter.
A second approximation is made considering C
1
>> C
2
⇒ C
1
+ C
2
≈ C
1
, which simplifies Z
F
(s)
in both cases to:
iii
The complete 3
rd
order, nonfactorable, transfer is discussed in section 4.1.
R
1
I
in
R
3
Z
3
Z
p
C
1
V
out
C
2
C
3
V
M
Z
3
R
3
Z
s
I
in
V
out
R
1
C
1
C
2
C
3
V
M
30 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
( ) ( )
3 3 2 1 1
1 1
1 1
1
) (
C R s C R s C s
C R s
I
V
s Z
in
out
F
⋅ ⋅ + ⋅ ⋅ ⋅ + ⋅ ⋅
⋅ ⋅ +
· ·
Z
F
(s) corresponds to F(s) for:
T
z1
=R
1
.C
1
; T
p2
=R
1
.C
2
; T
p3
=R
3
.C
3
;
K = 1/C
1
; and, f
p3
>> f
p2
>> f
z1
.
The spacing between f
z1
and f
p2
, is justifiable by the fact that the zero influence in pulling up the
phase from its initial value (for w << w
z
) of 180° , is only visible if:
f
z1
<< f
p2
⇒ T
z1
>> T
p2
; but since T
z1
/ T
p2
= C
1
/ C
2
⇒ C
1
>> C
2
the open and closed loop transfer functions of the PLL with this 3
rd
order filter become:
( )
( ) ( )
3 2 1
2
1
1 1
1
) (
p p
z
T s T s C s
T s
s H
⋅ + ⋅ ⋅ + ⋅ ⋅
⋅ + ⋅
·
α
(2.6)
( )
( ) ( ) ( )
1 3 2 1
2
1
1 1 1
1
) (
z p p
z
T s T s T s C s
T s
N s B
⋅ + ⋅ + ⋅ + ⋅ ⋅ + ⋅ ⋅
⋅ + ⋅
⋅ ·
α
α
(2.7)
Root locus and Bode diagram sketches showing PhM, GM, Mr, w
3dB
, and the closed loop root
asymptotes are plotted in figures 2.5 and 2.6.
The closed loop magnitude Bode plot suggests a PLL phase transfer resembling a 3
rd
order LPF.
This resemblance is confirmed by the rootlocus that has for adequately high open loop gains, α,
one pole that tends to the zero (being “cancelled”), and three others that tend to the asymptotes:
180° + k.360° / n ; with n=3 , and k = 0, 1, 2.
The 3
rd
order LPF approximation for B(s) would have a transfer function, B
3LPF
(s) , in the form:
( )
) (
1
2
1
) (
3
2
2
3
s B
w
s
w
s
T s
N
s B
LPF
n n
p
·
,
`
.

+
⋅ ⋅
+ ⋅ ⋅ +
≈
ξ
(2.8)
where T
p3
is the postfilter equivalent pole, and the second order function in the ξ w
n
form
represents the two other roots. These last two may be complex or real, depending on the value
of α.
This simplified LPF form suggests a 1
st
stability boundary, analogous to a standard 2
nd
order
characteristic equation, expressed in terms of ξ and w
n
.
iv
The boundary imposes a minimum ξ
value that may be represented in the rootlocus diagram.
iv
Later, in 3.4.1 , the LPF approximation is also used to evaluate the 3 dB closed loop bandwidth, indicated as f
cl3dB
in figure 2.5.b.
Chapter 2 / Phase Model for PLL Synthesizers 31
Figure 2.5 4
th
order PLL: Open and Closed Loop Bode Plots
Figure 2.6 4
th
order PLL: Root Locus diagram
fig. 2.5.a
log( f ) [Hz]
f
p3
f
p2
f
z1
PhM
max
∠H(jw)
[ ° ]
90°
180°
270°
H(jw)
[ dB ]
60dB/dec
20dB/dec
40dB/dec
log( f ) [Hz]
f
p3
f
p2
f
z1
Open Loop : H(s)
f
cl3dB
f
cl3dB
log( f ) [Hz]
f
p3
f
p2
f
z1
∠B(jw)
[ ° ]
90°
180°
270°
B(jw)
[ dB ]
N
N3dB
log( f ) [Hz]
f
p3
f
p2
f
z1
40dB/dec
60dB/dec
Closed Loop : B(s)
fig. 2.5.b
Re{s}
Root Locus Im{s}
45°
ξ=1/√2
f
z1
f
p3 f
p2
32 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
In figure 2.6, the dotted axes indicate a boundary of
2
1
· ξ .
We observe that the gain value, α, has a minimum and a maximum limit value to ensure that the
complex roots have a convenient damping, ξ. In fact for increasing α values, these two branches
will finally cross the imaginary axis indicating an unstable behaviour.
For a 2
nd
order filter, there are only three root branches. One is still directed towards the zero,
and the other two tend to asymptotes parallel to the imaginary axis. Therefore the loop does not
become unstable for increasing α values, but less and less damped as the equivalent ξ for the
complex roots tends to zero.
This same reasoning can be applied to the open loop Bode diagram, where a changing α value
corresponds to shift the magnitude curve vertically, without moving the phase plot.
This variation also shows a limitation for a minimum and a maximum value of α, in trying to
keep the phase margin above a suitable value.
A classical security limit for a system phase margin is about: PhM ≥ 30° .
Figure 2.7 shows open and closed loop Bode plots with three different gain values:
• a centered value, α
n
, corresponding to the maximum phase margin for a 2
nd
order filter (or a
3
rd
order loop);
• and two other gain values, geometrically equidistant to α
n
.
The curves plotted with dotted lines indicate the 3
rd
order loop transfer for the centered gain
value, α
n
. The curves with solid lines correspond to the 4
th
loop transfer with the 3 α values.
The gain variation chosen is proportional to the leadlag, zeropole spacing, since,
21
21
21
min
max
r
r
r
n
n
·
⋅
·
α
α
α
α
and r
21
is defined as
1
2
21
z
p
f
f
r · .
The filter calculation and the maximum supported gain variation are discussed in the following
sections. For the moment we observe some new parameters introduced in figure 2.7:
½ in the open loop diagrams:
• w
ol
: open loop zero crossing frequency or open loop bandwidth;
• w
oln
: central w
ol
corresponding to the centered gain α
n
;
½ in the closed loop diagrams:
• peak: resonant overshoot with respect to the closein, low frequency, B(jw) value;
• w
peak
: frequency corresponding to the peak value;
• w
3dB
: 3dB closed loop bandwidth, as indicated in figure 2.5.b.
Chapter 2 / Phase Model for PLL Synthesizers 33
Figure 2.7 Gain Variation X Stability in Bode Plots
Remembering that α = (Icp . Kvco)/ N, and that its variation represents the system functioning
range, we must adapt F(s) parameters to fit α ∈ [α
min
, α
max
] and to meet the frequency and time
specifications.
In this example we observe that a gain variation of r
21
implies quite significant variations of
bandwidth and PhM.
Furthermore the centered gain value for the 3
rd
order loop, α
n
, is not really ideal for the 4
th
order
loop.
Thus in the next sections we define successively:
 a filter calculation algorithm for the 2
nd
order filter;
 a centering compensation for the 3
rd
order filter;
 and the relation between the zeropole spacing and the maximum supportable gain variation.
fig. 2.7.a fig. 2.7.b
34 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
2.2 Algorithm for the Loop Filter Calculation
TV tuner applications very often work with quite large variations in the parameters:
K
vco
and N.
K
vco
variations are connected to the oscillator tank circuit sensitivity. In varicap based tank
circuits, the sensitivity is proportional to the varicap capacitance variation dC/dV
bias
.
Typically this capacitance variation decreases for high V
bias
values, i.e. for high values of V
tune
,
or at the highend of the tuning range.
N variation is directly proportional to the frequency variation inside the tuning range, plus
eventually a multiplication factor to compensate changes in the reference divider ratio, R.
Taking into account these two variations and one fixed I
cp
value results in the maximum α range
demanded by the application.
Furthermore the minimum α value is found at the high end of the VCO frequency spectrum,
corresponding to the minimum K
vco
and maximum N values and viceversa for the maximum α
value.
In terrestrial applications, with a fixed I
cp
value, it is not rare to find α variations (α
max
/α
min
)
higher than 100. In satellite applications they are typically to the order of 50.
In the case of such large variations it is wise to use different I
cp
values to reduce the variation,
especially if the output spectrum needs to be optimized for noise performance.
However for stability reasons and user flexibility, the filter design should be centered, to ensure
the best application robustness, and as far as possible cope with all the gain variation range.
2.2.1 Nominal Design
Direct solving of the 4
th
order B(s) denominator with respect to f
ol
or w
3dB
would be onerous and
not very enlightening with respect to the stability aspect or for an intuitive and quick filter
calculation method.
Taking the phase margin aspect as a departure point and expressing it with respect to the ratios,
pole frequencies divided by zero frequency, leads to a simpler approach. Let us define r
31
and
recall r
21
:
1
3
31
1
2
21
;
z
p
z
p
f
f
r
f
f
r · · ;
and express phase margin as a function of f
ol
(w
ol
/2π ), and the zero and poles frequencies.
,
`
.

−
,
`
.

−
,
`
.

· ° − − ∠ ·
·
3 2 1
) 180 ( ) (
p
ol
p
ol
z
ol
ol
w w
f
f
arctg
f
f
arctg
f
f
arctg jw H PhM
ol
(2.9)
The maximum PhM point is somewhere between f
z1
and f
p2
, and intuitively we may say that if
f
p3
is distant enough not to have much influence on H(jw
ol
), it should be equidistant to both f
z1
and f
p2
.
Chapter 2 / Phase Model for PLL Synthesizers 35
This idea can be confirmed solving:
[ ] 0 ) ( · f PhM
df
d
with the approximation w
ol
<< w
p3
which result in:
) ( ) ( ) (
2 1 p z
T w arctg T w arctg w PhM ⋅ − ⋅ ≈
and max{PhM} for
21
2
21 1 2 1
r
f
r f f f f
p
z p z
· ⋅ · ⋅ · .
Choosing this maximum PhM frequency as f
ol
, makes:
( )
]
]
]
]
,
`
.

+ ° − ⋅ ·
31
21
21
90 2 ) (
r
r
arctg r arctg w PhM
ol
(2.10)
The maximum phase margin point should be adjusted to correspond to the geometrical average
of the open loop gain range. So that gain variations towards minimum and maximum values
imply phase margin variations around the maximum point.
( ) 1
oln
·
·
·
n
w w jw H
α α
[ ]
α α α α α α ∈ ∧ · ⋅
min max min max
,
n
( )
( )
1
/ 1 1 1
1
21
1
2
oln
1
1
supposing
2
31 21 21
21
1
2
oln
oln
31
21
· ⋅
⋅
÷ ÷ ÷ → ÷
+ ⋅ +
+
⋅
⋅
·
>>
>>
·
r
C w
r r r
r
C w
jw H
n
r
r
n
n
α α
α α
(2.11)
. ;
;
1
;
oln 31
21
3 3 3
21
1
1
1
2
1
2
2
oln
1 1 1
1
1
oln 1
2
oln
21
1
w r
r
C R T
r
C
C
T
T
R
T
C
w
C w C
T
R
w w w
r
C
p
z
p p
n z
z
z
n n
⋅
· ⋅ · · ⋅ · ·
·
⋅
· ·
⋅
·
⋅
·
⇒
α
α α
(2.12)
The expressions above allow for the calculation of the filter components, following a maximum
phase margin approach. They are valid for both 2
nd
and 3
rd
order filters.
The positioning of f
z1
and f
p2
, the leadlag controller, is made with respect to a 2
nd
order filter.
The influence of the postfilter is taken into account in expressions (2.9) and (2.10) for the total
PhM, but it was not considered in the choice of the center or nominal gain value α
n
.
A compensation for this gain centering, with respect to the PhM loss due to the postfilter, is
discussed in the following section.
36 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
2.2.2 Robust design including Gain Variation and 3
rd
Pole compensation
We wish to investigate the maximum gain variation that we are able to accommodate within
convenient PhM values.
In fact expression (2.9) shows that for fixed filter parameters, the phase margin depends uniquely
on the open loop zero cross frequency, f
ol
.
Thus, we need to translate the gain variation in an open loop bandwidth variation, in order to
associate gain values with PhM values.
Figure 2.8 gives an intuitive approach to the relation gainbandwidth with respect to the filter
design parameter, r
21
, i.e., the influence of r
21
in the variation of w
ol
with respect to α.
The sketches show two extreme situations, for large and small r
21
values:
• for small r
21
(approximately r
21
< 10). The open loop slope stays practically unchanged
around the w
ol
frequency, with a 40 dB/dec value, and w
ol
changes are proportional to
sqrt(α).
• for large r
21
(approximately r
21
≥ 25), the slope around w
ol
decreases to 20 dB/dec and w
ol
changes are proportional to α.
Figure 2.8 The influence of r
21
in the gainbandwidth variation
In other words, w
ol
variation with respect to α may be expressed as:
( )
21
ln
r f
n o
ol
w
w
,
`
.

·
α
α
(2.13)
with: ( ) 1 5 . 0
21
< < r f ; and,
( )
( ) 1 lim
5 . 0 lim
21
21
0
21
21
·
·
∞ →
→
r f
r f
r
r
log (f )
[Hz]
log (f )
[Hz]
w
1
w
2
w
3
f
p3
f
p2
f
z1
H(jw)
[ dB ]
sqrt(r
21
) → 1
f
p3
f
p2
f
z1
H(jw)
[ dB ]
w
1
w
2
w
3
sqrt(r
21
) >> 1
α
1
< α
2
< α
3
α
i
↔ w
i
Chapter 2 / Phase Model for PLL Synthesizers 37
A formal solution for f(r
21
) would require solving 3
rd
and 4
th
order polynomial equations.
Using polynomial interpolation in numerical examples, we find a simpler form for f(r21), which
is quite accurate around the central point, w
ol
/w
oln
= 1.
21
21
1
1
) (
r
r f
+
≅
(2.14)
The interpolation error is evaluated for PhM variations with respect to the central PhM value.
For gain values implying a phase margin variation ≤ 20°, the bandwidth ratio is estimated with a
maximum 5% error.
We consider the error acceptable, and expression (2.14) is used to evaluate the following issues
concerning the maximum supported gain variation and the filter recentering with respect to the
postfilter.
We start evaluating the gain range corresponding to w
ol
variations between w
z1
and w
p2
, for the
2
nd
order filter.
Table 2.1 shows some PhM values for r
21
values commonly found in tuner applications.
v
The PhM values are calculated at:
 w = w
oln
;
 w = w
z1
, or w = w
p2
, (with no postfilter we find the same PhM for both points).
max{PhM} [°] PhM [°] (α
n
/ α
min
)
2
with w
ol
=w
oln
w
ol
=w
z1
or w
ol
=w
p2 α
n
=>w
ol
=w
oln
r
21
w/o postfilter w/o post filter α
min
=>w
ol
=w
z1
f (r
21
)
10 54.90 39.29 20.71 0.760
15 61.04 41.19 30.18 0.795
20 64.79 42.14 39.08 0.817
25 67.38 42.71 47.59 0.833
Table 21 2
nd
order filter: Phase Margin Variation for w
ol
∈ [ w
z1
, w
p2
]
The last column gives the gain range values corresponding to the open loop bandwidth variation:
( )
21
1
oln
2
min min
max
max 2
min 1
r f
ol n
p ol
z ol
w
w
w w
w w
,
`
.

·
,
`
.

·
⇔ ·
⇔ ·
α
α
α
α
α
α
The ratio α
n
/ α
min
is evaluated according to the f (r
21
) approximation ( equation (2.14) ).
In fact for this α variation corresponding to w
ol
=w
z1
or w
ol
=w
p2
, the bandwidth variation is a
function of a unique variable: r
21
. It follows that:
v
PhM values are calculated using expression (2.10) .
38 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
( )
21
21
1
1
21
1
z1
2
min
max
r
r f
p
r
w
w
+
·
,
`
.

·
α
α
(2.15)
For restricted domains of r
21
,we may use a linear estimation of equation (2.15), with a
normalized error smaller than 5%:
[ ]
[ ] 31 , 12 ; 95 . 1
25 , 4 ; 2
21
21
21
1
1
21
21
∈ ·
∈ ·
⋅ ≈
+
r K
r K
r K r
r
L L
(2.16)
The r
21
range between 4 and 25 covers quite well the values used in our tuner applications.
We consider that the minimum acceptable PhM value is 30°.
So, combining the results of table 21 and expressions (2.15) and (2.16), shows that normalized
gain variations of (2.r
21
) can be accommodated within suitable PhM values.
We are implying that r
21
is chosen in relation to: the maximum PhM required, and, the gain
variation ratio.
We continue our analysis including the postfilter for the 3
rd
order loop filter.
Table 22 brings some PhM values for sets of r
21
and r
31
parameters.
The PhM values are calculated at:
 w = w
oln
with and without postfilter;
 w = w
z1
, and w = w
p2
, with postfilter (different PhM values for the 2 points).
max {PhM} [°] {PhM} [°] PhM [°] PhM [°]
with w
ol
=w
oln
with w
ol
=w
oln
with w
ol
=w
z1
with w
ol
=w
p2
r
21
r
31
w/o postfilter w/ postfilter w/ post filter w/ post filter
r
31
/ r
21
15 25 61.04 52.24 38.90 10.22 ♣ 1.67
15 40 61.04 55.51 39.75 20.63 2.67
25 30 67.38 57.92 40.80 2.90 ♣ 1.20
25 50 67.38 61.67 41.56 16.14 ♣ 2.00
(♣) : unacceptably low PhM values.
Table 22 3
rd
order filter: Phase Margin Variation for w
ol
∈ [ w
z1
, w
p2
]
Phase margin differences for zero cross frequencies at w
z1
and w
p2
,with postfilter, show the
influence of w
p3
in the PhM for gain values α > α
n
.
A certain minimum r
31
/r
21
ratio is necessary to keep a PhM ≥ 30° for a α range with
α
max
/ α
min
≈ (2.r
21
) .
Actually, the effect of w
p3
is already visible in the PhM of the centered bandwidth, w
oln
, as
shown in figure 2.7 and table 22 .
Chapter 2 / Phase Model for PLL Synthesizers 39
So, we wish to find a correction factor to recenter the open loop bandwidth around the maximum
PhM for a given set of r
21
and r
31
parameters.
Using a 1
st
order limited development for equation (2.10), enables us to find a simple
polynomial correction factor, r
pf
(postfilter factor). The estimated centered bandwidth is named
w
olnpf
, and the related gain value α
npf
.
]
]
]
−
·
31
21 31
r
r r
r
pf
1 0 ≤ ≤
pf
r K K (2.17)
pf
r
w
w
olnpf
oln
·
olnpf oln
w w ≥ K K (2.18)
( )
,
`
.

+
,
`
.

,
`
.

⋅ ·
,
`
.

⋅ ·
2
1
1
1 21
21
1 1
r
pf
npf
r f
pf
npf n
r
r
α α α
npf n
α α ≥ K K (2.19)
Table 23 shows numerical examples of the postfilter recentering. The same values for r
21
and
r
31
used in table 22 are recalculated after repositioning the central open bandwidth around w
olnpf
.
PhM [°]
for α
npf
PhM [°]
for α
min
PhM [°]
for α
max
∆ (PhM)
r
21
r
31
(r
pf
)
0,5
w
ol
= w
olnpf
w
ol
=w
olnpf
/(r
21
)
0,5
w
ol
=w
olnpf
.(r
21
)
0,5
r
31
/r
21
PhM(wz1)  PhM(wp2)
15 25 0.632 52.92 28.45 30.89 1.67 2.44
15 40 0.791 56.00 34.18 30.34 2.67 3.84
25 30 0.408 55.34 20.49 43.41 1.20 22.92 ♣
25 50 0.707 62.11 32.83 32.03 2.00 0.81
(♣) : recentering approach fails.
Table 23 3
rd
order filter : Open Loop Bandwidth recentering
The recentering approximation is quite effective for (r
31
/ r
21
) > 1.6 ; but it cannot be used for
smaller ratios, since the accuracy is quickly degraded.
vi
The bandwidth ratio (w
olmax
/w
olmin
), used in table 23 , is also equal to r
21
; so, the corresponding
gain variation is approximately (2.r
21
) .
Hence, we observe that recentered 3
rd
order filters can also cope with the normalized gain
variation, equal to (2.r
21
) , as far as the minimum ratio, [(r
31
/ r
21
)>1,6 ], is respected.
In practice for (r
31
/ r
21
)< 1.6 , it is not possible to accommodate the normalized gain variation
with PhM ≥ 30° .
The limit (r
31
/ r
21
) ratio imposes a condition for the postfilter placement.
vi
As a matter of fact for small (r
31
/ r
21
) ratios we also loose the accuracy of the filter transfer function, as discussed
in section 2.1.2, and quantified in 4.1.1.
40 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
In fact, placing the postfilter pole is a compromise between PhM loss and spurious suppression
requirement. The latter would ask to place it as close as possible to f
p2
, but a minimum PhM, in
a given α range, has to be preserved.
Once the postfilter pole position is chosen, R
3
and C
3
values may be directly calculated.
There is a limitation concerning the R
3
/R
1
ratio, that is discussed further in section 4.1. For the
moment let us keep in mind a practical boundary suggesting : R
3
≥ R
1
.
In some applications we can also see an influence of the C
3
value with respect to the resonant
tank circuit of the oscillator. In these cases C
3
, which appears as a parallel, parasitic capacitance,
should be chosen to be as small as possible.
So far so good, since these two practical boundaries tend to the same direction; for a given T
p3
,
we should choose a large R
3
and a small C
3
. However as usual, there is an additional factor
imposing a compromise.
C
3
and a series resistor connecting the loop filter to the tank resonator, form an LPF, whose
function is to block the VCO signal leaking towards V
tune
. Thus, we should keep a certain
minimum C
3
to assure the necessary RF attenuation.
2.2.3 Summary of steps and numerical example
The points discussed up to now suggest sequential steps for the loop filter calculation following
the maximum phase margin approach, and the recentering correction:
(a) Evaluate the system open loop gain range, corresponding to the functioning conditions.
Calculate the geometrical average (α
n
) and the variation ratio, α
max
/ α
min
.
: usually lower part of frequency range;
: higher part of frequency range.
If gain variations are too large, α
max
/ α
min
≥ 100 , look for possible compensations choosing a
specific Icp value for extreme cases.
(b) Choose parameters r
21
and r
31
taking into account PhM requirements and α ratio.
6 . 1 ;
2
1
21
31
min
max
21
≥ ⋅ ≥
r
r
r
α
α
(c) Choose w
olnpf
with respect to the following parameters: switching time, spurious attenuation
and adequacy to the noise performance of the VCO.
(d) Recenter α
n
with respect to (r
31
/ r
21
) ratio, for gain and cross frequency variation around α
npf
and w
olnpf
.
For
min max
α α α ⋅ ·
npf
and
]
]
]
−
·
31
21 31
r
r r
r
pf
α
α
α
·
⋅
·
⋅
·
⋅
Icp Kvco
Ndiv
Icp Kvco
Ndiv
Icp Kvco
Ndiv
max
max max
min
min
min min
max
Chapter 2 / Phase Model for PLL Synthesizers 41
pf
r
w
w
olnpf
oln
·
and
,
`
.

+
,
`
.

⋅ ·
2
1
1
21
1
r
pf
npf n
r
α α
(e) Evaluate filter components using recentered w
oln
, α
n
and expressions (2.12) .
In the case of a 2
nd
order loop filter, the same algorithm can be used ignoring the recentering
correction. So after choosing the central open loop bandwidth , w
oln
in this case (item (c) ), we
skip item (d) and calculate the filter components directly with expressions (2.12) .
The open loop bandwidth choice is the remaining compromise that is not completely discussed.
As we mentioned in section 2.1.2. it depends on many parameters including circuit and system
requirements. In chapter 3 we discuss a significant parameter, the phase jitter, concerning the
total phase noise power in the carrier.
Finally we present a numerical example to illustrate the recentering plus the normalized gain
variation. In figure 2.9 the graphs use the same r
21
and r
31
values as in figure 2.7. :
r
21
=25 ; r
31
=50; and,
21
min
max
2 r ⋅ ·
α
α
.
Some other parameters are also indicated:
• w
z1
( o ) ; w
olnpf
( * ) ; w
oln
( ) ; w
p2
( x ) ; w
p3
( x ) ;
• w
peak
: frequency corresponding to the maximum value of closed loop
magnitude;
• w
3dB
: frequency corresponding to the DC value –3dB in closed loop
magnitude;
• peak: maximum value –DC value for the closed loop magnitude;
• dPhB(jw)/Foct :
( ) [ ]
w
jw B phase
∆
∆
with ∆w an octave frequency delta around w
peak
.
Analogous to the 2
nd
order example in annex IIA, a steep phase change
corresponds to a bigger overshoot.
42 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Figure 2.9 Numerical example of robust filter design
We verify that the centering compensation is effective and that the normalized (2.r
21
) gain
variation is conveniently fitted.
Therefore the polynomial approximations used in the development are accurate enough for our
applications.
The filter algorithm and the associated notation, through frequency ratios, proved to be quite
adequate to design and compare loop applications in a systematic and simple manner.
They are continuously applied in the following chapters.
The numerical examples of figures 2.7 and 2.9 are calculated with a mathematical simulation
software, Matlab. The graphs are the output of executable files that are programmed with
parametric inputs, being a flexible calculation tool.
The tables are also an interesting design tool easily implemented in any spreadsheet software.
fig. 2.9.a Open Loop fig.2.9.b Closed Loop
Chapter 3 / Application Related Constraints 43
Contents:
3. Application Related Constraints 43
3.1. Reference Breakthrough ......................................................................................................................... 44
3.2. VCO Noise Representation and Phase Noise Units ................................................................................ 46
3.3. Optimum Closed Loop Bandwidth .......................................................................................................... 50
3.4. PLL Closed Loop Bandwidth .................................................................................................................. 52
3.4.1. w
3dB
derivation from B
RL
(s)........................................................................................................... 53
3.4.2. w
3dB
derivation from w
as
................................................................................................................ 59
3.5. Maximum Phase Jitter ............................................................................................................................ 61
3.6. Gain Stability Boundary.......................................................................................................................... 65
Figures:
Figure 3.1 BB noise representation of the VCO........................................................................................... 47
Figure 3.2 Free running VCO power spectrum density ............................................................................... 49
Figure 3.3 PSD of a VCO locked by a PLL .................................................................................................. 49
Figure 3.4 Peaking X Optimum Closed Loop bandwidth............................................................................ 50
Figure 3.5 Combined Spectrum: PLL + VCO noise contributions ............................................................. 52
Figure 3.6 Rootlocus for w
3dB
location.......................................................................................................... 58
Figure 3.7 Rootlocus for w
as
location............................................................................................................ 60
Figure 3.8 Optimizing Total Phase Deviation .............................................................................................. 63
Figure 3.9 Maximum SSB noise requirement .............................................................................................. 64
Tables:
Table 31 Comparing the denominators of B(s) and B
RL
(s) ....................................................................... 54
Table 32 Rootlocus approach for w
cl
: parameters of B
RL
(s) ..................................................................... 58
Table 33 Gain Stability Boundary.............................................................................................................. 65
Table 34 Maximum Normalized Gain Variation...................................................................................... 67
3 Application Related Constraints
So far we discussed the PLL system quite separate from its application. In this chapter we study
parameters concerning the spectral purity of a VCO locked by a PLL. The parameters concern
the adequacy of the closed loop bandwidth to the noise performance of the VCO, and the
suppression of deterministic interference at f
cp
.
The filter calculation method is extended to discuss the maximum phase deviation in the
synthesized carrier, and an example of a satellite application is developed.
44 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
This chapter starts to analyze the phase noise contents of the carrier output of the PLL
synthesizer. At this point, it is a system level analysis, that considers two single noise
contributions: one for the VCO and another for the ensemble of the PLL blocks.
The sources of noise, that can be either deterministic or random, are progressively presented in
chapters 4 and 6. Later in chapter 7, these noise specifications are translated to a circuit level
description.
In order to minimize the phase noise in the spectrum of the synthesized carrier, we should be
able to choose the closed loop bandwidth with respect to the noise performances of the PLL and
the VCO. The calculation algorithm for the loop filter is then extended to take into account the
specification of a closed loop bandwidth.
The total phase deviation is introduced as a figure of merit for the noise contents in the carrier
spectrum. A numerical example for a satellite frontend exemplifies the calculation method. In
this example, we calculate a loop filter that guarantees a total phase deviation lower than 2° for
the entire range of normalized gain variation (2.r
21
).
3.1 Reference Breakthrough
Reference breakthrough, or spurious rays
i
, is a FM interference found in the VCO output at
frequency offsets of tf
cp
. The value of H(jw)
w = 2π.fcp
represents the rejection by the loop filter
of the fundamental component of the input current pulses. The f
cp
component of the loop filter
output generates the FM modulation of the VCO. The spurious requirement should be met by
providing the necessary attenuation of the f
cp
component.
A first cause of the reference breakthrough is leakage currents. The leakage currents cause
variations in the value of V
tune
. These variations are compensated by the feedback action of the
PLL, which provides every T
cp
the average lost charge. Practical examples of leakage currents
are:
the reverse current of the varicap (from the oscillator resonant circuit);
in the case of active loop filters, the amplifier input current;
an unwanted current of the charge pump in the off state;
a discharge current in the loop filter impedance, proportional to the residual transient current.
This effect is relevant for large bandwidth (bw) filters.
ii
A second cause is the transient mismatch of the sinking and sourcing pulses of the charge pump.
When in lock both sources are switched on during the reset interval. This is done
in order to avoid deadzone problems (see chapter 1). The sinking and sourcing pulses have
different rise and fall times so the combined current output is not null, and it presents
components at f
cp
and its harmonics.
i
Sometimes the name spurious rays is also used for other deterministic interference found in the VCO output. These
interferences are originated by the operation of different integrated blocks, and they contaminated V
tune
by parasitic
coupling.
ii
For a charge pump output and resonant circuit input with high impedance, the loop filter discharge is proportional
to the time constant T
p2
. In large bw filters this discharge causes significant changes in V
tune
during a T
cp
interval.
The time response of the filter is further discussed in chapter 5.
Chapter 3 / Application Related Constraints 45
Once we evaluate the total leakage current and mismatch we can calculate the corresponding
spurious level. The spurious level is proportional to the current that compensates these effects.
For the calculation we do two approximations. First we assume that the frequency content of the
compensation current is concentrated at f
cp
. Second we use the narrow band FM approximation
as the phase deviations are small.
Let us suppose a single tone modulating signal m(t), and an FM modulated carrier s(t):
[ ]
]
]
]
]
⋅ ⋅ ⋅
+ ⋅ ⋅ · ⋅ + ⋅ ⋅ ·
⋅ ⋅ ·
∫
cp
cp m
c c c c
cp m
f
t w A Kvco
t w A dt t m Kvco t w A t s
t w A t m
) sin(
cos ) ( 2 cos ) (
) cos( ) (
π
We define the peak phase deviation β:
cp
m
f
A Kvco ⋅
· β
;
and apply the FM narrow band approximation for β << 1 rad , which gives:
( ) ( ) ( ) ( ) [ ]
¹
'
¹
¹
'
¹
+ − − ⋅ + ⋅ ⋅ · t w w t w w t w A t s
cp c cp c c c
cos cos
2
cos
β
(3.1)
The leakage current component at f
cp
represents a voltage amplitude in the VCO input of:
cp
w w
filter leakage m
jw Z I A
·
⋅ · ) (
The resulting SSB spurious rays measured with respect to the carrier amplitude becomes:
]
]
]
⋅ ·
]
]
]
⋅ ·
2
log 20
amplitude carrier
component f modulated FM SSB
log 20
cp β
As
or
]
]
]
]
⋅
⋅ ⋅
⋅ ·
cp
vco cp filter leakage
f
K w Z I
As
2
) (
log 20
(3.2)
Equation (3.2) is a 1
st
order evaluation of the sidebands at the reference frequency. It is an
overestimation because we assumed all the power of the compensation current concentrated at f
cp
. In practice, the accuracy of the calculation of the spurious rays is limited by the evaluation of
the I
leakage
value.
The leakage currents that depend only on the V
tune
value are easier to evaluate, (in locked mode
V
tune
is practically constant). It is the case of the varicap reverse current (component
specification), the amplifier input current, and the charge pump off current.
The residual transient current depends on the circuit design, and it is easier and more accurate to
use a mixed circuit and behavioural simulation. For instance the mismatch between sinking and
sourcing may be evaluated with a PLL behavioural model including a circuit level description of
46 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
the charge pump.
iii
The resulting spurious rays may be calculated with the value of I
leakage
and
equation (3.2), or directly applying an FFT (fast Fourier transform) at the simulated V
tune
signal.
The PLL behavioural model for time domain simulations is discussed in chapter 7. In this model
we may add other causes of spurious rays, such as supply contamination and substrate coupling.
In chapter 4 we discuss the role of the loop amplifier in the transmission of supply perturbations.
The narrow band treatment used above is valid for any phase deviation that respects the
maximum peak deviation boundary, ∆ϕ
max
<< 1rad. For perturbations exceeding this modulation
index, or when a better accuracy is required, a more complete description should be used,
including other harmonic components.
For the moment we use the narrow band approach to discuss rather small phase disturbances,
such as random noise sources. We start with a global approach that considers the optimization of
the VCO spectrum for given VCO and PLL noise performances. Later in chapter 6, the
mechanisms of phase noise generation are described, and in chapter 7 the simulation tools that
relate noise and design are discussed.
The following section introduces the units used to characterize the oscillator phase noise, and we
proceed with the choice of the PLL bandwidth optimizing the phase deviation content.
3.2 VCO Noise Representation and Phase Noise Units
The spectrum of a VCO locked by a PLL is composed of two zones. One is called inloop and
the other outofloop. These names refer to the zones of the VCO output which are dominated by
the PLL input noise or by the VCO intrinsic (freerunning) noise.
Roughly the flat part of B(jw) corresponds to the PLL determined, inloop zone. The
–60dB/dec region of B(jw) , where the intrinsic VCO noise (with –20dB/dec) takes over, is the
outofloop zone.
In reality all input signals, noise or deterministic, have finite power and have a band limited
power spectrum density (PSD). However, in a first approach let us consider two white noise
sources representing the VCO and PLL noise contributions. The total noise contribution from
the different PLL blocks is concentrated at the phase detector input, and we name it N
PLL
.
In the baseband (BB) phase representation adopted in chapter 2, the VCO is represented by an
integrator with sensitivity Kvco. The BB representation makes a frequency conversion of the
BPF behaviour of the VCO in an LPF behaviour. In this context the VCO spectrum may be
modeled by a white noise voltage source at the integrator input.
iii
Another method of direct evaluation is rather lengthy, since we need first to find the correct phase difference
between the phase detector inputs that corresponds to an average constant charge, at V
tune
. After that, the current
difference, T
cp
periodic signal, is compared to a square or triangular pulse, and the power fraction at f
cp
is calculated.
Chapter 3 / Application Related Constraints 47
Figure 3.1 BB noise representation of the VCO
]
]
]
⋅
,
`
.

⋅ · ⋅
,
`
.

⋅ ·
Hz
Vrms
Kvco
f
f L
Kvco
f
bw
v offset
f
dB
L
offset
offset
offset
nvco
2
10
2 2
2
) (
10 2 ) ( 2 (3.3)
The part of the VCO spectrum with a –20dB/dec slope is correctly represented by a white
voltage noise source. Near the carrier, a free running oscillator presents a phase noise with higher
rolloff, due to the presence of 1/f (flicker) noise sources. In figure 3.1 this is indicated by the
corner frequency f
recover
, which points to the intersection of the white and flicker noise
contributions. So a more complete description, which would be valid for offset frequencies
below f
recover
, needs to include poles and zeros in the v
nvco
expression, to represent the different
slopes in the output spectrum.
In the case of a large bandwidth PLL, the voltage noise source, v
nvco
, does not need to be
frequency shaped. The part of the spectrum with the 30dB/dec rolloff is hidden by the PLL
noise.
In equation (3.3) the factor 2 relates this base band representation to a singleside band (SSB)
measurement, L(f). L(f) is SSB phase noise defined by:
curve under the area total
f at bw Hz 1 in area
power signal total
n fluctuatio phase to due power SSB
) (
offset
· ·
offset
f L
or
]
]
]
· ≈
+
·
∫
∞
Hz CNR P
f P
df f P P
f P
f L
carrier
offset noise
noise carrier
offset noise
offset
1 1
) (
) (
) (
) (
0
(3.4)
when expressed in dB it equals
[ ]
]
]
]
·
Hz
dBc
f L f L
dB
) ( log 10 ) ( ; dBc ⇒ dB with respect to carrier power.
ϕ
osc
VCO output spectrum
v
nvco
2
[Vrms
2
/Hz]
s
K
o
~ frecover
VCO
PSD
[W/Hz]
f
osc
log (foffset)
20dB/dec
30dB/dec
48 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
At this point we take a filtered portion of v
nvco
, and analyze it as a deterministic signal that
modulates the VCO. Using equation (3.1), and an ideal filter with a bandwidth of 1Hz around f
m
, we obtain:
( ) [ ] V t w v t m
m m nvco
ϕ + ⋅ ⋅ · cos 2 ) ( ;
with a peak phase deviation:
m
nvco vco
f
v K ⋅ ⋅
·
2
β ;
and an oscillator phase: ( ) [ ] rad t w t w t
m m c osc
ϕ β ϕ + ⋅ + · sin ) (
The baseband representation of the oscillator phase is given by:
∫
⋅ ⋅ · ⋅ − dt t m K t w
vco c osc
) ( 2π ϕ
which corresponds directly to the block diagram in figure 3.1. We may represent the phase
deviation caused by m(t) as two sidebands at offset frequencies of tf
m
, with an amplitude value
equal to A
c
.β /2 , or:
,
`
.

⋅
⋅
⋅ ·
,
`
.

⋅ · ·
⋅
,
`
.
 ⋅
·
m
nvco vco
m dB
c
c
m
f
v K
f L
A
A
f L
2
log 20
2
log 20 ) (
4
2
2
1
2
) (
2
2
2
β β
β
K
S
ϕ
(f) is the double side band (DSB) phase noise, or the mean square phase fluctuations power. It
may be seen as the BB equivalent of L(f) :
[ ] dB f L
rad
S
f S
Hz
rad
f L f S
dB dB offset
3 ) (
1
log 10 ) ( ; ) ( 2 ) (
2
2
+ ·
,
`
.

⋅ · ⋅ ·
ϕ
ϕ ϕ
(3.5)
Expression (3.5) holds when the sideband amplitudes are evaluated by the narrow band
approach. Otherwise a significant amount of the BB power is scattered in higher harmonics of f
m
around the carrier.
For decreasing values of f
m
, the phase deviation increases and the narrow band approximation is
no longer valid. This condition indicates the minimum frequency offset for which the VCO can
be represented by a linear phase model. Once more, this limitation is hidden by the PLL inloop
region, since the PLL noise contribution appears as a phase and not as a frequency modulating
signal of ϕ
osc
.
iv
Figure 3.2 illustrates the phase noise units in the side band and base band representations of the
free running VCO spectrum.
iv
A more detailed discussion of the spectrum differences between PM and FM appears in chapter 6 .
Chapter 3 / Application Related Constraints 49
(
v
)
Figure 3.2 Free running VCO power spectrum density
The PLL noise contribution, N
PLL
, is a phase jitter in rad/sqrt(Hz). Figure (3.3) shows BB and
DSB representations of the spectrum of a VCO locked by a PLL. The noise contributions from
N
PLL
and v
nvco
are indicated separately. The level of the sidebands corresponds to a unitary
normalized carrier level, or to the phase deviation values.
The closed loop transfer function, B(s), analyzed in chapter 2, determines the transfer of N
PLL
to
the output spectrum. In a similar manner we may define B
vco
(s) as the closed loop transfer
function of ϕ
osc
/ v
nvco
. Since the feedback path is the same for B(s) and B
vco
(s), they have equal
denominators.
( ) ( )
( ) ( ) ( )
1 3 2 1
2
3 2 1
1 1 1
1 1
) (
) (
) (
z p p
p p o
vco
sT sT sT C s
sT sT C s K
s F K
s B
s B
+ ⋅ + + ⋅ + ⋅ ⋅
+ ⋅ + ⋅ ⋅ ⋅
·
⋅
·
α
ϕ
(3.6)
Figure 3.3 PSD of a VCO locked by a PLL
v
The DSB graphs abscissas need to be split in two regions if we want to keep the logarithm scale with respect to
f
offset
.
4
2
β
1
S
ϕ
(f)
[rad
2
/Hz]
BB representation
2 . L(f
off1
) = S
ϕ
(f
off1
)
foff1
f
offset
log(ffc)
L(f
offset
)
foffset
8
2
β ⋅
c
A
2
2
c
A
P
osc
(f)
[W/Hz]
f
osc
f
DSB representation
log(ffc)
N
pll
+3dB
20log(N)
S
ϕ
(f)
[rad
2
/Hz]
BB representation
log(f)
freerunning VCO_Sφ(f)
from Vnvco
from Npll
1
(Npll)
2
. B(f)
2
60dB/dec
20dB/dec
log(ffc)
log(ffc)
P
osc
(f)
[W/Hz]
f
osc
DSB representation
(vnvco)
2
/2.Bvco(f)
2
50 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
B
vco
(s) has an overall band pass filtering behaviour. This can be represented by an approximate
transfer function B
vco_BPF
. It is a simplified function resembling B
3LPF
(s) (equation (2.8) ), the
simplified LPF description of B(s).
α
ξ
⋅
,
`
.

+ ⋅ +
⋅ ⋅
·
1
2
) (
2
2
1
_
s
w w
s
C s K
s B
n n
o
BPF vco
(3.7)
Comparing B
vco_BPF
and B
3LPF
, we notice that they both have a second order polynomial in the
denominator, written in a standard ξ and w
n
form. We choose this common notation to indicate
similar roots in the two functions. In numerical examples, we verify that the w
n
in B
vco_BPF
is
slightly larger than the one in B
3LPF
.
The interest of these simplified forms appears when we are minimizing the noise content of the
output spectrum. Figure 3.3 shows an ideally smooth intersection between the two zones of the
spectrum, the inloop one and the outofloop one. Nevertheless, the dominant noise in each of
these zones originates from independent noise sources, and in practice the feedback bandwidth
and gain determine whether the intersection is smooth or bumpy.
3.3 Optimum Closed Loop Bandwidth
In order to minimize the noise of the output spectrum, we need to match the PLL closed loop
bandwidth (f
cl
) with the intersection frequency, where the noise contributions from N
pll
and v
nvco
cross each other. Mismatches result in additional peaking or excessive PLL noise, as drafted in
figure 3.4.
We use again the term peaking to refer to the spectral overshoot. This mismatch peaking adds to
the low phase margin peaking seen in chapter 2. In the measurements, an overall peaking is
observed, and it is due to both causes.
Thus, we need to know the PLL and VCO noise performances in order to choose an adequate
feedback bandwidth, and afterwards center a stable filter around this bandwidth.
Figure 3.4 Peaking X Optimum Closed Loop bandwidth
additional
peaking
Ideal closed
loop bw
fosc
from Vnvco.
from Npll
excessive
PLL noise
Ideal closed
loop bw
fosc
from Vnvco.
from Npll
Chapter 3 / Application Related Constraints 51
The ideal feedback bandwidth is indicated in the figure above. The spectrum has a minimum
jitter content when we center a loop filter around this bandwidth. Unfortunately this bandwidth
will correspond only to the central gain value, and we know that synthesizers work with a large
range of gain variation. The choice of the bandwidth should take into account the optimization of
the phase jitter over the entire range of gain.
We start with a numerical example showing the spectrum of a VCO locked by a PLL, and the
separated PLL and VCO noise contributions for a set of different gain values. The figure is
divided into four parts:
• fig. 3.5.a : shows the total output spectrum plus isolated PLL and VCO noise
contributions, for the centered gain value α
npf
. Three asymptotes are
added in dotted lines. They correspond to the VCO freerunning
behaviour, the N
pll
DC transfer value (20.log[N]), and 3dB below the DC
value.
vi
• fig 3.5.b: total output spectrum for gain values varying within a range of (2.r
21
)
around α
npf
.
• fig 3.5.c and d: detailed contributions of PLL and VCO noise for the curves in part b.
The same symbols from figure 2.9 are used to indicate w
z1
( o ), w
olnpf
( * ), w
oln
( ). y
p2
( x),
w
p3
( x ). N
PLL
, also called synthesizer noise floor, is indicated in figure 3.5.d by a dotted line.
The numerical values used for these graphs correspond to the performance of low noise satellite
PLL and VCO:
Hz dBc KHz L
GHz F
N
MHz Hz dBc N
vco
vco
pll
/ 100 ) 100 (
5 . 1
1500
1 F for / 154
cp
− ·
·
,
`
·
· − · K
Let us define f
i
as being the intersection frequency for PLL and VCO noise asymptotes, as
indicated in figure 3.5.a:
) log( 20 log 20 ) ( N N
f
f
f L
pll
i
offset
offset vco
⋅ + ·
,
`
.

⋅ +
]
]
]
− ⋅ +
−
⋅ ·
20
) ( ) log( 20
10
offset vco pll
f L N N
offset i
f f (3.8)
In order to optimize the output spectrum we want to center the closed bandwidth f
cl
around f
i
.
But so far we only specified the open loop bandwidth f
ol
, used in the loop filter calculation.
Hence, we seek now a relationship between the open and closed loop bandwidths for a gain
range around the centered value α
npf
.
vi
The asymptotes are repeated in the other subplots (3.5.b/c/d) to simplify the comparison among the curves, which
are plotted in different scales.
52 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Figure 3.5 Combined Spectrum: PLL + VCO noise contributions
3.4 PLL Closed Loop Bandwidth
The simplified transfer functions B
3LPF
and B
vco_BPF
, showed that the PLL and the VCO noise
contributions have a similar closed loop bandwidth, depending on w
n
and ξ . This bandwidth
corresponds to the LPF cutoff frequency for N
PLL
, and to the central frequency of a BPF for
v
nvco
.
Later on, we assume that both transfer functions have an identical closed loop bandwidth, which
is determined by the zero and poles of the loop filter, and by the loop gain α . Therefore, we need
to relate the open and closed loop PLL bandwidths. The closed bandwidth must approach f
i
, but
it is the open loop bandwidth that is used for the filter calculation.
Let us consider w
3dB
as the closed loop bandwidth. First we do a quantitative approach of the
ratio w
3dB
/w
ol
, with numerical evaluations. After that, two analytic methods are discussed.
a b c d e
fig. 3.5.a fig. 3.5.b
fig. 3.5.c
fig. 3.5.d
Chapter 3 / Application Related Constraints 53
Numerical evaluations of the ratio w
3dB
/w
ol
, for a centered gain variation of (2.r
21
) around
w
olnpf
, show that this ratio is contained in a limited range, when we assume that the r
21
and r
31
values belong to the ranges indicated below. The limiting ranges include the typical values
encountered in synthesizer applications. The results and conditions are:
[ ]
[ ] 28 . 0 63 . 1
6 . 1
, 16
50 , 10
3
31
21
31
21
t · ⇒
≥ ∧
∞ ∈
∈
ol
dB
w
w
r
r
r
r
In chapter 2 we saw that the open loop bandwidth w
ol
varies around w
olnpf
. Thus it is likely that
w
3dB
, which is proportional to w
ol
, and slightly larger, varies around a value close to w
oln
.
The difficulty to evaluate w
3dB
(more precisely) comes from the fact that the denominator of the
closed loop transfer function D
B
(s), has complex roots with a variable damping. This implies a
variable peaking and a variable w
3dB
/w
n
.
The rootlocus representation of B(s) may be used to derive two formal expressions for w
3dB
.
These expressions are derived in sections 3.4.1 and 3.4.2 using some algebra puzzles.
The overall result is already announced in the paragraph above.
Closed loop bandwidth varies as much as open loop bandwidth and we need some application
criteria to define how to accommodate this variation. An example of an application criterion for
digital phase modulations is presented in section 3.5 .
3.4.1 w
3dB
derivation from B
RL
(s)
This first method compares the closed loop transfer B(s), with a polynomial that arises from the
rootlocus representation. Subsequently, it deduces the minimum and maximum boundaries for
w
n
and ξ, and relates these parameters to w
3dB
. Numerical evaluations are used to validate the
method.
The polynomial B
RL
(s) is equivalent to B(s). B
RL
(s) has 4 roots agreeing with the branches of the
rootlocus presented in figure 2.6.
( )
( ) ( ) ( ) [ ]
1 3 2 1
2
1
1 1 1
1 ) (
z p p
z
sT sT sT C s
sT
N
s B
+ ⋅ + + ⋅ + ⋅
+ ⋅
·
α
α
(3.9)
( )
( ) ( ) α
ξ
α
⋅
,
`
.

+ + ⋅ + ⋅ +
+ ⋅
·
1
2
1 1
1 ) (
2
2
’
1
’
3
1
n n
z p
z RL
w
s
w
s
sT sT
sT
N
s B
By inspection we verify that B
3LPF
(eq. (2.8) ) is a simplified version of B
RL
, with the following
approximations: T
z1
’ → T
z1
and T
p3
’ → T
p3
.
N
s B
N
s B
RL
) ( ) (
·
54 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
The transfer function B
RL
states that for any given α, at least two roots are real. The two others
are either real or complex depending on the value of ξ . The assumption of two real roots agrees
with the rootlocus diagram of figure 2.6.
Furthermore the diagram shows that the position of the real roots may be specified within limited
frequency ranges. In our notation, the real roots correspond to the time constants T
z1
’ and T
p3
’.
We define γ and β, as the ratios between the time constants, with:
1 0
3
’
3
≤ ≤ · β β K K
p
p
T
T
and
1 0
1
’
1
≤ ≤ · γ γ KK
z
z
T
T
.
We expand the denominators of B(s) and B
RL
(s), and compare the coefficients of the 4
th
and 1
st
order terms of s, finding the following equalities:
term
D
B
(s)/α D
BRL
(s)/α
4
th
s
4
2
oln
2
31
21
4
oln 31
21
w w r
r
w r
r
n
n
⋅ ⋅
⋅ ⋅
·
⋅
⋅
γ β
α
α
1
st
s
1
n
w w
r
w
r
ξ
γ
2
oln
21
oln
21
+
⋅
·
Table 31 Comparing the denominators of B(s) and B
RL
(s)
from 4
th
order terms:
2
1
21 oln
,
`
.

⋅ ⋅ ⋅ ⋅ · r w w
n
n
γ β
α
α
(3.10)
from 1
st
order terms:
( ) γ
ξ
− ⋅
⋅ ·
1
2
21
oln
r
w w
n
(3.11)
We may use the last two expressions to derive the minimum and maximum boundaries of w
n
.
Expression (3.10) contains variables that belong to closed and known ranges. We use it to derive
the maximum limit of w
n
.
[ ]
[ ] [ ]
{ ¦
¹
¹
¹
'
¹
→
→
→
↔
∈ ∧ ∈
·
]
]
]
]
⋅ ⋅
⋅
∈
1
1 max with
1 , 0 1 , 0
, 2 ,
2
max
max min 21
21
γ
β
α α
γ β
α α α
α
α
n
npf
npf
w
r
r
Chapter 3 / Application Related Constraints 55
so:
{ ¦ ( )
4
1
21
2
1
oln
2
1
21 oln
1
1
max
lim max r w r w w
n n
n
,
`
.

⋅ ·
,
`
.

⋅ ⋅ ⋅ ⋅ <
→
→
→
α
α
γ β
α
α
γ
β
α α
but since
21 max
2 r
n npf n
⋅ ⋅ < ⇒ ≥ α α α α
the maximum of w
n
becomes
vii
: { ¦ ( ) ( ) ( ) 19 , 1 2 max
2
4
1
2
1
21 oln
⋅ · ⋅ ⋅ <
p n
w r w w
(3.12)
In order to find the minimum of w
n
with expression (3.11) we need to find the minimum
occurring value of ξ.
viii
After the recentering procedure outlined in chapter 2, we observed that a gain variation of 2.r
21
can be covered with a minimum phase margin of 30°, for r
31
≥ 1.6 . r
21
.
So we may look for a relationship between ξ and the phase margin parameters to specify the
boundary of the variation of ξ.
Observing B
RL
(s) and the rootlocus, we may suppose that the phase margin is mostly influenced
by the pair of complex roots which are represented by the 2
nd
order polynomial in ξ and w
n
.
Therefore we may rely on the analysis of the 2
nd
order LPF to derive the relationship between the
damping factor ξ, and the open loop phase margin PhM. It holds that
,
`
.

+ + −
·
1 4 2
2
4 2
ξ ξ
ξ
arctg PhM
(3.13)
Using equation (3.13) we evaluate the minimum value of ξ corresponding to a 30° PhM.
( ) ° · · ⇒ ° · 6 . 15 sin 269 . 0 30 ξ PhM (3.14)
Finally the minimum boundary for w
n
is calculated substituting (3.14) in equation (3.11):
[ ]
[ ]
{ ¦
( )
1
21
oln
21
oln
269 , 0
0
54 . 0 54 . 0
1
2
lim min
1 , 0
1 , 269 . 0
z n
w
r
w
r
w w ⋅ · ⋅ ·
− ⋅
⋅ >
,
`
∈
∈
→
→
γ
ξ
γ
ξ
ξ
γ
(3.15)
The next step concerns the relationships between ξ, w
n
and w
3dB
. We continue to work with the
hypothesis that the two complex roots are largely determining B(jw) around w
n
. Hence, we may
use the following expression deduced from the standard 2
nd
LPF:
vii
A more rigorous treatment should take into account the ratio α
n
/α
npf
, related to the recentering procedure, seen in
chapter 2. Later in this section a numerical example illustrates the difference.
viii
The maximum ξ value is 1, corresponding to α values with 4 real roots.
56 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
( ) [ ]
2
1
2 3
2 2 1 + − + − · ξ ξ ξ
n
dB
w
w
(3.16)
Combining (3.16) with our restricted domain of ξ , we find:
[ ] [ ] 1 , 404 . 1 1 , 269 . 0
3
∈ ⇒ ∈
n
dB
w
w
ξ
(3.17)
The extreme values of w
n
, occurring for α
max
and α
min
, both correspond to cases where the PhM
equals 30°, or ξ equals 0.269 , or:
404 . 1
3
·
n
dB
w
w
The combination of the minimum and maximum boundaries of w
n
and this ratio gives the desired
range of w
3dB
:
[ ]
2 3 1 2 1 max min
67 . 1 75 , 0 2 . 1 54 , 0 ,
p dB z p n z
w w w w w w ⋅ < < ⋅ ⋅ < < ⋅ ∈ K K α α α
The geometrical mean of the range of w
3dB
equals: ( )
oln 3
w 1.12 mean geom. ⋅ ·
dB
w
The maximum value of w
n
was overestimated in equation (3.12) because we neglected the ratio
α
n
/ α
npf
ix
. A numerical application correcting this maximum boundary for given values of r
21
and r
31
is presented below:
for:
[ ]
¹
¹
¹
¹
¹
¹
¹
'
¹
⋅ < < ⋅
↓
⋅ < < ⋅
⇒
¹
¹
¹
¹
¹
¹
¹
¹
¹
'
¹
⋅ · ∈
·
,
`
.

⇒
·
·
2 3 1
2 1
21
min
max
max min
2
1
npf 31
21
36 . 1 75 . 0
97 . 0 54 . 0
2 with ,
23 . 1
50
25
p dB z
p n z
n
w w w
w w w
r
r
r
α
α
α α α
α
α
Here, the geometrical mean of the range of w
3dB
is: ( )
oln 3
w 1.01 mean geom. ⋅ ·
dB
w
Thus the range of w
3dB
centers approximately around w
ol
. With this result we combine the open
and closed loop specifications for the spectrum optimization.
Another possibility to relate the close loop transfer with the values of ξ is found in phase Bode
plots. This relationship was presented numerically in figure 2.9, by dPhB, the phase variation for
a frequency delta of one octave around w
n
.
[ ] [ ] [ ]
2
)) ( (
2
2 )) ( ( )) ( ( ) (
n n
n octave
w
jw B ph
dw
d w
w jw B ph
dw
d
w jw B phase
dw
d
jw dPhB ⋅ ·
,
`
.

− ⋅ · ∆ ⋅ ·
(3.18)
ix
In order to introduce α
n
/ α
npf
factor, we need to know the ratio r
31
/r
21
. Expression (3.12) is a rougher boundary
estimation not depending on r
31
value.
Chapter 3 / Application Related Constraints 57
For our faithful 2
nd
order LPF, dPhB becomes:
[ ] [ ]
{ ¦ octave / 149 ) ( max 269 . 0 for
40
rad
2
1
2
1
) (
min
° − · ⇒ · ·
°
−
·
⋅
−
· ⋅
⋅
−
·
jw dPhB
w
w
jw dPhB
n
n
ξ ξ
ξ
ξ
ξ
In this case, the analogy to the 2
nd
order LPF is accurate for 3
rd
order loops, but not for 4
th
order
loops, where the postfilter has a significant influence in the phase variation around w
n
.
Hence we stick to the rootlocus criterion to center the closed loop bandwidth .
Figure 3.6 illustrates the rootlocus for different values of r
21
and r
31
.
The grid indicates natural frequencies and damping arches (ϕ = arcsin ξ ). A set of gain values
within the usual (2.r
21
) interval is chosen, and the roots corresponding to these gain values are
indicated by delta signs (∆) .
The plot is magnified around the origin of the splane, so that the damping of the complex roots
can be easily visualized. We verify that all the roots signaled by a ∆, are effectively contained in
the area corresponding to arcsin(ξ)>15° , or ξ >0.26 .
Grid:
[ ]
[ ]
¹
¹
¹
'
¹
° ° ° ° ° ·
∗ ·
15 , 30 , 45 , 60 , 75 arcsin
8 , 4 , 2 , 1
olnpf
ξ
w w
n
Gain values signaled by a delta (∆): ( ) ( )
]
]
]
]
⋅ ⋅ ⋅ ·
− 5 . 0
21
5 . 0
21
2 , , 1 , 2 r r
npf
n
npf
α
α
α α
.
In figure 3.6.b we observe that a small value of r
21
limits the maximum value of ξ . This result
agrees with expression (2.10), concerning the maximum phase margin.
The 4
th
branch follows the real axis from –w
p3
towards ∞ .
The values of β, γ, ξ, and w
n
, from the expression of B
RL
(s), are evaluated for the left rootlocus
diagram with: r
21
=25 and r
31
=50 .
In table 32 the columns coloured gray correspond to the α values indicated by a ∆ signal in
figure 3.15.a .
58 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Figure 3.6 Rootlocus for w
3dB
location
α
( )
2
1
21
npf
2 r ⋅
α
( )
4
1
21
npf
2 r ⋅
α
α
npf
α
n
( )
4
1
21 npf
2 r ⋅ ⋅ α ( )
4
1
21 npf
2 r ⋅ ⋅ α
’
3
3
3
’
3
p
p
p
p
w
w
T
T
· · β
0.991 0.978 0.948 0.927 0.890 0.802
’
1
1
1
’
1
z
z
z
z
w
w
T
T
· · γ
0.0415 0.0442 0.0547 0.756 0.879 0.958
olnpf
w
w
n
x
0.196 0.328 0.585 2.65 3.71 5.99
min (ξ) 0.325 0.542 0.958 1.00 0.676 0.275
arcsin [min (ξ) ] 19.0° 32.8° 73.3° 90.0° 42.5° 15.9°
Table 32 Rootlocus approach for w
cl
: parameters of B
RL
(s)
x
w
n
for the pair of complex roots. For α values where all roots are real, we take an average of the two roots which
are the closest to the complex branches.
Figure 3.6.a Figure 3.6.b
Chapter 3 / Application Related Constraints 59
3.4.2 w
3dB
derivation from w
as
This second method gives some further insight into the rootlocus representation. However it is
limited to a single gain value.
The asymptotes of the rootlocus for increasing gain values are given by radial lines, which have
a known phase and origin, φ
l
and w
as
.
0
1
1
1 ) (
) (
1 0
) (
) (
1 ) ( 1
lim
lim
·
,
`
.

+
+ ·
,
`
.

+ ⋅
⋅ + ÷ ÷ ÷ → ÷ ·
⋅
⋅ + · +
− −
∞ →
∞ → m n
as
m n
as
F
F
w
and
F
F
w
s
w
s
s N
s N
s D s
s N
s H
α
α α
α
(3.19) (3.20)
where n : order of the denominator of H(s);
m : order of the numerator of H(s).
xi
Expressing the asymptotes in the polar form (
l
j
o
e R s
Φ
⋅ · ) and solving the phase condition for
(3.20), gives:
( )
( ) [ ] 1 , 0
;
360 180
360 180
1
− − ∈ ∧ ∈
−
° ⋅ + °
· Φ
Φ ⋅ − · ° ⋅ + ° ·
,
`
.

−
∞ →
·
−
m n l Z l
m n
l
m n l
w s
phase
l
l
w
s s
m n
as
o
For n > m+1 , we can apply the following expression, that is derived from(3.19) and (3.20),
comparing the coefficients of order s
n1
. It follows that:
LHP in the zeros for z with _ H(s) of s z :
(LHP) plane  S the of side left in the
poles for p with _ H(s) of poles :
i
i
i i
i i
i i
as
z ero z
p p
m n
z p
w
·
·
∴
−
−
·
∑ ∑
In our case (nm) = 3 , φ
l
= 60° ; 180° ; 300° , and
[ ]
,
`
.

+
⋅ ÷ ÷ ÷ → ÷ − + ⋅ ·
,
`
.

− + ⋅
·
>>
>>
21
31 21
oln
1 r and
1 r for 31 21
21
oln
21 21
31
21 oln
r 3
1
r 3 3
1
31
21
r r
w r r
w
r r
r
r w
w
as
xi
There are (nm) centrifugal asymptotes because m root branches tend to the m zeros of the open loop transfer
function. In fact for an increasing gain there are two possibilities of satisfying the closed loop characteristic equation
(3.19):
( )
−∞ →
⋅
→
s N
s D s
s N
F
F
F
) (
, 0 ) (
. The second case supposes n > m and w → ∞ .
60 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
We use w
as
to define a LPF transfer function, B
as
(s), with three real poles at w
as
.
A rough estimate of the closed loop bandwidth for α ≈ α
n
is the frequency of 3dB attenuation
for B
as
(jw), named w
3dBas
:
( ) ( )
( )
2 3
21
31
2 3
21
31
21
31 21
oln 3
2
3
2
3
3
3
4 . 0 6 , 1
r
5 . 0 2
r
for examples numerical
r 6
51 , 0
2
1
1
1
1
1
p as dB
p as dB
as as dB
as
as dB
as dB as
as
as
w w
r
w w
r
r r
w w w
w
w
N
jw B
w
s
N
s B
⋅ · ·
⋅ · ·
,
`
.

⋅
+
⋅ ≈ ⋅ ·
·
,
`
.

+
,
`
.

·
,
`
.

+
·
−
−
−
−
−
K
K
K K
The figure below shows a rootlocus in full scale, with the asymptotes for large gain and w
as
. The
roots corresponding to α
max
and α
min
are indicated with ∆ signals.
Figure 3.7 Rootlocus for w
as
location
Chapter 3 / Application Related Constraints 61
We would like to compare the results of the two methods for the estimation of w
3dB
.
In the 2
nd
method w
3dB
was estimated for a gain of α
n
, and in the 1
st
method the centered value
corresponds to α
npf
. So before the comparison we need to choose values for r
21
and r
31
and
recenter w
3dB_as
with respect to α
n
/α
npf
.
oln oln _ 3 oln 2 _ 3
31
21
8 , 1 5 , 2 5 , 2 5 , 0
50
25
npf
w w r w w w w
r
r
pf as dB p as dB
n
⋅ · ⋅ ⋅ · ⋅ · ⋅ · ⇒
·
·
α α
K
The 2
nd
method results in a larger value of w
3dB
than the 1
st
one. Using this larger value the
spectrum will present a smaller variation of the peaking value α
min
and α
max
.
xii
In practice we often choose w
3dB
in the range:
oln 3 oln
2 w w w
dB
⋅ ≤ ≤ ;
or inversely, when we have a given f
i
(intersection frequency), we choose :
i dB
f w ⋅ · π 2
3
and
3dB oln
3dB
2
w w
w
≤ ≤
In a larger scope, including the specifications of the demodulator block, the optimization of the
LO spectrum is bound to the type of data modulation. The following section discusses the total
phase deviation, which is a determinant parameter for phase modulated data.
3.5 Maximum Phase Jitter
The specification of the spectral purity of the local oscillator depends on the input signal that has
to be frequencyconverted. For some types of digital phase modulation, such as BPSK, QPSK
and GMSK, the total phase deviation is a meaningful parameter.
The total phase deviation is defined as:
( )
∫
·
max
min
f
f
df f S
ϕ ϕ
σ [rad] (3.21)
where f
min
and f
max
are related to the channel bandwidth , and/or to the symbol rate.
The characteristics of other blocks of the receiver, such as filter stages and the carrier recovery
loop are also relevant to the sensibility to phase noise. So the achievable BER performance may
not be directly derived from σ
ϕ
.
In chapter 7 we discuss a behavioural model including the carrier recovery loop of a QPSK
decoder. This model is used to evaluate the amount of phase deviation that appears in the
demodulator, and the implementation loss caused by this signal degradation.
The LO spectrum is a combination of the contributions of N
pll
and v
nvco
, transferred by B(s) and
B
vco
(s) respectively. We know that these two transfer functions have similar bandwidths, close to
w
n
in B
3LPF
(s) and B
VCOBPF
(s), and that w
n
varies with α, in a range closely proportional to the
variation of w
ol
.
xii
Figure 3.5 is traced for a w
3dB
chosen by the 1
st
method (2π.f
i
= w
3dB
= w
oln
), and we see that small α values
present a quite higher peaking than large α values.
62 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Using σ
ϕ
as a spectral quality parameter, we search for the value of w
olnpf
with respect to (2π.f
i
), which optimizes σ
ϕ
over the gain range of (2.r
21
).
The plot below shows an example of the placement of w
olnpf
with respect to f
i
and r
pf
xiii
, so as
to obtain a minimum σ
ϕ
over the total gain range.
( )
oln olnpf
4
1
olnpf
2 2 w w f r f w
i pf i
⋅ · ⋅ ⇒ ⋅ ⋅ · π π (3.22)
The output spectrum is plotted with logarithmic and linear scales. The curves are calculated for
different gain values covering the normalized (2.r
21
) range.
The linear scale is presented as a visual recall of the spectrum analyzer output, usually with a
linear frequency scale around f
vco
. It also helps to visualize the idea of a similar integral (area
under the curve), or σ
ϕ
for the extreme gain cases.
The 3
rd
curve presents the total phase deviation observed in the plots of the spectrum. A large
bandwidth is assumed for the evaluation of σ
ϕ
.
For a −∞ → →
>> <<
p3 oln
) ( and ) (
f f f f
f S cst f S
ϕ ϕ
we may enlarge the integration limits of (3.21) without changing σ
ϕ
significantly.
∫ ∫ ∫
⋅
≈ ≈
+∞ 3
40
500
1
max
min
0
p
f
z
f
df S df S df S
f
f
ϕ ϕ ϕ
(3.23)
The integration boundaries of the right most term of (3.23), are used in the calculation of σ
ϕ
.
The integer values of the abscissa correspond to the geometrically distributed values of α .
These α values are the same used in the other plots of Fig. 3.8 :
xiv
( ) ( ) ( ) ( ) [ ]
5 . 0
21
25 . 0
21
25 . 0
21
5 . 0
21
2 , 2 , 1 , 2 , 2 r r r r
npf
⋅ ⋅ ⋅ ⋅ ⋅ ·
− −
α α .
The characteristics of the PLL and the VCO are identical to the ones used in the Bode plot of
Fig. 3.5 . They are:
N
pll
= 154 dBc/Hz @ F
cp
= 1 MHz ;
N = 1500 ;
L
vco
(100KHz)=100dBc/Hz ;
r
21
= 25 ; r
31
= 50 .
xiii
Function of r
21
and r
31
, expression (2.17).
xiv
In figure 3.8 there is an approximation due to the constant divider ratio N. The factor 20.log(N) modulates the
height of the PLL noise contribution. So a changing value of N modifies σ
ϕ
. In our example, with a ratio
N
max
/N
min
=2, the change would not be significant. For other cases with a larger range of dividing ratios, we may
expect that:
• N → N
max
⇒ α → α
min
: an increase in σ
ϕ
with respect to the evaluation with a constant N;
• N → N
min
⇒ α → α
max
: a decrease in σ
ϕ
with respect to the evaluation with a constant N.
Therefore we may choose to center w
olnpf
in a frequency larger than the one indicated in equation (3.22), or in other
words closer to f
i
.
A numerical simulation tool is always indicated to verify the total phase deviation, with respect to N and α values.
We present two options of simulation tools. The graph below is calculated with a programmed Matlab routine. In
chapter 7 we discuss another simulation model easily implemented in software for analog circuitry simulation.
Chapter 3 / Application Related Constraints 63
Figure 3.8 Optimizing Total Phase Deviation
Fig. 3.8 shows that this set of noise performances of the PLL and VCO can accommodate a gain
variation (α
max
/α
min
) of factor 50, with a total phase deviation under 1.8° .
This optimum σ
ϕ
performance is an important practical result for synthesizers generating low
noise carriers.
The curves from left
to right correspond to
the gain values:
a) α
npf
. (2.r
21
)
0.5
b) α
npf
. (2.r
21
)
0.25
c) α
npf
d) α
npf
. (2.r
21
)
+0.25
e) α
npf
. (2.r
21
)
+0.5
64 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Other applications will demand different spectral purity parameters, for example a maximum
peak or a minimum L(f) (absolute single side band phase noise) within a certain frequency
offset range.
In this case, we may use a very large
feedback bandwidth ,
w
olnpf
>> (2π.f
i
) in order to have the
PLL behaviour determining most of
the spectrum around w
n
in all the
gain range.
However, in the case of a large
bandwidth we must pay attention to
keep: w
n
/ w
cp
< 0.5 ; mainly with
α=α
max
.
Figure 3.9 Maximum SSB noise requirement
The limitation of a maximum bandwidth appears when the PLL model includes the sampling of
the phase detector. This issue is treated in chapter 5.
The boundary we propose for the moment, is a rough estimation, which is similar to a Nyquist
bandwidth for a discrete system with a sampling frequency f
cp
.
In the numerical example treated above, it would not be possible to increase w
olnpf
as much as
needed for an equilibrated minimum L(f) throughout the whole range of α, as the max{w
n
} is
already near to w
cp
. In other cases with a much worse PLL phase noise performance, it would be
possible to apply this minimum L(f) criterion.
The criterion of minimal L(f) is also called maximum flat spectrum optimization.
In the scope of the rootlocus representation, we may deduce this maximum flat condition as the
maximum ξ condition. Therefore maximum flat spectra are obtained for values of α
corresponding to 4 real roots (ξ=1), and a closed bandwidth well matched with f
i
.
The formal solution of the maximum flat point is found minimizing B(jw). Reference
[Wong96] discusses this problem for 4
th
and 5
th
order PLLs, comparing the algorithms of
maximum PhM and maximum flat spectrum. But the discussion is limited to a single gain value,
and is not therefore very useful in our application, where we need to accommodate rather large
gain variations.
fosc
Locked VCO output Spectrum
min L (f) 
α
min
α
max
Chapter 3 / Application Related Constraints 65
3.6 Gain Stability Boundary
We end this chapter deriving one last practical feature that is emphasized by the rootlocus. It is
the limiting gain value that implies system instability.
In the rootlocus representation, we observe a pair of complex roots crossing the imaginary axis
for increasing gain values. Routh’s stability criterion may be used to evaluate this gain stability
boundary.
xv
B(s) is rewritten as a function of α
n,
, w
oln
, r
21
, r
31
:
( )
1 s s
1
s s
1
oln
21
2
oln
21 2
31
31 21
3
oln
3
31
4
oln
21 4
oln
21
+
,
`
.

⋅ +
,
`
.

⋅ ⋅ +
,
`
.
 +
⋅ ⋅ ⋅ +
,
`
.

⋅
⋅ ⋅
,
`
.

⋅ +
·
w
r
w
r
r
r r
w r w
r
w
r
s
N
s B
n n n
α
α
α
α
α
α
For α , α
n,
, w
oln
, r
21
, r
31
∈ R
+
all the coefficients of the denominator are positive, but we need
also to check the first column of the Routh array, depicted in the table below:
s
4
1 1
s
3
oln
21
31 21
w
r
r r
⋅
+ a
1
s
2
( )
]
]
]
]
+
⋅ − ⋅ ⋅
31 21
21
31
2
oln
1
r r
r
r w
n
α
α
b
1
s
1
( )
( )
¹
¹
¹
¹
¹
'
¹
¹
¹
¹
¹
¹
'
¹
]
]
]
⋅ − + ⋅ ⋅
+
− ⋅ ⋅ ⋅
21 31 21 31 21
2
31 21
31
3
oln
1
r r r r r
r r
r w
n
n
α
α
α
α
c
1
s
0
= 1
n
r
r
w
α
α
⋅ ⋅
21
31 4
oln
d
1
Table 33 Gain Stability Boundary
xv
The criterion observes the coefficients of the system characteristics equation (expressed as a monic polynomial,
i.e. the coefficient of the higher order term equals 1) to compose two statements:
having all coefficients positive, it is a necessary condition for all the roots to have negative real parts;
having all elements of the 1
st
column of Routh array positive, it is a necessary and sufficient condition for all
roots to have negative real parts.
66 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Terms b
1
and c
1
may become negative for an increasing
n
α
α
factor.
lim 1 1lim
lim 1
31 21
31 21
21
31 21
1
lim 1
21
31 21
1
with
1 0
0
b c
c
r r
r r
r
r r
c
b
r
r r
b
n
n
<
¹
¹
¹
¹
¹
¹
¹
'
¹
·
]
]
]
]
,
`
.

⋅
+
− ⋅
+
< ⇒ >
·
+
< ⇒ >
α
α
α
α
The difference between c
1lim
and b
1lim
is rather small when r
21
and r
31
are much larger than 1; so
we may work with b
1lim
for simplicity.
Thus for
lim 1
b
n
>
α
α
, we have two signal changes in the column vector indicating two roots in
the RHP.
Next we combine b
1lim
with the gain recentering expression (2.19), to determine the maximum
α/α
npf
ratio.
2
1
1
21 31
31
21
31 21
2
1
1
21
31 21
21
21
1
r
r
pf npf
n
n npf
r r
r
r
r r
r
r
r r
+
+
,
`
.

−
⋅
+
·
,
`
.

⋅
+
< ⋅ ·
α
α
α
α
α
α
We search to eliminate r
31
in the expression above, by using the minimum ratio r
31
/r
21
indicated
in chapter 2.
3
8 1
min 6 , 1 min
1
min
21
31
·
,
`
.

∴ ·
,
`
.

⇒
,
`
.

pf pf
r r
r
r
In this manner the maximum gain boundary is a function of a single parameter r
21
, so that:
( )
,
`
.

· ⋅ ⋅ <
+
npf
r
npf
r
α
α
α
α
max 67 . 2 6 . 2 2
1
1
21
21
A couple of numerical examples for given r
21
values are listed in the table below.
r
21
,
`
.

npf
α
α
max
10
2 . 15 2 4 . 3
21
· ⋅ ⋅ r
25
3 . 23 2 3 . 3
21
· ⋅ ⋅ r
→ ∞
∞ → ⋅ ⋅
21
2 0 . 3 r
Chapter 3 / Application Related Constraints 67
Table 34 Maximum Normalized Gain Variation
In the table, the maximum stability values, max (α/α
npf
), are compared to the normalized
maximum value α
max
= ( )
npf
r α ⋅ ⋅
21
2 .
The comparison shows that the stability boundary is achieved for α approaching 3.α
max
, which
emphasizes the importance of choosing r
21
in adequacy to the gain variation.
In this chapter we developed practical tools to evaluate the spurious rays, and to optimize the
phase jitter in the ensemble VCO+PLL.
We introduced the units to quantify the phase noise, and examined the closed loop transfer of the
inherent noise of the VCO.
The closed and open loop bandwidths of the PLL were related to adjust the filter calculation to
the requirement of a minimum phase jitter.
The PLL analysis tools from chapter 2 were largely employed, and we continued to discuss
robust approaches taking in account the whole range of gain variation.
Finally, we calculated the theoretical limits of the gain variation to give a practical numerical
boundary for people facing the constraints of a synthesizer implementation.
68 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Chapter 4 / Active Loop Filters: AC & disturbances issues 69
Contents:
4. Active Loop Filters: AC & disturbances issues 69
4.1. Nonideal Filter Impedance .................................................................................................................... 70
4.1.1. Fully 3
rd
order passive filter........................................................................................................... 71
4.1.2. Amplifier AC characteristics ......................................................................................................... 72
4.1.3. Amplifier with single dominant pole............................................................................................. 74
4.1.4. Numerical example........................................................................................................................ 76
4.1.5. Input impedance: Z
in
...................................................................................................................... 79
4.1.6. Summary of AC boundaries for filter design................................................................................. 80
4.2. Disturbances and Noise Propagation ..................................................................................................... 80
4.2.1. Random Electrical Noise............................................................................................................... 81
4.2.2. Supply Disturbances...................................................................................................................... 82
4.2.3. Amplifier Noise............................................................................................................................. 82
4.2.4. Filter Component Noises ............................................................................................................... 83
4.2.5. Transfer functions table................................................................................................................. 84
4.2.6. Simulation Example ...................................................................................................................... 85
Figures:
Figure 4.1 Active Loop Filter ........................................................................................................................ 70
Figure 4.2 Fully 3
rd
order passive filter impedance...................................................................................... 72
Figure 4.3 Active Filter AC model ................................................................................................................ 73
Figure 4.4 Loop rootlocus with active filter.................................................................................................. 75
Figure 4.5 gm Influence in Open Loop Transfers........................................................................................ 77
Figure 4.6 Amplifier Input Impedance X Filter Impedance ........................................................................ 79
Figure 4.7 Supply disturbances...................................................................................................................... 82
Figure 4.8 Amplifier noise.............................................................................................................................. 83
Figure 4.9 Filter components noise .............................................................................................................. 83
Figure 4.10 Noise simulation scheme............................................................................................................. 85
Figure 4.11 Noise simulation results .............................................................................................................. 86
Tables:
Table 41 Fully 3
rd
order passive filter: ∆PhM and ∆GM.......................................................................... 72
Table 42 Active Filter example: Phase Margin degradation..................................................................... 78
Table 43 Disturbances transfer functions.................................................................................................. 84
Table 44 Noise sources voltage spectrum density ...................................................................................... 87
4 Active Loop Filters: AC & disturbances issues
Quite often PLL synthesizers drive VCOs with a tuning range higher than the PLL supply
voltage. In these cases the filter impedance is associated with a transconductance amplifier
supporting the desired DC range at its output.
In order to preserve the AC and noise specifications of the locked VCO, we must include the
amplifier AC characteristics in the loop transfer functions, and examine the propagation of its
intrinsic noise sources.
70 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
This chapter introduces the first nonideal aspects of the AC model of the PLL, which was
presented in chapter 2.
Here, we look at the changes in the filtering function, that are caused by a nonideal loop
amplifier. Later in chapter 5, we study the limitations of the linear model with respect to the
maximum feedback bandwidth and the maximum comparison frequency for the PLL.
In this chapter we also continue the analysis of the noise in the VCO spectrum, starting to
descend from the system approach to the level of circuit implementation.
The study of the active filter gives us an appropriate example to look at noise sources in the level
of circuit description. The example of deterministic sources (that are transmitted by parasitic
coupling) and the example of electrical random noise sources (shot, thermal and flicker) are
discussed in both theoretical and practical approaches.
4.1 Nonideal Filter Impedance
Let us consider the active inverting loop filter represented in figure 4.1. The passive elements are
still responsible for the leadlag and postfilter of Z
F
(s) , as represented in figure 2.4.
Figure 4.1 Active Loop Filter
The filter configuration above is quite classical in tuner applications. The amplifier is a
transconductor with a high input impedance and a current output transformed in voltage by the
pullup resistor, R
pu
.
Ideally for a very high input impedance, transconductance gain (gm), and pullup resistor, the
amplifier characteristics are invisible in the AC transfer: V
tune
/I
cp
, and the input node connected
to the charge pump output is held around the DC value V
ref
.
In a less ideal context, mainly for large bandwidth filters, the AC characteristics of the amplifier
are relevant, and need to be checked and included in the loop transfer.
Z
3
I
cp
V
ref
V
dc_high
V
tune
C
2
C
1
R
1
Z
s
R
pu
R
3
C
3
Chapter 4 / Active Loop Filters: AC & disturbances issues 71
In addition, the input node voltage may vary significantly during acquisition intervals. So the
amplifier input should be sensitive within the whole DC functioning range of the charge pump
output, to assure loop stability.
Sometimes active filters are also used in loops with an equal tuning range and supply voltage.
i
In these cases the amplifier is implemented to reduce DC constraints on the charge pump output
(that can work in a reduced range, being optimized for matching and noise properties), while
keeping the tuning range close to the maximum: from ground to supply voltage. Nevertheless,
choosing an active or passive filter configuration is a compromise between the reduced DC
constraints and the AC issues related to the amplifier, such as modifications in the filter transfer
and transmission or addition of disturbances and noise sources.
In this chapter we study these AC issues, starting with nonideal effects in the filter impedance.
In order to keep a comparative insight between the passive and active configurations, we start
with the nonideal fully 3
rd
order transfer for the passive configuration, which was simplified in
chapter 2 by the approximation: f
p3
>> f
p2
.
Next we discuss the AC model of the amplifier, including first the transconductance and R
pu
effects, with a first order (single dominant pole for gm) analytical and numerical example.
Secondly the influence of the input impedance is analyzed and the suggested ensemble of
boundaries is summarized.
4.1.1 Fully 3
rd
order passive filter
Before we start introducing the parameters that are specific to the active filter, we reexamine the
transfer of the equivalent passive filter without the approximation: Z
3
>>Z
s
.
This fully 3
rd
order filter transfer has a denominator which is not completely factorable as
equation (2.5). So we may identify the necessary assumptions to approach the simplified
factorable denominator.
( )
( ) ( ) ( )
) (
1 1 1
1
) (
3 1
3 2 1
1 3 3 2 1
1
3
s Z
R R
C C C
T s C s T s T s C s
T s
I
V
s Z
F
z p p
z
cp
tune
F
≈ ÷ ÷ ÷ ÷ ÷ ÷ → ÷
<<
>> >>
⋅ + ⋅ ⋅ + ⋅ + ⋅ ⋅ + ⋅ ⋅
⋅ +
· ·
(4.1)
For r
21
>>1 and r
31
≥ (1,6).r
21
, the two conditional statements above may be resumed by:
R
3
>> R
1
.
A numerical example shows us the dependency of the nonzero poles position with respect to the
R
3
/R
1
ratio. Let us call w
p2n
and w
p3n
, the nonzero poles of the equation (4.1), and k the ratio
R
3
/R
1
. Generally, a decreasing k causes w
p2n
to approach w
z1
and w
p3n
to move away from w
p2
.
i
In the sketch above V
dchigh
would then be equal to Vcc for the PLL circuit biasing.
72 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Figure 4.2 Fully 3
rd
order passive filter impedance
Looking at the open loop Bode plot, the magnitude plot is rather insensitive to k changes, but the
phase curve will change causing a decrease in PhM, and an increase in the frequency
corresponding to the gain margin, w
CG
. A larger w
CG
with an unchanged monotonously
decreasing H(jw) implies an increase in the gain margin, Gm. Some numerical values for r=25
and r31=50 are listed in the table below.
k = R
3
/R
1 ∆PhM (°) ∆Gm (dB) w
p2n
/ w
p2
w
p3n
/ w
p3
¼ 11,8 +7,36 0,32 3,34
1 3,46 +2,50 0,60 1,70
4 0,903 +0,70 0,83 1,21
Table 41 Fully 3
rd
order passive filter: ∆PhM and ∆GM
Bode plots of B(jw) show that only for high gain values, with α approaching α
max
, a slight
increase in peaking and decrease of w
peak
is noticed, as the ratio k decreases.
As a practical conclusion we can keep in mind that passive filters should work with
R
3
≥ R
1
, as a condition to correctly estimate the full 3
rd
order transfer by its factored version.
These considerations set us a 1
st
AC boundary to be taken into account during the calculation of
the loop filter components, discussed in chapter 2.
In the next sections the amplifier AC characteristics are included, setting additional boundaries
with respect to R
pu
, gm and the amplifier poles and input impedance (Z
in
).
4.1.2 Amplifier AC characteristics
The AC equivalent circuit for the active filter, with the amplifier represented by its input
impedance Z
in
, transconductance gm and output parallel impedance Z
o
, is pictured in figure 4.3.
We consider Z
o
>> R
pu
, which is usually true for our application context, but if needed we may
easily replace R
pu
by the parallel impedance Z
opu
in the expressions derived below.
ii
ii
The amplifier output as a current source may be seen as the Norton equivalent of a voltage gain amplifier, with
gain gv=gm.R
pu
, and a series output impedance R
pu
. The representation as a voltage controlled amplifier may be
useful in certain simulation software containing amplifier models with Thevenin equivalent outputs.
log( f ) [Hz]
f
p3
f
p2
f
z1
∠H(jw)
[ ° ]
90°
180°
270°
with Z
F3
(s)
with Z
F
(s)
Chapter 4 / Active Loop Filters: AC & disturbances issues 73
Figure 4.3 Active Filter AC model
For the sake of clarity, we present first the transfer of an active filter with an ideal infinite Z
in
,
and look at the influence of gm and R
pu
. The active filter transfer, Z
Fa
(s), becomes:
( )
( ) ( )
]
]
]
]
+
,
`
.

+ ⋅ ⋅ ⋅ +
]
]
]
]
+
⋅
,
`
.

−
·
⋅ +
⋅
⋅ +
⋅ −
⋅ ·
3
3
3
3 3
3
1
1
1
1
) (
1
1
1
) ( 1
) ( 1
) ( ) (
R
R
R
gm
C s
R gm
s Z
gm
T s s Z gm
s Z gm
s Z s Z
pu pu
s
p u
s
u Fa
(4.2)
( )
( )
( )
3
’
3
’
3
3 3
’
3
3
3 3 3
’
3
3
3u
and
1
1
;
1
1
Z with
p p
p
pu p
p
p
p
p pu
w w
w
R R C T
w
R C T
T s
T s R
<
· + ⋅ ·
· ⋅ ·
⋅ +
⋅ + ⋅
·
General conditions may be imposed over gm to approach Z
Fa
(s) to Z
F
(s).
) (
) ( Z
1
gm
with
1
) (
1
1
1
with
) (
s
3
3
s Z
s
T s
s Z
gm
R
R
gm
R gm
s Z
F
p
s
pu
pu
Fa
− ≈ ÷ ÷ ÷ ÷ ÷ ÷ → ÷
>>
⋅ +
,
`
.

−
≈ ÷ ÷ ÷ ÷ ÷ ÷ → ÷
>> ⋅
>> ⋅
The first conditions just affect the postfilter pole with respect to the amplifier voltage gain,
gv=R
pu
.gm . The second condition is more hermetic since the poles of gm and the zeros of Z
s
will be mixed in the numerator polynomial.
We will now include frequency dependent aspects in the amplifier transconductance.
Simple and usual loop amplifiers are composed of a high impedance voltage follower and DC
level shifter, plus a transconductor amplifying stage. We suppose that the overall
transconductance has an LPF behaviour, with a low frequency value Gmo, and poles represented
by the polynomial D
G
(s) . The dominant poles are either from the follower or the
transconductance stage.
R
3
Z
s
I
cp
gm.v
in
V
tune
Z
in
C
3
Z
3u
R
pu
v
in
v
M
Z
o
74 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
The leadlag filter part is also split in numerator and denominator polynoms, N
s
(s) and D
s
(s).
Finally, Z
Fa
(s) can be rewritten using:
{ ¦
{ ¦
{ ¦
; with
) (
) (
) (
;
) (
) (
) ( ;
) (
s s
g G
s s
s s
s
s
s
G
m n
n s D order
n s D order
m s N order
s D
s N
s Z
s D
Gmo
gm >
·
·
·
· · L
( ) ( )
¹
¹
¹
'
¹
¹
¹
¹
'
¹
⋅ + + ⋅ + ⋅
⋅
⋅
]
]
]
⋅
− −
·
3
’
3
1 1
) (
) (
) ( ) (
) (
) (
p p
pu
G
s
s G
s
Fa
T s T s
R Gmo
s D
s D
Gmo
s D s D
s N
s Z
(4.3)
We can preview the order of the Z
Fa
(s) numerator and denominator with respect to m
s
, n
s
and n
g
, and compare to the passive filter Z
F
(s).
{ ¦
{ ¦ cst k
w
k
w Z jw s
n
m
s Z order
cst k
w
k
w Z jw s
n n
n n
s Z order
s s
m n
Fa
w
s
s
F
Fa
w
s g
s g
Fa
· · ⇒ · ∴
+
·
· · ⇒ · ∴
+ +
+
·
− +
∞ →
∞ →
’
1
’
for ) ( lim for
1
) (
for ) ( lim for
1
) (
Z
Fa
(s) order indicates that the gm poles are reducing the filter attenuation for high frequencies,
which affects for example, the suppression of the comparison frequency component.
Besides, equation (4.3) suggests that at least one zero will appear in the RHP. There will also be
additional poles in the LHP. Both the RHP zero and LHP poles will contribute to decrease
stability margins.
In order to have some qualitative understanding to better analyze the simulation results, we
develop a first order analytical case, for a gm with a single dominant pole.
4.1.3 Amplifier with single dominant pole
An example is presented below for a simple amplifier model with a single dominant pole at w
a
.
The transconductance and voltage gain become:
a a
pu
a
w
s
Gvo
w
s
R Gmo
gv
w
s
Gmo
gm
+
·
+
⋅
·
+
·
1 1
and
1
Replacing this 1
st
order gm in equation (4.3) for Z
Fa
, we verify the following changes in the
denominator:
an extrapole is added at
,
`
.

+ ⋅ ⋅ ≈
pu
a
R
R
Gvo w w
3
1 ;
the position of the postfilter pole is a bit changed.
Chapter 4 / Active Loop Filters: AC & disturbances issues 75
For w
a
and Gvo kept within reasonable bounds (w
a
≥w
p3
and Gvo≥10) the influence in the
denominator is rather small.
On the other hand, the numerator receives two extrazeros, one of which is in the RHP. In
addition, the zero from the leadlag impedance (Z
s
) is quite sensitive to the product R
1
.Gmo.
The numerator of equation (4.3) is detailed below for the single pole gm. The corresponding
rootlocus is sketched in figure 4.4 .
iii
( )
( )
{ ¦ ( ) ( )
]
]
]
,
`
.

+ ⋅ ⋅ + ⋅
⋅
− ⋅ + ·
⋅
− ·
,
`
.

+ ·
⋅ + ⋅ ⋅ ·
⋅ + ·
a
p z
s G
s Fa
a
G
p s
z s
w
s
T s
Gmo
C s
T s
Gmo
s D s D
s N s Z num
w
s
s D
T s C s s D
T s s N
1 1 1
) ( ) (
) ( ) (
1 ) (
1 ) (
1 ) (
2
1
1
2 1
1
(4.4)
Figure 4.4 Loop rootlocus with active filter
This rootlocus present an asymptotic branch running towards +∞, which is normally found in
positive feedback cases, with a characteristic equation like: 1H(s) . In our example, this branch
appears because of the RHP zero, which causes an inversion in the H(s) signal for large gain
values.
As we commented previously, most of the changes in the frequency behaviour of the active
transfer are due to the additional zeros. In the rootlocus sketch we may verify that the two zeros
at low frequencies are specially relevant to system stability.
iii
The scale of this rootlocus is not linear. Distances are compacted as they run away from the origin, in order to
visualize both: closein zeros and poles from the passive elements; and, farther ones introduced by the active device.
f
z2
High frequency
additional
zero and pole
f
’
z1
Re{s}
Root Locus Im{s}
f
z1
f
p3
f
p2
76 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
In order to better understand the changes in the Z
Fa
numerator ( with respect to N
s
), we search
simplified expressions for the zeros indicated in the rootlocus.
We can consider two frequency intervals to derive approximate values for the two lowest
magnitude zeros: w
’
z1
and w
z2
. The first (w
’
z1
) is close to the leadlag zero from N
s
, but its
position depends on the Gmo value. The second (w
z2
) is the zero added in the RHP.
{ ¦
{ ¦
,
`
.

− ⋅
⋅
⋅ ·
,
`
.

− ⋅ ⋅ + ·
,
`
.

+ ≈
⇒ << ∧ << << •
< < ∴
,
`
.

+ ⋅
,
`
.

− ⋅
,
`
.

+ ≈
1
and
1
1 1 ) (
10
for
; 1 1 1 ) (
1
1
1
’
1 1 1 ’
1
2
1
3 2
’
1
3 2
’
1
R Gmo
R Gmo
w w
Gmo
R C s
w
s
s Z num
w w w w
w
w w w
w
s
w
s
w
s
s Z num
z z
z
Fa
a p
z
z z z
z z
z
Fa
{ ¦
( ) 1 : for and
C
s  1 1 1 ) (
10
for
1 2 2 2
’
1
2 1 2 1
1
2
’
1
2
2
− ⋅ ⋅ · <<
,
`
.
 ⋅
⋅
,
`
.

− ⋅ + ·
,
`
.

− ⋅
,
`
.

+ ≈
⇒ << ∧ << << •
R Gmo w w w w
Gmo
T
Gmo
C
T s
w
s
w
s
s Z num
w w w w
w
p z z z
p
z
z
z
Fa
a p a
p
(4.5)
We notice that the two zeros are related to the product Gmo.R
1
. However, we should remember
that R
1
is chosen with respect to the PLL bandwidth and gain (w
oln
and α
n
).
iv
Therefore keeping
a large enough Gmo.R
1
, may imply changing w
oln
.
However the choice of w
oln
is limited by many other criteria (spurious suppression, optimized
noise transfer, limitation with respect to discrete system nature,…), and it is better to keep some
design flexibility by assuring a high Gmo value.
4.1.4 Numerical example
We may visualize the influence of the new zeros of Z
Fa
(s) and the accuracy of the w
’
z1
and w
z2
estimates through a numerical example.
A reference case is calculated for an ideal amplifier (with Z
in
, Gmo and w
a
tending to infinite).
The reference case is equivalent to –Z
F
(s) .
A typical tuner application value is assumed for R
pu
, equal to 22 kΩ.
Figure 4.5 is calculated for a narrow band filter with the following parameters:
f
olnpf
=10 kHz; r
21
=25; r
31
=50;
for:
Fcp=1 MHz; Icp=200 µA;
Fvco=1.5 GHz; Kvco=100 MHz/V.
The resulting R
1
value is 4.4 kΩ, and R
3
is chosen to be equal to R
pu
.
iv
Equation (2.12) repeated here for convenience:
n
oln
1
α
w
R ·
.
Chapter 4 / Active Loop Filters: AC & disturbances issues 77
Curve a) corresponds to the ideal factorable transfer Z
F
(s) .
Curve b) and c) are Z
Fa
(s) with w
a
=w
p3
and two different values of Gmo.
Curve d) is an estimation of case c) using expressions (4.5) for w
’
z1
and w
z2
.
Figure 4.5 gm Influence in Open Loop Transfers
A phase margin loss and a decrease in reference suppression
v
is visible in cases b and c,
becoming quite restrictive in c) where we may no longer work with a (2.r
21
) gain variation.
v
Normally the reference suppression is calculated with the closed loop frequency response, B(s) , but since the open
loop magnitude is significantly smaller than 1 for f=f
cp
:
( )
( )
N
w B
w H
cp
cp
≈
.
So we call reference attenuation
( )
cp
w H N ⋅
, which represents the transfer of a phase disturbance at f
cp
injected at
the reference input, or equivalently, the transfer of a charge pump current disturbance divided by K
ϕ
.
d
c
a
b
c
d
a
b
78 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
We can define
’
1
2 ’
21
z
p
w
w
r · , which compared to r
21
gives an overall idea of the PhM loss.
The estimation of Z
Fa
(s), which is represented by curve d), is calculated replacing w
z1
by w
’
z1
and
adding w
z2
over an ideal transfer Z
F
(s). The zero frequencies, w
’
z
and w
z2
are evaluated by
equations (4.5).
The approximation is fairly accurate up to w
p2
, but for higher frequencies the absence of the
additional zeropole pair deviates the estimate from the real Z
Fa
(s) curve. Nevertheless, the w
’
z1
estimation is correct enough to evaluate the parameter r
’
21
.
The table below brings PhM and reference transfer values for the above curves. We remark that
in cases b) and c) the reference injection is no longer attenuated. The reference injection was
evaluated in terms of phase disturbance.
vi
case a) Z
F
(s) b) Z
Fa
(s)
with Gmo=25/R
pu
c) Z
Fa
(s)
with Gmo=10/R
pu
Gmo*R
1 → ∞ 5 2
[ ] dB
i
o
θ
θ 16.8 +8.05 +12.2
PhM(f
olnpf
)
[°]
62.2 55.6 39.5
PhM(f
olnpf
*r
21
)
[°]
33.4 17.9 9.72
r
21
or r
’
21
25 20.4 13.8
Table 42 Active Filter example: Phase Margin degradation
In this narrow band filter example, we notice that low values for the product Gmo.R
1
, may
degrade significantly the filter transfer.
If we take the same parameters in the above example, but recalculate it for a larger bandwidth
filter with f
olnpf
=50 kHz, we get a bigger R
1
value, equal to 22 kΩ. In this case, even for low gm
values, like in case c), the product Gmo.R
1
is still large, and no important degradation is
observed in the filter transimpedance. The parameter r
’
21
equals 23 for this large bandwidth
example, with Gmo=10/R
pu
.
Thus the requirements for the amplifier transconductance depend on the R
1
value, or in other
words, on the loop bandwidth and gain. Once more we repeat that a flexible amplifier design
should assure an important Gmo value, to avoid additional constraints on the bandwidth choice.
It is important to remember that the Gmo value varies along the output DC range. So we need to
identify the worst case situation and verify the stability boundaries for this case.
Since the PhM loss becomes worse for w
ol
close to w
p2
, we must avoid having the lowest Gmo
values for α tending to α
max
.
vii
vi
( )
( ) ( ) N w H w B
K w I w
dB
cp cp
cp ChP
o
cp i
o
log 20
) (
⋅ + ≈ · ·
ϕ
θ
θ
θ
vii
The high gain situation, α
max
, happens for large K
vco
, and small N, which corresponds to the beginning of the
frequency band, with low V
tune
values and high current output in the amplifier. For cases where the overall
Chapter 4 / Active Loop Filters: AC & disturbances issues 79
Finally we may identify a practical boundary for the transconductance pole, w
a
.
The pole w
a
is very determining for the position of the additional high frequency zero and pole.
It also slightly affects the RHP zero, w
z2
, but it has almost no drift over w
’
z1
. Thus, for w
a
larger
than w
p3
, its position concerns mainly the spurious attenuation, having a minor role for the PhM
loss.
4.1.5 Input impedance: Z
in
We will mention one last AC characteristics of the amplifier: its input impedance, Z
in
.The filter
transfer including Z
in
is named Z
Fai
(s) and can be compared to the first form of Z
Fa
(s) in (4.2).
( )
( )
( )
3
3
3
3
1
1
1
1
) (
p
u
in
u s
s
u Fai
T s
Z gm
Z
Z Z
Z gm
Z s Z
⋅ +
⋅
⋅ + +
,
`
.
 +
⋅ −
⋅ ·
(4.6)
The indication of frequency dependency (F(s)=F) for Z
s
, Z
3u
, Z
in
and gm is implied.
In order to approach Z
Fai
to Z
Fa
we impose a boundary for Z
in
: Z
in
>> Z
s
+ Z
3u
.
Often we search for a Z
in
with an infinite DCimpedance, which may be approached by a MOS
gate input. In this case Z
in
can be represented as an equivalent input capacitor C
in
.
The sketch below represents the impedance magnitudes: Z
s
, Z
3u
and Z
in
.
In this figure we suppose
R
3
≈ R
pu
and
R
1
< R
pu
, but we may
analyze C
in
constraint for a
general unknown
R
3
, R
1
and R
pu
.
Let us define w
i1
and w
i2
as
the intersection frequencies
of R
pu
and Z
in
, and R
1
and
Z
in
respectively.
Figure 4.6 Amplifier Input Impedance X Filter Impedance
( )
3 3
’
3
3 3
1 1
for
1
if ;
1
p u in p
pu
i
in pu
i
w w Z Z w
R R C
w
C R
w ≤ > ⇒ ·
+ ⋅
>
⋅
·
transconductance is directly proportional to the output stage current, this α
max
situation corresponds to a high Gmo
value. Nevertheless, AC simulations are necessary to check the gm for the whole amplifier (with the input stage) in
different points of the DC working range.
w
’
p3
w
i1
w
i2
R
1
Z
in
(w)
Z
3u
(w)
R
pu
Z
s
(w)
Z(jw)
w
[rad/sec]
w
p3
w
p2
w
z1
80 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Hence keeping Z
in
>> Z
3u
for a maximum frequency higher than w
p3
, and for an unknown R
3
,
implies: C
in
<< C
3
w Z Z
C R
w w
C R
w
s in p i
in
i
∀ > ⇒
⋅
· >
⋅
· for
1
if ;
1
2 1
2 2
1
2
So for Z
in
>> Z
s
we must choose C
in
<< C
2
.
It was already suggested, during the calculation of Z
F3
(s) , to work with C
2
>>C
3
; which allows
us to reduce the Z
in
restriction to: C
in
<<C
3
.
4.1.6 Summary of AC boundaries for filter design
An outline of all the boundaries proposed in this section :
amplifier) filter active for impedance input negligible (
) ( ) ( for
and
ion) approximat factored with compared r denominato order 3 (full
) ( ) ( for
3
3 1
3 2 1
s Z s Z
s Z s Z
R R
C C C C
Fa Fai
rd
F F
in
→
→
]
]
]
]
]
]
]
]
<<
>> >> >>
one) passive with compared nsfer filter tra (active
) ( ) ( for
5
10
1
3
s Z s Z
R Gmo
R Gmo
w w
F Fa
pu
p a
→
]
]
]
]
]
> ⋅
≥ ⋅
≥
4.2 Disturbances and Noise Propagation
The amplifier noise is sometimes visible in the outofloop zone of the locked spectrum,
worsening the expected phase noise performance.
viii
Another degradation caused by active filters is the transmission of disturbances injected in the IC
internal supply nodes.
We may quantify these effects seeking the AC transfer of noise and disturbance sources present
in the active filter model.
The supply disturbance is shown as a deterministic AC signal source, v
d
(t), with an equivalent
Laplace form, V
d
(s) .
A simplified representation, analogue to an AC model, is applied for the noise sources. The noise
sources are replaced by independent AC sources, and uncorrelated noise sources are added in
viii
L(f
offset
) for frequencies out of the PLL bandwidth is ideally equivalent to the freerunning VCO behaviour; but
in practice, filter passive elements are already bringing some extra baseband noise that is frequency modulated by
the VCO.
Chapter 4 / Active Loop Filters: AC & disturbances issues 81
power magnitude. The statistical theory allowing such a treatment is shortly discussed in chapter
6.
The same notation used for AC sources is adopted for the noise sources, and we define small
signal sources i
ni
and v
ni
representing component i noise in a current or voltage form.
The frequency domain representations for (i
ni
)
2
and (v
ni
)
2
are the classical power densities for
electrical noise (thermal, shot, flicker,…).
We take the freedom to define the noise transfers in Laplace transform, but we must remember
that noise transfers are just defined for power magnitudes. Hence a transfer F(s) for a noise
source replaces the power transfer of the noise PSD, which is actually represented by F(jw)
2
.
A short revision on electrical noise sources and notations follows below.
4.2.1 Random Electrical Noise
We consider restrictively the most common types of electrical noise: thermal, shot and flicker
noise.
The notation adopted is in the form of unitary impedance power densities, expressed in current or
voltage terms:
f
jw V
f
jw I
∆ ∆
2 2
) (
,
) (
.
The thermal noise is associated to resistors, and has the following current or voltage
representation:
2
2
2
2
2
2
2
4 ;
4
R
V
I
Hz
V
R T k
f
V
Hz
A
R
T k
f
I
n
n
rms
n
rms
n
·
]
]
]
⋅ ⋅ ⋅ ·
∆
]
]
]
⋅ ⋅
·
∆
K
T is the absolute temperature, in Kelvin, and k is the Boltzmann constant: 1.38.10
23
V.C/K .
Shot noise is encountered in any conducting junction, and flicker noise is associated to active
devices.
The shot noise associated with I
D
, the current of a diode or bipolar transistor (base or collector),
is:
]
]
]
⋅ ⋅ ·
∆
Hz
A
I q
f
I
rms
D
n
2
2
2
with q the charge of the electron in coulombs: 1.60.10
19
C .
The flicker noise associated with I
B
, base current in a bipolar transistor, is:
]
]
]
⋅ ·
∆
Hz
A
f
I
K
f
I
rms
B
f
n
2
2
β
α
;
where, K
f
, α and β are process dependent parameters, commonly determined through
measurements. Typically, α and β have values around one. K
f
reflects the quality of the
interfaces between diffusion layers, and a low K
f
is associated with mature, and well controlled
processes.
82 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
4.2.2 Supply Disturbances
The voltage source v
d
represents the
disturbances found in the IC internal
supply and ground nodes.
Figure 4.7 Supply disturbances
These disturbances can be RF current pulses either injected in the substrate or simply drained
from the external supply causing a voltage drop difference (ddp) as they go through the
connection path impedance. The disturbance v
d
often arises as deterministic modulating tones at
the oscillator input.
Switching blocks working with very steep voltage slopes and clipped signals are a typical
example of v
d
generating circuitry, since they may inject quite some current in the substrate
through the collectorsubstrate capacitors. The crystal oscillator for low noise PLLs, working
with large and steep swings is a good example.
The source v
d
is almost directly transmitted to V
tune
, being only filtered by the first order
attenuation of the postfilter.
The transfer function shown in table 43 is calculated for Z
o
and Z
in
→ ∞. . An infinite Z
o
means
that the output current variation due to v
d
is neglected: v
d
/Z
o
<< gm.v
d
.
In passive filters, such disturbances are better attenuated. First v
d
is transformed into a current
error by the charge pump output impedance, which is typically high. Afterwards this current
error is filtered by the whole Z
F
(s), which roughly represents a 2
nd
order LPF with a lower cut
frequency than w
p3
.
Eventually in the active filter design we may interchange w
p2
and w
p3
, placing the lower pole
after the amplifier in order to improve v
d
rejection. This exchange should be checked in a
numerical application to verify gm influence in w
p2
placement, and the real PhM in Z
F3
(s)
compared to the factored Z
F
(s) .
4.2.3 Amplifier Noise
It is opportune to evaluate and represent the amplifier noise by a current noise source at its
output (i
na
in figure 4.8).
The usual noisy twoport representation with noise sources at the quadripole input is convenient
for settings with a well known source and input impedance, but it is not adapted to a variable
vM
Zo
Zs
vd
R3 Icp
gm.vin
Vtune
Zin
C3
Z3u
Rpu
vin
Chapter 4 / Active Loop Filters: AC & disturbances issues 83
source impedance (charge pump on or off) and a very large input impedance (approaching
infinity, approximation of the amplifier input impedance). Furthermore the amplifier noise varies
with respect to its output current, and this is more clearly depicted by a noise source in parallel to
the output port.
The amplifier noise appears in V
tune
attenuated by the transconductance gm, and filtered by the
w
p3
pole. The gm poles also introduce an equal number of extra zeros and poles in the V
tune
/I
na
ratio . The transfer function in table 43 is detailed for a gm with a single dominant pole.
The postfilter components are not explicitly
drawn in figure 4.8 but as long as we
calculate V
M
with a load impedance equal to
Z
3u
, V
tune
it is easily derived as:
3
1
1
p M
tune
T s V
V
⋅ +
·
Figure 4.8 Amplifier noise
The thermal noise of the pullup resistor, R
pu
, may be symbolized by a current source i
npu
,
placed in parallel to i
na
; thus the transfer V
tune
/I
npu
is identical to the function V
tune
/I
na.
.
4.2.4 Filter Component Noises
In figure 4.9 we add the noise sources from the filter resistors R
1
and R
3
. They are the only
noise sources common to both active and passive loop filters .
Figure 4.9 Filter components noise
Resistors thermal noise is depicted either in current or voltage form, following the convenience
of the transfer calculation.
R
1
noise (I
n1.
) is associated to the parallel R
1
//C
2
impedance and transformed in its Thevenin
equivalent, V
n12
, whose transfer to V
tune
is quite similar to V
tune
/V
d
.
R
3
noise in its voltage form (v
n3
) is only filtered by the postfilter before emerging directly in
V
tune
.
vin
Z3u
vM Zo
Zs
ina
Icp
gm.vin Zin
Zs
in1
C2
C1
Rpu
vM
R1 R3 vn3
Icp
gm.vin
Vtune
Zin
C3
vin
Zs vn12
2
1
1 12
1
) ( ) (
p
n n
T s
R
s I s V
⋅ +
·
84 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
4.2.5 Transfer functions table
The following transfer functions were evaluated for the AC models in figures 4.7 through 4.9,
with the approximation: Z
in
→ ∞ and Z
o
>> R
pu
.
The general expressions using variables gm and Z
3u
are further specified for the particular gm
case with a single dominant pole. These simplified expressions are also bounded by other
conditions that are indicated in table 43 . The expressions of Z
3u
and the 1
st
order gm are
recalled below.
( )
( )
3
’
3 ’
3
3
3
: with
1
1
;
1
p p
p
p pu
u
a
w w
T s
T s R
Z
w
s
Gmo
gm <
⋅ +
⋅ + ⋅
·
,
`
.

+
·
Signal Transfer to V
tune
Specific pratical approach
for a 1
st
order gm
Internal supply
disturbances:
v
d
(t) ↔ V
d
(s)
( ) ( )
3 3
3
1
1
1
p u
u
d
tune
T s Z gm
Z gm
V
V
⋅ +
⋅
⋅ +
⋅
·
3
3
1
1
for
p d
tune
u a
T s V
V
Z Gmo w w
⋅ +
≈
⋅ ⋅ <<
Amplifier noise:
i
na
↔ I
na
(s)
Pull up resistor,
R
pu
noise:
i
npu
↔ I
npu
(s)
( ) ( )
npu
tune
na
tune
u p
u
na
tune
I
V
I
V
Z gm T s
Z
I
V
·
⋅ + ⋅ ⋅ +
·
3 3
3
1 1
( )
,
`
.

⋅ ⋅
+
,
`
.

+
⋅
⋅ +
≈
>> ⋅
a u
a
p na
tune
u
w Z Gmo
s
w
s
T s
Gmo
I
V
Z Gmo
3
3
3
1
1
1
1
1 for
Filter components
noise (R
1
):
i
n1
↔ I
n1
(s)
( ) ( ) ( )
3 2
1
3
3
1
1 1 1
p p u
u
n
tune
T s T s
R
Z gm
Z gm
I
V
⋅ + ⋅ ⋅ +
⋅
⋅ +
⋅
·
( ) ( )
3 2
1
1
3
1 1
for
p p n
tune
u a
T s T s
R
I
V
Z Gmo w w
⋅ + ⋅ ⋅ +
≈
⋅ ⋅ <<
Filter components
noise (R
3
):
v
n3
↔ V
n3
(s)
( ) ( )
3
3
3 3 3
1
;
1
1
p n
t
p n
tune
T s
R
I
V
T s V
V
⋅ +
·
⋅ +
·
Table 43 Disturbances transfer functions
The above transfer functions are better illustrated by a simulation example developed in the
following section.
Chapter 4 / Active Loop Filters: AC & disturbances issues 85
4.2.6 Simulation Example
Figures 4.10 and 4.11 present the scheme and results of an AC noise simulation for an active
filter, with an integrated amplifier and external passive components for R
pu
, Z
s
and the post
filter.
R
d
thermal noise symbolizes an AC disturbance between the internal and external grounds. A
small resistor value was chosen to avoid significant DC disturbances. The transfer for the
thermal noise of R
d
is equivalent to the transfer of V
d
(a supply disturbance). However we should
remember that this thermal noise is a broadband source with a rather small amplitude in our
numerical application.
The DCoperating point is fixed by a voltage source with a high series impedance, R
biasin
.
A large source impedance is necessary to avoid interfering in the filter AC transfer within the
frequency range containing the zeros and poles of interest. Besides, R
biasin
noise contribution at
V
tune
appears as a current source filtered by Z
s
and Z
3u
; and the larger the resistor the smaller the
equivalent current noise generator. For a 10MΩ resistor, R
biasin
has a negligible effect on the
total output noise for the plotted frequency range (10Hz to 1GHz).
The passive components are chosen for the following zero, poles and open gain values:
f
z1
= 1.9kHz; f
p2
= 48kHz; f
p3
= 106kHz ;
with: f
oln
= 9.5kHz; α
n
= 6; r
21
= 25 .
These numerical values are close to a satellite application, like the one shown in the Bode plots
of figure 3.5.
Figure 4.10 Noise simulation scheme
I
dc
1.24mA
gnd
vcc
R
d
1Ω
IC internal ground
30 V
V
dc_high
V
tune
330pF
8.2nF
10kΩ
R
biasin
10MΩ
22kΩ
22kΩ
68pF
IC blocks
Input
Stage
Zin
Gm
Stage
gm.vin
Loop Amplifier
Bias
block
V
biasin
1.7 V
5 V
86 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
The analog simulator models thermal, shot and flicker noise sources, in the form of unitary
impedance power densities (
f
jw V
f
jw I
∆ ∆
2 2
) (
,
) (
).
The resistors have intrinsic thermal noise and the current in the transistors of the amplifier
contribute with shot and flicker noise components.
Figure 4.11 shows the voltage noise density at the V
tune
output, total Vn, and the separated
contributions of the noise sources whose transfer we identified in table 43 .
The notation Vni stands for the noise voltage contribution of element i, in dBV/Hz units.
Vna is for the amplifier noise, and Vnd, Vnpu, Vn1 and Vn3 for the resistors R
d
, R
pu
, R
1
and
R
3
respectively.
The amplifier noise in our example (Vna1_total) is dominated by the gm stage, which is quite
often a commonemiter, open collector output transistor. In the plot below this transistor base
current shot and flicker contributions are explained, (Vna1_ib and Vna1_fn respectively).
Figure 4.11 Noise simulation results
The simulation shows an overall filter noise dominated by the postfilter resistor, R
3
, except for
low frequencies, where the gmtransistor flicker noise becomes important.
V
nvco
[Hz]
Chapter 4 / Active Loop Filters: AC & disturbances issues 87
In section 3.2 we saw the representation of the oscillator freerunning intrinsic behaviour as a
voltage noise source, v
nvco
, at the VCO input (eq. (3.3) ). The overall filter noise appears as well
at the VCO input, and is added (in power magnitude) to v
nvco
.
Let us call the overall filter noise contribution, v
nfilter
, and the total voltage noise at the oscillator
input, v
na
:
2 2 2
nfilter nvco na
v v v + ·
The closed loop transfer of v
nvco
to the output spectrum was named B
vco
(s) , and figure 3.12
sketched the output spectra for a flat (white) noise input. Basically, a voltage noise appearing at
the VCO input is bandpass filtered, with a central frequency close to the PLL closed loop
bandwidth.
After the addition of the filter noise contribution, we need to verify that the v
na
components are
still sufficiently supressed in the inloop range, and how much or how far the outofloop
behaviour deteriorated.
ix
We may compare v
nfilter
of figure 4.11 with the v
nvco
of a satellite VCO, with:
( )
Hz
dBV
f
v
Hz
V
n
f
v
Hz
V
f
v
V MHz Kvco
Hz dBc kHz L
nvco
rms nvco rms nvco
157 log 10 or
14 ; 10 2
/ 100
/ 100 100
2
2
16
2
− ·
,
`
.

∆
⋅
·
∆
⋅ ·
∆
⇒
·
− ·
−
The value of v
nvco
is indicated in figure 4.11 by a dashed line. We verify that the filter noise is
dominant for frequencies below 100kHz, or with respect to the filter poles, below f
p3
. Since the
PLL closed loop bandwidth will usually vary between f
z1
and f
p2
frequencies, it is most likely
that some extra outofloop noise will be visible up to an octave after f
p3
. Hence the value of R
3
may be changed to improve this outofloop performance, still keeping in mind the boundaries
discussed in section 4.1.6.
The marker trace, M1, highlights the f
p2
pole position, which is visible as a filtering corner on
the R
1
noise contribution.
In fact the different noise contributions correspond quite accurately to the simplified transfer
expressions in table 43. The numerical values below for the resistor noise sources help to verify
this result.
R
[ ]
Hz
V
nvco
rms
f v ∆ ( ) [ ]
Hz
dBV
nvco
f v ∆ ⋅
2
log 10
R
d
: 1Ω 0.129n 197
R
pu
, R
3
: 22kΩ 19.1n 154
R
1
: 10kΩ 12.9n 158
Table 44 Noise sources voltage spectrum density
ix
It is convenient to simulate such effects with a base band PLL model. In chapter 7 a system level model is
presented, including the filter noise effects, and also an empirical approach for the phase detector discrete behaviour
influence in the PLL noise.
88 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
The thermal noise sources are evaluated for a 300K temperature, or a 4kT=1.66.10
20
VC .
The difference in R
pu
and R
3
noise contributions at the V
tune
output, shows quite clearly the
amplifier feedback rejection of I
npu
and
I
na
(as discussed in 4.2.3). Actually, for low frequencies,
a R
pu
noise represented as a voltage source is attenuated by the amplifier gain:
Gvo=Gmo.R
pu
.
The amplifier design used in this simulation has effectively a capacitive input impedance, with
an equivalent C
in
much smaller than C
3
in the postfilter. This situation well suits the
approximation of Z
in
→ ∞ , as assumed in the expressions in table 43.
For cases with a lower Z
in
the transfers are modified and part of V
d
and V
n12
appear as current
disturbances filtered by Z
s
. A similar effect is observed for a decreasing source impedance (R
bias
in
). In a complete PLL, this source impedance is the charge pump output impedance, which has a
variable value depending on whether it is conducting (on) or not (off). For a PLL in locked
mode, the charge pump is mostly off, and it does present a rather high impedance.
Thus the transfers from table 43 are a valuable reference to understand and explore simulation
results for the loop amplifier design.
This chapter developed analytical and practical approaches to deal with AC characteristics of
active loop filters. The practical boundaries and simplified transfer expressions provide the
means to evaluate and specify the design of the loop amplifier.
Furthermore for cases with an equal tuning and biasing range, these evaluations indicate the
tradeoff between passive and active filtering solutions.
In addition we introduced noise considerations that start to relate system specifications to a
circuit implementation. Specifically, the noise of the loop filter is mostly influent in the outof
loop zone of the VCO spectrum, thus its noise level is compared to the inherent noise sources of
the VCO.
Chapter 5 / Limitations of the LTI Phase Model 89
Contents:
5. Limitations of the LTI Phase Model 89
5.1. Threestate comparator: frequency and phase detector ......................................................................... 91
5.1.1. Minimum phase deviation range ................................................................................................... 92
5.2. DC range limitations............................................................................................................................... 94
5.2.1. Loop filter time domain response.................................................................................................. 94
5.2.2. Numerical examples and design considerations ............................................................................ 96
5.3. Lock convergence approaches ................................................................................................................ 99
5.3.1. Frequency approach..................................................................................................................... 100
5.3.2. Phase approach............................................................................................................................ 103
5.3.3. Comparing the frequency and phase approaches......................................................................... 105
5.4. Discrete transfers for the PLL Phase Model......................................................................................... 109
5.4.1. The sampler ................................................................................................................................. 109
5.4.2. The holder.................................................................................................................................... 111
5.4.3. Continuous equivalent with transmission delay .......................................................................... 114
Figures:
Figure 5.1 Phasedetector & Charge Pump transfer.................................................................................... 91
Figure 5.2 Maximum Phase Detection Range & Cycle slips ....................................................................... 92
Figure 5.3 Condition for unlimited frequency tracking range..................................................................... 93
Figure 5.4 Loop Filter: time response for current pulses ............................................................................ 94
Figure 5.5 Time response through normalized functions ............................................................................ 96
Figure 5.6 Convergence towards lock: phase deviation sequence............................................................... 99
Figure 5.7 Frequency approach convergence criterion ............................................................................. 103
Figure 5.8 Phase approach convergence criterion..................................................................................... 104
Figure 5.9 Comparing frequency and phase approaches........................................................................... 105
Figure 5.10 Convergence approaches X leadlag spacing r
21
.................................................................... 107
Figure 5.11 Convergence approaches X gain variation............................................................................. 108
Figure 5.12 Discrete model for digital blocks............................................................................................... 110
Figure 5.13 Discrete phase detector input: ∆ϕ
n
............................................................................................ 111
Figure 5.14 Charge Pump DAC output ......................................................................................................... 112
Figure 5.15 Continuous equivalent with transmission delay ....................................................................... 114
Figure 5.16 Frequency and Time response for the continuous + delay model ........................................... 115
5 Limitations of the LTI Phase Model
Phase noise constraints, and even more integrated oscillator architectures, demand increasing
bandwidths in PLL synthesizers. As the PLL bandwidth increases the comparison frequency
needs to increase as well to keep the system stable.
In fact, design and stability constraints will appear to limit the values of both f
ol
and f
cp
.
These limitations are not contained in the LTI model discussed so far, but they can be evaluated
and/or added with additional considerations.
90 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
The limit for maximum feedback bandwidth, f
cl
/f
cp
, was already mentioned in chapter 3, making
an analogy to Nyquist bandwidths for sampled systems.
The sampled nature of the PLL is connected to the digital blocks, phase detector and dividers,
that we modeled so far, as linear continuous elements. Therefore the stability boundary, for
f
cl
/f
cp
, can only appear by including discrete characteristics in the loop model.
The threshold bandwidth determines a limit for single loop configurations, associated to poor
noise performance oscillators. We also saw (section 3.5) that spectrum optimization in the basis
of a minimum L(f) criteria may encounter limitations bound to the maximum feedback
bandwidth.
In this chapter we develop two approaches to evaluate maximum bandwidth stability conditions.
The first comes from a time domain model, examining the loop convergence from acquisition to
lock mode. The second introduces time delay compensations into the frequency domain phase
model.
The time domain expressions are also used to consider problems related to reduced DC tuning
ranges. They are mostly encountered for fully integrated oscillators working with large
bandwidth PLLs and a tuning range equal to the circuit supply voltage.
Multiloop configurations are an architectural solution to the limitations of the feedback
bandwidth. However, multiloop configurations tend to work with at least one wide band loop at
high comparison frequency; and in this case, we may see design constraints reducing the linear
portion of the phase detector/charge pump transfer.
In frequency synthesizers we are concerned about the minimum linear range necessary to
guarantee an unlimited frequency tracking behaviour. In other words, the limit for the threestate
comparator as a frequency and phase detector.
The ensemble of limitations above have nonlinear characteristics that can either be included in
the LTI model, through compensations, or evaluated to mark its validity boundaries.
The first three sections deal with the PLL acquisition mode, which is not a steady mode where
the PLL can be used as a frequency synthesizer.
Nevertheless, after every change in the PLL programming the loop passes through an outoflock
interval, and we need to verify how the loop parameters influence the acquisition, i.e., the
convergence towards a locked mode.
The acquisition or tracking mode is formally treated in the de/modulators and in the clock/carrier
recovery contexts. A nice discussion of pulling time and pulling range may be found in reference
[Wola91] for different types of phase detectors.
Here we limit our scope to a qualitative understanding of the threestate phase detector in its
frequency detector range, and to two quantitative approaches for lock convergence in the phase
detection range.
A couple of characteristics of the acquisition mode, such as locking time and maximum phase
change for a certain step (closely related to the rising time), may be specified by constraints that
are related to the functioning of the demodulator, and to the timing for the programming of the
different circuits in a receiver. Nevertheless these characteristics may also be derived from the
linear model, as far as the validity bounds of this representation are known.
Chapter 5 / Limitations of the LTI Phase Model 91
5.1 Threestate comparator: frequency and phase detector
As mentioned in section 1.5.3 the tristate phase detector has an unlimited tracking range. This
behaviour is assured by a monotonously increasing or decreasing average charge injected in the
loop filter, for input signals with a positive or negative frequency difference.
The figure below helps us to understand the idea of this average charge.
Let us suppose a passive filter PLL, and a lagging oscillator. In this case, the divider is late with
respect to the reference and the charge pump is sourcing, i.e. injecting current in the loop filter
impedance.
If the two input signals are not at the same frequency, the phase difference will periodically
exceed 2π and the phase detector will slip to a new linear part of the transfer curve starting at
(n.2π), with n ∈ N.
The phase detector slips are periodical with a rate corresponding to the frequency difference. The
phase detector works as a frequency deviation detector.
Figure 5.1 Phasedetector & Charge Pump transfer
After some time, when the oscillator frequency approaches the programmed value, the phase
differences, minus (n.2π), will oscillate between positive and negative values.
The oscillator approaches lock, and we will call this functioning mode, with low frequency
difference: the phase detection trapping zone. In figure 5.1 this is represented by the grey
dotted line.
i
Hence, we realize that our transfer function, I
average
/∆ϕ, is representing the average current over
one comparison period; and, for input signals with different frequencies the average current over
several periods is proportional to the frequency difference.
However, in the PLL, the oscillator frequency is changing continuously with respect to V
tune
,
i.e., proportionally to the charges stored in the loop capacitors. Therefore it is difficult to talk
about a frequency difference, or an average current, over several periods, and it is easier to talk
about an accumulated charge over several periods.
i
The dotted curve is slightly shifted to the right of 2π just for a better visualisation.
I
cp
I
average
[A]
I
cp
∆ϕ
[rad]
4π 2π 0 2π 4π
92 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
For the phase detector transfer sketched above, as far as the oscillator frequency is not equal to
(N.f
cp
), the average charge derivative has the same sign as the frequency difference.
Thus, the loop is capable of tracking any frequency difference inside the oscillator tunable range.
Once we recognize that the frequency correction depends on the average charge, we may
consider which limitations occur in the transfer, I
average
/∆ϕ, that would still enable us to guarantee
a monotonously changing charge, with the same signal as the input frequency delta. These
limitations are related to the width of the reset interval, and they define a maximum comparison
frequency for our tristate comparator.
5.1.1 Minimum phase deviation range
A subsequent question arises for loops working with high comparison frequencies, where the
charge pump reset delay (τ
rst
) becomes comparable to T
cp
, and significantly reduces the phase
deviation input range.
As discussed in section 1.5.3, the reset delay is introduced to avoid the deadzone problem, and
its width is related to the charge pump, current sources, switching on time.
Figure 5.2 sketches possible inputs and outputs of a phasedetector/chargepump block, for a
PLL in acquisition interval. In this example the reset delay (τ
rst
) is almost half of the comparison
period (T
cp
).
The drawing is simplified, showing only a limited slew rate for the charge pump outputs. The
reset command and the divider outputs are assumed as faster logic stages with a much higher
slew rate.
Figure 5.2 Maximum Phase Detection Range & Cycle slips
Ref.div.
output
Main div.
output
Charge
Pump
And
+
delay
T
cp In the
Ph.Detector
Ref. input
Var.input
Sourcing
&
Sinking
currents
asynchr.
reset
τ
rst
Chapter 5 / Limitations of the LTI Phase Model 93
Figure 5.2 shows a VCO varying towards lock. The VCO is initially at a good frequency but it
has a phase advance of ∆ϕ
1
. The reset delay is large enough to hide the following front of the
variable input, and consequently the next phase deviation is measured with respect to the
reference input. The phase detector has slipped one cycle.
The current output after this cycle slip, increases V
tune
and further accelerates the VCO. After
some cycles the VCO is again in advance and the charge pump current starts sinking out charges
from the loop filter.
These cycle slips, due to the finite reset window, may be represented in the transfer function
I
average
/∆ϕ
in
. They appear as a decrease in the linear portion; in reality, the transfer is not linear
up to t 2π, but only up to t 2π.(1−τ
rst
/Τ
cp
).
The resulting transfer is shown in figure 5.3 for
2
1
·
cp
rst
T
τ
.
Figure 5.3 Condition for unlimited frequency tracking range
We observe that τ
rst
equals T
cp
/2, is the limiting value for which the accumulated charge has the
same sign as the derivative of the phase difference.
Therefore to guarantee an unlimited frequency tracking range, f
cp
is limited to:
rst
cp
f
τ ⋅
<
2
1
(5.1)
Another way to derive the minimum range of the linear portion, is to seek a convergence
condition for the phase deviation values.
Let us consider a discrete variable ∆ϕ
n
, representing the phase deviation of the nth comparison
period. Close to lock the phase deviation sequence should decrease towards zero:
n n
ϕ ϕ ∆ < ∆
+1
(5.2)
This degressive sequence can only be obtained, over a cycle slip, if the linear portion of the
transfer covers the range [π , +π ]. Otherwise the module of the phase deviation would increase
after each cycle slip, avoiding the convergence towards the lock condition.
Thus we confirm the boundary proposed by the average charge approach.
3π π
I
cp
/2
I
cp
I
average
[A]
I
cp
I
cp
/2
∆ϕ
[rad]
4π 2π 0 2π 4π
∆Q = 0
2π
π
0
∆Q > 0
2π
∆ϕ > π
0
94 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Next, we continue to analyze other limitations of the linear model, related to the limited DC
tuning range.
The minimum phase deviation range stated above will be used in the convergence analysis to
limit the phase detection zone, and in the numerical examples of V
tune
deviations due to cycle
slips.
5.2 DC range limitations
In figure 5.2 we saw that reducing the linear portion of the phase detector transfer causes some
extra “frequency bouncing”, before the oscillators attain a locked condition. In fact the cycle slip
causes the inversion of the charge pump current with respect to the previous comparison interval.
This effect may be quantified as a V
tune
deviation, and compared to the VCO tunable range.
The comparison inform us about limiting bandwidth values to avoid bouncing up and down with
V
tune
deviations as big as the VCO tuning range.
A 2
nd
order filter is chosen, because it already contains the leadlag characteristics of the 3
rd
order filter, but the resulting expressions are shorter and the physical meaning is more easily
understood. Comments about 1
st
and 3
rd
order filters are made to extend the present results to
these other cases.
5.2.1 Loop filter time domain response
We use the Laplace inverse transform to evaluate the loop filter response for a current pulse
input, with amplitude I
cp
and width T
d
.
Figure 5.4 Loop Filter: time response for current pulses
I
cp
0 T
d
T
cp
v
M
(0)
t (s)
i(t)
v
M
(t)
i(t)
Z
s
R
1
C
1
C
2
v
M
(t)
Chapter 5 / Limitations of the LTI Phase Model 95
¹
¹
¹
¹
¹
¹
¹
'
¹
]
]
]
]
⋅
,
`
.

− + ⋅ ⋅ + ·
]
]
]
⋅ + · ≤ ≤
]
]
]
,
`
.

− + ⋅ ⋅ + · ≤ ≤
− − − − −
−
2 2 2
2
) (
1
1
) (
2 1
1
1
1 ) 0 ( ) ( ) ( ) ( :
1 ) 0 ( ) ( : 0
p
d
p
d
p
d
p
T
T t
T
T
z
d
cp M
T
T t
d C d C M cp d
T
t
z
cp M M d
e e
T
T
R I v e T v T v t v T t T
e
T
t
R I v t v T t
(5.3)
where
2 1 2 1 1 1
; C R T C R T
p z
⋅ · ⋅ ·
.
The expression for v
M
(t) in the discharging interval, [T
d
, T
cp
], is written in two forms. The
second form assumes a C
2
almost discharged at t=0:
⇒ ) 0 ( ) 0 (
1 M C
v v ≈ .
Roughly, when the charge pump is active, the filter impedance is charged or discharged in a rate
proportional to Icp, and when the charge pump is off a portion of V
tune
discharges through the
parallel R
1
C
2
branch. The charge pump output impedance and the VCO input impedance are
considered very high, though C
1
discharge is not visible within T
cp
.
A 1
st
order filter (single RC series branch) would present a stepwise variation in V
tune
when Icp
is turned off, with an amplitude equal to: (I
cp
. R) .
ii
A 3
rd
order filter (like in figure 2.4) would have an extra time constant appearing in the charge
and discharge intervals; for instance, C
1
discharge would have to be considered, and it would
depend on the ddp difference between v
M
and v
out
at t = T
d
.
The maximum V
tune
variation happens during tI
cp
injection. We choose T
d
= T
cp
/2 as the
injection interval, and equivalent V
tune
deviation, to be compared to the tunable range.
This interval of T
cp
/2 is equivalent to phase deviations of tπ. So for a loop working with a large
f
cp
, this interval is equivalent to the worst phase deviation that can occur after a cycle slip. On the
other hand, for a loop working with a low f
cp
, this interval equals an average deviation within the
phase trapping zone.
So V
tune
deviation is evaluated as ∆v
M
(T
cp
/2) :
[ ] ( )
( )
]
]
]
]
,
`
.

− +
⋅
⋅ ⋅ ·
,
`
.

∆
−
,
`
.

·
,
`
.

∆ · ∧ ∈
⋅
−
2
2
1
1
1
2 2
0
2 2
:
2
, 0
p
cp
T
T
z
cp
cp
cp
M
M
cp
M
cp
M
cp
d d
e
T
T
R I
T
v
v
T
v
T
v
T
T T t
Since we look for maximum bandwidth boundaries, ∆v
M
(T
cp
/2) should be expressed as a
function of f
oln
and f
cp
. Let us define the bandwidth ratio, x, and rewrite the V
tune
deviation as a
function of x and r
21
.
ii
This variation term, named phase detector ripple in reference [Gard80], has to be inferior to the VCO input range.
Reference [Gard80] discuss an approach of maximum PLL bandwidth, through the analysis of discrete transfer
functions.
96 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
[ ] ; 1 , 0 with
oln
∈ · x
f
f
x
cp
and remembering:
2 oln
z1 oln 21
1
T
p
T w
w r
⋅
· ⋅ ·
( ) [ ] ) , ( exp 1
2
21 1 21
21
1
r x g R I x r x
r
R I
T
v
cp cp
cp
M
⋅ ⋅ ·
]
]
]
]
⋅ ⋅ − − + ⋅ ⋅ ⋅ ·
,
`
.

∆ π
π
(5.4)
or for a I
cp
value corresponding to α
n
, and K
vco
an average frequency sensitivity:
[ ] [ ] ) , ( 2 ) , (
2
2
21 21
r x g x
f
f
V r x g x
K
f
T
v
osc
osc
tune
vco
osc
cp
M
⋅ ⋅
∆
⋅ ∆ ⋅ · ⋅ ⋅
⋅
·
,
`
.

∆ π
π
(5.5)
The functions g(x, r
21
) and x.g(x, r
21
) are plotted for a constant r
21
in figure 5.5.a and 5.5.b
respectively. For a given r
21
, g(x, r
21
) varies between two linear functions, and x.g(x, r
21
)
between two quadratic functions of x, corresponding to the limiting values, 0 and 1, of the
exponential term.
Expression (5.4) , with I
cp
and R
1
variables, is useful in the analysis of a given synthesizer with
fixed parameters and application components. Still, R
1
and I
cp
are related to the loop bandwidth
and gain, so for a system under definition (5.5) is better suited.
Figure 5.5 Time response through normalized functions
5.2.2 Numerical examples and design considerations
fig. 5.5.a fig. 5.5.b
Chapter 5 / Limitations of the LTI Phase Model 97
Expressions (5.4) and (5.5) are better perceived through numerical examples. Let us consider
three different situations with common values for the following parameters:
These values are again comparable to a bandL, satellite synthesizer application. The comparison
frequency is not especially high, and our phase detector transfer should be linear up to t(1,996)π.
Therefore ∆v
M
(T
cp
/2) is an average V
tune
deviation.
• Example I: What are the values of the bandwidth ratio and ∆v
M
(T
cp
/2) for a loop filter with
R
1
= 10kΩ and r
21
=25 ?
( ) V g V
T
v
x
x kHz f
w
R
cp
M
47 , 1 25 ; 0398 , 0 3
2
1 , 25
1
; 0398 , 0 ; 8 , 39
oln
n
oln
1
· ⋅ ·
,
`
.

∆
· · · → ·
α
This narrow band filter situation may be compared to two specific oscillator contexts with
different tuning ranges.
In both cases a PLL bandwidth is evaluated for an average V
tune
deviation equal to the tuning
range. The resulting f
oln
is named DCthreshold bandwidth.
• Example II: What is the DCthreshold bandwidth for a LC oscillator with 28 V of tuning
range?
[ ] kHz f
x
x x g x
K
f
V
vco
osc
312 ; 21 , 3
1
; 312 , 0 ) 25 , (
2
28
oln
· · · ⋅ ⋅
⋅
·
π
For a satellite band LC oscillator, a sensitivity of 125 MHz/V corresponds to a maximum K
vco
value, rather than an average one. Hence the ∆v
M
(T
cp
/2) value is somewhat exaggerated and the
DCthreshold bandwidth is a pessimistic estimation.
However practical experience shows that a bandwidth of 312 kHz for a loop with a 1MHz
comparison frequency is rather unfeasible. So for loops with a large DC range, we may expect
that another limiting characteristic will determine the maximum f
oln
.
Sections 5.3 and 5.4 discuss maximum bandwidth ratios through stability approaches.
α
n
= 25 A.Hz/V
(1−τ
rst
/Τ
cp
) · 0,998
N = 1,5 k
• K
vco
= 125 MHz/V
• I
cp
= 300 µA
• f
vco
=1.5 GHz
• f
cp
= 1 MHz
• τ
rst
= 2 ns
• r
21
= 25
98 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
• Example III: What is the DCthreshold bandwidth for an RC fully integrated oscillator with
3.4 V of tuning range?
[ ] kHz f
x
x x g x
K
f
V
vco
osc
66 ; 2 . 15
1
; 066 . 0 ) 25 , (
2
4 . 3
oln
· · · ⋅ ⋅
⋅
·
π
In this example the resulting bandwidth is rather narrow, and it shows a drawback for enlarging
the PLL bandwidth under restrained tuning ranges.
Nevertheless, RC integrated oscillators often have a degraded phase noise performance and to
optimize the overall spectrum, it is necessary to work with low noise, large bandwidth PLLs.
The resulting behaviour of loops larger than the DCthreshold bandwidth is also a “bouncing
behaviour” during acquisition. It appears as a V
tune
transition that jumps up and down, and often
blocks some time in the limiting values, before it attains lock.
Thus the acquisition period may be longer than for a slower filter that would not block so often
in the tuning range limits.
So far we treated the DC tuning range only as a given interval related to the VCO frequency
range and sensibility. Once we recognize the need to work with “bouncing” loops, we should
verify the design limitations connected to the tuning range, and the behaviour of input and output
blocks around V
tune
, for the extreme values of the reachable range.
LCoscillators are usually limited by the varicap sensitivity curve, presenting a degressive K
vco
for an increasing V
tune
. RCoscillators will depend on the control parameter, and the interface
block between V
tune
and the control parameter.
In a passive filter, V
tune
is also the charge pump output voltage, thus restricting the DC
functioning range because of the output transistor saturation. In an active filter the charge pump
limitation is replaced by the loop amplifier limitation. Generally, for amplifiers with an open
collector output, there is only a minimum V
tune
, corresponding to the output transistor saturation.
The combination of the VCO and the charge pump (or the amplifier) DC functioning ranges
must be examined to avoid unstable situations.
For V
tune
values where the VCO input is no longer sensible (K
vco
=0), the oscillator will stay
clipped to the maximum or minimum achieved frequency, but its spectrum is no longer locked
by the PLL, since the open loop gain is null.
On the other hand, for V
tune
values where the charge pump may no longer deliver current but the
VCO is still sensitive, we may see an oscillating behaviour. For instance if V
tune
varies around
this charge pump limit value, the output current varies in consequence and we may produce a
sustainable oscillation. This problem should be avoided by defining suitable DC functioning
ranges for the charge pump output and the VCO input.
For the moment let us suppose that all V
tune
reachable values do not imply in an oscillating
behaviour, but for V
tune
out of the working range the oscillator stays clipped to a maximum or
minimum limit frequency.
Chapter 5 / Limitations of the LTI Phase Model 99
So, with more or less “bouncing” the oscillator is dragged towards lock, and now we need to
verify the influence of the PLL bandwidth inside the phase detection trapping zone.
5.3 Lock convergence approaches
In the previous section, time domain expressions for V
tune
sweep were derived, and compared to
the tunable range. In this section we use these expressions to verify the convergence of the phase
deviation sequence as the VCO reaches the programmed frequency.
The phase deviation sequence, as introduced in equation (5.2), represents the discrete values of
the phase difference for each comparison period.
( ) [ ]
lim lim
, ; : 1 ϕ ϕ ϕ ϕ + − ∈ ∆ ∆ ⋅ + < ≤ ⋅
n n cp cp
T n t T n
(5.6)
with π ϕ π 2
lim
< <
Let us consider the time diagram below showing the phase detector inputs and the charge pump
outputs for a VCO in acquisition mode.
Figure 5.6 Convergence towards lock: phase deviation sequence
0 T
d1
T
cp
(T
cp
–T
d2
)
t (s)
I
cp
In the
Ph.Detector
Ref. input
Var.input
Charge Pump
output current
V
tune
∆ϕ
1
∆ϕ
2
v
M
(0)
100 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
The oscillator initially with a phase lag, ∆ϕ
1
, is accelerated through the interval T
cp
, and in the
following interval presents an advance of ∆ϕ
2
.
The loop reaction is very abrupt; thus the situation concerns a fast, large bandwidth filter.
We fix an arbitrary time origin to simplify the time function expressions, and we represent only
the net current output for the charge pump.
The condition for a ∆ϕ
n
sequence converging to 0, or a PLL tending to lock, may be applied to
the phase deviations above, imposing:
1 2
ϕ ϕ ∆ < ∆
We define a stability limit for the PLL bandwidth as the maximum bandwidth for which this
condition is fulfilled.
The following subsections develop expressions for this maximum bandwidth in terms of the
VCO frequency and phase variations.
An initial condition is assumed for the VCO frequency in order to end up with an expression that
is an independent of this variable. The VCO is assumed at the programmed frequency, N.f
cp
at
t=0. Hence our phase deviation convergence is analyzed within a phase detector trapping zone.
Section 5.1 showed that phase detectors with a minimum linear range of tπ, are able to track any
frequency differences inside the tunable range. Furthermore, section 5.2 showed that fast filters
have a high V
tune
average deviation, which increases the probability of crossing the frequency
programmed value several times.
Therefore the initial condition proposed above is coherent with any synthesizer loop (with an
unlimited tracking range) close to lock or crossing the target frequency during V
tune
variations
around the target value.
5.3.1 Frequency approach
Referring to figure 5.6, the stability limit is reached for a PLL bandwidth that implies:
1 2
ϕ ϕ ∆ · ∆
which means that the main divider counted N cycles of the oscillator signal between T
d1
and (T
cp
–T
d2
).
Let us rename the limit delay, in phase and time, and relate it to the oscillator frequency, f
osc
:
,
`
.

⋅ · ∆
¹
¹
¹
'
¹
· ·
∆ · ∆ · ∆
cp
d
d d d
T
T
T T T
π ϕ
ϕ ϕ ϕ
2
2 1
1 2
and
( )
( )
d osc
d cp
T f
N
T T · ⋅ − 2 (5.7)
Expression (5.7) supposes that the oscillator frequency does not vary within the interval
( ) [ ]
d cp d
T T T − , , or in other words, that V
tune
is constant during the same interval.
Chapter 5 / Limitations of the LTI Phase Model 101
We call this approximation the frequency stability approach. Its inaccuracy depends on the loop
filter discharge during the interval where the charge pump is off.
The discharge would decrease V
tune
, decrease f
osc
, and consequently increase the maximum
stable PLL bandwidth. Hence, the frequency approach is pessimistic about the maximum
bandwidth.
The amplitude of C
2
discharge increases accordingly to the PLL bandwidth, so a maximum
bandwidth boundary is quite concerned about the discharging influence.
It is easier to watch the oscillator changing frequency through its integral. So, a second approach
in phase cycles is discussed in section 5.3.2. The phase stability criteria is expressed in terms of
the oscillator phase, θ
osc
:
( ) ( ) π θ θ 2 ⋅ · − − N T T T
d osc d cp osc
(5.8)
Our initial condition for the VCO is expressed as: ( )
cp osc
f N f ⋅ · 0 (5.9)
It may be combined with expressions (5.3), for the filter pulse response, to obtain a time function
for the oscillator frequency:
( ) ( ) [ ] ( ) [ ]
( )
( )
¹
¹
¹
¹
¹
¹
¹
'
¹
− ≤ ≤
]
]
]
]
⋅
,
`
.

− + ⋅ ⋅ ⋅ + ⋅
≤ ≤
]
]
]
,
`
.

− + ⋅ ⋅ ⋅ + ⋅
·
∆ ⋅ + · − ⋅ + ·
− − −
−
d cp d
T
T t
T
T
z
d
cp vco cp
d
T
t
z
cp vco cp
osc
M vco osc M M vco osc osc
T T t T e e
T
T
R I K f N
T t e
T
t
R I K f N
t f
t v K f v t v K f t f
p
d
p
d
p
: 1
0 : 1
) ( 0 ) 0 ( ) ( 0
2 2
2
) (
1
1
1
1
(5.10)
iii
As a result the frequency stability criterion becomes:
( )
( )
]
]
]
]
,
`
.

− + ⋅ ⋅ ⋅ + ⋅ · ·
⋅ −
−
2
1
2
1
1
p
d
T
T
z
d
cp vco cp d osc
d cp
e
T
T
R I K f N T f
T T
N
It is convenient to define a time deviation, p, and make some substitutions to express the
criterion in terms of x, r
21
, α and p:
iii
Once again the expression of the discharging interval assumes a C
2
almost discharged at t=0; and in fact we
approach this condition in two cases:
• for fast filters with w
p2
comparable to 2π.f
cp
;
• and for close to lock condition, with T
d
tending to zero.
The phase deviation sequence towards lock is examined for large bandwidth filters, and for ∆ϕ
n
tending to zero, so
completely in accord with the supposition of a discharged C
2
.
102 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
5 . 0 0 ;
2
< <
∆
· ⋅ · · p T f
T
T
p
d cp
cp
d
π
ϕ
( )
( )
]
]
]
]
⋅ ⋅ − − +
,
`
.

⋅ ⋅ ⋅ ⋅ ⋅
,
`
.

+ ·
⋅ −
p x r p x
r
x
p
n
21
21
2 exp 1
2
2 1
2 1
1
π
π
π
α
α
or expressing this boundary as a function g
frap
, we find:
( ) 0 2 exp 1
2
2
1 2
2
g
21
21
frap
·
]
]
]
]
⋅ ⋅ − − +
,
`
.

⋅ ⋅ ⋅ ⋅ ⋅
,
`
.

+
−
· p x r p x
r
x
p
p
n
π
π
π
α
α
(5.11)
remembering:
[ ] 1 , 0 ;
f
) gain value (average R
gain) loop (open
I
;
1
T
cp
oln
n
n
oln
1
cp
2 oln
z1 oln 21
∈ ·
·
⋅
·
⋅
· ⋅ ·
x
f
x
w
N
K
T w
w r
vco
p
α
α
α
The value of x solving equation (5.11), is the limit bandwidth ratio for a given set of r
21
, p and α
values. We know that the loop is considered in lock for p close to 0. Hence we need to verify that
x tends to a finite, nonzero value for the limit p→0.
First we look for some physical understanding of g
frap
(limit function for the frequency
approach), reducing it to a two variable function, and plotting it in the space (p, x, z).
Figure 5.7 illustrates g
frap
for constant values of r
21
and α, and zooms around the valid ranges of
p and x:
[ ] [ ] 5 , 0 ; 0 ; 1 ; 0 ; ; 25
21
∈ ∈ · · p x r
n
α α
The surface g
frap
(p, x) is cut by the plane z=0, and we may observe that x tends to a finite value
(around 0.1) for p tending to 0. The influence of the other two variables, r
21
and α, is examined
in section 5.3.3, including a comparison of the frequency and phase approaches.
Chapter 5 / Limitations of the LTI Phase Model 103
Figure 5.7 Frequency approach convergence criterion
5.3.2 Phase approach
The phase criterion as presented in equation (5.8) may also be expressed as a function of p, x, r
21
and α. The calculation steps for the phase approach limit function, g
phap
, are indicated below.
We obtain a time function for the oscillator phase, integrating equation (5.10), and evaluate the
phase change during the spotted interval: [ T
d
, (T
cp
–T
d
) ].
( ) ( ) ( )
( )
¹
¹
¹
'
¹
¹
¹
¹
'
¹
∆ ⋅ + ⋅ − ⋅ ⋅ ⋅ + · −
∫
−
d cp
d
T T
T
M vco d cp cp d osc d cp osc
dt t v K T T f N T T T ) ( 2 2π θ θ (5.12)
Comparing (5.12) and (5.8) , gives the function below:
( ) ( )
( )
¹
¹
¹
'
¹
¹
¹
¹
'
¹
]
]
]
]
]
,
`
.

−
,
`
.

− − − + − ·
− −
,
`
.

−
1 1 2 2 2 2
2 2
2
2
1
1
p
d cp
p
d
T
T T
T
T
p d cp
z
d
cp vco d cp cp
e e T T T
T
T
R I K T T f N N π π
104 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Dividing by 2π.N , and using the same substitutions as for g
frap
, g
phap
becomes:
( ) ( ) ( ) [ ] ( ) ( ) [ ] { ¦ 0 2 1 2 exp 1 2 exp 1 2 1 2
1
2 g
21 21
2
21
phap
· − ⋅ − − ⋅ ⋅ − − + − ⋅
,
`
.

+ − · x p r px r p p x
r
p
n
π π π
α
α
(5.13)
A general idea of g
phap
(p, x, r
21
, α) is given by figure 5.8, showing g
phap
for fixed values of r
21
and α, and restricted ranges of x and p:
[ ] [ ] 5 . 0 ; 0 ; 1 ; 0 ; ; 25
21
∈ ∈ · · p x r
n
α α
The intersection with the plane, z=0, shows a finite valued x (around 0.25) as p tends to 0.
Figure 5.8 Phase approach convergence criterion
As expected, the limit bandwidth ratio for the phase approach is higher than for the frequency
approach. The difference accounts for the filter discharge during the interval where the charge
pump is off.
Hence, effectively the frequency approach is pessimistic, but the phase approach is a final
stability boundary. And in order to guarantee loop stability, including several variable
parameters, it is necessary to have a safety margin.
The following section contains comparative graphs between the two approaches, and graphs
showing the influence of the two variables fixed in figures 5.7 and 5.8, r
21
and α .
Chapter 5 / Limitations of the LTI Phase Model 105
5.3.3 Comparing the frequency and phase approaches
A better graphical insight of the stability boundary, shown in the tridimensional plots, is given
by figure 5.9. It illustrates the intersection lines between g
frap
, g
phap
and z=0.
We choose to inverse the bandwidth ratio and plot 1/x (f
cp
/f
oln
) values with respect to p
(normalized delay). Therefore the frequency approach indicates a maximum PLL open loop
bandwidth of approximately f
cp
/10 , and the phase approach of approximately f
cp
/4 .
Although the lock condition is achieved for p tending to zero, the limit of maximum bandwidth
has to satisfy all values of the p range to guarantee a converging phase deviation sequence. For
our case, this condition is naturally fulfilled since the stability curves present a minimum value
of x, or a maximum value of 1/x, as p tends to zero.
Figure 5.9 Comparing frequency and phase approaches
Before introducing the two missing variables, r
21
and α/α
n
, we may compare the expressions
g
frap
(p, x) and g
phap
(p, x) to get some insight into their differences.
We observe that g
phap
has a higher order than g
frap
, with respect to p, because of the time
integration. A reduced form, as a limited development, may be helpful to homogenize both
equations and simplify the comparison.
The first order limited developments with respect to p, around p=0 (lock point), is evaluated for
g
phap
and g
frap
.
106 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
( )
4 4 8 4 4 7 6
f
A
n
p
r
r
p x p
]
]
]
]
+ ⋅ ⋅
,
`
.

+ − ≈
→
21
21
2
0
frap
1
2 2 g π
α
α
(5.14)
( )
( ) [ ]
4 4 4 4 4 4 3 4 4 4 4 4 4 2 1
p
A
n
p
x
r x
r
p x p
]
]
]
]
− −
+ ⋅ ⋅
,
`
.

+ − ≈
→
π
π
π
α
α
2
2 exp 1
1
2 2 g
21
21
2
0
phap
(5.15)
In this form we verify that both functions are very similar, and the only differing term would be
equivalent to an approximation, in g
phap
, of the exponential by its first order series around x=0.
However for large bandwidth filters, x is not close to 0, and the difference between the linear and
the exponential terms is representing the filter discharge, whose time constant depends on x and
r
21
.
The sum terms, A
f
and A
p
, correspond to the voltage variations of C
1
and C
2
for current injection
intervals (T
d
) tending to zero. Capacitor C
1
variation is equally considered in both approaches,
and capacitor C
2
discharge is neglected in g
frap
. It is important to notice in (5.14), that for the
usual r
21
values (r
21
>>1), C
2
voltage variation is the dominant effect in ∆v
M
.
5.3.3.1 ZeroPole spacing ( r
21
)
Next we verify the influence of the filter zeropole spacing parameter, r
21
.
Figure 5.10 plots the limit bandwidth values (1/x) for a variable zeropole spacing and p equals
to and ε close to 0 (p=ε , ε = 10
12
).
We notice that for decreasing values of r
21
, the two limiting values (g
frap
=0 and g
phap
=0)
approach each other. This result is in accordance with equations (5.14) and (5.15), since the
differing term decreases as r
21
is reduced.
The limiting bandwidth variation with respect to r
21
, may be intuitively understood for the
frequency approach. In fact, reducing r
21
implies nearing f
z1
and f
p2
to f
oln
,i.e., for the same
bandwidth (f
oln
) and the gain value (α) C
1
is reduced and C
2
is increased.
Hence, for the same charge injection (Icp.T
d
), the voltage variation in V
tune
is decreased,
iv
and
the bandwidth limit value (f
oln
) increased.
In the phase approach it is harder to foresee a general idea of the sensibility to r
21
. This happens
because ∆v
M
is a function of both r
21
and x.
iv
Remembering that C
2
variation is dominant as p tends to zero.
Chapter 5 / Limitations of the LTI Phase Model 107
Figure 5.10 Convergence approaches X leadlag spacing r
21
5.3.3.2 Gain variation
Finally the gain variation influence is shown in figure 5.11. It is a plot of the limit bandwidth
with respect to a normalized gain variation (α/α
n
), for fixed p and r
21
values.
The plot is reproduced on two scales, loglinear, and loglog. In the first we can easily read the
limit 1/x values for typical gain variations.
For instance, the satellite tuner example discussed in section 3.5, has a gain range, α
max
/α
min
,
equal to 50 (normalized variation for r
21
= 25) ; centering this variation around α
n
in figure 5.11.a
implies a maximum bandwidth value around f
cp
/19 .
The plot on the loglog scale is superposed by two asymptotes in the form:
( )
1 2
10 log log
2 1
k k
x y k x k y ⋅ · + ⋅ · L
The asymptotes are indicated by the lines in ◊ and symbols.
The limit bandwidth for the frequency approach may be very accurately represented by such an
asymptote, with k
1
=0,5 . In fact k
1
and k
2
values could be directly estimated from equation
(5.14), making g
frap
equal to zero, and isolating 1/x as a function of α/α
n
and r
21
.
108 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
In expression (5.15) it is not easy to isolate x. However figure 5.11.b, for the phase approach,
shows that the graph can be approximated by two asymptotes. One around α/α
n
equal to one,
with k
1
=0.75, and another for high gains, in parallel to the frequency approach asymptote.
v
Figure 5.11 Convergence approaches X gain variation
Summarizing, this section (5.3) describes a lock convergence analysis to evaluate stability
boundaries for the maximum bandwidth ratio (f
oln
/f
cp
). The influence of the zeropole spacing,
and the gain variation are also examined.
The limiting bandwidth is discussed directly in terms of the center open loop bandwidth, f
oln
,
used in the loop filter calculations. Thus we should keep in mind that α variations are an implicit
manner of discussing open and closed loop variations around the center value.
In the case of oscillators that work with small tuning ranges (f
max
/ f
min
< 2), the oscillator
frequency can not vary as much as presented in figure 5.6.
In fact, the oscillator will mostly stay blocked at the limit V
tune
values, bouncing between the
low and high boundaries. It will only converge if there is a sequence of ∆ϕ
n
values small enough
to cause ∆v
M
inferior to the tuning range. So as the bandwidth approaches the limits discussed
above, such a small range oscillator will pass most of its acquisition period blocked in the low
and high V
tune
boundaries.
v
The second asymptote shows that very high gain ratios correspond to such a large ∆v
M
during injection, that the
discharge voltage delta is less and less significant.
fig. 5.11.a fig. 5.11.b
Chapter 5 / Limitations of the LTI Phase Model 109
The convergence criterion is issued from the acquisition mode as a condition to attain the lock
mode. In the previous chapters we discussed filter centering algorithms to optimize the output
spectrum in lock mode.
In order to combine these two treatments we need to include the effects of the bandwidth
limitation in the small signal model that is described in the frequency domain.
5.4 Discrete transfers for the PLL Phase Model
The PLL synthesizer is typically a hybrid system containing both analog and digital blocks. So
far we have replaced the digital blocks by their average behaviour with respect to the phase of
the input and output signals.
The accuracy of average behaviour models hold for loops with a control bandwidth largely
inferior to the sample frequency, i.e., the filtering is effective enough for all passing components
in order to smooth out the input power and show an output with changing rates proportional to
the control bandwidth, and not to the sample frequency.
The average model for the digital blocks, is a linear time invariable approximation, of their
discrete, time variable, functioning.
The linear representation of the analog blocks is also approximate because of the limited linear
functioning range. These linear range limitations were discussed in section 5.1.
So, this section continues our analysis of the LTI model limitations, examining the discrete, time
variable nature of the digital blocks.
5.4.1 The sampler
As the system bandwidth increases it is necessary to consider the limitations associated with a
finite sampling frequency. A first approach, pseudocontinuous, includes extra poles or delays in
the continuous linear model, representing the stability constraints of the discrete system.
vi
A
direct discrete approach, developing discrete time equations and the associated z transform
transfers, is also conceivable, but mainly applied in the context of fully digital PLLs (see
reference [Berg95]).
As a general rule, the following boundaries are suggested for the model choice, concerning the
system with a closed loop bandwidth, w
cl
, and the sampling frequency, w
s
:
• w
cl
< 20*w
s
: continuous model
• 20*w
s
≤ w
cl
< 10*w
s
: between the continuous and the pseudocontinuous model
• 10*w
s
≤ w
cl
< 2*w
s
: between the pseudocontinuous and the discrete model
This section develops a pseudocontinuous approach for the PLL phase model and compares it to
the stability boundaries found in section 5.3.
The basic architecture of the frequency synthesizer, as shown in figure 1.9, contains three digital
blocks: main divider, reference divider and phase detector.
vi
Reference [Craw94] details the pseudocontinuous approach, developing compensated transfer function for
different phase detector types.
110 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
The charge pump is certainly driven by a digital input, but its output is a continuous current,
better modeled as an analog signal.
The dividers are fully or partially programmable counters that transmit an overload signal every
counting cycle. The output of the dividers is in fact one input transition that is selected by the
count overload window and transmitted to the output. Therefore, the discrete model of the
counter is a sampler with a period equivalent to the output signal frequency.
The phase detector is another edge driven block, with two memory nodes registering two inputs,
and a delayed asynchronous reset. It drives two switchable current sources, transforming the time
difference, T
d
, of the two inputs, in a current injection T
d
wide.
The complete discrete representation of the phase detector should include the discontinuous
effects of both edge driven inputs. However, this would imply a nonconstant sampling period
and a rather complex modeling. A simplified representation takes the reference input as the
sampling frequency, and the phase detector output becomes a sampled phase deviation sequence
as depicted in expression (5.6).
vii
Figure 5.12 Discrete model for digital blocks
vii
The accuracy of the assumption of a synchronous resampling is limited to conditions close to lock, where the
output of the main divider has a period approaching T
cp
.
A constant sensitivity, K
ϕ
, is also assumed for the phase detector, limiting our model to the phase detection zone.
θ
xtal
(t)
Xosc
%R
θ
ref
(t)
∆ϕ(t)
θ
div
(t) θ
osc
(t)
T
cp
T
cp
T
cp
+

%N
Charge
Pump
θ
div
(n.T
cp
)
∆ϕ (n.T
cp
)
θ
ref
(n.T
cp
)
∆ϕ (n.T
cp
)
θ
ref
(t)
∆ϕ(t)
θ
div
(t)
T
cp
+

Charge
Pump
Chapter 5 / Limitations of the LTI Phase Model 111
The divider outputs are connected to the phase detector input, therefore, our discrete
representation would contain two samplers driving a third one, with all working at the same f
cp
frequency. In other words the reference and main divider outputs are coherently resampled by
the phase detector latches.
Coherent resampling does not modify a discrete variable, hence we may condense these three
samplers in the last one, within the phase detector block.
The discrete phase deviation ∆ϕ(n.T
cp
) is designated as ∆ϕ
n
, for short. The Laplace transform of
the discrete and continuous phase deviations are related by:
( ) ( )
∑ ∑
∞
·
∞
·
⋅ + ∆ ⋅ ·
,
`
.

+ ∆ ⋅ · ∆
0 0
1 2 1
n
cp
cp n cp cp
n
w n s
T T
n
s
T
s ϕ
π
ϕ ϕ (5.16)
for: ( ) ( ) { ¦ t L s ϕ ϕ ∆ · ∆
and ( ) ( ) ( )
∑
∞
·
⋅ − ⋅ ∆ · ⋅ ∆
0 n
cp cp n
T n t t T n δ ϕ ϕ (5.17)
The alias terms due to the sampling will be analyzed in chapter 7. For the moment we consider
the ∆ϕ portion due to the feedback signal, with the alias terms well outside the loop bandwidth.
In this case the sampled Laplace transform becomes:
( ) ( ) s
T
s
cp
n
ϕ ϕ ∆ ⋅ · ∆
1
5.4.2 The holder
The following step is to identify the DAC (digital to analog converter) nature of the charge
pump. In reality the output current, i(t), is a sequence of current pulses, with width, sign and
delay related to the phase deviation sequence.
Figure 5.13 Discrete phase detector input: ∆ϕ
n
i(t)
I
cp
n.T
cp
(n+1).T
cp
t (s)
I
cp
Charge Pump
output current
∆ϕ
n
.(T
cp
/2π) ∆ϕ
n+1
.(T
cp
/2π)
For:
∆ϕ
n
> 0
∆ϕ
n+1
< 0
112 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
For the frequency domain model we search I(s), the Laplace transform of i(t).
An exact representation of I(s) is quite difficult because the frequency content (amplitude, phase
and number of significant f
cp
harmonics needed to represent a period) depends on the pulse
width, i.e., the nonlinearity is a function of ∆ϕ
n
 .
In section 3.1, during the analysis of spurious rays, in the lock condition, we made a first
approximation about the leakage current frequency content. We supposed that it was mostly
concentrated in the 1
st
or fundamental harmonic.
This supposition allows a worst case evaluation of the reference breakthrough. Furthermore,
ignoring the higher f
cp
harmonics is justified by the fact that they are strongly attenuated in the
loop filter.
However this approximation contains no DC component, and thus is not suited to represent the
bandbase contents of i(t).
viii
Consequently, we looked for a second approximation that preserves the DC component and
simplifies the frequency content, to a fixed known envelope. In a periodic , locked context, this
envelope shapes a series of f
cp
harmonics.
Representing the charge pump as a ZOH (zero order holder) converter is equivalent to shaping
the pulse frequency content by a sinc envelope, with the first lobe node at f
cp
. Figure 5.14 shows
a truncated portion, over one period, of i(t), i
ZOH
(t), and the associated Fourier transform,
I
ZOH
(w).
Figure 5.14 Charge Pump DAC output
with:
( )
]
]
]
− ⋅
,
`
.

⋅ ⋅ ∆ ⋅ ·
2
exp
2
sinc
cp cp
cp n ZOH
T
jw
wT
T K w I ϕ
ϕ
(5.18)
viii
The baseband contents are present for every ∆ϕ
n
different to zero.
t (s)
I
cp
.(∆ϕ
n
/2π) = K
ϕ
. ∆ϕ
n
I
cp
. (∆ϕ
n
.T
cp
/2π )
n.T
cp
(n+1).T
cp
Fourier
Transform
t (s)
∆ϕ
I
cp
I
cp
. (∆ϕ
n
.T
cp
/2π
)
n.T
cp
( 1) T
∆ϕ
I
cp
I
cp
. (∆ϕ
n
.T
cp
/2π )
n.T
cp
(n+1).T
cp
i(t)
i
ZOH
(t)
 I
ZOH
(w) 
K
ϕ
.∆ϕ
n
.T
cp
3w
cp
2.w
cp
w
cp
w
cp
2w
cp
3w
cp
w
(rad/s)
Chapter 5 / Limitations of the LTI Phase Model 113
The charge pump transfer, for the ZOH equivalent output, is deduced from equations (5.17) and
(5.18):
with u(t) a step function defined as:
¹
'
¹
< ·
≥ ·
0 ; 0 ) (
0 ; 1 ) (
t t u
t t u
and G
sh
(s), the sample and hold transfer in the Laplace transform.
ix
We notice that G
ChPZOH
is independent of ∆ϕ
n
, which is not the case for the transfer function of
the actual i(t), pulse width modulated by ∆ϕ
n
.
x
The pseudocontinuous model is an extension of the bandbase, linear time invariable phase
model. It includes some characteristics of the loop discrete functioning, but it intends to stay as a
LTI system.
G
ChPZOH
is a linear transfer, but the only time invariable component is the DC one.
xi
In a periodic locked case, this reduction can be seen as the loop filter action, attenuating the
spectrum rays at f
cp
harmonics, and keeping only the DC ray.
Hence, the sinc shaped charge pump transfer is reduced to its DC term plus the delay:
( )
2
cp
T s
cp ZOH ChP
e T K s G
⋅ −
−
⋅ ⋅ ≅
ϕ
(5.19)
Equation (5.19) corresponds to a first order approximation of the ZOH. The delay term appears
in a Bode plot as a constant unitary magnitude, and a linear decreasing phase. Thus it mostly
affects the phase margin parameter. For example at f equals f
cp
/10 it reduces the phase margin of
π/10 radians, or 18° .
ix
We may verify the correspondence of G
ChPZOH
(s) and I
ZOH
(w), replacing s by jw in the G
sh
(s):
( )
,
`
.

⋅ ⋅ ⋅ ·
,
`
.

⋅
⋅ ⋅ ÷ ÷ ÷ → ÷
·
−
⋅ ·
,
`
.

⋅ −
,
`
.

⋅ −
,
`
.

⋅ −
,
`
.

⋅ +
,
`
.

⋅ −
2
sinc
2
sin
2
2 2
2 2
2 cp
cp
T
jw
cp
T
jw
T
s
T
s
T
s
sh
T
w T e
w
T
w
e
jw s
s
e e
e s G
cp cp
cp cp
cp
x
For i(t) output in the form:
( )
∑
∞
· ]
]
]
]
,
`
.
 ⋅ ∆
− − − − ⋅ ·
0
2
) (
n
cp n
cp cp cp
T
T n t u nT t u I t i
π
ϕ
the associated transfer G
ChP
is:
( )
]
]
]
]
]
−
⋅
∆
·
⋅ ∆
⋅ −
s
e
I
s G
cp n
T
s
n
cp
ChP
π
ϕ
ϕ
2
1
xi
Later on, in section 6.3, a more complete transfer, time variable, is discussed for small signal analysis.
( ) ( )
∑
∞
·
∆ ⋅ − · ∆
0 n
cp n
t nT t ϕ δ ϕ
( ) ( ) s G K
s
e
K s G
sh
T s
ZOH ChP
cp
⋅ ·
]
]
]
]
−
⋅ ·
⋅ −
− ϕ ϕ
1
Charge
Pump
( ) ( ) ( ) ( ) [ ]
cp cp n ZOH
T n t u nT t u K t i 1 + − − − ⋅ ⋅ ∆ ·
ϕ
ϕ
114 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
5.4.3 Continuous equivalent with transmission delay
We may recognize that other pulse approximations for i(t) would present similar LTI transfers.
In figure 5.15 we name i
pw
(t) a generic pulse function of width T
w
and same DC content as i(t).
The related Fourier transform, I
pw
(w), and charge pump transfer, G
ChPpw
(s), are also indicated.
Figure 5.15 Continuous equivalent with transmission delay
( )
2
w
T s
w
w
cp
pw ChP
e T
T
T
K s G
⋅ −
−
⋅ ⋅ ⋅ ≅
ϕ
Among the possible pulse approximations, the ZOH presents the largest delay. And since the
time delay is the limiting stability constraint introduced by the pseudocontinuous model, we
continue this analysis with the ZOH approach.
Next we search convenient polynomial representations for the time delay. Two simple
possibilities are:
• real pole at f=f
cp
/2 (similar to first order filtering around the Nyquist frequency, f
c
/2):
easy implementation, but not accurate in magnitude and phase, mainly for frequencies
nearing f
cp
/2. At f
cp
/2 it represents a phase decrease of 45°, comparable to a time delay of
T
cp
/4. This time delay is associated to a charge pump transfer with width T
w
equals to T
cp
/2.
• Pade polynomials: composed of pairs of zero and poles, symmetrically placed around the
imaginary axis of the Splane. The order, n, indicates the order of the numerator and
denominator polynomials. The magnitude frequency response is unitary everywhere, and the
phase decreases up to n*(180°) .
The phase decreases almost linearly up to n*(90°) . Therefore the order of the polynomial
must be chosen comparing the maximum loop bandwidth to(w*T
delay
) .
A numerical example is presented below. We examine the open and closed loop transfers for a
filter with r
21
equals to 25, and a normalized gain variation range (2.r
21
).
∆ϕ
n
. K
ϕ
. T
cp
/T
w1
Τ
w1
K
ϕ
.∆ϕ
n
.T
cp
3w
cp
2w
cp
w
cp
w
cp
2w
cp
3w
cp
w
(rad/s)
i
pw
(t)  I
pw
(w) 
t (s)
Τ
w2
n.T
cp
( 1) T
n.T
cp
(n+1).T
cp
Chapter 5 / Limitations of the LTI Phase Model 115
The zeropole spacing parameter (r
21
) is equal to the evaluation of figure 5.11, so that we can
compare the results of the delay approach and the ∆ϕ
n
convergence approach.
Figure 5.16 shows the open loop phase plot, and the closed loop step response for a continuous
model with a transmission delay of T
cp
/2 , modeled by a 2
nd
order Pade polynomial.
The continuous nominal loop is a 3
rd
order one, with a 2
nd
order loop filter. The numerical
parameters used in the graphs, are listed below:
r
21
= 25; w
oln
= 10 rad/s (symbolical value, not related to applications)
w
cp
= 21.1 * w
oln
= 211 rad/s
Figure 5.16 Frequency and Time response for the continuous + delay model
The phase response pictures three curves corresponding to the pure time delay, the nominal
continuous transfer and the continuous plus delay model.
Dasheddotted lines indicate the open loop crossing frequencies (f
ol
) for the normalized gain
variation. Over the 180° line there are symbols marking: w
z1
(o), w
oln
( ). y
p2
(x) and
w
cp
(◊).
The sample frequency, w
cp
, was chosen as the limit value for which the phase margin
corresponding to the maximum normalized gain (α
max
) equals zero. Therefore we may compare
the ratio w
cp
/w
oln
to the limit 1/x values in figure 5.11.
fig. 5.16.a fig. 5.16.b
nominal + delay
c
b
a
116 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
( ) ( ) ( ) ( )
ln 2 21 max
5 07 , 7 2
max
o p ol n n
w PhM w PhM w PhM r ⋅ · · ⋅ · ⋅ ⋅ ·
·α α
α α α K
1 , 21
19 ~
1
ln ln
L
x f
f
w
w
o
cp
o
cp
· ·
So in spite of all reductive approximations made in the delay analysis, it is still comparable to the
time convergence methods.
The step response is calculated for a frequency change equal to w
osc
/N, and the signal plotted is
proportional to either the oscillator angular frequency or the filter voltage output.
( ) ( )
2
1
1
or
N
N
N
s B
f
N
s B
N
w
V
N
K
ref
osc
tune
o
⋅ ∆ ⋅ ↔ · ⋅
The three curves correspond to the following gain values:
a: α·α
min
or w
ol
= w
z1
= 2 rad/s = 2π.(0.32 Hz)
b: α·α
n
or w
ol
= w
oln
= 10 rad/s = 2π.(1.59 Hz)
c: α≈α
max
/2 or w
ol
≈ 3.w
oln
= 30 rad/s = 2π.(4.7 Hz)
Curve c corresponds to the maximum gain value with a PhM≥30° for the continuous plus delay
model. In the phase plot, the corresponding f
ol
is also indicated through the dasheddotted lines.
The continuous plus delay model is mostly an approximation for locked mode simulations, due
to its linear character. Nevertheless we should be aware of the limitations to know the tendency
of the inaccuracy present in the simulations results.
In fact, during the acquisition mode there is not really a constant sampling frequency, but f
cp
is
the slowest one possible, so the most critical.
The phase deviation is also not constant during each comparison interval, and this may interfere
in the width of the current injection for cases where the oscillator is lagging the reference. Again
when we use the maximum delay (T
cp
/2) we are taking the worst case.
Therefore the continuous plus delay model, with a T
cp
/2 delay, is a pessimistic estimate of the
lock and acquisition mode, and it may be used to evaluate stability boundaries due to enlarging
feedback bandwidths. The pessimistic error is not so large, as we see through the comparison
with the phase convergence method, and it constitutes a small addition to the safety margin.
Another application of this delayed model appears in spectrum optimizations, where the phase
margin loss may affect the peaking. For this typical locked mode simulations, the T
cp
/2 delay is
too pessimistic, and the results will not fit measured situations. A compromise fitting
measurements is found for a delayed model with a T
cp
/4 delay.
: for the phase convergence method
: for the continuous + worst delay method
Chapter 5 / Limitations of the LTI Phase Model 117
This chapter dealt with nonlinear aspects of the PLL functioning. These aspects are bounded to
large bandwidth loops, and they impose maximum limits for f
cp
and f
ol
.
The first issue (f
cp
) appears in multiloop contexts and it was analyzed through the minimum
phase detection range assuring an unlimited frequency tracking behaviour.
The second (f
ol
) appears in general loop structures containing discrete behavioural elements.
Most of the PLL discrete models are issued from pure digital loops analysis, where descriptions
in Z transform are easily determined.
In our mixed discretecontinuous context, two characteristics are especially difficult to include in
a Ztransform representation: a DAC not strictly linear and a varying sampling frequency.
Thus, we preferred to start with time domain models, and, later search for a simplified frequency
domain representation.
The simplified frequency model is in fact a continuous one, with an additional time delay.
Both time and frequency models were evaluated and discussed with respect to the loop
parameters presented in the previous chapters, (zeropole spacing, gain variation, …)
118 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Chapter 6 / Phase Noise: theoretical to practical approach 119
Contents:
6. Phase Noise: theoretical to practical approach 119
6.1. Electrical Noise: random source representation & measurements....................................................... 120
6.1.1. Electrical noise as a random process ........................................................................................... 121
6.1.2. Measuring Phase Noise ............................................................................................................... 123
6.2. Phase Noise Notations .......................................................................................................................... 125
6.2.1. Interchanging Modulation Types................................................................................................. 125
6.2.1.1. Angular modulation................................................................................................................ 127
6.2.2. Phasor Notations.......................................................................................................................... 128
6.2.3. Slope approach ............................................................................................................................ 133
6.3. Large Signal Linearization ................................................................................................................... 135
6.3.1. Time and Frequency representation............................................................................................. 135
6.3.2. Linear Time Variable transfer ..................................................................................................... 136
Figures:
Figure 6.1 Spectrum Analyzer Output ........................................................................................................ 124
Figure 6.2 FM & PM carriers.................................................................................................................... 128
Figure 6.3 SSB superposed noise: AM + PM decomposition (phasor)...................................................... 129
Figure 6.4 Superposed Noise: AM + PM decomposition (spectrum)......................................................... 130
Figure 6.5 Phase modulated carrier by DSB superposed noise ................................................................. 131
Figure 6.6 Phase deviation from DSB sidebands ....................................................................................... 132
Figure 6.7 Slope approach: voltage & time deviations............................................................................... 133
Figure 6.8 Periodic transfer determined by a large signal ......................................................................... 136
Figure 6.9 Large Signal Transfer: ideal and hyperbolictangent limitations............................................ 138
Tables:
Table 61 Phase Modulated Carrier .......................................................................................................... 126
Table 62 L(f
offset
) from modulated and superposed noise ........................................................................ 132
6 Phase Noise: theoretical to practical approach
Phase noise is an important parameter in the performance of frequency synthesizers. Low noise
design needs to consider the mechanisms originating phase deviations in the output carrier; and
relate them to the noise sources that are present in the circuit.
The analysis starts with basic aspects on random noise representation and measurement, and is
followed by a discussion on different notations for phase noise. Finally, we consider the transfer
function of stages that work in a periodic, nonlinear mode.
120 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Phase Noise is a convenient parameter to quantify unwanted phase variation in a periodic signal.
Phase variation can be caused by a linear phenomenon such as signal addition and also by non
linear phenomena such as angular modulation.
In the PLL synthesizer we consider two sources of periodic signals, which are disturbed by phase
noise: the reference oscillator and the voltage controlled oscillator. The disturbances are either
intrinsic to the periodic sources, or are accumulated as their outputs propagate through the PLL
blocks.
The power that generates phase variations can come from random or deterministic sources. The
representation of electrical random noise is shortly discussed, introducing the notation in the
frequency domain, for stationary and cyclostationary sources. The deterministic sources are also
described in the frequency domain, which allows us to develop a common treatment for both
types of disturbance.
Phase noise is represented in many different notations, which are chosen with respect to the
origin of the phase deviation, or to the measurement tools. We discuss some notations that are
based on: the equivalence amongst different types of modulation, the addition of signals
represented by phasors, and the time deviation in switching stages.
The last one is very significant to describe the noise added by the logical blocks of the PLL
(dividers and phase detector). This description is further developed to take into account the
nonlinear and periodic behaviour of these blocks.
In chapter 7 we relate the notations for phase noise and the transfer functions of the preceding
chapters. The noise performance of the synthesizer is investigated in a topdown approach, from
behavioural to circuit level descriptions.
6.1 Electrical Noise: random source representation & measurements
The denomination noise is given to any power signal disturbing the data signal (which contains
the transmitted data or information). Noise sources can be internal to the integrated circuit, or
external, from the application environment.
We consider two types of noise: interference and stochastic electrical noise.
The first is associated to deterministic signals polluting the output carrier. They are generated by
the operation of different parts of the circuit and are transmitted by parasitic coupling.
The second refers to the random movement of electrons, implying fluctuations in voltage and
current signals. They are thermal, shot, flicker and other types of random noise.
We mentioned two sources of interference in chapters 3 and 4: the reference breakthrough and
the deterministic disturbances found in the supplies of the loopamplifier.
On the other hand, N
PLL
and v
nvco
(defined in chapter 3), and the shot and thermal noise of the
amplifier and the loopfilter components (discussed in chapter 4), are random noise sources.
Furthermore we consider that they are stationary noise sources that can be described by their
power spectrum density.
Chapter 6 / Phase Noise: theoretical to practical approach 121
6.1.1 Electrical noise as a random process
Electrical noise arises from current and voltage fluctuations in the circuit. The mechanisms
originating these fluctuations are related to thermal agitation, and to variations in the current
flow of electronic devices. These fluctuations vary randomly, and are described as stochastic or
random processes.
The random characteristic defines a variable or a process that is not predictable before its
occurrence, but presents defined statistical properties.
Random processes are defined as an ensemble of time functions whose statistical properties are
described by a common probability rule. Each time function is a sample of the random process
sample space. The statistical description of the process is contained in the probability density
function. This function describes the probabilistic distribution of the values of the sample
functions, when they are observed at a given time instant.
When the probability density function is independent of the observation instant, the random
process is said to be stationary. An important property is derived from the stationary condition:
ergodicity. This is attributed to processes where the statistical properties of the ensemble can be
estimated by time averages of individual sample functions of the process.
Ergodicity is a very important property for the measurement of stochastic processes, since these
measurements are based on the observation of a sample function during a time interval.
In practice, stochastic processes are not evaluated by a probability density function (which is not
directly measurable) but more frequently by their first and second moments: mean value and
autocorrelation, respectively. A stationary process X(t) presents the following mean and
autocorrelation:
mean: [ ] ) (t X m
X
Ε ·
autocorrelation: ( ) ( ) ( ) [ ] τ τ − ⋅ Ε · t X t X
X
R
where E is the expectation operator, and τ is a time delay. The meansquare value equals the
autocorrelation for a zero time delay:
meansquare: ( ) ( ) [ ] t X
X
2
0 R Ε ·
A process that presents: a constant average, an autocorrelation which is independent of shifts in
the time origin, and a finite value for the autocorrelation at the time origin, is said to be wide
sense stationary (WSS). They do not present all the characteristics of a stationary process, but
include the most significant, as described by the 1
st
and 2
nd
moments.
Usually for the measurement intervals that we are interested in
i
, the electrical noise sources may
be modeled as WSS processes with a Gaussian distribution of amplitude.
The Gaussian distribution is nicely adapted to describe physical phenomena depending on many
independent random variables. This is related to the central limit theorem, which affirms that the
sum of many independent random variables with defined 1
st
and 2
nd
moments, tends to present a
Gaussian distribution as the number of variables increases without limit.
Consider that the movement of each electron is described by an average component plus a
random one.
ii
The sum of the different paths of the electrons in a conductor approaches a
i
Measurements in the time and frequency domain observe a signal during a time interval that is large enough to
average over several periods of the noise components being measured, but still small enough to consider the process
as stationary.
122 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Gaussian random variable. Thermal and shot noise present a Gaussian amplitude distribution and
a zero mean value. The thermal noise of a resistor of R ohms has the following mean square
value expressed in volts:
( ) [ ]
2 2 2
2 volts f R kT t V V
TN n
∆ ⋅ · Ε · (6.1)
where ∆f indicates the bandwidth over which the noise voltage is measured. In equation (6.1) the
multiplying factor 2 instead of 4 (as in equation (4.7) of chapter 4) refers to a double sided
frequency representation, for a spectrum with positive and negative frequencies.
The Fourier transform of the autocorrelation function describes the random process in the
frequency domain. It is the power spectral density (PSD) of the process, defined as:
( ) ( ) ( ) τ τ π τ d f j R f S
X X
2 exp − ⋅ ·
∫
∞
∞ −
or inversely
( ) ( ) ( ) df f j f S R
X X
τ π τ 2 exp
∫
∞
∞ −
⋅ ·
We observe that the integral of the power spectral density over the whole frequency range,
equals R
X
(0), which is the total power or the meansquare value. When considering a voltage or
current noise density, the integral equals the total power for a unitary impedance.
The power spectrum density of a WSS random process has similar properties to the PSD of
deterministic signals. The output of a block with a lineartimeinvariable transfer function H(f)
for a noise input described by S
X
(f) becomes:
( ) ( ) ( ) f S f H f S
X Y
⋅ ·
2
A process that presents a constant power spectrum density for all frequencies is called white.
White noise is a practical representation for band limited systems where the noise spectrum is
constant over the relevant part of the frequency range. White noise with unlimited bandwidth
does not exist because it would represent an infinite power.
Ideal white noise corresponds to an autocorrelation function which is an impulse at τ=0 , and
equals zero everywhere else. It means that any two samples from different time instants are
completely uncorrelated. Bandlimited white noise presents an autocorrelation function shaped
as a sinc curve. The width of the lobes of the sinc are inversely proportional to the filtering
bandwidth.
Shot and thermal noise are approximated by white Gaussian noise. These approximations hold
for limiting bandwidths to the order of 10
12
Hz, which is largely above the limit of our working
frequencies.
Flicker noise is commonly represented by a white Gaussian noise which is shaped by a 1/f filter.
This representation is limited to a minimum value of frequency, to avoid an infinite power
density as f approaches 0.
Electrical noise contributions whose amplitude varies with respect to a periodic deterministic
signal, are called cyclostationary. They are represented by the product of a normalized stationary
ii
In the case of thermal noise the average component equals zero, and in the case of shot noise the average
component equals the net current flowing in the device.
Chapter 6 / Phase Noise: theoretical to practical approach 123
process with a periodic large signal; or in other words, by a random process which is amplitude
modulated. The shot noise of a transistor driven by a periodic input is a cyclostationary noise.
The time average of the noise power of a cyclostationary noise is proportional to the rms value of
the periodic signal which modulates the random process.
For example let us consider the shot noise of a transistor driven by a sinousoidal input at
frequency f
c
:
( ) ( ) ( ) t X t i q t I
shot
⋅ ⋅ · (6.2)
iii
where X(t) is the normalized random process, with a white unitary PSD which is limited by a
physical bandwidth defined by the circuit. i(t) is the deterministic current signal that results from
the sinusoidal input, for example:
( ) ( ) [ ] Θ + + ⋅ · t f
I
t i
c
t
π 2 cos 1
2
Θ is a random phase uniformly distributed in the range [0 , 2π]. It indicates that X(t) and i(t) are
not related to a common time origin.
Part of the power of this shot noise is frequency translated around tf
c
. Other examples of
frequency translation of noise appear as we investigate time variable transfer functions. These
transfers are discussed in section 6.3.
The representation of random noise by their PSD allows us to use a common small signal
treatment for both deterministic and random signals. The random signal is considered as the
superposition of uncorrelated portions of narrow band signals. This supposition was first
mentioned in chapter 3 when we considered a single tone contribution of v
nvco
.
We continue this introduction considering the measurement of noise in the time and frequency
domain.
6.1.2 Measuring Phase Noise
Phase noise is a magnitude measuring phase deviations in a carrier. Section 6.2 discusses
different mechanisms that convert noise power in amplitude and phase deviations. In the output
of the VCO we find mainly phase deviations. This is due to the frequency modulating
characteristic of the input of the VCO, and also due to amplitude limitations that occur in the
intermediate and output stages of the VCO.
Phase noise is measured by different methods which evaluate the performance of the carrier in
the time and frequency domains.
In our context the spectrum analysis is the most current method.
The spectrum analyzer measures the power present in a certain band of frequency, by sweeping
an analysis window through a specified range of frequency. It is basically composed of a
frequency conversion block, which is followed by a filter with a variable bandwidth and by a
power meter. The analysis window corresponds to the filter bandwidth and is called resolution
bandwidth (RBW). Figure 6.1 represents an LO spectrum measured with two different resolution
bandwidths, RBW
1
and RBW
2
.
iii
In equation (6.2) the amplitude of the shot noise also refers to a double sided spectrum with positive and negative
frequencies.
124 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Figure 6.1 Spectrum Analyzer Output
In figure 6.1 the sideband rays at frequency offsets of tf
m
are caused by a deterministic noise
component. This noise has a spectrum component at frequency f
m
which modulates the carrier
output. The power of the modulated rays is concentrated in very narrow bandwidths around f
osc
t
f
m
iv
, which are considerably smaller than the values of the RBW. So the power of these
sidebands is not affected by the width of the RBW. The power ratio between these sidebands and
the carrier is expressed in dBc.
The parts of the sidebands that are caused by random noise (inloop contribution from N
PLL
and
outofloop contribution from v
nvco
) have a power level that varies with the width of the RBW.
This is due to the spreadout characteristic of the power spectrum density of these noise
contributions.
Let us consider a white random noise in the output with a power spectral density N
o
in W/Hz.
The power due to this contribution as the analysis window sweeps the frequency range equals:
N
o
.RBW. The power ratio between the sidebands due to random noise and the carrier is often
expressed in dBc/Hz. This unit is used to normalize the power level to a 1Hz bandwidth. The
ratio SSB noise / carrier when expressed in dBc/Hz, corresponds to L
dB
(f
offset
) which was defined
in chapter 3 (equation (3.4) ).
The phase noise performance can also be measured by a time parameter: the time jitter. This
expresses the variations of the period of the carrier. There are two different methods. One
measures the variations of the period when compared to a reference oscillator. The result is
called timedeviation jitter. The second calculates the dispersion of the value of the period with
respect to its own average. The result is called timeinterval jitter. In both types of measurement
there are several parameters that strongly influence the value of the jitter measured. For instance
the time step and the measurement interval determine the maximum and minimum frequencies of
the noise components that are taken into account.
Reference [Nord97] discusses the techniques of time jitter measurement and the parameters that
influence the results. It also shows that timedeviation jitter is related to the phase deviation in
the carrier, and that timeinterval jitter is related to the frequency deviation.
The relationships amongst phase, frequency and time deviations are discussed in the following
section.
iv
Ideally the modulating rays are represented by impulses at f
osc
t f
m
. However the modulating signal is limited in
time and its spectrum has a finite width.
Spurious
deterministic signal
f
osc
f
m
f
osc
f
osc
+f
m
,
`
.

⋅
2
1
log 10
RBW
RBW
Chapter 6 / Phase Noise: theoretical to practical approach 125
6.2 Phase Noise Notations
The description of phase noise varies with respect to the functionality of the blocks to which it
refers. In oscillators the phase noise is often quantified by phase or frequency magnitudes, and in
logical blocks it is quantified by time magnitudes.
In every node of the circuit there is some noise power being added to the data signal. In
particular at the input node of the VCO, the voltage noise is converted into phase deviation by
frequency modulation. In other nodes of the circuit the added noise power causes both amplitude
and phase deviations of the signal. Phase noise can be caused by angular modulation of noise
power, or by addition of noise power to the signal.
In this section we detail these two mechanisms of the generation of phase noise, that we call
modulated and superposed noise. We start with the angular modulation, looking at the
relationships amongst phase, frequency and time modulations. We continue with the distinction
of phase and amplitude deviations caused by an added noise power. Finally we look at the effect
of amplitude limitation on the transmission of signals corrupted by noise.
6.2.1 Interchanging Modulation Types
The phase deviation of a carrier may also be expressed as frequency and time deviations (see
reference [Nord97]). Let us consider a sinousoidal carrier v
c
(t), and the time functions ∆ϕ(t),
∆f(t) and ∆t(t) which modulate the carrier. It follows that:
unmodulated carrier: ( ) v t A f t
c c c
( ) sin · ⋅ ⋅ ⋅ 2π
phase modulated carrier: ( ) v t A f t t
PMc c c
( ) sin ( ) · ⋅ ⋅ ⋅ + 2π ∆ϕ
frequency modulated carrier: ( )
[ ]
v t A f f t t
FMc c c
( ) sin ( ) · ⋅ ⋅ + ⋅ + 2π µ ∆
∆ϕ
time modulated carrier: ( )
[ ]
v t A f t t t
TMc c c
( ) sin ( ) · ⋅ ⋅ + 2π ∆
The three modulated signals are equivalent to each other if:
∆ ∆ϕ ∆
∆ϕ
∆ϕ
f t
t
t
t
t
t
t t t
t
f
c
( )
( )
; ( )
( )
; ( )
( )
· ⋅ · − ⋅ ·
1
2 2 π
∂∆ϕ
∂
µ
∂∆ϕ
∂ π
We may also express v
c
(t) and the modulating functions ∆ϕ(t), ∆f(t) and ∆t(t) with respect to
their power spectrum densities. They become:
carrier: v
c
(t) …….. ) ( f S
c
phase deviation: ∆ϕ(t) …….. ) ( f S
ϕ ∆
126 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
frequency deviation: ∆f(t) …….. ) ( ) (
2
2
) (
2
2
f S f f S
f j
f S
f ϕ ϕ
π
π
∆ ∆ ∆
⋅ − · ⋅
]
]
]
·
time deviation: ∆t(t) …….. ) (
2
1
) (
2
f S
f
f S
c
t ϕ
π
∆ ∆
⋅
]
]
]
·
Therefore the power of the total frequency or time deviations can be evaluated using the spectral
density of the phase deviation. The power of the deviations is the integral of the PSD over a
determined frequency interval.
Let us consider that ∆ϕ(t) is a random phase deviation, with a PSD which is a bandlimited white
noise. The spectra of the carrier and the modulating noise are sketched in the table below, using
single and double sided representations of the frequency axis.
Spectra
Signal & PSD
Single Sided
(only positive frequencies)
Double Sided
(pos. and neg. frequencies)
carrier:
S
c
(f) [V
2
/Hz]
[ ] ) ( ) (
4
) (
2
c c
c
c
f f f f
A
f S + + − ⋅ · δ δ
phase deviation:
S
∆ϕ
(f) [rad
2
/Hz]
¹
¹
¹
¹
¹
'
¹
· ∧ >
≤
·
∆
0 ; 0
;
2
) (
f bw f
bw f
N
f S
O
ϕ
phase modulated carrier:
S
osc
(f) [V
2
/Hz]
( ) ( ) { ¦
c c
c
c osc
f f S f f S
A
f S f S
+ + − ⋅ +
+ ≈
∆ ∆ ϕ ϕ
4
...
... ) ( ) (
2
Table 61 Phase Modulated Carrier
The spectra of the phase modulated signal was drawn considering that the peak phase deviation
is small (max{∆ϕ(t)}<<1 rad). The following subsection details the expressions of the angular
modulation, and the FM narrow bandwidth approximation.
fc f
2
2
c
A
Sc(f)
fc fc f
4
2
c
A
Sc(f)
No
bwn f
S∆ϕ(f)

No/2
bwn bwn f
Pϕ(f)
8
2
o c
N A ⋅
fcbwn fc fc
4
2
c
A
Sosc(f)
4
2
o c
N A ⋅
2
2
c
A
fcbwn fc
Sosc(f)
Chapter 6 / Phase Noise: theoretical to practical approach 127
6.2.1.1 Angular modulation
The output spectrum of the PLL synthesizer presents an inloop zone that is phase modulated by
the PLL noise (N
PLL
), and an outofloop zone that is frequency modulated by the intrinsic noise
of the VCO and by the loop filter noise.
PM and FM are two types of angular modulation. The example of a single tone modulation is
detailed below. Furthermore noise contributions that are represented by a power density, may be
seen as a superposition of single tone modulations.
Let us consider the same carrier v
c
(t) defined above, and a single modulating tone v
m
(t). The
phase modulated carrier is named v
PM
(t), and equals:
( ) [ ]
m m m p c c PM
t f A K t f A t v ϕ π π + ⋅ ⋅ + ⋅ · 2 sin 2 sin ) ( (6.3)
where
( )
m m m m
t f A t v ϕ π + ⋅ ⋅ ⋅ · 2 sin ) (
and K
p
is the phase deviation sensibility in rad/V. We may also define ∆ϕ
p
the peak phase
deviation and rewrite v
PM
as:
( ) ( ) [ ] ( ) ( ) [ ] { ¦
m m p c m m p c c PM
t f t f t f t f A t v ϕ π ϕ π ϕ π ϕ π + ⋅ ∆ ⋅ + + ⋅ ∆ ⋅ ⋅ · 2 sin sin 2 cos 2 sin cos 2 sin ) (
and
m p p
A K ⋅ · ∆ϕ
or ( ) ( ) [ ]
m m c
n
p n c PM
t f n t f J A t v ϕ π ϕ + + ⋅ ∆ ⋅ ·
∑
+∞
−∞ ·
2 sin ) (
where the coefficients J
n
(β) are the values of the Bessel function of the n
th
order with argument
β. The value of these coefficients for β << 1 rad , approach:
( ) ( ) ( ) J J J for n and n N
n 0 1
1
2
0 1 β β
β
β ≈ ≈ ≈ > ∈ ; ; ,
In this case of small phase deviations v
PM
is simplified to:
( ) ( ) [ ] ( ) [ ]
¹
'
¹
¹
'
¹
− − ⋅
∆
− + + ⋅
∆
+ ⋅ ·
m m c
p
m m c
p
c c PM
t f f t f f t f A t v ϕ π
ϕ
ϕ π
ϕ
π 2 sin
2
2 sin
2
2 sin ) (
(6.4)
where the SSB ratio noise/carrier equals:
( )
2
:
2
log 20
2
log 20
p
rms
rms
p
m dB
f L
ϕ
ϕ
ϕ
ϕ ∆
· ∆
,
`
.
 ∆
⋅ ·
,
`
.
 ∆
⋅ ·
Next we consider a single tone frequency modulated carrier v
FM
(t) , in the form:
[ ] ( )
]
]
]
+ ⋅
⋅
⋅ ⋅
+ ⋅ · + ⋅ ·
∫
m m
m
m f
c c mf c c FM
t f
f
A K
t f A dt t v t f A t v ϕ π
π
π
π π π 2 sin
2
2
2 sin ) ( 2 2 sin ) (
(6.5)
128 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
where
v
( )
m m m mf
t f A (t) v ϕ + ⋅ ⋅ ⋅ · 2 cos
and K
f
is the frequency deviation sensibility in Hz/V. If we define the peak phase deviation as
m
p
m
mf f
p
f
f
f
A K ∆
·
⋅
· ∆ϕ
equation (6.5) becomes equivalent to equation (6.3) for the phase modulated carrier.
An important difference between frequency and phase modulation is that the phase deviation
caused by FM has an amplitude which depends on the frequency of the modulating signal. Figure
6.2 shows these differences in the spectrum of a carrier that is modulated by a bandlimited white
noise.
Figure 6.2 FM & PM carriers
In the frequency modulated carrier the phase deviation is proportional to 1/f
m
. Therefore for f
m
tending to zero, the approximation of small phase deviations is no longer valid. In figure 6.2 this
limit is indicated by the dotted lines and by the reduction of the power at tf
c
( J
0
(∆ϕ
p
)<1).
6.2.2 Phasor Notations
In this section we consider the phase and amplitude deviations caused by a superposed noise. We
start looking at the deviations caused by a single tone noise at a certain frequency offset from the
carrier. This case is called the single side band superposed noise.
The combination of two SSB noise contributions at opposite frequency offsets (tf
offset
) is also
considered and compared to the sidebands produced by angular modulation.
v
In the FM example the modulating tone is assumed as a cosinus function just to end with the same form as in the
PM example.
4
2
c
c
A
P ≤
for bwn < fc/2
PM
FM
No/2
bwn fm +fm bwn
Sn(f)
Noise
fc fc f
4
2
c
A
Sc(f)
Carrier
fcbwn fc fc f
4
2
c
A
Sosc(f)
fcbwn fc fc f
Sosc(f)
Chapter 6 / Phase Noise: theoretical to practical approach 129
The concepts developed in this section are based on references [Robi91] and [Boon89].
Let us consider the addition of our sinousoidal carrier, v
c
(t), with some broadband noise.
( ) ( ) ( ) ( ) ( ) [ ] t t f t a A t n t f A t v
n c n c c c n c
θ π π + ⋅ + ⋅ · + ⋅ ·
+
2 sin ) ( 1 2 sin
(6.6)
For values of: v
c+n
(t) ∈ [A
c
, A
c
]
we could model every deviation as a phase error, ϕ
n
(t). However it would not be possible to
include the values exceeding the envelope of the sinusoidal carrier. On the other hand an
amplitude error, a
n
(t), can model every value of:
v
c+n
(t) ∈ [[A
c
+max{n(t)}] , [A
c
+max{n(t)}] ]
but it would not be able to represent the noise in the time instants that correspond to zero
crossings of the carrier. Therefore the added noise has to be decomposed into amplitude and
phase deviations.
Figure 6.3 shows the phasor diagram of v
c
(t) plus a single tone noise v
n
(t). The superposed noise
is a narrow band portion of n(t), and equals:
( ) ( ) ( ) [ ]
n no c n n n n n
t f f A t f A t v ϕ π ϕ π + + · + · 2 sin . 2 sin . (6.7)
where f
no
is the frequency offset between the noise contribution and the carrier. The phase of the
carrier is taken as a reference for the diagram.
Figure 6.3 SSB superposed noise: AM + PM decomposition (phasor)
The right side of Fig. 6.3 shows two pairs of sidebands that explain the amplitude and phase
deviations caused by the superposed noise.
We may also express the amplitude and phase deviation, by substituting n(t) by v
n
(t) in equation
(6.6), and developing the corresponding time functions a
n
(t) and θ
n
(t) that express the amplitude
and phase modulation. It follows:
ϕ
n
f
no
A
n
A
c
A
n
/2
+f
no
A
n
/2
A
c
/2
f
no
PM
A
n
/2
+f
no
A
n
/2
A
c
/2
f
no
AM
130 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
( ) ( ) [ ]
( ) ( ) [ ] ( ) ( ) [ ]
n no n c n no n c c
n no c n c c n c n c
t f A t f t f A A t f
t f f A t f A t v t v t v
ϕ π π ϕ π π
ϕ π π
+ ⋅ ⋅ + + ⋅ + ⋅ ·
· + + ⋅ + ⋅ · + ·
+
2 sin 2 cos 2 cos 2 sin
2 sin 2 sin ) ( ) ( ) (
Then we compare it to the 2
nd
form of v
c+n
in equation (6.6):
( ) ( ) [ ]
( ) ( ) ( ) [ ] [ ] ( ) ( ) ( ) [ ] [ ] t t a A t f t t a A t f
t t f t a A t v
n n c c n n c c
n c n c n c
θ π θ π
θ π
sin ) ( 1 2 cos cos ) ( 1 2 sin
2 sin ) ( 1 ) (
⋅ + ⋅ + ⋅ + ⋅ ·
· + ⋅ + ⋅ ·
+
Finally assuming A
n
<<A
c
and A
n
/A
c
<< 1 rad, we find:
( ) ( )
n no
c
n
n
t f
A
A
t ϕ π θ + ⋅ ≈ 2 sin and ( )
n no
c
n
n
t f
A
A
t a ϕ π + ⋅ ≈ 2 cos ) (
(6.8) (6.9)
This result is represented in a spectrum diagram in figure 6.4. The plot showing the PM
contribution has sidebands with “negative” power. It is in fact a liberty of notation to indicate the
sign of the voltage signals that are associated with these sidebands.
Figure 6.4 Superposed Noise: AM + PM decomposition (spectrum)
We may now consider a 2
nd
SSB noise contribution. When a broadband noise is added to a signal
it is very likely that for certain offsets the noise density at both sides of the carrier has a similar
level. We take two single tone components at frequency offsets of ±f
no
, that are named v
nu
(t) and
v
nl
(t) for upper and lower sidebands respectively.
8
2
n
A
8
2
n
A
4
2
n
A
fcfno fc +fc fc+fno f
4
2
c
A
Sc(f) + Sn(f)
PM AM
fcfno fc +fc fc+fno f
8
2
c
A
fcfno fc +fc fc+fno f
8
2
c
A
Chapter 6 / Phase Noise: theoretical to practical approach 131
They represent DSB superposed noise: they have equal amplitudes, and opposite frequency
offsets with respect to the carrier frequency,
( ) ( ) [ ]
nu no c n nu
t f f A t v ϕ π + + · 2 sin . and ( ) ( ) [ ]
nl no c n nl
t f f A t v ϕ π + − · 2 sin .
(6.10)
The phases ϕ
nu
and ϕ
nl
are random variables uniformly distributed in the range: [0, 2π]
Therefore the phase difference between the two sidebands for t=0, is also a random phase with a
similar flat distribution.
Figure 6.3 shows us that sidebands that cause exclusively phase modulation, “cross” each other
in a phasor diagram in phases that are in quadrature to the carrier phase. Inversely the amplitude
modulating sidebands “cross” in positions that are in phase with the carrier.
The two superposed sidebands , v
nu
and v
nl
, have an equal probability of “crossing” either in
phase or in quadrature, because of the uniformly distributed phase difference ϕ
nu
ϕ
nl
. Therefore
statistically, the combined power of these two sidebands is divided into two equal parts: one
causing phase modulation and the other causing amplitude modulation.
We can represent this statistical result by two sidebands that “cross” each other at positions with
a phase offset of ±(π/4 + π) with respect to the carrier. The peak phase deviation caused by these
two sidebands equals: ( ) { ¦
c
n
n
A
A
t ⋅ · 2 max θ (6.11)
which corresponds to an increase of 3dB in the phase deviation when compared to the SSB
superposed noise. We may also see this increase in 3dB as a power addition of the phase
disturbances caused by two independent or uncorrelated noise sidebands.
The superposed DSB sidebands are called uncorrelated in reference to their random distributed
phase difference; in opposition to the DSB sidebands caused by angular or phase modulation of a
base band noise contribution.
The modulated DSB sidebands have frequency offsets and phases that are equal in module and
with opposite signs. The type of modulation that causes the frequency translation of the noise
power determines whether this disturbance generates phase or amplitude deviations.
In the case of the PLL synthesizer, we are particularly interested in the phase deviations caused
by added noise and angular modulated noise. Actually, most of the added noise is propagated
through stages that work with strong amplitude limitation. This nonlinear behaviour attenuates
much of the power of the sidebands that cause amplitude deviations. Therefore it is common to
refer to the total sideband noise power as a phase noise power.
Figure 6.5 Phase modulated carrier by DSB superposed noise
( ) 2 4
2
n
A
fcfno fc +fc fc+fno f
4
2
c
A
Sosc(f)
Two sidebands
Superposed noise
+
ideal limiter ⇒
carrier only
phase modulated
132 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Figure 6.5 shows the spectrum of a carrier plus a DSB superposed noise after it has been
transmitted by a stage that eliminates the amplitude modulating sidebands.
The SSB phase noise in this case equals:
,
`
.

⋅
⋅ ·
,
`
.
 ∆
⋅ ·
c
m
p
DSB
no
A
A
f L
2
log 20
2
log 20 ) (
 superposed
ϕ
where ∆ϕ
p
is the peak phase deviation, or as defined in equation (6.11):
( ) { ¦
c
n
n p
A
A
t ⋅ · · ∆ 2 max θ ϕ
Next we compare the phase deviations caused by two types of sideband: superposed and angular
modulated. In order to compare sidebands that have equal frequency offsets and amplitude, we
suppose that the angular modulated sidebands are due to a band base signal v
bb
(t) that equals:
( ) ( ) [ ]
n no c
c
n
p
bb
t f f
A
A
K
t v ϕ π + + ⋅ · 2 sin .
2
where K
p
is the phase deviation sensibility in rad/V.
Figure 6.6 Phase deviation from DSB sidebands
I) Superposed DSB sidebands II) Ang. modulated DSB sidebands
( ) ( )
,
`
.

⋅
⋅ · − ·
⋅
≈
,
`
.

⋅
· ∆
c
n
no no
c
n
c
n
p
A
A
f L f L
A
A
A
A
arctg
2
log 20
2 2
ϕ
( ) ( )
,
`
.

⋅ · − ·
⋅
≈
,
`
.
 ⋅
· ∆
c
n
no no
c
n
c
n
p
A
A
f L f L
A
A
A
A
arctg
log 20
2 2
ϕ
Table 62 L(f
offset
) from modulated and superposed noise
f
c
f
no
f
c
+f
no
A
m
A
m
A
c
f
c
Maximum
Phase
deviation
∆ϕ
p
A
n
A
n
A
c
∆ϕ
p
A
n
A
c
A
n
Angular Modulated DSB Superposed DSB
Chapter 6 / Phase Noise: theoretical to practical approach 133
The phase noise caused by two superposed sidebands is 3dB smaller than the one caused by
angular modulated sidebands with the same amplitude. It is important to notice that this
comparison has considered a DSB superposed noise with both AM and PM portions. In section
6.3 we discuss the transfer of stages that cause amplitude limitation, and their action over the
AM portion of the superposed noise.
6.2.3 Slope approach
The results of noise simulations in analog circuits is usually given as a voltage noise density at a
specific node. If this node is part of one of the PLL blocks this noise power may be propagated to
the VCO tuning input, and ultimately it will modulate the frequency of the VCO output.
The phase detector and charge pump transform phase deviations in current, and this current
charges the impedance of the loop filter, and determines the tuning voltage v
tune
. Therefore if we
are able to express voltage noise densities as phase deviations, we may calculate the phase noise
in the VCO output that is caused by a certain contribution of voltage noise.
Let us consider a logical or switching stage that has two output values, low and high. These
stages may work with differential or single ended inputs and outputs. In figure 6.7 we consider a
differential stage, whose output is represented by a single ended output (with an amplitude that is
twice the amplitude of each side of the differential output) and a threshold. The instants where
the signal crosses the threshold are called zerocrossings. The interval between two successive
zerocrossings is the period of the signal driving the stage. The variations of this period that are
due to additional voltage noise are called time jitter.
Figure 6.7 Slope approach: voltage & time deviations
The noise voltage V
n
(t) is calculated by a small signal noise simulation around a zerocrossing
instant. The result is usually presented as a voltage noise density δv
nrms
(f) in
[ ]
V Hz
. The rms
amplitude equals the square root of the power spectral density for the unitary impedance. The
time deviation is represented by similar functions in the time and frequency domain: ∆t
n
(t) and
δt
nrms
(f) in
[ ] Hz s
.
The relationship between the voltage and time deviations is given by the voltage slope of the
large signal driving the stage. We name v
s
(t) the output signal and t
c
the zerocrossing time
instant; and we start looking at a single tone portion of V
n
(t) that we call v
n
(t). This single tone
portion is equal to the SSB superposed noise defined by equation (6.7), and it may also be
written as a frequency function: ( ) ( )
n rms n n
f v t v
−
↔ δ .
Ts
dv
s
/dt
∆t
n
(t)
V
n
(t)
tc
2A
differential signal + treshold
134 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
The error caused by this superposed sideband at the zerocrossing instants is necessarily a phase
error. Equation (6.8) shows us the value of the phase error caused by the SSB superposed noise,
and it specifies that the phase deviation is a sinus with frequency equals to the offset frequency
between the superposed sideband and the carrier.
Furthermore in section 6.2.1 we saw that phase deviations can be expressed as equivalent time
deviations. Thus the time deviation that is caused by the single tone component δv
nrms
(f
n
)
becomes:
]
]
]
· −
−
−
Hz
s
dt
t dv
f v
f f t
c s
n rms n
c n rms n
) (
) (
) (
δ
δ
or remembering that
c no n
f f f + · ; it follows that:
dt
t dv
f f v
f t
c s
c no rms n
no rms n
) (
) (
) (
+
·
−
−
δ
δ (6.12)
This is the time deviation due to a SSB superposed noise at a frequency offset f
no
from the
carrier. If the voltage noise density δv
nrms
(f) has the same amplitude for the frequencies f
c
+f
no
and f
c
f
no
the time deviation due to a DSB superposed noise becomes:
dt
t dv
f f v
dt
t dv
f f v f f v
f t
c s
c no rms n
c s
c no rms n c no rms n
no rms n
) (
) ( 2
) (
) ( ) (
) (
2 2
+ ⋅
·
− + +
·
− − −
−
δ δ δ
δ (6.13)
Finally the phase deviation due to a time deviation is:
]
]
]
⋅ ·
− −
Hz
rad
f t
T
f
offset rms n
s
offset rms n
) (
2
) ( δ
π
δϕ (6.14)
where T
s
is the period of the signal, and we indicate the independent parameter as the frequency
offset to remember that the voltage noise that originates this time deviation is found at f
c
tf
offset
.
The phase deviation relates the time jitter to the SSB phase noise of the output signal. It follows
that:
( )
( ) ( )
2
:
2
log 20
2
log 20
p
rms
offset rms offset p
offset dB
f f
f L
ϕ
ϕ
ϕ ϕ ∆
· ∆
,
`
.
 ∆
⋅ ·
,
`
.
 ∆
⋅ ·
So for a rms phase deviation given by equation (6.14), it becomes:
( )
( ) ( )
,
`
.

⋅ ⋅
⋅ ·
,
`
.

⋅ ·
− −
s
offset rms n offset rms n
offset dB
T
f t f
f L
δ π δϕ 2
log 20
2
log 20
(6.15)
Equation (6.15) shows the degradation of a periodic signal due to a time deviation. It also shows
that the phase noise is inversely proportional to the period of the signal.
Chapter 6 / Phase Noise: theoretical to practical approach 135
6.3 Large Signal Linearization
The term large signal linearization refers to a transfer function that is calculated around a
periodic steady state of a block with a large signal input. The previous section started discussing
the phase noise induced by a voltage noise that is sampled at the zero crossing moments.
Here we search the transfer function for a small signal that is transmitted by a block which is
driven by a large signal input. The large signal is considered as periodic, and the transfer causes
amplitude limitations of the output, which appears as a time variable transfer function.
vi
The resulting time variable transfer function may be used to explain the frequency translation of
the noise contributions that are found around the harmonics of the frequency of the signal.
6.3.1 Time and Frequency representation
Let us consider the transfer function of a voltage amplifier that has an ideal limiting output. It
presents a constant voltage gain for input voltages below a certain threshold and for amplitudes
above this threshold the voltage gain equals zero.
Figure 6.8 shows the transfer of a sinusoidal input signal v
si
(t) that overdrives the ideal limiting
amplifier. The output signal v
so
(t) has a fundamental harmonic at the same frequency as the
input, but it also has higher harmonics that are generated by the nonlinear clipping of the limiter.
The transfer function v
so
(t) / v
si
(t) is time variable, and it may be represented in both time and
frequency domains. We call it the periodic large signal (PLS) transfer.
The transfer of a small signal that is added to v
si
(t) may be calculated making a 1
st
order
development of the periodic transfer around the steadystate that is driven by v
si
(t). If the small
signal is represented by a noise component v
n
(t), it becomes:
( ) ( ) [ ] ( ) [ ]
( )
( )
( ) ( ) ( ) ( ) t v t h t v t v
dx
x dh
t v h t v t v h
n PLS so n
t v x
si n si
si
⋅ + · ⋅ + ≈ +
·
(6.16)
where h
PLS
(t) is the transfer function for a small signal that is added to the large input signal. The
Fourier transform of this time transfer is denoted as H
PLS
(f), and we use it to define the transfer
of the small signal when it is represented in the frequency domain;
for
( ) ( )
( ) ( )
( ) ( ) ( ) ( ) f H f v t h t v
f H t h
f v t v
PLS n rms n PLS n
PLS PLS
n rms n n
⊗ ↔ ⋅
↔
↔
−
−
δ
δ
(6.17)
where the frequency domain transfer function is convoluted with the small signal input. The
periodic transfer for a small signal that is defined by equation (6.17) is linear; since the output of
vi
These ideas are based on the convolution transfer discussed in reference [Boon89]. A similar discussion focused
on oscillators noise can be found in [Haji98].
h[v
si
(t)+v
n
(t)]
v
si
(t)
v
n
(t)
h(x)
136 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
the sum of two small signals equals the sum of their separate outputs. The supposition of a linear
transfer holds for small signals whose amplitude does not disturb significantly the periodic large
signal transfer h
PLS
(t).
It is important to notice that the time variable characteristic of this transfer causes frequency
translation of the input signals. For broadband noise contributions the frequency translation also
causes aliasing or folding. These effects are further discussed in chapter 7.
Figure 6.8 Periodic transfer determined by a large signal
6.3.2 Linear Time Variable transfer
Figure 6.9 shows the periodic transfer functions h
PLS
(t) and H
PLS
(f) that are calculated for two
types of limiting amplifiers: an ideal limiter and a hyperbolic tangent (tanh) limiter. We choose
the hyperbolic tangent because it represents the transfer of a block that appears very often in ICs:
the differential stage composed of bipolar transistors.
The figure is divided in 6 parts:
A) The input and output signals have a unitary amplitude. The input signal v
si
(t) is a sinus curve
with a frequency equal to 0.5 Hz. The output of the ideal limiter is called v
soideal
and the
output of the hyperbolic tangent limiter is called v
sotanh
. The gain at the zero crossing is
equal for both limiters, G
c
=2. The curves are indicated by the labels: si, ideal, tanh.
input large
signal:
v
si
(t)
( )
c
in
out
G
dV
dV
·
0
Τ
s
/2 =2.f
s
Τ
w
=1/f
w
t
V
in
V
out
t
G
c
t
G
c
.T
w
/T
s
f
w
f
w f
(Hz)
Τ
s
=1/f
s
amplifier
+
ideal
amplitude
limiter
output large
signal:
v
so
(t)
Time
variable
transfer
function:
h
PLS
(s)
H
PLS
(f)
Chapter 6 / Phase Noise: theoretical to practical approach 137
B) The time derivatives of the 3 signals are: dv
si
/dt , dv
soideal
/dt and dv
sotanh
/dt . The labels are
the same as used in part A).
C) The periodic transfer functions h
PLSideal
(t) and h
PLStanh
(t) are plotted. The functions are
calculated using the approximation:
( )
( )
( )
( ) t dv
dt
dt
t dv
t dv
t dv
si
so
si
so
⋅ ≈
D) The periodic transfer functions H
PLSideal
(f) and H
PLStanh
(f) are presented. In this plot the
frequency axis is single sided (only positive frequencies).
E) The periodic transfer functions H
PLSideal
(f) and H
PLStanh
(f) are plotted in a larger range of
frequencies. The yaxis is in dB, the amplitude value equals: 20.log( H
PLS
(f) )
F) The curve in solid line shows the difference between the two transfers: H
PLSideal
(f) and H
PLS
tanh
(f) . It can be seen that it is the lowpass filtering behaviour that differentiates the ideal and
the tanh limiters. The yaxis is also in dB. The dark gray dashed curve shows an
approximation of the black curve, it is a LPF to the order of 24; and it correctly fits the
difference curve for frequencies above 5Hz. The light gray dashed curve shows a first order
LPF that fits the difference curve for frequencies below 2Hz.
The amplitude limitation of the tanh transfer is smoother than the ideal limiter. The difference
may be represented as a LPF, that has a very steep attenuation slope.
The curves of figure 6.9 are calculated with a mathematical model. The actual transfer of a block
of a circuit may be calculated with software for analogic simulations. Particularly for circuits
working with high signal frequencies and/or very steep signals there is another lowpassfiltering
behaviour that appears to limit the slope of the output signals. This is the slew rate, which is
related to the biasing of the stage and to the load impedance. Together they determine the
maximum slope of the output signal.
Recently software implementations have appeared (see reference [Wiel97]) which allow one to
calculate a periodic transfer that is associated with a large driving signal. The periodic transfer
function is very useful to evaluate the noise at the output of strongly nonlinear stages.
A simulation example is given in chapter 7, to compare practical and theoretical aspects of the
periodic transfer function.
Finally we can observe that for T
w
→0, the periodic transfer h
PLS
(t) approaches a comb sampler.
This ideal sampler would completely suppress the AM component of a superposed noise.
138 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Figure 6.9 Large Signal Transfer: ideal and hyperbolictangent limitations
A) B)
C) D)
E) F)
si
ideal
tanh
si
ideal
ideal
ideal
tanh
tanh
tanh
tanh
ideal
Chapter 6 / Phase Noise: theoretical to practical approach 139
This chapter discussed the generation of phase noise due to noise power that is added to a signal,
or to noise that causes modulation of a signal. The representation of random electrical noise was
briefly commented. Different notations were presented and related to the mechanisms of phase
noise generation.
The periodic transfer of switching stages was modeled as a time variable transfer function, that
may be used to calculate the noise at the output of nonlinear blocks.
140 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Chapter 7 / Phase Noise in the PLL context 141
Contents:
7. Phase Noise in the PLL context 141
7.1. Translating the SNF into phase, time, voltage and current noise ......................................................... 143
7.2. Sampling effects: SNF x fcp .................................................................................................................. 147
7.2.1. Narrow bandwidth noise sources................................................................................................. 149
7.2.2. Large bandwidth noise sources.................................................................................................... 151
7.3. Detailing noise sources in different PLL blocks ................................................................................... 154
7.3.1. Dflip flop.................................................................................................................................... 154
7.3.2. Charge Pump ............................................................................................................................... 158
7.4. Behavioural Models .............................................................................................................................. 159
7.4.1. Frequency domain ....................................................................................................................... 159
7.4.2. Time domain................................................................................................................................ 160
7.5. Implementation Loss due to Phase Deviations ..................................................................................... 162
7.5.1. Signal to noise ratio and implementation loss ............................................................................. 163
7.5.2. Digital Demodulator: clock and carrier recovery loops............................................................... 167
Figures:
Figure 7.1 PLL block diagram with signal+noise inputs........................................................................ 142
Figure 7.2 Noise Transfer Slopes................................................................................................................ 143
Figure 7.3 Synthesizer Noise Floor............................................................................................................ 144
Figure 7.4 Sampled Loop Model ............................................................................................................... 148
Figure 7.5 Large bandwidth noise folding................................................................................................ 152
Figure 7.6 DFF plus superposed noise in the clock input: time domain signals.................................... 155
Figure 7.7 DFF plus superposed noise in the clock input: frequency domain signals .......................... 155
Figure 7.8 Charge Pump current noise levels within one period............................................................ 158
Figure 7.9 Behavioural model of the PLL for AC and noise simulations .............................................. 160
Figure 7.10 Behavioural model of the PLL for transient simulations..................................................... 161
Figure 7.11 Digital Demodulator and Decoder .................................................................................... ...... 162
Figure 7.12 Noise Power added by the LO sidebands................................................................................ 164
Figure 7.13 Behavioural Model of the Carrier Recovery loop................................................................. 167
Tables:
Table 71 Data sheet points from: TSA5059  low noise PLL................................................................ 145
Table 72 The influence of f
cp
change for narrow band noise................................................................ 151
Table 73 The influence of f
cp
change for large band noise.................................................................... 153
Table 74 Implementation Loss X Phase deviations ............................................................................... 166
7 Phase Noise in the PLL context
In this chapter we continue our topdown analysis of the PLL circuit. The results from the
preceding chapters, about the transfer functions of the phase model and about the mechanisms of
phase noise generation, are combined, to analyze the noise contribution of different blocks.
Simulations and measurement possibilities that are used to guide the design and the evaluation of
a PLL IC are also discussed.
142 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
This chapter combines the results of the previous chapters to develop a numerical analysis of the
phase noise of a PLL synthesizer. It starts with the translation of the SNF requirement for noise
densities in phase, time, current and voltage magnitudes. These densities can be compared with
the simulation of the different constituent blocks.
The noise densities are affected by the sampling effects of the edge triggered blocks. This
influence is examined, considering the bandwidth of the noise sources. The possibilities to
distinguish the dominant noise sources are also discussed. Two examples of simulation are
presented, for a Dflip fop and charge pump design, to illustrate the concept of the periodic
transfer.
Finally we present behavioural models that enable one to combine circuit and system level
descriptions in AC and TR simulations. The behavioural model of a digital demodulator is also
presented. These top level models can be used to examine the total implementation loss that is
caused by the phase deviations in the LO signal. The relationship between the phase deviations
and the implementation loss are presented with a short numerical evaluation. Later in chapter 8,
these tools are illustrated by simulations and comparison to measurements.
The following block diagram with signal and noise inputs is used in this chapter.
Figure 7.1 PLL block diagram with signal+noise inputs
The noise inputs are indicated by grey rectangles.
N
pll
is a phase degradation that was introduced in chapter 3 as the synthesizer noise floor (SNF).
It is measured in rad/sqrt(Hz), and it is composed of the noise contributions from: the reference
chain (crystal oscillator and reference divider), the main divider and the comparator (phase
detector and charge pump).
The input v
nvco
represents the intrinsic noise of the VCO, and, v
nf
accounts for the noise sources
of the loop filter. In chapter 4
i
, we saw that the noise contributions from a loopfilter (from the
filter impedance and the amplifier) are attenuated by the postfilter, and therefore it is practical to
split these two contributions. Both v
nvco
and v
nf
are voltage noise densities given in ( V/sqrt(Hz)
).
The sketches and expressions below summarize the results from chapters 2 and 3 that are used in
the following sections. In figure 7.2 the noise transfer slopes are indicated for inputs with a white
spectral density.
i
See table 43 : transfer functions of the disturbances that are related to the active loop filter.
X
osc
(ϕ
xosc
)
÷ R
N
pll
Ph. Det.
&
Ch. Pump
( Kϕ )
VCO
( Ko )
÷ N
ϕ
osc
v
nvco
Post
Filter
Z
filter
v
nf
Chapter 7 / Phase Noise in the PLL context 143
( )
( )
,
`
.

+
⋅ ⋅
+ ⋅ ⋅ +
· ≈ ·
1
2
1
) (
2
2
3
3
n n
p
LPF
pll
osc
w
s
w
s
T s
N
s B s B
N
ξ
ϕ
( ) ( )
,
`
.

+
⋅ ⋅
+ ⋅
⋅ ⋅
· ≈ ·
1
2
2
2
1
_
n n
o
BPF vco vco
nvco
osc
w
s
w
s
C s K
s B s B
v
ξ
α
ϕ
and
) 1 (
3 p
BPF vco
nf
osc
T s
B
v ⋅ +
·
−
ϕ
Figure 7.2 Noise Transfer Slopes
In chapter 6 we discussed the deviations that are caused by noise contributions which are
superposed to the signal or which modulate the signal. The superposed contributions cause both
amplitude and phase deviations. When the disturbed signal is propagated through stages that
have a periodic transfer with high gain around the zerocrossing instants and low gain elsewhere,
the amplitude deviations are strongly attenuated. Therefore the noise from switching blocks of
the PLL (N
pll
) is expressed as a phase deviation.
The sidebands that are found in the output of the VCO are mostly caused by the frequency
modulation of noise power at the input of the VCO. Part of the intrinsic noise of the VCO is not
frequency modulated, but just superposed or amplitude modulated. Nevertheless this part of the
noise is usually not significant. Hence we treat the sidebands of the output of the VCO as angular
modulated sidebands.
Our analysis starts with N
pll
, translating the phase deviation in voltage, time and current
deviations. These translations are used to reflect the requirement of phase noise into magnitudes
that are comparable to the outputs of the different PLL blocks.
7.1 Translating the SNF into phase, time, voltage and current noise
The requirement of phase noise for PLL synthesizers is often specified as a maximum phase
noise density at the input of the phase detector. It is a single sideband measurement in dBc/Hz,
referring to the noise performance of the inloop zone of the output spectrum.
( ) { ¦ ( ) [ ]
Hz
dBc
loop in offset dB dB pll
N f L N log 20 min
_ _
⋅ − · (7.1)
The peaking that is indicated in figure 7.3 is the combination of two effects:
 the mismatch of the closed loop bandwidth with respect to f
i
(the intersection frequency for
the asymptotes of the noise performances of the PLL and the VCO);
 and the overshoot associated to the closed loop transfer function B(s). This resonant
overshoot is related to the stability of the loop, that is measured by the open loop phase
margin.
0 dB/dec
60 dB/dec
+20 dB/dec
40 dB/dec
ϕ
osc
/N
pll
ϕ
osc
/v
nf
20 dB/dec
ϕ
osc
/v
nvco
144 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
It is important to notice that excessive peaking masks the measurement of the inloop SSB noise
(L(f
offset
) ). Loop filters with a large bandwidth (that assures a closed bandwidth equal or greater
than f
i
) and an elevated phase margin are indicated to perform the measurements of N
pll
.
Figure 7.3 Synthesizer Noise Floor
The value of N
pll
is derived from the SSB phase noise, and the latter is related to the peak phase
deviation that is caused by the PLL noise.
We would like to express N
pll
as the equivalent phase and time deviations that would cause the
same L
dB
(f
offset
). The deviations are base band components that modulate the VCO output, as
presented in section 6.2.1. We calculate the deviations as noise densities that are denoted as δϕ
pll
and δt
pll
.
Later on, we relate δt
pll
to the slope and the period of a carrier signal, and we derive δv
pll
using
the slope approach (see section 6.2.3). Finally the sensitivity of the charge pump K
ϕ
is used to
transform δϕ
pll
into a current noise density δi
ChP
.
Let us picture these ideas through a numerical example. The values in the table below are taken
from the data sheet of the Low Phase Noise Frequency Synthesizer, TSA5059 for satellite
frontend applications.
ii
ii
A similar analysis for a GSM synthesizer can be found in [Gree95].
peaking
f
osc
20.log(N)
inloop
L
dB
(f
offset
)
outloop
L
dB
(f
foffset
)
f
offset
N
pll_dB
: Synthesizer Phase Noise floor
Chapter 7 / Phase Noise in the PLL context 145
Symbol Parameter Conditions Typical value
N
plldB
Equivalent phase noise at
the phase detector input
measured with:
f
cp
= 250 KHz; I
cp
=1.2 mA
157 dBc/Hz
I
cp
Charge pump current
(absolute value)
4 programmable values
(2 bits)
120 µA / 260 µA
555 µA / 1.2 mA
R
Reference divider ratio
16 programmable values
[indicated as series in the form:
(a+2
k1
).2
k2
]
2 / 4 / 8 / … / 128 / 256 ;
24;
5 / 10 / 20 / … / 160 / 320
N
Main divider ratio
17 programmable bits
+
optional prescaler (/2)
w/o presc.: 64 … (2
17
1)=131071
or
w presc.: 128 … 262142
f
cp
Comparison frequency
for a 4MHz crystal
directly related
to R values
2MHz / 1MHz … / 15.625kHz ;
166.67kHz;
800kHz / 400kHz … / 12.5kHz
f
rf
RF input frequency
(main divider input ⇒
f
rf
= f
vco
)
Input sensibility
+
related to N and f
cp
values
64 MHz  2700 MHz
Table 71 Data sheet points from: TSA5059  low noise PLL
• The phase noise density at the phase detector input becomes:
Hz
rad
rms pll Hz
dBc
rms pll
dB pll
N
8
_
10 998 . 1 157
2
log 20
−
−
−
⋅ · ⇒ − ·
,
`
.

⋅ · δϕ
δϕ
In table 71 the value of the synthesizer noise floor is referenced to certain conditions of f
cp
and
I
cp
. The relationship between N
pll
and the comparison period appears as we look for the
equivalent time noise density at the phase detector input.
• Time noise density at the phase detector input equals:
iii
Hz
s
pll cp
cp
rms pll pll
f t
kHz
T
T
t 72 . 12 and s 4
250
1
for so
2
· · · ⋅ ·
−
δ µ
π
δϕ δ L
When we compare the same δϕ
pll
to the period of the crystal oscillator, we find a more strict
specification for the time density:
Hz
s
Xosc Xosc
Xosc
rms pll Xosc
f t n
MHz
T
T
t 795 . 0 and s 250
4
1
for
2
· · · ⋅ ·
−
δ
π
δϕ δ L
The values of the time noise densities that are calculated above do not take into account any
possible aliasing effects. Section 7.2 discusses the sampling effects for the noise transfer, taking
iii
From here on the notations δx
rms
are shortened to δx , but the noise density variables continue to be given in rms
values.
146 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
into account the noise bandwidth and the sampling frequency. For the moment we may consider
that our phase and time deviations are white bandlimited noise densities, with a cutoff
frequency smaller than f
cp
/2 .
• The voltage noise density at the phase detector:
The time noise may be translated into a voltage noise for any logical or switching stage that is
driven by a large periodic signal with a defined voltage slope (dv/dt) at the zero crossings.
The output of the dividers and the phase detector itself are polarized with elevated biasing
currents in order to increase their voltage slopes and decrease their sensibility to voltage
disturbances. The maximum voltage slope of the output of a block is called slew rate. Usual
values of slew rate for PLL stages with strong biasing are to the order of 1V/ns, or 10
9
V/s.
Under these conditions the voltage noise becomes:
Hz V v
dt
dv
dt
dv
t v
rms pll
kHz
pll pll
/ 72 . 12 10 for
s
V
9
crossing zero
250 f for
cp
µ δ δ δ · ⇒ ≈ ⋅ ·
−
·
L
The voltage density is referenced to a time noise, and consequently it is related to the period of
the large signal driving the blocks under analysis.
• The current noise density at the charge pump output:
The specification of phase noise may be translated into a current noise value that is related to the
sensitivity of the charge pump K
ϕ
. Let us consider the minimum and maximum values of I
cp
in
table 71, then:
Hz pA i mA I
Hz pA i A I
rms ChP
rms ChP
pll ChP
K i
/ 82 . 3 1,2 for
/ 382 . 0 120 for
cp
cp
· ⇒ ·
· ⇒ ·
⋅ ·
δ
δ µ
ϕ
δϕ δ L
• Noise performance of the freerunning oscillator:
Finally we may estimate the minimum noise performance of the VCO that enables us to assure a
smooth transition between the inloop and the outofloop zones of the output spectrum. The
smooth transition is related to the optimization of the phase jitter σ
ϕ
in the output spectrum.
Let us consider the tuner of a satellite receiver, that downconverts the RF input signals from the
Lband (950 MHz to 2150MHz) to an IF stage. The intermediate frequency equals 470MHz, and
the frequency of the local oscillator equals f
RF
+ f
IF
. We suppose a comparison frequency of
250kHz. The range of the LO frequency and the counting ratios of the main divider follow:
[ ] [ ] 10480 ; 5680 250 for 2620 ; 1420 ∈ → · ∈ N kHz f MHz f
cp vco
K
Next we consider the level of the inloop sidebands for the maximum closed loop bandwidth.
The maximum closed loop bandwidth occurs for the largest open loop gain: α = α
max
. This
situation corresponds to small values of N, and large values of I
cp
.
iv
The synthesizer noise floor
in table 71 is indicated for the maximum I
cp
value, so we combine this data with the minimum
value of N, to obtain the PLL inloop contribution:
iv
Remembering
N
K I
vco cp
⋅
· α
.
Chapter 7 / Phase Noise in the PLL context 147
( ) ( )
Hz
dBc
loop in pll
f L 82 5680 log 20 157 − ≅ ⋅ + − ·
−
Chapter 5 discussed the limitation of the maximum closed loop bandwidth for a given f
cp
value.
If we take some practical margin to cope with gain variations (up to α
max
/α
n
=3 ), the following
boundary may be suggested:
10
cp
ol
f
f ≤
.
Earlier in chapter 3, we saw that the optimum closed loop bandwidth equals f
i
; and that the open
loop bandwidth, f
ol
, is related to the closed loop bandwidth, f
3dB
, by the following expression:
28 . 0 63 , 1
3
t ≈
ol
dB
f
f
.
Therefore we may estimate the maximum closed loop bandwidth and the corresponding noise
performance of the VCO in order to match f
3dB
with f
i
. It follows that:
( ) ( )
Hz
dBc
vco Hz
dBc
vco
cp
i
kHz L kHz L kHz
f
f 90 100 82 8 . 40 8 . 40 63 . 1
10
− < ↔ − < ⇒ · ⋅ <
where L
vco
is the SSB phase noise of the freerunning oscillator.
The limit of L
vco
that is indicated above would be just enough to obtain a smooth spectrum for
α=α
max
. Nevertheless if we want to optimize the phase jitter over a range of gain, we should
consider using a VCO with a better noise performance. Otherwise if there is no restriction to
increase the minimum tuning step, we may increase f
cp
and work with higher closed loop
bandwidths.
The numerical examples developed in this section are a starting point for the analysis of the noise
performance of a PLL circuit. They are mostly useful in two circumstances: while translating the
specifications of phase noise of the LO to specific blocks within the PLL; or
when choosing adequate VCO and PLL circuits to compose a lownoise synthesizer.
We continue our analysis looking for parameters that allow us to differentiate the noise
contributions that compose N
pll
. We will also treat the folding effects due to sampling of the
switching stages.
7.2 Sampling effects: SNF x fcp
We start recalling the discrete model for the PLL that was discussed in chapter 5. It is a phase
model with an ideal sampler and a zeroorder holder. The sampling rate equals the comparison
frequency of the phase detector, f
cp
. The sampling accounts for the discrete outputs of the
dividers and for the discrete input of the phase detector. The holder represents the charge pump,
with a continuous current output.
When we introduce the sampling operation in the phase model of the PLL, we obtain the
diagram in figure 7.4.
148 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Figure 7.4 Sampled Loop Model
The discrete input of the phase detector ∆ϕ
n
is the same as defined in equation (5.17). It is the
output of an ideal sampler with a comb shaped spectrum. The Fourier transform of ∆ϕ
n
(n.T
cp
) is
named ∆ψ
n
(w) , and it is analogous to the Laplace transform of ∆ϕ
n
defined in equation (5.16).
( ) ( )
∑
+∞
−∞ ·
⋅ + ∆Ψ ⋅ · ∆Ψ
n
cp
cp
n
w n w
T
w
1
with
cp
cp
T
w
π 2
·
The transfer of the ChP as a zeroorder holder was defined in chapter 5, equation (5.18), as:
( )
( )
,
`
.
 ⋅
⋅ ⋅ ⋅ ·
∆Ψ
−
2
sinc
2
w
T
jw
cp
n
o
T w
e T K
w
w I
w
ϕ
where T
w
is the width of the current pulse, that outputs the charge pump for a given phase
deviation input.
In chapter 5 we used this discrete model to discuss the constraints of stability during an interval
of lock acquisition. For this analysis we used the worst case of the delay for the stability
constraint: T
w
= T
cp
.
Here we are interested in the transfer of the noise that appears in the output spectrum of a locked
LO. Therefore the output of the charge pump corresponds to the small pulses that are generated
to compensate the leakage currents and the residual transient currents. For an ideally matched
and leakless case we may consider that the signal output of the charge pump for a locked loop is
null. In what concerns the noise there is a difference. The instantaneous value of the phase noise
at the input of the phase detector is not null, and there is also the noise of the charge pump itself.
The noise of the charge pump is related to the reset interval, τ
rst
, during which both current
sources are activated in order to prevent deadzone problems.
v
Thus we may consider a
minimum T
w
=τ
rst
for the locked condition.
Most of the synthesizers work with a reset interval much smaller than T
cp
, and consequently the
charge pump transfer can be simplified to:
( )
( )
cp
n
o
T K
w
w I
⋅ ≈
∆Ψ
ϕ
for
rst
w
τ
π
<
v
The noise contributions that come from the sinking and sourcing side are added in power, hence their sum does not
equal to zero during the reset interval.
θosc(t)
( ) w
osc
Θ
[ ] Hz V
io (t)
( ) w I
o
[ ] Hz rad
N
pll
v
nvco
Xosc
∆ϕn(n.Tcp)
( ) w
n
∆Ψ
∆ϕ(t)
( ) w ∆Ψ
Tcp
ZOH
ChP
1/R
ZF (w) Ko/jw
1/N
Chapter 7 / Phase Noise in the PLL context 149
This simplified transfer holds for frequency values that are within the first lobe of the sinc term
in equation (5.18).
The combined transfer for the phase detector plus charge pump becomes:
( ) ( )
∑
+∞
−∞ ·
⋅ + ∆Ψ ⋅ ·
n
cp o
w n w K w I
ϕ
(7.2)
Equation (7.2) is used to describe the transmission of large bandwidth noise sources, which are
eventually aliased by the sampling action of the dividers and the phase detector.
vi
In chapter 6, we saw that the transfer of the digital blocks approached this representation of an
ideal sampler as their gain and/or the slope of the input signals increased. We call the switching
blocks, which are driven by the edges of the input signals: edge driven stages. In fact, increasing
the slope of the edges for a fixed voltage disturbance, decreases the resulting time and phase
disturbances. Therefore in the context of low phase noise synthesizer, we find logical blocks with
rather steep edges, with transfers approaching the ideal Dirac comb sampler.
Next we examine the influence of the comparison frequency for the noise contributions that
compose N
pll
. We start considering narrow band noise contributions that are not aliased by
discretization, and we continue with large bandwidth noise in section 7.2.2.
7.2.1 Narrow bandwidth noise sources
In section 7.1, we translated the SNF in time, voltage and current noise densities. Here we take
the inverse path, and discuss the total phase deviation that is caused by the voltage and current
noises from the dividers, the phase detector and the charge pump. We also look for the
parameters that may influence the noise contributions of each block, so that comparative
measurements can be used to identify the dominant noise source in N
pll
.
The total phase deviation of the PLL blocks, δϕ
pll
, is composed of the following noise
contributions:
( )
2 2 2 2
2
2 2 2
,
`
.

+
,
`
.

⋅ +
,
`
.

⋅ +
,
`
.

⋅ ·
ϕ
δ
π
δ
π
δ
π
δ δϕ
K
i
T
t
T
t
T
t
chp
cp
phde
cp
div
cp
ref pll
(7.3)
where δt
ref
, δt
div
and δt
phse
represent the time noise densities from the reference chain, from the
main divider and from the phase detector respectively. The current noise from the charge pump
is denoted as δi
chp
. The noise densities are a function of frequency, and we simplify their
notation, from δϕ(f) to δϕ, by supposing that they have white band limited spectra, and that we
consider the same frequency f for all the noise contributions.
In equation (7.3) we see just one noise contribution that is independent of T
cp
: the charge pump
noise. However the time noise densities are a translation of voltage densities that are transmitted
by edge driven blocks; and the slope of the edges may be a function of T
cp
.
We may distinguish two extreme behaviours for the voltage slopes with respect to the input
signal frequency:
• Transition slope limited by the slew rate:
vi
We recall that in lock mode the output of the two dividers, and the phase detector work at the same frequency.
Therefore the sequence of coherent samplers can be replaced by a single discretization with period T
cp
.
150 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
The slope of the output is fixed by the slew rate of the block transmitting the signal; dv/dt is
independent of the frequency of the input signal.
( ) ( )
max
t t
crossing zero
max
0
v
dt
t dv
cst
dt
t dv
′ ·
¹
'
¹
¹
'
¹
· ·
·
−
This situation happens for stages that are driven by signals with very steep slopes, (the input
slopes are already close to the slew rate), and/or for stages that have a very high gain around
the zero crossings.
• Transition slope proportional to the frequency of the driving signal:
The slope of the output signal is proportional to the frequency of the input signal.
( )
in
w A
dt
t dv
⋅ ·
·
−
0
t t
crossing zero
This case appears for stages that are driven by rather smooth inputs. Around the zero
crossings the slope of the input is amplified to an output slope which is not limited by the
slew rate. The output slope equals the input slope times the gain around the zero crossing.
vii
Table 72 examines the case of a voltage noise contribution that is transmitted by two edge
driven stages with the slope characteristics described above. The voltage noise δv
n
(f) is
independent of f
cp
, and it is band limited.
( ) [ ]
2
for ;
cp
Hz
V
no n
f
f V f v ≤ · δ (7.4)
Equation (7.4) describes a voltage noise density in a single sided frequency spectrum, with only
positive frequencies. It is a band base noise that modulates the phase of the signal that drives the
switching stage.
In the table we observe the influence of a change of f
cp
, for the phase deviation that is caused by
δv
n
. The phase deviation at the input of the phase detector and also at the output of the VCO are
indicated.
The change of the comparison frequency is compensated by changes in the divider ratios, R and
N, in order to keep a fixed oscillator frequency. The time and frequency noise densities are valid
for frequency offsets below f
cp
/2 .
vii
We may illustrate this case by a sinus input, or a series of harmonic sinus with the fundamental and the
harmonics nearly in phase, then:
( ) ( ) ( )
∑
+∞
·
+ ⋅ + + ·
2
1 1
sin sin
n
n in n in in
t w n A t w A t v ϕ ϕ
and
1
ϕ ϕ ≈
n
so
( )
]
]
]
⋅ + ⋅ ≈
∑
∞ +
·
·
−
2
1
t t
crossing zero
0
n
n in
in
A n A w
dt
t dv
Chapter 7 / Phase Noise in the PLL context 151
Transition
type
( )
dt
t dv
o
[V/s]
w
cp
[rad/s]
 δt 
[s/sqrt(Hz)]
 δϕ
pll

[rad/sqrt(Hz)]
N
 δϕ
osc

(in  loop)
[rad/sqrt(Hz)]
L(f) x f
cp
[dB/fcp_octave]
w
cp1
max
1
v
V
t
no
′
· δ
δt
1
.w
cp1
N
1 Ν
1
.δt
1
.w
cp1
Slew rate
slope
max
v′
2.w
cp1
1
t δ
2.δt
1
.w
cp1
N
1
/2 Ν
1
.δt
1
.w
cp1
0dB/oct.
A.w
cp1
w
cp1
cp
no
w A
V
t
⋅
·
2
δ
A
V
no
·
2
δϕ
N
1 N
1
.δϕ
2
Proportional
slope
2.A.w
cp1
2.w
cp1
cp
no
w A
V t
⋅ ⋅
·
2 2
2
δ
2
δϕ N
1
/2 N
1
.δϕ
2
/2
6dB/oct.
Table 72 The influence of f
cp
change for narrow band noise
For the first type of transition with a slew rate slope, a change in f
cp
does not influence the time
noise, and the inloop phase noise remains unchanged as the comparison frequency is doubled. It
corresponds to a constant time noise density with respect to f
cp
.
On the other hand, for the case of proportional slopes, we find a constant phase noise density
with respect to f
cp
. The contribution of this phase noise to the inloop L(f) is directly scaled by
N.
We verify that besides the charge pump noise there is a second noise contribution that is
independent of T
cp
. Nevertheless these two sources can be differentiated by another parameter:
the charge pump sensitivity K
ϕ
, that is proportional to I
cp
.
The noise of the charge pump is added in the loop after the phase detector sampling; and it is
lowpass filtered by Z
F
before it attains an edge driven stage. We know that for stability reasons
the bandwidth of the loopfilter is well below f
cp
/2 ; thus we may consider that the charge pump
noise is a narrow band contribution suffering from no aliasing effect.
So in the next section, which treats large bandwidth noises, we will only look at the time noise
densities of the logical blocks (dividers and phase detector).
7.2.2 Large bandwidth noise sources
Particularly in low noise PLLs, it is common to resynchronize the output of the reference and the
main divider to their input signals. This resynchronization means that the output signal is in fact
a transition of the input signal that is copied to the output. Or in other words, the output of the
counter is triggered by a zero crossing of the input signal. This operation aims to conserve the
phase quality of the input and to transmit it directly to the output, avoiding the additional phase
deviations of the countingcells. The output of a resynchronization stage has a constant slope
with respect to the dividing ratio, since it is determined by the slope of the input signal.
Furthermore these slopes are usually limited by the slew rate of the stage.
152 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
So next, as we consider the sampling effects for large bandwidth noises, we restrict our analysis
to the time noise densities that are related to stages with a constant output slope.
We take the case of a broad band white noise, δv
n
, at the input of the phase detector. The noise
bandwidth equals bw
n
, with bw
n
much larger than f
cp
. We call δv
ncp
the voltage noise density
that is equivalent to a sampled version of δv
n
.
Figure 7.5 illustrates the aliasing of δv
n
as it passes the ideal sampler.
( ) [ ]
n Hz
V
no n
bw f V f v ≤ · for ; δ
Figure 7.5 Large bandwidth noise folding
The sampling is represented by a convolution product with a comb of rays that are spaced by f
cp
intervals. The power density of δv
ncp
is increased by the aliasing effect. The multiplying factor
between the power levels of δv
n
and δv
ncp
is named n
lim
. It is derived by observing the number
of frequency translated spectra that superpose each other. It follows that:
N n
f
bw
n bw bw f n
cp
n
n n cp
∈
⋅
≥ ⇒ ≥ − ⋅
lim lim lim
with ;
2
(7.5)
Approximately, the power of δv
ncp
equals
2
lim no
V n ⋅ for
2
cp
f
f ≤ . This frequency
boundary is related to a physical limitation. Mathematically the sampling is represented by a
convolution product. Physically, however, a signal that has been sampled at a ratio f
cp
, can not
contain power in frequencies above f
cp
/2. This limit equals half the sample frequency and it is
also called the Nyquist frequency.
Therefore δv
ncp
becomes:
…
2
2
lim no
V n ⋅
…
bwn fcp/2 bwn f
bwn bwn f
2
2
no
V
fcp
…
P
vn
(f)
[V
2
/Hz]
δv
n
(f )
bandlimited
white noise
δvncp(f )
δvn(f )
Tcp
1
…
P
vncp
(f)
[V
2
/Hz]
Chapter 7 / Phase Noise in the PLL context 153
( ) [ ]
2
for ;
2
lim
cp
Hz
V
cp
n
no no cp n
f
f
f
bw
V n V f v ≤
⋅
⋅ · ⋅ ·
−
δ (7.6)
viii
Table 73 examines the influence of f
cp
for the phase deviation that is caused by δv
ncp
.
Transition type
w
cp
[rad/s]
δv
ncp
[V/sqrt(Hz)]
 δt 
[s/sqrt(Hz)]
 δϕ
pll

[rad/sqrt(Hz)]
N
 δϕ
osc

(in  loop)
[rad/sqrt(Hz)]
L(f) x f
cp
[dB/fcp_octave
]
w
cp1
=
2π.f
cp1
1
2
cp
n
n
f
bw
v
⋅
⋅
1 max
1
2
.
cp
n no
f
bw
v
V
t
⋅
′
· δ
1 1 cp
w t ⋅ δ
N
1
1 1 1 cp
w t N ⋅ ⋅ δ
Slew rate slope
( )
max
v
dt
t dv
o
′ ·
[V/s]
2.w
cp1
1 cp
n
n
f
bw
v ⋅
1 max
1
.
2
cp
n no
f
bw
v
V t
′
·
δ
1 1
2
cp
w t ⋅ ⋅δ
N
1
/2
2
1 1 1 cp
w t N ⋅ ⋅δ
3dB/oct.
Table 73 The influence of f
cp
change for large band noise
We observe that a broad band noise at the input of the phase detector causes a phase deviation
that depends on the sqrt(f
cp
). This behaviour results in a change of the synthesizer noise floor of
3dB/octoff
cp
, remembering that the SNF or N
pll
is directly related to δϕ
pll
in the table 73.
The SNF change of 3dB/octoff
cp
is commonly observed in low noise PLL synthesizers.
Let us now compare the transfer of the ideal sampler with the periodic large signal transfer
(H
PLS
(f)_equation (6.17) ) that was discussed in chapter 6:
• H
PLS
(f) tends to a comb as T
w
tends to zero. The comb transfer is a reasonable approximation
for noise bandwidths such as:
n
w
bw
T
⋅ > 2
1
.
Furthermore the output of the dividers often have a duty cycle that is smaller than 50%,
which relatively increases the width of the first lobe of the sinc envelope of H
PLS
(f) .
• The slew rate of the switching stages is usually determined by the loading of the output
impedance and the biasing level. It is represented as a lowpassfilter that follows H
PLS
(f) ,
and this postfiltering does not limit the folding effects.
viii
The voltage noise density refers to a spectrum representation with only positive frequencies, explaining the
factor 2 with respect to the double sided (positive and negative frequencies) power spectrum.
( )
2
f H
PLS
⊗
LPF
Slew rate
154 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
7.3 Detailing noise sources in different PLL blocks
The preceding sections discussed the noise contributions that compose the SNF, and the
relationships of these contributions to the parameters I
cp
and T
cp
. Here we will look at two
simulations of different PLL blocks to examples the issues discussed above.
We choose two blocks that have a different type of noise output: a Dflip flop (DFF) and a
charge pump. The first is a basic cell that appears in the three logical blocks: the reference
divider, the main divider and the phase detector. The second has a particular noise contribution
that is not quantified as a time deviation but as a current deviation. The two examples use circuit
blocks that are integrated in the testchips discussed in chapter 8.
7.3.1 Dflip flop
The simulation uses a DFF that is implemented in emittercoupled logic (ECL). The D input is
hard set to a logical “1” and we add a small signal deviation at the periodic clock input. The DFF
also has an asynchronous reset input. In the example the reset input alternates with the clock, so
that we obtain a periodic output with the same frequency as the clock frequency. This sequence
of clock and reset signals represents the inputs of one DFF of the phase detector for a locked
loop. The time domain signals are shown in figure 7.6. They are differential signals that refer to
the following voltages and currents:
• (VT(“/ck”) VT(“/ckn”)): differential clock input, with a fundamental frequency equals:
f
clk
=2MHz. It is a voltage signal. On one side of the input we add a series voltage source with
a small sinus output. It represents a superposed noise. The frequency of the superposed tone
equals: f
n
=11.4MHz .
• (VT(“/rst”) VT(“/rstn”)): reset input. It is a periodic voltage pulse with no added
noise.
• (IT(“/Q10/C”) IT(“/Q11/C”): differential current signal. It is the current at the collectors
of a pair of transistors that receive the clock input. The tail current in this differential pair is
deviated during the intervals where the reset impulse is high.
• (VT(“/cpon”) VT(“/cponn”)): Q output of the DFF. It is also a voltage signal. The names
cpon and cponn refer to the destination of these outputs, which command the inputs of the
charge pump.
The superposed tone in the clock input causes phase deviations in the collector currents of the
transistors Q10 and Q11. These currents are converted into voltage signals that command the
rising edge of the output signal. The falling edge of the Q output is determined by the reset input.
In order to observe the sidebands that result from the phase deviations, we perform a discrete
Fourier transform (DFT) of the time domain signals. The spectra are shown in figure 7.7.
Chapter 7 / Phase Noise in the PLL context 155
Figure 7.6 DFF plus superposed noise in the clock input: time domain signals
Figure 7.7 DFF plus superposed noise in the clock input: frequency domain signals
frequency
[Hz]
[seconds]
156 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
The settings of the time simulation and of the DFT are carefully chosen to improve the accuracy
of the frequency domain plots.
The spectrum of the clock input is composed of a sequence of odd harmonics of the fundamental
frequency: 2, 6, 10, 14 …MHz. There is also a ray that corresponds to the added tone at
11.4MHz. We indicate this ray with an ellipse.
The differential current signal is the output of a transconductor (the differential pair) that samples
the input clock signal at every zerocrossing. So the sample frequency equals twice the clock
frequency, or 2.f
clk
= 4MHz.
If we recall the results of section 6.3, we can represent the transfer function of this
transconductor as a periodic large signal transfer: H
PLS
(f), with rays at 4MHz and its multiples.
The convolution product of the input with H
PLS
(f) should then present rays at the frequencies: tf
n
t n.2.f
clk
with n ∈ N; or numerically:
MHz MHz n
MHz MHz n
K K
K K
6 . 8 ; 6 . 4 ; 6 . 0 ; 4 . 3 ; 4 . 7 ; 4 . 11 4 4 . 11
6 . 8 ; 6 . 4 ; 6 . 0 ; 4 . 3 ; 4 . 7 ; 4 . 11 4 4 . 11
− − − + + + ⇒ ⋅ t +
+ + + − − − ⇒ ⋅ t −
This is indeed the result we observe in the spectrum of the current signal.
ix
The rays due to the
input noise tone may also be seen as time or phase modulated sidebands, as discussed in section
6.2.3. The sidebands appear at a frequency offset of t 1.4MHz around the odd harmonics of f
clk
.
There are also rays at the frequencies n.4MHz. These even rays of the fundamental appear
because of the pulses that are caused by the reset input.
The differential Q signal has rising edges that are determined by the current signal
(IT(“/Q10/C”) IT(“/Q11/C”). Therefore the Q output samples this current signal every 1/f
clk
. So
the output will present rays at: tf
n
t n.f
clk
with n ∈ N, or in other words it will present
sidebands at t0.6MHz and t1.4MHz . This expectation is once more verified by the simulation.
Finally we can calculate the expected L(f) of these sidebands and compare it to the level found in
the simulation. We start with the sidebands of the current signal.
The peak amplitude of the added noise tone in the clock input equals 25mV. The slope of the
differential clock input equals:
( )
s
V
c
M
ns
mV
dt
t dv
16
25
200 2
·
⋅
·
, with t
c
a zero crossing
instant. If we suppose that H
PLS
(f) is close enough to a comb sampler, the rays that are frequency
translated at f
clk
t1.4MHz will present the same amplitude as the ray at 11.4MHz. Therefore we
make an analogy with equation (6.12), and we find the time deviation:
( ) ( ) s n
M
mV
MHz t f t
s
V
peak n offset peak n
5625 . 1
16
25
4 . 1 · · ∆ · ∆
− −
Next we use the relationships between time and phase deviations to find ∆ϕ
npeak
:
( ) ( ) ( ) rad m f t f f
offset peak n clk offset peak n
63 . 19 2 · ∆ ⋅ ⋅ · ∆
− −
π ϕ
So the L(f) of the sidebands in the current signal are estimated as:
( )
( )
dBc
f
f L
offset peak n
offset dB
16 . 40
2
log 20 − ·
]
]
]
∆
⋅ ·
−
ϕ
(7.7)
ix
We remark that figure 7.7 is a single sided frequency representation, so with respect to figure 7.5 the “negative”
frequencies are folded in the positive side of the frequency axis.
Chapter 7 / Phase Noise in the PLL context 157
In the simulation result the sidebands at t1.4MHz around f
clk
, have an amplitude that is
40.51dB below the amplitude of the fundamental. So the estimation of L(f) in equation (7.7) is
quite accurate, which means that our periodic transfer H
PLS
(f) in this simulation is indeed close to
a comb sampler. This result is reconfirmed by the fact that the rays at f
n
t2.n.f
clk
all have similar
amplitudes within the frequency range that is plotted.
If we continue to suppose a comb transfer from the signal current to the Q output, we expect to
find sidebands with an equal amplitude at the frequency offsets of t0.6MHz and t1.4MHz. The
level of these sidebands should be reduced by 3dB with respect to the sidebands in the current
signal, because only the rising edges are transmitting the phase disturbances. So the expected
L(f) equals:
( ) ( ) dBc MHz L MHz L
dB dB
16 . 43 6 . 0 4 . 1 − · t · t
The output of the simulations shows a L(f) of –44.4dBc, which is still reasonably accurate.
This example shows that the periodic transfer of added noise sources can be accurately estimated
by the large signal linearization (transfer represented by H
PLS
(f)). The numerical application
holds even for rather large perturbations such as the superposed tone used in this simulation.
In a PLL that has resynchronized dividers, we may concentrate our attention on a few nodes to
determine the total time noise density that is transmitted to the phase detector input by the logical
blocks. Once more the logical blocks are the phase detector, the reference and the main divider.
If the resynchronization stages and the phase detector are composed of DFFs that have similar
biasing levels, we can try to find the one that represents the critical path with respect to the noise
performance. It is often the reference chain, due to the broad band noise floor that outputs the
crystal oscillator (Xosc). If we consider that the output of the Xosc has a buffering stage that is
rather nonlinear, with steep edges and T
w
tending to zero; the broadband noise is then sampled
to a Nyquist bandwidth equal to f
xosc
. Later on it is downsampled by the resynchronization
stage, which causes a new folding to a Nyquist bandwidth of f
cp
/2 . Equation (7.5) can be used to
define a folding factor n
lim
for the noise coming from the Xosc. It equals:
R
f
f
f
bw
f
bw
n
cp
xosc
cp sample
Xosc n
cp Nyquist
Xosc n
⋅ ·
⋅
·
⋅
· ·
−
−
−
−
2
2 2
lim
(7.8)
where R is the dividing ratio of the reference divider.
The noise of the Xosc that is transmitted to the phase detector input is then estimated using
equation (7.6). It becomes:
( ) [ ]
2
for ; 2
lim
input detector
phase at the
cp
Hz
V
no no Xosc n
f
f R V n V f v ≤ ⋅ ⋅ · ⋅ ·
−
δ
(7.9)
The noise contribution of this broad band noise has a 3dB/octoff
cp
behaviour as discussed in
table 73. The value of V
no
can be obtained by noise simulations using software that calculate a
periodic transfer for the noise.
158 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
7.3.2 Charge Pump
The simulation concerns a phase detector and a charge pump blocks that were designed to work
with very high comparison frequencies, to the order of 310MHz. It is part of a multiloop PLL
structure that is discussed in chapter 8.
The inputs of the phase detector are adjusted to correspond to a locked loop situation with an
average current output equal to zero. Due to the elevated comparison frequency the charge pump
that has slow pnp current sources, acts like a lowpass filter. The output currents sinking and
sourcing are a filtered copy of the input impulses of the phase detector. We know that the
minimum width of these impulses equals τ
rst
. Here the ratio τ
rst
/T
cp
approaches 1/3 and
consequently the current sources are never completely switched off. Therefore the noise
contribution of the charge pump block can become very significant for the total phase noise
performance.
A series of noise simulations is realized around different points of a time domain simulation. The
points are chosen within an interval of one period, and, after the transient signals have attained a
periodic steady state, this corresponds to the lockedloop condition.
The current noise densities that were calculated for the different transient points had roughly a
white bandlimited shape with a cutoff frequency around 30MHz. The level of the current noise
density at a frequency of 1MHz is sketched in figure 7.8. It corresponds to an instantaneous
value calculated for a given time instant in a period. We indicated it as:
δi
ChPinstant
(1MHz) .
Figure 7.8 Charge Pump current noise levels within one period
In figure 7.8 the peak of noise level occurs during the zero crossing of the inputs that command
the charge pumps. The total noise contribution of the charge pump is a time average of the
instantaneous noise power levels. Here it becomes:
( )
( ) ( )
Hz
A
n
n
p
n
n
p
T
T
i
T
T
i MHz i
cp
inst ChP
cp
inst ChP total ChP
2
22 2 2
2 2
2 .
1 2
1 .
2
10 . 768 . 9
2 . 3 2
150 . 0
140
2 . 3
9 . 2
8
... 1
−
− − −
·
⋅
⋅ + ⋅ ≈
+ ⋅ + ⋅ · δ δ δ
The current density is transformed into a phase density using K
ϕ
, and finally expressed as a SSB
phase noise, as follows:
300ps
t
[s]
140p
8p
δi
ChPinstant
(1MHz)
A/sqrt(Hz)
n.T
cp
(n+1).T
cp
δiChPinstant(f)
8p A/sqrt(Hz)
f
[Hz]
30M
T
cp
=3.2ns
I
cp
=182uA
Chapter 7 / Phase Noise in the PLL context 159
( )
Hz
rad
p
K
i
MHz
total ChP
total ChP
µ π
µ
δ
δϕ
ϕ
079 . 1 2
182
25 . 31
1 · ⋅ · ·
−
−
( )
( )
Hz
dBc
MHz
MHz L
total ChP
total ChP dB
35 . 122
2
1
log 20 1
_
− ·
,
`
.

·
−
−
δϕ
This calculation is useful to estimate the limitation of the noise performance that is imposed by
such a charge pump working with a high f
cp
. The calculation is compared to measurement
results in chapter 8.
7.4 Behavioural Models
The behavioural model is a synthetic form to represent different blocks of a circuit. It is used to
simulate an ensemble of blocks that interact among each other. Often they become interesting
when a simulation using the full circuit description would demand too much memory and/or time
. We may model all the circuit blocks in behavioural descriptions or combine behavioural and
circuit level descriptions. The following sections present briefly some points about a behavioural
representation of the PLL synthesizer, for simulations in the time and in the frequency domains.
Numerical examples are presented in chapter 8 while discussing the results of the testchips.
7.4.1 Frequency domain
A behavioural description of the PLL may represent the output of the VCO and the Xosc by
their respective phases. This phase model greatly simplifies the representation of the dividers that
may directly divide the phase values instead of identifying and counting zerocrossing moments.
The PLL phase model that was presented in figure 2.1, is very close to a behavioural model that
may be used for AC and noise simulations. In an analog simulator the phase signals have to be
transformed in either voltage or current magnitudes. We choose to represent the phase signals as
voltages. The dividers are replaced by voltage controlled sources that have an output equal to
1/N or 1/R times their input.
The integration of the phase model of the VCO is represented by measuring the ddp of a
capacitor that integrates a current. For a noise simulation we introduce two noise sources that
represent N
pll
and v
nvco
. In figure 7.9 the noise input of N
pll
is replaced by a source that
represents the noise of the crystal oscillator. The aliasing factor sqrt(2.R) is also included through
the gain block that follows the noise source. The loop filter is an active one. The amplifier is
represented by a transconductor with a capacitive input impedance, and the output impedance
equals the pullup resistor.
This model may also be used for AC simulations that verify the open and closed loop transfers.
160 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Figure 7.9 Behavioural model of the PLL for AC and noise simulations
The output PHIvco (ϕ
vco
) in this behavioural model may be used to calculate the total phase jitter
of the LO signal. In fact ϕ
vco
equals the mean square phase fluctuation S
ϕ
(f) (equation (3.5) ).
The total phase deviation or phase jitter, σ
ϕ
, is then derived by integrating S
ϕ
(equation (3.21) ).
The boundaries of the integral are related to the bandwidth of the channel that is being down
converted.
In section 7.5 we continue to discuss these integration boundaries as we consider the
implementation losses that are caused by σ
ϕ
.
7.4.2 Time domain
The behavioural representation in the time domain also uses phase models for the dividers.
However it is interesting to represent the phase detector and charge pump in a form that is
compatible with their circuit description, so that we may combine behavioural and circuit blocks.
Chapter 7 / Phase Noise in the PLL context 161
Figure 7.10 shows a combined model that contain behavioural descriptions for the dividers and
phase detector, and a circuit level charge pump and loopfilter amplifier. This schematic is used
to observe the transient residual currents that are due to mismatches between the sourcing and
sinking sides.
Figure 7.10 Behavioural model of the PLL for transient simulations
The accuracy of simulations in the time domain is closely related to the ratio timestep/signal
period. The time step is the space between two consecutive points that are calculated in the
transient simulation. In an ensemble of blocks that work with different frequencies, we should
consider the smallest period.
The difficulty to simulate the full PLL circuit is connected to the large difference between the
period of the signals at different points of the loop. In this transient model we reduce this
difference of periods changing the parameters K
vco
and N. In fact the VCO is represented by its
phase and this phase is divided before it is retransformed into a sinusoidal signal. Therefore we
may simply divide K
vco
and N by a common factor, and reduce significantly the difference
between the comparison frequency and the frequency of the VCO.
162 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
7.5 Implementation Loss due to Phase Deviations
Implementation loss is the difference between the theoretical limits that are calculated for the
correct functioning of a system and the limits that are measured in a physical implementation.
Here, we discuss the implementation loss that is caused by the phase deviations in the LO signal.
The numerical values are related to the reception of a QPSK modulated channel in a satellite
receiver.
In the frontend or more specifically in the frequency conversion stage, the phase jitter of the LO
adds noise to the RF data being downconverted.
The circuit that receives the BB output from the frontend is a digital demodulator and decoder
(see figure 7.11). The first part, demodulator, is composed of the following blocks: ADC, clock
recovery loop and carrier recovery loop. The decoder is the second part, and it contains the
stages of forward error correction.
Figure 7.11 Digital Demodulator and Decoder
For digital modulations, the final consequence of phase jitter is measured as a biterror rate
(BER)
x
. In the case of QPSK signals the bit error rate reflects the probability that the additional
phase noise exceeds a value of π/4 .
xi
Thus, for phase noise contributions that present a Gaussian distribution and a mean square value
or variance of σ
ϕ
, we can calculate the BER using the distribution curves of a Gaussian variable.
Usually these results are presented in graphs of SNR versus BER. They show the theoretical and
minimum signal quality that is required to
decode the input signal with a certain amount of biterrors. The SNR is often indicated as a
power density ratio: energy per bit over noise, E
b
/N
o
, that normalizes the signal power with
respect to the bit rate.
The decoder can correct a certain number of bit errors depending on the redundancy and the
robustness of the coding. MPEG standards for video coding impose BER to the order of 10
11
at
the output of the decoder. For the satellite DVBS that has an inner ReedSolomon coding and an
outer Viterbi coding; this implies a BER to the order of 2.10
4
at the input of the Reed Solomon
x
The BER is a common unit used in the context of digital decoders. It measures the amount of errors encountered in
the reception of a bit stream.
xi
Referring to a constellation diagram, as represented in figure 1.7 .
SDD: satellite demodulator and decoder
Frontend
Forward Error Correction
Viterbi
Decoder
ReedSolomon
Decoder
Demodulator
ADC Clock & Carrier
Recovery Loops
RF
input
LO
PLL
Chapter 7 / Phase Noise in the PLL context 163
decoder, and a BER to the order of 6.10
3
at the input of the Viterbi decoder. The BER in the
input of the decoder is also called raw BER.
Using the theoretical curves of SNR x BER for QPSK signals we find that the raw BER of 6.10
3
is equivalent to a theoretical E
b
/N
o
of 5dB. We may also express the SNR as an energy per
symbol instead of an energy per bit, which gives us a E
s
/N
o
of 8dB. The implementation loss is
measured as the increase in the ratio E
s
/N
o
which is required to obtain a raw BER of 6.10
3
.
7.5.1 Signal to noise ratio and implementation loss
The following treatment of the implementation loss and phase noise power is based on the
reference [Sinde98b].
Let us consider the signal and noise powers indicated in the schematic below:
where
P
s
: signal power measured within the bandwidth bw
ch
;
P
Nin
: noise power before the mixing stage, also measured within bw
ch
;
P
Nϕ
: noise power added by the phase noise of the LO, measured within bw
ch
.
For an ideal receiver working with a noiseless local oscillator, SNR
in
and SNR
min
are equal, and
they become:
1
1 min
Nin
s
in
P
P
SNR SNR · ·
where P
Nin1
is the maximum noise power that can be handled by the receiver.
When we consider a noisy LO the SNR
min
equals:
ϕ
ϕ
ϕ
SNR SNR
P
P
P
P P P
P
SNR
in
s s
Nin N Nin
s
1 1
1 1
2
2 2
min
+
·
+
·
+
·
where P
Nin2
is the maximum noise power at the input, in the presence of the phase noise P
Nϕ
; and
SNR
ϕ
is the signal to noise ratio for the phase noise contribution.
The implementation loss (IL) due to P
Nϕ
is defined by the ratio of the input SNR for the noisy
and noiseless cases:
ϕ
SNR
SNR
P
P
SNR
SNR
IL
Nin
Nin
in
in
min
2
1
1
2
1
1
−
· · ·
It may also be expressed in dB as:
]
]
]
]
− ⋅ − ·
,
`
.
 −
− −
10
min
10 1 log 10
dB dB
SNR SNR
dB
IL
ϕ
(7.10)
where SNR
mindB
and SNR
ϕdB
are the same ratios defined above, but expressed in dB.
We can also calculate the SNR
ϕ
which corresponds to a given IL and SNR
min
. It equals:
S
SNR
min
P
s
P
Nin
P
Nϕ
164 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
1
min
−
⋅ ·
IL
IL
SNR SNR
ϕ
or expressed in dB:
]
]
]
]
− ⋅ − + ·
,
`
.

− −
1 10 log 10
10
min
dB
IL
dB dB dB
IL SNR SNR
ϕ
(7.11)
Let us now consider the relationship between SNR
ϕ
and the phase noise parameter S
ϕ
(f) which
was introduced in chapter 3. The latter is a noise to signal ratio, that considers the noise
contribution of a 1 Hz bandwidth in a certain offset from the carrier. The first one is a signal to
noise ratio that considers the noise within the bandwidth of the selected channel (bw
ch
). So, we
expect the integral of S
ϕ
(f) to be related to SNR
ϕ
1
.
Indeed, if we consider the phase noise sidebands as narrow band noise contributions that are also
downconverting the input channel, we find that:
( ) ( )
offset
bw
f
bw
f
bw
f
bw
ch s
N
df df f S df f S
bw P
P
SNR
ch
offset
ch
offset
ch
offset
ch
∫ ∫ ∫
]
]
]
]
]
⋅ + ⋅ · ·
,
`
.

+
,
`
.

−
,
`
.

−
−
2
0
2
2
2
0
1
2
1 2
ϕ ϕ
ϕ
ϕ
(7.12)
1 −
− foffset
SNR
ϕ
where the noise being added corresponds to the frequencyshifted copies of the input channel.
We should remember that S
ϕ
(f) is the double side band phase noise, which explains that the
boundaries of the integral are limited to positive offsets.
Figure 7.12 gives a physical idea of the integral above. It shows the noise contribution that is
brought by two narrow sidebands around the oscillator frequency.
Figure 7.12 Noise Power added by the LO sidebands
∆f
1
f
offset
,
`
.

∆ −
1
2
f
bw
ch
∆f
1
S
s
(f)
[W/Hz]
f [Hz]
bw
ch
S
osc
(f)
[W/Hz]
f [Hz]
,
`
.

∆ +
1
2
f
bw
ch
f [Hz]
f [Hz]
S
BBoutput
(f)
[W/Hz]
S
BBoutput
(f)
[W/Hz]
f
offset
Chapter 7 / Phase Noise in the PLL context 165
The outermost integral in expression (7.12) sweeps the channel bandwidth from its center to one
of the extremities. The inner integral evaluates the noise power that is projected over each
narrow bandwidth portion of the channel spectrum. The noise amount that is projected on two
sidebands that are equally spaced with respect to the center of the channel bandwidth, is equal.
Therefore the outermost integral just needs to sweep a range of one half channel.
However, depending on the position of the narrow bandwidth within the channel spectrum, it is a
different range of the DSB phase noise, S
ϕ
(f), that downconverts or projects noise. For offsets
close to the center of the channel, or for f
offset
<< bw
ch
, it is basically S
ϕ
(f) in the range [0,
bw
ch
/2], where the DSB phase noise accounts for the left and right sided offsets from the center
of the channel. For offsets close to the extremities of the channel, or for f
offset
~ bw
ch
/2 , it is
S
ϕ
(f)/2 in the range [0, bw
ch
].
In expression (7.12), the total noise, P
Nϕ
, is the sum of the noise contributions that are down
converted by the sidebands around the LO. In the present case, where we consider a single
channel at the RF input, the maximum frequency offset for these sidebands equals bw
ch
.
Next, two particular cases, concerning random and spurious sidebands, are discussed.
7.5.1.1 Spurious Sidebands
Discrete spurious sidebands are also contributing to P
Nϕ
. If we consider a pair of sidebands at a
frequency offset f
1
, the DSB phase noise can be expressed as:
( ) ( ) [ ]
2
1 1 1
rad f f P f S
s
− ⋅ · δ
ϕ
for
ch
bw f < <
1
0
where P
s1
is the DSB spurious amplitude. It may also be expressed in dB, P
s1dB
, and compared
to A
s
, the SSB spurious amplitude defined in equation (3.2).
[ ] dBc dB A P
s dB s
3
1
+ ·
−
(7.13)
Then, replacing S
ϕ1
in expression (7.12) results in:
[ ]
2 1
1
1
1
1 rad
bw
f
P SNR
ch
s
,
`
.

− ⋅ ·
−
ϕ
for
ch
bw f < <
1
0
{ ¦ [ ]
2
1
1
1
max rad P SNR
s
<
−
ϕ
(7.14)
Therefore P
s1
is an overestimation of the SNR related to these single tone sidebands.
7.5.1.2 Random Phase Noise
The random noise sources that modulate the tunable oscillator cause sidebands that are measured
by a phase noise density, S
ϕ
(f). These sidebands may be divided into two zones. The first, in
loop, is mostly flat with some peaking close to the intersection of the outofloop zone. In the
second one, the power of the sidebands decreases with a 1/f slope. The PLL closed bandwidth
(f
cl
) determines the size of the inloop zone.
Most of the phase deviation power is due to the sidebands that are found in frequency offsets in
the range [0 , f
cl
] .
166 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
In most of the tuner applications, the PLL bandwidth is considerably smaller than the channel
bandwidth (bw
ch
) . Thus the parameter
1 −
− foffset
SNR
ϕ
in expression (7.12) is bounded by:
( ) [ ]
2
2
0
1
0 _
1
_
rad df f S SNR SNR
ch
bw
foffset
∫
· ≤
− −
ϕ ϕ ϕ
Furthermore the value of
1 −
− foffset
SNR
ϕ
is rather close to
1
0
−
− ϕ
SNR for all the frequency offsets that
are in the range: [0 , bw
ch
f
cl
] .
If we replace
1 −
− foffset
SNR
ϕ
by
1
0
−
− ϕ
SNR in equation (7.12), we obtain a simplified form of
1 −
ϕ
SNR
that equals:
( )
∫ ∫
· · · ⋅ ≈
− − −
2
0
2 1
0 _
2
0
1
0 _
1
2
ch ch
bw
offset
bw
ch
df f S SNR df SNR
bw
SNR
ϕ ϕ ϕ ϕ ϕ
σ (7.15)
Expression (7.15) is an overestimation of
1 −
ϕ
SNR for the random noise sidebands; and it equals
the square of the phase jitter, for an integration within half of the channel bandwidth.
7.5.1.3 Numerical Example
The specifications of a receiver system define allocations of implementation losses for the
different parameters causing signal degradations. In TV and satellite tuners the implementation
loss due to phase deviation of the LO are specified by a maximum value of 0.2dB.
We can use expressions (7.10) and (7.11) to calculate some numerical examples for the satellite
QPSK receiver. Table 74 relates SNR
ϕ
and IL for a E
s
/N
o
of 8dB, corresponding to the raw BER
of 6.10
3
.
IL
dB SNR
ϕdB
1 −
ϕ
SNR
1 −
ϕ
SNR
[dB] [dB] [rad] [°]
1.6 13.112 2.210E01 12.662
0.8 15.741 1.633E01 9.356
0.4 18.556 1.181E01 6.766
0.2 21.467 8.446E02 4.839
0.1 24.428 6.006E02 3.441
0.05 27.413 4.259E02 2.440
0.025 30.411 3.016E02 1.728
Table 74 Implementation Loss X Phase deviations
We may also use expressions (7.13), (7.14) and (7.15) to relate the values of SNR
ϕ
with the
spurious level (A
s
) and the phase jitter (σ
ϕ
) .
For instance the implementation loss of 0.2 dB is equivalent to a phase jitter of 4.84°, or to a
single pair of spurious sidebands at – 24.5 dBc.
Chapter 7 / Phase Noise in the PLL context 167
In practise the maximum
1 −
ϕ
SNR has to take into account both the phase jitter and the spurious
power. Hence we should seek a practical boundary that compromises the phase deviation of the
random and spurious noises and also preserves a margin for variations in the parameters that
determine A
s
and σ
ϕ
.
xii
A phase jitter of 2° and a spurious level below –36dBc is a compromise that implies a total
SNR
ϕdB
of 28.2 dB,with a margin of 6.7 dB for the variation of the total phase deviation.
7.5.2 Digital Demodulator: clock and carrier recovery loops
Finally we need to consider the action of the demodulator blocks (carrier and clock recovery
loops) for the phase deviations that come from the frontend.
There are different configurations of carrier and clock recovery loops, our model is based on the
architecture of the circuit TDA8043, a satellite demodulator and decoder for BPSK and QPSK
signals.
The behavioural model for the phase transfer of the clock and carrier recovery loops is shown in
figure 7.13.
Figure 7.13 Behavioural Model of the Carrier Recovery loop
The two loops are based on PLLs of the 2
nd
order. The clock recovery loop is the external, slow
loop, which works with the smaller closed loop bandwidth. There are three stages that are
contained in the clock recovery loop: the antialias filtering, the Nyquist filtering and the
interpolator. These stages are only represented by the delays that they cause in the signal path
(block delay_2). The length of this delay depends on the symbol rate.
xii
The spurious level, A
s
, depends on the amplitude of the modulating signal, on the frequency sensitivity of the
oscillator (K
vco
), and on the suppression of the loop filter. The phase jitter, σ
ϕ
, depends on the noise performance of
the PLL and the VCO ( N
pll
, v
nvco
), on the peaking of the closed loop transfer and on the closed loop bandwidth.
Clock recovery loop Carrier Recovery loop
168 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
There are other delay elements that account for the phase detectors functioning. These delays are
independent of the symbol rate.
The carrier recovery loop is the internal, fast loop. The bandwidth and damping parameters of
each loop are programmable. In the behavioural model these settings are translated to the loop
filter parameters that correspond to a 2
nd
order closed loop transfer with a natural oscillating
frequency w
n
and a damping ξ .
The ensemble of the demodulator blocks is synchronous, and it works with a clock at 65MHz.
Therefore the delays may be normalized as an entier number of periods of the reference clock.
The TDA8043 can decode channels with variable symbol rates. The maximum symbol rate that
can be decoded is 32Msps. For symbol rates below 10Msps, the loops should be interlaced (an
external clock loop containing the carrier loop) as represented in figure 7.13. For symbol rates
above 10Msps, the two loops should be connected in series. For the phase model, the series
connection just changes the feedback return for the clock recovery loop, which would be taken
from the node at the input of the carrier loop.
The overall transfer of the demodulator is very close to a high pass filter of 2
nd
order, with a
cutting frequency that equals the natural frequency of the fast loop. As we increase the
bandwidth of either loop, the effect of the delays will become visible, causing some overshoot in
the transfer.
The phase model of the demodulator is used in noise simulations in combination with the PLL
phase model. The demodulator input (PHIdemin) receives the phase noise density that outputs
the PLL. The output of the demodulator is a highpass filtered portion of ϕ
osc
.
The combined PLL+demodulator model is used to calculate the phase jitter that appears at the
input of the digital signal decoder. In this manner, the IL that is measured at the input of the
decoder, can be correctly compared to a phase jitter value. Simulation examples are presented in
chapter 8.
In this chapter we applied the results of the preceding parts, about the PLL model and the related
transfer functions, and, about the generation of phase noise.
The analysis of a PLL design, in a topdown approach, was discussed with numerical examples
related to existing ICs.
A systematic approach to investigate the dominant noise sources was presented, with suggestions
for simulations and measurements.
Finally, behavioural models for transient and AC simulations were briefly described. A model
for a QPSK demodulator, used in the analysis of chapter 8, was also introduced.
Chapter 8 / Testchips Realized 169
Contents:
8. Testchips Realized 169
8.1. GmC oscillator..................................................................................................................................... 170
8.1.1. Structure ...................................................................................................................................... 170
8.1.2. Results ......................................................................................................................................... 172
8.2. TC2 : MixerOscillatorPLL circuit for satellite direct conversion..................................................... 173
8.2.1. Double Loop Synthesizer ............................................................................................................ 173
8.2.2. TC2 structure............................................................................................................................... 175
8.2.3. TC2: results ................................................................................................................................. 177
8.3. TC3 : single PLL plus QCCO circuit .................................................................................................... 180
8.4. Comparative analysis: phase jitter and implementation loss................................................................ 183
8.4.1. Configurations compared ............................................................................................................ 183
8.4.2. Conditions for the simulations..................................................................................................... 184
8.4.3. Results and conclusions............................................................................................................... 187
Figures:
Figure 8.1 GmC integrated oscillator .......................................................................................... ............ 171
Figure 8.2 Double loop MOPLL: block diagram..................................................................................... 174
Figure 8.3 Block diagram of TC2 .............................................................................................................. 176
Figure 8.4 Photo of a testchip TC2............................................................................................................ 177
Figure 8.5 TC2 _ inloop spectrum for N1=7 and f
cp1
=300Mhz............................................................. 179
Figure 8.6 TC2 _outofloop spectrum for N1=6 and f
cp1
=300MHz ...................................................... 179
Figure 8.7 TC3 _ single low noise PLL plus QCCO................................................................................ 181
Figure 8.8 Simulation result for the SSB phase noise _ linear scale....................................................... 182
Figure 8.9 Spectra for ∆f
step
=125kHz and f
lo
=900MHz .......................................................................... 186
Figure 8.10 Phase noise simulation for DL+QCCO with and without demodulator .............................. 186
Tables:
Table 81 Measurements of the frequency coverage of the QCCO....................................................... 172
Table 82 Double Loop: minimum step and comparison frequencies................................................... 175
Table 83 Parameters of the two zeroIF configurations being compared ........................................... 183
Table 84 Parameters and outputs for comparative analysis ................................................................ 184
Table 85 Settings of the demodulator block........................................................................................... 185
Table 86 Phase Jitter and implementation loss for r
s
=30Msps and f
LO
= 2,2GHz.............................. 188
Table 87 Phase Jitter and implementation loss for r
s
=3Msps and ∆f
step
= 125kHz............................. 188
Table 88 Margin for degradations in the oscillators phase noise performance .................................. 189
8 Testchips Realized
This chapter presents two synthesizer testchips which contain a fully integrated GmC oscillator
covering the satellite bandL. The synthesizers are designed for a monodyne or zeroIF receiver,
and they present a multiloop architecture.
The structures of the GmC oscillator and a double loop PLL synthesizer are exposed in tables
and block diagrams. The performance of the double loop synthesizer, with an integrated satellite
band oscillator, is compared to a classical single loop and external LC oscillator. Finally
measurement results of phase noise and implementation losses are compared to simulations.
170 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
A fully integrated oscillator becomes quite interesting in monodyne receivers where the radiation
of the input RF signal may significantly deviate a LC externallycoupled oscillator.
In terrestrial and satellite tuners the usual range of the tuning voltage is 30V. This high voltage
supply can be suppressed if the LO can be tuned under a 5V range.
The integrated GmC oscillator has a range divided into 4 bands that are tuned in a 5V range. Its
phase noise is on average 20dB worse than a LC oscillator covering the same range with a 30V
tuning range. The solution, to cope with the degradation of the phase noise, is to increase the
closed loop bandwidth. In order to respond to both the specifications of a maximum tuning step
and a minimum closed loop bandwidth, a multiloop structure is needed.
The first testchip that is discussed, TC2, is an implementation developed in collaboration with
Nat.Lab. the research laboratory of Philips. It is a doubleloop PLL synthesizer. The first loop
drives an oscillator in the VHF band, which is used as the input reference for the second loop
which drives the GmC oscillator. The two oscillators are tuned in a 5V range.
The second testchip, TC3, exploits the possibility of a single loop, with a wide closed bandwidth,
to drive the same GmC oscillator. The input reference in this case is a crystal oscillator.
The testchips were realized in a bipolar process that is derived from a BiCMOS process. The
stripped bipolar process kept the gate oxide of the CMOS components for the capacitors. This
enables us to compose a native PMOS, which gives us a bipolar+PMOS process. The peak value
of the ft of the NPN transistors equals 13GHz. The maximum ft of the lateral PNP equals
200MHz. There are three levels of metallization, with a pitch of 2.4µm.
We start describing the results of the GmC oscillator, which is a common block in the two
testchips. A fuller description of the double loop structure and the GmC oscillator can be found
in references [Vauc98] , [Tang97] and [Kokk92].
8.1 GmC oscillator
The GmC oscillator is a ring structure with two integrator stages and an inverting feedback. The
two stages have outputs with an equal frequency, and phases that are shifted by 90° with respect
to each other.
i
The oscillating frequency depends on the value of the capacitors and on the
transconductance Gm. The frequency tuning is made by varying the biasing current of the
transconductance stages. Hence the oscillator is also called a QCCO: quadrature current
controlled oscillator.
8.1.1 Structure
Let us consider the block schematic of figure 8.1. It shows the basic parts of the QCCO. Part
8.1.a presents a single ended integrator stage. The transconductance gm
a
compensates the current
i
These quadrature outputs are very convenient for a receiver with a monodyne structure. A monodyne receiver
needs to provide two outputs, in quadrature to each other, so that the demodulator can distinguish the channel from
its mirror image. In a zeroIF architecture the mirror image is a flipped version of the selected channel, which is also
converted to base band.
Basically there are two possibilities to provide the two outputs in quadrature: either phase shifting the input RF
channel, or having a LO oscillator with quadrature outputs. The second solution is often chosen because it demands
a phase shifter for a single tone signal, instead of a large bandwidth shifter.
Furthermore the digital standards of satellite broadcasting use QPSK modulation. Therefore the quadrature outputs
may be directly sampled and demodulated to retrieve the I and Q streams of data.
Chapter 8 / Testchips Realized 171
losses in the resistor R, keeping the quadrature between the input and output voltages v
in
and
v
out
. Implementation in the testchips uses differential transconductances gm
t
and gm
a
as drafted
in figure 8.1.b.
Fig.8.1.a Single ended GmC integrator Fig.8.1.b Differential cascaded integrators
Figure 8.1 GmC integrated oscillator
The condition of oscillation, a unitary feedback with a phase shift of 360° , is met by cascading
two integrator stages and an inversion. In the differential scheme the inversion is simply a
crossover between the feedback signals.
If the transconductance gm
a
compensates exactly the losses of each integrator stage
( )
R
gm
a
1
− ·
, the closed loop transfer function for a voltage input becomes:
( )
2
1
1
,
`
.
 ⋅
+
·
t
QCCO
gm
C s
s B
(8.1)
where the transfer of a single integrator is :
( )
( )
n
t
in
out
w
C s
gm
s V
s V
·
⋅
· ;
which is also equal to the natural oscillating frequency w
n
.
This situation is identified as the linear mode of the QCCO. In practice an amplitude control, that
acts on gm
a
, is needed to assure a minimum negative impedance during the start up of the
oscillator and later on to fix the value of the amplitude.
The phase noise performance of the QCCO depends: on the inherent noise sources, on the
frequency sensitivity of the oscillator and on the amplitude of the signals V
I
and V
Q
.
We can define a frequency sensitivity K
cco
in Hz/A .
If we decrease K
cco
by increasing the capacitors C, we will need a higher I
gmt
to cover the
frequency range, which implies an increase in some noise sources that are proportional to the
biasing currents.
On the other hand, as we increase the amplitude of the oscillating signal the transconductors gm
t
will no longer work in a linear mode, and the losses due to this nonlinear function have to be
compensated by the negative resistance, or in other words by increasing I
gma
.
C R
I
gmt
gm
t
v
out
v
in
I
gma
gm
a
vQ vI
gmt (tune)
gma (amp)
gmt (tune)
gma (amp)
I
gmt
I
gma
I
gmt
I
gma
172 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
In fact I
gma
is already the parameter that controls the amplitude, and, for oscillators working in a
nonlinear mode the amplitude control is also influencing the frequency. Therefore the design of
the QCCO is a tricky compromise between the requirements of phase noise, tunable range and
consumption budget.
8.1.2 Results
The QCCO implemented in TC2 and TC3 has a frequency range divided into 4 bands. The bands
are selected by programmable inputs. The frequency range covers the entire bandL from
950MHz to 2150MHz, with some overlap in the extremities and in between each band. The
outputs V
I
and V
Q
have a peak value to the order of 200mV to 300mV. This amplitude represents
the result of the compromise between consumption and phase noise performance. The ensemble
of the biasing and transconductance blocks consume 26mA under a 5V bias.
The first design was reworked to improve the band coverage and the uniformity of the K
cco
and
the L(f) throughout the 4 bands.
ii
The measurement results are presented in table 81, in
comparison to the ideal band partition shown below. The overlap for the limits of each band is
chosen as 100MHz.
Ideal band partition:
MHz MHz f 425
4
300 850 2250
band
·
+ −
· ∆
Measurements:
Band 1 Band 2 Band 3 Band 4 measurement conditions:
Frequency
Ranges
[MHz]
815

1230
1190

1640
1520

1950
1850

2310
∆f
band
[MHz] 415 450 430 460
K
vcco
[MHz/V]
119 129 123 131
constant V
amp
=2.6V
V
tune
∈ [0.1 ; 3.6]
Table 81 Measurements of the frequency coverage of the QCCO
The frequency sensibility K
vcco
is equivalent to the K
vco
of the LC tuned oscillator. The tuning
input of the QCCO is a voltage/current (V/I) converter that receives V
tune
as input, and output I
gmt
ii
The bands have an equal frequency range, that enables a simple programming mode for the QCCO, and assures a
low K
cco
variation throughout the band.
1175M
1600M
1825M 2250M
1500M
950M 1275M
850M
1925M
2150M
Chapter 8 / Testchips Realized 173
. The parameter K
vcco
is the overall sensitivity that includes the gain of the V/I converter plus
the K
cco
of the GmC oscillator. The input range for V
tune
is limited by the working range of the
V/I converter.
A second V/I input is used for the amplitude control, and its input is called V
amp
. The present
design was improved to work with a fixed V
amp
value, so that this input can be used to
compensate the process spread.
The same uniformity was also aimed at for the SSB phase noise performance, and the following
values are measured in the two extremes of the tunable range:
( ) ( )
Hz
dBc
Hz
dBc
QCCO
KHz L KHz L GHz f 8 . 76 100 4 . 92 600 2 . 1 − · ↔ − · ⇒ ·
( ) ( )
Hz
dBc
Hz
dBc
QCCO
KHz L KHz L GHz f 9 . 75 100 5 . 91 600 1 . 2 − · ↔ − · ⇒ ·
At the beginning of the band the main noise source is the thermal noise of the resistors loading
the transconductors; and at the end of the band the L(f) is limited by the shot noise of the
transistor of gm
t
. The noise from the biasing stages is minimized by using a large voltage
interval for the degeneration of the current sources.
8.2 TC2 : MixerOscillatorPLL circuit for satellite direct conversion
The testchip TC2 contains several blocks of a double loop PLL synthesizer. The synthesizer chip
is combined with mixeroscillator blocks to compose a MOPLL circuit. The circuit is
dimensioned for a monodyne receiver, which means that the input RF channels are directly
downconverted to band base.
8.2.1 Double Loop Synthesizer
Figure 8.2 is a block schematic of the double loop architecture.
The tuning system is composed of two cascaded PLLs. The first one (loop #1) locks the QCCO
to the reference delivered by the second loop. Loop #1 works with small divider ratios (N1)
which allows one to obtain a quite low phase noise for part of the inloop spectrum (to the order
of 108 dBc/Hz).
Loop #2 drives an oscillator that works in the VHF range. This VHFoscillator has a strict
requirement for phase noise, since its spectrum is “copied” to the LO output.
The reference of loop#2 is a traditional 4MHz quartz oscillator (Xosc). The reference divider is
composed of two counters, one is programmed with the same count (N1) as the divider of loop
#1, and the other (R2) determines the minimum tuning step.
Table 82 shows the relationships among the comparison frequencies and the oscillator
frequencies.
174 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Figure 8.2 Double loop MOPLL: block diagram
Parameters:
∆f
step
: minimum tuning step;
f
cco1
: QCCO frequency, output frequency of loop #1;
N1: main divider ratio in loop #1;
f
cp1
: comparison frequency in phase detector #1;
f
vco2
: VCOVHF frequency, output frequency of loop #2;
N2: main divider ratio in loop #2;
R2: reference divider ratio in loop #2;
f
cp2
: comparison frequency in phase detector #2;
f
Xosc
: Xosc frequency.
RF
input
I
Q
RF
AGCLoop
BB output  I
QCCO  LO
Ph. Det. + Ch.P.
#1
V/I
converter
/ N1
Ph.Det.+Ch.P.
#2
Z
filter
#2
VCO2
VHF band
/N2
/N1 /R2
Xosc
(4 MHz)
doubleloop MOPLL circuit
Loop #1
Loop #2
BB output  Q
Z
filter
#1
Chapter 8 / Testchips Realized 175
It is important to notice that the
comparison frequency of loop #2
becomes:
1
2
N
f
f
step
cp
∆
·
Table 82 Double Loop: minimum step and comparison frequencies.
The main divider of loop#1 is composed of two swallow counters and N1 belongs to the set: [4, 5, 6, 7]. The
frequency range of VCO2 is then determined with respect to the limits of the QCCO band. It follows that:
{ ¦ MHZ
M
f
vco
5 . 237
4
950
max
2
· ·
{ ¦ MHz
M
f
vco
1 . 307
7
2150
min
2
· ·
Actually the range of VCO2 should also include some margin at the extremities. If we consider a
margin of 20MHz and a tuning range of 4 V, the average K
vco
of VCO2 equals 27.4MHz/V.
Thus VCO2 works in the range of a VHFIII oscillator, with a frequency sensitivity that is close
to the K
vco
of UHF oscillators. These parameters serve as references for the design and the
application of loop #2.
The comparison frequency of loop #1 equals the VCO2 frequency, which means a maximum f
cp1
to the order of 330MHz. The design of the charge pump and the phase detector are mostly
determined by this constraint, since the transfer characteristics I
average
/ ∆ϕ
in
should cover a
minimum input range of t180° . This condition assures that the comparator can retrieve
frequency and phase differences (see chapter 5).
8.2.2 TC2 structure
The blocks that are colored in grey in figure 8.2 were implemented in the testchip TC2. A more
detailed schematic diagram is included in figure 8.3.
The testchip is basically divided into two parts, analog and digital, that interact through interface
blocks. The analog part has symmetrical inputs for the RF signal and asymmetrical outputs for
the BB signals: I and Q. There are external control inputs for the amplitude and frequency of the
QCCO. The frequency input is bound to the charge pump output and to an external LPF
impedance. The LO signal can be monitored through a test output. The ensemble of blocks is
programmed by a 3wire bus. The bus has an additional acknowledge block that indicates the
oscillators
frequency
f
vco2
= f
cp1
f
cco1
wrt f
cp f
cp2
*N2 f
cp1
*N1
wrt N and R
1 * 2
2 *
N R
N f
Xosc
2
2 *
R
N f
Xosc
wrt ∆f
step
with:
∆f
step
=
2 R
f
Xosc
1
2 *
N
N f
step
∆
2 * N f
step
∆
176 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
reception of a full programming word. The output of the acknowledge block is equivalent to an
I
2
C bus output. In reality this block is included to test the sensibility to bus crosstalk.
iii
The charge pump has 2 programmable values of I
cp
( 20µA and 190µA) and it can also be set to
test modes with sinking, sourcing and highimpedance outputs.
Figure 8.3 Block diagram of TC2
There are 4 supply pins, a pair for the analog part and another for the digital one. The total
consumption is 60mA under 5V, and the active layout area equals 1.2mm
2
. The total layout area
is 2.1mm
2
, which includes the 20 input/output pins.
The symmetry of the layout of the analog part is stressed to guarantee the quadrature
characteristics of the I and Q branches. Figure 8.4 shows a photo of a testchip TC2. On the left
side there are the digital blocks (bus, main divider and phasedetector /charge pump, from the
higher to the lower corner); and on the right side, the analog part (QCCO, mixer, regulator, input
and output buffers).
iii
Bus crosstalk denotes the interference of the bus activity in the others blocks of the synthesizer. It is measured as
perturbations in the output spectrum when the synthesizer is continuously receiving a repetitive programming word.
Vreg
2
2 2
2
2
4
44
2
Dual Mixer
Phase Det.
+
Ch. Pump #1
V/I
Div.1
(4.5.6.7)
Sym> Assym Output stage
BBQ
BBI
4
Q
I
QCCO
Vamp Rf
in
Bus data load
synchronization
Plus block
combine I &Q
CCOout
output for
Z=50Ω
Test
Bus
SDA
SCL
ENB
ACK
3
QCCO
2
DIV456
4
PhDetChP
Biasref
VCCO
GNDO
ANALOG
PART
BNISOLATION
Pin for external
Loop Filter
Ref
VCC
GND DIGITAL
PART
INTERFACE LAYER
Bandgap
regulator
V/I
Chapter 8 / Testchips Realized 177
Figure 8.4 Photo of a testchip TC2
TC2 was measured in a separate board using a signal generator as input and also in combination
with a terrestrial synthesizer whose application was adapted to cover the frequency range of loop
#2. The results are discussed in the following section.
8.2.3 TC2: results
The blocks are all functional and the loop locks correctly. Some particular points of the
measurements of the different blocks are summarized below:
• 3W + acknowledge bus:
there is no visible interference in the LO spectrum for a continuous programming
sequence.
• Phase detector and Charge Pump:
The comparator is able to retrieve frequency differences for a maximum f
cp
equal
to 450MHz, with no loss in its sensibility K
ϕ
(no dead zone).
The SNF for a f
cp
of 300MHz is measured as –124dBc/Hz. This result is very
close to the estimation of the charge pump noise presented in section 7.3.2. Thus
the SNF of this wide band loop is set by the charge pump noise performance.
178 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
• Mixer and BB buffers:
The conversion gain of the mixer plus BB stages equals 5dB.
iv
The IP3 referenced
to the input is measured as 17dBm. These two values agree with the simulation
results.
The leakage of the LO signal at the RF inputs is measured as –64dBm, which
indicates that there is no major pollution of LO signals in the supplies that are
shared with the mixer. The noise performance of the mixer is good enough to keep
the same L(f) of the LO in the BB outputs.
• QCCO:
The frequency coverage is the same presented in section 8.1.2. The quadrature of
the I and Q outputs is measured in the 4 bands. The measurement was made
comparing I and Q single tones around 10MHz in the base band outputs. The
phase deviations are kept under 2° as long as the amplitude control assures a
minimum level around 200mVpeak
for the oscillator signal. In the worst case for
low v
agc
input and in the highest band the maximum deviation is 3.5° .
The spurious rays at tf
cp1
are lower than –62 dBc , for a loop filter with a closed
bandwidth around 2MHz.
• Pulling:
The interference of the RF input on the LO signal was evaluated by a method
which is used in the characterization of terrestrial MOPLL circuits. A strong RF
carrier, 100% AM modulated by a signal at 100kHz, is injected into the mixer.
The sidebands that appear around the LO carrier at the same 100kHz frequency
offset are measured.
RF input power Interference at t100 kHz
offset from LO
0 dBm 45 dBc
5 dBm 55 dBc
10 dBm 64 dBc
These levels are roughly 10dB better than the requirements for terrestrial MOPLL.
In ZIF satellite receivers the pulling is also evaluated as the deviation of the LO
frequency for a given RF power. However this method is mostly adapted to the
LC oscillator where the radiation of the RF input disturbs the resonator. In the
QCCO, as expected, there is no frequency deviation of the carrier for RF input
powers exceeding 10dBm.
Two plots of the LO spectrum are shown in figures 8.5 and 8.6. The first is measured with a
small span of 250kHz, for an f
cco1
of 2.1GHz. It shows the inloop zone of loop #1, when the
reference input is a signal generator. The L(f) is indicated in the plot.
( ) ( ) ( )
Hz
dBc
N
loop Hz
dBc
MHz f
N MHz SNF kHz L
cp
9 . 123 1 log 20 107 300 107 25
7 1
1 #
300
1
− · − − · ⇒ − ·
· ·
iv
We should remember that the current testchip does not contain the preamplifier block that should significantly
increase the range of dynamic gain.
Chapter 8 / Testchips Realized 179
Figure 8.5 TC2 _ inloop spectrum for N1=7 and f
cp1
=300Mhz
Figure 8.6 TC2 _outofloop spectrum for N1=6 and f
cp1
=300MHz
180 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
The second plot shows a larger span where the outofloop zone can be observed. The charge
pump current was set to 20µA to decrease the closed loop bandwidth. There is a supply
interference at 2.3MHz that causes visible sidebands. It is an external disturbance from the
laboratory environment that unfortunately could not be suppressed.
( ) ( )
Hz
dBc
GHz f
Hz
dBc
GHz f
cco cco
kHz L MHz L 24 . 76 100 28 . 108 4
8 . 1 8 . 1
− · ⇒ − ·
· ·
The noise measurements with great dBc dynamics are very sensitive to the surrounding
environment. For the plots presented above the output spectra were averaged over several sweeps
in order to keep the static signals and filter the sporadic interference. In figure 8.6 this average is
particularly difficult, because of the large span combined with a narrow resolution bandwidth.
The consequence is that the central carrier frequency changes slightly during the averages (due to
the finite precision of the spectrum analyzer) and the marker indicating this reference is no
longer fixed at the reference value. This problem is already previewed by the measurement tool
that provides a steady reference for the noise measurement, which is fixed in the first sweep.
An application board of a terrestrial mixeroscillator, the TDA5732, was adapted to use its UHF
oscillator as the reference VCO2 oscillator. The phase noise performance of this reference
oscillator was measured as –114 dBc/Hz at a 100kHz offset.
The ensemble of the two boards (loop#2 plus loop#1) was evaluated in a biterrorrate (BER)
measurement.
v
This measurement is used to quantify the implementation loss that is due to the
frequency synthesizer.
Different QPSK channels with symbol rates from 3Msps up to 30Msps were tested. The
performance of the double loop synthesizer was compared to a single loop synthesizer with a LC
oscillator that has an L(100kHz)=98dBc/Hz. The implementation losses of both systems are
practically identical. The influence of the L(f) of VCO2 appears mainly when we are decoding
narrow channels, for instance with the symbol rate of 3Msps. In this case the phase noise of
VCO2 has to be kept better than L(100kHz)=112dBc/Hz. Otherwise the implementation loss of
the double loop is worse than the LC oscillator plus a single loop.
8.3 TC3 : single PLL plus QCCO circuit
The testchip TC3 contains a low noise satellite PLL plus a QCCO. The low noise PLL was
designed by the PLLtuner development group at Philips Semiconductors in Caen. The objective
of this testchip is to verify the maximum closed loop bandwidth that can be achieved in a single
loop configuration.
Figure 8.7 shows a plot of the output spectrum of this single loop. The comparison frequency
equals 1MHz and the loop filter is calculated for an open loop bandwidth around 165kHz. The
closed loop bandwidth or the 3dB bandwidth for the PLL is: f
3dB
= 279kHz.
If we refer to the results of chapter 5 we see that this closed loop bandwidth comes close to the
maximum stable value. Indeed a 50% increase of the open loop bandwidth would already cause
the instability of the system.
v
The BER is a common unit used in the context of digital decoders. It measures the amount of errors encountered in
the reception of a test sequence.
Chapter 8 / Testchips Realized 181
Figure 8.7 TC3 _ single low noise PLL plus QCCO
Figure 8.8.a Linear scale
1
182 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Figure 8.8.b Logarithmic scale
Figure 8.8 Simulation result for the SSB phase noise _ linear scale
The measurement may be compared with the simulation results presented in figures 8.8.a and
8.8.b. They show the result of a noise simulation with the AC behavioural model of the PLL (see
section 7.4.1). Figure a uses a linear scale for the abscissa so that it can be better compared with
the spectrum output. Figure b uses a logarithmic scale to emphasize the LPF transfer of N
pll
and
the BPF transfer of v
nvco
.
The noise simulations used the parameters L
vco
and N
pll
that were found in the measurements,
and the results agree very closely with the output of the spectrum analyzer.
The comparison between the plots 8.8.a and 8.8.b evidences the influence of the peaking in
masking the noise performance of the PLL in the inloop zone. Actually in order to measure N
pll
it is necessary to use a very small span around the carrier.
We measured L
pll
and calculated N
pll
, measuring the spectrum in a span of 10kHz. They were
found to be:
L
pll
(2kHz) = 86.7 dBc/Hz ;
with: N = 900 ; f
cp
= 1MHz ⇒ SNF(1MHz) = 145.7 dBc/Hz
The noise performance of the VCO is the same encountered in TC2, which is:
L
vco
(100kHz) = 76 dBc/Hz .
Chapter 8 / Testchips Realized 183
The intersection frequency for the two noise asymptotes equals: 343kHz ; which indicates that
the open loop frequency of the filter should be increased to have a smaller peaking in the
spectrum. However, we know that we already reached the maximum values of f
ol
with respect to
the stability constraints.
The phase jitter of the present output spectrum exceeds the limit value of 4.84° that would be
necessary to keep the implementation loss below 0.2 dB (see section 7.5.1.3). Therefore this
single loop plus QCCO configuration would need to incorporate a fractional divider, in order to
have two different values for the minimum frequency step and the comparison frequency.
8.4 Comparative analysis: phase jitter and implementation loss
In this section we compare the spectra of two synthesizer configurations for a zeroIF satellite
receiver: the double loop plus QCCO and the single loop plus LC oscillator.
Currently the satellite tuner has separated ICs for the MO and PLL functions. This analysis
intends to orient the next steps of the IC development of a single chip MOPLL for satellite
reception.
8.4.1 Configurations compared
The configuration, double loop plus QCCO (DL+QCCO), corresponds to the architecture of
TC2, and its present status of development was discussed in section 8.2.
The configuration, single loop plus LC oscillator (SL+LCosc), is based on the Philips IC: the
TDA8060, a mixeroscillator for zeroIF satellite reception.
The values used in the simulations, for the noise performance of the PLL and the VCO,
correspond to the measurements of the parameters L
vco
and SNF in TC2 , TC3 and in the
TDA8060. The table below summarizes these parameters:
Double Loop + QCCO Single Loop + LC oscillator
Loop #1:
SNF
loop#1
(f
cp
= 300MHz) = 124 dBc/Hz
L
QCCO
(f
offset
= 100kHz) = 76 dBc/Hz
K
vcco
= 125 MHz/V ; I
cp1
= 190 µA
Loop #2:
SNF
loop#2
(f
cp
= 125kHz) = 154.7 dBc/Hz
L
VCO2
(f
offset
= 100kHz) = 114 dBc/Hz
K
vco2
= 27.4 MHz/V ; I
cp2
= 1.2 mA
Single loop parameters:
SNF(f
cp
= 125kHz) = 154.7 dBc/Hz
L
VCO
(f
offset
= 100kHz) = 100 dBc/Hz
K
vco
= 100 MHz/V ; I
cp
= 550 µA
Table 83 Parameters of the two zeroIF configurations being compared
184 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
The current of loop #2 in the DL+QCCO is chosen as the largest value for which we have
already tested low noise charge pump designs. The need for this high I
cp2
value appears when we
are minimizing the phase jitter in loop#2. In fact, VCO2 has a very tight phase noise
performance and the noise from the resistors of the loop filter becomes significant for values
above 2kΩ. High I
cp2
values enable us to decrease the loop filter impedance.
The synthesizer noise floor of loop #2 in the DL+QCCO, and in the SL+LCosc are derived from
the measurements of TC3.
There are already some standalone PLL ICs that present a better SNF (see data about the
TSA5059 in section 7.1). However when combining the PLL and the MO in the same IC, it is
probable that the crystaloscillator design should work with smaller amplitudes and currents, and
closer to a linear mode; in order to avoid excessive interference in the common substrate, and
undersampling phenomena with respect to strong RF and BB signals.
The calculations use the SNF of TC3 that contains a more linear design for the crystal oscillator.
When the simulations are made with comparison frequencies that are different from the value
indicated in table 83 (125kHz); the changes in SNF are assumed to respect the variation rate of
3dB/octaveoff
cp
. This variation rate is discussed in chapter 7, and it is confirmed by
measurement results.
8.4.2 Conditions for the simulations
The comparative analysis is based on simulation results for the phase jitter in the LO signal. The
settings of the simulations are the same used during the BER measurements of TC2. So that we
can evaluate the accuracy of the behavioural model used in the simulations.
Table 84 lists the variable parameters and the outputs that were calculated:
Variable Parameters: Simulated Outputs:
• LO frequency [Hz]:
f
lo
= 900M ; 2.2G ;
changes the dividing ratios (N1, N2);
• Tuning step [Hz]:
∆f
step
= 125k ; 1M ;
changes the comparison frequencies and the
loop filters;
• Symbol rate for QPSK modulation [sps]:
r
s
= 3M ; 30M ;
changes the settings of the demodulator and
the integration boundaries for the phase jitter;
• Phase Jitter at the PLL output:
σ
ϕpll
(f
min
, f
max
) [°] ;
where f
min
and f
max
are the integration
boundaries.
• Phase Jitter at the demodulator output:
σ
ϕdem
(f
min
, f
max
) [°] ;
σ
ϕdBdem
(f
min
, f
max
) [dΒ] ;
• Implementation loss due to the phase jitter at the
demodulator output:
IL
dB
[dB]
Table 84 Parameters and outputs for comparative analysis
Let us examine these outputs and parameters.
The phase jitter is evaluated at two points of the reception chain, at the PLL output, and at the
demodulator output. The second one is also expressed in dB and translated in an implementation
loss. The implementation loss is calculated for a SNR
min
of 8dB, which corresponds to the raw
BER of 6.10
3
.
Chapter 8 / Testchips Realized 185
The value of IL
dB
accounts for the losses due to the phase jitter, and it can be compared to the
0.2dB threshold discussed in section 7.5.
The power of the spurious rays is not included in this IL
dB
. However we can easily derive a
specification for the acceptable spurious level looking at the value of σ
ϕdBdem
, and
remembering expressions (7.13) and (7.14). In general a pair of spurious rays with a SSB level of
(σ
ϕdBdem
– 6dB) in dBc, should be the maximum discrete disturbance allowed. If there are more
pairs of spurious rays, the maximum power level should be divided by the number of rays that
are found within the range of phase jitter integration.
The phase jitters are integrated in the bandwidth: [f
min
; f
max
] = [0 ; bw
ch
]. The higher boundary
is chosen as bw
ch
instead of bw
ch
/2, as indicated in expression (7.15). In fact the earlier
expression takes into account a single channel, with no disturbance from adjacent channels.
When we enlarge the integration boundary to bw
ch
we are also taking into account the effect of
the two closest adjacent channels, considering that they have the same power density as the
selected channel.
The LO frequency range covers the bandL with a small margin. We simulate the two extremities
to test the cases of the largest and the narrowest loop bandwidths, with the lowest and the highest
inloop noise contribution from the PLL.
The settings of the demodulator block are derived from the satellite demodulator and decoder
TDA8043. The phase model of the demodulator part was discussed in section 7.5.2.
The frequency and phase detection range of the carrier recovery loop equals r
s
/8 , where r
s
is the
input symbol rate. Therefore, with respect to the demodulator, the maximum tuning step for a
given symbol rate would be r
s
/4. Nevertheless the circuit specifications often demand much
lower tuning steps. For satellite applications the typical value is 125kHz, and more recently
higher steps like 1MHz are discussed to tune high symbol rate channels.
In a QPSK modulated channel the symbol rate is equal to the channel bandwidth in Hz. The
simulations test two symbol rates or channel bandwidths: 3Msps (bw
ch
=3MHz) and 30Msps
(bw
ch
=30MHz).
The bandwidth and damping parameters for both clock and carrier recovery loops are derived
from the application note of the demodulator, and they are the same as those used in the
measurements of TC2. Table 85 lists the inputs of the behavioural model of the demodulator for
the two symbol rates:
r
s
[sps] Nd1 WNslow/2π [Hz] ξslow WNfast/2π [Hz] ξfast
1.56k 0.68
3M
74
722 1.16
4.95k 0.83
30M 20 7.91k 1.13 15.2k 0.81
Table 85 Settings of the demodulator block
Nd1 is the number of delays within the clock recovery loop, WN and ξ determine the loop filter
parameters, and the subscript fast and slow refer to the carrier and clock recovery loops
respectively.
The tightest situation for the LO requirement appears for the narrowest channels, where the
demodulator loops are narrower, and they filter less of the LO phase jitter. We test two values for
the bandwidth of the fast loop to verify the influence of this parameter.
186 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Figure 8.9 Spectra for ∆f
step
=125kHz and f
lo
=900MHz
Figure 8.10 Phase noise simulation for DL+QCCO with and without demodulator
f
cp2
= 31,25k
3k 5k 320k 5M
71,6
77,6
112
L(f)
(dBc/Hz)
log (f
offset
)
[Hz]
L(f
offset
=10kHz) ~ 80 dBc/Hz
f
cp
= 125k
SL+LCosc
DL+QCCO
Chapter 8 / Testchips Realized 187
Figure 8.9 is a sketch of the spectra found at the output of the two configurations for a tuning
step of 125kHz, and an LO frequency of 900MHz. The levels indicated correspond to the SSB
phase noise at the output of the PLL. The spurious rays due to the reference breakthrough are
also indicated.
The level of the L(f) for the inner part of the double loop configuration (determined by loop #2)
is generally higher than the L(f) of the single loop configuration. In the outer part, for f
offset
above
320kHz), the double loop is also worse because it adds some noise with respect to the single
loop.
Nevertheless we know that the double loop, with an integrated oscillator, presents advantages of
compactness and robustness with respect to strong RF inputs. Therefore, our analysis evaluates if
the losses of the double loop, when compared to a single loop, are really influencing the IL
dB
that is measured at the input of the decoder.
Figure 8.10 shows the output of a noise simulation for the DL+QCCO configuration. The noise
density is plotted for the phase at the output of the PLL, and also at the output of the
demodulator.
The curves of figure 8.10 are also calculated for f
LO
=900MHz and ∆f
step
=125kHz. The
parameters of the demodulator are the ones listed in table 85 for a r
s
= 3Msps and a
WNfast=4.95kHz. We observe that most of the phase jitter below WNfast is filtered by the
carrier recovery loop, which may significantly change the value of the total phase jitter before
and after the demodulator.
The loop filters of the two configurations were set to minimize the phase jitter at the output of
the PLL ( σ
ϕpll
(0, bw
ch
) ). The values used in the simulations were:
• filters for DL+QCCO (foln: C1/C2/R1/C3/R3):
loop#1: 8MHz: 10pF/0.39pF/10kohms ;
(no postfilter, and equal values for the 2 cases of ∆f
step
)
loop#2:
for ∆f
step
1MHz: 5.5kHz: 100nF/3.9nF/1.2kohms/3.9nF/1kohms;
for ∆f
step
125kHz: 2.5kHz: 68nF/2.7nF/4.7kohms/2.2nF/3.9kohms;
• filters for SL+LCosc (foln: C1/C2/R1/C3/R3):
for ∆f
step
1MHz: 46kHz: 2.2nF/82pF/8.2kohms/27pF/15kohms
for ∆f
step
125kHz: 3kHz: 68nF/2.7nF/3.9kohms/820pF/8.2kohms
8.4.3 Results and conclusions
The largest differences in σ
ϕpll
(0, bw
ch
) appear for f
LO
= 2.2GHz, and N1=7. Therefore we start
comparing these situations for a high symbol rate channel with r
s
=30Msps. The simulation
outputs are shown in table 86.
188 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
∆f
step
= 1MHz ∆f
step
= 125kHz
Configuration
σ
ϕpll
[°]
σ
ϕdem
[°]
σ
ϕdBdem
[dΒ]
IL
dB
[dB]
σ
ϕpll
[°]
σ
ϕdem
[°]
σ
ϕdBdem
[dΒ]
IL
dB
[dB]
DL+QCCO 4.38 1.65 30.8 0.023 7.76 1.63 30.9 0.022
SL+LCosc 2.72 2.19 28.4 0.040 4.02 0.67 38.7 0.004
Table 86 Phase Jitter and implementation loss for r
s
=30Msps and f
LO
= 2,2GHz
The results above verify that both configurations have quite some margin with respect to the 0.2
dB threshold for the IL
dB
due to phase deviations. The phase jitter of the DL+QCCO after the
demodulator, for a large carrier recovery loop is very close to the SL+LCosc.
The filter of the SL+LCosc for ∆f
step
of 1MHz could probably be made narrower to improve the
σ
ϕdem
with some loss in σ
ϕpll
.
The next table shows the outputs for a low symbol rate channel of 3Msps. In this case only the
smaller frequency step of 125kHz is presented. The phase jitter at the output of the demodulator
is calculated for two values of carrier recovery loop bandwidth.
WNfast=1,56kHz WNfast=4,95kHz
Config.
f
LO
[Hz]
σ
ϕpll
[°]
σ
ϕdem
[°]
σ
ϕdBdem
[dΒ]
IL
dB
[dB]
σ
ϕdem
[°]
σ
ϕdBdem
[dΒ]
IL
dB
[dB]
900M 3.19 2.24 28.1 0.042 1.38 32.4 0.016 DL
+
QCCO
2.2G 7.68 3.88 23.4 0.127 2.16 28.5 0.039
900M 2.81 2.29 28.0 0.044 1.61 31.0 0.022 SL
+
LCosc
2.2G 4.01 2.52 27.1 0.053 1.50 31.6 0.019
Table 87 Phase Jitter and implementation loss for r
s
=3Msps and ∆f
step
= 125kHz
In the reception of low symbol rate channels, and in particular with small carrier recovery loops,
we start to notice the influence of the LO phase jitter.
The results for low and high symbol rates are coherent with the comparative measurements of
TC2 and the zeroIF mixeroscillator TDA8060.
The measurement set that was used enables a precision of 0.05dB in the readings of
implementation loss. Therefore a quantitative analysis needs to identify the most significant
parameters for the performance of each configuration and vary them as much as to cause
differences in the IL
dB
above the measurable limit.
The most sensible parameters in the configuration DL+QCCO are L
vco2
and SNF
loop#1
. The
experience of the testchips implemented show that SNF
loop#1
is quite stable among different
samples and different diffusion lots. However the L
vco
of LC oscillators tends to vary within a 3
to 6 dB range amongst different samples and application layouts. Therefore this last parameter is
considered as the most critical.
Chapter 8 / Testchips Realized 189
In the SL+LCosc configuration, it is again the L
vco
that is the most influencing parameter. Table
88 shows the margin for degradations in the L
vco
of the two configurations for the low symbol
rate reception. The minimum values of L
vco
should be compared with the nominal values that
were presented in table 83 (DL+QCCO: L
VCO2
(f
offset
= 100kHz)=114 dBc/Hz; and SL+LC
osc: L
VCO
(f
offset
= 100kHz) = 100 dBc/Hz).
In particular for the double loop system we also test the margin of acceptable degradation of the
QCCO phase performance (nominal value: L
QCCO
(f
offset
=100kHz)=76 dBc/Hz). The margins are
measured as the maximum L
vco
value that would cause an IL
dB
of 0.2dB for the reception of a
3Msps channel.
Margin for L
vco
(100kHz) degradation to achieve IL
dB
= 0.2 dB
Config.
WNfast=1.56kHz WNfast=4.95kHz observations
max{L
vco2
}=110 dBc/Hz max {L
vco2
}=104.5 dBc/Hz only varying L
vco2
(f) DL
+
QCCO max {L
vco2
}=110 dBc/Hz
max {L
QCCO
}=65 dBc/Hz
max {L
vco2
}=105 dBc/Hz
max {L
QCCO
}=64 dBc/Hz
Varying both
L
vco2
(f) and L
QCCO
(f)
SL
+
LCosc
max {L
vco
}=92 dBc/Hz max {L
vco
}=88 dBc/Hz
Table 88 Margin for degradations in the oscillators phase noise performance
The margins of L
vco
degradation in both configurations show that these system specifications are
practicable for production on an industrial scale. We notice that the bandwidth of the carrier
recovery loop, when increased to 4.95kHz, can improve the margins of 4 to 5dB.
The margins of the L
vco
have to be respected within the entire frequency range, which means a
range of 1.3GHz for the SL+LCosc , and a range of 110MHz for the VHF oscillator of
DL+QCCO. Therefore the larger margin in the performance of the L
vco
for the SL+LCosc is not
necessarily easier to be held than the margin of the VHF oscillator.
Besides, for values of carrier recovery bandwidth that are close to or larger than the PLL
bandwidth, the SNF has no major influence. This effect can be verified for the SL+LCosc where
a variation of 10dB in the SNF is barely visible for a WNfast of 4.95kHz. In the double loop only
the SNF
loop#2
can be relaxed; in fact variations of 7dB can also be tolerated for the large carrier
recovery loop.
This analysis and the conclusions are valid for the context of a QPSK receiver where the
neighbouring channels have power density levels that are close to the level of the selected
channel. Other extended models can be derived to analyze the implementation losses for FM,
QAM and OFDM receivers. Furthermore the behaviour of the decoder, for the final output signal
quality should also be examined, in particular the sensitivity to the shape of the random phase
noise sidebands (white or 1/f
2
).
This chapter presented physical results from testchips and comparative measurements for a
double loop synthesizer with a completely integrated GmC oscillator, that covers the satellite
bandL.
190 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Chapter 9 / Conclusions 191
9 Conclusion
New communication standards are very demanding for tuner specifications. Therefore
behavioural system analysis becomes a more and more relevant step, in evaluating and
dimensioning circuit and block requirements.
In this work we analyzed the PLL frequency synthesizer for its stability and noise aspects. The
application context was the frontend of TV tuners, with special focus on satellite receivers.
The PLL was presented as a control system, in order to study the influence of different
parameters using a simple and flexible model. This representation was used to examine some
issues around the application and specification of the PLL: controlling the feedback bandwidth,
working with larger comparison frequencies, dealing with phase noise, stability and spurious
requirements, etc.
We continued pushing the noise issue farther away in the PLL system, and looked for a
theoretical basis that could be linked to the measurement and simulation contexts.
Next, we treated an example of a new frontend architecture: the nearzero IF receiver for a
satellite tuner, using an integrated oscillator. The concept and the implementation of two
testchips was discussed and the measurements were compared to calculations and simulations
results.
Finally, the loss of signal quality, which is due to the phase deviations of the LO, was studied
and a numerical example was calculated for the case of a QPSK receiver.
In summary, there were three basic parts in our study: control theory applied to PLL, treating
phase noise in the PLL system, examining new architectures and system specifications.
192 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Bibliography 193
Bibliography
[AN98049] Philips Semiconductors System Laboratory  Tuner and SDD applications
teams. OM5719A – Digital SatelliteTV Receiver ZeroIF Demo Board
with TDA8060 and TDA8044A. Eindhoven (NL): Philips Semiconductors,
1998. 78 p. Application Note n° AN98049.
[Asch96] Aschwanden, F. Direct Conversion – How to make it work in TV Tuners.
IEEE Transactions on Consumer Electronics, Aug. 1996, vol. 42, n° 3, p.
729738.
[Berg95] Bergmans, J.W.M. Effect of loop delay on stability of discretetime PLL.
IEEE Trans. Circuits Syst.I, Apr. 1995, vol. CAS42, n° 4, p. 229231.
[Berg96] Bergmans, J.W.M. Digital Baseband Transmission and Recording.
Boston: Kluwer Academic Publishers, 1996. XVI, 633 p.
[Blau97] Blaud, P., Fiebig, N. and Ipek, M. A Direct Conversion IC for Digital
Satellite TV. Proceedings of the 23
rd
European SolidStates Circuits
Conference. Southampton (GB): Sept. 1997, p. 124127.
[Boon89] Boon, C.A.M. Design of HighPerformance NegativeFeedback
Oscillators. PhD thesis: Delft, University of Technology, 1989. 150 p.
[Cran98] Craninckx, J.F. and Steyaert, M. Wireless CMOS Frequency Synthesizer
Design. Dordrecht (NL): Kluwer Academic Publishers, 1998. XXVI, 247 p.
ISBN 0792381386
[Craw94] Crawford, J.A. Frequency Synthesizer Design Handbook. Norwood (UK):
Artech House, 1994. XIII, 435 p. ISBN 0890064407
[DVB96] Brand, S.J., Dulk, R.C.D., Graaf, C.R., Kuijken, O.M. and With, P.N.H.
Digital Video Broadcast (DVB) – training course. Eindhoven (NL):
Philips Research Centre for Technical Training, Sept. 1996. 900 p.
[Frank91] Franklin, G.F., Powell, J.D. and EmamiNaeini, A. Feedback Control of
Dynamic Systems. 2
nd
edition. Massachusetts (USA): AddisonWesley,
1991. XVI, 672 p. ISBN 0201508621
[Gard80] Gardner, F.M. ChargePump PhaseLock Loops. IEEE Transactions on
Communications, Nov. 1980, vol. COM28, p. 18491858.
[Gray93] Gray, P.R. and Meyer, R.G. Analysis an Design of Analog Integrated
Circuits. 3
rd
edition. New York (USA): John Wiley & Sons, 1993. XIV,
792 p. ISBN 0471574953
194 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
[Gree95] Greer, N. Some PLL Noise Calculations. Caen (FR): Philips
Semiconductors, May 1995. 12 p. Internal study report nonnumbered.
[Haji98] Hajimiri, A. and Lee, T.H. A General Theory of Phase Noise in Electrical
Oscillators. IEEE Journal of SolidState Circuits, Feb. 1998, vol. 33, n° 2,
p. 179194.
[Hayk89] Haykin, S. An Introduction to Analog & Digital Communications. New
York (USA): John Wiley & Sons, 1989. XVI, 652p.
ISBN 0471617164
[Hell71] Heller, J.A. and Jacobs, I.M. Viterbi Decoding for Satellite and Space
Communication. IEEE Transactions on Communications Technology, Oct.
1971, vol. COM19, n° 5, p. 835848.
[Howa93] Howald, R.L. Phase Noise and BER, sequence of articles In Microwaves
& RF.
Understand the Mathematics of Phase Noise, Dec. 1993, Part 1, p. 97100.
Defining the Relationships for Random Phase Errors, Jan. 1994, Part 2,
p.95100.
Create Math Models for Phase Noise, Feb. 1994, Part 3, p. 7786.
Modeling the Dynamics of PLL Sources, Apr.1994, Part 5, p. 160166.
Isolating Sources of Phase Errors, May 1994, Part 6, p. 8588.
Analyzing Phase Power Spectral Density for Noise Power, June 1994, Part
7, p. 97105.
Modeling Phase Noise in Simple PLLs, July 1994, Part 8, p. 7984.
[HP3048] Hewlett Parket. Noise Concepts. In Training course for Dynamic Signal
Analyzers. Southampton (UK): Hewlett Parket edition, 1994. 60 p.
[Klaa96] Klaasen, M.G.J.J. and Rutten, P.J.H. Design document for carrier recovery
In Design document TDA8043 (SDD). Eindhoven (NL): Philips
Semiconductors System Laboratory, Jul. 1996. 26 p. Internal report for
Product Concept & Application n° ETV/IR96066.0.
[Kokk92] Kokke, R.F.E. and Ruijter, H.C. Integratable Linear SineCosine
Oscillator. Eindhoven (NL): Philips Research Laboratory Nat.Lab., 1992.
74 p. Technical Note n° 6600.
[Krou82] Kroupa, V.F. Noise Properties of PLL Systems. IEEE Transactions on
Communications, Oct. 1982, vol. COM30, n° 10, p. 22442252.
Bibliography 195
[Kuij95] Kuijken, O.M. Phase Disturbance and BER in a DVB Satellite Receiver.
Eindhoven (NL): Philips Semiconductors System Laboratory, Jun. 1995.
12 p. Internal report for Product Concept & Application n°
ETV/IN95038.0.
[Kuij96a] Kuijken, O.M. Synthesizer Comparison Frequency and LO Phase Noise
Spectra for Satellite Tuners. Eindhoven (NL): Philips Semiconductors
System Laboratory, Mar. 1996. 26 p. Internal report for Product Concept
& Application n° ETV/IR96024.0.
[Kuij96b] Kuijken, O.M. Jitter (integrated phase noise) in the LO + Synthesizer
Combinations for the 3CoRD Measurements. Eindhoven (NL): Philips
Semiconductors System Laboratory, Apr. 1996. 10 p. Internal report for
Product Concept & Application n° ETV/OK96002.0.
[Kuij96c] Kuijken, O.M. BitError Rate in an MPEG2 Decoder with Various Local
Oscillator Phase Noise Spectra. Eindhoven (NL): Philips Semiconductors
System Laboratory, Apr. 1996. 6 p. Internal report for Product Concept &
Application n° ETV/OK96001.0.
[Lind78] Lindsey, W.C. and Simon, M.K. PhaseLocked Loops & Their
Applications. New York (USA): IEEE Press, 1978. VII, 431 p.
ISBN 0879421010
[Mana87] Manassewitsch, V. Frequency Synthesizers Theory and Design. 3
rd
edition. New York (USA): John Wiley & Sons, 1987. XI, 608 p.
ISBN 0471011169
[McNe97] McNeill, J.A. Jitter in Ring Oscillators. IEEE Journal of SolidState
Circuits, Feb. 1997, vol.32, n°6, p. 870879.
[Mill87] Millman, J. and Grabel, A. Microelectronics. New York (USA): McGraw
Hill, 1987. XX, 1001 p. ISBN 007100596X.
[Nord97] Norden, M.J. and Sinderen, J.v. Theory and Measurement of Time Jitter.
Eindhoven (NL): Philips Research Laboratory Nat.Lab., 1997. 86p.
Technical Note n° 069/97.
[Raza96] Razavi, B. A Study of Phase Noise in CMOS Oscillators. IEEE Journal of
SolidState Circuits, Mar. 1996, vol.31, n°3, p. 331343.
[Raza97] Razavi, B. Design Considerations for DirectConversion Receivers. IEEE
Transactions on Circuits and SystemsII: Analog and Digital Signal
Processing, June 1997, vol.44, n°6, p. 428435.
196 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
[Robi91] Robins, W.P. Phase Noise in Signal Sources (Theory and Applications).
2
nd
edition reprinted. London (UK): Peter Peregrinus, 1991. X, 322 p.
ISBN 086341026X.
[Rohd83] Rohde, U.L. Digital PLL Frequency Synthesizers Theory and Design.
New Jersey (USA): Prentice Hall, 1983. XVI, 494 p.
ISBN 0132142392.
[Roma97] Romanowski, A., Klank, O. and Fazel, K. Concept of a Multistandard
Receiver for Digital Broadcast and Communication Services. IEEE
Transactions on Consumer Electronics, Aug. 1997, vol.43, n°3, p. 662
670.
[Sinde98a] Sinderen, J. v. Phase Noise Requirements of Some Digital Modulated
Systems. Eindhoven (NL): Philips Research Laboratory Nat.Lab., 1998. 6
p. Internal study report nonnumbered.
[Sinde98b] Sinderen, J. v. Implementation Loss. Eindhoven (NL): Philips Research
Laboratory Nat.Lab., 1998. 5 p. Internal study report nonnumbered.
[Soyu90] Soyuer, M. and Meyer, R.G. Frequency Limitations of a Conventional
PhaseFrequency Detector. IEEE Journal of SolidState Circuits, Aug.
1990, vol.25, n°4, p.10191022.
[Tang97] Tang, J.D.v.d. and Kasperkovitz, D. A 0.9 – 2.2GHz monolithic
quadrature mixer oscillator for directconversion satellite receivers. In
Digest of technical papers of the International SolidState Circuits
Conference (ISSCC). San Francisco (USA): Feb. 1997, vol. 40, p. 8889.
[TDA8043] Philips Semiconductors Data Sheet. TDA8043: Satellite Demodulator and
Decoder (SDD). Caen (FR): Philips Semiconductors, Feb. 98. 56 p.
[TDA8060] Philips Semiconductors Data Sheet. TDA8060TS: Satellite ZeroIF QPSK
downconverter. Caen (FR): Philips Semiconductors, May 1998. 18 p.
[TSA5059] Philips Semiconductors Data Sheet. TSA5059: 2.7GHz I
2
C bus controlled
Low Phase Noise Frequency Synthesizer. Caen (FR): Philips
Semiconductors, May 1999. 22 p.
[Thai95] Thain, W.E. and Connelly, J.A. Simulating Phase Noise in PhaseLocked
Loops with a Circuit Simulator, IEEE Symposium on Circuits and Systems,
1995, vol. 3, p. 17601763.
Bibliography 197
[Vauc98] Vaucher, C. and Kasperkovitz, D. A WideBand Tuning System for Fully
Integrated Satellite Receivers. IEEE Journal of Solid States, July 1998,
vol.33, n°7, p. 987997.
[Wiel97] Wiel, M.C.J. Simulation techniques for the analysis of noise in dynamic
nonlinear circuits. Eindhoven (NL): Philips Research Laboratory
Nat.Lab., 1997. 108 p. Technical report n° 6971/97.
[Wola91] Wolaver, D.H. PhaseLocked Loop Circuit Design. New Jersey (USA):
Prentice Hall, 1991. X, 262p. ISBN 0136627439
[Wong96] Wong, W.K. Optimization Techniques for HighOrder PhaseLocked
Loop Type Jitter Reduction Circuit for Digital Audio. IEEE Transactions
on Consumer Electronics, Feb. 1996, vol. 42, n°1, p. 156163.
198 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
FOLIO ADMINISTRATIF
THESE SOUTENUE DEVANT L’INSTITUT NATIONAL DES SCIENCES APPLIQUEES DE LYON
NOM: de Queiroz Tavares DATE DE SOUTENANCE: 09 /12 / 1999
PRÉNOMS: Marina
TITRE:
SYNTHETISEUR DE FREQUENCE A BOUCLE DE VERROUILLAGE DE PHASE:
ETUDE DU BRUIT DE PHASE ET DE BOUCLES A LARGE BANDE
NATURE: Doctorat Numéro d’ordre: 99 ISAL 0086
FORMATION DOCTORALE: Dispositifs de l’électronique intégrée
ECOLE DOCTORALE: Electronique, Electrotechnique, Automatique (EEA)
Cote B.I.U. – Lyon : T 50 / 210 / 19 / et bis CLASSE:
RESUME:
Les synthétiseurs de fréquences à boucle de verrouillage de phase sont largement utilisés dans les récepteurs et les transmetteurs
pour les télécommunications, comme partie du bloc de conversion de fréquence. Ils sont constitués d’un oscillateur accordable et
d’une boucle à contrôle de phase programmable. Les tendances actuelles dans le développement des PLL concernent les
performances en bruit et un plus haut degré d’intégration. Le premier est en relation direct avec les nouvelles techniques de
modulation numériques, nécessitant souvent un plus fort rapport porteuse/bruit dans la chaîne de traitement du signal. Les secondes
répondent à l’orientation générale vers des systèmes plus petits et plus compacts.
La thèse développe et discute les modèles d’un système PLL pour étudier les aspects stabilité et bruit. Les résultats du modèle sont
utilisés pour la conception des circuits intégrés et de leur applications. Ces résultats sont confirmés par les mesures.
L’approche «stabilité» étudie la robustesse du système PLL, travaillant typiquement avec des très grandes variations de gain. Une
approche du système au circuit (topdown), étudie la génération et la transmission du bruit. Finalement, des réalisations de circuits
tests du PLL avec des oscillateurs intégrés sont présentés.
La thèse s’est déroulée dans le cadre d’une collaboration entre le CEGELY  INSA de Lyon et Philips Semiconductors et plus
particulièrement au sein du centre de production et développement de Caen.
MOTSCLES:
‘‘Tuner’’, Partie Entrée Récepteur RF, Boucle Phase Asservie, Bruit de Phase, Stabilité, Oscillateurs OTAC
Laboratoire de recherche: CEGELY – INSA de Lyon
Directeur de thèse: Jean Pierre Chante
Président de jury: ……..
Composition du jury:
RichardGRISEL Professeur  Université Picardie rapporteur
MichielSTEYAERT Professeur  K.U. Leuven rapporteur
JeanPierreCHANTE Professeur  INSA de Lyon directeur
BrunoALLARD Maître de Conférences  INSA de Lyon examinateur
PhilippeKLAEYLE Ingénieur  Philips Semiconductors  Caen examinateur
EduardStikvoort Chercheur  ingénieur – Philips Nat.Lab. – Eindhoven examinateur
200 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
No d’ordre: 99 ISAL 086
Année 1999
THESE présentée
DEVANT L’INSTITUT NATIONAL DES SCIENCES APPLIQUEES DE LYON
pour obtenir
LE GRADE DE DOCTEUR
FORMATION DOCTORALE: ECOLE DOCTORALE:
Dispositifs de l’électronique intégrée Electronique, Electrotechnique, Automatique (EEA)
par Marina, de Queiroz Tavares
SYNTHETISEUR DE FREQUENCE A BOUCLE DE VERROUILLAGE DE PHASE: ETUDE DU BRUIT DE PHASE ET DE BOUCLES A LARGE BANDE
Soutenue le 09/Décembre/1999 devant la Commission d’Examen Jury
RichardGRISEL MichielSTEYAERT JeanPierreCHANTE BrunoALLARD PhilippeKLAEYLE EduardStikvoort
Professeur  Université Picardie Professeur  K.U. Leuven Professeur  INSA de Lyon Maître de Conférences  INSA de Lyon Ingénieur  Philips Semiconductors  Caen Chercheur  ingénieur – Philips Nat.Lab. – Eindhoven
rapporteur rapporteur directeur examinateur examinateur examinateur
Cette thèse a été préparée chez Philips Semiconductors – Caen, en collaboration avec le Laboratoire CEGELY de l’INSA de Lyon
PhD student: Marina de Queiroz Tavares Advisor: Prof. as part of the frequency conversion block. more specifically in the production and development centre of Caen.Title: PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops frontend/ tuners / PLL / phase noise / stability / gmC oscillators Keywords: Abstract: PLL frequency synthesizers are widely used in telecommunication receivers and transmitters. A topdown system to circuit approach. The stability approach investigates the robustness of the PLL system. They consist of a tunable oscillator and a programmable phase controlling loop. The thesis was conducted within the context of a collaboration between the CEGELYINSA de Lyon and Philips Semiconductors. And the second concerns a global trend towards smaller and more compact systems. JeanPierre Chante Director of the CEGELY laboratory . typically working with very large gain variations. being confirmed via measurements. The model results are employed in IC and application design. This thesis discusses and develops PLL system models to study stability and noise aspects. Finally testchip realizations of PLLs with fully gmC integrated oscillators are presented. The first is connected to the new digital modulation techniques. Current tendencies in PLL development focus noise performance and a higher integration level. studies noise generation and transmission. often demanding a higher CNR in the signal chain.
4. Maximum Phase Jitter 3.2. w3dB derivation from BRL(s) 3.5. Nominal Design 34 2. VCO 1. VCO Noise Representation and Phase Noise Units 3. w3dB derivation from was 3. 1.1.1.4.2. Introduction 1.2.2. 21 2.3.4. Dividers 1.3.3. 1.5.5.1.1.1. 1.5. Requirements in the Time and Frequency Domain 24 2.5.3.1.ii PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops Contents: Index List of figures List of Tables List of symbols and abbreviations Preface ii v viii ix xiv 1.1. SecondOrder Loop 26 2. Application Related Constraints 3.6.2.4.2.3.4. Optimum Closed Loop Bandwidth 3. Third and Fourth Order Loop 28 Algorithm for Loop Filter Calculation 34 2. The frontend in a telecommunication receiver The frontend in TV broadcasting Current tendencies: low noise and higher integration PLL systems : different application contexts PLL frequency synthesizers constituting blocks and nomenclature 1. Reference Breakthrough 3. Gain Stability Boundary 43 44 46 50 52 53 59 61 65 . Summary steps and numerical example 40 3. 1. Loop Filter 1 2 3 9 14 15 16 17 17 19 2.1. Robust design including Gain Variation and 3rd Pole compensation 36 2. PLL Phase Model and Loop Filter calculation 2.5.1.2. Phase Model for PLL synthesizers 22 2.1.2.2. PLL Closed Loop Bandwidth 3. Phase Detector – Charge Pump 1.2.
1.2. Supply Disturbances 4.3. Threestate comparator: frequency and phase detector 5.2.1. Slope approach 6. Interchanging Modulation Types 6. Loop filter time domain response 5. Summary of AC boundaries for filter design 4.3.2.1.2.1.2.4. Transfer functions table 4.2.3.2.1. Numerical examples and design considerations 5.1. Continuous equivalent with transmission delay 89 91 92 94 94 96 99 100 103 105 109 109 111 114 6. Phasors Notations 6. Discrete trasfers for the PLL Phase Model 5. Nonideal Filter Impedances 4. Simulation Example 69 70 71 72 74 76 79 80 80 81 82 82 83 84 85 5.2. Fully 3rd order passive filter 4.1.1.2.5. Electrical Noise: random sources representation & measurements 6.1.4. Comparing the frequency and phase approaches: 5.1.2.2.2.4.4.4.2. Limitations of the LTI Phase Model 5. Phase approach 5.3.3.2.2.2. Amplifier with single pole 4.4.2.3. Angular modulation 6. Electrical noise as a random process 6.2.2.6.1.1. The holder 5. Phase Noise: theoretical to practical approach 6.3. Frequency approach 5.5. Lock convergency approaches 5.3.1.3.1. Disturbances and Noise Propagation 4. Phase Noise Notations 6.2.2.2. Random Electrical Noise 4. Minimum phase deviation range 5. Input impedance: Zin 4.1. Large Signal Linearization 6. Numerical example 4.1. Amplifier AC characteristics 4.3.1. Active Loop Filters: AC & disturbances issues 4. Linear Time Variable transfer 119 120 121 123 125 125 127 128 133 135 135 136 .Contents iii 4. Amplifier Noise 4.1. The sampler 5.1.1. Time and Frequency representation 6.2. DC range limitations 5.1.3.1. Measuring Phase Noise 6.6.3. Filter Components Noise 4.1.
2. Comparative analysis: phase jitter and implementation loss 8.3. time.iv PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops 7.2.2.1.1. Time domain 7. Conditions for the simulations 8.4.2.2. TC3 : single PLL plus QCCO circuit 8.5.1. Results 8. Dflip flop 7. Translating the SNF into phase. Configurations compared 8.3.5. Conclusion 191 Bibliography 193 .4. Frequency domain 7. Large bandwidth noise sources 7.1.4.2. Detailing noise sources in different PLL blocks 7.1.1.1. Charge Pump 7.3. Digital Demodulator: clock and carrier recovery loops 141 143 147 149 151 154 154 158 159 159 160 162 163 167 8.1. Structure 8. Behavioural Models 7. Signal to noise ratio and implementation loss 7. Results and conclusions 169 170 171 172 173 173 175 177 180 183 183 184 187 9.3. TC2 structure 8.2.2.2. Sampling effects: SNF x fcp 7. GmC oscillator 8.1.2.3.4.1.3.4. Phase Noise in the PLL context 7. Narrow bandwidth noise sources 7. TC2 : MixerOscillatorPLL circuit for satellite direct conversion 8.2. Implementation Loss due to Phase Deviations 7.5. Testchips Realized 8.2.2.4. TC2: results 8. voltage and current noise 7.1. Double Loop Synthesizer 8.4.2.
List of Figures v List of figures Chapter 1 Figure 1.3 Figure 1.1 Figure 3.8 Figure 1.6 Figure 3.3 Figure 3.1 Figure 4.3 Figure 4.9 Chapter 4 Figure 4.9 Chapter 3 Figure 3.11 Figure 1.1 Figure 1.13 Chapter 2 Figure 2.2 Figure 4.2 Figure 3.2 Figure 2.7 Figure 1.12 Figure 1.10 Figure 1.5 Figure 3.6 Figure 1.8 Figure 2.8 Figure 3.3 Figure 2.1 Figure 2.4 Figure 2.2 Figure 1.6 Communication transceiver: TX and RX systems Heterodyne Receiver _ Terrestrial TV Frontend DVB Satellite transmission modes Satellite Receiver Frontend: heterodyne and ZIF architectures Local Oscillator Spectral Purity X SNR Carrier Spectrum QPSK constellation + phase deviation Phase Noise requirements PLL frequency synthesizer: block diagram VCO and tunable resonator Phase Detector & Charge Pump block diagram Phase detector & Charge pump: transfer and state machine 2 4 6 7 9 10 11 12 16 16 18 19 PLL linear Phase Model Vtune time response for a frequency step Locked VCO output spectrum 3rd order Loop Filter Impedance 4th order PLL: Open and Closed Loop Bode Plots 4th order PLL: Root Locus diagram Gain Variation X Stability in Bode Plots The influence of r21 in the gainbandwidth variation Numerical example of robust filter design 23 25 25 29 31 31 33 36 42 BB noise representation of the VCO Free running VCO power spectrum density PSD of a VCO locked by a PLL Peaking X Optimum Closed Loop bandwidth Combined Spectrum: PLL + VCO noise contributions Rootlocus for w3dB location Rootlocus for was location Optimizing Total Phase Deviation Maximum SSB noise requirement 47 49 49 50 52 58 60 63 64 Active Loop Filter Fully 3rd order passive filter impedance Active Filter AC model Loop rootlocus with active filter Active Filter example: Bode plots Active filter: input impedance 70 72 73 75 77 79 .4 Figure 4.4 Figure 3.5 Figure 2.9 Figure 1.6 Figure 2.7 Figure 3.4 Figure 1.7 Figure 2.5 Figure 4.
vi PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops Figure 4.9 Figure 5.7 Figure 5.2 Figure 7.10 Figure 5.2 Figure 6.6 Figure 7.2 Figure 5.9 Chapter 7 Figure 7.5 Figure 5.7 Supply disturbances Amplifier noise Filter components noise Noise simulation schematic Noise simualtion results 82 83 83 85 86 Phasedetector & Charge Pump transfer Maximum Phase Detection Range & Cycle slips Condition for unlimited frequency tracking range Loop Filter: time response for current pulses Time response through normalized functions Convergence towards lock: phase deviation sequence Frequency approach convergence criterion Phase approach convergence criterion Comparing frequency and phase approaches Convergence approaches X leadlag spacing r21 Convergence approaches X gain variation Discrete model for digital blocks Discrete phase detector input: ∆ϕn Charge Pump DAC output Continuous equivalent with transmission delay Frequency and Time response for the continuous+delay model 91 92 93 94 96 99 103 104 105 107 108 110 111 112 114 115 Spectrum Analyzer Output FM & PM carriers SSB superposed noise: AM + PM decomposition (phasor) Superposed Noise: AM + PM decomposition (spectrum) Phase modulated carrier by DSB superposed noise Phase deviation from DSB sidebands Slope approach: voltage & time deviations Periodic transfer determined by a large signal Large Signal Transfer: ideal and hyperbolictangent limitations 124 128 129 130 131 132 133 136 138 PLL block diagram with signal+noise inputs Noise Transfer Slopes Synthesizer Noise Floor Sampled Loop Model Large bandwidth noise folding DFF plus superposed noise in the clock input: time domain signals DFF plus superposed noise in the clock input: frequency domain signals 142 143 144 148 152 155 155 .5 Figure 6.6 Figure 6.13 Figure 5.11 Chapter 5 Figure 5.12 Figure 5.8 Figure 6.4 Figure 6.11 Figure 5.6 Figure 5.1 Figure 7.8 Figure 5.9 Figure 4.4 Figure 5.3 Figure 7.10 Figure 4.3 Figure 5.14 Figure 5.3 Figure 6.1 Figure 5.1 Figure 6.7 Figure 4.16 Chapter 6 Figure 6.5 Figure 7.4 Figure 7.8 Figure 4.7 Figure 6.15 Figure 5.
9 Figure 7.8 Figure 8.8 Figure 7.6 Figure 8.12 Figure 7.7 Figure 8.9 Figure 8.1 Figure 8.5 Figure 8.13 Chapter 8 Figure 8.11 Figure 7.2 Figure 8.10 Charge Pump current noise levels within one period Behavioural model for AC and noise simulations Behavioural model for transient simulations Digital Demodulator and Decoder Noise Power added by the LO sidebands Behavioural Model of the Carrier Recovery loop 158 160 161 162 164 167 GmC integrated oscillator Double loop MOPLL: block diagram Block diagram of TC2 Photo of a testchip TC2 TC2 _ inloop spectrum for N1=7 and fcp1=300Mhz TC2 _outofloop spectrum for N1=6 and fcp1=300MHz TC3 _ single low noise PLL plus QCCO Simulation result for the SSB phase noise _ linear scale Spectra for ∆fstep =125kHz and flo =900MHz Phase noise simulation for DL+QCCO with and without demodulator 171 174 176 177 179 179 181 182 186 186 .10 Figure 7.3 Figure 8.4 Figure 8.List of Figures vii Figure 7.
wp2 ] 3rd order filter: Phase Margin Variation for wol ∈ [ wz1 .viii PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops List of tables Chapter 1 Table 11 Chapter 2 Table 21 Table 22 Table 23 Chapter 3 Table 31 Table 32 Table 33 Table 34 Chapter 4 Table 41 Table 42 Table 43 Table 44 Chapter 6 Table 61 Table 62 Chapter 7 Table 71 Table 72 Table 73 Table 74 Chapter 8 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Table 87 Table 88 DVB standards: bandwidth and modulation types 2nd order filter: Phase Margin Variation for wol ∈ [ wz1 . Parameters of the two zeroIF configurations being compared Parameters and outputs for comparative analysis Settings of the demodulator block Phase Jitter and implementation loss for rs=30Msps and fLO = 2. wp2 ] 3rd order filter : Open Loop Bandwidth recentering 10 37 38 39 Comparing the denominators of B(s) and BRL(s) Rootlocus approach for wcl : parameters of BRL(s) Gain Stability Boundary Maximum Normalized Gain Variation Fully 3rd order passive filter: ∆PhM and ∆GM Active Filter example: Phase Margin degradation Disturbances transfer functions Noise sources voltage spectrum density 54 58 65 66 72 78 84 87 Phase Modulated Carrier Phase Noise X CNR 126 132 Data sheet points from: TSA5059 .low noise PLL The influence of fcp change for narrow band noise The influence of fcp change for large band noise Implementation Loss X Phase deviations 145 151 153 166 Measurements of the frequency coverage of the QCCO Double Loop: minimum step and comparison frequencies.2GHz Phase Jitter and implementation loss for rs=3Msps and ∆fstep = 125kHz Margin for degradations in the oscillators phase noise performance 172 175 183 184 185 188 188 189 .
Hz/V] phase noise density [rad/sqrt(Hz)] current noise density [A/sqrt(Hz)] time noise density [s/sqrt(Hz)] voltage noise density [V/sqrt(Hz)] phase deviation or phase error [rad] phase deviation as a discrete variable [rad] Fourier transform of ∆ϕn(nT) peak value of a phase deviation [rad] minimum tuning step of a synthesizer [Hz] phase of the main divider output [rad] phase error at the phase detector input [rad] phase of the single tone modulating signal vm(t) [rad] phase of the single tone noise component vn(t) [rad] phase of the controlled oscillator [rad] phase of the reference input [rad] ksi. damping factor.Hz/V] nominal gain value after the compensation wrt the postfilter [A. vn(t) [V] amplitude of the spurious sidebands wrt the carrier amplitude [dBc] closed loop transfer function ϕosc/ϕref.List of Symbols and Abbreviations ix List of Symbols and Abbreviations Symbols α: αn: αnpf: δϕi: δii: δti: δvi: ∆ϕ: ∆ϕn(nT): ∆Ψn(w): ∆ϕp: ∆fstep: ϕdiv: ϕe: ϕm: ϕn: ϕosc: ϕref: ξ: σϕ: τ: τrst: θn(t): Ac: Am: an(t): An: As: B(s): BRL(s): Bvco(s): BvcoBPF(s): B3LPF(s): DB(s): DG(s): Ds(s): F(s): fi: fc: fcl: gain of the open loop transfer function [A. dimensionless approximation of B(s) derived from the root locus closed loop transfer function ϕosc/vnvco [rad/V] bandpass filter approximation for Bvco(s) [rad/V] 3rd order lowpass filter approximation for B(s) denominator of the closed loop transfer function B(s) denominator of the transconductance of the loop amplifier denominator of Zs(s) loop filter transfer function in Laplace variable [Ω] intersection frequency for the PLL and VCO noise asymptotes [Hz] carrier frequency [Hz] bandwidth of the closed loop transfer function B(s) [Hz] . dimensionless total phase deviation [rad or °] time delay [s] time delay for the reset of the phase detector [s] phase modulating noise amplitude of the carrier signal [V] amplitude of the modulating signal [V] amplitude modulating noise amplitude of a single tone noise component.Hz/V] nominal gain value for loop filter calculation [A.
derived from the phase approach gphap: gm: transconductance [Ω1] Gmo: DC value of the transconductance of the loop amplifier Gvo: DC value of the voltage gain of the loop amplifier g(x. ipw(t): output of the charge pump with a delay equals Tw [A] ini. dimensionless N: PLL main divider ratio.x PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops fcp: comparison frequency at the phase detector [Hz] fj . folnpf: frequencies related to woln and wolnpf [Hz] fosc: frequency of the controlled oscillator [Hz] frecover: intersection between flicker and white noise contributions of a transistor [Hz] fp2. iZOH(t): output of the charge pump for a ZOH approach [A] Ipw(w). dimensionless Npll: noise of the PLL as a phase noise density [rad/sqrt(Hz)] Ns(s): numerator of Zs(s) PhM: phase margin for a open loop transfer function [°] p: normalized time deviation Td/Tcp Q: charges [C] Vtune: tuning voltage for the VCO [V] . Ini: current noise density from component i [A/sqrt(Hz)] Kϕ: sensitivity of the phase detector plus charge pump comparator [A/rad] Kcco: frequency sensitivity of a currentcontrolled oscillator [Hz/A] Ko: VCO frequency sensitivity [rad/(s. fp3: frequencies of 2nd and 3rd poles of the loop filter [Hz] fz1: frequency of the zero of the loop filter [Hz] f3dB: 3dB attenuation frequency for the closed loop transfer function B(s) [Hz] GChPZOH(s): transfer function of the charge pump as a ZOH [A/rad] GChPpw(s): transfer function of the charge pump as a holder with Tw delay [A/rad] gfrap: function expressing the maximum fcl.r21): function expressing the time response of vtune . derived from the frequency approach function expressing the maximum fcl. LdB(f): singleside band phase noise [1/Hz. dimensionless hPLS(t). Fj: frequency of j [Hz] fm: frequency of the modulating signal [Hz] fn: frequency of a single tone noise component. HPLS(f): transfer function related to a periodic large signal H(s): open loop transfer function ϕdiv/ϕe. vn(t) [Hz] fno: offset frequency of vn(t) wrt the carrier [Hz] foffset: frequency increment with respect to the frequency of a reference signal [Hz] fol: zerocrossing frequency for the open loop transfer function H(s) [Hz] foln. dBc/Hz] Lpll(f): L(f) in the inloop zone of a locked VCO spectrum [dBc/Hz] L(f) of the freerunning oscillator [dBc/Hz] Lvco(f): nlim: aliasing factor related to the sampling of large bandwidth noise.V)] Kvco: VCO frequency sensitivity [Hz/V] L(f). dimensionless Iaverage: average current at the output of the charge pump [A] Icp: charge pump current [A] leakage current at the tuning input [A] Ileakage: IZOH(w).
vd(t): voltage disturbance signal [V] vM(t): tuning voltage for a 2nd order filter impedance [V] vni. dBc/Hz] SJ(f): power spectrum density of J Tcp: comparison period [s] Td: delay or time interval between the two inputs of the phase detector [s] Tp2. wp3.List of Symbols and Abbreviations xi RJ(τ): autocorrelation function of the random process J Rpu: pullup resistor in an active loop filter [Ω] rpf: postfilter factor for the compensation of αn and woln r21: 2ndpole to zero ratio for loop filter r31: 3rdpole to zero ratio for loop filter Sϕ(f). Tp3. Zfilter(s): impedance of the loop filter [Ω] ZFa(s): impedance of the active loop filter [Ω] ZFai(s): impedance of the active loop filter with a nonideal input impedance [Ω] ZF3(s): full 3rd order impedance of the loop filter [Ω] Zin: input impedance [Ω] Zs(s): series version for the leadlag filter impedance [Ω] Zo: output impedance [Ω] Zp(s): parallel version for the leadlag filter impedance [Ω] Z3(s): postfilter impedance [Ω] Z3u(s): impedance of the postfilter in parallel to the pullup resistor [Ω] . SϕdB(f): mean square phase fluctuation power [rad2/Hz. wz1: angular frequencies related to the zero and poles of the loop filter [rad/s] ws: sample angular frequency [rad/s] w3dB: angular frequency related to f3dB [rad/s] x: bandwidth ratio foln/fcp ZF(s). Tz1: time constants related to the zero and poles of the loop filter [s/rad] Vd(s). Vni: voltage noise density from component i [V/sqrt(Hz)] vn(t): single tone noise component [V] voltage noise density from the loop filter at the input of the VCO [V/sqrt(Hz)] vnf: vnvco: inherent noise of the VCO as a voltage noise source [V/sqrt(Hz)] w: angular frequency [rad/s] wa: pole of the loop amplifier [rad/s] was: intersection frequency for the asymptotes of the root locus [rad/s] angular frequency of the carrier signal [rad/s] wc: wcl: bandwidth of the closed loop transfer function B(s) [rad/s] wcp: angular comparison frequency [rad/s] wn: natural frequency [rad/s] wol: zerocrossing angular frequency for the open loop transfer function H(s) [rad/s] nominal value of wol for loop filter calculation [rad/s] woln: wolnpf: nominal value of wol after the compensation wrt the postfilter [rad/s] wp2.
refers to the quiescent state of a circuit direct digital synthesis Dtype flip flop doubleside band digital video broadcasting frequency of unity current gain for a transistor frequency modulation transconductance and capacitor integrator for a ring oscillator integrated circuit intermediate frequency in phase and quadrature signals bidirectional 2wire bus for interIC programming and control inductor and capacitor resonator left hand plane in a sspace (Laplace transform) low noise amplifier local oscillator low pass filter linear time invariable system multichannel per carrier mixeroscillator plus phaselockedloop circuit ntype bipolar junction transistor orthogonal frequency division multiplexing.xii PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops Abbreviations AC: ADC: AGC: AM: BB: BiCMOS: BPF: bw: CMOS: CNR: DAB: DAC: DBS: DC: DDS: DFF: DSB: DVB: ft: FM: GmC: IC: IF: I/Q: I2C: LC: LHP: LNA: LO: LPF: LTI: MCPC: MOPLL: NPN: OFDM: PLL: PM: PMOS: PNP: PSD: PWM: QAM: QCCO: alternate current. refers to small signal frequency domain models (commonly named AC models in analog simulations) analog to digital converter automatic gain control amplitude modulation base band IC founding process with both BJT and CMOS devices bandpass filter bandwidth complementary metaloxidesemiconductors carrier to noise ratio digital audio broadcasting digital to analog converter direct broadcast satellite direct current. type of multicarrier modulation phase locked loop phase modulation Pchannel metaloxidesemiconductor ptype bipolar junction transistor power spectrum density pulse width modulation quadrature amplitude modulation. type of digital modulation quadrature current controlled oscillator .
television broadcasting band voltage controlled oscillator voltage to current converter vestigial side band. type of digital phase modulation resolution bandwidth in a spectrum analyzer radio frequency right hand plane in a sspace (Laplace transform) receiver in a telecommunication system surface acoustic wave filters singlechannel per carrier satellite demodulator and decoder synthesizer noise floor signal to noise ratio singleside band square root testchips #2 and #3 time division multiplexing transient analysis in analog simulation television transmitter in a telecommunication system very high frequency.List of Symbols and Abbreviations xiii QPSK: RBW: RF: RHP: RX: SAW: SCPC: SDD: SNF: SNR: SSB: sqrt: TC2. TC3: TDM: TR: TV: TX: VHF: UHF: VCO: V/I: VSB: wrt: WSS: Xosc: ZIF: ZOH: 3W: quadrature phaseshift keying. architecture of a frontend zero order holder unidirectional 3wire bus for interIC programming . property of some stochastic processes crystal oscillator zeroIF receiver. television broadcasting band ultra high frequency. type of modulation with respect to wide sense stationary.
In particular. where the gain parameters vary within a large range. Frequency synthesizers are a common block of the frontend of RF telecommunication systems. Chapter four examines the active loop filter configurations and continues the noise analysis.xiv PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops Preface The central issue of this thesis is the stability and noise performance of PLL frequency synthesizers. A discrete time domain approach is compared to a continuous frequency model with an equivalent delay. describing their basic functionality. Most of the thesis dissertation is concerned with models: calculations and behavioural simulation tools. . are bringing new issues for IC design and application. Chapter one introduces the context of the TV tuner and the current tendencies in architecture and IC requirements. and the maximum comparison frequency that still guarantees the frequency tracking behaviour of the tristate phase detector. Application constraints related to phase deviations and reference breakthrough are discussed in the light of this algorithm. These tendencies point to low phase noise synthesizers. in chapter three. The design of a monolithic mixeroscillator and PLL synthesizer is also presented and used as a practical example to compare the simulations and calculation tools with measurement results. The assumptions of a narrow band FM modulation and a periodic steady behaviour are combined. An example of phase jitter optimization for a satellite synthesizer is discussed. They concern the maximum feedback bandwidth for a loop that is partially discrete. In chapter five we continue to discuss other limitations of the linear time invariable model of the frequency synthesizer. and the continuous trend for higher integration levels. The relationships among the different notations are explored. We focus on the context of TV broadcasting tuners. PLL synthesizers are extensively used for their programming flexibility. where the new standards of digital modulation broadcasting (DVB) which are appearing. implemented in very monolithic architectures with integrated oscillators. Chapter two studies the stability and robustness of a phaselocked loop in a tuner application. which were developed to support the activities of design and engineering for the integrated circuits in frequency synthesizers. ease of integration and low production cost. This is the beginning of a topdown analysis about the phase noise in the local oscillator (LO) signal. The constituent blocks of the PLL synthesizer are presented. The noise performances of the PLL and the VCO are adjusted by centering the closed loop bandwidth of the feedback. in a first example that descends to a circuit implementation level. An algorithm for the loop filter calculation is developed. in order to develop a linear time variable transfer for the noise. It allows a systematic and consistent approach to combine the IC parameters and the filtering requirements. The AC characteristics of the filter amplifier exemplify the first nonideal aspects of the phase model of the PLL. Chapter six presents the theoretical basis of the generation of phase noise. and discusses different possibilities of notation that are compared to measurement and simulation tools.
or more specifically the electrical engineering laboratory CEGELY. Normandie. Furthermore we discuss behavioural models to mix system and circuit descriptions in simulations.List of Symbols and Abbreviations xv In chapter seven. Finally we compare the spectra of two synthesizers: a single loop PLL plus an LC oscillator and a double loop synthesizer plus a GmC oscillator. Caen. they contain a PLL and a monolithic GmC oscillator that covers the satellite band L (950MHz to 2150MHz). and the margin for production for the most critical parameters is calculated. and two simulation examples are presented. This thesis was developed in the industrial site of Philips Semiconductors in Caen. Practical examples. due to the phase deviations in the LO. We also present considerations about the implementation loss in the receiver due to the phase deviations in the LO signal. Marina de Queiroz Tavares . It was part of a collaboration contract between Philips Semiconductors and the INSA de Lyon. the phase noise issue is detailed to the circuit level. are presented in chapter eight. simulations and measurements. The parameters that can distinguish the dominant noise sources in measurements are identified. both for a QPSK near zeroIF receiver. with an inloop noise in the order of –108dBc/Hz. June 99. The testchip designs are briefly presented. Testchip TC2 is part of a double synthesizer with a comparison frequency that goes up to 330MHz. Testchip TC3 explores the maximum bandwidth of a single loop PLL and confirms the theoretical approach of chapter five. The comparison refers to the allocation of implementation loss in a tuner. by an analysis of the noise performance of the different constituent blocks of the PLL. where these analytical tools are used to design and evaluate two testchips. Two examples of high and low bit rate channels are discussed. I would like to thank all of the colleagues within Philips Caen and Philips Eindhoven for their help and support. France.
Chapter 1 / Introduction
1
Contents:
1 1.1 1.2 1.3 1.4 Introduction 1
The frontend in a telecommunication receiver.........................................................................................2 The frontend in TV broadcasting .............................................................................................................3 Current tendencies: low noise and higher integration.............................................................................9 PLL systems : different application contexts .........................................................................................14
1.5 PLL frequency synthesizers constituting blocks and nomenclature .......................................................15 1.5.1 VCO ...............................................................................................................................................16 1.5.2 Dividers..........................................................................................................................................17 1.5.3 Phase Detector – Charge Pump......................................................................................................17 1.5.4 Loop Filter .....................................................................................................................................19
Figures:
Figure 1.1 Figure 1.2 Figure 1.3 Figure 1.4 Figure 1.5 Figure 1.6 Figure 1.7 Figure 1.8 Figure 1.9 Figure 1.10 Figure 1.11 Figure 1.12 Example of a communication transceiver: TX and RX systems ................................................2 Heterodyne Receiver _ Terrestrial TV Frontend.......................................................................4 DVB Satellite transmission modes...............................................................................................6 Satellite Receiver Frontend: heterodyne and ZIF architectures...............................................7 Local Oscillator Spectral Purity X SNR .....................................................................................9 Carrier Spectrum........................................................................................................................10 QPSK constellation + phase deviation........................................................................................11 Phase Noise requirements ..........................................................................................................12 PLL frequency synthesizer: block diagram..............................................................................16 VCO and tunable resonator .......................................................................................................16 Phase Detector & Charge Pump block diagram ......................................................................18 Phase detector & Charge pump: transfer and state machine .................................................19
Tables:
Table 11 DVB standards: bandwidth and modulation types......................................................................10
1 Introduction
In this chapter we locate the context of this thesis by introducing basic aspects and innovation tendencies for the frontends of TV broadcasting receivers. This thesis focuses on the frequency synthesizer block, which is a constituent part of the frontend. PLL frequency synthesizers are a common element of different telecommunication receivers that are produced on a large scale. This choice is connected to their compactness and low cost, both of which are continuously improved by larger integration levels. Furthermore, emerging digital modulation techniques are imposing new requirements on this block, which carries out the frequency conversion of the input data. Finally, we shortly describe the constituent elements of the PLL synthesizer, so as to present their functionality and general structure.
2
PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
1.1 The frontend in a telecommunication receiver
Communication and transport are probably the key technological fields that most changed daily life in the 20th century. Our world became smaller, because it may be rapidly crossed by waves and engines taking information and people worldwide. The term communication system is employed here to include transceivers that convert data into electromagnetic waves (transmitters_TXs) and the other way around (receivers_RXs), in order to transmit this data through a fast moving media such as air, metallic cables, optical fibers and others. The TX and RX have two basic parts, namely: • Backend: data processor and (de)modulator; • Frontend: frequency translator and selectivity. The first one is in charge of transforming data into a convenient manageable electrical signal i that is later transposed into a well defined frequency window (channel) by the second.
input data
data processor + Modulator
Up Conversion
output data
Down Conversion + Selectivity Demodulator + data processor
Frontend
Backend
Figure 1.1
Example of a communication transceiver: TX and RX systems
The spread of communication systems relies on the advance of modulation techniques, digital signal treatment and RFfrequency electronics. The first two greatly increased the amount and quality of transmitted information, and the last one enabled the utilization of an increasing range of the frequency spectrum. However this spectrum range is limited by the physical properties of the conducting materials and the maximum working frequencies of the electronic devices employed. So further exploitation of this already crowded spectrum depends on a greater compaction of modulated data, or capacity to share the same frequency range (spread spectrum modulations). Occupying narrower frequency bands with higher information density decreases the margin for signal degradation in the up and down conversion of the data in the TX and RX systems. In other words, modulation types with increasing bandwidth efficiency require higher signaltonoise ratio (SNR) for a correct reception.
i
There are also communication systems that use base band transmissions, i.e. the data is directly transmitted after modulation, without being frequency translated. However the applications are usually restricted by their maximum data flow.
Chapter 1 / Introduction
3
Up and down conversions are carried out by mixing data signals with carrier signals in TXs, or by mixing channels with carrier signals in RXs. Therefore the loss of quality due to this operation depends on the mixer and carrier qualities. Mixer performance is usually specified in terms of conversion gain, noise figure and linearity parameters, amongst others. There is a compromise between the parameters of gain on one side and linearity and noise figure on the other. This compromise has to be solved in combination with the specifications of the filtering and amplification stages, taking into account the constraints of consumption and signal quality. The carrier signal performance includes factors such as frequency tunability and spectrum purity. The frequency tunability refers to the coverage of a frequency range, with a certain resolution or minimum variation step. The carrier spectrum quality is often defined by a carriertonoise ratio (CNR), specified in accordance to the modulation nature and SNR requirements of the data signal. Carrier signal generation can be split into three basic types:  Direct digital synthesis (DDS), using sine lookup tables, accumulators and digital clocks. They are often limited in speed and quality by the maximum clock frequency. Thus, they are more frequently employed in bandbase (BB), or intermediatefrequency (IF) stages; mainly after analogtodigital data conversion (ADC). Mixerdivider chains, combining an ensemble of reference oscillators, through frequency conversion and filtering. Increasing the precision and the frequency range is a trade off with size, integrability and power consumption. They are often bulky systems that become hardly integrable as the number of reference sources increases. For nonintegrated systems, the advantage of keeping the spectral purity of the sources may be decisive.

Feedback loops with a reference source and a programmable counter block to sweep the frequency range of a tunable oscillator. Phaselocked loop types are the most widespread in transceiver applications. Integrability and low cost are the main advantages, but settling times are elevated compared to methods of direct synthesis. A wide span of systems of hybrid generation combine the basic types above to explore the advantages of each architecture. They may be generally called multiloop architectures, as they compose the carrier signal through two or more loops in different concatenated and/or interlaced structures. The scope of the present work is centered around PLL frequency synthesizers for terrestrial and satellite TV receivers. Stability and noise issues are discussed and applied to single and double loop architectures. The models developed for stability and disturbance are certainly useful for other PLL applications, but the issues and numerical examples are oriented by the primary context.
1.2 The frontend in TV broadcasting
The block schematic below represents a heterodyne receiver, detailing the elements of the ii selectivity and frequency conversion stages.
ii
The denomination heterodyne or superheterodyne, is given to receivers working with two distinct amplification and filtering sections prior to demodulation.
(3) double RF filter: middle bandwidth filtering. linearity and noise figure constraints. (8) IF signal treatment: amplification. demodulation and signal level detector. (6) IF preamplifier: gain prior to selective filtering to keep minimum SNR. and frequency tuning for oscillator and input filters tracking. (5) Level detector BB output data VCO or LO Vtune PLL TUNE VAGC Figure 1. (2) RF preamplifier: 1st amplification stage (keeping SNR). rejecting image channel and also blocking VCO signal . plus buffer avoiding fosc leakage towards the antenna input. .2 Heterodyne Receiver _ Terrestrial TV Frontend (1) 1st RF filter: large bandwidth filtering plus impedance adaptation between antenna and preamplifier. (7) IF filter: fixed frequency very selective filtering (SAW filter).4 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops RF stage IF stage (1) (2) (3) (4) (6) (7) (8) video & audio demod. (4) Mixer: frequency conversion kernel: conversion gain. (5) Local Oscillator (LO) + PLL tuning system: carrier generator for downconversion.
In a TV set the tuner is easily recognized by its metallic screening box.400 MHz . but usually outside the reception bands. assuring the correlation of their frequency variation. The audio is transmitted through a modulated subcarrier that is placed in the high end of the channel bandwidth. After the first frequency downconversion. with another 60 dB controllable amplification capacity in the demodulator. these characteristics usually oppose each other. A convenient amplification level is assured by an automatic gain control (AGC) loop. having one set specific for the reception of the VHF bands. Therefore the RF stages covering the whole input frequency range are necessarily less selective than the IF stage. the input data appears around the IF.VHF III: 140 MHz . with the following typical values of i RF and IF frequencies and bandwidths: • RF input. i The frequency values indicated for the terrestrial and satellite applications are just a rough range. The highest possible IF value is chosen.Chapter 1 / Introduction 5 In figure 1.8 MHz Most of the channel bandwidth is occupied by the video information. The work in this thesis deals with stability and noise aspects of the PLL plus RF oscillator ensemble. working at a fixed frequency. There are several standards with different values for RF.140 MHz .UHF: 400 MHz . close to the most common standards. and the other for UHF. For instance.2 the incoming signal is initially modulated at the channel or RF frequency. to avoid direct coupling between the RF input and the IF output. correlating their specifications and design constraints to the tuner application requirements. • The bandwidths of bandpass filters (1) and (3) vary significantly amongst the different applications.55 MHz The choice of Fvco larger than FRF reduces the relative tuning range (fmax/fmin) of the local oscillator. . and passes a sharper selectivity stage represented by filter (7). The rejection of this same filter for the image channel is in the order of 60 dB. • Channel bandwidth: 6 MHz . comparing the RF oscillator to a reference crystal oscillator. RF filters and oscillator are constructed with similar resonant circuits. to ease the filtering of the image channel. channel frequency range divided in three bands: . For elements with a frequency dependent behaviour. The frequency tuning of the RF stages is made by the PLL block. • The AGC dynamic for the amplifying blocks of the tuner is generally between 40 and 50 dB.860 MHz The input amplifier. filter (3) may present a bandwidth between 7 and 25 MHz. The elements constituting the tuner are indicated by the dotted arrow. filtering and mixing stages are often doubled. The frequency variability is guaranteed by programmable counters interpolated in the control loop. where a primary rough selection is carried out by filters (1) and (3). used for RF isolation. mixing and amplification blocks reflects an important tradeoff between selectivity and frequency tunability. Filter (7) presents a sharp selectivity for the neighbouring frequencies. IF and channel width. and a bandwidth in the order of 5MHz. for both terrestrial and satellite applications.2 represents a terrestrial tuner architecture. • Most standards work with: Fvco = FRF + FIF and IF typically within the range : 39 MHz . In fact figure 1. also named tracking characteristic or matched filteroscillators. The sequence of filtering. The tuner architectures and the issues studied are focused on the TV reception context. with an amplitude sensor at the BB stage.VHF I: 47 MHz . It contains a feedback control system. between 4 and 6 MHz.
which imposes a first frequency conversion close to the antenna. The choice of the 2nd IF was connected to the availability of SAW filters with Nyquist slope at this frequency. • SCPC (singlechannel per carrier): several narrow bandwidth channels splitting the transponder spacing. • Transponder bandwidth: 33 MHz – 36MHz . Kuband: 10. Satellite tuners have a slightly different architecture. using multiplexing in frequency and time domain (see figure 1. • Constant LO frequency downconverting block: LNA (low noise amplifier) Due to the strong attenuation between the satellite and the RX antennas. have different channel compositions. MCPC QPSK SCPC QPSK FM Multicast QPSK 13dB 36MH Figure 1.Direct Broadcast Satellite).4. in order to support the losses through the cable binding the antenna and the RX frontend. .3 DVB Satellite transmission modes The first RX systems for QPSK channels used a double IF heterodyne architecture. • Multicast (analog+digital channels): a standard analog FM channel of 27 MHz bandwidth multiplexed in frequency with a 9MHz wide digital channel. The last LO converting the data to the base band has quadrature outputs. as shown in figure 1.7 GHz .3). whose ADC input is connected to the bandbase output of last mixing stage. this block has tight noise figure requirements. band L : 950 MHz . • 1st RF at the antenna input.2150 MHz . use FM modulated channels with a bandwidth varying between 27 and 36 MHz. transmitted with a power level 13dB below the analog channel.6 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops For analog standards. splitting the output data in I (in phase) and Q (quadrature) outputs.75 GHz . Kuband. to start causing visible errors in the video reception. • 2nd RF at LNA output. • MCPC (multichannel per carrier): single modulation package multiplexing in time (TDM) up to 8 TV channels transmitted in a bit flow with rates around 55 Mbps.12. is rather elevated. regarding the ensemble of signals transmitted by a single amplifier in a determined frequency window. (DBS . In this case we prefer to refer to the frequency spacing as the transponder bandwidth. The older analog standards. (satellite DVB – Digital Video Broadcasting). with 1st LO: Fvco1 = FRF + FIF1 nd • 2 IF: 70 MHz. The more recent digital norms. the minimum SNR at the IF output is in the order of 55dB. and a downmixing stage with a LO containing 2 outputs in quadrature. with the following intermediate frequencies: • 1st IF: 460 MHz – 480 MHz. The demodulation and decoding are performed by a digital IC. The RF transmission bandwidth.
Chapter 1 / Introduction 7 RF stages 1st RF VCO IF and/or BB I Q SAW 90° Level detector Demodulator BB output data LNA down converter Vtune PLL VAGC 2 nd heterodyne receiver Fvco = FIF + FRF FIF ~ 470 MHz I Q Vtune 90° ADC & filters carrier & clock recovery forward error correction Satellite (SDD) demod. & decoder BB output data VAGC VCO Level detector Vtune PLL VAGC Nearzero IF receiver Fvco = FRF Figure 1.4 Satellite Receiver Frontend: heterodyne and ZIF architectures .
containing the necessary information to distinguish the two superposed spectra.4dB for QPSK modulated data [Sinde98a].8 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops In more recent systems the Nyquist filtering is integrated in the digital IC realizing the demodulation and signal decoding. A maximum biterror rate (BER) of 104 is usually acceptable for most decoders. and a nearzero IF (named ZIF or zeroIF for short) receivers. Besides. The bandwidths of the filters are greatly dependent on the application.4 illustrates block schematics of a heterodyne. The limitations are connected to the performance of several blocks such as: .4). . However the latter suffers from much larger attenuation in the transmission path. but is programmed to a frequency close to the RF carrier. neighbouring channels may come from different TXs and consequently their incoming power vary greatly according to the TX and RX “line of sight”. We can note the large difference of the minimum SNR for the reception of analog terrestrial TV signals and the satellite digitally modulated ones. The difference between the output spectrum and a real BB signal are recovered by the digital demodulator in the so called. Finally the latest satellite tuner ICs are concentrating in a monodyne. is to the order of 50 dB. The precision is also limited by the minimum allowable tuning step in the LO controlling loop.5dB) and quadrature (<3°). single IF. . and furthermore they are adapted to the demodulation of the QPSK modulated data. for the tuner. as they come from a common TX source. The nomenclature nearzero IF stress the fact that the LO signal is not locked to the RF input. Figure 1. besides their frequency ranges. carrier recovery loop. is the constraint for the filtering of the neighbouring channels. Another important difference between the terrestrial and satellite applications. It is certainly an architecture allowing greater compactness and economy in external components. but also increasing the performance constraints for the integrated blocks and the surrounding application. nearzero IF architecture (see lower half of figure 1.the matching of the I/Q stages in BB. The I and Q outputs have this convenient format. the rejection of the image channel (which is now the selected channel but with a spectrum reversion) can be replaced by a proper output form.the quadrature LO. Satellite transmitted channels have the same power levels at the RX input. . Thus an intermediate heterodyne architecture uses a single IF (similar to the 1st IF above) and a quadrature LO at this IF frequency (see upper half of figure 1. and needs to fulfill the conditions of minimum mismatches in amplitude (<0. In both configurations the AGC dynamic range.4). The minimum SNR at the base band output will depend on the maximum biterror rate that can be corrected by the signal decoder. There is one single stage of frequency translation between the 2nd RF (band L) and the BB output. The advantages are connected to the suppression of the IF stage and the replacement of the SAW – BPF by a discrete and cheaper LPF. In fact the monodyne RX is especially sensitive to coupling between the RF and LO signals (in this case at the same frequency) and to interference generated by intermodulation products of even orders (appearing at low frequencies). In terrestrial transmission. which now works in the band L. and it implies a minimum SNR of 11.the isolation and linearity of the RF amplifiers and mixers. and it would not be feasible to work with such high SNR as in the terrestrial systems.
From now on. a MOPLL. Nowadays. tuners often have one single integrated circuit (IC). In the next section we discuss some current tendencies in the development of tuner ICs. This level of integration is the result of a continuous miniaturization that combines the functionality of several ICs and also integrates parts of previously discrete circuitry. with respect to selectivity and SNR degradation.2 and 1. . centered around fch2 . Figure 1. are imposing new constraints on the CNR of the local oscillator. mixeroscillator and IF amplifier blocks. decreasing the SNR and adding noise which is correlated to the signal.5 illustrates the importance of the carrier spectral purity for the proper reception of neighbouring channels with different input power.3 Current tendencies: low noise and higher integration Current trends in the tuner circuit developments are bound to the developing standards using digitally modulated signals. where different phase delayed versions of the input signal reach the RX. other more strict parameters of spectral purity are added. may be translated to corresponding specifications for the frequency synthesizer block. Specially for strongly attenuated signals this is an important drawback. This example introduces the idea that the tuner requirements. based on phase modulation techniques and/or using closely spaced multicarriers. is degenerated by an adjacent channel down converted by a noisy local oscillator. including the PLL.Chapter 1 / Introduction 9 The “line of sight” concerns the distance and blocking obstacles. i Signal reflection causes multipath reception. and to the continuous demand for higher integration levels. Therefore from the basic requirements of the frequency synthesizer concerning the tuning range and the resolution. causing attenuation and i reflection of the transmitted signal.4). marked by a gray rectangle in the frontend schematics (figures 1. RF fch1 fch2 IF flofch1 LO flo Figure 1.5 Local Oscillator Spectral Purity X SNR flofch2 The channel with lower input power. relating the new requirements to the emerging digital broadcasting systems. Furthermore the more recent digital standards. 1. we concentrate our attention on the frequency synthesizer block.
Analog terrestrial TV standards use vestigial sideband (VSB) modulation and FM for the video information and either FM and AM signals for audio.g. In Europe the DVBS.: 33MHz – 36MHz Not fixed.47kHz / 1.: 34. e. the noise added by a local oscillator with 1/f2 power sidebands (as represented in figure 1. Besides the video signal needs higher signal quality for an interferencefree (or errorfree) reception.9MHz Not fixed.7 – 12. and in the PLL synthesizer context we will see that it is directly associated to the phase noise in the carrier signal. e.27 VHF I VHF III UHF DVBC Single carrier MQAM modulated (M=16. In satellite applications the analog standards use FM signals. are a translation of the CNR required for the reception. transmitted by the VCO intrinsic noise.61MHz 10. we concentrate on the video signal because of its larger amount of information compared to the audio signal. carrier spectrum. The spectral purity is largely discussed during this work.5 / 2 / 3 ∆f= 8kHz /…/ 1kHz 1. white distributed noise interfering in the output data.75GHz 2nd RF: 950 – 2150MHz Not fixed.g.37 VHF I VHF III UHF Table 11 DVB standards: bandwidth and modulation types . cable and terrestrial or offair systems.6 Carrier Spectrum Digital video broadcasting standards and services have undergone great expansion recently.fcp f [Hz] fosc f [Hz] Figure 1.6) is demodulated at the output as a flat. needed for their robustness with respect to amplitude distortions.: 51.304 Slots within: VHF III Band L _ Not fixed. noise specifications are often bound to the free running. e.80 – 39. Therefore the specifications of phase noise in the output of a local oscillator. 256) _ DAB Multiple carrier OFDM subcarriers modulation: DQPSK 193/ 385/ 769 /1537 mode: 1 / 1. DVBS Basic modulation principle Number of subcarriers & frequency spacing Signal bandwidth Gross data rates [Mbps] Frequency ranges Single carrier QPSK modulated DVBT Multiple carrier OFDM subcarriers modulation: QAM16 or QAM64 1705 / 6817 mode: 2k / 8k ∆f= 4. e.g.60 10. In particular for FM signals. or outofloop.5 sketches the pollution of the input RF signal by the spectral dispersion of the local oscillator.10 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops Figure 1. Therefore in the FM context.536MHz 2. DVBC. These specifications also depend on the modulation type and on the selectivity of the input filtering stages.: 7. When talking about SNR. P(f) Programmable & tunable range single sideband phase noise N. …64. DVBT and DAB describe the norms of video and audio transmissions through satellite.g.12kHz 7.
The optimization of the phase deviation in the LO signal is one of our central subjects that is progressively discussed in the following chapters. for a maximum BER of 104 . the implementation losses due to the phase deviations of the LO signal should be kept below 0. tuner constructors ask for the following phase noise performances: for QPSK receivers a maximum total phase deviation under 2°. Indeed.8. has developed into a multimedia standard (DMB). these specifications can be derived from the allocation of implementation losses within the system. showing that phase deviations directly increase the occurrence of errors in bit detection. or for OFDM receivers a single sideband (SSB) phase noise lower than –80dBc/Hz at a frequency offset of 1kHz. frontend plus demodulator. and they strongly depend on the application used for the measurements. either as a total value in degrees or as a maximum SSB level at a certain offset. Nowadays there are also DAB radio and data transmission services. The underlying modulation principles are either phase or phase and amplitude based. the specifications for the LO spectrum become very tight. QPSK constellation In figure 1. Nevertheless. At this point.7 and 1.2 dB [Sinde98a]. requiring simpler TX and RX. the relationship between the implementation loss and the LO phase deviation depend on the characteristics of the demodulator used in the reception. most of these specifications are empirically determined. For example. The first digital broadcasting services available were the single carrier ones. we may expect that the phase accuracy of the carrier becomes relevant. This requirement can be translated into a total phase deviation brought by the synthesized carrier.7 we sketch the influence of phase noise in a QPSK constellation. All these standards have source coding algorithms based on MPEG2. we give a first glance of the issue with figures 1. reflects the sensitivity of the ensemble. For example. The minimum signal to noise ratios vary in accordance to the bandwidth efficiency of the different types of modulation and coding.7 QPSK constellation + phase deviation . and the first consumer DVBT systems are currently being tested. For DVB standards.2 dB [Sinde98a]. initially imagined for audio transmission only. Thus with respect to the sensitivity of the local oscillator to the CNR. showing important advantages for mobile applications when compared to the DVBT. More formally. However. and in QAM 256 it equals 30. Table 11 [Roma97] presents a short overlook of these standards.Chapter 1 / Introduction 11 The DAB system. the SNR of a DVBC channel in QAM 64 is 24. which is considerably higher than the SNR for the QPSK channel.3 dB. to a certain noise spectrum shape. ∆ϕ Figure 1. Therefore the specification for phase deviations.
8. it becomes harder to fulfill this requirement by relying only on the oscillator characteristics. The dotted line spectrum presents a better oscillator performance than the solid line spectrum.8. The lower and upper limits of the integral are determined by the demodulator and channel bandwidth parameters. The large frequency range of the TV applications limits the possibility of integrating the resonant circuit. as occurs in narrow band reception systems. . However as the offset frequency of the noise specifications decreases. for offsets that are comparable to the frequency spacing between subcarriers. most of the controllable LOs are based on a resonant amplifier with an external resonator. In practice this situation appears in two contexts: • very strict noise performances related to modulation types with compact data representation in narrow bandwidths or using multicarriers closely spaced to each other. and it also indicates a SSB phase noise limit for two different frequency offsets(foff1 and foff2). the noise specifications are eventually determined by a maximum threshold for the level of the sidebands.8 Phase Noise requirements Figure 1. Figure 1. The solid line spectrum shows an option where the inloop (PLL related) noise performance is adapted to the CNR specification at both offsets: foff1 and foff2 . The second situation sends us back to the trend for higher integration levels.b shows two carrier spectra with different noise performances. It shows noise specifications that may concern the intrinsic behaviour of the oscillator (out of loop SSB phase noise) or the PLL blocks (in loop SSB phase noise).8. Currently.a Figure 1. This situation is often encountered when using completely integrated oscillators. have to be tried.12 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops The total phase deviation can be calculated integrating the sidebands of the LO spectrum. like mobile telephones.8. Therefore other oscillator structures.6. out of loop SSB phase in loop SSB phase noise …… ∆ϕ2/2 foff1 fosc foffset fmin fmax f [Hz] foff2 Figure 1. as shown in figure 1. but associated to low noise PLL.8 continues the zoom around fosc started in figure 1. like ring or relaxation. Figure 1. • oscillators with a poor intrinsic noise performance.a. In TV broadcasting the OFDM (Orthogonal Frequency Division Multiplexing) standard has the most strict specifications concerning the local carrier spectral purity. used to tune the oscillator frequency.b For multicarrier standards.
in an application context that is not very flexible. As the improvement in coverage+selectivity of the VCOs attains a limit. and learn about the constraints that limit the PLL bandwidth. The absence of external tracking filters can be more easily coped with in satellite receivers. to rely on the PLL characteristics. we need to control the closed loop bandwidth. OFDM). for solutions with integrated oscillators. The three issues above are completely entangled with each other since the optimization of the spectrum suggests bandwidth constraints that have to be guaranteed within the whole gain interval. QAM. A combination of PLL and VCO noise performances are the IC parameters that can be specified to fullfil this specification.8 showed that the noise requirement imposes a compromise between the PLL and the VCO noise performances. These constraints brought an additional interest to a completely integrated oscillator suffering form less external coupling problems. that are closely related to the evolution of an analog carrier generation for RX frontends. Low Phase Deviation: the VCO spectrum has to be optimized for minimum phase deviations in accordance to the new digital modulation standards (DVB standards: QPSK.Chapter 1 / Introduction 13 The drawbacks of these other structures are: their poorer phase noise performance as compared to LC resonators with high quality factors. Coupling interactions between the local oscillator and the RF input signal (now in the same frequency). The advantages appear mostly in the zeroIF configurations. Furthermore the variable parameter adapting these performances is the loop bandwidth. have to be controlled to reduce the signal degeneration by “selfreception” or “selfdemodulation”. a multiloop synthesizer. However this option is quite challenging for the aspects of power consumption and RF isolation. and the impossibility to track the LC matched filters in the input stages of the tuner. or ZIF receivers. In fact. Furthermore. Therefore the integration tendency forces architectural modifications in the tuner. Furthermore. or in other words. In summary the following topics. PLL synthesizers in tuners have to cope with large variations in gain parameters. Nevertheless. The PLL bandwidth is the compensation variable between the performances of these two circuits. The use of an integrated oscillator covering a large tuning range often brings an inherent degradation of the oscillator spectral purity. The AGC dynamics in the RF and BB parts have to replace the previous IF dynamics while preserving the linearity and noise figure properties. with no LC resonator. it is also in satellite applications that we see more and more frontend receptors using direct conversion. increases the robustness to RF interference. multiloop schemes with large PLL bandwidths are required. Direct conversion schemes have new constraints related to the suppression of the IF stage. figure 1. which unfortunately is not independent of other parameters such as loop gain. The integrated oscillators may also be piloted by a second oscillator with an external resonator but working at a different frequency. comparison frequency. So the most natural and inexpensive point for optimization is a careful fitting of the loop filter. the noise quality of the PLLs starts to be an issue. Thus achieving strict phase noise requirements becomes obligatory for the PLL circuitry. where the uniform ii input level enables a feasible compromise between selectivity and linearity requirements. minimum tuning step and DC tuning range. ii Another option to the input filtering is to integrated selectivity stages with structures that are matched to the integrated oscillator. are guiding the issues studied in this work: Noise and stability treatments for large bandwidth and low phase deviation PLL synthesizers in tuner applications. where a totally integrated oscillator. .
locking time. with lower power consumption. but still not locked to it. The phase detector. ranging and instrumentation systems. This last point concerns the generation and sensitivity to interference in the supplies and in the substrate (for integrated blocks that share a common substrate and/or common supplies). determining the bandwidth of the feedback action. command. Frequently there is also a filter before the input of the oscillator. limits of tracking.… . The phase detector is the comparing element between a variable or steady input and the driven oscillator element. In particular for PLL synthesizers. time and frequency control. It is not unusual to classify a PLL with respect to the type of . In the first two. These are phenomena described in the time domain with complicated nonlinear behaviour and modeling. stability. • Frequency Synthesis.14 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops These issues are the conducting line through the sequence of practical and theoretical points tackled in this work. telemetry. the locked mode refers to synthesizers with a constant input. • in synthesizers: noise performances. The first PLL applications were synchronous receptors for coherent demodulation. tracking. specifies many characteristics of the control loop. In the third. Some different investigation issues are seen in association with the fields of application above: • in coherent demodulators: cycle slips. aided acquisition. and the first industrial use on a large scale appears within the TV market (in the 50’s). The acquisition mode refers to the interval during which the loop wanders within its tuning range. and in combination with other analog and digital blocks. This division is also related to the PLL functioning modes: acquisition. frequency and phase properties of the reference signal. whose variations have to be tracked within the tuning range. for the synchronization of horizontal and vertical scans. and. the oscillator is coupled to a fixed reference. In the next sections a short listing of PLL applications precedes a description of the constituting blocks of a PLL synthesizer. • Coherent Demodulation of Digital and Analog Signals. However with respect to their functionality there are mainly three areas: • Carrier Tracking and Synchronization. from which one tries to extract either a carrier or the information that modulates the input signal. Usually described in linear. frequency domain representations. locked or synchronous mode. radar. The application contexts are widespread in areas such as: communications. Finally. 1. higher working frequencies. such as the comparator block in the feedback system. searching to follow the input.4 PLL systems : different application contexts Phase locked loops are feedback systems containing at least a controllable oscillator and a phase detector. • in general: aspects concerning the increasing integration level of the PLL blocks. The tracking mode concerns the function of the PLL when it follows a non constant input. the phase detector receives a variable input. the first patents appeared in the 70’s. in order to transfer to this.
The output. fixes the ratio between fcp and the LO frequency. that is interpolated between the VCO and the phase detector. We would like to enumerate some phase detection principles relating their characteristics of memory or tracking to their respective applications: • Mixers: nonlinear element outputting the sum and difference of the frequencies of the input tones. for set and reset states.9 introduces the basic constituting elements and their nomenclature. • ExclusiveOR: very similar properties with the mixer type with a digital logical implementation. The threestate phase/frequency detector and its tristate implementation are discussed in the following section.Chapter 1 / Introduction 15 the phase detector. The input frequency may be changed by programming different ratios in the reference divider. a memory phase detector would have difficulty to attain lock. Its advantage is related to the possibility of extremely fast lock intervals. or with very high input frequencies. and a more specific description focused on the synthesizer context is made in [Craw94]. thereby choosing the frequency at the input of the phase detector: fcp (comparison frequency). We close this section with the remark that the limited tracking solutions are mostly adapted to low SNR loops. due to the strong deviations it would suffer in the presence of high noise levels. such as in carrier and clock recovery applications. . Therefore the dividing ratios also determine the coverage of the tuning range of the synthesizer. It is the common type used in PLL synthesizers. The tracking zone is unlimited allowing frequency and phase error correction. It has also a limited tracking range due to the ambiguity of the folded elements coming from different harmonics of the input signals. The input is a crystal oscillator with a very selective output. The phase detector is a threestate type. due to its absence of error averaging. and it translates the current information into the tuning voltage input for the VCO. The programmable divider. The tracking range is limited by the sinus periodicity. The loop filter has an impedance magnitude. where the phase detector has to average a carrier or signal information mixed with important noise levels.5 PLL frequency synthesizers constituting blocks and nomenclature From now on we treat exclusively the frequency synthesizer PLL. The tracking zone is expanded with respect to the previous memoryless types. 1. This structure is often reserved to applications with a critical phase noise requirement. related to an external quartz resonator. • Twostate detectors: logical implementation containing two memory nodes. or a flipflop. The block schematic of figure 1. In such conditions. A low pass filter is used to select the difference portion. A general insight of different PLL applications can be found in [Wola91]. • Threestate phase and frequency detectors: two flipflops and an asynchronous reset return. with a current output block. • Samplers: nonlinear element bringing a high frequency component to base band by aliasing with a known input tone. which represents the phase error. may depend on the amplitude of the input signals. named a charge pump. or in other words. There are numerous references discussing the different types of phase detectors.
the resonant circuit is a second order LC structure with a tunable capacitance. such as switches and analogtodigital converters (ADC).16 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops In addition. The series capacitance Cp (padder) is chosen as a compromise between the diode capacitance ratio (Cmax/Cmin) and the quality factor (Q) of the resonant circuit . composed by capacitors and varicaps. before they are fed back to the amplifier input. there are auxiliary service blocks. A minimum Cmax/Cmin is . the ground signal just indicates the DC biasing of the varicap. 1. The active device amplifies the inherent noise sources that are filtered by the resonator. a large resistor or inductor is added for this DC connection. Crystal Oscillator Reference Divider BUS Programming input fcp Biasing & Service Blocks Phase Detector Charge Pump Loop Filter Voltage Controlled Oscillator (VCO) LO output Main Divider Figure 1.10 VCO and tunable resonator In figure 1. Often. that are used to command the functioning of the filtering and amplifying elements within the tuner. Vtune Ct Lp Cp R Cd Figure 1.5.9 PLL frequency synthesizer: block diagram The following sections give further details about some central blocks of the frequency synthesizer. The selectivity is then determined by the resonator.10. Usually.1 VCO The VCO is often a resonant amplifier that contains a tunable band pass filter (BPF) and a gain device.
5.11 shows a block diagram of the ensemble. depending on the limitations of frequency and sensitivity in the input of the main divider. or divideby2 plus swallow cells. Basically we may distinguish two structures: • prescaler structure: composed of divideby2 or swallow cells. As mentioned in section 1. In this manner the swallow cascade may count all the integers within the interval: [ (2n ) . For other PLL applications working with smaller tuning ranges. and the +1 pulse is commanded by the 2nd synchronizing input. 1. (2n+1 – 1) ] . with a fixed capacitor that has a better Q. Several swallow cells may be connected in series. this output is often resynchronized with the input signal in order to copy its phase accuracy. This means that it can recover both phase and frequency differences within the VCO + PLL tunable and programmable range. which separately track the two input phases. This counter works with lower frequencies. which is the most common type of VCO that is encountered in frequency synthesizers for TV tuners. and it is implemented with only divideby2. both reference and main. but it has no minimum count. and m the number of flipflops in the shift counter. are cascaded structures composed of flipflops and combinatory logical ports. In chapter 8. with n defined above. Figure 1. Cp values larger than Cmax tend to be transparent for the capacitance variation. it is not unusual to also find ring and relaxation oscillators.Chapter 1 / Introduction 17 required to cover the whole tuning frequency range. This additional part receives a second data and a synchronizing input that commands the “swallowing” of an extra clock pulse. In low noise synthesizers. whereas the quality factor determines the phase noise performance of oscillator. Therefore the swallow cell can count 2+1. The parallel capacitor Ct assures a minimum capacitance value and it may be added to compensate for the changes in temperature of the IC input impedance. containing two extra latches and some logic ports. to eliminate the time jitter introduced by the divider cells. and it works with the higher frequencies. It may be fully programmable or not. (2n+m+1 – 1) ] . is in fact the transcription of one pulse from the input signal. The prescaler is normally at the input stage. The swallow cells are an extension of divideby2 cells. The reference divider usually has a limited set of dividing ratios. where n is the number of cascaded swallow cells.3 Phase Detector – Charge Pump The phase detector and charge pump comparator is a three state phase/frequency detector. enabled by a programmable counter. The structure described above corresponds to a resonance oscillator.4 the threestate phase detector has 2 memory nodes. The association of these two structures allows for continuous counting between : [ (2n ) . working with a common clock and a common 2nd synchronizing input which is shifted forward between adjacent cells. However smaller values may be needed to improve the quality factor.5. 1. . This improvement is achieved by the serial association of the varicap. It is important to remark that the output of both main and reference dividers.2 Dividers The dividers. that are tuned by a variable biasing current or voltage. • shift counter. or in other words. we discuss another controllable oscillator structure based on cascaded integrator stages. with a poorer Q. The main divider often combines the prescaler with a serial counter.
The phase detector behaviour for phase deviations with a module smaller than 2π. and the slope of the transfer is called Kϕ . 2π]. The sourcing and sinking sources have a programmable current value that is called charge pump current. Functionally this delay iii avoids a change in Kϕ for small input phase differences. In this manner phase differences of up to ± 2π are detected. an asynchronous reset reinitializes the detector. (variable) input from the main divider. The thick central line in figure 1. Thus small phase differences would be masked if the switching on interval was to small to guarantee that the current sources attained their nominal output value. is not capable of distinguishing phase differences with a module above 2π. The delay interval of the assynchronous reset causes the existence of an intermitent 4th state (Off’). the phase detector sensitivity. explaining their functioning through logical state machines. with an average current output that is linearly proportional to the input phase difference. the phase detector will slip one cycle and fall into a new linear zone around +2π or 2π.12. . The state machine of our threestate phase detector is pictured on the right side of figure 1. This phenomena is called deadzone. iii Charge pump circuitry has often slower settingup times than the asynchronous reset in the DFFs. This state is usually transparent for the transfer function. Note that the transfer is periodic over 2π. output average current for input phase deviation. since ideally the sum of both currents equals zero. (reference) input comes from the reference divider.18 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops 1 Ref D CK R Qref programmable input for Icp delay τrst output tuning voltage loop filter impedance R Var CK 1 D Qvar Figure 1. Figure 1. or Icp . during which both current sources are active.11 Phase Detector & Charge Pump block diagram The Ref. and that two shifted linear regions superpose each other in every 2π interval. The rising edges of the input signals command the DFF outputs which in turn command the switches of the sinking and sourcing current sources. when the module of the phase difference exceeds 2π. is represented by a single valued linear function with an input range: [2π.12 represents the transfer. and the Var. When the two outputs are equal to one. Reference [Wola91] makes an interesting representation of different phase detectors. This phase detector with two DFFs.12 represents this function. So.
Chapter 1 / Introduction 19 Kϕ = I cp 2π A rad (1. PLL frequency synthesizers. The frontend of terrestrial and satellite TV receivers was discussed.4 Loop Filter The loop filter is the main subject of chapters 2 and 4. The investigation issues that orient this work were presented and related to the changes in the tuner architecture. However. in order to increase the tuning range. which explains the nomenclature tristate detector. because with the charge pump output a fixed current value charges the filter capacitors with a constant dv/dt and Kϕ . that are bound to the new broadcasting standards (DVB) and to the continuous demand for higher integration levels. 1. The active filters use a high gain amplifier with a large DC output range.5. It is a low pass filter (LPF) using either a passive (with no DC shift) or an active solution. Tristate detectors can also be implemented with a voltage output. In this case the DFF outputs command switches that short circuit the output to nodes with a fixed voltage value (low impedance points such as vcc and gnd). while discussing stability and noise concepts.12 Phase detector & Charge pump: transfer and state machine The Off state is also called highimpedance or tristate.1) Ref Sourcing Qref =1 Qvar =0 Var Iaverage [A] Ref Off Qref=Qvar=0 Var Off ’ Qref=Qvar=1 Icp τrst 4π 2π 0 2π 4π ∆ϕ [rad] Sinking Qref =0 Qvar =1 Var Ref I Figure 1. the advantage of the current output becomes clear with a capacitive loop impedance. identifying the tendencies for innovation. The constituent blocks of the PLL synthesizer were also presented. in a topdown approach. This chapter introduced the context of the present study. .
20 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops .
......... 36 Numerical example of robust filter design........................... 23 Vtune time response for a frequency step...............................................1 Figure 2....................... Requirements in the Time and Frequency Domain ..........................................................2.........................................1..... 38 3rd order filter : Open Loop Bandwidth recentering........................3..............................................2............... Third and Fourth Order Loops......................... SecondOrder Loop ................. 37 3rd order filter: Phase Margin Variation for wol ∈ [ wz1 ..... Phase Model for PLL synthesizers .... Nominal Design................................................................................2....................... Robust design including Gain Variation and 3rd Pole compensation........................................................ 28 2.....3..................... wp2 ] ............................1.................................. 40 Figures: Figure 2......... Summary of steps and numerical example ......................................... PLL Phase Model and Loop Filter calculation 21 2............................... A new notation is introduced to study the 3rd and 4th order loops............................................................................... through qualitative discussions and numerical examples...................................................... 25 Locked VCO output spectrum .............................. 24 2...........................................................2........... Algorithm for the Loop Filter Calculation.... The 2nd order loop is analyzed through standard dynamic parameters ξ and wn ................................... 34 2................Chapter 2 / Phase Model for PLL Synthesizers 21 Contents: 2............... 42 Tables: Table 21 Table 22 Table 23 2nd order filter: Phase Margin Variation for wol ∈ [ wz1 ............................................................. 34 2..........................................2.......................... 31 4th order PLL: Root Locus diagram ........................................................................................4 Figure 2.......9 Linear Phase Model for a PLL ............. 31 Gain Variation X Stability in Bode Plots ... 36 2.2 Figure 2................................. exploiting stability and robustness aspects........................3 Figure 2....... wp2 ]....................... ................................... 29 4th order PLL: Open and Closed Loop Bode Plots ......... 25 3rd order Loop Filter Impedance .......................................................................................................... 26 2.......................... 33 The influence of r21 in the gainbandwidth variation..................7 Figure 2........... 39 2 PLL Phase Model and Loop Filter calculation A linear time invariant (LTI) model for the PLL synthesizer is used to study frequency and time domain characteristics......2.................................................1.............................8 Figure 2..............5 Figure 2.............. 22 2...............6 Figure 2....................1.........................1.......1................... The study is constantly linked to the tuner application context...............
22 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops We start our study of PLL synthesizers presenting a linear phase model that simply and efficiently describes most of the system behaviour around a locked condition. and. phase detector based on flipflops. In fact we seek a simple model where continuous linear time invariant (LTI) tools may be applied. average current to a phase deviation slope. For the moment. In our case its main limitations are the absence of DC range boundaries and the removal of the discrete nature of the digital blocks (phase detector and dividers). The charge pump is replaced by a constant.3 . with the same sensitivity as a pulse width modulation block (PWM). The robustness of the method is exemplified by numerical examples. Using the phase variation as the model parameter amounts to a baseband equivalent representation. In this nomenclature. The baseband phase model in Laplace transform is shown in the block diagram of figure 2.1.1 Phase Model for PLL synthesizers From this chapter on. These characteristics are assessed later with additional modeling in chapter 5 . We introduce a new notation in terms of the spacing between the zeros and poles of the transfer function of the loop filter. This linear average sensitivity is valid for phase differences smaller than 2π. with phase modulating inputs and carrier fc . These models are based on a phase representation of a PLL. Such a representation is equivalent to the small signal AC models used for circuit simulation. in terms of its natural resonance frequency (wn) and damping factor (ξ). The new notation is used to develop an algorithm to calculate loop filters that respond to stability constraints in a large range of gain variation. a phase variation with respect to these. These signals carry phase information that is related to the time interval (T) between similar edges.5. the VCO block is not included in the PLL. with: [K o ] = rad ⋅ Hz Ko = d w osc d f osc = 2π ⋅ = 2π ⋅ K vco d V tune d V tune V K [K vco ] = Hz V and Kϕ defined in equation (1. A topdown approach is proposed starting with behavioural models that give an insight into frequency and time domain characteristics. we consider that the PLL bandwidth is small enough compared to the phase detector comparison frequency. 2. as seen in section 1.1) . The phase representation concerns all logic signals that are inputs of edge triggered blocks. We abbreviate it to PLL. and tristate charge pump. and we suppose that this AC description is valid within the whole DC range that may be swept. with the following constituent blocks: programmable dividers. The linear description is related to specifications in the time and frequency domain by using a standard notation for a 2nd order lowpass filter. We may also define an average or initial time interval (Tc) and frequency (fc = 1/ Tc ). we focus on the phase locked loops for frequency synthesis. The description is enlarged to treat systems of a higher order.
is valid for phase deviations considerably smaller than π. The linear approximation that allows the calculation of FM components by their peak phase deviation. . H (s) = K ϕ div Icp ⋅ Kvco F ( s ) F (s) 1 = K ϕ ⋅ F (s) ⋅ o ⋅ = ⋅ =α ⋅ s N N s s ϕ ref (2. We define H(s) and B(s). i More detailed discussions of the narrow band FM context are made in sections 3. F(s).1) with α.1 Linear Phase Model for a PLL The phase detector is replaced by an adder that continuously evaluates the phase difference between the reference input and the divider output. The loop filter impedance. This phase difference is transformed in an average charge pump current. represented by the block with a sensitivity Kϕ. Our applications use a second order LC resonator that is equivalent to an integrator in a base band representation.2) It is convenient to split the filter impedance into two polynomials representing its zeros and poles. converts this current in Vtune and the oscillator is depicted by its frequency slope associated with an integrator.2.1 and 6. as the open and closed loop transfers respectively.Chapter 2 / Phase Model for PLL Synthesizers 23 Phase Detector Charge Pump Loop Filter Iaver [A] VCO ϕref [rad] +  ϕe [rad] Kϕ F(s) Vtune [V] Ko/s ϕosc [rad] for open loop ϕdiv [rad] 1/ N Figure 2. Therefore ϕosc (VCO output phase) is a valid approximation of the ratio: modulated sideband amplitude divided by carrier amplitude. The VCO is a frequency modulator with a voltage input and frequency selectivity determined by its resonant circuit. the open loop gain: B(s) = α = Icp ⋅ Kvco N ϕ osc α ⋅ F (s) H ( s) =N⋅ =N⋅ ϕ ref 1 + H (s) s + α ⋅ F (s) (2. i for frequency modulating components with Am/fm << π where Am and fm indicate the amplitude and frequency of the modulating tone.
overshoot. settling time for error within an acceptable x% variation around vfinal .2) corresponds to a frequency change. comparison frequency suppression with respect to Pcarrier. The specifications indicated in the time and frequency envelopes are the guiding issues discussed in the following sections. The following parameters are indicated in the time response: • • • • vinitial / vfinal : Mp : trise : tsettling : initial and final values corresponding to the step input. need to be translated into transfer function characteristics to guide the design of the control function (loop filter). The time response (figure 2. normalized difference between maximum value and final value. closed loop bandwidth and peaking. step response overshoot. 2. Let us choose two measurable signals for these envelopes such as Vtune and the oscillator spectrum.24 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops H (s) = F (s) = N F (s) D F (s) ⇒ B (s) = N ⋅ α ⋅ N F (s) s ⋅ D F (s) α ⋅ N F (s) s ⋅ D F (s) + α ⋅ N F (s) Then we may see that B(s) have the same zeros as H(s).3. or –3dB point with respect to the close in spectrum. A summary of these specifications can be represented by time and frequency response envelopes. spurious amplitude. closed loop bandwidth. and. their poles are equal to H(s) for α=0 (no feedback gain).1. like a step input for fref . the frequency change is made by reprogramming the main divider ratio. rise time with respect to a “y” fraction of the transition step. spurious rejection.1 Requirements in the Time and Frequency Domain The PLL system performances: locking time. stability.3. as shown in figures 2. oscillator frequency. maximum peaking: maximum sideband value with respect to the closein spectrum.3) represents the output spectrum of a VCO in lock mode. The frequency response (figure 2. The parameters indicating the frequency domain specifications are: • • • • • • Pcarrier: AS : (PcarrierAS): fo : bwcl : carrier output power. and gradually change as α increases. Most often however.1.2 and 2. or a ramp input for ϕref . . N. This idea is very clearly represented by the rootlocus diagram discussed in 2.
vfinal vfinal (y).2 Vtune time response for a frequency step Power Spectrum Density (PSD) [dB] Pcarrier PcarrierAS maximum peaking 3dB fosc fosc+ fcp fosc+ bwcl f (Hz) Figure 2. All the following chapters use the filter notation and design tools developed in the present chapter. Later.3 Locked VCO output spectrum We start with the time requirements that may be directly related to a standard 2nd order characteristic equation. taking into account the inherent noise performance of the VCO. in chapter 3. we introduce a convenient notation for the 3rd and 4th order systems.Chapter 2 / Phase Model for PLL Synthesizers 25 Vtune(t) = fo(t)/Kvco [V] (1+Mp). The frequency envelope is a combination of the PLL and the VCO performances. Later. and a loop filter design algorithm to guarantee a robust stable functioning.(vfinalvinitial) + vinitial vinitial trise tsettling t (s) Figure 2. . In this chapter we focus on the PLL characteristics. the complete frequency envelope is discussed.
undamped natural frequency.3) ii Otherwise the error response stabilizes around ϕefinal . having a final phase error that tends to zero. In our phase model the zero final error for a phase ramp input implies an H(s) with two pure integrators. with T=R. with wn . F(s). and ξ. B(s) = N ⋅ α ⋅ N F (s) N ⋅ (1 + s ⋅ T ) N (s) = B = C s ⋅ DF ( s ) + α ⋅ N F ( s) s 2 ⋅ + s ⋅ T + 1 DB ( s) α .1. it is useful to guarantee that ii a frequency step is perfectly followed. the charge pump is still injecting an average current (Kϕ . frequency controlled by the loop gain.2. which implies that even in lock.C s/rad. A feedback system with two integrators and no zero would be an oscillator. Therefore the simplest form of F(s) is: Iin F (s) = 1 + s ⋅T s ⋅C . One integrator is intrinsic to the VCO phase representation. and the other must be included in the loop filter. The open and closed transfer functions for the resulting 2nd order PLL are: H (s) = α ⋅ (1 + s ⋅ T ) α ⋅ N F ( s ) = s2 ⋅ C DF ( s) . which may increase significantly the reference spurious. so we must also include a zero in F(s) for stability reasons. As a matter of fact. an allpass filter (simple resistor) combined with the oscillator pole would already present a lowpass filter behaviour for the overall loop.26 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops 2.2 SecondOrder Loop We start searching for the simplest filter that would present a time response with the form indicated in figure 2. Comparing DB(s) to a standard 2nd order equation. . damping factor. R Vout C which corresponds to the impedance of a RC series branch. results in: B(s) = N ⋅ (1 + s ⋅ T ) C s2 ⋅ + s ⋅T + 1 α ← → N ⋅ (1 + s ⋅ T ) s w n 2 ⋅ξ + s ⋅ w n 2 C= +1 L R= α 2 wn 2 ⋅ξ 2 ⋅ ξ ⋅ wn = α α ⋅C (2. ϕefinal ). However for a PLL with a phase detectorcharge pump comparator.
2 } : roots of DB(s) : damped natural frequency : exponential envelope factor σ = ξ ⋅ w n = Re {s1. Typically ξ is kept above 0. and through the following chapters we tackle other parameters. Next.7. For instance the unitary step response of 1/DB(s) is: wn 1 = 2 s ⋅ DB ( s) s ⋅ s + 2ξ wn s + wn 2 2 ( ) σ ← → 1 − e −σ ⋅t ⋅ cos (wd ⋅ t ) + ⋅ sin (wd ⋅ t ) wd s1. The 1st order filter. and a resonant peak inversely proportional to ξ. depends on many parameters. 2 } where overshoot and settling time can be derived as functions of wn and ξ.Ko. or Vtune(t). or ξ and wn . Some aspects of the output spectrum may be obtained from the frequency response of the closed loop. Therefore the time response of the 2nd order loop is simply fitted in its envelope requirement through a convenient choice of σ and wd. We may also recognize that y(t) represents the derivative of ϕosc(t) for the ramp input. with a 20dB/dec attenuation for w>>wn . The choice of the bandwidth. and it indicates the system is approaching instability. wd and σ. wn representation is its direct relation to frequency and time responses. has a B(jw) close to a low pass filter (LPF).Chapter 2 / Phase Model for PLL Synthesizers 27 The advantage of this ξ. which is the oscillator instantaneous frequency: 2π.3) using ξ. Using the same variables. since it increases noise presence at the output. such as: . wn and the open loop gain. The oscillator output spectrum results from a combination of the PLL and VCO frequency responses. 2 = −ξ ⋅ w n ± j ⋅ w n ⋅ 1 − ξ 2 = −σ ± j ⋅ w d w d = w n ⋅ 1 − ξ 2 = Im {s1. with a single integratorzero. the values of the filter components are evaluated with expressions (2. Let us now consider the frequency domain envelope. We have already seen the rise time and settling time in Vtune time response. represented at the input of the phase detector. B(jw). Hence the choices of wn and ξ. Generally the resonant peak should be kept to its minimum. wn . we find a similar step response for B(s): wn + 2ξ wn s B (s ) =N⋅ 2 s s ⋅ s 2 + 2ξ wn s + w n 2 ( ) ← → y (t ) = N ⋅ 1 − e −σ ⋅t σ ⋅ cos (wd t ) − ⋅ sin (wd t ) wd (2.4) The integration property of the Laplace transform can be applied to equation (2. The PLL response is given by B(jw). α. and the input is the overall phase disturbances due to the PLL blocks.fosc(t). are a compromise between the time and frequency domain specifications.4) to derive the ramp response of B(s).
and the resulting open and closed loop frequency responses. Since we treat fairly simple systems with no zeros or poles in the right hand plane (on a Splane). The pole at the origin is preserved to fulfill the steady error condition discussed in 2. the closed loop transfers are not so easily perceived as the second order B(s). In addition the closed loop transfer B(s) for a 2nd order loop leaves the phase noise contribution of the PLL visible within a 20dB/dec slope. 2. in order to achieve the necessary outofloop rejection. and microphony and other interference robustness. is not directly factorable in 2nd or 1st order polynomials. from the VCO output spectrum to a broader context including requirements from the application environment and from the demodulator block. This means that a poor noise performance of the PLL would be visible even for frequencies above the closed loop bandwidth. most tuner synthesizers use 3rd order loop filters.3 Third and Fourth Order Loops Before we may examine the stability conditions of a 3rd or 4th order PLL. requirement of spurious suppression. the stability may be unambiguously analyzed by the open loop frequency response parameters: phase margin (PhM) and gain margin (GM). we need to introduce the corresponding loop filter impedance. unchanging open loop gain (α) value.2. before discussing further aspects of the frequency envelope requirements we introduce some stability concerns in the 3rd and 4th order loops. As mentioned in the previous section. As we evolve towards higher order loops. Thus. At the moment we can state a 1st rule of thumb. its attenuation for high frequency (w>>wn) is often not enough to suppress the reference spurious to a satisfactory level. These filters are implemented with additional resistors and capacitors. The following notation is adopted for the zeros and poles. VCO freerunning noise performance. resulting in a 4th order PLL. Nevertheless. DB(s). introducing one or two extra poles at frequencies higher than the zero frequency. and elsewhere it is convergent. most synthesizer applications use a 2nd or 3rd order loop filter.1. Indeed. In these terms the 2nd order PLL is very convenient since it only imposes a minimum gain value related to a minimum ξ. maximum phase change for small frequency steps. These questions belongs to quite different contexts. which is equal to the slope of the VCO intrinsic noise. because their characteristic function. .1. frequencies and time constants: f z1 = w 1 = z1 2π ⋅ Tz1 2π : with fz1 and Tz1 . However we need to keep in mind that α can vary a lot in certain synthesizer applications and this variation needs to be accommodated by the filter dimensioning. common to synthesizer applications that use wn in the range: wcp wcp ≤ wn ≤ 30 10 So far we have discussed ξ and wn choices for a unique.28 • PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops comparison frequency (fcp). zero frequency [Hz] and time constant [s/rad].
4 3rd order Loop Filter Impedance The filter impedances. . By convention our 2nd order filter has a finite fp2. Zs = VM 1 + s ⋅ R 1 ⋅ (C 1 + C 2 ) = I in s ⋅ C 1 ⋅ (1 + s ⋅ R 1 ⋅ C 2 ) .5) A second order filter is obtained if either fp2 or fp3 tend to infinity. remembering that the 1st pole is a pure integrator with fp1= 0 Hz. V out 1 1 = = VM 1 + s ⋅ R3 ⋅ C 3 s ⋅ C3 ⋅ Z 3 Zp and Zs are composed of an integrator plus a leadlag. pair. which simplifies ZF(s) in both cases to: iii The complete 3rd order. The single pole low pass filter (LPF). zeropole. and Z3 >> Zs are valid. The two RC filter configurations below have approximately this transfer function as impedance: Z3 Iin Zp R1 C1 C2 VM C3 Vout R1 C2 R3 Iin C1 Zs VM C3 Vout Z3 R3 Figure 2. Zp = VM = I in 1 + s ⋅ R1 ⋅ C1 C ⋅C s ⋅ (C 1 + C 2 ) ⋅ 1 + s ⋅ R1 ⋅ 1 2 (C1 + C 2 ) .1. transfer is discussed in section 4. These approximations are made to keep a transfer with real factorable poles. which greatly iii simplify the filter design. supposing that the approximations: Z3 >> Zp . Its accuracy holds for fp3 >> fp2 . nonfactorable. is often called a postfilter.Chapter 2 / Phase Model for PLL Synthesizers 29 f p2 = w 1 = p2 2π ⋅ Tp 2 2π and f P3 = w 1 = p3 2π ⋅ Tp 3 2π for the 2nd and 3rd poles. Zs and Zp . associated with Z3 . are calculated as independent 2nd order terms. The resulting 3rd order filter is: F (s) = k ⋅ (1 + s ⋅ Tz1 ) s ⋅ (1 + s ⋅ T p 2 ) ⋅ (1 + s ⋅ T p 3 ) (2. A second approximation is made considering C1 >> C2 ⇒ C1 + C2 ≈ C1 . and a Tp3 = 0. and.
and.C3 . GM. 2. one pole that tends to the zero (being “cancelled”).C2 . analogous to a standard 2nd order iv characteristic equation. is justifiable by the fact that the zero influence in pulling up the phase from its initial value (for w << wz) of 180° . in the form: B(s) ≈ N 2 (1 + s ⋅ Tp3 ) ⋅ s 2 + 2 ⋅ ξ ⋅ s + 1 w wn n = B3 LPF ( s ) (2.5 and 2.7) Root locus and Bode diagram sketches showing PhM. indicated as fcl3dB in figure 2.360° / n . w3dB .6) B(s) = N ⋅ α ⋅ (1 + s ⋅ Tz1 ) s ⋅ C1 ⋅ (1 + s ⋅ T p 2 ) ⋅ (1 + s ⋅ T p 3 ) + α ⋅ (1 + s ⋅ T z1 ) 2 (2. but since Tz1 / Tp2 = C1 / C2 ⇒ C1 >> C2 the open and closed loop transfer functions of the PLL with this 3rd order filter become: H (s) = α ⋅ (1 + s ⋅ T z1 ) s ⋅ C1 ⋅ (1 + s ⋅ T p 2 ) ⋅ (1 + s ⋅ T p 3 ) 2 (2. and the second order function in the ξ wn form represents the two other roots. The boundary imposes a minimum ξ value that may be represented in the rootlocus diagram. This resemblance is confirmed by the rootlocus that has for adequately high open loop gains.30 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops Z F ( s) = Vout 1 + s ⋅ R1 ⋅ C1 = I in s ⋅ C1 ⋅ (1 + s ⋅ R1 ⋅ C2 ) ⋅ (1 + s ⋅ R3 ⋅ C3 ) ZF(s) corresponds to F(s) for: Tz1 =R1 . fp3 >> fp2 >> fz1 . These last two may be complex or real.C1 . K = 1/C1 . Mr. is only visible if: fz1 << fp2 ⇒ Tz1 >> Tp2 . and the closed loop root asymptotes are plotted in figures 2. The 3rd order LPF approximation for B(s) would have a transfer function. 1.8) where Tp3 is the postfilter equivalent pole. Tp2 =R1 . Tp3 =R3 . The spacing between fz1 and fp2 . the LPF approximation is also used to evaluate the 3 dB closed loop bandwidth. depending on the value of α. iv Later. expressed in terms of ξ and wn. in 3. α. and k = 0.6. with n=3 . and three others that tend to the asymptotes: 180° + k.1 .5. This simplified LPF form suggests a 1st stability boundary. .b. B3LPF(s) .4. The closed loop magnitude Bode plot suggests a PLL phase transfer resembling a 3rd order LPF.
5. 2.5.6 .Chapter 2 / Phase Model for PLL Synthesizers 31 Open Loop : H(s) B(jw) H(jw) [ dB ] Closed Loop : B(s) 40dB/dec 20dB/dec [ dB ] N N3dB 40dB/dec fp2 fz1 fp3 log( f ) [Hz] fz1 fcl3dB fp2 fp3 log( f ) [Hz] 60dB/dec 60dB/dec ∠H(jw) [°] fp2 fz1 fp3 log( f ) [Hz] ∠B(jw) [°] fz1 fcl3dB fp2 fp3 log( f ) [Hz] 90° 180° PhMmax 270° fig.b Figure 2.5 4th order PLL: Open and Closed Loop Bode Plots Root Locus Im{s} ξ=1/√2 fz1 fp3 fp2 Re{s} 45° 4th order PLL: Root Locus diagram Figure 2.a 90° 180° 270° fig. 2.
corresponding to the maximum phase margin for a 2nd order filter (or a 3rd order loop). the dotted axes indicate a boundary of ξ = 1 2 . and the other two tend to asymptotes parallel to the imaginary axis.7 shows open and closed loop Bode plots with three different gain values: • • a centered value. αn . wpeak: frequency corresponding to the peak value. This same reasoning can be applied to the open loop Bode diagram. as indicated in figure 2. The gain variation chosen is proportional to the leadlag. One is still directed towards the zero. For the moment we observe some new parameters introduced in figure 2. α. zeropole spacing. . these two branches will finally cross the imaginary axis indicating an unstable behaviour. The curves with solid lines correspond to the 4th loop transfer with the 3 α values. there are only three root branches.5. in trying to keep the phase margin above a suitable value.7: ½ in the open loop diagrams: • wol: open loop zero crossing frequency or open loop bandwidth.32 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops In figure 2. αn. A classical security limit for a system phase margin is about: PhM ≥ 30° . has a minimum and a maximum limit value to ensure that the complex roots have a convenient damping. geometrically equidistant to αn . B(jw) value. The filter calculation and the maximum supported gain variation are discussed in the following sections. The curves plotted with dotted lines indicate the 3rd order loop transfer for the centered gain value. This variation also shows a limitation for a minimum and a maximum value of α. ½ • • • in the closed loop diagrams: peak: resonant overshoot with respect to the closein.b. without moving the phase plot. α max α n ⋅ r21 = = r21 α min α n r21 and r21 is defined as r21 = f p2 f z1 . w3dB: 3dB closed loop bandwidth. For a 2nd order filter. but less and less damped as the equivalent ξ for the complex roots tends to zero. • woln: central wol corresponding to the centered gain αn. and two other gain values. where a changing α value corresponds to shift the magnitude curve vertically. since. We observe that the gain value. ξ. Figure 2.6. Therefore the loop does not become unstable for increasing α values. low frequency. In fact for increasing α values.
Furthermore the centered gain value for the 3rd order loop.7.and the relation between the zeropole spacing and the maximum supportable gain variation. and that its variation represents the system functioning range. Kvco)/ N. 2. 2. . αmax] and to meet the frequency and time specifications. is not really ideal for the 4th order loop.a fig.a filter calculation algorithm for the 2nd order filter.a centering compensation for the 3rd order filter. αn . In this example we observe that a gain variation of r21 implies quite significant variations of bandwidth and PhM. . Thus in the next sections we define successively: .7 Gain Variation X Stability in Bode Plots Remembering that α = (Icp . we must adapt F(s) parameters to fit α ∈ [αmin .b Figure 2.7.Chapter 2 / Phase Model for PLL Synthesizers 33 fig. .
corresponding to the minimum Kvco and maximum N values and viceversa for the maximum α value. or at the highend of the tuning range. especially if the output spectrum needs to be optimized for noise performance. and as far as possible cope with all the gain variation range. and intuitively we may say that if fp3 is distant enough not to have much influence on H(jwol). and the zero and poles frequencies.2. Let us define r31 and recall r21 : r21 = f p2 f z1 . R. N variation is directly proportional to the frequency variation inside the tuning range. Furthermore the minimum α value is found at the high end of the VCO frequency spectrum. the sensitivity is proportional to the varicap capacitance variation dC/dVbias. i. PhM f f f = ∠ H ( jw ol ) − ( − 180 °) = arctg ol − arctg ol − arctg ol f f f z1 p2 p3 w = w ol (2. for high values of Vtune.34 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops 2. it is not rare to find α variations (αmax/αmin) higher than 100.9) The maximum PhM point is somewhere between fz1 and fp2 . Kvco variations are connected to the oscillator tank circuit sensitivity. However for stability reasons and user flexibility. the filter design should be centered. with a fixed Icp value. . Typically this capacitance variation decreases for high Vbias values.e. In varicap based tank circuits. plus eventually a multiplication factor to compensate changes in the reference divider ratio. leads to a simpler approach. to ensure the best application robustness. pole frequencies divided by zero frequency. Taking the phase margin aspect as a departure point and expressing it with respect to the ratios. and express phase margin as a function of fol (wol /2π ). In satellite applications they are typically to the order of 50. Taking into account these two variations and one fixed Icp value results in the maximum α range demanded by the application. In terrestrial applications. In the case of such large variations it is wise to use different Icp values to reduce the variation. 2.2 Algorithm for the Loop Filter Calculation TV tuner applications very often work with quite large variations in the parameters: Kvco and N.1 Nominal Design Direct solving of the 4th order B(s) denominator with respect to fol or w3dB would be onerous and not very enlightening with respect to the stability aspect or for an intuitive and quick filter calculation method. it should be equidistant to both fz1 and fp2 . r31 = f p3 f z1 .
9) and (2.12) The expressions above allow for the calculation of the filter components. R1 = 1 Tz1 w = = oln C1 wz1 ⋅ C1 α n r21 r31 ⋅ woln .10) The maximum phase margin point should be adjusted to correspond to the geometrical average of the open loop gain range. is made with respect to a 2nd order filter. The influence of the postfilter is taken into account in expressions (2. makes: PhM ( w ol ) = 2 ⋅ arctg ( r r21 − 90 ° + arctg 21 r31 ) (2.Chapter 2 / Phase Model for PLL Synthesizers 35 This idea can be confirmed solving: with the approximation which result in: d df [PhM ( f )]= 0 wol << wp3 PhM ( w) ≈ arctg ( w ⋅ T z1 ) − arctg ( w ⋅ T p 2 ) and max{PhM} for f = f z1 ⋅ f p 2 = f z1 ⋅ r21 = f p2 r21 . The positioning of fz1 and fp2 . Tp 3 = R3 ⋅ C3 = . So that gain variations towards minimum and maximum values imply phase margin variations around the maximum point.11) C1 = ⇒ C2 = α n ⋅ r21 αn = 2 wz1 ⋅ woln woln Tp 2 R1 = Tp 2 Tz1 ⋅ C1 = C1 r21 . . Choosing this maximum PhM frequency as fol . α max ] ∧ α n = α min ⋅ α max H ( jwoln ) α =α n = 1 + r21 αn ⋅ 2 woln ⋅ C1 1 + 1 r21 ⋅ 1 + r21 / (r31 )2 supposing → r21 >>1 r31 >>1 αn ⋅ r21 = 1 2 woln ⋅ C1 (2. They are valid for both 2nd and 3rd order filters. (2.10) for the total PhM. following a maximum phase margin approach. but it was not considered in the choice of the center or nominal gain value αn . with respect to the PhM loss due to the postfilter. is discussed in the following section. . H ( jw) w = woln α =α n =1 α ∈[α min . the leadlag controller. A compensation for this gain centering.
5 lim f (r21 ) = 1 with: . Thus. wol variation with respect to α may be expressed as: wol α = wo ln α n 0. r21. we need to translate the gain variation in an open loop bandwidth variation. i. Figure 2. and.13) lim f (r21 ) = 0. r21 → 0 r21 → ∞ . for large r21 (approximately r21 ≥ 25). H(jw) [ dB ] sqrt(r21) >> 1 α1 < α2 < α3 αi ↔ wi fp2 fz1 fp3 log (f ) [Hz] H(jw) [ dB ] sqrt(r21) → 1 fp2 fz1 fp3 log (f ) [Hz] w1 w2 w3 w1 w2 w3 Figure 2.8 gives an intuitive approach to the relation gainbandwidth with respect to the filter design parameter..9) shows that for fixed filter parameters.8 The influence of r21 in the gainbandwidth variation In other words. The open loop slope stays practically unchanged around the wol frequency. for large and small r21 values: • • for small r21 (approximately r21 < 10). with a 40 dB/dec value. the slope around wol decreases to 20 dB/dec and wol changes are proportional to α.36 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops 2. fol . in order to associate gain values with PhM values. and wol changes are proportional to sqrt(α). The sketches show two extreme situations.e. the phase margin depends uniquely on the open loop zero cross frequency. the influence of r21 in the variation of wol with respect to α.2.2 Robust design including Gain Variation and 3rd Pole compensation We wish to investigate the maximum gain variation that we are able to accommodate within convenient PhM values.5 < f (r21 ) < 1 f ( r21 ) (2. In fact expression (2.
29 41.04 64.79 67.08 47. We consider the error acceptable. (with no postfilter we find the same PhM for both points).14) ).833 Table 21 2nd order filter: Phase Margin Variation for wol ∈ [ wz1 . We start evaluating the gain range corresponding to wol variations between wz1 and wp2 . Using polynomial interpolation in numerical examples. and expression (2.19 42. for the 2nd order filter. we find a simpler form for f(r21). the bandwidth variation is a function of a unique variable: r21 .14) The interpolation error is evaluated for PhM variations with respect to the central PhM value.w = wz1 .760 0. (αn/ αmin)2 αn =>wol=woln αmin =>wol=wz1 max{PhM} [°] PhM [°] wol=wz1 or wol=wp2 w/o post filter r21 10 15 20 25 with wol=woln w/o postfilter f (r21) 54. It follows that: v PhM values are calculated using expression (2.795 0.14 42.Chapter 2 / Phase Model for PLL Synthesizers 37 A formal solution for f(r21) would require solving 3rd and 4th order polynomial equations. the bandwidth ratio is estimated with a maximum 5% error. For gain values implying a phase margin variation ≤ 20°. wp2 ] The last column gives the gain range values corresponding to the open loop bandwidth variation: wol = wz1 ⇔ α min wol = w p 2 ⇔ α max α max α min α w = n = ol α w min oln 2 1 f ( r21 ) The ratio αn / αmin is evaluated according to the f (r21) approximation ( equation (2. In fact for this α variation corresponding to wol=wz1 or wol=wp2. v Table 2. The PhM values are calculated at: .18 39. or w = wp2 .71 20. .90 61.10) . .59 0.14) is used to evaluate the following issues concerning the maximum supported gain variation and the filter recentering with respect to the postfilter.38 39. f ( r21 ) ≅ 1 1+ r21 (2.71 30.817 0. which is quite accurate around the central point. wol/woln = 1.w = woln .1 shows some PhM values for r21 values commonly found in tuner applications.
wp2 ] Phase margin differences for zero cross frequencies at wz1 and wp2 .with postfilter. combining the results of table 21 and expressions (2.r21) .14 ♣ 1. shows that normalized gain variations of (2.67 2.22 ♣ 20.04 61.00 (♣) : unacceptably low PhM values.38 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops w p2 α max = w α min z1 1 f ( r21 ) = r21 1+ 1 r21 (2.80 41.20 2. So.24 55. the effect of wp3 is already visible in the PhM of the centered bandwidth. A certain minimum r31/r21 ratio is necessary to keep a PhM ≥ 30° for a α range with αmax / αmin ≈ (2.15). We are implying that r21 is chosen in relation to: the maximum PhM required.we may use a linear estimation of equation (2.75 40.67 38. show the influence of wp3 in the PhM for gain values α > αn .63 2.16) The r21 range between 4 and 25 covers quite well the values used in our tuner applications. Table 22 brings some PhM values for sets of r21 and r31 parameters. and. We consider that the minimum acceptable PhM value is 30°. the gain variation ratio.38 52.04 67. 31 ] ≈ K ⋅ r21 LL K = 1 . . max {PhM} [°] {PhM} [°] with wol=woln w/ postfilter PhM [°] with wol=wz1 w/ post filter PhM [°] with wol=wp2 w/ post filter r21 r31 with wol=woln w/o postfilter r31 / r21 15 15 25 25 25 40 30 50 61.67 1. We continue our analysis including the postfilter for the 3rd order loop filter. as shown in figure 2. with a normalized error smaller than 5%: K =2 r 1+ 21 1 r21 .7 and table 22 .51 57.15) For restricted domains of r21 . The PhM values are calculated at: . 95 (2. 25 ] . Table 22 3rd order filter: Phase Margin Variation for wol ∈ [ wz1 .w = woln with and without postfilter.38 67.90 ♣ 16. Actually.15) and (2. . r21 ∈ [12 . and w = wp2 .92 61.56 10.90 39. with postfilter (different PhM values for the 2 points).w = wz1 . woln. r21 ∈ [4 .r21) can be accommodated within suitable PhM values.16).
20 2. Using a 1st order limited development for equation (2. rpf (postfilter factor).6 . is also equal to r21 .10).18) 1 α n = α npf ⋅ r pf 1 = α npf ⋅ r pf KK α n ≥ α npf (2.34 62. [(r31 / r21)>1. and quantified in 4.18 20.6 . .83 PhM [°] for αmax wol=wolnpf . but it cannot be used for vi smaller ratios. vi As a matter of fact for small (r31 / r21) ratios we also loose the accuracy of the filter transfer function. equal to (2.67 1.PhM(wp2) 15 15 25 25 25 40 30 50 0.84 22. it is not possible to accommodate the normalized gain variation with PhM ≥ 30° .1.03 1. and the related gain value αnpf . The estimated centered bandwidth is named wolnpf . used in table 23 .6 ].408 0.17) KK woln ≥ wolnpf (2. Hence.81 (♣) : recentering approach fails.67 2. as far as the minimum ratio.r21) .5 28. The bandwidth ratio (wolmax /wolmin).Chapter 2 / Phase Model for PLL Synthesizers 39 So.5 30. so. is respected. r − r21 r pf = 31 r31 w oln = w olnpf r pf 1 f (r ) 21 1+ 1 r21 2 KK 0 ≤ r pf ≤ 1 (2.19) Table 23 shows numerical examples of the postfilter recentering.49 32. we observe that recentered 3 rd order filters can also cope with the normalized gain variation.2. The limit (r31 / r21) ratio imposes a condition for the postfilter placement.89 30. Table 23 3rd order filter : Open Loop Bandwidth recentering The recentering approximation is quite effective for (r31 / r21 ) > 1.707 52. since the accuracy is quickly degraded.92 ♣ 0. ∆ (PhM) PhM [°] PhM [°] for αmin wol=wolnpf /(r21)0.(r21)0.1.44 3.5 for αnpf wol = wolnpf r31/r21 PhM(wz1) .00 55.r21) . The same values for r21 and r31 used in table 22 are recalculated after repositioning the central open bandwidth around wolnpf .11 2. the corresponding gain variation is approximately (2.791 0.45 34. we wish to find a correction factor to recenter the open loop bandwidth around the maximum PhM for a given set of r21 and r31 parameters.41 32. enables us to find a simple polynomial correction factor.00 r21 r31 (rpf) 0. as discussed in section 2.1.632 0. In practice for (r31 / r21)< 1.92 56.34 43.
αmax / αmin ≥ 100 . R3 and C3 values may be directly calculated. There is a limitation concerning the R3 /R1 ratio. r31 ≥ 1 . which appears as a parallel. spurious attenuation and adequacy to the noise performance of the VCO. : higher part of frequency range. (d) Recenter αn with respect to (r31/ r21) ratio.40 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops In fact. look for possible compensations choosing a specific Icp value for extreme cases.1. that is discussed further in section 4. In some applications we can also see an influence of the C3 value with respect to the resonant tank circuit of the oscillator. placing the postfilter pole is a compromise between PhM loss and spurious suppression requirement. Once the postfilter pole position is chosen. we should choose a large R3 and a small C3. there is an additional factor imposing a compromise. we should keep a certain minimum C3 to assure the necessary RF attenuation. for gain and cross frequency variation around αnpf and wolnpf . 2. In these cases C3 . r21 ≥ 1 α max ⋅ 2 α min . Calculate the geometrical average (αn ) and the variation ratio.2. If gain variations are too large. (b) Choose parameters r21 and r31 taking into account PhM requirements and α ratio. but a minimum PhM. For the moment let us keep in mind a practical boundary suggesting : R3 ≥ R1 . C3 and a series resistor connecting the loop filter to the tank resonator. for a given Tp3.3 Summary of steps and numerical example The points discussed up to now suggest sequential steps for the loop filter calculation following the maximum phase margin approach. in a given α range.6 r21 (c) Choose wolnpf with respect to the following parameters: switching time. The latter would ask to place it as close as possible to fp2 . should be chosen to be as small as possible. whose function is to block the VCO signal leaking towards Vtune . α m ax = α = Icp ⋅ K vco N div α m in = Icp m ax ⋅ K vco m ax N div m in Icp m in ⋅ K vco m in N div m ax : usually lower part of frequency range. has to be preserved. corresponding to the functioning conditions. So far so good. since these two practical boundaries tend to the same direction. form an LPF. and the recentering correction: (a) Evaluate the system open loop gain range. Thus. However as usual. parasitic capacitance. For α npf = α max ⋅ α min and r − r21 r pf = 31 r31 . αmax / αmin .
In chapter 3 we discuss a significant parameter. The open loop bandwidth choice is the remaining compromise that is not completely discussed. . a steep phase change corresponds to a bigger overshoot. Analogous to the 2nd order example in annex IIA. concerning the total phase noise power in the carrier.7. In figure 2.1. frequency corresponding to the maximum value of closed loop magnitude. wp2 ( x ) . and.12) . So after choosing the central open loop bandwidth . αn and expressions (2.9 the graphs use the same r21 and r31 values as in figure 2. ∆phase [B( jw)] ∆w with ∆w an octave frequency delta around wpeak . wolnpf ( * ) .2. woln in this case (item (c) ). it depends on many parameters including circuit and system requirements. the phase jitter. wpeak: w3dB: peak: dPhB(jw)/Foct : woln ( ). Finally we present a numerical example to illustrate the recentering plus the normalized gain variation. As we mentioned in section 2. we skip item (d) and calculate the filter components directly with expressions (2. r31 =50.12) .Chapter 2 / Phase Model for PLL Synthesizers 41 w oln = w olnpf r pf and 1 α n = α npf ⋅ r pf 1+ 1 r21 2 (e) Evaluate filter components using recentered woln . In the case of a 2nd order loop filter. the same algorithm can be used ignoring the recentering correction. : α max r21 =25 . frequency corresponding to the DC value –3dB in closed loop magnitude. = 2 ⋅ r21 . wp3 ( x ) . maximum value –DC value for the closed loop magnitude. α min Some other parameters are also indicated: • • • • • wz1 ( o ) .
The filter algorithm and the associated notation. The graphs are the output of executable files that are programmed with parametric inputs.2. Therefore the polynomial approximations used in the development are accurate enough for our applications.b Closed Loop Figure 2.9 are calculated with a mathematical simulation software.9. through frequency ratios. They are continuously applied in the following chapters. 2. Matlab.r21) gain variation is conveniently fitted.42 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops fig.9. . The numerical examples of figures 2. being a flexible calculation tool.a Open Loop fig.9 Numerical example of robust filter design We verify that the centering compensation is effective and that the normalized (2. The tables are also an interesting design tool easily implemented in any spreadsheet software.7 and 2. proved to be quite adequate to design and compare loop applications in a systematic and simple manner.
................................ 3.......................... 65 Figures: Figure 3...................................................................Chapter 3 / Application Related Constraints 43 Contents: 3.. 47 Free running VCO power spectrum density ........................ 59 3...................................... 64 Tables: Table 31 Table 32 Table 33 Table 34 Comparing the denominators of B(s) and BRL(s) .1 Figure 3...................................... and an example of a satellite application is developed............4................................................................................................. In this chapter we study parameters concerning the spectral purity of a VCO locked by a PLL.....................................................................................................5..................................... 3.................. ................................................................................................................................ 60 Optimizing Total Phase Deviation .................................................... The parameters concern the adequacy of the closed loop bandwidth to the noise performance of the VCO........7 Figure 3..........................................................................6 Figure 3.............4............................................................................................ 50 Combined Spectrum: PLL + VCO noise contributions . 54 Rootlocus approach for wcl : parameters of BRL(s) ................... 53 3............................3 Figure 3...........8 Figure 3. 50 3.....2 Figure 3....................................................5 Figure 3......................... 44 VCO Noise Representation and Phase Noise Units ............................................................................................................................................................................................................................ 52 Rootlocus for w3dB location........... 49 PSD of a VCO locked by a PLL ....4. 49 Peaking X Optimum Closed Loop bandwidth.......................... 67 3 Application Related Constraints So far we discussed the PLL system quite separate from its application........................................ 3...................................................................1. 46 Optimum Closed Loop Bandwidth ..... Application Related Constraints 43 Reference Breakthrough ......................6.............................................. 58 Rootlocus for was location............................................................1............ Maximum Phase Jitter ........................................... w3dB derivation from was ..................9 BB noise representation of the VCO..............................3............................................................... and the suppression of deterministic interference at fcp .............................. 3......... 61 Gain Stability Boundary........................................................ 52 3............................2.................................................................................................................... PLL Closed Loop Bandwidth ............................................. 63 Maximum SSB noise requirement .... The filter calculation method is extended to discuss the maximum phase deviation in the synthesized carrier... w3dB derivation from BRL(s)...................... 65 Maximum Normalized Gain Variation .4 Figure 3............................2...... 58 Gain Stability Boundary .............................................
is a FM interference found in the VCO output at frequency offsets of ±fcp. in the case of active loop filters. i Sometimes the name spurious rays is also used for other deterministic interference found in the VCO output. that can be either deterministic or random. The sinking and sourcing pulses have different rise and fall times so the combined current output is not null. The spurious requirement should be met by providing the necessary attenuation of the fcp component. These interferences are originated by the operation of different integrated blocks. and they contaminated Vtune by parasitic coupling. that considers two single noise contributions: one for the VCO and another for the ensemble of the PLL blocks.1 Reference Breakthrough Reference breakthrough. The fcp component of the loop filter output generates the FM modulation of the VCO. These variations are compensated by the feedback action of the PLL. The sources of noise.44 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops This chapter starts to analyze the phase noise contents of the carrier output of the PLL synthesizer. we calculate a loop filter that guarantees a total phase deviation lower than 2° for the entire range of normalized gain variation (2. or spurious rays . This is done in order to avoid deadzone problems (see chapter 1). it is a system level analysis. we should be able to choose the closed loop bandwidth with respect to the noise performances of the PLL and the VCO. In this example. which provides every Tcp the average lost charge. A first cause of the reference breakthrough is leakage currents. The total phase deviation is introduced as a figure of merit for the noise contents in the carrier spectrum. At this point. In order to minimize the phase noise in the spectrum of the synthesized carrier. the amplifier input current. The value of H(jw)w = 2π.fcp represents the rejection by the loop filter of the fundamental component of the input current pulses. ii i For a charge pump output and resonant circuit input with high impedance. The time response of the filter is further discussed in chapter 5. ii This effect is relevant for large bandwidth (bw) filters. Later in chapter 7. proportional to the residual transient current. these noise specifications are translated to a circuit level description.r21). . A second cause is the transient mismatch of the sinking and sourcing pulses of the charge pump. a discharge current in the loop filter impedance. an unwanted current of the charge pump in the off state. are progressively presented in chapters 4 and 6. 3. the loop filter discharge is proportional to the time constant Tp2 . The leakage currents cause variations in the value of Vtune . and it presents components at fcp and its harmonics. A numerical example for a satellite frontend exemplifies the calculation method. Practical examples of leakage currents are: the reverse current of the varicap (from the oscillator resonant circuit). When in lock both sources are switched on during the reset interval. The calculation algorithm for the loop filter is then extended to take into account the specification of a closed loop bandwidth. In large bw filters this discharge causes significant changes in Vtune during a Tcp interval.
(in locked mode Vtune is practically constant). which gives: β s(t ) = Ac ⋅ cos(wc ⋅ t ) + ⋅ cos(wc − wcp ) t − cos(wc + wcp ) t 2 [ ] (3. the accuracy of the calculation of the spurious rays is limited by the evaluation of the Ileakage value.2) is a 1st order evaluation of the sidebands at the reference frequency. The spurious level is proportional to the current that compensates these effects. For instance the mismatch between sinking and sourcing may be evaluated with a PLL behavioural model including a circuit level description of . It is an overestimation because we assumed all the power of the compensation current concentrated at fcp . and an FM modulated carrier s(t): m(t ) = Am ⋅ cos( wcp ⋅ t ) Kvco ⋅ Am ⋅ sin( wcp ⋅ t ) s(t ) = Ac ⋅ cos wc ⋅ t + 2π ⋅ Kvco ∫ m(t ) dt = Ac ⋅ cos wc ⋅ t + f cp [ ] We define the peak phase deviation β: β= Kvco ⋅ Am f cp . For the calculation we do two approximations.Chapter 3 / Application Related Constraints 45 Once we evaluate the total leakage current and mismatch we can calculate the corresponding spurious level.1) The leakage current component at fcp represents a voltage amplitude in the VCO input of: Am = I leakage ⋅ Z filter ( jw ) w = wcp The resulting SSB spurious rays measured with respect to the carrier amplitude becomes: SSB FM modulated f cp component As = 20 ⋅ log carrier amplitude β = 20 ⋅ log 2 or I leakage ⋅ Z filter ( w cp ) ⋅ K vco As = 20 ⋅ log 2 ⋅ f cp (3. First we assume that the frequency content of the compensation current is concentrated at fcp. In practice. and the charge pump off current.2) Equation (3. The residual transient current depends on the circuit design. The leakage currents that depend only on the Vtune value are easier to evaluate. and it is easier and more accurate to use a mixed circuit and behavioural simulation. Second we use the narrow band FM approximation as the phase deviations are small. Let us suppose a single tone modulating signal m(t). It is the case of the varicap reverse current (component specification). and apply the FM narrow band approximation for β << 1 rad . the amplifier input current.
or when a better accuracy is required. noise or deterministic. have finite power and have a band limited power spectrum density (PSD). the current difference.46 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops the charge pump. such as supply contamination and substrate coupling. at Vtune. These names refer to the zones of the VCO output which are dominated by the PLL input noise or by the VCO intrinsic (freerunning) noise. The PLL behavioural model for time domain simulations is discussed in chapter 7. For perturbations exceeding this modulation index. iii Another method of direct evaluation is rather lengthy. Roughly the flat part of B(jw) corresponds to the PLL determined. The –60dB/dec region of B(jw) . and in chapter 7 the simulation tools that relate noise and design are discussed. . and we proceed with the choice of the PLL bandwidth optimizing the phase deviation content. or directly applying an FFT (fast Fourier transform) at the simulated Vtune signal. In this context the VCO spectrum may be modeled by a white noise voltage source at the integrator input. iii 3. The BB representation makes a frequency conversion of the BPF behaviour of the VCO in an LPF behaviour. and the power fraction at fcp is calculated. since we need first to find the correct phase difference between the phase detector inputs that corresponds to an average constant charge. Tcp periodic signal.2 VCO Noise Representation and Phase Noise Units The spectrum of a VCO locked by a PLL is composed of two zones. The total noise contribution from the different PLL blocks is concentrated at the phase detector input. In this model we may add other causes of spurious rays. However. in a first approach let us consider two white noise sources representing the VCO and PLL noise contributions. inloop zone. a more complete description should be used. In the baseband (BB) phase representation adopted in chapter 2. The narrow band treatment used above is valid for any phase deviation that respects the maximum peak deviation boundary. In chapter 4 we discuss the role of the loop amplifier in the transmission of supply perturbations. is the outofloop zone. We start with a global approach that considers the optimization of the VCO spectrum for given VCO and PLL noise performances. where the intrinsic VCO noise (with –20dB/dec) takes over. The resulting spurious rays may be calculated with the value of Ileakage and equation (3. After that.2). In reality all input signals. For the moment we use the narrow band approach to discuss rather small phase disturbances. such as random noise sources. the mechanisms of phase noise generation are described. The following section introduces the units used to characterize the oscillator phase noise. One is called inloop and the other outofloop. including other harmonic components. the VCO is represented by an integrator with sensitivity Kvco. is compared to a square or triangular pulse. and we name it NPLL . ∆ϕmax << 1rad. Later in chapter 6.
.Chapter 3 / Application Related Constraints 47 Ko s [Vrms2/Hz] ϕosc VCO output spectrum VCO PSD [W/Hz] 30dB/dec vnvco2 20dB/dec ~ frecover log (foffset) fosc Figure 3. So a more complete description. the voltage noise source. L(f) is SSB phase noise defined by: L( f offset ) = area in 1 Hz bw at f offset SSB power due to phase fluctuation = total signal power total area under the curve or L ( f offset ) = Pnoise ( f offset ) Pcarrier + ∫ Pnoise ( f ) df 0 ∞ ≈ Pnoise ( f offset ) Pcarrier = 1 CNR 1 Hz (3.3) the factor 2 relates this base band representation to a singleside band (SSB) measurement.3) The part of the VCO spectrum with a –20dB/dec slope is correctly represented by a white voltage noise source.1 BB noise representation of the VCO 2 L dB ( f offset ) f f offset vnvco 10 ⋅ L ( f offset ) = 2 ⋅ offset ⋅ 10 = 2 ⋅ Kvco Kvco bw 2 2 Vrms 2 Hz (3. In the case of a large bandwidth PLL. which points to the intersection of the white and flicker noise contributions. a free running oscillator presents a phase noise with higher rolloff. vnvco. Near the carrier.1 this is indicated by the corner frequency frecover . due to the presence of 1/f (flicker) noise sources. which would be valid for offset frequencies below frecover . needs to include poles and zeros in the vnvco expression. In equation (3. In figure 3. The part of the spectrum with the 30dB/dec rolloff is hidden by the PLL noise.4) when expressed in dB it equals LdB ( f ) = 10 log [L ( f ) ] dBc Hz . to represent the different slopes in the output spectrum. dBc ⇒ dB with respect to carrier power. does not need to be frequency shaped. L(f).
For decreasing values of fm . and an ideal filter with a bandwidth of 1Hz around fm . this limitation is hidden by the PLL inloop region.5) holds when the sideband amplitudes are evaluated by the narrow band approach. . with an amplitude value equal to Ac. the phase deviation increases and the narrow band approximation is no longer valid. It may be seen as the BB equivalent of L(f) : S ϕ ( f ) = 2 ⋅ L ( f offset ) [rad 2 Hz ] .1). K vco ⋅ 2 ⋅ v nvco fm with a peak phase deviation: and an oscillator phase: . Sϕ S ϕ dB ( f ) = 10 ⋅ log 1rad 2 = L dB ( f ) + 3 dB (3.48 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops At this point we take a filtered portion of vnvco . since the PLL noise contribution appears as a phase and not as a frequency modulating iv signal of ϕosc.5) Expression (3. or the mean square phase fluctuations power. Using equation (3. we obtain: m (t ) = 2 ⋅ v nvco ⋅ cos (w m t + ϕ m ) [V ] β = . Otherwise a significant amount of the BB power is scattered in higher harmonics of fm around the carrier. iv A more detailed discussion of the spectrum differences between PM and FM appears in chapter 6 . We may represent the phase deviation caused by m(t) as two sidebands at offset frequencies of ±fm . Once more. and analyze it as a deterministic signal that modulates the VCO. This condition indicates the minimum frequency offset for which the VCO can be represented by a linear phase model.β /2 . or: Ac ⋅ β ⋅ 1 2 2 β 2 L( fm ) = = 2 4 Ac 2 2 K β L dB ( f m ) = 20 ⋅ log = 20 ⋅ log 2 K vco ⋅ v nvco 2 ⋅ fm Sϕ(f) is the double side band (DSB) phase noise. ϕ osc (t ) = wc t + β ⋅ sin (w m t + ϕ m ) [rad ] The baseband representation of the oscillator phase is given by: ϕ osc − wc ⋅ t = 2π ⋅ K vco ⋅ ∫ m(t ) dt which corresponds directly to the block diagram in figure 3. Figure 3.2 illustrates the phase noise units in the side band and base band representations of the free running VCO spectrum.1.
3 v PSD of a VCO locked by a PLL The DSB graphs abscissas need to be split in two regions if we want to keep the logarithm scale with respect to foffset . Since the feedback path is the same for B(s) and Bvco(s). they have equal denominators.Chapter 3 / Application Related Constraints 49 Posc(f) [W/Hz] Ac 2 2 DSB representation 1 [rad2/Hz] Sϕ(f) BB representation L(foffset) Ac ⋅ β 8 2 2 . The noise contributions from NPLL and vnvco are indicated separately. B(s). determines the transfer of NPLL to the output spectrum.2 Free running VCO power spectrum density v The PLL noise contribution. In a similar manner we may define Bvco(s) as the closed loop transfer function of ϕosc / vnvco . or to the phase deviation values.6) Posc(f) [W/Hz] 1 DSB representation Sϕ(f) BB representation [rad2/Hz] freerunning VCO_Sφ(f) (Npll)2 . is a phase jitter in rad/sqrt(Hz). . L(foff1) = Sϕ(foff1) β2 4 fosc log(ffc) foffset f log(ffc) foff1 foffset ( ) Figure 3. Figure (3. The level of the sidebands corresponds to a unitary normalized carrier level. B(f)2 (vnvco)2/2. K o ⋅ s ⋅ C 1 ⋅ (1 + sT p 2 ) ⋅ (1 + sT p 3 ) B (s) = 2 K ϕ ⋅ F (s) s ⋅ C 1 ⋅ (1 + sT p 2 ) ⋅ (1 + sT p 3 ) + α ⋅ (1 + sT z 1 ) B vco ( s ) = (3. NPLL . The closed loop transfer function.Bvco(f)2 from Vnvco from Npll 20dB/dec 20log(N) log(f) log(ffc) log(ffc) fosc 60dB/dec Npll+3dB Figure 3.3) shows BB and DSB representations of the spectrum of a VCO locked by a PLL. analyzed in chapter 2.
8) ). we notice that they both have a second order polynomial in the denominator. K o ⋅ s ⋅ C1 s 2ξ 2 + ⋅ s + 1 ⋅ α w n wn 2 B vco _ BPF ( s ) = (3. the inloop one and the outofloop one.50 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops Bvco(s) has an overall band pass filtering behaviour. we need to know the PLL and VCO noise performances in order to choose an adequate feedback bandwidth. Nevertheless. This mismatch peaking adds to the low phase margin peaking seen in chapter 2.4. from Npll additional peaking from Npll Ideal closed loop bw Ideal closed loop bw excessive PLL noise from Vnvco. fosc fosc from Vnvco. we verify that the wn in Bvco_BPF is slightly larger than the one in B3LPF . In numerical examples. the dominant noise in each of these zones originates from independent noise sources.3 Optimum Closed Loop Bandwidth In order to minimize the noise of the output spectrum.3 shows an ideally smooth intersection between the two zones of the spectrum. It is a simplified function resembling B3LPF(s) (equation (2. where the noise contributions from Npll and vnvco cross each other. Figure 3. we need to match the PLL closed loop bandwidth (fcl) with the intersection frequency.7) Comparing Bvco_BPF and B3LPF .4 Peaking X Optimum Closed Loop bandwidth . the simplified LPF description of B(s). and in practice the feedback bandwidth and gain determine whether the intersection is smooth or bumpy. and it is due to both causes. Figure 3. as drafted in figure 3. and afterwards center a stable filter around this bandwidth. written in a standard ξ and wn form. an overall peaking is observed. The interest of these simplified forms appears when we are minimizing the noise content of the output spectrum. We choose this common notation to indicate similar roots in the two functions. We use again the term peaking to refer to the spectral overshoot. 3. Thus. Mismatches result in additional peaking or excessive PLL noise. This can be represented by an approximate transfer function Bvco_BPF . In the measurements.
and 3dB below the DC vi value. woln ( . Unfortunately this bandwidth will correspond only to the central gain value. for the centered gain value αnpf . • fig 3.Chapter 3 / Application Related Constraints 51 The ideal feedback bandwidth is indicated in the figure above. The choice of the bandwidth should take into account the optimization of the phase jitter over the entire range of gain. The same symbols from figure 2.log[N]). 3.c and d: detailed contributions of PLL and VCO noise for the curves in part b.a : shows the total output spectrum plus isolated PLL and VCO noise contributions.9 are used to indicate wz1 ( o ). and we know that synthesizers work with a large range of gain variation. and the separated PLL and VCO noise contributions for a set of different gain values. • fig 3.5. wolnpf ( * ). We start with a numerical example showing the spectrum of a VCO locked by a PLL. Three asymptotes are added in dotted lines.r21) around αnpf .5. the Npll DC transfer value (20. The spectrum has a minimum jitter content when we center a loop filter around this bandwidth.b: total output spectrum for gain values varying within a range of (2. They correspond to the VCO freerunning behaviour. The figure is divided into four parts: • fig.5.
is indicated in figure 3. Zp2 ( x). wp3 ( x ).5. used in the loop filter calculation. we seek now a relationship between the open and closed loop bandwidths for a gain range around the centered value αnpf .5 GHz Let us define fi as being the intersection frequency for PLL and VCO noise asymptotes. which are plotted in different scales. also called synthesizer noise floor.8) In order to optimize the output spectrum we want to center the closed bandwidth fcl around fi . The asymptotes are repeated in the other subplots (3. NPLL . But so far we only specified the open loop bandwidth fol.5.d by a dotted line.5. Hence.b/c/d) to simplify the comparison among the curves. as indicated in figure 3. vi .a: f offset Lvco ( f offset ) + 20 ⋅ log f i f i = f offset ⋅ 10 = N pll + 20 ⋅ log( N ) N pll + 20⋅log( N ) − Lvco ( f offset ) − 20 (3. The numerical values used for these graphs correspond to the performance of low noise satellite PLL and VCO: K for Fcp = 1 MHz N = 1500 Lvco (100 KHz ) = − 100 dBc / Hz dBc / Hz N pll = − 154 Fvco = 1 .
and to the central frequency of a BPF for vnvco.c fig. two analytic methods are discussed. This bandwidth corresponds to the LPF cutoff frequency for NPLL.4 PLL Closed Loop Bandwidth The simplified transfer functions B3LPF and Bvco_BPF . 3. 3.52 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops a b c d e fig.a fig. showed that the PLL and the VCO noise contributions have a similar closed loop bandwidth. The closed bandwidth must approach fi . but it is the open loop bandwidth that is used for the filter calculation. depending on wn and ξ . and by the loop gain α .d Figure 3.5.5. with numerical evaluations. we assume that both transfer functions have an identical closed loop bandwidth. 3. Therefore. which is determined by the zero and poles of the loop filter.5. Later on. After that. . First we do a quantitative approach of the ratio w3dB/wol .b fig.5 Combined Spectrum: PLL + VCO noise contributions 3. Let us consider w3dB as the closed loop bandwidth.5. we need to relate the open and closed loop PLL bandwidths. 3.
4. Subsequently. α ⋅ (1 + sT z 1 ) B(s) = 2 N s ⋅ C 1 (1 + sT p 2 ) ⋅ (1 + sT p 3 ) + α ⋅ (1 + sT z 1 ) [ ] B ( s ) B RL ( s ) = N N B RL ( s ) = N α ⋅ (1 + sT z 1 ) 2 ξ (1 + sT p’ 3 ) ⋅ (1 + sT z’1 ) ⋅ s 2 + 2w s + 1 ⋅ α w n n (3.1 w3dB derivation from BRL(s) This first method compares the closed loop transfer B(s).9) By inspection we verify that B3LPF (eq. it deduces the minimum and maximum boundaries for wn and ξ. 28 w ol In chapter 2 we saw that the open loop bandwidth wol varies around wolnpf . which is proportional to wol .5 . The polynomial BRL(s) is equivalent to B(s). and relates these parameters to w3dB .r21) around wolnpf. The difficulty to evaluate w3dB (more precisely) comes from the fact that the denominator of the closed loop transfer function DB(s). Thus it is likely that w3dB. show that this ratio is contained in a limited range. . when we assume that the r21 and r31 values belong to the ranges indicated below. The overall result is already announced in the paragraph above. with a polynomial that arises from the rootlocus representation. Closed loop bandwidth varies as much as open loop bandwidth and we need some application criteria to define how to accommodate this variation.6 r31 w 3 dB = 1 . .4. for a centered gain variation of (2. BRL(s) has 4 roots agreeing with the branches of the rootlocus presented in figure 2. The results and conditions are: r21 r31 ∧ ∈ ∈ [10 [16 . varies around a value close to woln . The limiting ranges include the typical values encountered in synthesizer applications.2 using some algebra puzzles. 63 ± 0 .4. This implies a variable peaking and a variable w3dB/wn . The rootlocus representation of B(s) may be used to derive two formal expressions for w3dB .1 and 3.6. An example of an application criterion for digital phase modulations is presented in section 3. and slightly larger. (2. These expressions are derived in sections 3.Chapter 3 / Application Related Constraints 53 Numerical evaluations of the ratio w3dB/wol . has complex roots with a variable damping. Numerical evaluations are used to validate the method. with the following approximations: Tz1’ → Tz1 and Tp3’ → Tp3 .8) ) is a simplified version of BRL . 3. 50 ] ∞] ⇒ r21 ≥ 1 .
with: β = T p’ 3 T p3 KK 0 ≤ β ≤1 and γ = T z’1 T z1 KK 0 ≤γ ≤1 . 1] with β ∈ [0 . Expression (3.54 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops The transfer function BRL states that for any given α. The two others are either real or complex depending on the value of ξ .11) We may use the last two expressions to derive the minimum and maximum boundaries of wn . the real roots correspond to the time constants Tz1’ and Tp3’.10) from 1st order terms: w n = w oln ⋅ r21 ⋅ (1 − γ 2ξ ) (3. We define γ and β. We expand the denominators of B(s) and BRL(s). α max ] . The assumption of two real roots agrees with the rootlocus diagram of figure 2. Furthermore the diagram shows that the position of the real roots may be specified within limited frequency ranges. In our notation. and compare the coefficients of the 4th and 1st order terms of s. as the ratios between the time constants.10) contains variables that belong to closed and known ranges. α α ∈ npf 2 ⋅ r21 .6. finding the following equalities: term DB(s)/α r21 αn ⋅ 4 α r31 ⋅ w oln r21 w oln = DBRL(s)/α β ⋅ γ ⋅r21 2 2 r31 ⋅ w n ⋅ w oln γ ⋅ r21 2ξ + w oln wn 4th s4 1st s1 Table 31 = Comparing the denominators of B(s) and BRL(s) from 4 order terms: th w n = w oln α ⋅ α ⋅ β ⋅ γ ⋅ r21 n 1 2 (3. α npf ⋅ 2 ⋅ r21 = [α min ∧ . We use it to derive the maximum limit of wn. at least two roots are real. 1] γ ∈ [0 α → α max max{wn } ↔ β → 1 γ → 1 .
. 269 w oln ⋅ 2ξ r21 ⋅ (1 − γ ) = 0 . It holds that PhM = arctg 2ξ − 2ξ 2 + 4ξ 4 + 1 (3. The maximum ξ value is 1. r21 . for r31 ≥ 1. We continue to work with the hypothesis that the two complex roots are largely determining B(jw) around wn . we may suppose that the phase margin is mostly influenced by the pair of complex roots which are represented by the 2nd order polynomial in ξ and wn. 1] 1] min {w n } > lim γ →0 ξ → 0 . PhM = 30 ° ⇒ ξ = 0 .13) Using equation (3.14) in equation (3.19 ) (3.r21 can be covered with a minimum phase margin of 30°. related to the recentering procedure. seen in chapter 2.13) we evaluate the minimum value of ξ corresponding to a 30° PhM. we observed that a gain variation of 2. wn and w3dB . 54 ⋅ w oln r21 = 0 .14) Finally the minimum boundary for wn is calculated substituting (3. 6 ° ) (3.12) In order to find the minimum of wn with expression (3.15) The next step concerns the relationships between ξ. Observing BRL(s) and the rootlocus. Later in this section a numerical example illustrates the difference. and the open loop phase margin PhM. we may use the following expression deduced from the standard 2nd LPF: vii A more rigorous treatment should take into account the ratio αn/αnpf . corresponding to α values with 4 real roots.11): ξ γ ∈ ∈ [0 .6 . viii . 269 [0 .Chapter 3 / Application Related Constraints 55 so: α max {wn } < lim woln ⋅ α ⋅ β ⋅ γ ⋅ r21 α →α max n β →1 γ →1 1 2 α = woln ⋅ α n 1 2 (r21 )14 but since the maximum of wn becomes : vii α n ≥ α npf ⇒ α max < α n ⋅ 2 ⋅ r21 1 2 max {w n } < w oln ⋅ (r21 ) ⋅ (2 ) 1 4 = w p 2 ⋅ (1. So we may look for a relationship between ξ and the phase margin parameters to specify the boundary of the variation of ξ. Therefore we may rely on the analysis of the 2nd order LPF to derive the relationship between the damping factor ξ. After the recentering procedure outlined in chapter 2. Hence.269 = sin (15 . 54 ⋅ w z 1 (3.11) we need to find the minimum viii occurring value of ξ.
1] ⇒ w 3 dB wn ∈ [1 . Another possibility to relate the close loop transfer with the values of ξ is found in phase Bode plots. by dPhB.9.97 ⋅ w p 2 ↓ 0. mean (w3 dB ) = 1.54 ⋅ w z1 < wn < 0.56 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops w 3 dB = (1 − ξ ) + ξ 2 − 2ξ + 2 wn [ ] 1 2 (3.404 .12 ⋅ w oln The maximum value of wn was overestimated in equation (3. we need to know the ratio r31/r21 . . mean (w3 dB ) = 1. Expression (3.12) is a rougher boundary estimation not depending on r31 value.269 . we find: ξ ∈ [0 .12) because we neglected the ratio ix αn / αnpf . occurring for αmax and αmin .23 1 α ∈ [α min . 1] (3. both correspond to cases where the PhM equals 30°.16) Combining (3. 404 wn The combination of the minimum and maximum boundaries of wn and this ratio gives the desired range of w3dB: α ∈ [α min .16) with our restricted domain of ξ .17) The extreme values of wn .18) ix In order to introduce αn / αnpf factor. This relationship was presented numerically in figure 2. or: w 3 dB = 1 . A numerical application correcting this maximum boundary for given values of r21 and r31 is presented below: r21 = 25 r31 = 50 for: ⇒ αn α npf 2 = 1. or ξ equals 0. dPhB ( jw ) = d [ phase ( B ( jw )) ]⋅ ∆ woctave = d [ ph ( B ( jw )) ]⋅ 2 wn − wn = d [ ph ( B ( jw )) ]⋅ wn dw dw 2 dw 2 (3.01 ⋅ w oln Thus the range of w3dB centers approximately around wol . α max ] K 0.54 ⋅ w z1 < w n < 1. the geometrical mean of the range of w3dB is: geom.269 .α max ] with α max = 2 ⋅ r21 α min ⇒ 0.36 ⋅ w p 2 Here.75 ⋅ w z1 < w3dB < 1. With this result we combine the open and closed loop specifications for the spectrum optimization. the phase variation for a frequency delta of one octave around wn .67 ⋅ w p 2 The geometrical mean of the range of w3dB equals: geom.75 ⋅ w z1 < w3 dB < 1.2 ⋅ w p 2 K 0.
10). n . 2 . 1 . 4 . concerning the maximum phase margin. are evaluated for the left rootlocus diagram with: r21=25 and r31=50 . (2 ⋅ r21 ) α = α npf ⋅ (2 ⋅ r21 ) α npf . A set of gain values within the usual (2. w n = w olnpf ∗ [ 1 .269 max {dPhB ( jw )} = −149 ° / octave In this case. Figure 3.b we observe that a small value of r21 limits the maximum value of ξ . are effectively contained in the area corresponding to arcsin(ξ)>15° . 45 ° . This result agrees with expression (2. γ.5 0.26 . The 4th branch follows the real axis from –wp3 towards ∞ . The grid indicates natural frequencies and damping arches (ϕ = arcsin ξ ).6 illustrates the rootlocus for different values of r21 and r31.5 . so that the damping of the complex roots can be easily visualized. The plot is magnified around the origin of the splane. ξ. 15 ° ] Grid: Gain values signaled by a delta (∆): α − 0. We verify that all the roots signaled by a ∆.Chapter 3 / Application Related Constraints 57 For our faithful 2nd order LPF. or ξ >0. where the postfilter has a significant influence in the phase variation around wn .60 ° . . and wn . from the expression of BRL(s). 30 ° . In figure 3. and the roots corresponding to these gain values are indicated by delta signs (∆) . 8 ] arcsin ξ = [75 °.15.a . the analogy to the 2nd order LPF is accurate for 3rd order loops. In table 32 the columns coloured gray correspond to the α values indicated by a ∆ signal in figure 3. The values of β. but not for 4th order loops. Hence we stick to the rootlocus criterion to center the closed loop bandwidth .6.r21) interval is chosen. dPhB becomes: dPhB ( jw ) = − 1 wn ⋅ = ξ ⋅ wn 2 ⇒ −1 2 ⋅ξ [rad ] = − 40 ξ [°] for ξ = ξ min = 0 .
6 Rootlocus for w3dB location α β = T ’ p3 α npf α npf 1 2 (2 ⋅ r21 ) = w p3 w ’p 3 (2 ⋅ r21 ) 0.6. we take an average of the two roots which are the closest to the complex branches.927 0.71 0.0442 0.9° γ = T z’1 w = z1 ’ T z1 w z1 x 0.6.58 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops Figure 3.676 42.0415 0.802 0.978 αnpf 1 4 αn α npf ⋅ (2 ⋅ r21 ) 0.890 0.00 90.196 0.275 15.958 5.99 0.3° 0.b Figure 3.0° 0. For α values where all roots are real.948 0.0° 0.5° 1 4 α npf ⋅ (2 ⋅ r21 ) 1 4 T p3 0.958 73.756 2.0547 0.585 0.a Figure 3.325 19.8° wn w olnpf min (ξ) arcsin [min (ξ) ] Table 32 Rootlocus approach for wcl : parameters of BRL(s) wn for the pair of complex roots.542 32. x .328 0.65 1.879 3.991 0.
l∈Z l ∈ [0 .2 w3dB derivation from was This second method gives some further insight into the rootlocus representation. we can apply the following expression.19) and (3. xi m : order of the numerator of H(s). φl = 60° . In fact for an increasing gain there are two possibilities of satisfying the closed loop characteristic equation (3.20).19): s ⋅ DF (s) . that is derived from(3.Chapter 3 / Application Related Constraints 59 3. 300° . N F (s) → 0 .20) Expressing the asymptotes in the polar form ( s o = R ⋅ e jΦ l ) and solving the phase condition for (3. N F (s) =0 s ⋅ DF ( s ) N F (s) s N F (s) ⋅ w + 1 as 1 + H (s) = 1 + α ⋅ lim → α →∞ and lim w → ∞ 1+α ⋅ n−m = 1+ α s w + 1 as n−m =0 (3.4. 180° . comparing the coefficients of order sn1 . (3. However it is limited to a single gain value. → −∞ N F (s ) xi .20).plane (LHP) n−m ∴ zi : zero s of H(s) _ with z i = z i for zeros in the LHP In our case (nm) = 3 . and r − 1 woln ⋅ r21 + 31 r21 r21 = woln ⋅ [r + r − 1] → w = oln 21 31 for r 21 >> 1 3 3 r21 and r31 >> 1 was r + r31 ⋅ 21 3 r 21 There are (nm) centrifugal asymptotes because m root branches tend to the m zeros of the open loop transfer function. The asymptotes of the rootlocus for increasing gain values are given by radial lines. gives: 1 phase s − w as n−m = 180 ° + l ⋅ 360 ° = (n − m ) ⋅ Φ s = so w→ ∞ Φ l l = 180 ° + l ⋅ 360 ° n−m ∧ . φl and was . which have a known phase and origin. It follows that: w as = ∑ p −∑z i pi i : poles of H(s) _ with p i = p i for poles in the left side of the S . The second case supposes n > m and w → ∞ .19) where n : order of the denominator of H(s). (n − m − 1 )] For n > m+1 .
The roots corresponding to αmax and αmin are indicated with ∆ signals.5 ⋅ w p 2 r21 numerical examples for r31 = 1. A rough estimate of the closed loop bandwidth for α ≈ αn is the frequency of 3dB attenuation for Bas(jw).51) ≈ woln ⋅ 21 31 6⋅ r 21 r31 = 2 K w3dB − as = 0. Figure 3.60 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops We use was to define a LPF transfer function. with the asymptotes for large gain and was . Bas(s).6 K w3dB − as = 0.7 Rootlocus for was location .4 ⋅ w p 2 r21 The figure below shows a rootlocus in full scale. named w3dBas : B as (s ) 1 = 3 N s + 1 was B as ( jw3dB − as ) 1 1 = = 3 N 2 2 2 w3dB − as + 1 w as K K r +r w3dB − as = w as ⋅ (0. with three real poles at was .
For some types of digital phase modulation. xii . including the specifications of the demodulator block.8 ⋅ woln n npf r31 = 50 nd st The 2 method results in a larger value of w3dB than the 1 one. In the 2nd method w3dB was estimated for a gain of αn . the total phase deviation is a meaningful parameter.fi = w3dB = woln). The total phase deviation is defined as: σϕ = ∫ f max f min S ϕ ( f ) df [rad] (3. The characteristics of other blocks of the receiver. and we see that small α values present a quite higher peaking than large α values. In practice we often choose w3dB in the range: woln ≤ w3dB ≤ 2 ⋅ woln .5 ⋅ woln = 1. in a range closely proportional to the variation of wol. Figure 3. Using this larger value the xii spectrum will present a smaller variation of the peaking value αmin and αmax . We know that these two transfer functions have similar bandwidths. So before the comparison we need to choose values for r21 and r31 and recenter w3dB_as with respect to αn/αnpf . the optimization of the LO spectrum is bound to the type of data modulation. and/or to the symbol rate. In chapter 7 we discuss a behavioural model including the carrier recovery loop of a QPSK decoder. So the achievable BER performance may not be directly derived from σϕ . such as filter stages and the carrier recovery loop are also relevant to the sensibility to phase noise. ⇒ w3dB _ as α = 0. when we have a given fi (intersection frequency). The LO spectrum is a combination of the contributions of Npll and vnvco.5 ⋅ woln K w3dB _ as α = rpf ⋅ 2.21) where fmin and fmax are related to the channel bandwidth . transferred by B(s) and Bvco(s) respectively.5 is traced for a w3dB chosen by the 1st method (2π.Chapter 3 / Application Related Constraints 61 We would like to compare the results of the two methods for the estimation of w 3dB . and that wn varies with α. and the implementation loss caused by this signal degradation. close to wn in B3LPF(s) and BVCOBPF(s). QPSK and GMSK. The following section discusses the total phase deviation. we choose : w 3 dB = 2π ⋅ f i and w 3dB ≤ w oln ≤ w 3dB 2 In a larger scope. which is a determinant parameter for phase modulated data. This model is used to evaluate the amount of phase deviation that appears in the demodulator.5 Maximum Phase Jitter The specification of the spectral purity of the local oscillator depends on the input signal that has to be frequencyconverted. such as BPSK. 3. and in the 1st method the centered value corresponds to αnpf .5 ⋅ w p 2 = 2. r21 = 25 or inversely.
So a changing value of N modifies σϕ . The characteristics of the PLL and the VCO are identical to the ones used in the Bode plot of Fig. Lvco(100KHz)=100dBc/Hz .8 : α = αnpf ⋅ (2 ⋅ r21)−0. N = 1500 . The linear scale is presented as a visual recall of the spectrum analyzer output. A large bandwidth is assumed for the evaluation of σϕ . the change would not be significant.log(N) modulates the height of the PLL noise contribution.25 .17).8 there is an approximation due to the constant divider ratio N. They are: Npll = 154 dBc/Hz @ Fcp = 1 MHz . xiii xiv Function of r21 and r31 .25 . The graph below is calculated with a programmed Matlab routine.5 . expression (2.22). Therefore we may choose to center wolnpf in a frequency larger than the one indicated in equation (3. wolnpf = 2π ⋅ f i ⋅ (rpf ) 1 4 ⇒ 2π ⋅ f i = wolnpf ⋅ woln (3. so as to obtain a minimum σϕ over the total gain range. (2 ⋅ r21)0. The integer values of the abscissa correspond to the geometrically distributed values of α .23) The integration boundaries of the right most term of (3.23).r21) range. In chapter 7 we discuss another simulation model easily implemented in software for analog circuitry simulation. The factor 20. For other cases with a larger range of dividing ratios. xiii The plot below shows an example of the placement of wolnpf with respect to fi and rpf . with a ratio Nmax/Nmin =2. A numerical simulation tool is always indicated to verify the total phase deviation. we may expect that: • N → Nmax ⇒ α → αmin : an increase in σϕ with respect to the evaluation with a constant N.fi ). (2 ⋅ r21)−0. with respect to N and α values.5 [ ] . f max f min ∫ Sϕ df ≈ +∞ ∫ Sϕ 0 40 ⋅ f p 3 df ≈ f z1 ∫ Sϕ df 500 (3.62 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops Using σϕ as a spectral quality parameter. xiv These α values are the same used in the other plots of Fig. The 3rd curve presents the total phase deviation observed in the plots of the spectrum. In figure 3. The curves are calculated for different gain values covering the normalized (2. (2 ⋅ r21)0. 3. For a Sϕ ( f ) f << f oln → cst and Sϕ ( f ) f >> f p3 → −∞ we may enlarge the integration limits of (3. r21 = 25 . usually with a linear frequency scale around fvco . • N → Nmin ⇒ α → αmax : a decrease in σϕ with respect to the evaluation with a constant N.22) The output spectrum is plotted with logarithmic and linear scales. we search for the value of wolnpf with respect to (2π. 3.5 . or σϕ for the extreme gain cases. which optimizes σϕ over the gain range of (2. We present two options of simulation tools. It also helps to visualize the idea of a similar integral (area under the curve). 1 . or in other words closer to fi . are used in the calculation of σϕ .r21). r31 = 50 . In our example.21) without changing σϕ significantly. .
. with a total phase deviation under 1.8 Optimizing Total Phase Deviation Fig. (2.5 Figure 3.25 αnpf .r21)0.r21)0.r21)+0. This optimum σϕ performance is an important practical result for synthesizers generating lownoise carriers. (2.8° .5 αnpf . (2.Chapter 3 / Application Related Constraints 63 The curves from left to right correspond to the gain values: a) b) c) d) e) αnpf .r21)+0.8 shows that this set of noise performances of the PLL and VCO can accommodate a gain variation (αmax/αmin) of factor 50. (2.25 αnpf αnpf . 3.
In the scope of the rootlocus representation. In the numerical example treated above. The formal solution of the maximum flat point is found minimizing B(jw). In other cases with a much worse PLL phase noise performance. as the max{wn} is already near to wcp . for example a maximum peak or a minimum L(f) (absolute single side band phase noise) within a certain frequency offset range. is a rough estimation. Locked VCO output Spectrum min L (f)  fosc In this case. and a closed bandwidth well matched with fi . αmin αmax Figure 3.64 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops Other applications will demand different spectral purity parameters. we may deduce this maximum flat condition as the maximum ξ condition. The boundary we propose for the moment. and is not therefore very useful in our application. Therefore maximum flat spectra are obtained for values of α corresponding to 4 real roots (ξ=1). wolnpf >> (2π. which is similar to a Nyquist bandwidth for a discrete system with a sampling frequency fcp .9 Maximum SSB noise requirement The limitation of a maximum bandwidth appears when the PLL model includes the sampling of the phase detector. However. This issue is treated in chapter 5. mainly with α=αmax . where we need to accommodate rather large gain variations.5 . The criterion of minimal L(f) is also called maximum flat spectrum optimization. in the case of a large bandwidth we must pay attention to keep: wn / wcp < 0.fi) in order to have the PLL behaviour determining most of the spectrum around wn in all the gain range. comparing the algorithms of maximum PhM and maximum flat spectrum. it would not be possible to increase wolnpf as much as needed for an equilibrated minimum L(f) throughout the whole range of α. But the discussion is limited to a single gain value. Reference [Wong96] discusses this problem for 4th and 5th order PLLs. . it would be possible to apply this minimum L(f) criterion. we may use a very large feedback bandwidth .
αn. woln . i. it is a necessary and sufficient condition for all roots to have negative real parts. r31 ∈ R+ all the coefficients of the denominator are positive. depicted in the table below: s4 s3 s2 s1 1 r21 + r31 ⋅ woln r21 α r21 2 ⋅ woln ⋅ r31 ⋅ 1 − α n (r21 + r31 ) 2 α (r21 + r31 ) 3 woln ⋅ r31 ⋅ ⋅ 1 − α n r ⋅ r ⋅ (r + r ) − α ⋅ r 21 31 21 31 21 αn α r 4 woln ⋅ 31 ⋅ r21 α n Gain Stability Boundary 1 a1 b1 c1 s0 = 1 d1 Table 33 The criterion observes the coefficients of the system characteristics equation (expressed as a monic polynomial.e. but we need also to check the first column of the Routh array. Routh’s stability criterion may be used to evaluate this gain stability xv boundary.Chapter 3 / Application Related Constraints 65 3. r31 : r 1 + s ⋅ 21 woln B (s ) = α α N r α r 1 r +r s 4 ⋅ n ⋅ 4 21 + s 3 ⋅ n ⋅ 3 ⋅ 21 31 + s 2 ⋅ n ⋅ 221 α w α woln r31 oln α woln ⋅ r31 r + s ⋅ 21 + 1 woln For α .6 Gain Stability Boundary We end this chapter deriving one last practical feature that is emphasized by the rootlocus. it is a necessary condition for all the roots to have negative real parts. B(s) is rewritten as a function of αn. r21 . we observe a pair of complex roots crossing the imaginary axis for increasing gain values. woln . the coefficient of the higher order term equals 1) to compose two statements: having all coefficients positive. . In the rootlocus representation. having all elements of the 1st column of Routh array positive. . xv . It is the limiting gain value that implies system instability. r21 .
Next we combine b1lim with the gain recentering expression (2.66 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops Terms b1 and c1 may become negative for an increasing α α r +r < 21 31 = b1 lim αn r21 α r + r r + r < 21 31 ⋅ 1 − 21 31 = c1 lim αn r21 r21 ⋅ r31 α n factor. 2 3 .3 ⋅ 3 . so we may work with b1lim for simplicity. by using the minimum ratio r31/r21 indicated in chapter 2. 1+ 1 2 r +r α α αn = ⋅ < 21 31 α npf α n α npf r21 1 ⋅ r pf r21 1+ 1 2 r + r r31 = 21 31 ⋅ r21 r31 − r21 r21 We search to eliminate r31 in the expression above.4 ⋅ r21 10 25 → ∞ 2 ⋅ r21 = 15 . 1 min r pf ⇒ min r31 = 1.67 ) α npf 1+ 1 2 r21 α = max α npf A couple of numerical examples for given r21 values are listed in the table below. we have two signal changes in the column vector indicating two roots in the RHP. α max α npf 3 . to determine the maximum α/αnpf ratio.0 ⋅ 2 ⋅ r21 = 23 .6 r 21 1 ∴ min r pf 8 = 3 In this manner the maximum gain boundary is a function of a single parameter r21 . Thus for α α n > b1 lim . so that: α < 2.19). b1 > 0 ⇒ with c1lim < b1 lim c1 > 0 ⇒ The difference between c1lim and b1lim is rather small when r21 and r31 are much larger than 1.6 ⋅ r21 ⋅ (2. 3 2 ⋅ r21 → ∞ .
The PLL analysis tools from chapter 2 were largely employed. and examined the closed loop transfer of the inherent noise of the VCO. In this chapter we developed practical tools to evaluate the spurious rays. Finally. and to optimize the phase jitter in the ensemble VCO+PLL.αmax . we calculated the theoretical limits of the gain variation to give a practical numerical boundary for people facing the constraints of a synthesizer implementation. and we continued to discuss robust approaches taking in account the whole range of gain variation. We introduced the units to quantify the phase noise. the maximum stability values. which emphasizes the importance of choosing r21 in adequacy to the gain variation. . max (α/αnpf ). The closed and open loop bandwidths of the PLL were related to adjust the filter calculation to the requirement of a minimum phase jitter. are compared to the normalized maximum value αmax = 2 ⋅ r21 ⋅ α npf .Chapter 3 / Application Related Constraints 67 Table 34 Maximum Normalized Gain Variation In the table. ( ) The comparison shows that the stability boundary is achieved for α approaching 3.
68 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops .
................................................................................................................................................................................ Transfer functions table ................................... Numerical example.................................................................. In order to preserve the AC and noise specifications of the locked VCO...................3..2................................................................................... 80 4.............................................................................. 74 4........................................................ 79 4.......................10 Figure 4..................... 85 Figures: Figure 4............. 82 Amplifier noise.................................................3 Figure 4............................... 73 Loop rootlocus with active filter................................................................................11 Active Loop Filter ........................... 83 Filter components noise ....................4...................... 72 Active Filter AC model .................. 70 4........2.......8 Figure 4...........2................................Chapter 4 / Active Loop Filters: AC & disturbances issues 69 Contents: 4............................................................ 83 4...5.................................................................................................................. ................................. we must include the amplifier AC characteristics in the loop transfer functions...................................................2........ 83 Noise simulation scheme ... 86 Tables: Table 41 Table 42 Table 43 Table 44 Fully 3rd order passive filter: ∆PhM and ∆GM .... Nonideal Filter Impedance .................................... 80 4.....1.....................................6......................................................................... 82 4...................... 78 Disturbances transfer functions................ 72 Active Filter example: Phase Margin degradation...1........................................................ Active Loop Filters: AC & disturbances issues 69 4.........6...................................... Disturbances and Noise Propagation ......1.....6 Figure 4................ Summary of AC boundaries for filter design................................................................................................................... 79 Supply disturbances.. Filter Component Noises ............................ 87 4 Active Loop Filters: AC & disturbances issues Quite often PLL synthesizers drive VCOs with a tuning range higher than the PLL supply voltage...............................................................4..............5 Figure 4.......2......................................... Amplifier with single dominant pole................1................................................................................... Random Electrical Noise ... and examine the propagation of its intrinsic noise sources.......................................5.............................................................................................. 85 Noise simulation results ........................................................................... Fully 3rd order passive filter...........................................................2...........................1... 77 Amplifier Input Impedance X Filter Impedance .......................................................................................................................................2 Figure 4............2.................................... 71 4............ 76 4....................3..............................1......................... In these cases the filter impedance is associated with a transconductance amplifier supporting the desired DC range at its output............................................... Simulation Example ......................9 Figure 4.....................................1 Figure 4................................ 72 4..............1.........................................7 Figure 4.. Input impedance: Zin ...................2......................................................................................................................... 84 Noise sources voltage spectrum density ............ Supply Disturbances . Amplifier AC characteristics ...............1.........1..........................................................................4 Figure 4...... 84 4...... 70 Fully 3rd order passive filter impedance......................................... 81 4......................................... Amplifier Noise .........................................................................2.. 75 gm Influence in Open Loop Transfers........................... 82 4...............
Vdc_high Zs R1 Rpu C1 C2 Icp Z3 R3 C3 Vref Vtune Figure 4. starting to descend from the system approach to the level of circuit implementation. Ideally for a very high input impedance. the amplifier characteristics are invisible in the AC transfer: Vtune/Icp . and need to be checked and included in the loop transfer. The amplifier is a transconductor with a high input impedance and a current output transformed in voltage by the pullup resistor. and pullup resistor. thermal and flicker) are discussed in both theoretical and practical approaches. In a less ideal context.1. 4. the AC characteristics of the amplifier are relevant. In this chapter we also continue the analysis of the noise in the VCO spectrum. Rpu . The example of deterministic sources (that are transmitted by parasitic coupling) and the example of electrical random noise sources (shot. The passive elements are still responsible for the leadlag and postfilter of ZF(s) . transconductance gain (gm).70 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops This chapter introduces the first nonideal aspects of the AC model of the PLL. that are caused by a nonideal loop amplifier. we study the limitations of the linear model with respect to the maximum feedback bandwidth and the maximum comparison frequency for the PLL. Later in chapter 5. and the input node connected to the charge pump output is held around the DC value Vref . which was presented in chapter 2. . we look at the changes in the filtering function.4.1 Nonideal Filter Impedance Let us consider the active inverting loop filter represented in figure 4. mainly for large bandwidth filters.1 Active Loop Filter The filter configuration above is quite classical in tuner applications. Here. as represented in figure 2. The study of the active filter gives us an appropriate example to look at noise sources in the level of circuit description.
being optimized for matching and noise properties). including first the transconductance and Rpu effects. we reexamine the transfer of the equivalent passive filter without the approximation: Z3>>Zs. and k the ratio R3/R1 . i In the sketch above Vdchigh would then be equal to Vcc for the PLL circuit biasing.1) → C1 >> C 2 >> C 3 R1 << R 3 ≈ Z F (s) For r21>>1 and r31 ≥ (1. choosing an active or passive filter configuration is a compromise between the reduced DC constraints and the AC issues related to the amplifier.Chapter 4 / Active Loop Filters: AC & disturbances issues 71 In addition. . Generally. In order to keep a comparative insight between the passive and active configurations. So the amplifier input should be sensitive within the whole DC functioning range of the charge pump output. So we may identify the necessary assumptions to approach the simplified factorable denominator. a decreasing k causes wp2n to approach wz1 and wp3n to move away from wp2 . while keeping the tuning range close to the maximum: from ground to supply voltage. A numerical example shows us the dependency of the nonzero poles position with respect to the R3/R1 ratio. to assure loop stability. This fully 3rd order filter transfer has a denominator which is not completely factorable as equation (2.1. In this chapter we study these AC issues. Let us call wp2n and wp3n . Z F 3 (s) = (1 + s ⋅ T z 1 ) V tune = I cp s ⋅ C 1 ⋅ (1 + s ⋅ T p 2 ) ⋅ (1 + s ⋅ T p 3 ) + s ⋅ C 3 ⋅ (1 + s ⋅ T z 1 ) (4. such as modifications in the filter transfer and transmission or addition of disturbances and noise sources. In these cases the amplifier is implemented to reduce DC constraints on the charge pump output (that can work in a reduced range. which was simplified in chapter 2 by the approximation: fp3 >> fp2 . Nevertheless. the nonzero poles of the equation (4.1 Fully 3rd order passive filter i Before we start introducing the parameters that are specific to the active filter. starting with nonideal effects in the filter impedance. 4.6). the input node voltage may vary significantly during acquisition intervals. with a first order (single dominant pole for gm) analytical and numerical example.r21 . the two conditional statements above may be resumed by: R3 >> R1 .1).5). Secondly the influence of the input impedance is analyzed and the suggested ensemble of boundaries is summarized. Sometimes active filters are also used in loops with an equal tuning range and supply voltage. Next we discuss the AC model of the amplifier. we start with the nonideal fully 3rd order transfer for the passive configuration.
In the next sections the amplifier AC characteristics are included.2 Amplifier AC characteristics The AC equivalent circuit for the active filter. the magnitude plot is rather insensitive to k changes.3.70 1.46 0. discussed in chapter 2.32 0. We consider Zo >> Rpu .2 Fully 3rd order passive filter impedance Looking at the open loop Bode plot.903 ∆Gm (dB) +7. a slight increase in peaking and decrease of wpeak is noticed. and a series output impedance Rpu .21 Table 41 Fully 3rd order passive filter: ∆PhM and ∆GM Bode plots of B(jw) show that only for high gain values. These considerations set us a 1st AC boundary to be taken into account during the calculation of the loop filter components. setting additional boundaries with respect to Rpu . Some numerical values for r=25 and r31=50 are listed in the table below.70 k = R3/R1 ¼ 1 4 wp2n / wp2 0.36 +2.Rpu . ∆PhM (°) 11. but the phase curve will change causing a decrease in PhM.50 +0. As a practical conclusion we can keep in mind that passive filters should work with R3 ≥ R1 .1. and an increase in the frequency corresponding to the gain margin. Gm. with the amplifier represented by its input impedance Zin . with gain gv=gm. ii . gm and the amplifier poles and input impedance (Zin).34 1. with α approaching αmax . A larger wCG with an unchanged monotonously decreasing H(jw) implies an increase in the gain margin. transconductance gm and output parallel impedance Zo . which is usually true for our application context. as the ratio k decreases. The representation as a voltage controlled amplifier may be useful in certain simulation software containing amplifier models with Thevenin equivalent outputs. but if needed we may ii easily replace Rpu by the parallel impedance Zopu in the expressions derived below. as a condition to correctly estimate the full 3rd order transfer by its factored version.72 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops ∠H(jw) [°] fp2 fz1 fp3 log( f ) [Hz] with ZF(s) with ZF3(s) 90° 180° 270° Figure 4.83 wp3n / wp3 3. wCG . The amplifier output as a current source may be seen as the Norton equivalent of a voltage gain amplifier. 4.60 0.8 3. is pictured in figure 4.
1 gm − Z s ( s ) ≈ 1 + s ⋅ Tp3 Z Fa ( s ) → with gm ⋅ R pu >> 1 gm ⋅ R pu R3 >> 1 → ≈ − Z F (s) with gm >> 1 Zs (s) The first conditions just affect the postfilter pole with respect to the amplifier voltage gain.gm . with a low frequency value Gmo. we present first the transfer of an active filter with an ideal infinite Zin . .3 Active Filter AC model For the sake of clarity. We suppose that the overall transconductance has an LPF behaviour. and poles represented by the polynomial DG(s) . The active filter transfer. and w ’p 3 < w p 3 General conditions may be imposed over gm to approach ZFa(s) to ZF(s). plus a transconductor amplifying stage. and look at the influence of gm and Rpu .vin Zo vM Z3u R3 C3 Vtune Rpu Figure 4.2) R pu ⋅ (1 + s ⋅ T p 3 ) 1 T p 3 = C 3 ⋅ R3 = w p3 1 ’ T p 3 = C 3 ⋅ (R 3 + R pu ) = w ’ p3 with Z 3u = (1 + s ⋅ T ) ’ p3 . The second condition is more hermetic since the poles of gm and the zeros of Zs will be mixed in the numerator polynomial. Simple and usual loop amplifiers are composed of a high impedance voltage follower and DClevel shifter. ZFa(s).Chapter 4 / Active Loop Filters: AC & disturbances issues 73 Zs Icp vin Zin gm. We will now include frequency dependent aspects in the amplifier transconductance. The dominant poles are either from the follower or the transconductance stage. becomes: 1 gm − Z s ( s ) 1 R + s ⋅ C3 ⋅ ⋅ 3 + 1 + R3 gm R pu Z Fa ( s ) = 1 (1 − gm ⋅ Z s ( s ) ) ⋅ = Z 3u ( s ) ⋅ (1 + gm ⋅ Z 3 u ( s ) ) (1 + s ⋅ T p 3 ) 1 + 1 gm ⋅ R pu (4. gv=Rpu.
There will also be additional poles in the LHP. In order to have some qualitative understanding to better analyze the simulation results.3) suggests that at least one zero will appear in the RHP. the suppression of the comparison frequency component.3) We can preview the order of the ZFa(s) numerator and denominator with respect to ms . for a gm with a single dominant pole. N (s) Z s (s) = s Ds ( s ) with ns > ms .3) for ZFa . Finally. Ns(s) and Ds(s). . we verify the following changes in the denominator: R an extrapole is added at w ≈ wa ⋅ Gvo ⋅ 1 + 3 . ns and ng . equation (4. R pu the position of the postfilter pole is a bit changed. which affects for example. ZFa(s) can be rewritten using: order {N s ( s )} = ms . D ( s ) ⋅ Ds ( s ) − N s (s) − G Gmo Z Fa ( s ) = DG ( s ) ⋅ 1 + s ⋅ T p’3 + (1 + s ⋅ T p 3 ) Ds ( s ) ⋅ Gmo ⋅ R pu ( ) (4.3 Amplifier with single dominant pole An example is presented below for a simple amplifier model with a single dominant pole at wa. we develop a first order analytical case. and compare to the passive filter ZF(s). The transconductance and voltage gain become: gm = Gmo 1+ s wa and gv = Gmo ⋅ R pu Gvo = s 1+ 1+ s wa wa Replacing this 1st order gm in equation (4. 4. L order {Ds ( s )} = ns order {DG ( s )} = n g Gmo gm = DG ( s ) .1. Both the RHP zero and LHP poles will contribute to decrease stability margins. Besides. order {Z Fa ( s )} = ng + ns n g + ns + 1 ∴ for s = jw ⇒ lim Z Fa ( w) = w→ ∞ k for k = cst w order {Z F ( s )} = ms k’ ∴ for s = jw ⇒ lim Z Fa ( w) = n +1− m w→ ∞ ns + 1 ws s for k ’ = cst ZFa(s) order indicates that the gm poles are reducing the filter attenuation for high frequencies.74 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops The leadlag filter part is also split in numerator and denominator polynoms.
The numerator of equation (4. in order to visualize both: closein zeros and poles from the passive elements. which is normally found in positive feedback cases. . In our example. the numerator receives two extrazeros.3) is detailed below for the single pole gm.Chapter 4 / Active Loop Filters: AC & disturbances issues 75 For wa and Gvo kept within reasonable bounds (wa≥wp3 and Gvo≥10) the influence in the denominator is rather small. the zero from the leadlag impedance (Zs) is quite sensitive to the product R1.Gmo. and. which causes an inversion in the H(s) signal for large gain values. In the rootlocus sketch we may verify that the two zeros at low frequencies are specially relevant to system stability. farther ones introduced by the active device. this branch appears because of the RHP zero. one of which is in the RHP. In addition. On the other hand.4) Root Locus fz1 f’z1 Im{s} fp3 fp2 fz2 Re{s} High frequency additional zero and pole Figure 4.4 . Distances are compacted as they run away from the origin. As we commented previously. most of the changes in the frequency behaviour of the active transfer are due to the additional zeros.4 Loop rootlocus with active filter This rootlocus present an asymptotic branch running towards +∞. The corresponding iii rootlocus is sketched in figure 4. with a characteristic equation like: 1H(s) . iii The scale of this rootlocus is not linear. N s ( s ) = (1 + s ⋅ Tz1 ) Ds ( s ) = s ⋅ C1 ⋅ (1 + s ⋅ T p 2 ) DG ( s ) = 1 + s wa num {Z Fa ( s )} = N s ( s ) − DG ( s ) ⋅ Ds ( s ) s ⋅ C1 = (1 + s ⋅ Tz1 ) − Gmo Gmo ⋅ (1 + s ⋅ T p 2 ) ⋅ 1 + s wa (4.
equal to 22 kΩ. iv Equation (2.4 Numerical example We may visualize the influence of the new zeros of ZFa(s) and the accuracy of the w’z1 and wz2 estimates through a numerical example.5) We notice that the two zeros are related to the product Gmo. We can consider two frequency intervals to derive approximate values for the two lowest magnitude zeros: w’z1 and wz2 . The second (wz2) is the zero added in the RHP. r31=50. Figure 4. Gmo and wa tending to infinite). but its position depends on the Gmo value. we search simplified expressions for the zeros indicated in the rootlocus. Icp=200 µA. Fvco=1.4 kΩ. and R3 is chosen to be equal to Rpu . 4. A reference case is calculated for an ideal amplifier (with Zin . The reference case is equivalent to –ZF(s) .…). and it is better to keep some design flexibility by assuring a high Gmo value.R1 . we should remember iv that R1 is chosen with respect to the PLL bandwidth and gain (woln and αn ). optimized noise transfer.R1 . r21=25.1. A typical tuner application value is assumed for Rpu . The resulting R1 value is 4.5 GHz. However the choice of woln is limited by many other criteria (spurious suppression. 1 num {Z Fa ( s )} ≈ 1 + s ’ = 1 + s ⋅ C 1 ⋅ R1 − w z1 Gmo • for wp2 10 << w << wa ∧ w p 2 << wa ⇒ 2 C1 ⋅ T p 2 s ⋅ Gmo = 1 + s ⋅ T − C1 num {Z Fa ( s )} ≈ 1 + s ’ ⋅ 1 − s z1 wz 2 wz1 Gmo and for ’ w z1 << w z 2 : w z 2 = w p 2 ⋅ (Gmo ⋅ R1 − 1) (4. ⋅ 1 + s num {Z Fa ( s )} ≈ 1 + s ’ ⋅ 1 − s wz 2 wz3 w z1 • for w z1 << w << w p 2 10 ∧ w << w a ⇒ and Gmo ⋅ R1 ’ w z 1 = w z1 ⋅ Gmo ⋅ R − 1 1 ∴ ’ w z1 < w z 2 < w z 3 .5 is calculated for a narrow band filter with the following parameters: folnpf=10 kHz.76 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops In order to better understand the changes in the ZFa numerator ( with respect to Ns ). may imply changing woln . Kvco=100 MHz/V. Therefore keeping a large enough Gmo. for: Fcp=1 MHz. The first (w’z1) is close to the leadlag zero from Ns . limitation with respect to discrete system nature.12) repeated here for convenience: R = w oln 1 αn . . However.
Chapter 4 / Active Loop Filters: AC & disturbances issues 77 Curve a) corresponds to the ideal factorable transfer ZF(s) . c b d a a b c d Figure 4. Curve d) is an estimation of case c) using expressions (4. the transfer of a charge pump current disturbance divided by Kϕ .5) for w’z1 and wz2 . which represents the transfer of a phase disturbance at fcp injected at the reference input. Curve b) and c) are ZFa(s) with wa=wp3 and two different values of Gmo.r21) gain variation.5 gm Influence in Open Loop Transfers v A phase margin loss and a decrease in reference suppression is visible in cases b and c. loop magnitude is significantly smaller than 1 for f=fcp : H (w cp ) ≈ N So we call reference attenuation N ⋅ H (w cp ) . Normally the reference suppression is calculated with the closed loop frequency response. B(s) . but since the open B (w cp ) . v . or equivalently. becoming quite restrictive in c) where we may no longer work with a (2.
R1 is still large.5). If we take the same parameters in the above example.4 13. The table below brings PhM and reference transfer values for the above curves. the w’z1 estimation is correct enough to evaluate the parameter r’21 . The zero frequencies. which is represented by curve d). with low Vtune values and high current output in the amplifier. or in other words. w’z and wz2 are evaluated by equations (4.78 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops ’ We can define r21 = wp2 ’ w z1 . is calculated replacing wz1 by w’z1 and adding wz2 over an ideal transfer ZF(s). case Gmo*R1 θo θi a) ZF(s) →∞ 16. Nevertheless. The parameter r’21 equals 23 for this large bandwidth example. αmax . we notice that low values for the product Gmo. vi θo θo = θ i ( w cp ) I ChP (w cp ) Kϕ = B (w cp )≈ H (w cp ) dB + 20 ⋅ log N The high gain situation.5 9. For cases where the overall vii . The estimation of ZFa(s). with Gmo=10/Rpu . Since the PhM loss becomes worse for wol close to wp2 . but for higher frequencies the absence of the additional zeropole pair deviates the estimate from the real ZFa(s) curve. like in case c).8 Active Filter example: Phase Margin degradation In this narrow band filter example. we get a bigger R1 value. The approximation is fairly accurate up to wp2 . the product Gmo.4 b) ZFa(s) with Gmo=25/Rpu 5 +8. on the loop bandwidth and gain.2 39. which corresponds to the beginning of the frequency band. and small N.9 c) ZFa(s) with Gmo=10/Rpu 2 +12. So we need to identify the worst case situation and verify the stability boundaries for this case.8 62.2 33. to avoid additional constraints on the bandwidth choice. equal to 22 kΩ. happens for large Kvco . even for low gm values.05 55. We remark that in cases b) and c) the reference injection is no longer attenuated. In this case. The reference injection was vi evaluated in terms of phase disturbance.72 [dB ] PhM(folnpf) [°] PhM(folnpf*r21) [°] r21 or r’21 Table 42 25 20. and no important degradation is observed in the filter transimpedance. It is important to remember that the Gmo value varies along the output DC range. we must avoid having the lowest Gmo vii values for α tending to αmax .R 1. Thus the requirements for the amplifier transconductance depend on the R1 value. but recalculate it for a larger bandwidth filter with folnpf=50 kHz.6 17. which compared to r21 gives an overall idea of the PhM loss. Once more we repeat that a flexible amplifier design should assure an important Gmo value. may degrade significantly the filter transfer.
The pole wa is very determining for the position of the additional high frequency zero and pole. AC simulations are necessary to check the gm for the whole amplifier (with the input stage) in different points of the DC working range. The sketch below represents the impedance magnitudes: Zs . wa . Z Fai ( s ) = Z 3 u ⋅ (1 − gm ⋅ Z s ) Z s + Z 3u Z in + (1 + gm ⋅ Z 3 u ) ⋅ 1 (1 + s ⋅ T p 3 ) (4. Zin and gm is implied.5 Input impedance: Zin We will mention one last AC characteristics of the amplifier: its input impedance. In order to approach ZFai to ZFa we impose a boundary for Zin : Zin >> Zs + Z3u . .Chapter 4 / Active Loop Filters: AC & disturbances issues 79 Finally we may identify a practical boundary for the transconductance pole.6 Amplifier Input Impedance X Filter Impedance wi1 = 1 R pu ⋅ C in . Often we search for a Zin with an infinite DCimpedance. Nevertheless. and R1 and Zin respectively.1. if w i1 > 1 = w ’p 3 C 3 ⋅ (R 3 + R pu ) ⇒ Z in > Z 3 u for w ≤ w p3 transconductance is directly proportional to the output stage current. It also slightly affects the RHP zero. Zin .2). Z3u and Zin . Thus. Figure 4. 4. but we may analyze Cin constraint for a general unknown R3 . Z3u . its position concerns mainly the spurious attenuation. having a minor role for the PhM loss. but it has almost no drift over w’z1 . In this case Zin can be represented as an equivalent input capacitor Cin . this αmax situation corresponds to a high Gmo value. which may be approached by a MOS gate input. wz2 . Z(jw) Zin(w) Rpu Z3u(w) Zs(w) R1 wz1 wp2 w p3 ’ In this figure we suppose R3≈ Rpu and R1 < Rpu .The filter transfer including Zin is named ZFai(s) and can be compared to the first form of ZFa(s) in (4. R1 and Rpu .6) The indication of frequency dependency (F(s)=F) for Zs . for wa larger than wp3 . w [rad/sec] wp3 wi1 wi2 Let us define wi1 and wi2 as the intersection frequencies of Rpu and Zin .
during the calculation of ZF3(s) .6 Summary of AC boundaries for filter design An outline of all the boundaries proposed in this section : C1 >> C 2 >> C 3 >> C in R1 << R3 for Z F 3 ( s) → Z F ( s) (full 3 rd order denominator compared with factored approximation) and for Z Fai ( s ) → Z Fa ( s ) ( negligible input impedance for active filter amplifier) wa ≥ w p3 Gmo ⋅ R pu ≥ 10 Gmo ⋅ R1 > 5 for Z Fa ( s ) → Z F ( s) (active filter transfer compared with passive one) 4. 4. The supply disturbance is shown as a deterministic AC signal source. . and for an unknown R3. and uncorrelated noise sources are added in viii L(foffset ) for frequencies out of the PLL bandwidth is ideally equivalent to the freerunning VCO behaviour. analogue to an AC model. with an equivalent Laplace form.1.80 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops Hence keeping Zin >> Z3u for a maximum frequency higher than wp3 . Vd(s) . It was already suggested. Another degradation caused by active filters is the transmission of disturbances injected in the IC internal supply nodes. A simplified representation. filter passive elements are already bringing some extra baseband noise that is frequency modulated by the VCO. which allows us to reduce the Zin restriction to: Cin<<C3 . implies: Cin << C3 wi2 = 1 R 1 ⋅ C in . is applied for the noise sources. viii worsening the expected phase noise performance.2 Disturbances and Noise Propagation The amplifier noise is sometimes visible in the outofloop zone of the locked spectrum. if wi2 > w p2 = 1 R1 ⋅ C 2 ⇒ Z in > Z s for ∀ w So for Zin >> Zs we must choose Cin << C2 . but in practice. The noise sources are replaced by independent AC sources. We may quantify these effects seeking the AC transfer of noise and disturbance sources present in the active filter model. vd(t). to work with C2>>C3 .
60. V ( jw ) ∆f ∆f The thermal noise is associated to resistors. Shot noise is encountered in any conducting junction. A short revision on electrical noise sources and notations follows below. The notation adopted is in the form of unitary impedance power densities. expressed in current or 2 voltage terms: I ( jw ) 2 . The frequency domain representations for (ini )2 and (vni )2 are the classical power densities for electrical noise (thermal. shot. Kf reflects the quality of the interfaces between diffusion layers.…). shot and flicker noise. and a low Kf is associated with mature. and k is the Boltzmann constant: 1. We take the freedom to define the noise transfers in Laplace transform. . the current of a diode or bipolar transistor (base or collector). is: I n2 = K ∆f f ⋅ α IB f β 2 A rms Hz . but we must remember that noise transfers are just defined for power magnitudes. The statistical theory allowing such a treatment is shortly discussed in chapter 6. in Kelvin.38.1019 C . base current in a bipolar transistor. α and β are process dependent parameters.C/K .2. The shot noise associated with ID . 4. Hence a transfer F(s) for a noise source replaces the power transfer of the noise PSD. . is: I n2 = 2 ⋅q ⋅ ID ∆f 2 A rms Hz with q the charge of the electron in coulombs: 1.1 Random Electrical Noise We consider restrictively the most common types of electrical noise: thermal. Kf . which is actually represented by F(jw)2 . commonly determined through measurements. flicker. and well controlled processes. and we define small signal sources ini and vni representing component i noise in a current or voltage form. and flicker noise is associated to active devices.Chapter 4 / Active Loop Filters: AC & disturbances issues 81 power magnitude. α and β have values around one. The flicker noise associated with IB . where.1023 V. V n2 = 4 ⋅ k ⋅ T ⋅R ∆f 2 V rms Hz K I n2 = V n2 R2 T is the absolute temperature. The same notation used for AC sources is adopted for the noise sources. Typically. and has the following current or voltage representation: I n2 4 ⋅ k ⋅T = R ∆f 2 A rms Hz .
vin Zo vM vd Z3u R3 Vtune Rpu C3 The voltage source vd represents the disturbances found in the IC internal supply and ground nodes. Eventually in the active filter design we may interchange wp2 and wp3.8). . In passive filters. The source vd is almost directly transmitted to Vtune . Figure 4. placing the lower pole after the amplifier in order to improve vd rejection. An infinite Zo means that the output current variation due to vd is neglected: vd/Zo<< gm. Switching blocks working with very steep voltage slopes and clipped signals are a typical example of vd generating circuitry. which is typically high.3 Amplifier Noise It is opportune to evaluate and represent the amplifier noise by a current noise source at its output (ina in figure 4. being only filtered by the first order attenuation of the postfilter. Afterwards this current error is filtered by the whole ZF(s).82 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops 4.2 Supply Disturbances Zs Icp vin Zin gm. which roughly represents a 2nd order LPF with a lower cut frequency than wp3 . but it is not adapted to a variable .2. and the real PhM in ZF3(s) compared to the factored ZF(s) . The transfer function shown in table 43 is calculated for Zo and Zin→ ∞.7 Supply disturbances These disturbances can be RF current pulses either injected in the substrate or simply drained from the external supply causing a voltage drop difference (ddp) as they go through the connection path impedance.vd . The disturbance vd often arises as deterministic modulating tones at the oscillator input. First vd is transformed into a current error by the charge pump output impedance. working with large and steep swings is a good example. such disturbances are better attenuated. The usual noisy twoport representation with noise sources at the quadripole input is convenient for settings with a well known source and input impedance. This exchange should be checked in a numerical application to verify gm influence in wp2 placement.2. since they may inject quite some current in the substrate through the collectorsubstrate capacitors. The crystal oscillator for low noise PLLs. 4.
The gm poles also introduce an equal number of extra zeros and poles in the Vtune /Ina ratio . Rpu . R1 noise (In1.2. Furthermore the amplifier noise varies with respect to its output current. approximation of the amplifier input impedance).vin ina Zo vM vin Z3u The postfilter components are not explicitly drawn in figure 4. whose transfer to Vtune is quite similar to Vtune /Vd . placed in parallel to ina . Vn12 . They are the only noise sources common to both active and passive loop filters . The transfer function in table 43 is detailed for a gm with a single dominant pole. following the convenience of the transfer calculation. . 4..9 we add the noise sources from the filter resistors R1 and R3 .) is associated to the parallel R1//C2 impedance and transformed in its Thevenin equivalent.vin R3 vn3 vn12 Icp vin Zin Vtune Rpu vM V n 12 ( s ) = I n 1 ( s ) C3 R1 1 + s ⋅Tp2 Figure 4. R3 noise in its voltage form (vn3 ) is only filtered by the postfilter before emerging directly in Vtune . and filtered by the wp3 pole. Zs Icp Zin gm. thus the transfer Vtune /Inpu is identical to the function Vtune /Ina. may be symbolized by a current source inpu . Zs C1 C2 Zs in1 R1 gm.Chapter 4 / Active Loop Filters: AC & disturbances issues 83 source impedance (charge pump on or off) and a very large input impedance (approaching infinity.4 Filter Component Noises In figure 4. and this is more clearly depicted by a noise source in parallel to the output port.8 but as long as we calculate VM with a load impedance equal to Z3u .8 Amplifier noise The thermal noise of the pullup resistor.9 Filter components noise Resistors thermal noise is depicted either in current or voltage form. Vtune it is easily derived as: V tune 1 = VM 1 + s ⋅ Tp3 Figure 4. The amplifier noise appears in Vtune attenuated by the transconductance gm.
2.7 through 4. . These simplified expressions are also bounded by other conditions that are indicated in table 43 . The expressions of Z3u and the 1st order gm are recalled below. I n 3 = (1 + s ⋅ T p 3 ) Vn 3 Table 43 Disturbances transfer functions The above transfer functions are better illustrated by a simulation example developed in the following section.84 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops 4. Rpu noise: inpu ↔ Inpu(s) Filter components noise (R1): in1 ↔ In1(s) Filter components noise (R3): vn3 ↔ Vn3(s) 1 V tune Gmo ≈ (1 + s ⋅ T p 3 ) ⋅ 1 + I na Vtune gm ⋅ Z 3 u R1 = ⋅ (1 + gm ⋅ Z 3u ) (1 + s ⋅ T p 2 ) ⋅ (1 + s ⋅ T p 3 ) I n1 for w << w a ⋅ Gmo ⋅ Z 3 u V tune R1 ≈ (1 + s ⋅ T p 2 )⋅ (1 + s ⋅ T p 3 ) I n1 Vtune Vt R3 1 = (1 + s ⋅ T p 3 ) . with the approximation: Zin → ∞ and Zo >> Rpu .5 Transfer functions table The following transfer functions were evaluated for the AC models in figures 4.9. gm = Gmo 1 + s wa . The general expressions using variables gm and Z3u are further specified for the particular gm case with a single dominant pole. Z 3u = R pu ⋅ (1 + s ⋅ T p 3 ) (1 + s ⋅ T ) ’ p3 with : w ’p 3 < w p 3 Signal Internal supply disturbances: vd(t) ↔ Vd(s) Transfer to Vtune V tune gm ⋅ Z 3u 1 = ⋅ (1 + gm ⋅ Z 3u ) (1 + s ⋅ T p 3 ) Vd V tune Z 3u = (1 + s ⋅ T p 3 ) ⋅ (1 + gm ⋅ Z 3 u ) I na V tune V = tune I na I npu Specific pratical approach for a 1st order gm for w << w a ⋅ Gmo ⋅ Z 3 u V tune 1 ≈ Vd 1 + s ⋅ T p3 for Gmo ⋅ Z 3 u >> 1 s 1 + wa s Gmo ⋅ Z 3 u ⋅ w a Amplifier noise: ina ↔ Ina(s) Pull up resistor.
Chapter 4 / Active Loop Filters: AC & disturbances issues 85 4.24mA 68pF IC blocks vcc Loop Amplifier Input Stage Bias block Zin Gm Stage gm.10 Noise simulation scheme . αn = 6.9kHz. These numerical values are close to a satellite application. and the larger the resistor the smaller the equivalent current noise generator. The passive components are chosen for the following zero. poles and open gain values: fz1 = 1. fp3 = 106kHz . fp2 = 48kHz.10 and 4. Vdc_high 30 V 10kΩ 22kΩ Rbiasin 10MΩ 8. The DCoperating point is fixed by a voltage source with a high series impedance. Besides. Zs and the postfilter.7 V Idc 1. Rbiasin has a negligible effect on the total output noise for the plotted frequency range (10Hz to 1GHz).2nF Vtune 330pF 22kΩ Vbiasin 1.5kHz. The transfer for the thermal noise of Rd is equivalent to the transfer of Vd (a supply disturbance). Rbiasin . with an integrated amplifier and external passive components for R pu . like the one shown in the Bode plots of figure 3. r21 = 25 . A small resistor value was chosen to avoid significant DC disturbances. Rbiasin noise contribution at Vtune appears as a current source filtered by Zs and Z3u . with: foln = 9. However we should remember that this thermal noise is a broadband source with a rather small amplitude in our numerical application. A large source impedance is necessary to avoid interfering in the filter AC transfer within the frequency range containing the zeros and poles of interest.6 Simulation Example Figures 4. For a 10MΩ resistor.11 present the scheme and results of an AC noise simulation for an active filter.vin 5V gnd IC internal ground Rd 1Ω Figure 4.2.5. Rd thermal noise symbolizes an AC disturbance between the internal and external grounds.
86 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops The analog simulator models thermal. total Vn. V ( jw ) ∆f ∆f The resistors have intrinsic thermal noise and the current in the transistors of the amplifier contribute with shot and flicker noise components. The amplifier noise in our example (Vna1_total) is dominated by the gm stage. open collector output transistor. The notation Vni stands for the noise voltage contribution of element i. .11 shows the voltage noise density at the Vtune output. Vn1 and Vn3 for the resistors Rd . Vna is for the amplifier noise. (Vna1_ib and Vna1_fn respectively).11 Noise simulation results The simulation shows an overall filter noise dominated by the postfilter resistor. Vnpu. and Vnd. R1 and R3 respectively. Rpu . . Vnvco [Hz] Figure 4. in the form of unitary 2 2 impedance power densities ( I ( jw ) ). in dBV/Hz units. which is quite often a commonemiter. In the plot below this transistor base current shot and flicker contributions are explained. except for low frequencies. Figure 4. R3 . where the gmtransistor flicker noise becomes important. and the separated contributions of the noise sources whose transfer we identified in table 43 . shot and flicker noise sources.
vnfilter .11 by a dashed line.3) ). After the addition of the filter noise contribution.129n 19. R3 : 22kΩ R1 : 10kΩ v nvco ∆f 0. . below f p3 . Let us call the overall filter noise contribution. Since the PLL closed loop bandwidth will usually vary between fz1 and fp2 frequencies. it is most likely that some extra outofloop noise will be visible up to an octave after fp3. R Rd : 1Ω Rpu . a voltage noise appearing at the VCO input is bandpass filtered.11 with the vnvco of a satellite VCO.1n 12. with: 2 vnvco = 2 ⋅ 10 −16 ∆f 2 Vrms Hz L (100 kHz ) = − 100 dBc / Hz Kvco = 100 MHz / V ⇒ . still keeping in mind the boundaries discussed in section 4. with a central frequency close to the PLL closed loop bandwidth.1. vna : 2 2 2 vna = vnvco + vnfilter The closed loop transfer of vnvco to the output spectrum was named Bvco(s) . at the VCO input (eq. and the total voltage noise at the oscillator input. or with respect to the filter poles. and figure 3. and how much or how far the outofloop ix behaviour deteriorated. Hence the value of R3 may be changed to improve this outofloop performance. and also an empirical approach for the phase detector discrete behaviour influence in the PLL noise. In fact the different noise contributions correspond quite accurately to the simplified transfer expressions in table 43. highlights the fp2 pole position.2 we saw the representation of the oscillator freerunning intrinsic behaviour as a voltage noise source. (3. we need to verify that the v na components are still sufficiently supressed in the inloop range.12 sketched the output spectra for a flat (white) noise input. In chapter 7 a system level model is presented.6. which is visible as a filtering corner on the R1 noise contribution. vnvco = 14 n ∆f Vrms Hz or v2 10 ⋅ log nvco ∆f dBV = − 157 Hz The value of vnvco is indicated in figure 4. including the filter noise effects. vnvco . The numerical values below for the resistor noise sources help to verify this result. We may compare vnfilter of figure 4. We verify that the filter noise is dominant for frequencies below 100kHz. M1.Chapter 4 / Active Loop Filters: AC & disturbances issues 87 In section 3. and is added (in power magnitude) to vnvco . The overall filter noise appears as well at the VCO input.9n [ ] Vrms Hz 2 10 ⋅ log v nvco ∆f ( ) [ ] dBV Hz 197 154 158 Table 44 ix Noise sources voltage spectrum density It is convenient to simulate such effects with a base band PLL model. Basically. The marker trace.
Specifically. for low frequencies.88 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops The thermal noise sources are evaluated for a 300K temperature. these evaluations indicate the tradeoff between passive and active filtering solutions. . this source impedance is the charge pump output impedance. This situation well suits the approximation of Zin → ∞ . or a 4kT=1. as assumed in the expressions in table 43. In addition we introduced noise considerations that start to relate system specifications to a circuit implementation. a Rpu noise represented as a voltage source is attenuated by the amplifier gain: Gvo=Gmo. The difference in Rpu and R3 noise contributions at the Vtune output. The amplifier design used in this simulation has effectively a capacitive input impedance. the noise of the loop filter is mostly influent in the outofloop zone of the VCO spectrum. the charge pump is mostly off. thus its noise level is compared to the inherent noise sources of the VCO. A similar effect is observed for a decreasing source impedance (Rbiasin). with an equivalent Cin much smaller than C3 in the postfilter. This chapter developed analytical and practical approaches to deal with AC characteristics of active loop filters. Furthermore for cases with an equal tuning and biasing range. which has a variable value depending on whether it is conducting (on) or not (off). Thus the transfers from table 43 are a valuable reference to understand and explore simulation results for the loop amplifier design.Rpu .3).66. Actually. and it does present a rather high impedance.1020 VC . In a complete PLL. shows quite clearly the amplifier feedback rejection of Inpu and Ina (as discussed in 4.2. For cases with a lower Zin the transfers are modified and part of Vd and Vn12 appear as current disturbances filtered by Zs . The practical boundaries and simplified transfer expressions provide the means to evaluate and specify the design of the loop amplifier. For a PLL in locked mode.
........................................ 107 Convergence approaches X gain variation ................6 Figure 5........................................................ 96 5................ Limitations of the LTI Phase Model 89 5........ Phase approach ....................... The sampler ...........................4.. 111 5..........2............... 109 5.............................................. 103 Phase approach convergence criterion ....................... 96 Convergence towards lock: phase deviation sequence.................................................................. 114 Frequency and Time response for the continuous + delay model ..... 108 Discrete model for digital blocks ................. Frequency approach.................9 Figure 5.................15 Figure 5...................4.........10 Figure 5. 100 5................. DC range limitations..11 Figure 5...............................................................13 Figure 5.............................................1.................... 94 5.............2....................... 104 Comparing frequency and phase approaches.............. The holder...1......................................................... 109 5................................2..............................................3............ 91 Maximum Phase Detection Range & Cycle slips .... Loop filter time domain response ...........1......7 Figure 5.. 114 Figures: Figure 5.................................................................. Numerical examples and design considerations .... Threestate comparator: frequency and phase detector .. design and stability constraints will appear to limit the values of both fol and fcp .1.....4........................................................ 105 Convergence approaches X leadlag spacing r21 ................................................. 112 Continuous equivalent with transmission delay ..... but they can be evaluated and/or added with additional considerations..........................................................................3 Figure 5.......................................................3............. 111 Charge Pump DAC output ................8 Figure 5........................................................................................ Lock convergence approaches ........ As the PLL bandwidth increases the comparison frequency needs to increase as well to keep the system stable......................12 Figure 5.............. These limitations are not contained in the LTI model discussed so far.....2................................................................................. 99 Frequency approach convergence criterion ........................5 Figure 5................................................................................................................................ 93 Loop Filter: time response for current pulses ............................................................................................................................... Minimum phase deviation range . 94 Time response through normalized functions ...................................3.................................................4. demand increasing bandwidths in PLL synthesizers................................................................................ and even more integrated oscillator architectures............................................................................16 Phasedetector & Charge Pump transfer.................. In fact................................2............................................... 110 Discrete phase detector input: ∆ϕn ........................................... 103 5.....................3................ 91 5...........................................14 Figure 5..................... ......1 Figure 5...................1................................. Discrete transfers for the PLL Phase Model.................3.............2...........................................3..........1. 94 5.............................................. 115 5 Limitations of the LTI Phase Model Phase noise constraints......... Continuous equivalent with transmission delay ......... 92 Condition for unlimited frequency tracking range..............................2 Figure 5..................... 99 5.........................................Chapter 5 / Limitations of the LTI Phase Model 89 Contents: 5............................. Comparing the frequency and phase approaches.................................... 105 5...........................................4 Figure 5.............................. 92 5..............................................
In other words. as linear continuous elements. A couple of characteristics of the acquisition mode. can only appear by including discrete characteristics in the loop model. associated to poor noise performance oscillators. which is not a steady mode where the PLL can be used as a frequency synthesizer.90 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops The limit for maximum feedback bandwidth. that we modeled so far. The time domain expressions are also used to consider problems related to reduced DC tuning ranges. The ensemble of limitations above have nonlinear characteristics that can either be included in the LTI model. phase detector and dividers. A nice discussion of pulling time and pulling range may be found in reference [Wola91] for different types of phase detectors. i. The second introduces time delay compensations into the frequency domain phase model. the convergence towards a locked mode. We also saw (section 3. for fcl/fcp. The first three sections deal with the PLL acquisition mode. The first comes from a time domain model. and we need to verify how the loop parameters influence the acquisition. Multiloop configurations are an architectural solution to the limitations of the feedback bandwidth. examining the loop convergence from acquisition to lock mode. Nevertheless. and to the timing for the programming of the different circuits in a receiver. as far as the validity bounds of this representation are known. and to two quantitative approaches for lock convergence in the phase detection range. In this chapter we develop two approaches to evaluate maximum bandwidth stability conditions. such as locking time and maximum phase change for a certain step (closely related to the rising time). They are mostly encountered for fully integrated oscillators working with large bandwidth PLLs and a tuning range equal to the circuit supply voltage. The sampled nature of the PLL is connected to the digital blocks. or evaluated to mark its validity boundaries. was already mentioned in chapter 3. Here we limit our scope to a qualitative understanding of the threestate phase detector in its frequency detector range. may be specified by constraints that are related to the functioning of the demodulator.5) that spectrum optimization in the basis of a minimum L(f) criteria may encounter limitations bound to the maximum feedback bandwidth. after every change in the PLL programming the loop passes through an outoflock interval. The acquisition or tracking mode is formally treated in the de/modulators and in the clock/carrier recovery contexts. the limit for the threestate comparator as a frequency and phase detector. making an analogy to Nyquist bandwidths for sampled systems. The threshold bandwidth determines a limit for single loop configurations. . we may see design constraints reducing the linear portion of the phase detector/charge pump transfer.e. Therefore the stability boundary. through compensations. However. In frequency synthesizers we are concerned about the minimum linear range necessary to guarantee an unlimited frequency tracking behaviour. multiloop configurations tend to work with at least one wide band loop at high comparison frequency. Nevertheless these characteristics may also be derived from the linear model. fcl/fcp . and in this case..
the phase differences. when the oscillator frequency approaches the programmed value.1 this is represented by the grey i dotted line. and we will call this functioning mode. In this case. This behaviour is assured by a monotonously increasing or decreasing average charge injected in the loop filter. for input signals with different frequencies the average current over several periods is proportional to the frequency difference. In figure 5.1 Phasedetector & Charge Pump transfer After some time. If the two input signals are not at the same frequency. Iaverage [A] Icp 4π 2π 0 2π 4π ∆ϕ [rad] Icp Figure 5.2π). will oscillate between positive and negative values.. and a lagging oscillator. over several periods. i. is representing the average current over one comparison period. injecting current in the loop filter impedance. with low frequency difference: the phase detection trapping zone.2π). and it is easier to talk about an accumulated charge over several periods. the divider is late with respect to the reference and the charge pump is sourcing. i The dotted curve is slightly shifted to the right of 2π just for a better visualisation. Therefore it is difficult to talk about a frequency difference. we realize that our transfer function. . with n ∈ N.5. i.e. Iaverage/∆ϕ. or an average current. Hence. The phase detector slips are periodical with a rate corresponding to the frequency difference. for input signals with a positive or negative frequency difference.Chapter 5 / Limitations of the LTI Phase Model 91 5. the phase difference will periodically exceed 2π and the phase detector will slip to a new linear part of the transfer curve starting at (n. proportionally to the charges stored in the loop capacitors. The phase detector works as a frequency deviation detector. However.e. minus (n. Let us suppose a passive filter PLL. The oscillator approaches lock. and. in the PLL. The figure below helps us to understand the idea of this average charge.3 the tristate phase detector has an unlimited tracking range.1 Threestate comparator: frequency and phase detector As mentioned in section 1. the oscillator frequency is changing continuously with respect to V tune .
output Var. reset τrst Figure 5. the loop is capable of tracking any frequency difference inside the oscillator tunable range. Thus. Once we recognize that the frequency correction depends on the average charge. for a PLL in acquisition interval. showing only a limited slew rate for the charge pump outputs. and significantly reduces the phase deviation input range.3.fcp). switching on time.1 Minimum phase deviation range A subsequent question arises for loops working with high comparison frequencies. that would still enable us to guarantee a monotonously changing charge.92 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops For the phase detector transfer sketched above. with the same signal as the input frequency delta. These limitations are related to the width of the reset interval.1. the reset delay is introduced to avoid the deadzone problem. the average charge derivative has the same sign as the frequency difference. current sources. where the charge pump reset delay (τrst) becomes comparable to Tcp. input Main div. output Ref. The reset command and the divider outputs are assumed as faster logic stages with a much higher slew rate. as far as the oscillator frequency is not equal to (N. As discussed in section 1.5. 5.2 sketches possible inputs and outputs of a phasedetector/chargepump block.Detector Ref. Tcp In the Ph. we may consider which limitations occur in the transfer. Iaverage/∆ϕ. and its width is related to the charge pump.input Charge Pump Sourcing & Sinking currents And + delay asynchr. and they define a maximum comparison frequency for our tristate comparator.2 Maximum Phase Detection Range & Cycle slips . Figure 5. The drawing is simplified.div. In this example the reset delay (τrst) is almost half of the comparison period (Tcp).
over a cycle slip. Thus we confirm the boundary proposed by the average charge approach.2) This degressive sequence can only be obtained. The current output after this cycle slip.(1−τrst/Τcp). After some cycles the VCO is again in advance and the charge pump current starts sinking out charges from the loop filter. fcp is limited to: 1 f cp < (5. representing the phase deviation of the nth comparison period. and consequently the next phase deviation is measured with respect to the reference input. may be represented in the transfer function Iaverage/∆ϕin . Otherwise the module of the phase deviation would increase after each cycle slip. the transfer is not linear up to ± 2π. Let us consider a discrete variable ∆ϕn . Close to lock the phase deviation sequence should decrease towards zero: ∆ϕ n +1 < ∆ϕ n (5. The resulting transfer is shown in figure 5. in reality. increases Vtune and further accelerates the VCO. The reset delay is large enough to hide the following front of the variable input. but only up to ± 2π.3 for rst = Tcp 2 Iaverage [A] ∆Q = 0 Icp Icp/2 4π 3π 2π π 0 2π 4π 0 π 2π ∆ϕ [rad] ∆Q > 0 0 2π Icp/2 Icp ∆ϕ > π Figure 5. The VCO is initially at a good frequency but it has a phase advance of ∆ϕ1 . These cycle slips. Therefore to guarantee an unlimited frequency tracking range. 1 τ . .2 shows a VCO varying towards lock. if the linear portion of the transfer covers the range [π .1) 2 ⋅ τ rst Another way to derive the minimum range of the linear portion.3 Condition for unlimited frequency tracking range We observe that τrst equals Tcp/2. is the limiting value for which the accumulated charge has the same sign as the derivative of the phase difference.Chapter 5 / Limitations of the LTI Phase Model 93 Figure 5. avoiding the convergence towards the lock condition. They appear as a decrease in the linear portion. due to the finite reset window. The phase detector has slipped one cycle. is to seek a convergence condition for the phase deviation values. +π ].
2. 5. we continue to analyze other limitations of the linear model. Icp i(t) C1 R1 Zs vM(t) C2 vM(0) 0 Td Tcp i(t) vM(t) t (s) Figure 5. and compared to the VCO tunable range.4 Loop Filter: time response for current pulses . The comparison inform us about limiting bandwidth values to avoid bouncing up and down with Vtune deviations as big as the VCO tuning range. In fact the cycle slip causes the inversion of the charge pump current with respect to the previous comparison interval.1 Loop filter time domain response We use the Laplace inverse transform to evaluate the loop filter response for a current pulse input. Comments about 1st and 3rd order filters are made to extend the present results to these other cases. 5. but the resulting expressions are shorter and the physical meaning is more easily understood. A 2nd order filter is chosen. The minimum phase deviation range stated above will be used in the convergence analysis to limit the phase detection zone. with amplitude Icp and width Td .2 DC range limitations In figure 5.94 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops Next. because it already contains the leadlag characteristics of the 3rd order filter. This effect may be quantified as a Vtune deviation. before the oscillators attain a locked condition.2 we saw that reducing the linear portion of the phase detector transfer causes some extra “frequency bouncing”. related to the limited DC tuning range. and in the numerical examples of Vtune deviations due to cycle slips.
Reference [Gard80] discuss an approach of maximum PLL bandwidth. The charge pump output impedance and the VCO input impedance are considered very high. ∆vM(Tcp/2) should be expressed as a function of foln and fcp . R) . and rewrite the Vtune deviation as a function of x and r21. Tcp]. and it would depend on the ddp difference between vM and vout at t = Td . for a loop working with a low fcp. through the analysis of discrete transfer functions. A 3rd order filter (like in figure 2.3) where . named phase detector ripple in reference [Gard80]. T d ] ∧ Td = T cp 2 : T cp ∆v M 2 T = v M cp − v M (0 ) 2 T cp ∆v M 2 = I cp ⋅ R1 − Tcp T cp (2 ⋅T p 2 ) ⋅ + 1 − e 2 ⋅ T z1 Since we look for maximum bandwidth boundaries. T p 2 = R1 ⋅ C 2 The expression for vM(t) in the discharging interval. with an amplitude equal to: (Icp . and equivalent Vtune deviation. this interval equals an average deviation within the phase trapping zone. v C 1 ( 0) ≈ v M (0) Roughly. has to be inferior to the VCO input range. ii This variation term. [Td . Let us define the bandwidth ratio. though C1 discharge is not visible within Tcp . We choose Td = Tcp/2 as the injection interval. this interval is equivalent to the worst phase deviation that can occur after a cycle slip.Chapter 5 / Limitations of the LTI Phase Model 95 − t t T 0 ≤ t ≤ Td : v M (t ) = v M (0) + I cp ⋅ R1 ⋅ + 1 − e p 2 T z1 −Td Td −(t −Td ) T p 2 T T ≤ t ≤ T : v M (t ) = v C1 (Td ) + v C 2 (Td ) ⋅ e + 1 − e p 2 = v M (0) + I cp ⋅ R1 ⋅ cp d T z1 −( t −Td ) T p 2 ⋅e (5. the filter impedance is charged or discharged in a rate proportional to Icp. On the other hand. C1 discharge would have to be considered. So for a loop working with a large fcp. and when the charge pump is off a portion of Vtune discharges through the parallel R1C2 branch. T z1 = R 1 ⋅ C 1 . to be compared to the tunable range. The maximum Vtune variation happens during ±Icp injection. The second form assumes a C2 almost discharged at t=0: ⇒ . This interval of Tcp/2 is equivalent to phase deviations of ±π. for instance. when the charge pump is active. . A 1st order filter (single RC series branch) would present a stepwise variation in Vtune when Icp ii is turned off. So Vtune deviation is evaluated as ∆vM(Tcp/2) : t ∈ [0 . x. is written in two forms.4) would have an extra time constant appearing in the charge and discharge intervals.
0 and 1. and remembering: r21 = woln ⋅ Tz1 = 1 woln ⋅ T p 2 Tcp ∆v M 2 π = I cp ⋅ R1 ⋅ ⋅ x + 1 − exp − π ⋅ r21 ⋅ x = I cp ⋅ R1 ⋅ [g ( x. with Icp and R1 variables. r21) between two quadratic functions of x.96 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops x= f oln f cp with x ∈ [0.a and 5.5. and Kvco an average frequency sensitivity: Tcp ∆vM 2 2π ⋅ f osc f = ⋅ [x ⋅ g ( x .a fig. so for a system under definition (5.4) .b Figure 5. g(x.5 Time response through normalized functions 5. r21) varies between two linear functions. r21 ) ] ∆ f osc K vco (5.2. Expression (5.5. r21) are plotted for a constant r21 in figure 5. corresponding to the limiting values.5.b respectively.g(x. r21 ) ] r21 ( ) (5.g(x.5) The functions g(x.2 Numerical examples and design considerations . r21 ) ] = 2π ⋅ ∆ Vtune ⋅ osc ⋅ [x ⋅ g ( x . 5. r21) and x. 5.4) or for a Icp value corresponding to αn . For a given r21 .5. is useful in the analysis of a given synthesizer with fixed parameters and application components.5) is better suited. Still. of the exponential term. R1 and Icp are related to the loop bandwidth and gain. fig. 1] . and x.
21 x . In both cases a PLL bandwidth is evaluated for an average Vtune deviation equal to the tuning range. Sections 5. satellite synthesizer application. a sensitivity of 125 MHz/V corresponds to a maximum Kvco value.312 .Hz/V These values are again comparable to a bandL. The resulting foln is named DCthreshold bandwidth. Hence the ∆vM(Tcp/2) value is somewhat exaggerated and the DCthreshold bandwidth is a pessimistic estimation. Therefore ∆vM(Tcp/2) is an average Vtune deviation. The comparison frequency is not especially high.996)π. So for loops with a large DC range. 1 = 25. x = 0. 25 ) ] K vco x = 0 . we may expect that another limiting characteristic will determine the maximum foln . and our phase detector transfer should be linear up to ±(1. • Example II: What is the DCthreshold bandwidth for a LC oscillator with 28 V of tuning range? 2π ⋅ f osc ⋅ [x ⋅ g ( x . 25) = 1.5 GHz fcp = 1 MHz τrst = 2 ns r21 = 25 (1−τrst/Τcp) = 0.8 kHz .3 and 5.4) and (5. However practical experience shows that a bandwidth of 312 kHz for a loop with a 1MHz comparison frequency is rather unfeasible. • Example I: What are the values of the bandwidth ratio and ∆vM(Tcp/2) for a loop filter with R1 = 10kΩ and r21 =25 ? woln αn → f oln = 39.0398 .0398 .Chapter 5 / Limitations of the LTI Phase Model 97 Expressions (5. Let us consider three different situations with common values for the following parameters: • • • • • • Kvco = 125 MHz/V Icp = 300 µA fvco =1.4 discuss maximum bandwidth ratios through stability approaches. .5 k αn = 25 A. f oln = 312 kHz 28 V = For a satellite band LC oscillator. 1 = 3.998 N = 1.1 x R1 = Tcp ∆v M 2 = 3V ⋅ g (0. rather than an average one.47 V This narrow band filter situation may be compared to two specific oscillator contexts with different tuning ranges.5) are better perceived through numerical examples.
but for Vtune out of the working range the oscillator stays clipped to a maximum or minimum limit frequency.4 V of tuning range? 2π ⋅ f osc ⋅ [x ⋅ g ( x . we should verify the design limitations connected to the tuning range.98 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops • Example III: What is the DCthreshold bandwidth for an RC fully integrated oscillator with 3.4 V = In this example the resulting bandwidth is rather narrow. It appears as a Vtune transition that jumps up and down. . LCoscillators are usually limited by the varicap sensitivity curve. 25 ) ] K vco x = 0 . and the interface block between Vtune and the control parameter. large bandwidth PLLs. and often blocks some time in the limiting values. 1 = 15 . So far we treated the DC tuning range only as a given interval related to the VCO frequency range and sensibility. The combination of the VCO and the charge pump (or the amplifier) DC functioning ranges must be examined to avoid unstable situations. For Vtune values where the VCO input is no longer sensible (Kvco =0). This problem should be avoided by defining suitable DC functioning ranges for the charge pump output and the VCO input. and it shows a drawback for enlarging the PLL bandwidth under restrained tuning ranges. we may see an oscillating behaviour. before it attains lock. there is only a minimum Vtune . 066 . Thus the acquisition period may be longer than for a slower filter that would not block so often in the tuning range limits. the oscillator will stay clipped to the maximum or minimum achieved frequency. for the extreme values of the reachable range. Once we recognize the need to work with “bouncing” loops. Vtune is also the charge pump output voltage. presenting a degressive Kvco for an increasing Vtune. f oln = 66 kHz 3 . since the open loop gain is null. In an active filter the charge pump limitation is replaced by the loop amplifier limitation. for Vtune values where the charge pump may no longer deliver current but the VCO is still sensitive. and the behaviour of input and output blocks around Vtune . The resulting behaviour of loops larger than the DCthreshold bandwidth is also a “bouncing behaviour” during acquisition. corresponding to the output transistor saturation. For the moment let us suppose that all Vtune reachable values do not imply in an oscillating behaviour. In a passive filter. Generally. thus restricting the DC functioning range because of the output transistor saturation. 2 x . RC integrated oscillators often have a degraded phase noise performance and to optimize the overall spectrum. RCoscillators will depend on the control parameter. For instance if Vtune varies around this charge pump limit value. but its spectrum is no longer locked by the PLL. it is necessary to work with low noise. the output current varies in consequence and we may produce a sustainable oscillation. Nevertheless. for amplifiers with an open collector output. On the other hand.
Chapter 5 / Limitations of the LTI Phase Model
99
So, with more or less “bouncing” the oscillator is dragged towards lock, and now we need to verify the influence of the PLL bandwidth inside the phase detection trapping zone.
5.3 Lock convergence approaches
In the previous section, time domain expressions for Vtune sweep were derived, and compared to the tunable range. In this section we use these expressions to verify the convergence of the phase deviation sequence as the VCO reaches the programmed frequency. The phase deviation sequence, as introduced in equation (5.2), represents the discrete values of the phase difference for each comparison period.
n ⋅ Tcp ≤ t < (n + 1) ⋅ Tcp ∆ϕ n ∆ϕ n ∈
:
;
[− ϕ lim
, + ϕ lim ]
(5.6) with
π < ϕ lim < 2π
Let us consider the time diagram below showing the phase detector inputs and the charge pump outputs for a VCO in acquisition mode.
In the Ph.Detector
Ref. input ∆ϕ1 ∆ϕ2
Var.input
Charge Pump output current
Icp
Vtune
vM(0)
0
Td1
Tcp (Tcp–Td2)
t (s)
Figure 5.6
Convergence towards lock: phase deviation sequence
100
PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
The oscillator initially with a phase lag, ∆ϕ1, is accelerated through the interval Tcp , and in the following interval presents an advance of ∆ϕ2 . The loop reaction is very abrupt; thus the situation concerns a fast, large bandwidth filter. We fix an arbitrary time origin to simplify the time function expressions, and we represent only the net current output for the charge pump. The condition for a ∆ϕn sequence converging to 0, or a PLL tending to lock, may be applied to the phase deviations above, imposing: ∆ϕ 2 < ∆ϕ1 We define a stability limit for the PLL bandwidth as the maximum bandwidth for which this condition is fulfilled. The following subsections develop expressions for this maximum bandwidth in terms of the VCO frequency and phase variations. An initial condition is assumed for the VCO frequency in order to end up with an expression that is an independent of this variable. The VCO is assumed at the programmed frequency, N.fcp at t=0. Hence our phase deviation convergence is analyzed within a phase detector trapping zone. Section 5.1 showed that phase detectors with a minimum linear range of ±π, are able to track any frequency differences inside the tunable range. Furthermore, section 5.2 showed that fast filters have a high Vtune average deviation, which increases the probability of crossing the frequency programmed value several times. Therefore the initial condition proposed above is coherent with any synthesizer loop (with an unlimited tracking range) close to lock or crossing the target frequency during Vtune variations around the target value. 5.3.1 Frequency approach
Referring to figure 5.6, the stability limit is reached for a PLL bandwidth that implies: ∆ϕ 2 = ∆ϕ1 which means that the main divider counted N cycles of the oscillator signal between T d1 and (Tcp –Td2). Let us rename the limit delay, in phase and time, and relate it to the oscillator frequency, fosc : ∆ϕ 2 = ∆ϕ1 = ∆ϕ Td 1 = Td 2 = Td and ∆ϕ = 2π T ⋅ d T cp
(T
cp
− 2 ⋅ Td ) =
N f osc (Td )
(5.7)
Expression (5.7) supposes that the oscillator frequency does not vary within the interval Td , (Tcp − Td ) , or in other words, that Vtune is constant during the same interval.
[
]
Chapter 5 / Limitations of the LTI Phase Model
101
We call this approximation the frequency stability approach. Its inaccuracy depends on the loop filter discharge during the interval where the charge pump is off. The discharge would decrease Vtune , decrease fosc , and consequently increase the maximum stable PLL bandwidth. Hence, the frequency approach is pessimistic about the maximum bandwidth. The amplitude of C2 discharge increases accordingly to the PLL bandwidth, so a maximum bandwidth boundary is quite concerned about the discharging influence. It is easier to watch the oscillator changing frequency through its integral. So, a second approach in phase cycles is discussed in section 5.3.2. The phase stability criteria is expressed in terms of the oscillator phase, θosc :
θ osc (Tcp − Td ) − θ osc (Td ) = N ⋅ 2π
Our initial condition for the VCO is expressed as:
f osc (0 ) = N ⋅ f cp
(5.8) (5.9)
It may be combined with expressions (5.3), for the filter pulse response, to obtain a time function for the oscillator frequency:
f osc (t ) = f osc (0 ) + K vco ⋅ [vM (t ) − vM (0)] = f osc (0 ) + K vco ⋅ [∆vM (t )] − t t N ⋅ f cp + K vco ⋅ I cp ⋅ R1 ⋅ + 1 − e T p 2 Tz1 f osc (t ) = − Td − ( t − Td ) Tp 2 N ⋅ f + K ⋅ I ⋅ R ⋅ Td + 1 − e T p 2 ⋅ e cp vco cp 1 Tz1
: 0 ≤ t ≤ Td
: Td ≤ t ≤ (Tcp − Td )
iii
(5.10) As a result the frequency stability criterion becomes:
−Td T N T = f osc (Td ) = N ⋅ f cp + K vco ⋅ I cp ⋅ R1 ⋅ d + 1 − e p 2 (Tcp − 2 ⋅ Td ) T z1
It is convenient to define a time deviation, p, and make some substitutions to express the criterion in terms of x, r21 , α and p:
Once again the expression of the discharging interval assumes a C2 almost discharged at t=0; and in fact we approach this condition in two cases: • for fast filters with wp2 comparable to 2π.fcp ; • and for close to lock condition, with Td tending to zero. The phase deviation sequence towards lock is examined for large bandwidth filters, and for ∆ϕn tending to zero, so completely in accord with the supposition of a discharged C2.
iii
102 p=
PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Td ∆ϕ = f cp ⋅ Td = Tcp 2π
;
0 < p < 0.5
α 1 = 1 + ⋅ 2π ⋅ x ⋅ α (1 − 2 ⋅ p ) n
2π ⋅ x ⋅ p + 1 − exp − 2π r21 ⋅ x ⋅ p r21
(
)
or expressing this boundary as a function gfrap , we find:
g frap =
2p + 2 p −1
α ⋅ 2π ⋅ x ⋅ α n
2π ⋅ x ⋅ p + 1 − exp − 2π r21 ⋅ x ⋅ p r 21
(
) =0
(5.11)
remembering:
r21 = woln ⋅ Tz1 = R1 = x= woln αn ;
1 woln ⋅ Tp 2
;
α=
Icp ⋅ K vco N
(open loop gain)
α n (average gain value)
x ∈
f oln f cp
[0 , 1]
The value of x solving equation (5.11), is the limit bandwidth ratio for a given set of r 21 , p and α values. We know that the loop is considered in lock for p close to 0. Hence we need to verify that x tends to a finite, nonzero value for the limit p→0. First we look for some physical understanding of gfrap (limit function for the frequency approach), reducing it to a two variable function, and plotting it in the space (p, x, z). Figure 5.7 illustrates gfrap for constant values of r21 and α, and zooms around the valid ranges of p and x: r21 = 25 ; α = α n ; x ∈ [0 ; 1] ; p ∈ [0 ; 0,5 ] The surface gfrap(p, x) is cut by the plane z=0, and we may observe that x tends to a finite value (around 0.1) for p tending to 0. The influence of the other two variables, r21 and α, is examined in section 5.3.3, including a comparison of the frequency and phase approaches.
and evaluate the phase change during the spotted interval: [ Td .12) Comparing (5.8) .2 Phase approach The phase criterion as presented in equation (5. r21 and α.8) may also be expressed as a function of p.7 Frequency approach convergence criterion 5. (Tcp −Td ) θ osc (Tcp − Td ) = θ osc (Td ) + 2π ⋅ N ⋅ f cp ⋅ (Tcp − 2 ⋅ Td ) + K vco ⋅ ∫ ∆v M (t ) dt Td (5. We obtain a time function for the oscillator phase.10). x. integrating equation (5. (Tcp –Td) ].12) and (5. gphap .Chapter 5 / Limitations of the LTI Phase Model 103 Figure 5. The calculation steps for the phase approach limit function. are indicated below.3. gives the function below: T − (Tcp − 2Td ) − d Td (T − 2T ) − T 1 − e T p 2 e Tp 2 − 1 N 2π = 2π N f cp (Tcp − 2Td ) + K vco I cp R1 d p2 Tz1 cp .
104
PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
Dividing by 2π.N , and using the same substitutions as for gfrap , gphap becomes: g phap = −2 p + 1 α 2 α ⋅ (2πx ) p (1 − 2 p ) + 1 − exp − 2π r21 ⋅ px ⋅ 1 − exp − 2π r21 ⋅ (1 − 2 p )x r21 n (5.13) A general idea of gphap(p, x, r21, α) is given by figure 5.8, showing gphap for fixed values of r21 and α, and restricted ranges of x and p: r21 = 25 ; α = α n ; x ∈ [0 ; 1] ; p ∈ [0 ; 0.5 ]
{
[
(
)] [
(
)] } = 0
The intersection with the plane, z=0, shows a finite valued x (around 0.25) as p tends to 0.
Figure 5.8
Phase approach convergence criterion
As expected, the limit bandwidth ratio for the phase approach is higher than for the frequency approach. The difference accounts for the filter discharge during the interval where the charge pump is off. Hence, effectively the frequency approach is pessimistic, but the phase approach is a final stability boundary. And in order to guarantee loop stability, including several variable parameters, it is necessary to have a safety margin. The following section contains comparative graphs between the two approaches, and graphs showing the influence of the two variables fixed in figures 5.7 and 5.8, r21 and α .
Chapter 5 / Limitations of the LTI Phase Model
105
5.3.3
Comparing the frequency and phase approaches
A better graphical insight of the stability boundary, shown in the tridimensional plots, is given by figure 5.9. It illustrates the intersection lines between gfrap , gphap and z=0. We choose to inverse the bandwidth ratio and plot 1/x (fcp/foln) values with respect to p (normalized delay). Therefore the frequency approach indicates a maximum PLL open loop bandwidth of approximately fcp/10 , and the phase approach of approximately fcp/4 . Although the lock condition is achieved for p tending to zero, the limit of maximum bandwidth has to satisfy all values of the p range to guarantee a converging phase deviation sequence. For our case, this condition is naturally fulfilled since the stability curves present a minimum value of x, or a maximum value of 1/x, as p tends to zero.
Figure 5.9
Comparing frequency and phase approaches
Before introducing the two missing variables, r21 and α/αn , we may compare the expressions gfrap(p, x) and gphap(p, x) to get some insight into their differences. We observe that gphap has a higher order than gfrap , with respect to p, because of the time integration. A reduced form, as a limited development, may be helpful to homogenize both equations and simplify the comparison. The first order limited developments with respect to p, around p=0 (lock point), is evaluated for gphap and gfrap .
106
PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
g frap
p →0
64 744 4f 8 1 α 2 + r21 ≈ −2 p + ⋅ (2π x) ⋅ p α r21 n
1 1 − exp − 2π x r21 α 2 ≈ −2 p + ⋅ (2π x ) ⋅ p + α 2π x n r21 444442444443 1 4 4
Ap
A
(5.14)
g phap
[
(
)]
p →0
(5.15)
In this form we verify that both functions are very similar, and the only differing term would be equivalent to an approximation, in gphap , of the exponential by its first order series around x=0. However for large bandwidth filters, x is not close to 0, and the difference between the linear and the exponential terms is representing the filter discharge, whose time constant depends on x and r21 . The sum terms, Af and Ap, correspond to the voltage variations of C1 and C2 for current injection intervals (Td) tending to zero. Capacitor C1 variation is equally considered in both approaches, and capacitor C2 discharge is neglected in gfrap. It is important to notice in (5.14), that for the usual r21 values (r21>>1), C2 voltage variation is the dominant effect in ∆vM. 5.3.3.1 ZeroPole spacing ( r21 ) Next we verify the influence of the filter zeropole spacing parameter, r21 . Figure 5.10 plots the limit bandwidth values (1/x) for a variable zeropole spacing and p equals to and ε close to 0 (p=ε , ε = 1012). We notice that for decreasing values of r21 , the two limiting values (gfrap =0 and gphap =0) approach each other. This result is in accordance with equations (5.14) and (5.15), since the differing term decreases as r21 is reduced. The limiting bandwidth variation with respect to r21 , may be intuitively understood for the frequency approach. In fact, reducing r21 implies nearing fz1 and fp2 to foln ,i.e., for the same bandwidth (foln) and the gain value (α) C1 is reduced and C2 is increased. iv Hence, for the same charge injection (Icp.Td), the voltage variation in Vtune is decreased, and the bandwidth limit value (foln ) increased. In the phase approach it is harder to foresee a general idea of the sensibility to r21 . This happens because ∆vM is a function of both r21 and x.
iv
Remembering that C2 variation is dominant as p tends to zero.
Chapter 5 / Limitations of the LTI Phase Model
107
Figure 5.10
Convergence approaches X leadlag spacing r21
5.3.3.2 Gain variation Finally the gain variation influence is shown in figure 5.11. It is a plot of the limit bandwidth with respect to a normalized gain variation (α/αn ), for fixed p and r21 values. The plot is reproduced on two scales, loglinear, and loglog. In the first we can easily read the limit 1/x values for typical gain variations. For instance, the satellite tuner example discussed in section 3.5, has a gain range, αmax/αmin, equal to 50 (normalized variation for r21 = 25) ; centering this variation around αn in figure 5.11.a implies a maximum bandwidth value around fcp/19 . The plot on the loglog scale is superposed by two asymptotes in the form: log y = k1 ⋅ log x + k 2 L y = 10 k 2 ⋅ x k1 V\PEROV
(
)
The asymptotes are indicated by the lines in ◊ and
The limit bandwidth for the frequency approach may be very accurately represented by such an asymptote, with k1=0,5 . In fact k1 and k2 values could be directly estimated from equation (5.14), making gfrap equal to zero, and isolating 1/x as a function of α/αn and r21 .
a fig. . In fact. The influence of the zeropole spacing. in parallel to the frequency approach asymptote. However figure 5. 5. and the gain variation are also examined.11.75. bouncing between the low and high boundaries. that the discharge voltage delta is less and less significant.11.15) it is not easy to isolate x. this section (5. foln .11.b Figure 5. v The second asymptote shows that very high gain ratios correspond to such a large ∆vM during injection.11 Convergence approaches X gain variation Summarizing. v with k1=0. fig. such a small range oscillator will pass most of its acquisition period blocked in the low and high Vtune boundaries. The limiting bandwidth is discussed directly in terms of the center open loop bandwidth. the oscillator frequency can not vary as much as presented in figure 5. Thus we should keep in mind that α variations are an implicit manner of discussing open and closed loop variations around the center value. So as the bandwidth approaches the limits discussed above. used in the loop filter calculations.b. 5. shows that the graph can be approximated by two asymptotes. In the case of oscillators that work with small tuning ranges (fmax / fmin < 2). the oscillator will mostly stay blocked at the limit Vtune values.3) describes a lock convergence analysis to evaluate stability boundaries for the maximum bandwidth ratio (foln/fcp ). One around α/αn equal to one.108 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops In expression (5.6. It will only converge if there is a sequence of ∆ϕn values small enough to cause ∆vM inferior to the tuning range. and another for high gains. for the phase approach.
contains three digital blocks: main divider. In the previous chapters we discussed filter centering algorithms to optimize the output spectrum in lock mode. time variable. this section continues our analysis of the LTI model limitations. i. ws : • wcl < 20*ws : continuous model • 20*ws ≤ wcl < 10*ws : between the continuous and the pseudocontinuous model • 10*ws ≤ wcl < 2*ws : between the pseudocontinuous and the discrete model This section develops a pseudocontinuous approach for the PLL phase model and compares it to the stability boundaries found in section 5. is a linear time invariable approximation. wcl . reference divider and phase detector. and the sampling frequency. but mainly applied in the context of fully digital PLLs (see reference [Berg95]). includes extra poles or delays in vi the continuous linear model. as shown in figure 1.4 Discrete transfers for the PLL Phase Model The PLL synthesizer is typically a hybrid system containing both analog and digital blocks.1. the filtering is effective enough for all passing components in order to smooth out the input power and show an output with changing rates proportional to the control bandwidth. developing compensated transfer function for different phase detector types.1 The sampler As the system bandwidth increases it is necessary to consider the limitations associated with a finite sampling frequency. representing the stability constraints of the discrete system. 5. The basic architecture of the frequency synthesizer. So. The average model for the digital blocks.4. The linear representation of the analog blocks is also approximate because of the limited linear functioning range. concerning the system with a closed loop bandwidth. of their discrete. is also conceivable. examining the discrete.e. developing discrete time equations and the associated z transform transfers. As a general rule. vi . A direct discrete approach. Reference [Craw94] details the pseudocontinuous approach. time variable nature of the digital blocks. So far we have replaced the digital blocks by their average behaviour with respect to the phase of the input and output signals. These linear range limitations were discussed in section 5. A first approach. 5.3. In order to combine these two treatments we need to include the effects of the bandwidth limitation in the small signal model that is described in the frequency domain.. the following boundaries are suggested for the model choice.Chapter 5 / Limitations of the LTI Phase Model 109 The convergence criterion is issued from the acquisition mode as a condition to attain the lock mode. pseudocontinuous. functioning. The accuracy of average behaviour models hold for loops with a control bandwidth largely inferior to the sample frequency. and not to the sample frequency.9.
The output of the dividers is in fact one input transition that is selected by the count overload window and transmitted to the output.Tcp) Tcp +  ∆ϕ(t) Charge Pump Tcp θdiv (n.110 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops The charge pump is certainly driven by a digital input. . The dividers are fully or partially programmable counters that transmit an overload signal every counting cycle. limiting our model to the phase detection zone. the discrete model of the counter is a sampler with a period equivalent to the output signal frequency.Tcp) θdiv (t) %N θosc (t) θref (t) +  Tcp ∆ϕ(t) ∆ϕ (n. Td . with two memory nodes registering two inputs. of the two inputs. in a current injection Td wide.Tcp) Charge Pump θdiv (t) Figure 5.6). A simplified representation takes the reference input as the sampling frequency. but its output is a continuous current. Therefore. this would imply a nonconstant sampling period and a rather complex modeling.12 Discrete model for digital blocks vii The accuracy of the assumption of a synchronous resampling is limited to conditions close to lock. A constant sensitivity. The phase detector is another edge driven block.Tcp) ∆ϕ (n. The complete discrete representation of the phase detector should include the discontinuous effects of both edge driven inputs. and a delayed asynchronous reset. and the phase detector output becomes a sampled phase deviation sequence vii as depicted in expression (5. It drives two switchable current sources. better modeled as an analog signal. However. Kϕ . transforming the time difference. is also assumed for the phase detector. where the output of the main divider has a period approaching Tcp . Tcp Xosc θxtal (t) %R θref (t) θref (n.
(Tcp/2π) ∆ϕn+1 . sign and delay related to the phase deviation sequence.Tcp (n+1). In this case the sampled Laplace transform becomes: 1 ∆ϕ n (s ) = ⋅ ∆ϕ (s ) Tcp 5. therefore. hence we may condense these three samplers in the last one.Tcp Figure 5. The Laplace transform of the discrete and continuous phase deviations are related by: ∆ϕ n (s ) = 2π n 1 ∞ 1 ∞ = ⋅ ∑ ∆ϕ (s + n ⋅ wcp ) ⋅ ∑ ∆ϕ s + Tcp n =0 Tcp Tcp n = 0 (5. For the moment we consider the ∆ϕ portion due to the feedback signal. for short.16) for: and ∆ϕ (s ) = L{∆ϕ (t )} ∆ϕ n (n ⋅ Tcp ) = ∑ ∆ϕ (t ) ⋅ δ (t − n ⋅ Tcp ) n =0 ∞ (5. is a sequence of current pulses.4.13 Discrete phase detector input: ∆ϕn .Tcp) is designated as ∆ϕn . i(t). The discrete phase deviation ∆ϕ(n. Coherent resampling does not modify a discrete variable. with width.2 The holder The following step is to identify the DAC (digital to analog converter) nature of the charge pump.(Tcp/2π) For: Charge Pump output current Icp Icp i(t) ∆ϕn > 0 ∆ϕn+1 < 0 t (s) n. our discrete representation would contain two samplers driving a third one. In reality the output current. ∆ϕn . with the alias terms well outside the loop bandwidth.Chapter 5 / Limitations of the LTI Phase Model 111 The divider outputs are connected to the phase detector input. within the phase detector block. with all working at the same fcp frequency. In other words the reference and main divider outputs are coherently resampled by the phase detector latches.17) The alias terms due to the sampling will be analyzed in chapter 7.
ignoring the higher fcp harmonics is justified by the fact that they are strongly attenuated in the loop filter.Tcp n. the nonlinearity is a function of ∆ϕn . (∆ϕn . to a fixed known envelope. over one period.112 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops For the frequency domain model we search I(s).e. An exact representation of I(s) is quite difficult because the frequency content (amplitude. Furthermore. This supposition allows a worst case evaluation of the reference breakthrough. However this approximation contains no DC component. In section 3. locked context. We supposed that it was mostly concentrated in the 1st or fundamental harmonic. (∆ϕn . we looked for a second approximation that preserves the DC component and simplifies the frequency content. Consequently. iZOH(t).Tcp (n+1). Figure 5. phase and number of significant fcp harmonics needed to represent a period) depends on the pulse width. ∆ϕn Icp. In a periodic .(∆ϕn /2π) = Kϕ .Tcp/2π ) ) Icp. IZOH(w). of i(t). this envelope shapes a series of fcp harmonics.1. ∆ϕ IIcp cp t (s) t (s) Icp .Tcp ( 1) T (n+1). and thus is not suited to represent the viii bandbase contents of i(t).18) The baseband contents are present for every ∆ϕn different to zero. in the lock condition. the Laplace transform of i(t). . we made a first approximation about the leakage current frequency content. with the first lobe node at fcp .14 Charge Pump DAC output wcp 2wcp 3wcp with: Tcp wTcp I ZOH (w) = K ϕ ⋅ ∆ϕ n ⋅ Tcp ⋅ sinc 2 ⋅ exp − jw 2 viii (5.Tcp w (rad/s) 3wcp 2.14 shows a truncated portion. and the associated Fourier transform..Tcp/2π ) n. during the analysis of spurious rays. i. Representing the charge pump as a ZOH (zero order holder) converter is equivalent to shaping the pulse frequency content by a sinc envelope.wcp wcp Figure 5.∆ϕn .Tcp i(t) i ZOH(t) Fourier Transform  I ZOH(w)  Kϕ .
t < 0 with u(t) a step function defined as: and Gsh(s).18): Charge Pump ∆ϕ n = ∑ δ (t − nT ) ⋅ ∆ϕ (t ) n =0 cp ∞ iZOH (t ) = ∆ϕn ⋅ Kϕ ⋅ u (t − nTcp ) − u (t − (n + 1)Tcp ) [ ] 1 − e − s⋅Tcp G ChP − ZOH (s ) = K ϕ ⋅ = K ϕ ⋅ G sh (s ) s u (t ) = 1 . time variable. ix We notice that GChPZOH is independent of ∆ϕn . in section 6. The pseudocontinuous model is an extension of the bandbase. It includes some characteristics of the loop discrete functioning. xi GChPZOH is a linear transfer. The delay term appears in a Bode plot as a constant unitary magnitude. is deduced from equations (5. linear time invariable phase model. Thus it mostly affects the phase margin parameter.19) Equation (5. is discussed for small signal analysis. and a linear decreasing phase. and keeping only the DC ray. pulse width modulated by ∆ϕn .Chapter 5 / Limitations of the LTI Phase Model 113 The charge pump transfer. the sample and hold transfer in the Laplace transform. which is not the case for the transfer function of x the actual i(t). Hence. For example at f equals fcp/10 it reduces the phase margin of π/10 radians. replacing s by jw in the Gsh(s): T + s ⋅ cp 2 T cp − s⋅ 2 G sh (s ) = e x T cp − s⋅ 2 ⋅ e −e s → e s = jw T − jw ⋅ cp 2 T cp sin w ⋅ 2 ⋅2⋅ w For i(t) output in the form: the associated transfer GChP is: xi ∞ i (t ) = ∑ I cp ⋅u (t − nT cp ) n=0 ∆ ϕ n ⋅Tcp − s⋅ 2π I cp 1 − e G ChP (s ) = ⋅ s ∆ϕ n T cp ⋅ T cp ⋅ sinc w ⋅ 2 ∆ϕ n ⋅ Tcp − u t − n Tcp − 2π = e T − jw ⋅ cp 2 Later on. ix We may verify the correspondence of GChPZOH (s) and IZOH(w). t ≥ 0 u (t ) = 0 . In a periodic locked case. but it intends to stay as a LTI system. but the only time invariable component is the DC one. the sinc shaped charge pump transfer is reduced to its DC term plus the delay: G ChP − ZOH (s ) ≅ K ϕ ⋅ Tcp ⋅ e − s ⋅Tcp 2 (5. a more complete transfer. this reduction can be seen as the loop filter action.17) and (5. attenuating the spectrum rays at fcp harmonics. .3. or 18° . for the ZOH equivalent output.19) corresponds to a first order approximation of the ZOH.
and the phase decreases up to n*(180°) . fc/2): easy implementation.Tcp ( 1) T (n+1). We examine the open and closed loop transfers for a filter with r21 equals to 25. The magnitude frequency response is unitary everywhere. • A numerical example is presented below. we continue this analysis with the ZOH approach. Kϕ . The order. The related Fourier transform.r21). Ipw(w). Tcp/Tw1 i pw(t)  I pw(w)  Figure 5.3 Continuous equivalent with transmission delay We may recognize that other pulse approximations for i(t) would present similar LTI transfers. n. and charge pump transfer. In figure 5.15 we name ipw(t) a generic pulse function of width Tw and same DC content as i(t).4. . the ZOH presents the largest delay.15 Continuous equivalent with transmission delay G ChP − pw (s ) ≅ K ϕ ⋅ Tcp Tw ⋅ Tw ⋅ e − s ⋅Tw 2 Among the possible pulse approximations. Next we search convenient polynomial representations for the time delay. but not accurate in magnitude and phase. This time delay is associated to a charge pump transfer with width Tw equals to Tcp/2. The phase decreases almost linearly up to n*(90°) .114 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops 5.∆ϕn . and a normalized gain variation range (2. Pade polynomials: composed of pairs of zero and poles. Two simple possibilities are: • real pole at f=fcp/2 (similar to first order filtering around the Nyquist frequency. mainly for frequencies nearing fcp/2. comparable to a time delay of Tcp/4.Tcp 3wcp 2wcp wcp wcp 2wcp 3wcp w (rad/s) ∆ϕn . are also indicated. indicates the order of the numerator and denominator polynomials. Τw2 Τw1 Kϕ .Tcp t (s) n. GChPpw(s). At fcp/2 it represents a phase decrease of 45°. And since the time delay is the limiting stability constraint introduced by the pseudocontinuous model. Therefore the order of the polynomial must be chosen comparing the maximum loop bandwidth to(w*Tdelay) . symmetrically placed around the imaginary axis of the Splane.
b Figure 5.16.16. The numerical parameters used in the graphs. 5. and the closed loop step response for a continuous model with a transmission delay of Tcp/2 .a fig. Figure 5. 5. so that we can compare the results of the delay approach and the ∆ϕn convergence approach.16 Frequency and Time response for the continuous + delay model The phase response pictures three curves corresponding to the pure time delay. with a 2nd order loop filter. Over the 180° line there are symbols marking: wz1 (o).1 * woln = 211 rad/s c b a nominal + delay fig. are listed below: r21 = 25. Dasheddotted lines indicate the open loop crossing frequencies (fol) for the normalized gain variation. woln ( . The continuous nominal loop is a 3rd order one. the nominal continuous transfer and the continuous plus delay model. woln = 10 rad/s (symbolical value.Chapter 5 / Limitations of the LTI Phase Model 115 The zeropole spacing parameter (r21) is equal to the evaluation of figure 5. modeled by a 2nd order Pade polynomial.16 shows the open loop phase plot. not related to applications) wcp = 21.11.
wcp . Zp2 (x) and wcp (◊). Therefore we may compare the ratio wcp /woln to the limit 1/x values in figure 5. The sample frequency. . was chosen as the limit value for which the phase margin corresponding to the maximum normalized gain (αmax ) equals zero.11.
the Tcp/2 delay is too pessimistic. A compromise fitting measurements is found for a delayed model with a Tcp/4 delay. and the results will not fit measured situations. is a pessimistic estimate of the lock and acquisition mode. In the phase plot. where the phase margin loss may affect the peaking. The pessimistic error is not so large. In fact.07 ) K PhM (wol ) α =α wcp wo ln f cp f o ln 1 = L x ~ 19 21. during the acquisition mode there is not really a constant sampling frequency. w Ko ⋅ Vtune = osc N N ↔ B (s ) ⋅ ∆f ref N or B(s ) N1 ⋅ N1 N 2 The three curves correspond to the following gain values: or wol = wz1 = 2 rad/s = 2π.59 Hz) c: α≈αmax/2 or wol ≈ 3.32 Hz) a: α=αmin b: α=αn or wol = woln = 10 rad/s = 2π. Again when we use the maximum delay (Tcp/2) we are taking the worst case. and the signal plotted is proportional to either the oscillator angular frequency or the filter voltage output. Nevertheless we should be aware of the limitations to know the tendency of the inaccuracy present in the simulations results. and it may be used to evaluate stability boundaries due to enlarging feedback bandwidths. the corresponding fol is also indicated through the dasheddotted lines. so the most critical.(4. as we see through the comparison with the phase convergence method.116 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops α max = α n ⋅ 2 ⋅ r21 = α n ⋅ (7.(1. with a Tcp/2 delay.1 max = PhM (wp 2 ) = PhM (5 ⋅ wo ln ) : for the phase convergence method : for the continuous + worst delay method = So in spite of all reductive approximations made in the delay analysis. and this may interfere in the width of the current injection for cases where the oscillator is lagging the reference.woln = 30 rad/s = 2π. but fcp is the slowest one possible. and it constitutes a small addition to the safety margin. it is still comparable to the time convergence methods. Therefore the continuous plus delay model. Another application of this delayed model appears in spectrum optimizations. The continuous plus delay model is mostly an approximation for locked mode simulations.(0. The phase deviation is also not constant during each comparison interval. The step response is calculated for a frequency change equal to wosc/N.7 Hz) Curve c corresponds to the maximum gain value with a PhM≥30° for the continuous plus delay model. due to its linear character. . For this typical locked mode simulations.
and they impose maximum limits for fcp and fol . Thus. These aspects are bounded to large bandwidth loops. two characteristics are especially difficult to include in a Ztransform representation: a DAC not strictly linear and a varying sampling frequency. gain variation. with an additional time delay. The second (fol) appears in general loop structures containing discrete behavioural elements.Chapter 5 / Limitations of the LTI Phase Model 117 This chapter dealt with nonlinear aspects of the PLL functioning. and. The simplified frequency model is in fact a continuous one. In our mixed discretecontinuous context. where descriptions in Z transform are easily determined. Both time and frequency models were evaluated and discussed with respect to the loop parameters presented in the previous chapters. Most of the PLL discrete models are issued from pure digital loops analysis. we preferred to start with time domain models. The first issue (fcp) appears in multiloop contexts and it was analyzed through the minimum phase detection range assuring an unlimited frequency tracking behaviour. later search for a simplified frequency domain representation. (zeropole spacing. …) .
118 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops .
.. Angular modulation ..........................1...........................................2.................................................................................................................................................. The analysis starts with basic aspects on random noise representation and measurement............ 127 6..... 128 6............. Phase Noise Notations .......3..................................... Electrical Noise: random source representation & measurements................................1. 135 6.............. Phase Noise: theoretical to practical approach 119 6.................................................... 132 6 Phase Noise: theoretical to practical approach Phase noise is an important parameter in the performance of frequency synthesizers......1.......................1......................... 138 Tables: Table 61 Table 62 Phase Modulated Carrier ............ 133 6..................................................................... .....3 Figure 6.......... 120 6.... 136 Figures: Figure 6................ 129 Superposed Noise: AM + PM decomposition (spectrum)................................................................................. 133 Periodic transfer determined by a large signal...... Electrical noise as a random process ............................ Measuring Phase Noise ............ 124 FM & PM carriers ... we consider the transfer function of stages that work in a periodic...................3............................................. 136 Large Signal Transfer: ideal and hyperbolictangent limitations.......................2........8 Figure 6.................................................................................3................ 132 Slope approach: voltage & time deviations.................................................................9 Spectrum Analyzer Output .......................7 Figure 6..... 128 SSB superposed noise: AM + PM decomposition (phasor)..............6 Figure 6......................................... Linear Time Variable transfer .2...................5 Figure 6................................................................2................1................1......... Interchanging Modulation Types.......................................................................................... Phasor Notations................1.............1.............................................................. 135 6........................................1 Figure 6.............................. nonlinear mode..4 Figure 6............. Large Signal Linearization .......................................................................................................................... 130 Phase modulated carrier by DSB superposed noise ....... and relate them to the noise sources that are present in the circuit.......... Finally...............2.............................................................. 125 6......................... Low noise design needs to consider the mechanisms originating phase deviations in the output carrier.3.................................................2 Figure 6............................ 125 6..................................................... 121 6.........2....... 126 L(foffset) from modulated and superposed noise ...............................................................................Chapter 6 / Phase Noise: theoretical to practical approach 119 Contents: 6........................................ 123 6............................. and is followed by a discussion on different notations for phase noise............... Slope approach .......... Time and Frequency representation...............2...................... 131 Phase deviation from DSB sidebands ..2.............................
for stationary and cyclostationary sources. The representation of electrical random noise is shortly discussed. or are accumulated as their outputs propagate through the PLL blocks. the addition of signals represented by phasors. The power that generates phase variations can come from random or deterministic sources. Noise sources can be internal to the integrated circuit. and the time deviation in switching stages.1 Electrical Noise: random source representation & measurements The denomination noise is given to any power signal disturbing the data signal (which contains the transmitted data or information). 6. This description is further developed to take into account the nonlinear and periodic behaviour of these blocks. shot. The disturbances are either intrinsic to the periodic sources. The last one is very significant to describe the noise added by the logical blocks of the PLL (dividers and phase detector). On the other hand. The deterministic sources are also described in the frequency domain. The first is associated to deterministic signals polluting the output carrier. which are chosen with respect to the origin of the phase deviation. from the application environment. NPLL and vnvco (defined in chapter 3). In the PLL synthesizer we consider two sources of periodic signals. We mentioned two sources of interference in chapters 3 and 4: the reference breakthrough and the deterministic disturbances found in the supplies of the loopamplifier. Furthermore we consider that they are stationary noise sources that can be described by their power spectrum density. introducing the notation in the frequency domain. which are disturbed by phase noise: the reference oscillator and the voltage controlled oscillator. The noise performance of the synthesizer is investigated in a topdown approach. We consider two types of noise: interference and stochastic electrical noise. Phase variation can be caused by a linear phenomenon such as signal addition and also by nonlinear phenomena such as angular modulation. from behavioural to circuit level descriptions. In chapter 7 we relate the notations for phase noise and the transfer functions of the preceding chapters.120 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops Phase Noise is a convenient parameter to quantify unwanted phase variation in a periodic signal. and the shot and thermal noise of the amplifier and the loopfilter components (discussed in chapter 4). or external. are random noise sources. flicker and other types of random noise. We discuss some notations that are based on: the equivalence amongst different types of modulation. Phase noise is represented in many different notations. . or to the measurement tools. They are generated by the operation of different parts of the circuit and are transmitted by parasitic coupling. which allows us to develop a common treatment for both types of disturbance. implying fluctuations in voltage and current signals. The second refers to the random movement of electrons. They are thermal.
The mechanisms originating these fluctuations are related to thermal agitation. i Usually for the measurement intervals that we are interested in . and a finite value for the autocorrelation at the time origin. They do not present all the characteristics of a stationary process. This function describes the probabilistic distribution of the values of the sample functions. Ergodicity is a very important property for the measurement of stochastic processes. stochastic processes are not evaluated by a probability density function (which is not directly measurable) but more frequently by their first and second moments: mean value and autocorrelation. when they are observed at a given time instant. A stationary process X(t) presents the following mean and autocorrelation: mean: m X = Ε[ X (t )] autocorrelation: R X (τ ) = Ε[ X (t ) ⋅ X (t − τ )] where E is the expectation operator. the random process is said to be stationary. This is attributed to processes where the statistical properties of the ensemble can be estimated by time averages of individual sample functions of the process. The random characteristic defines a variable or a process that is not predictable before its occurrence. but still small enough to consider the process as stationary. and are described as stochastic or random processes. an autocorrelation which is independent of shifts in the time origin. In practice. tends to present a Gaussian distribution as the number of variables increases without limit. respectively. and to variations in the current flow of electronic devices. This is related to the central limit theorem. The statistical description of the process is contained in the probability density function. but presents defined statistical properties. and τ is a time delay. The meansquare value equals the autocorrelation for a zero time delay: meansquare: R X (0) = Ε X 2 (t ) [ ] A process that presents: a constant average.Chapter 6 / Phase Noise: theoretical to practical approach 121 6. since these measurements are based on the observation of a sample function during a time interval. but include the most significant. The Gaussian distribution is nicely adapted to describe physical phenomena depending on many independent random variables. as described by the 1st and 2nd moments.1. is said to be widesense stationary (WSS). When the probability density function is independent of the observation instant.1 Electrical noise as a random process Electrical noise arises from current and voltage fluctuations in the circuit. These fluctuations vary randomly. which affirms that the sum of many independent random variables with defined 1st and 2nd moments. . Each time function is a sample of the random process sample space. Random processes are defined as an ensemble of time functions whose statistical properties are described by a common probability rule. An important property is derived from the stationary condition: ergodicity. The sum of the different paths of the electrons in a conductor approaches a i Measurements in the time and frequency domain observe a signal during a time interval that is large enough to average over several periods of the noise components being measured. the electrical noise sources may be modeled as WSS processes with a Gaussian distribution of amplitude. Consider that the movement of each electron is described by an average component plus a ii random one.
the integral equals the total power for a unitary impedance. The thermal noise of a resistor of R ohms has the following mean square value expressed in volts: 2 Vn2 = Ε VTN (t ) = 2kT R ⋅ ∆f volts 2 (6. [ ] The Fourier transform of the autocorrelation function describes the random process in the frequency domain. The output of a block with a lineartimeinvariable transfer function H(f) for a noise input described by SX(f) becomes: SY ( f ) = H ( f ) ⋅ S X ( f ) 2 A process that presents a constant power spectrum density for all frequencies is called white. . When considering a voltage or current noise density. Shot and thermal noise are approximated by white Gaussian noise. In equation (6. are called cyclostationary. equals RX(0). White noise is a practical representation for band limited systems where the noise spectrum is constant over the relevant part of the frequency range. which is largely above the limit of our working frequencies.1) where ∆f indicates the bandwidth over which the noise voltage is measured. The width of the lobes of the sinc are inversely proportional to the filtering bandwidth. These approximations hold for limiting bandwidths to the order of 1012 Hz. for a spectrum with positive and negative frequencies.1) the multiplying factor 2 instead of 4 (as in equation (4. and in the case of shot noise the average component equals the net current flowing in the device. Bandlimited white noise presents an autocorrelation function shaped as a sinc curve.7) of chapter 4) refers to a double sided frequency representation. and equals zero everywhere else. This representation is limited to a minimum value of frequency. They are represented by the product of a normalized stationary ii In the case of thermal noise the average component equals zero. It means that any two samples from different time instants are completely uncorrelated. Ideal white noise corresponds to an autocorrelation function which is an impulse at τ=0 . Electrical noise contributions whose amplitude varies with respect to a periodic deterministic signal. to avoid an infinite power density as f approaches 0. which is the total power or the meansquare value. Flicker noise is commonly represented by a white Gaussian noise which is shaped by a 1/f filter. The power spectrum density of a WSS random process has similar properties to the PSD of deterministic signals. defined as: SX ( f ) = ∞ −∞ ∫ R (τ ) ⋅ exp(− j 2πfτ ) X X dτ or inversely R X (τ ) = ∞ −∞ ∫ S ( f ) ⋅ exp( j 2πfτ ) df We observe that the integral of the power spectral density over the whole frequency range. Thermal and shot noise present a Gaussian amplitude distribution and a zero mean value. It is the power spectral density (PSD) of the process. White noise with unlimited bandwidth does not exist because it would represent an infinite power.122 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops Gaussian random variable.
It is basically composed of a frequency conversion block. In the output of the VCO we find mainly phase deviations.3. These transfers are discussed in section 6. or in other words. The shot noise of a transistor driven by a periodic input is a cyclostationary noise. with a white unitary PSD which is limited by a physical bandwidth defined by the circuit.1. This supposition was first mentioned in chapter 3 when we considered a single tone contribution of vnvco . The time average of the noise power of a cyclostationary noise is proportional to the rms value of the periodic signal which modulates the random process. which is followed by a filter with a variable bandwidth and by a power meter. The random signal is considered as the superposition of uncorrelated portions of narrow band signals.2 discusses different mechanisms that convert noise power in amplitude and phase deviations. for example: It ⋅ [1 + cos(2πf ct + Θ )] 2 Θ is a random phase uniformly distributed in the range [0 .1 represents an LO spectrum measured with two different resolution bandwidths. It indicates that X(t) and i(t) are not related to a common time origin. We continue this introduction considering the measurement of noise in the time and frequency domain. .2 Measuring Phase Noise Phase noise is a magnitude measuring phase deviations in a carrier. Phase noise is measured by different methods which evaluate the performance of the carrier in the time and frequency domains.2) the amplitude of the shot noise also refers to a double sided spectrum with positive and negative frequencies. Figure 6.2) where X(t) is the normalized random process. by sweeping an analysis window through a specified range of frequency. In our context the spectrum analysis is the most current method. Other examples of frequency translation of noise appear as we investigate time variable transfer functions. The spectrum analyzer measures the power present in a certain band of frequency. iii In equation (6. RBW1 and RBW2. Section 6. The analysis window corresponds to the filter bandwidth and is called resolution bandwidth (RBW). and also due to amplitude limitations that occur in the intermediate and output stages of the VCO. by a random process which is amplitude modulated. i (t ) = 6. The representation of random noise by their PSD allows us to use a common small signal treatment for both deterministic and random signals. i(t) is the deterministic current signal that results from the sinusoidal input. Part of the power of this shot noise is frequency translated around ±fc . This is due to the frequency modulating characteristic of the input of the VCO. 2π]. For example let us consider the shot noise of a transistor driven by a sinousoidal input at frequency fc : iii I shot (t ) = q ⋅ i (t ) ⋅ X (t ) (6.Chapter 6 / Phase Noise: theoretical to practical approach 123 process with a periodic large signal.
One measures the variations of the period when compared to a reference oscillator. The ratio SSB noise / carrier when expressed in dBc/Hz. frequency and time deviations are discussed in the following section. So the power of these sidebands is not affected by the width of the RBW. This noise has a spectrum component at frequency fm which modulates the carrier output. The result is called timeinterval jitter. and that timeinterval jitter is related to the frequency deviation. The parts of the sidebands that are caused by random noise (inloop contribution from N PLL and outofloop contribution from vnvco) have a power level that varies with the width of the RBW. The power due to this contribution as the analysis window sweeps the frequency range equals: No. The power ratio between the sidebands due to random noise and the carrier is often expressed in dBc/Hz. iv . This expresses the variations of the period of the carrier.124 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops Spurious deterministic signal RBW1 10 ⋅ log RBW 2 foscfm Figure 6. It also shows that timedeviation jitter is related to the phase deviation in the carrier. Ideally the modulating rays are represented by impulses at fosc ± fm . The power of the modulated rays is concentrated in very narrow bandwidths around fosc± iv fm . This unit is used to normalize the power level to a 1Hz bandwidth. The result is called timedeviation jitter.1 fosc fosc+fm Spectrum Analyzer Output In figure 6. Let us consider a white random noise in the output with a power spectral density N o in W/Hz. which are considerably smaller than the values of the RBW. The power ratio between these sidebands and the carrier is expressed in dBc. In both types of measurement there are several parameters that strongly influence the value of the jitter measured. corresponds to LdB(foffset) which was defined in chapter 3 (equation (3.4) ). The phase noise performance can also be measured by a time parameter: the time jitter.RBW. Reference [Nord97] discusses the techniques of time jitter measurement and the parameters that influence the results. The relationships amongst phase. There are two different methods.1 the sideband rays at frequency offsets of ±fm are caused by a deterministic noise component. For instance the time step and the measurement interval determine the maximum and minimum frequencies of the noise components that are taken into account. However the modulating signal is limited in time and its spectrum has a finite width. This is due to the spreadout characteristic of the power spectrum density of these noise contributions. The second calculates the dispersion of the value of the period with respect to its own average.
Let us consider a sinousoidal carrier vc(t). looking at the relationships amongst phase. ∆f(t) and ∆t(t) with respect to their power spectrum densities. In other nodes of the circuit the added noise power causes both amplitude and phase deviations of the signal.. 6. frequency and time modulations. that we call modulated and superposed noise.1 Interchanging Modulation Types The phase deviation of a carrier may also be expressed as frequency and time deviations (see reference [Nord97]).2 Phase Noise Notations The description of phase noise varies with respect to the functionality of the blocks to which it refers. and in logical blocks it is quantified by time magnitudes. In every node of the circuit there is some noise power being added to the data signal. It follows that: unmodulated carrier: phase modulated carrier: frequency modulated carrier: time modulated carrier: v c ( t ) = A c ⋅ sin( 2π ⋅ fc ⋅ t ) v PMc ( t ) = A c ⋅ sin( 2π ⋅ fc ⋅ t + ∆ϕ ( t )) vFMc ( t ) = A c ⋅ sin 2π ⋅ ( fc + ∆f ( t )) ⋅ t + µ ∆ϕ [ ] v TMc ( t ) = A c ⋅ sin[ 2π ⋅ f c ( t + ∆t ( t ))] The three modulated signals are equivalent to each other if: ∆f ( t ) = 1 ∂∆ϕ ( t ) ⋅ 2π ∂t . ∆f(t) and ∆t(t) which modulate the carrier. ∆t ( t ) = ∆ϕ ( t ) 2πfc We may also express vc(t) and the modulating functions ∆ϕ(t). Phase noise can be caused by angular modulation of noise power. or by addition of noise power to the signal.Chapter 6 / Phase Noise: theoretical to practical approach 125 6. We continue with the distinction of phase and amplitude deviations caused by an added noise power. µ ∆ϕ = ∆ϕ ( t ) − ∂∆ϕ ( t ) ⋅t ∂t . Finally we look at the effect of amplitude limitation on the transmission of signals corrupted by noise. In this section we detail these two mechanisms of the generation of phase noise. In oscillators the phase noise is often quantified by phase or frequency magnitudes. We start with the angular modulation.2. S ∆ϕ ( f ) . and the time functions ∆ϕ(t). the voltage noise is converted into phase deviation by frequency modulation.. In particular at the input node of the VCO. They become: carrier: phase deviation: vc(t) ……. S c ( f ) ∆ϕ(t) …….
with a PSD which is a bandlimited white noise. The spectra of the carrier and the modulating noise are sketched in the table below. Let us consider that ∆ϕ(t) is a random phase deviation.. f ≤ bw 2 S ∆ϕ ( f ) = 0 .. + c ⋅ {S ∆ϕ ( f − f c ) + S∆ϕ ( f + f c )} 4 2 Ac 4 fcbwn Ac2 ⋅ N o 4 fc fcbwn fc 2 Ac ⋅ N o 8 fc Table 61 Phase Modulated Carrier The spectra of the phase modulated signal was drawn considering that the peak phase deviation is small (max{∆ϕ(t)}<<1 rad). The following subsection details the expressions of the angular modulation.. Spectra Signal & PSD carrier: Sc(f) Sc ( f ) = 2 c Single Sided (only positive frequencies) Sc(f) 2 Ac Double Sided (pos. and neg... using single and double sided representations of the frequency axis.126 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops frequency deviation: time deviation: ∆f(t) ∆t(t) j 2πf ……. The power of the deviations is the integral of the PSD over a determined frequency interval. and the FM narrow bandwidth approximation. A2 . S ∆f ( f ) = ⋅ S ∆ϕ ( f ) = − f 2 ⋅ S ∆ϕ ( f ) 2π 2 1 …….. . f > bw ∧ f = 0 No/2 bwn f phase modulated carrier: Sosc(f) [V /Hz] 2 Sosc(f) 2 Ac 2 Sosc(f) Sosc ( f ) ≈ Sc ( f ) + . S ∆t ( f ) = ⋅ S ∆ϕ ( f ) 2πf c 2 Therefore the power of the total frequency or time deviations can be evaluated using the spectral density of the phase deviation. frequencies) Sc(f) [V2/Hz] 2 2 Ac A ⋅ [δ ( f − fc ) + δ ( f + fc )] 4 4 fc f fc fc f phase deviation: S∆ϕ(f) [rad2/Hz] No bwn f bwn S∆ϕ(f)  Pϕ(f) NO .
4) where the SSB ratio noise/carrier equals: ∆ϕ p L dB ( f m ) = 20 ⋅ log 2 ∆ ϕ rms = 20 ⋅ log 2 :∆ ϕ rms = ∆ϕ p 2 Next we consider a single tone frequency modulated carrier vFM(t) . for n > 1 and n ∈N In this case of small phase deviations vPM is simplified to: ∆ϕ p ∆ϕ p v PM (t ) = Ac ⋅ sin (2πf c t ) + ⋅ sin[2π ( f c + f m )t + ϕ m ] − ⋅ sin [2π ( f c − f m )t − ϕ m ] 2 2 (6. J n (β) ≈ 0 .Chapter 6 / Phase Noise: theoretical to practical approach 127 6. The value of these coefficients for β << 1 rad . may be seen as a superposition of single tone modulations.1.2. and an outofloop zone that is frequency modulated by the intrinsic noise of the VCO and by the loop filter noise. PM and FM are two types of angular modulation.1 Angular modulation The output spectrum of the PLL synthesizer presents an inloop zone that is phase modulated by the PLL noise (NPLL). and a single modulating tone vm(t). The example of a single tone modulation is detailed below. Furthermore noise contributions that are represented by a power density. Let us consider the same carrier vc(t) defined above.3) where v m (t ) = Am ⋅ sin (2π ⋅ f m ⋅ t + ϕ m ) and Kp is the phase deviation sensibility in rad/V. We may also define ∆ϕp the peak phase deviation and rewrite vPM as: v PM (t ) = Ac ⋅ {sin (2πf c t ) ⋅ cos ∆ϕ p ⋅ sin (2πf m t + ϕ m ) + cos(2πf c t ) ⋅ sin ∆ϕ p ⋅ sin (2πf m t + ϕ m ) } [ ] [ ] and or ∆ϕ p = K p ⋅ Am v PM (t ) = Ac ⋅ n = −∞ ∑ J (∆ϕ ) ⋅ sin[2πf t + n( f n p c +∞ m t + ϕ m )] where the coefficients Jn(β) are the values of the Bessel function of the nth order with argument β. approach: J 0 (β ) ≈ 1 . The phase modulated carrier is named vPM(t). in the form: 2π ⋅ K f ⋅ Am ⋅ sin (2π f m t + ϕ m ) v FM (t ) = Ac ⋅ sin 2π f c t + 2π ∫ v mf (t )dt = Ac ⋅ sin 2π f c t + 2π ⋅ f m [ ] (6. and equals: v PM (t ) = Ac ⋅ sin 2πf c t + K p ⋅ Am ⋅ sin (2πf m t + ϕ m ) [ ] (6.5) . J 1 (β ) ≈ β 2 .
the approximation of small phase deviations is no longer valid. Figure 6.2. Therefore for fm tending to zero. In figure 6. We start looking at the deviations caused by a single tone noise at a certain frequency offset from the carrier.5) becomes equivalent to equation (6.3) for the phase modulated carrier. The combination of two SSB noise contributions at opposite frequency offsets (±foffset) is also considered and compared to the sidebands produced by angular modulation. An important difference between frequency and phase modulation is that the phase deviation caused by FM has an amplitude which depends on the frequency of the modulating signal.128 where v PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops v mf (t) = Am ⋅ cos(2 ⋅ f m ⋅ t + ϕ m ) and Kf is the frequency deviation sensibility in Hz/V. 6. Sn(f) Noise No/2 bwn fm +fm bwn fcbwn for bwn < fc/2 fc fc f PM Sosc(f) 2 Ac 4 Sosc(f) Pc ≤ Ac2 4 Sc(f) Carrier 2 Ac 4 fcbwn fc f fc fc f fc FM Figure 6.2 this limit is indicated by the dotted lines and by the reduction of the power at ±fc ( J0(∆ϕp)<1). If we define the peak phase deviation as ∆ϕ p = K f ⋅ A mf fm = ∆f p fm equation (6. v In the FM example the modulating tone is assumed as a cosinus function just to end with the same form as in the PM example.2 FM & PM carriers In the frequency modulated carrier the phase deviation is proportional to 1/fm.2 shows these differences in the spectrum of a carrier that is modulated by a bandlimited white noise. This case is called the single side band superposed noise.2 Phasor Notations In this section we consider the phase and amplitude deviations caused by a superposed noise. .
and equals: vn (t ) = An . Therefore the added noise has to be decomposed into amplitude and phase deviations. The superposed noise is a narrow band portion of n(t). Let us consider the addition of our sinousoidal carrier. [Ac+max{n(t)}] ] but it would not be able to represent the noise in the time instants that correspond to zero crossings of the carrier. It follows: . and developing the corresponding time functions an(t) and θn(t) that express the amplitude and phase modulation. However it would not be possible to include the values exceeding the envelope of the sinusoidal carrier.6). an(t).3 SSB superposed noise: AM + PM decomposition (phasor) The right side of Fig. On the other hand an amplitude error.7) where fno is the frequency offset between the noise contribution and the carrier. vc(t). 6. by substituting n(t) by vn(t) in equation (6.6) For values of: vc+n(t) ∈ [Ac . with some broadband noise. sin (2πf nt + ϕ n ) = An .Chapter 6 / Phase Noise: theoretical to practical approach 129 The concepts developed in this section are based on references [Robi91] and [Boon89]. v c + n (t ) = Ac ⋅ sin (2π f c t ) + n (t ) = Ac ⋅ (1 + a n (t ) ) ⋅ sin [2πf c t + θ n (t )] (6. ϕn fno PM +fno An/2 An/2 AM An An/2 An/2 fno fno +fno Ac Ac /2 Ac /2 Figure 6. The phase of the carrier is taken as a reference for the diagram. ϕn(t). Figure 6. can model every value of: vc+n(t) ∈ [[Ac+max{n(t)}] . Ac] we could model every deviation as a phase error. We may also express the amplitude and phase deviation.3 shows two pairs of sidebands that explain the amplitude and phase deviations caused by the superposed noise.sin[2π ( f c + f no )t + ϕ n ] (6.3 shows the phasor diagram of vc(t) plus a single tone noise vn(t).
6): vc + n (t ) = Ac ⋅ (1 + a n (t ) ) ⋅ sin[2πf c t + θ n (t )] = = sin (2πf c t )⋅ [ Ac (1 + a n (t ) ) ⋅ cos[θ n (t )]] + cos(2πf c t )⋅ [ Ac (1 + a n (t ) ) ⋅ sin [θ n (t )]] Finally assuming An<<Ac and An/Ac << 1 rad.130 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops vc + n (t ) = vc (t ) + v n (t ) = Ac ⋅ sin (2πf c t ) + An ⋅ sin[2π ( f c + f no )t + ϕ n ] = = sin (2πf c t )⋅ [ Ac + An ⋅ cos(2πf no t + ϕ n )] + cos(2πf c t )⋅ [ An ⋅ sin (2πf no t + ϕ n )] Then we compare it to the 2nd form of vc+n in equation (6. 2 Ac Sc(f) + Sn(f) 4 2 An 4 fcfno fc +fc fc+fno f PM AM 2 Ac 8 2 Ac 8 2 An 8 An2 8 fcfno fc +fc fc+fno f fcfno fc +fc fc+fno f Figure 6.8) and a n (t ) ≈ An ⋅ cos(2πf no t + ϕ n ) Ac (6. . It is in fact a liberty of notation to indicate the sign of the voltage signals that are associated with these sidebands. that are named vnu(t) and vnl(t) for upper and lower sidebands respectively.9) This result is represented in a spectrum diagram in figure 6. we find: θ n (t )≈ An ⋅ sin (2πf no t + ϕ n ) Ac (6. We take two single tone components at frequency offsets of ±fno . When a broadband noise is added to a signal it is very likely that for certain offsets the noise density at both sides of the carrier has a similar level.4 Superposed Noise: AM + PM decomposition (spectrum) We may now consider a 2nd SSB noise contribution. The plot showing the PM contribution has sidebands with “negative” power.4.
Inversely the amplitude modulating sidebands “cross” in positions that are in phase with the carrier. and opposite frequency offsets with respect to the carrier frequency. In the case of the PLL synthesizer. We may also see this increase in 3dB as a power addition of the phase disturbances caused by two independent or uncorrelated noise sidebands. Sosc(f) 2 Ac 4 Two sidebands Superposed noise + ideal limiter ⇒ +fc fc+fno f fcfno fc 2 An carrier only phase modulated (4 2 ) Figure 6. the combined power of these two sidebands is divided into two equal parts: one causing phase modulation and the other causing amplitude modulation. The peak phase deviation caused by these A max{ n (t )} = 2 ⋅ n two sidebands equals: θ (6. vnu and vnl. sin[2π ( f c + f no )t + ϕ nu ] and v nl (t ) = An . most of the added noise is propagated through stages that work with strong amplitude limitation.Chapter 6 / Phase Noise: theoretical to practical approach 131 They represent DSB superposed noise: they have equal amplitudes. we are particularly interested in the phase deviations caused by added noise and angular modulated noise. Figure 6. 2π] Therefore the phase difference between the two sidebands for t=0. The modulated DSB sidebands have frequency offsets and phases that are equal in module and with opposite signs. This nonlinear behaviour attenuates much of the power of the sidebands that cause amplitude deviations. The two superposed sidebands . Actually. is also a random phase with a similar flat distribution. Therefore statistically. The superposed DSB sidebands are called uncorrelated in reference to their random distributed phase difference. The type of modulation that causes the frequency translation of the noise power determines whether this disturbance generates phase or amplitude deviations.3 shows us that sidebands that cause exclusively phase modulation. have an equal probability of “crossing” either in phase or in quadrature. “cross” each other in a phasor diagram in phases that are in quadrature to the carrier phase. We can represent this statistical result by two sidebands that “cross” each other at positions with a phase offset of ±(π/4 + π) with respect to the carrier. because of the uniformly distributed phase difference ϕnuϕnl. v nu (t ) = An .10) The phases ϕnu and ϕnl are random variables uniformly distributed in the range: [0. Therefore it is common to refer to the total sideband noise power as a phase noise power. in opposition to the DSB sidebands caused by angular or phase modulation of a base band noise contribution.11) Ac which corresponds to an increase of 3dB in the phase deviation when compared to the SSB superposed noise. sin [2π ( f c − f no )t + ϕ nl ] (6.5 Phase modulated carrier by DSB superposed noise .
fc +fno Am fc fno Am An An An An Ac Maximum Phase deviation ∆ϕp ∆ϕp fc Ac Ac Angular Modulated DSB Superposed DSB Figure 6. The SSB phase noise in this case equals: Am ∆ϕ p = 20 ⋅ log L( f no ) superposed. sin [2π ( f c + f no )t + ϕ n ] K p Ac where Kp is the phase deviation sensibility in rad/V.DSB = 20 ⋅ log 2 2⋅A c where ∆ϕp is the peak phase deviation.11): A ∆ϕ p = max{ n (t )} = 2 ⋅ n θ Ac Next we compare the phase deviations caused by two types of sideband: superposed and angular modulated.6 Phase deviation from DSB sidebands I) Superposed DSB sidebands 2 ⋅ An ≈ ∆ϕ p = arctg A c 2 ⋅ An Ac II) Ang. modulated DSB sidebands 2 ⋅ An 2 ⋅ An ∆ϕ p = arctg A ≈ A c c A L( f no ) = L(− f no ) = 20 ⋅ log n A c An L( f no ) = L(− f no ) = 20 ⋅ log 2⋅A c Table 62 L(foffset) from modulated and superposed noise . In order to compare sidebands that have equal frequency offsets and amplitude. we suppose that the angular modulated sidebands are due to a band base signal vbb(t) that equals: v bb (t ) = 2 An ⋅ .132 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops Figure 6.5 shows the spectrum of a carrier plus a DSB superposed noise after it has been transmitted by a stage that eliminates the amplitude modulating sidebands. or as defined in equation (6.
The time deviation is represented by similar functions in the time and frequency domain: ∆tn(t) and δtnrms(f) in [s Hz ] . and this current charges the impedance of the loop filter. low and high. This single tone portion is equal to the SSB superposed noise defined by equation (6. The instants where the signal crosses the threshold are called zerocrossings. and ultimately it will modulate the frequency of the VCO output.7). If this node is part of one of the PLL blocks this noise power may be propagated to the VCO tuning input. . we may calculate the phase noise in the VCO output that is caused by a certain contribution of voltage noise. We name vs(t) the output signal and tc the zerocrossing time instant. In figure 6. Therefore if we are able to express voltage noise densities as phase deviations. The phase detector and charge pump transform phase deviations in current. Let us consider a logical or switching stage that has two output values. The rms amplitude equals the square root of the power spectral density for the unitary impedance. These stages may work with differential or single ended inputs and outputs.Chapter 6 / Phase Noise: theoretical to practical approach 133 The phase noise caused by two superposed sidebands is 3dB smaller than the one caused by angular modulated sidebands with the same amplitude.3 we discuss the transfer of stages that cause amplitude limitation.3 Slope approach The results of noise simulations in analog circuits is usually given as a voltage noise density at a specific node. whose output is represented by a single ended output (with an amplitude that is twice the amplitude of each side of the differential output) and a threshold. Vn(t) dvs/dt tc Ts 2A differential signal + treshold ∆tn(t) Figure 6. 6. It is important to notice that this comparison has considered a DSB superposed noise with both AM and PM portions. In section 6.7 Slope approach: voltage & time deviations The noise voltage Vn(t) is calculated by a small signal noise simulation around a zerocrossing instant. The variations of this period that are due to additional voltage noise are called time jitter. The result is usually presented as a voltage noise density δvnrms(f) in [ V Hz ] . and their action over the AM portion of the superposed noise. and it may also be written as a frequency function: v n (t ) ↔ δv n −rms ( f n ) . and we start looking at a single tone portion of Vn(t) that we call vn(t). and determines the tuning voltage vtune. The relationship between the voltage and time deviations is given by the voltage slope of the large signal driving the stage. The interval between two successive zerocrossings is the period of the signal driving the stage.7 we consider a differential stage.2.
1 we saw that phase deviations can be expressed as equivalent time deviations. it follows that: δt n −rms ( f no ) = δv n −rms ( f no + f c ) dv s (t c ) dt (6.8) shows us the value of the phase error caused by the SSB superposed noise. If the voltage noise density δvnrms(f) has the same amplitude for the frequencies fc+fno and fcfno the time deviation due to a DSB superposed noise becomes: 2 2 δv n − rms ( f no + f c ) + δv n − rms ( f no − f c ) = δt n − rms ( f no ) = dv s (t c ) dt 2 ⋅ δv n − rms ( f no + f c ) dv s (t c ) dt (6. Thus the time deviation that is caused by the single tone component δvnrms(fn) becomes: δv (f ) s δt n −rms ( f n − f c ) = n −rms n dv s (t c ) Hz dt or remembering that f n = f no + f c .14) where Ts is the period of the signal. and we indicate the independent parameter as the frequency offset to remember that the voltage noise that originates this time deviation is found at fc±foffset. The phase deviation relates the time jitter to the SSB phase noise of the output signal.15) Equation (6.12) This is the time deviation due to a SSB superposed noise at a frequency offset fno from the carrier.13) Finally the phase deviation due to a time deviation is: δϕ n− rms ( f offset ) = 2π ⋅ δt n −rms ( f offset ) Ts rad Hz (6. . and it specifies that the phase deviation is a sinus with frequency equals to the offset frequency between the superposed sideband and the carrier.2.134 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops The error caused by this superposed sideband at the zerocrossing instants is necessarily a phase error. Equation (6.14). It also shows that the phase noise is inversely proportional to the period of the signal. Furthermore in section 6.15) shows the degradation of a periodic signal due to a time deviation. it becomes: δϕ n − rms ( f offset L dB ( f offset ) = 20 ⋅ log 2 ) 2 ⋅ π ⋅ δ t n − rms ( f offset = 20 ⋅ log Ts ) (6. It follows that: ∆ ϕ p ( f offset L dB ( f offset ) = 20 ⋅ log 2 ) ∆ ϕ rms ( f offset = 20 ⋅ log 2 ) :∆ ϕ rms = ∆ϕ p 2 So for a rms phase deviation given by equation (6.
It presents a constant voltage gain for input voltages below a certain threshold and for amplitudes above this threshold the voltage gain equals zero.3 Large Signal Linearization The term large signal linearization refers to a transfer function that is calculated around a periodic steady state of a block with a large signal input. which appears as a time variable transfer function. If the small signal is represented by a noise component vn(t).16) where hPLS(t) is the transfer function for a small signal that is added to the large input signal.Chapter 6 / Phase Noise: theoretical to practical approach 135 6. The resulting time variable transfer function may be used to explain the frequency translation of the noise contributions that are found around the harmonics of the frequency of the signal. 6.1 Time and Frequency representation Let us consider the transfer function of a voltage amplifier that has an ideal limiting output.17) is linear. but it also has higher harmonics that are generated by the nonlinear clipping of the limiter. The periodic transfer for a small signal that is defined by equation (6. A similar discussion focused on oscillators noise can be found in [Haji98]. The transfer of a small signal that is added to vsi(t) may be calculated making a 1st order development of the periodic transfer around the steadystate that is driven by vsi(t). We call it the periodic large signal (PLS) transfer.8 shows the transfer of a sinusoidal input signal vsi(t) that overdrives the ideal limiting amplifier. The transfer function vso(t) / vsi(t) is time variable. vi .3. The Fourier transform of this time transfer is denoted as HPLS(f). it becomes: vsi(t) h(x) vn(t) h[vsi(t)+vn(t)] h[v si (t ) + v n (t )] ≈ h[v si (t )] + dh( x ) ⋅ v n (t ) = v so (t ) + hPLS (t ) ⋅ v n (t ) dx x =vsi (t ) (6. The large signal is considered as periodic. Figure 6. Here we search the transfer function for a small signal that is transmitted by a block which is driven by a large signal input. and it may be represented in both time and frequency domains. The previous section started discussing the phase noise induced by a voltage noise that is sampled at the zero crossing moments. since the output of These ideas are based on the convolution transfer discussed in reference [Boon89]. The output signal vso(t) has a fundamental harmonic at the same frequency as the input.17) where the frequency domain transfer function is convoluted with the small signal input. and the transfer causes vi amplitude limitations of the output. v n (t ) ↔ δv n −rms ( f n ) for hPLS (t ) ↔ H PLS ( f ) v n (t ) ⋅ hPLS (t ) ↔ δv n− rms ( f n ) ⊗ H PLS ( f ) (6. and we use it to define the transfer of the small signal when it is represented in the frequency domain.
fs f (Hz) Figure 6.3. The curves are indicated by the labels: si. The output of the ideal limiter is called v soideal and the output of the hyperbolic tangent limiter is called vsotanh . The gain at the zero crossing is equal for both limiters. We choose the hyperbolic tangent because it represents the transfer of a block that appears very often in ICs: the differential stage composed of bipolar transistors. These effects are further discussed in chapter 7. Gc=2. The input signal vsi(t) is a sinus curve with a frequency equal to 0. The supposition of a linear transfer holds for small signals whose amplitude does not disturb significantly the periodic large signal transfer hPLS(t).5 Hz. ideal. For broadband noise contributions the frequency translation also causes aliasing or folding. It is important to notice that the time variable characteristic of this transfer causes frequency translation of the input signals.Tw /Ts Time variable transfer function: hPLS(s) HPLS(f) t input large signal: vsi(t) fw fw Τs/2 =2.8 Periodic transfer determined by a large signal 6.9 shows the periodic transfer functions hPLS(t) and HPLS(f) that are calculated for two types of limiting amplifiers: an ideal limiter and a hyperbolic tangent (tanh) limiter. amplifier + ideal amplitude limiter output large signal: vso(t) Vout dVout = Gc dVin (0) Vin t Τw =1/fw Gc t Τs=1/fs Gc.136 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops the sum of two small signals equals the sum of their separate outputs. tanh. The figure is divided in 6 parts: A) The input and output signals have a unitary amplitude.2 Linear Time Variable transfer Figure 6. .
A simulation example is given in chapter 7. the periodic transfer hPLS(t) approaches a comb sampler. The functions are dv so (t ) dv so (t ) dt calculated using the approximation: ≈ ⋅ dv si (t ) dt dv si (t ) D) The periodic transfer functions HPLSideal(f) and HPLStanh(f) are presented. Recently software implementations have appeared (see reference [Wiel97]) which allow one to calculate a periodic transfer that is associated with a large driving signal. the amplitude value equals: 20. This is the slew rate. The light gray dashed curve shows a first order LPF that fits the difference curve for frequencies below 2Hz. This ideal sampler would completely suppress the AM component of a superposed noise. Together they determine the maximum slope of the output signal. Particularly for circuits working with high signal frequencies and/or very steep signals there is another lowpassfiltering behaviour that appears to limit the slope of the output signals. and it correctly fits the difference curve for frequencies above 5Hz.Chapter 6 / Phase Noise: theoretical to practical approach 137 B) The time derivatives of the 3 signals are: dvsi/dt . which is related to the biasing of the stage and to the load impedance. .9 are calculated with a mathematical model. The curves of figure 6. Finally we can observe that for Tw →0. The yaxis is also in dB. The yaxis is in dB. The difference may be represented as a LPF. The amplitude limitation of the tanh transfer is smoother than the ideal limiter. dvsoideal/dt and dvsotanh/dt . It can be seen that it is the lowpass filtering behaviour that differentiates the ideal and the tanh limiters. The periodic transfer function is very useful to evaluate the noise at the output of strongly nonlinear stages. that has a very steep attenuation slope. The dark gray dashed curve shows an approximation of the black curve. In this plot the frequency axis is single sided (only positive frequencies). C) The periodic transfer functions hPLSideal(t) and hPLStanh(t) are plotted. The labels are the same as used in part A). it is a LPF to the order of 24. to compare practical and theoretical aspects of the periodic transfer function. E) The periodic transfer functions HPLSideal(f) and HPLStanh(f) are plotted in a larger range of frequencies. The actual transfer of a block of a circuit may be calculated with software for analogic simulations.log( HPLS(f) ) F) The curve in solid line shows the difference between the two transfers: HPLSideal(f) and HPLStanh(f) .
9 Large Signal Transfer: ideal and hyperbolictangent limitations .138 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops A) B) si tanh si tanh ideal ideal C) D) tanh tanh ideal ideal E) F) tanh ideal Figure 6.
Different notations were presented and related to the mechanisms of phase noise generation. The representation of random electrical noise was briefly commented. The periodic transfer of switching stages was modeled as a time variable transfer function.Chapter 6 / Phase Noise: theoretical to practical approach 139 This chapter discussed the generation of phase noise due to noise power that is added to a signal. . that may be used to calculate the noise at the output of nonlinear blocks. or to noise that causes modulation of a signal.
140 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops .
................. 167 Figures: Figure 7........ 159 7....... 162 Noise Power added by the LO sidebands........................... 163 7........................................ are combined.. Large bandwidth noise sources............................................................................1 Figure 7............................. 160 7............. Time domain................................. 152 DFF plus superposed noise in the clock input: time domain signals........................... 155 DFF plus superposed noise in the clock input: frequency domain signals ..................................................................... Frequency domain ....................... 154 7.................1.................. time.............................. 166 7 Phase Noise in the PLL context In this chapter we continue our topdown analysis of the PLL circuit................6 Figure 7.................................................................... 149 7................................................ 162 7............................... Sampling effects: SNF x fcp ....................................................................................13 PLL block diagram with signal+noise inputs.............................................................5........ 148 Large bandwidth noise folding ................. voltage and current noise ..........3 Figure 7. 167 Tables: Table 71 Table 72 Table 73 Table 74 Data sheet points from: TSA5059 .........................................................................................low noise PLL............2 Figure 7................10 Figure 7..............................9 Figure 7........2........ Signal to noise ratio and implementation loss ........................12 Figure 7..8 Figure 7.... .... 142 Noise Transfer Slopes....................3...................................2.................... Charge Pump ....................... 158 Behavioural model of the PLL for AC and noise simulations ............................... 143 Synthesizer Noise Floor................................................................ Implementation Loss due to Phase Deviations ............... Digital Demodulator: clock and carrier recovery loops..11 Figure 7........................................................................................... about the transfer functions of the phase model and about the mechanisms of phase noise generation.... Simulations and measurement possibilities that are used to guide the design and the evaluation of a PLL IC are also discussed... 160 Behavioural model of the PLL for transient simulations.........................4...................................... 161 Digital Demodulator and Decoder .1.......................5........................2................................................... 153 Implementation Loss X Phase deviations ................................................. 147 7................................5.... Phase Noise in the PLL context 141 Translating the SNF into phase...................................1........................................... ........................3.. 158 7..................... Dflip flop..............................Chapter 7 / Phase Noise in the PLL context 141 Contents: 7.................2.....................................................................................3....................................... 144 Sampled Loop Model ...........4...................2.......................... 154 7..................................... Narrow bandwidth noise sources................................................................7 Figure 7.......... Detailing noise sources in different PLL blocks . 155 Charge Pump current noise levels within one period................................... 164 Behavioural Model of the Carrier Recovery loop......5 Figure 7.......................................................................................2......... 151 7... 145 The influence of fcp change for narrow band noise ................................................................................................................. Behavioural Models .... 143 7................... 151 The influence of fcp change for large band noise..................................................................................................2..............................4 Figure 7.1................... 7.................................... The results from the preceding chapters............................................ to analyze the noise contribution of different blocks............................. 159 7..............4.......................................1..............
The following block diagram with signal and noise inputs is used in this chapter. The input vnvco represents the intrinsic noise of the VCO. Later in chapter 8.142 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops This chapter combines the results of the previous chapters to develop a numerical analysis of the phase noise of a PLL synthesizer. It is measured in rad/sqrt(Hz). The possibilities to distinguish the dominant noise sources are also discussed. and it is composed of the noise contributions from: the reference chain (crystal oscillator and reference divider). the main divider and the comparator (phase detector and charge pump). current and voltage magnitudes. considering the bandwidth of the noise sources. Npll is a phase degradation that was introduced in chapter 3 as the synthesizer noise floor (SNF). The relationship between the phase deviations and the implementation loss are presented with a short numerical evaluation. these tools are illustrated by simulations and comparison to measurements. Xosc (ϕxosc) Npll Zfilter vnf Ph. time. Two examples of simulation are presented. and therefore it is practical to split these two contributions. These densities can be compared with the simulation of the different constituent blocks. This influence is examined. In chapter 4 . The sketches and expressions below summarize the results from chapters 2 and 3 that are used in the following sections. . to illustrate the concept of the periodic transfer. It starts with the translation of the SNF requirement for noise densities in phase. The noise densities are affected by the sampling effects of the edge triggered blocks. In figure 7. and. Finally we present behavioural models that enable one to combine circuit and system level descriptions in AC and TR simulations. we saw that the noise contributions from a loopfilter (from the filter impedance and the amplifier) are attenuated by the postfilter.1 PLL block diagram with signal+noise inputs The noise inputs are indicated by grey rectangles. i See table 43 : transfer functions of the disturbances that are related to the active loop filter. for a Dflip fop and charge pump design. Both vnvco and vnf are voltage noise densities given in ( V/sqrt(Hz) ). These top level models can be used to examine the total implementation loss that is caused by the phase deviations in the LO signal. Pump ( Kϕ ) vnvco ÷R PostFilter VCO ( Ko ) ÷N ϕosc Figure 7. Det. The behavioural model of a digital demodulator is also presented. vnf accounts for the noise sources i of the loop filter.2 the noise transfer slopes are indicated for inputs with a white spectral density. & Ch.
3 is the combination of two effects: . the amplitude deviations are strongly attenuated. Nevertheless this part of the noise is usually not significant. but just superposed or amplitude modulated.1) The peaking that is indicated in figure 7. N pll _ dB = min {LdB ( f offset _ in loop )}− 20 ⋅ log( N ) [ ] dBc Hz (7. 7. The superposed contributions cause both amplitude and phase deviations.the mismatch of the closed loop bandwidth with respect to fi (the intersection frequency for the asymptotes of the noise performances of the PLL and the VCO).and the overshoot associated to the closed loop transfer function B(s). translating the phase deviation in voltage.Chapter 7 / Phase Noise in the PLL context 143 ϕ osc = B ( s ) ≈ B 3 LPF (s ) = N pll N (1 + s ⋅ T )⋅ s p3 2 2 wn ϕosc/Npll + 2 ⋅ξ ⋅ s + 1 wn 0 dB/dec ϕosc/vnf ϕosc/vnvco ϕ osc = B vco (s ) ≈ B vco v nvco _ BPF (s ) = K o ⋅ s ⋅ C1 s2 2 ⋅ξ ⋅ s + 1 α ⋅ 2 + w wn n +20 dB/dec 20 dB/dec 40 dB/dec 60 dB/dec and B vco − BPF ϕ osc = v nf (1 + s ⋅ T p 3 ) Figure 7. Therefore the noise from switching blocks of the PLL (Npll) is expressed as a phase deviation. Our analysis starts with Npll . Hence we treat the sidebands of the output of the VCO as angular modulated sidebands. Part of the intrinsic noise of the VCO is not frequency modulated. referring to the noise performance of the inloop zone of the output spectrum.1 Translating the SNF into phase. time. . that is measured by the open loop phase margin. . These translations are used to reflect the requirement of phase noise into magnitudes that are comparable to the outputs of the different PLL blocks. voltage and current noise The requirement of phase noise for PLL synthesizers is often specified as a maximum phase noise density at the input of the phase detector. time and current deviations. It is a single sideband measurement in dBc/Hz. When the disturbed signal is propagated through stages that have a periodic transfer with high gain around the zerocrossing instants and low gain elsewhere. This resonant overshoot is related to the stability of the loop. The sidebands that are found in the output of the VCO are mostly caused by the frequency modulation of noise power at the input of the VCO.2 Noise Transfer Slopes In chapter 6 we discussed the deviations that are caused by noise contributions which are superposed to the signal or which modulate the signal.
3 Synthesizer Noise Floor The value of Npll is derived from the SSB phase noise. TSA5059 for satellite ii frontend applications. . Loop filters with a large bandwidth (that assures a closed bandwidth equal or greater than fi ) and an elevated phase margin are indicated to perform the measurements of Npll. as presented in section 6. Later on. Finally the sensitivity of the charge pump Kϕ is used to transform δϕpll into a current noise density δiChP . outloop LdB(ffoffset) inloop LdB(foffset) peaking foffset 20. We calculate the deviations as noise densities that are denoted as δϕpll and δtpll . ii A similar analysis for a GSM synthesizer can be found in [Gree95].1.log(N) fosc Npll_dB : Synthesizer Phase Noise floor Figure 7. We would like to express Npll as the equivalent phase and time deviations that would cause the same LdB(foffset).2. we relate δtpll to the slope and the period of a carrier signal. Let us picture these ideas through a numerical example.144 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops It is important to notice that excessive peaking masks the measurement of the inloop SSB noise (L(foffset) ).2.3). and the latter is related to the peak phase deviation that is caused by the PLL noise. The values in the table below are taken from the data sheet of the Low Phase Noise Frequency Synthesizer. and we derive δvpll using the slope approach (see section 6. The deviations are base band components that modulate the VCO output.
625kHz .795 f s Hz 4 MHz 2π The values of the time noise densities that are calculated above do not take into account any possible aliasing effects. taking iii From here on the notations δxrms are shortened to δx .2 mA 4 programmable values (2 bits) 16 programmable values [indicated as series in the form: (a+2k1). we find a more strict specification for the time density: T 1 δt Xosc = δϕ pll − rms ⋅ Xosc L for T Xosc = = 250ns and δt Xosc = 0.72 f s Hz When we compare the same δϕpll to the period of the crystal oscillator. Section 7.5kHz Icp R Reference divider ratio N Main divider ratio fcp Comparison frequency for a 4MHz crystal directly related to R values Input sensibility + related to N and fcp values frf RF input frequency (main divider input ⇒ frf = fvco ) 64 MHz . .2k2 ] 17 programmable bits + optional prescaler (/2) Typical value 157 dBc/Hz 120 µA / 260 µA 555 µA / 1. • Time noise density at the phase detector input equals: Tcp 1 δ t pll = δϕ pll − rms ⋅ L so for Tcp = = 4 µs 2π 250kHz iii and δ t pll = 12.2 discusses the sampling effects for the noise transfer.2 mA 2 / 4 / 8 / … / 128 / 256 .low noise PLL • The phase noise density at the phase detector input becomes: δϕ pll −rms N pll _ dB = 20 ⋅ log 2 = −157 dBc Hz ⇒ δϕ pll − rms = 1.67kHz. The relationship between Npll and the comparison period appears as we look for the equivalent time noise density at the phase detector input. 800kHz / 400kHz … / 12. Icp=1.2700 MHz Table 71 Data sheet points from: TSA5059 . 24.: 64 … (2171)=131071 or w presc. 5 / 10 / 20 / … / 160 / 320 w/o presc. 166. but the noise density variables continue to be given in rms values.998 ⋅ 10 −8 rad Hz In table 71 the value of the synthesizer noise floor is referenced to certain conditions of fcp and Icp.: 128 … 262142 2MHz / 1MHz … / 15.Chapter 7 / Phase Noise in the PLL context 145 Symbol NplldB Parameter Equivalent phase noise at the phase detector input Charge pump current (absolute value) Conditions measured with: fcp = 250 KHz.
that downconverts the RF input signals from the Lband (950 MHz to 2150MHz) to an IF stage.2 mA ⇒ δ i ChP = 0. We suppose a comparison frequency of 250kHz. with a cutoff frequency smaller than fcp/2 . The intermediate frequency equals 470MHz. and the frequency of the local oscillator equals fRF + fIF . The smooth transition is related to the optimization of the phase jitter σϕ in the output spectrum. The synthesizer noise floor in table 71 is indicated for the maximum Icp value. and consequently it is related to the period of the large signal driving the blocks under analysis. The range of the LO frequency and the counting ratios of the main divider follow: f vco ∈ [1420 .82 pArms / Hz δ iChP = δϕ pll ⋅ K ϕ L • Noise performance of the freerunning oscillator: Finally we may estimate the minimum noise performance of the VCO that enables us to assure a smooth transition between the inloop and the outofloop zones of the output spectrum. The maximum voltage slope of the output of a block is called slew rate. The output of the dividers and the phase detector itself are polarized with elevated biasing currents in order to increase their voltage slopes and decrease their sensibility to voltage disturbances. For the moment we may consider that our phase and time deviations are white bandlimited noise densities.146 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops into account the noise bandwidth and the sampling frequency. 10480] Next we consider the level of the inloop sidebands for the maximum closed loop bandwidth. so we combine this data with the minimum value of N. or 109 V/s. Let us consider the minimum and maximum values of Icp in table 71. 2620] MHz K for f cp = 250kHz → N ∈ [5680 . to obtain the PLL inloop contribution: iv Remembering α = I cp ⋅ K vco N . This iv situation corresponds to small values of N. The maximum closed loop bandwidth occurs for the largest open loop gain: α = αmax. • The voltage noise density at the phase detector: The time noise may be translated into a voltage noise for any logical or switching stage that is driven by a large periodic signal with a defined voltage slope (dv/dt) at the zero crossings.72 µVrms / Hz The voltage density is referenced to a time noise. Let us consider the tuner of a satellite receiver. Under these conditions the voltage noise becomes: δv pll = δ t pll for f cp = 250 kHz ⋅ dv dt L zero − crossing for dv ≈ 10 9 dt V s ⇒ δv pll = 12. then: for I cp = 120 µA for I cp = 1. . • The current noise density at the charge pump output: The specification of phase noise may be translated into a current noise value that is related to the sensitivity of the charge pump Kϕ . Usual values of slew rate for PLL stages with strong biasing are to the order of 1V/ns.382 pArms / Hz ⇒ δ iChP = 3. and large values of Icp.
2 Sampling effects: SNF x fcp We start recalling the discrete model for the PLL that was discussed in chapter 5. It follows that: fi < f cp 10 ⋅ 1 .Chapter 7 / Phase Noise in the PLL context 147 L pll ( f in −loop ) = −157 + 20 ⋅ log(5680 ) ≅ −82 dBc Hz Chapter 5 discussed the limitation of the maximum closed loop bandwidth for a given fcp value. f3dB . . The sampling accounts for the discrete outputs of the dividers and for the discrete input of the phase detector. Nevertheless if we want to optimize the phase jitter over a range of gain. we should consider using a VCO with a better noise performance. ≈ 1. by the following expression: f 3 dB . or when choosing adequate VCO and PLL circuits to compose a lownoise synthesizer. We will also treat the folding effects due to sampling of the switching stages. fcp . The numerical examples developed in this section are a starting point for the analysis of the noise performance of a PLL circuit. 63 ± 0 . It is a phase model with an ideal sampler and a zeroorder holder. we may increase fcp and work with higher closed loop bandwidths. fol . The limit of Lvco that is indicated above would be just enough to obtain a smooth spectrum for α=αmax. The sampling rate equals the comparison frequency of the phase detector. with a continuous current output.8 kHz ) < − 82 dBc Hz ↔ L vco (100 kHz ) < − 90 dBc Hz where Lvco is the SSB phase noise of the freerunning oscillator. If we take some practical margin to cope with gain variations (up to αmax/αn =3 ). 10 Earlier in chapter 3. the following boundary may be suggested: f ol ≤ f cp . we saw that the optimum closed loop bandwidth equals fi . We continue our analysis looking for parameters that allow us to differentiate the noise contributions that compose Npll . 28 f ol Therefore we may estimate the maximum closed loop bandwidth and the corresponding noise performance of the VCO in order to match f3dB with fi . The holder represents the charge pump.63 = 40 . They are mostly useful in two circumstances: while translating the specifications of phase noise of the LO to specific blocks within the PLL. and that the open loop bandwidth. 7. is related to the closed loop bandwidth.4. Otherwise if there is no restriction to increase the minimum tuning step.8 kHz ⇒ L vco (40 . When we introduce the sampling operation in the phase model of the PLL. we obtain the diagram in figure 7.
equation (5. τrst .4 Sampled Loop Model The discrete input of the phase detector ∆ϕn is the same as defined in equation (5. For this analysis we used the worst case of the delay for the stability constraint: Tw = Tcp . In chapter 5 we used this discrete model to discuss the constraints of stability during an interval of lock acquisition. It is the output of an ideal sampler with a comb shaped spectrum. and there is also the noise of the charge pump itself.Tcp) is named ∆ψn(w) . and it is analogous to the Laplace transform of ∆ϕn defined in equation (5. The noise of the charge pump is related to the reset interval. and consequently the charge pump transfer can be simplified to: I o (w ) ≈ K ϕ ⋅ T cp ∆Ψ n (w ) for w< π τ rst The noise contributions that come from the sinking and sourcing side are added in power. In what concerns the noise there is a difference. during which both current v sources are activated in order to prevent deadzone problems. The instantaneous value of the phase noise at the input of the phase detector is not null.Tcp) Tcp Hz ] vnvco [rad Npll Hz ∆Ψ (w) ∆Ψn (w) ZOH ChP io (t) ZF (w) Ko/jw θosc(t) I o (w ) ] 1/N Θ osc (w) Figure 7.18). v .16). Therefore the output of the charge pump corresponds to the small pulses that are generated to compensate the leakage currents and the residual transient currents.148 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops Xosc 1/R [V ∆ϕ(t) ∆ϕn(n. ∆Ψ n (w ) = +∞ 1 ⋅ ∑ ∆Ψ (w + n ⋅ w cp ) T cp n = −∞ with w cp = 2π T cp The transfer of the ChP as a zeroorder holder was defined in chapter 5. Here we are interested in the transfer of the noise that appears in the output spectrum of a locked LO. The Fourier transform of ∆ϕn(n. hence their sum does not equal to zero during the reset interval. Thus we may consider a minimum Tw=τrst for the locked condition. that outputs the charge pump for a given phase deviation input. For an ideally matched and leakless case we may consider that the signal output of the charge pump for a locked loop is null.17). as: − jw I o (w ) = K ϕ ⋅ Tcp ⋅ e ∆Ψ n (w ) Tw 2 w ⋅ Tw ⋅ sinc 2 where Tw is the width of the current pulse. Most of the synthesizers work with a reset interval much smaller than Tcp .
voltage and current noise densities. and that we consider the same frequency f for all the noise contributions. The combined transfer for the phase detector plus charge pump becomes: I o (w ) = K ϕ ⋅ n = −∞ ∑ ∆Ψ (w + n ⋅ w ) cp +∞ (7. from δϕ(f) to δϕ. decreases the resulting time and phase disturbances. δϕpll . we translated the SNF in time. We also look for the parameters that may influence the noise contributions of each block. We may distinguish two extreme behaviours for the voltage slopes with respect to the input signal frequency: • Transition slope limited by the slew rate: We recall that in lock mode the output of the two dividers.3) we see just one noise contribution that is independent of Tcp : the charge pump noise. we find logical blocks with rather steep edges.Chapter 7 / Phase Noise in the PLL context 149 This simplified transfer holds for frequency values that are within the first lobe of the sinc term in equation (5.3) where δtref .1 Narrow bandwidth noise sources In section 7. We call the switching blocks. Here we take the inverse path. The noise densities are a function of frequency.2) Equation (7. vi .2. δtdiv and δtphse represent the time noise densities from the reference chain.1. with transfers approaching the ideal Dirac comb sampler. In chapter 6. Next we examine the influence of the comparison frequency for the noise contributions that compose Npll . In equation (7. and we continue with large bandwidth noise in section 7. However the time noise densities are a translation of voltage densities that are transmitted by edge driven blocks. In fact. we saw that the transfer of the digital blocks approached this representation of an ideal sampler as their gain and/or the slope of the input signals increased.2. and the slope of the edges may be a function of Tcp . by supposing that they have white band limited spectra. increasing the slope of the edges for a fixed voltage disturbance.18). from the main divider and from the phase detector respectively. the phase detector and the charge pump. is composed of the following noise contributions: (δϕ ) pll 2 2π = δ t ref ⋅ T cp + δ t div ⋅ 2π T cp 2 + δ t phde ⋅ 2π T cp 2 δi + chp K ϕ 2 2 (7.2) is used to describe the transmission of large bandwidth noise sources.2. and discuss the total phase deviation that is caused by the voltage and current noises from the dividers. We start considering narrow band noise contributions that are not aliased by discretization. so that comparative measurements can be used to identify the dominant noise source in Npll . and the phase detector work at the same frequency. The current noise from the charge pump is denoted as δichp . which are vi eventually aliased by the sampling action of the dividers and the phase detector. The total phase deviation of the PLL blocks. 7. Therefore the sequence of coherent samplers can be replaced by a single discretization with period Tcp . which are driven by the edges of the input signals: edge driven stages. and we simplify their notation. Therefore in the context of low phase noise synthesizer.
and/or for stages that have a very high gain around the zero crossings. Table 72 examines the case of a voltage noise contribution that is transmitted by two edge driven stages with the slope characteristics described above. in order to keep a fixed oscillator frequency.4) Equation (7. The voltage noise δvn(f) is independent of fcp . vii We may illustrate this case by a sinus input. dv (t ) dv (t ) = cst = max = v′ max dt zero − crossing dt t=t0 This situation happens for stages that are driven by signals with very steep slopes.150 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops The slope of the output is fixed by the slew rate of the block transmitting the signal. Around the zero crossings the slope of the input is amplified to an output slope which is not limited by the vii slew rate. The change of the comparison frequency is compensated by changes in the divider ratios. then: +∞ and ϕ n ≈ ϕ1 v in (t ) = A1 sin (w in t + ϕ 1 ) + ∑ A n sin (n ⋅ w in t + ϕ n ) n=2 so dv in (t ) zero dt t=t − crossing 0 ≈ w in ⋅ A 1 + ∑ +∞ n=2 n ⋅ An . dv/dt is independent of the frequency of the input signal. (the input slopes are already close to the slew rate). with only positive frequencies. R and N. and it is band limited. or a series of harmonic sinus with the fundamental and the harmonics nearly in phase.4) describes a voltage noise density in a single sided frequency spectrum. The output slope equals the input slope times the gain around the zero crossing. for f ≤ f cp 2 (7. In the table we observe the influence of a change of fcp . The phase deviation at the input of the phase detector and also at the output of the VCO are indicated. for the phase deviation that is caused by δvn . The time and frequency noise densities are valid for frequency offsets below fcp/2 . dv (t ) = A ⋅ w in dt zero − crossing t=t 0 This case appears for stages that are driven by rather smooth inputs. δv n ( f ) = Vno [ V Hz ] . It is a band base noise that modulates the phase of the signal that drives the switching stage. • Transition slope proportional to the frequency of the driving signal: The slope of the output signal is proportional to the frequency of the input signal.
Chapter 7 / Phase Noise in the PLL context 151 Transition type dv(t o ) dt [V/s] wcp [rad/s]  δt  [s/sqrt(Hz)]  δϕpll  [rad/sqrt(Hz)] N  δϕosc  (in .2. The contribution of this phase noise to the inloop L(f) is directly scaled by N.δt1. On the other hand.wcp1 Vno δ t2 = 2 2 ⋅ A ⋅ wcp δϕ 2 N1/2 N1. We know that for stability reasons the bandwidth of the loopfilter is well below fcp/2 . that is proportional to Icp .wcp1 0dB/oct. Nevertheless these two sources can be differentiated by another parameter: the charge pump sensitivity Kϕ . 2. 2. and the inloop phase noise remains unchanged as the comparison frequency is doubled.wcp1 N1 Ν1. for the case of proportional slopes. This resynchronization means that the output signal is in fact a transition of the input signal that is copied to the output.wcp1 δ t1 δ t2 = Vno A ⋅ wcp 2.wcp1 N1/2 Ν1.A. The output of a resynchronization stage has a constant slope with respect to the dividing ratio.loop) [rad/sqrt(Hz)] L(f) x fcp [dB/fcp_octave] Slew rate slope ′ vmax wcp1 δ t1 = Vno v′ max δt1.2 Large bandwidth noise sources Particularly in low noise PLLs. since it is determined by the slope of the input signal.δϕ2 6dB/oct. it is common to resynchronize the output of the reference and the main divider to their input signals.wcp1 A. 7. and it is lowpass filtered by ZF before it attains an edge driven stage. This operation aims to conserve the phase quality of the input and to transmit it directly to the output. we find a constant phase noise density with respect to fcp . .wcp1 Proportional slope 2.δϕ2/2 Table 72 The influence of fcp change for narrow band noise For the first type of transition with a slew rate slope.wcp1 wcp1 δϕ 2 = Vno A N1 N1. which treats large bandwidth noises. We verify that besides the charge pump noise there is a second noise contribution that is independent of Tcp .δt1. avoiding the additional phase deviations of the countingcells. Or in other words. Furthermore these slopes are usually limited by the slew rate of the stage.δt1. a change in fcp does not influence the time noise. It corresponds to a constant time noise density with respect to fcp . The noise of the charge pump is added in the loop after the phase detector sampling. we will only look at the time noise densities of the logical blocks (dividers and phase detector). the output of the counter is triggered by a zero crossing of the input signal. So in the next section. thus we may consider that the charge pump noise is a narrow band contribution suffering from no aliasing effect.
We take the case of a broad band white noise. with nlim ∈ N f cp (7. The multiplying factor between the power levels of δvn and δvncp is named nlim . at the input of the phase detector. It follows that: nlim ⋅ f cp − bwn ≥ bwn ⇒ nlim ≥ 2 ⋅ bwn f cp .152 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops So next. a signal that has been sampled at a ratio fcp. with bwn much larger than fcp . This limit equals half the sample frequency and it is also called the Nyquist frequency. Mathematically the sampling is represented by a convolution product. The noise bandwidth equals bwn . however. δvn . Figure 7. Physically. as we consider the sampling effects for large bandwidth noises. This frequency 2 boundary is related to a physical limitation. We call δvncp the voltage noise density that is equivalent to a sampled version of δvn . Therefore δvncp becomes: Approximately. for f ≤ bwn Pvn(f) δvn(f ) bandlimited white noise bwn [V2/Hz] 2 Vno 2 bwn f 1 δvn(f ) Tcp δvncp(f ) … fcp … Pvncp(f) [V2/Hz] 2 nlim ⋅ Vno 2 … … bwn fcp/2 bwn f Figure 7. we restrict our analysis to the time noise densities that are related to stages with a constant output slope. It is derived by observing the number of frequency translated spectra that superpose each other. The power density of δvncp is increased by the aliasing effect. δv n ( f ) = Vno [ V Hz ] .5) . the power of δvncp equals 2 nlim ⋅ Vno for f ≤ .5 Large bandwidth noise folding The sampling is represented by a convolution product with a comb of rays that are spaced by fcp intervals.5 illustrates the aliasing of δvn as it passes the ideal sampler. can not contain power in frequencies above fcp/2.
• The slew rate of the switching stages is usually determined by the loading of the output impedance and the biasing level. ′ 2 vmax fcp1 2 ⋅δ t1 ⋅ wcp1 N1/2 N1 ⋅ δ t1 ⋅ wcp1 2 3dB/oct.wcp1 vn ⋅ bwn f cp1 δ t1 Vno bwn = .6) viii Table 73 examines the influence of fcp for the phase deviation that is caused by δvncp .fcp1 vn ⋅ 2 ⋅ bwn f cp1 δ t1 = Vno 2 ⋅ bwn . The comb transfer is a reasonable approximation 1 for noise bandwidths such as: > 2 ⋅ bw n . remembering that the SNF or Npll is directly related to δϕpll in the table 73. which relatively increases the width of the first lobe of the sinc envelope of HPLS(f) . The SNF change of 3dB/octoffcp is commonly observed in low noise PLL synthesizers. 2 LPF ⊗ H PLS ( f ) Slew rate viii The voltage noise density refers to a spectrum representation with only positive frequencies. for f ≤ f cp 2 (7. Table 73 The influence of fcp change for large band noise We observe that a broad band noise at the input of the phase detector causes a phase deviation that depends on the sqrt(fcp).17) ) that was discussed in chapter 6: • HPLS(f) tends to a comb as Tw tends to zero. and this postfiltering does not limit the folding effects. ′ vmax fcp1 δ t1 ⋅ wcp1 N1 N 1 ⋅ δ t1 ⋅ wcp1 2. .Chapter 7 / Phase Noise in the PLL context 153 δv n −cp ( f ) = Vno ⋅ nlim = Vno ⋅ 2 ⋅ bwn f cp [ V Hz ] . Let us now compare the transfer of the ideal sampler with the periodic large signal transfer (HPLS(f)_equation (6. Transition type wcp [rad/s] δvncp [V/sqrt(Hz)]  δt  [s/sqrt(Hz)]  δϕpll  [rad/sqrt(Hz)] N  δϕosc  (in .loop) [rad/sqrt(Hz)] L(f) x fcp [dB/fcp_octave ] Slew rate slope dv (t o ) = v′ max dt [V/s] wcp1 = 2π. It is represented as a lowpassfilter that follows HPLS(f) . Tw Furthermore the output of the dividers often have a duty cycle that is smaller than 50%. explaining the factor 2 with respect to the double sided (positive and negative frequencies) power spectrum. This behaviour results in a change of the synthesizer noise floor of 3dB/octoffcp .
4MHz . In the example the reset input alternates with the clock. • (IT(“/Q10/C”). The superposed tone in the clock input causes phase deviations in the collector currents of the transistors Q10 and Q11. They are differential signals that refer to the following voltages and currents: • (VT(“/ck”). This sequence of clock and reset signals represents the inputs of one DFF of the phase detector for a locked loop. . which command the inputs of the charge pump.6. with a fundamental frequency equals: fclk=2MHz. The spectra are shown in figure 7. The time domain signals are shown in figure 7.154 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops 7.7. we perform a discrete Fourier transform (DFT) of the time domain signals.3 Detailing noise sources in different PLL blocks The preceding sections discussed the noise contributions that compose the SNF. The D input is hard set to a logical “1” and we add a small signal deviation at the periodic clock input.3.VT(“/rstn”)): reset input. The falling edge of the Q output is determined by the reset input. It is also a voltage signal. It is the current at the collectors of a pair of transistors that receive the clock input. It represents a superposed noise. Here we will look at two simulations of different PLL blocks to examples the issues discussed above. In order to observe the sidebands that result from the phase deviations. We choose two blocks that have a different type of noise output: a Dflip flop (DFF) and a charge pump.1 Dflip flop The simulation uses a DFF that is implemented in emittercoupled logic (ECL). • (VT(“/cpon”). The frequency of the superposed tone equals: fn=11.VT(“/ckn”)): differential clock input. On one side of the input we add a series voltage source with a small sinus output. The first is a basic cell that appears in the three logical blocks: the reference divider.IT(“/Q11/C”): differential current signal. • (VT(“/rst”).VT(“/cponn”)): Q output of the DFF. The two examples use circuit blocks that are integrated in the testchips discussed in chapter 8. The names cpon and cponn refer to the destination of these outputs. The DFF also has an asynchronous reset input. so that we obtain a periodic output with the same frequency as the clock frequency. and the relationships of these contributions to the parameters Icp and Tcp . The second has a particular noise contribution that is not quantified as a time deviation but as a current deviation. It is a periodic voltage pulse with no added noise. It is a voltage signal. 7. These currents are converted into voltage signals that command the rising edge of the output signal. The tail current in this differential pair is deviated during the intervals where the reset impulse is high. the main divider and the phase detector.
6 DFF plus superposed noise in the clock input: time domain signals frequency [Hz] Figure 7.Chapter 7 / Phase Noise in the PLL context 155 [seconds] Figure 7.7 DFF plus superposed noise in the clock input: frequency domain signals .
4MHz . There are also rays at the frequencies n. − 3 .IT(“/Q11/C”). with tc a zero crossing = = 16 M V s dt 25 ns instant. so with respect to figure 7. If we recall the results of section 6. 6 . 6 .4MHz will present the same amplitude as the ray at 11. or numerically: − 11 .4MHz around the odd harmonics of fclk . with rays at 4MHz and its multiples. The differential Q signal has rising edges that are determined by the current signal (IT(“/Q10/C”). 6 . The sidebands appear at a frequency offset of ± 1. 6 .2. 4 . + 7 . 4 .7 is a single sided frequency representation.156 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops The settings of the time simulation and of the DFT are carefully chosen to improve the accuracy of the frequency domain plots.4MHz.16 dBc 2 ix (7. 14 …MHz. − 4 . 6 K + 11 . 4 MHz ) = 25 mV = 1 .2.3. we can represent the transfer function of this transconductor as a periodic large signal transfer: HPLS(f). So the sample frequency equals twice the clock frequency.5 the “negative” frequencies are folded in the positive side of the frequency axis. . 4 . This expectation is once more verified by the simulation. 5625 n s 16 M V s Next we use the relationships between time and phase deviations to find ∆ϕnpeak : ∆ ϕ n − peak ( f offset ) = (2π ⋅ f clk ) ⋅ ∆ t n − peak ( f offset ) = 19 . There is also a ray that corresponds to the added tone at 11. + 8 . 4 ± n ⋅ 4 + 11 . − 7 . 4 . The convolution product of the input with HPLS(f) should then present rays at the frequencies: ±fn ± n. The slope of the dv (t c ) 2 ⋅ 200 mV differential clock input equals: . or 2. So the output will present rays at: ±fn ± n. − 0 . 6.4MHz. + 4 . − 8 . as discussed in section 6. + 3 .fclk= 4MHz. the rays that are frequency translated at fclk±1. If we suppose that HPLS(f) is close enough to a comb sampler.7) We remark that figure 7.4MHz. 10. 6 K MHz K MHz ix This is indeed the result we observe in the spectrum of the current signal.12). The differential current signal is the output of a transconductor (the differential pair) that samples the input clock signal at every zerocrossing. We start with the sidebands of the current signal.fclk with n ∈ N.fclk with n ∈ N. Therefore we make an analogy with equation (6. 63 m rad So the L(f) of the sidebands in the current signal are estimated as: ∆ ϕ n − peak ( f offset ) L dB ( f offset ) = 20 ⋅ log = − 40 . The peak amplitude of the added noise tone in the clock input equals 25mV. 4 . 4 . Therefore the Q output samples this current signal every 1/fclk . The spectrum of the clock input is composed of a sequence of odd harmonics of the fundamental frequency: 2. We indicate this ray with an ellipse. or in other words it will present sidebands at ±0. and we find the time deviation: ∆ t n − peak ( f offset ) = ∆ t n − peak (1 .3. 4 ± n ⋅ 4 MHz MHz ⇒ ⇒ K − 11 . Finally we can calculate the expected L(f) of these sidebands and compare it to the level found in the simulation. These even rays of the fundamental appear because of the pulses that are caused by the reset input. The rays due to the input noise tone may also be seen as time or phase modulated sidebands. + 0 .6MHz and ±1.
9) The noise contribution of this broad band noise has a 3dB/octoffcp behaviour as discussed in table 73. The numerical application holds even for rather large perturbations such as the superposed tone used in this simulation.8) where R is the dividing ratio of the reference divider. which is still reasonably accurate. the broadband noise is then sampled to a Nyquist bandwidth equal to fxosc . It is often the reference chain.6).4MHz around fclk .n.51dB below the amplitude of the fundamental. Equation (7.4MHz.4dBc. It equals: nlim = bwn − Xosc 2 ⋅ bwn − Xosc 2 ⋅ f xosc = = = 2⋅R f Nyquist −cp f sample −cp f cp (7. which means that our periodic transfer HPLS(f) in this simulation is indeed close to a comb sampler. have an amplitude that is 40. we can try to find the one that represents the critical path with respect to the noise performance. The noise of the Xosc that is transmitted to the phase detector input is then estimated using equation (7.Chapter 7 / Phase Noise in the PLL context 157 In the simulation result the sidebands at ±1. we may concentrate our attention on a few nodes to determine the total time noise density that is transmitted to the phase detector input by the logical blocks. because only the rising edges are transmitting the phase disturbances.16 dBc The output of the simulations shows a L(f) of –44. So the estimation of L(f) in equation (7. The value of Vno can be obtained by noise simulations using software that calculate a periodic transfer for the noise.7) is quite accurate. It becomes: δv n − Xosc ( f ) at the phase = Vno ⋅ nlim = Vno ⋅ 2 ⋅ R detector input [ V Hz ] .4 MHz ) = L dB (± 0 .5) can be used to define a folding factor nlim for the noise coming from the Xosc. which causes a new folding to a Nyquist bandwidth of fcp/2 . we expect to find sidebands with an equal amplitude at the frequency offsets of ±0. If the resynchronization stages and the phase detector are composed of DFFs that have similar biasing levels. with steep edges and Tw tending to zero. Once more the logical blocks are the phase detector. The level of these sidebands should be reduced by 3dB with respect to the sidebands in the current signal. the reference and the main divider. for f ≤ f cp 2 (7. This result is reconfirmed by the fact that the rays at fn±2. If we continue to suppose a comb transfer from the signal current to the Q output. Later on it is downsampled by the resynchronization stage. This example shows that the periodic transfer of added noise sources can be accurately estimated by the large signal linearization (transfer represented by HPLS(f)).fclk all have similar amplitudes within the frequency range that is plotted. In a PLL that has resynchronized dividers.6 MHz ) = − 43 . due to the broad band noise floor that outputs the crystal oscillator (Xosc).6MHz and ±1. If we consider that the output of the Xosc has a buffering stage that is rather nonlinear. . So the expected L(f) equals: L dB (± 1 .
. The current noise densities that were calculated for the different transient points had roughly a white bandlimited shape with a cutoff frequency around 30MHz.8 Charge Pump current noise levels within one period In figure 7.1 ⋅ T1 T 2 + δiChP −inst . Tcp Tcp ≈ (8 p ) ⋅ 2 2 2. as follows: . The level of the current noise density at a frequency of 1MHz is sketched in figure 7.158 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops 7.2n The current density is transformed into a phase density using Kϕ . Therefore the noise contribution of the charge pump block can become very significant for the total phase noise performance.Tcp t [s] Figure 7.8 the peak of noise level occurs during the zero crossing of the inputs that command the charge pumps. We know that the minimum width of these impulses equals τrst . The output currents sinking and sourcing are a filtered copy of the input impulses of the phase detector.. after the transient signals have attained a periodic steady state. Tcp=3. The inputs of the phase detector are adjusted to correspond to a locked loop situation with an average current output equal to zero.2 Charge Pump The simulation concerns a phase detector and a charge pump blocks that were designed to work with very high comparison frequencies. to the order of 310MHz.Tcp (n+1).2 ⋅ 2 + . this corresponds to the lockedloop condition. It is part of a multiloop PLL structure that is discussed in chapter 8. A series of noise simulations is realized around different points of a time domain simulation. Due to the elevated comparison frequency the charge pump that has slow pnp current sources. We indicated it as: δiChPinstant(1MHz) . Here the ratio τrst/Tcp approaches 1/3 and consequently the current sources are never completely switched off. It corresponds to an instantaneous value calculated for a given time instant in a period.768. Here it becomes: 2 2 δiChP −total (1MHz ) = δiChP −inst . The total noise contribution of the charge pump is a time average of the instantaneous noise power levels.8. 9 n 2 0. and finally expressed as a SSB phase noise.150n + (140 p ) ⋅ = 9. The points are chosen within an interval of one period.10 − 22 A Hz 3. acts like a lowpass filter.3.2n 2 ⋅ 3. and.2ns Icp=182uA 300ps 140p 30M δiChPinstant(f) 8p A/sqrt(Hz) δiChPinstant(1MHz) A/sqrt(Hz) f [Hz] 8p n.
The dividers are replaced by voltage controlled sources that have an output equal to 1/N or 1/R times their input. and the output impedance equals the pullup resistor.9 the noise input of Npll is replaced by a source that represents the noise of the crystal oscillator. For a noise simulation we introduce two noise sources that represent Npll and vnvco . This phase model greatly simplifies the representation of the dividers that may directly divide the phase values instead of identifying and counting zerocrossing moments. In figure 7.Chapter 7 / Phase Noise in the PLL context 159 δϕ ChP − total (1MHz ) = δ i ChP − total 31 . We may model all the circuit blocks in behavioural descriptions or combine behavioural and circuit level descriptions. The PLL phase model that was presented in figure 2.4. This model may also be used for AC simulations that verify the open and closed loop transfers. We choose to represent the phase signals as voltages. for simulations in the time and in the frequency domains. 079 µ rad 182 µ Kϕ Hz δϕ ChP − total (1MHz ) L dB _ ChP − total (1MHz ) = 20 log = − 122 . Numerical examples are presented in chapter 8 while discussing the results of the testchips. It is used to simulate an ensemble of blocks that interact among each other.R) is also included through the gain block that follows the noise source. The amplifier is represented by a transconductor with a capacitive input impedance. is very close to a behavioural model that may be used for AC and noise simulations. 7.4 Behavioural Models The behavioural model is a synthetic form to represent different blocks of a circuit. In an analog simulator the phase signals have to be transformed in either voltage or current magnitudes. The loop filter is an active one. . Often they become interesting when a simulation using the full circuit description would demand too much memory and/or time . The integration of the phase model of the VCO is represented by measuring the ddp of a capacitor that integrates a current. 7. The following sections present briefly some points about a behavioural representation of the PLL synthesizer. 25 p = ⋅ 2π = 1 . The aliasing factor sqrt(2.1 Frequency domain A behavioural description of the PLL may represent the output of the VCO and the Xosc by their respective phases. 35 dBc Hz 2 This calculation is useful to estimate the limitation of the noise performance that is imposed by such a charge pump working with a high fcp .1. The calculation is compared to measurement results in chapter 8.
9 Behavioural model of the PLL for AC and noise simulations The output PHIvco (ϕvco) in this behavioural model may be used to calculate the total phase jitter of the LO signal.2 Time domain The behavioural representation in the time domain also uses phase models for the dividers. so that we may combine behavioural and circuit blocks. 7. In section 7. is then derived by integrating Sϕ (equation (3. The total phase deviation or phase jitter.160 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops Figure 7. The boundaries of the integral are related to the bandwidth of the channel that is being downconverted. .21) ).4. However it is interesting to represent the phase detector and charge pump in a form that is compatible with their circuit description. In fact ϕvco equals the mean square phase fluctuation Sϕ(f) (equation (3. σϕ .5) ).5 we continue to discuss these integration boundaries as we consider the implementation losses that are caused by σϕ .
This schematic is used to observe the transient residual currents that are due to mismatches between the sourcing and sinking sides. In an ensemble of blocks that work with different frequencies. .Chapter 7 / Phase Noise in the PLL context 161 Figure 7. The time step is the space between two consecutive points that are calculated in the transient simulation. Therefore we may simply divide Kvco and N by a common factor.10 Behavioural model of the PLL for transient simulations The accuracy of simulations in the time domain is closely related to the ratio timestep/signalperiod. Figure 7. we should consider the smallest period. The difficulty to simulate the full PLL circuit is connected to the large difference between the period of the signals at different points of the loop. In this transient model we reduce this difference of periods changing the parameters Kvco and N. and a circuit level charge pump and loopfilter amplifier. and reduce significantly the difference between the comparison frequency and the frequency of the VCO. In fact the VCO is represented by its phase and this phase is divided before it is retransformed into a sinusoidal signal.10 shows a combined model that contain behavioural descriptions for the dividers and phase detector.
the phase jitter of the LO adds noise to the RF data being downconverted. demodulator. RF input ADC Clock & Carrier Recovery Loops Viterbi Decoder ReedSolomon Decoder Demodulator LO PLL Forward Error Correction SDD: satellite demodulator and decoder Frontend Figure 7. In the case of QPSK signals the bit error rate reflects the probability that the additional xi phase noise exceeds a value of π/4 . that normalizes the signal power with respect to the bit rate. the final consequence of phase jitter is measured as a biterror rate x (BER) . we discuss the implementation loss that is caused by the phase deviations in the LO signal. this implies a BER to the order of 2. They show the theoretical and minimum signal quality that is required to decode the input signal with a certain amount of biterrors.7 . For the satellite DVBS that has an inner ReedSolomon coding and an outer Viterbi coding. Eb/No . Here.104 at the input of the Reed Solomon The BER is a common unit used in the context of digital decoders. The decoder is the second part.11 Digital Demodulator and Decoder For digital modulations. . MPEG standards for video coding impose BER to the order of 10 11 at the output of the decoder. as represented in figure 1. In the frontend or more specifically in the frequency conversion stage. The first part.11). and it contains the stages of forward error correction. The SNR is often indicated as a power density ratio: energy per bit over noise. It measures the amount of errors encountered in the reception of a bit stream.162 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops 7. clock recovery loop and carrier recovery loop. xi x Referring to a constellation diagram. is composed of the following blocks: ADC. Usually these results are presented in graphs of SNR versus BER. The numerical values are related to the reception of a QPSK modulated channel in a satellite receiver. The decoder can correct a certain number of bit errors depending on the redundancy and the robustness of the coding. for phase noise contributions that present a Gaussian distribution and a mean square value or variance of σϕ . we can calculate the BER using the distribution curves of a Gaussian variable. Thus. The circuit that receives the BB output from the frontend is a digital demodulator and decoder (see figure 7.5 Implementation Loss due to Phase Deviations Implementation loss is the difference between the theoretical limits that are calculated for the correct functioning of a system and the limits that are measured in a physical implementation.
Chapter 7 / Phase Noise in the PLL context
163
decoder, and a BER to the order of 6.103 at the input of the Viterbi decoder. The BER in the input of the decoder is also called raw BER. Using the theoretical curves of SNR x BER for QPSK signals we find that the raw BER of 6.103 is equivalent to a theoretical Eb/No of 5dB. We may also express the SNR as an energy per symbol instead of an energy per bit, which gives us a Es/No of 8dB. The implementation loss is measured as the increase in the ratio Es/No which is required to obtain a raw BER of 6.103 . 7.5.1 Signal to noise ratio and implementation loss
The following treatment of the implementation loss and phase noise power is based on the reference [Sinde98b]. Let us consider the signal and noise powers indicated in the schematic below: Ps
S
PNin PNϕ
SNRmin
where Ps : signal power measured within the bandwidth bwch ; PNin : noise power before the mixing stage, also measured within bwch ; PNϕ : noise power added by the phase noise of the LO, measured within bwch . For an ideal receiver working with a noiseless local oscillator, SNRin and SNRmin are equal, and they become: P SNRmin = SNRin1 = s PNin1 where PNin1 is the maximum noise power that can be handled by the receiver. When we consider a noisy LO the SNRmin equals: Ps 1 1 SNRmin = = = Pϕ 1 1 PNin 2 + PNϕ PNin 2 + + SNRin 2 SNRϕ Ps Ps where PNin2 is the maximum noise power at the input, in the presence of the phase noise PNϕ ; and SNRϕ is the signal to noise ratio for the phase noise contribution. The implementation loss (IL) due to PNϕ is defined by the ratio of the input SNR for the noisy and noiseless cases: SNRin 2 PNin1 1 IL = = = SNRmin SNRin1 PNin 2 1− SNRϕ It may also be expressed in dB as: SNRmin − dB − SNRϕ − dB 10 1 − 10 ILdB = −10 ⋅ log (7.10) where SNRmindB and SNRϕdB are the same ratios defined above, but expressed in dB. We can also calculate the SNRϕ which corresponds to a given IL and SNRmin. It equals:
164
PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
SNRϕ = SNRmin ⋅
IL IL − 1
or expressed in dB:
SNRϕ −dB = SNRmin −dB
ILdB + ILdB − 10 ⋅ log 10 10 − 1
(7.11)
Let us now consider the relationship between SNRϕ and the phase noise parameter Sϕ(f) which was introduced in chapter 3. The latter is a noise to signal ratio, that considers the noise contribution of a 1 Hz bandwidth in a certain offset from the carrier. The first one is a signal to noise ratio that considers the noise within the bandwidth of the selected channel (bwch). So, we expect the integral of Sϕ(f) to be related to SNRϕ1 . Indeed, if we consider the phase noise sidebands as narrow band noise contributions that are also downconverting the input channel, we find that:
bwch 2 bwch bwch − f offset + f offset 2 2 1 ∫ Sϕ ( f ) df + 2 ⋅ bw ∫ Sϕ ( f ) df df offset 0 ch − f offset 2
− SNRϕ 1 =
PNϕ Ps
=
2 ⋅ bwch
∫
0
(7.12)
−1 SNRϕ − foffset
where the noise being added corresponds to the frequencyshifted copies of the input channel. We should remember that Sϕ(f) is the double side band phase noise, which explains that the boundaries of the integral are limited to positive offsets. Figure 7.12 gives a physical idea of the integral above. It shows the noise contribution that is brought by two narrow sidebands around the oscillator frequency.
Ss(f)
[W/Hz]
bwch
foffset
Sosc(f)
[W/Hz]
f [Hz]
f [Hz]
∆f1
SBBoutput(f)
[W/Hz]
SBBoutput(f)
[W/Hz]
bw ch + ∆ f1 2
∆f1
Figure 7.12
foffset
f [Hz]
bwch − ∆f1 2
f [Hz]
Noise Power added by the LO sidebands
Chapter 7 / Phase Noise in the PLL context
165
The outermost integral in expression (7.12) sweeps the channel bandwidth from its center to one of the extremities. The inner integral evaluates the noise power that is projected over each narrow bandwidth portion of the channel spectrum. The noise amount that is projected on two sidebands that are equally spaced with respect to the center of the channel bandwidth, is equal. Therefore the outermost integral just needs to sweep a range of one half channel. However, depending on the position of the narrow bandwidth within the channel spectrum, it is a different range of the DSB phase noise, Sϕ(f), that downconverts or projects noise. For offsets close to the center of the channel, or for foffset << bwch , it is basically Sϕ(f) in the range [0, bwch/2], where the DSB phase noise accounts for the left and right sided offsets from the center of the channel. For offsets close to the extremities of the channel, or for foffset ~ bwch/2 , it is Sϕ(f)/2 in the range [0, bwch]. In expression (7.12), the total noise, PNϕ , is the sum of the noise contributions that are down converted by the sidebands around the LO. In the present case, where we consider a single channel at the RF input, the maximum frequency offset for these sidebands equals bwch . Next, two particular cases, concerning random and spurious sidebands, are discussed. 7.5.1.1 Spurious Sidebands Discrete spurious sidebands are also contributing to PNϕ . If we consider a pair of sidebands at a frequency offset f1, the DSB phase noise can be expressed as:
Sϕ 1 ( f ) = Ps1 ⋅ δ ( f − f 1 )
[rad ]
2
for
0 < f 1 < bwch
where Ps1 is the DSB spurious amplitude. It may also be expressed in dB, Ps1dB , and compared to As , the SSB spurious amplitude defined in equation (3.2). Ps1−dB = As + 3 dB
[dBc]
(7.13)
Then, replacing Sϕ1 in expression (7.12) results in:
f −1 SNRϕ 1 = Ps1 ⋅ 1 − 1 bw ch
−1 max SNRϕ 1 < Ps1
[rad ]
2
for
0 < f 1 < bwch
{
}
[rad ]
2
(7.14)
Therefore Ps1 is an overestimation of the SNR related to these single tone sidebands. 7.5.1.2 Random Phase Noise The random noise sources that modulate the tunable oscillator cause sidebands that are measured by a phase noise density, Sϕ(f). These sidebands may be divided into two zones. The first, inloop, is mostly flat with some peaking close to the intersection of the outofloop zone. In the second one, the power of the sidebands decreases with a 1/f slope. The PLL closed bandwidth (fcl) determines the size of the inloop zone. Most of the phase deviation power is due to the sidebands that are found in frequency offsets in the range [0 , fcl ] .
166
PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops
In most of the tuner applications, the PLL bandwidth is considerably smaller than the channel −1 bandwidth (bwch) . Thus the parameter SNRϕ − foffset in expression (7.12) is bounded by:
bwch
SNR
−1 ϕ _ foffset
≤ SNR
−1 ϕ _0
=
∫ Sϕ ( f ) df
0
2
[rad ]
2
−1 − Furthermore the value of SNRϕ − foffset is rather close to SNRϕ 1 0 for all the frequency offsets that − are in the range: [0 , bwchfcl ] . −1 − − If we replace SNRϕ − foffset by SNRϕ 1 0 in equation (7.12), we obtain a simplified form of SNRϕ 1 − that equals:
− SNRϕ 1 ≈
2 ⋅ bwch
bwch 2
∫ SNRϕ
0
−1 _0
− df offset = SNRϕ 1 0 = _
bwch 2
∫ Sϕ ( f ) df
0
2 = σϕ
(7.15)
− Expression (7.15) is an overestimation of SNRϕ 1 for the random noise sidebands; and it equals the square of the phase jitter, for an integration within half of the channel bandwidth.
7.5.1.3 Numerical Example The specifications of a receiver system define allocations of implementation losses for the different parameters causing signal degradations. In TV and satellite tuners the implementation loss due to phase deviation of the LO are specified by a maximum value of 0.2dB. We can use expressions (7.10) and (7.11) to calculate some numerical examples for the satellite QPSK receiver. Table 74 relates SNRϕ and IL for a Es/No of 8dB, corresponding to the raw BER of 6.103 .
ILdB
[dB] 1.6 0.8 0.4 0.2 0.1 0.05 0.025
SNRϕdB
[dB] 13.112 15.741 18.556 21.467 24.428 27.413 30.411
− SNRϕ 1
− SNRϕ 1
[rad] 2.210E01 1.633E01 1.181E01 8.446E02 6.006E02 4.259E02 3.016E02
[°] 12.662 9.356 6.766 4.839 3.441 2.440 1.728
Table 74
Implementation Loss X Phase deviations
We may also use expressions (7.13), (7.14) and (7.15) to relate the values of SNRϕ with the spurious level (As) and the phase jitter (σϕ) . For instance the implementation loss of 0.2 dB is equivalent to a phase jitter of 4.84°, or to a single pair of spurious sidebands at – 24.5 dBc.
A phase jitter of 2° and a spurious level below –36dBc is a compromise that implies a total SNRϕdB of 28.5.2 dB. vnvco ). The phase jitter.13.Chapter 7 / Phase Noise in the PLL context 167 − In practise the maximum SNRϕ 1 has to take into account both the phase jitter and the spurious power. Hence we should seek a practical boundary that compromises the phase deviation of the random and spurious noises and also preserves a margin for variations in the parameters that xii determine As and σϕ . depends on the noise performance of the PLL and the VCO ( Npll . depends on the amplitude of the modulating signal. The behavioural model for the phase transfer of the clock and carrier recovery loops is shown in figure 7.7 dB for the variation of the total phase deviation.2 Digital Demodulator: clock and carrier recovery loops Finally we need to consider the action of the demodulator blocks (carrier and clock recovery loops) for the phase deviations that come from the frontend.13 Behavioural Model of the Carrier Recovery loop The two loops are based on PLLs of the 2nd order. which works with the smaller closed loop bandwidth. on the peaking of the closed loop transfer and on the closed loop bandwidth. These stages are only represented by the delays that they cause in the signal path (block delay_2). 7. . xii The spurious level. There are three stages that are contained in the clock recovery loop: the antialias filtering. σϕ . Clock recovery loop Carrier Recovery loop Figure 7. slow loop. a satellite demodulator and decoder for BPSK and QPSK signals. our model is based on the architecture of the circuit TDA8043. The length of this delay depends on the symbol rate. The clock recovery loop is the external. There are different configurations of carrier and clock recovery loops. As . the Nyquist filtering and the interpolator. and on the suppression of the loop filter. on the frequency sensitivity of the oscillator (Kvco).with a margin of 6.
The output of the demodulator is a highpass filtered portion of ϕosc. the IL that is measured at the input of the decoder. The overall transfer of the demodulator is very close to a high pass filter of 2 nd order. fast loop. The ensemble of the demodulator blocks is synchronous. A systematic approach to investigate the dominant noise sources was presented.13. For the phase model. The analysis of a PLL design. For symbol rates above 10Msps. The TDA8043 can decode channels with variable symbol rates. the loops should be interlaced (an external clock loop containing the carrier loop) as represented in figure 7. used in the analysis of chapter 8. In this chapter we applied the results of the preceding parts. about the PLL model and the related transfer functions. was also introduced. the effect of the delays will become visible. The combined PLL+demodulator model is used to calculate the phase jitter that appears at the input of the digital signal decoder. which would be taken from the node at the input of the carrier loop. Simulation examples are presented in chapter 8. The phase model of the demodulator is used in noise simulations in combination with the PLL phase model. the two loops should be connected in series. For symbol rates below 10Msps. As we increase the bandwidth of either loop. The maximum symbol rate that can be decoded is 32Msps. Therefore the delays may be normalized as an entier number of periods of the reference clock. The carrier recovery loop is the internal. was discussed with numerical examples related to existing ICs. about the generation of phase noise. in a topdown approach. In the behavioural model these settings are translated to the loop filter parameters that correspond to a 2nd order closed loop transfer with a natural oscillating frequency wn and a damping ξ . and. These delays are independent of the symbol rate. The demodulator input (PHIdemin) receives the phase noise density that outputs the PLL. with a cutting frequency that equals the natural frequency of the fast loop. with suggestions for simulations and measurements. A model for a QPSK demodulator. can be correctly compared to a phase jitter value. and it works with a clock at 65MHz. Finally. behavioural models for transient and AC simulations were briefly described. In this manner. the series connection just changes the feedback return for the clock recovery loop. The bandwidth and damping parameters of each loop are programmable.168 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops There are other delay elements that account for the phase detectors functioning. causing some overshoot in the transfer. .
........................ The structures of the GmC oscillator and a double loop PLL synthesizer are exposed in tables and block diagrams....................................6 Figure 8......1..2........................... 188 Margin for degradations in the oscillators phase noise performance ..............................1.................. Double Loop Synthesizer ..................1...1................ 188 Phase Jitter and implementation loss for rs=3Msps and ∆fstep = 125kHz........................Chapter 8 / Testchips Realized 169 Contents: 8.......................................... The performance of the double loop synthesizer...........................4.......................... 186 Tables: Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Table 87 Table 88 Measurements of the frequency coverage of the QCCO ....................................................................................3.....................3 Figure 8...............................................................................2................................................................. 184 Settings of the demodulator block..................................... 177 8.................. 171 Double loop MOPLL: block diagram ........ 176 Photo of a testchip TC2 ...................................................................... with an integrated satellite band oscillator..2 Figure 8...............................................1.................................................... 186 Phase noise simulation for DL+QCCO with and without demodulator ... Results ............................3.......................................................... 174 Block diagram of TC2 ........................................... 177 TC2 _ inloop spectrum for N1=7 and fcp1=300Mhz ...................... is compared to a classical single loop and external LC oscillator....... 170 8.....................5 Figure 8................................ 179 TC2 _outofloop spectrum for N1=6 and fcp1=300MHz . ................................................................................... GmC oscillator..... 173 8............................................................................................................ 175 8............................. The synthesizers are designed for a monodyne or zeroIF receiver................... 183 Parameters and outputs for comparative analysis ................ 170 8............................... TC2: results ......2....4..................................4..............7 Figure 8.......................... Results and conclusions...........1..............9 Figure 8......... 181 Simulation result for the SSB phase noise _ linear scale .................................................................... 179 TC3 _ single low noise PLL plus QCCO..............................................................................................4.................. 183 8... ........... 187 Figures: Figure 8................................................................................................................................ Finally measurement results of phase noise and implementation losses are compared to simulations...................... 189 8 Testchips Realized This chapter presents two synthesizer testchips which contain a fully integrated GmC oscillator covering the satellite bandL......... Structure ....................... TC3 : single PLL plus QCCO circuit ........10 GmC integrated oscillator .................................................................................................................... Conditions for the simulations..................................4 Figure 8................. TC2 structure ................................................................................... 183 8....1 Figure 8.................3. Comparative analysis: phase jitter and implementation loss....... and they present a multiloop architecture...................................................................................................... 175 Parameters of the two zeroIF configurations being compared .............................2......2................. Configurations compared ..................2GHz...2......................... 180 8.......... TC2 : MixerOscillatorPLL circuit for satellite direct conversion ... 184 8................................. 172 8...................2................... 185 Phase Jitter and implementation loss for rs=30Msps and fLO = 2........................... 182 Spectra for ∆fstep =125kHz and flo =900MHz ........................................... 173 8...................... Testchips Realized 169 8........................................ 172 Double Loop: minimum step and comparison frequencies............8 Figure 8.................
The peak value of the ft of the NPN transistors equals 13GHz.1 GmC oscillator The GmC oscillator is a ring structure with two integrator stages and an inverting feedback. The maximum ft of the lateral PNP equals 200MHz. is an implementation developed in collaboration with Nat. In a zeroIF architecture the mirror image is a flipped version of the selected channel. In order to respond to both the specifications of a maximum tuning step and a minimum closed loop bandwidth. This enables us to compose a native PMOS. The first testchip that is discussed. 8. In terrestrial and satellite tuners the usual range of the tuning voltage is 30V. It is a doubleloop PLL synthesizer. 8. which is used as the input reference for the second loop which drives the GmC oscillator. The second solution is often chosen because it demands a phase shifter for a single tone signal. exploits the possibility of a single loop. TC3. Furthermore the digital standards of satellite broadcasting use QPSK modulation. to cope with the degradation of the phase noise. which is a common block in the two testchips. instead of a large bandwidth shifter. so that the demodulator can distinguish the channel from its mirror image. The integrated GmC oscillator has a range divided into 4 bands that are tuned in a 5V range. and phases that are shifted by 90° with respect i to each other. or having a LO oscillator with quadrature outputs. Basically there are two possibilities to provide the two outputs in quadrature: either phase shifting the input RF channel. [Tang97] and [Kokk92].1. A monodyne receiver needs to provide two outputs. The transconductance gma compensates the current i These quadrature outputs are very convenient for a receiver with a monodyne structure. Part 8.1. is to increase the closed loop bandwidth. with a pitch of 2.4µm. The two stages have outputs with an equal frequency. Hence the oscillator is also called a QCCO: quadrature current controlled oscillator. TC2. The oscillating frequency depends on the value of the capacitors and on the transconductance Gm. in quadrature to each other. The input reference in this case is a crystal oscillator.170 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops A fully integrated oscillator becomes quite interesting in monodyne receivers where the radiation of the input RF signal may significantly deviate a LC externallycoupled oscillator. The frequency tuning is made by varying the biasing current of the transconductance stages. to drive the same GmC oscillator. The first loop drives an oscillator in the VHF band. The testchips were realized in a bipolar process that is derived from a BiCMOS process.1 Structure Let us consider the block schematic of figure 8. The solution. Its phase noise is on average 20dB worse than a LC oscillator covering the same range with a 30V tuning range. The two oscillators are tuned in a 5V range. .a presents a single ended integrator stage. The second testchip. We start describing the results of the GmC oscillator. the research laboratory of Philips. which is also converted to base band. Therefore the quadrature outputs may be directly sampled and demodulated to retrieve the I and Q streams of data.1. It shows the basic parts of the QCCO. which gives us a bipolar+PMOS process. A fuller description of the double loop structure and the GmC oscillator can be found in references [Vauc98] . a multiloop structure is needed.Lab. This high voltage supply can be suppressed if the LO can be tuned under a 5V range. There are three levels of metallization. with a wide closed bandwidth. The stripped bipolar process kept the gate oxide of the CMOS components for the capacitors.
on the frequency sensitivity of the oscillator and on the amplitude of the signals VI and VQ .1. In the differential scheme the inversion is simply a crossover between the feedback signals. In practice an amplitude control. . that acts on gma . a unitary feedback with a phase shift of 360° . which is also equal to the natural oscillating frequency wn . On the other hand. Implementation in the testchips uses differential transconductances gmt and gma as drafted in figure 8. This situation is identified as the linear mode of the QCCO. gma Igma gmt C vin Igmt R vout gmt (tune) gma (amp) vI gmt (tune) gma (amp) vQ Igmt Igma Igma Igmt Fig. or in other words by increasing Igma .b Differential cascaded integrators GmC integrated oscillator The condition of oscillation. the closed loop transfer function for a voltage input becomes: gm a = − 1 ( R ) BQCCO (s ) = 1 s ⋅C 1+ gm t 2 (8. We can define a frequency sensitivity Kcco in Hz/A . as we increase the amplitude of the oscillating signal the transconductors gmt will no longer work in a linear mode. If the transconductance gma compensates exactly the losses of each integrator stage .b. which implies an increase in some noise sources that are proportional to the biasing currents.8. keeping the quadrature between the input and output voltages vin and vout . is met by cascading two integrator stages and an inversion.1. is needed to assure a minimum negative impedance during the start up of the oscillator and later on to fix the value of the amplitude.1.a Figure 8.Chapter 8 / Testchips Realized 171 losses in the resistor R.1) where the transfer of a single integrator is : Vout (s ) gmt = = wn Vin (s ) s ⋅ C . we will need a higher Igmt to cover the frequency range. and the losses due to this nonlinear function have to be compensated by the negative resistance.8. The phase noise performance of the QCCO depends: on the inherent noise sources. If we decrease Kcco by increasing the capacitors C.1 Single ended GmC integrator Fig.
Ideal band partition: 950M 1275M 1600M 850M 1175M 1500M 1925M 2150M ∆ f band 2250 − 850 + 300 = MHz = 425 MHz 4 1825M 2250M Measurements: Band 1 815  1230 415 119 Band 2 1190  1640 450 129 Band 3 1520  1950 430 123 Band 4 1850  2310 460 131 measurement conditions: Frequency Ranges [MHz] ∆fband [MHz] Kvcco [MHz/V] constant Vamp =2. and output Igmt ii The bands have an equal frequency range. The overlap for the limits of each band is chosen as 100MHz.172 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops In fact Igma is already the parameter that controls the amplitude. that enables a simple programming mode for the QCCO.1 . This amplitude represents the result of the compromise between consumption and phase noise performance. The bands are selected by programmable inputs. The frequency range covers the entire bandL from 950MHz to 2150MHz.1. The measurement results are presented in table 81. tunable range and consumption budget. 8.6V Vtune ∈ [0. Therefore the design of the QCCO is a tricky compromise between the requirements of phase noise. . and assures a low Kcco variation throughout the band. and.2 Results The QCCO implemented in TC2 and TC3 has a frequency range divided into 4 bands. The first design was reworked to improve the band coverage and the uniformity of the Kcco and ii the L(f) throughout the 4 bands. in comparison to the ideal band partition shown below. with some overlap in the extremities and in between each band. The ensemble of the biasing and transconductance blocks consume 26mA under a 5V bias. The outputs VI and VQ have a peak value to the order of 200mV to 300mV. for oscillators working in a nonlinear mode the amplitude control is also influencing the frequency. 3.6] Table 81 Measurements of the frequency coverage of the QCCO The frequency sensibility Kvcco is equivalent to the Kvco of the LC tuned oscillator. The tuning input of the QCCO is a voltage/current (V/I) converter that receives Vtune as input.
5 dBc Hz ↔ ↔ L (100 KHz L (100 KHz ) = − 76 .1 Double Loop Synthesizer Figure 8. since its spectrum is “copied” to the LO output. This VHFoscillator has a strict requirement for phase noise. one is programmed with the same count (N1) as the divider of loop #1. and the other (R2) determines the minimum tuning step. and its input is called Vamp . The reference divider is composed of two counters. A second V/I input is used for the amplitude control. 2 GHz f QCCO = 2 .2 TC2 : MixerOscillatorPLL circuit for satellite direct conversion The testchip TC2 contains several blocks of a double loop PLL synthesizer. Loop #2 drives an oscillator that works in the VHF range. and at the end of the band the L(f) is limited by the shot noise of the transistor of gmt . . The first one (loop #1) locks the QCCO to the reference delivered by the second loop. The tuning system is composed of two cascaded PLLs.2. The present design was improved to work with a fixed Vamp value. so that this input can be used to compensate the process spread. 8 ) = − 75 . The parameter Kvcco is the overall sensitivity that includes the gain of the V/I converter plus the Kcco of the GmC oscillator. The noise from the biasing stages is minimized by using a large voltage interval for the degeneration of the current sources. The input range for Vtune is limited by the working range of the V/I converter. 8. 8. The same uniformity was also aimed at for the SSB phase noise performance. 4 ) = − 91 . and the following values are measured in the two extremes of the tunable range: f QCCO = 1 . 9 dBc Hz dBc Hz dBc Hz At the beginning of the band the main noise source is the thermal noise of the resistors loading the transconductors. 1 GHz ⇒ ⇒ L (600 KHz L (600 KHz ) = − 92 . The reference of loop#2 is a traditional 4MHz quartz oscillator (Xosc). The synthesizer chip is combined with mixeroscillator blocks to compose a MOPLL circuit. Table 82 shows the relationships among the comparison frequencies and the oscillator frequencies.2 is a block schematic of the double loop architecture. Loop #1 works with small divider ratios (N1) which allows one to obtain a quite low phase noise for part of the inloop spectrum (to the order of 108 dBc/Hz). which means that the input RF channels are directly downconverted to band base. The circuit is dimensioned for a monodyne receiver.Chapter 8 / Testchips Realized 173 .
I RF input I QCCO .LO Q BB output . #1 Loop #1 / N1 Zfilter #2 VCO2 VHF band Loop #2 /N2 Ph.+Ch. . reference divider ratio in loop #2.P.174 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops doubleloop MOPLL circuit BB output . #2 /N1 /R2 Xosc (4 MHz) Figure 8. main divider ratio in loop #1. main divider ratio in loop #2.2 Parameters: Double loop MOPLL: block diagram ∆fstep : fcco1 : N1: fcp1: fvco2 : N2: R2: fcp2: fXosc: minimum tuning step. output frequency of loop #1. Det. Xosc frequency.Det. VCOVHF frequency. + Ch. output frequency of loop #2. comparison frequency in phase detector #2. QCCO frequency.P. comparison frequency in phase detector #1.Q RF AGCLoop V/I converter Zfilter #1 Ph.
7]. The main divider of loop#1 is composed of two swallow counters and N1 belongs to the set: [4. The comparison frequency of loop #1 equals the VCO2 frequency. The frequency input is bound to the charge pump output and to an external LPF impedance. This condition assures that the comparator can retrieve frequency and phase differences (see chapter 5).2 were implemented in the testchip TC2. analog and digital.Chapter 8 / Testchips Realized 175 oscillators frequency wrt fcp fvco2 = fcp1 fcp2*N2 fcco1 fcp1*N1 It is important to notice that the comparison frequency of loop #2 becomes: f cp 2 = ∆f step N1 wrt N and R wrt ∆fstep with: ∆fstep = f Xosc * N 2 R 2 * N1 f Xosc * N 2 R2 f Xosc R2 ∆f step * N 2 N1 ∆f step * N 2 Table 82 Double Loop: minimum step and comparison frequencies. If we consider a margin of 20MHz and a tuning range of 4 V. 6. The analog part has symmetrical inputs for the RF signal and asymmetrical outputs for the BB signals: I and Q. with a frequency sensitivity that is close to the Kvco of UHF oscillators. It follows that: max{ f vco 2 } = 950 M = 237. These parameters serve as references for the design and the application of loop #2.3. There are external control inputs for the amplitude and frequency of the QCCO. the average Kvco of VCO2 equals 27. that interact through interface blocks. The frequency range of VCO2 is then determined with respect to the limits of the QCCO band. since the transfer characteristics Iaverage / ∆ϕin should cover a minimum input range of ±180° . The bus has an additional acknowledge block that indicates the . The testchip is basically divided into two parts. A more detailed schematic diagram is included in figure 8.1 MHz 7 Actually the range of VCO2 should also include some margin at the extremities. which means a maximum fcp1 to the order of 330MHz.2.2 TC2 structure The blocks that are colored in grey in figure 8. 8.5 MHZ 4 min{ f vco 2 } = 2150 M = 307. The ensemble of blocks is programmed by a 3wire bus. Thus VCO2 works in the range of a VHFIII oscillator. The LO signal can be monitored through a test output. 5. The design of the charge pump and the phase detector are mostly determined by this constraint.4MHz/V.
5. The total consumption is 60mA under 5V. On the left side there are the digital blocks (bus. The charge pump has 2 programmable values of Icp ( 20µA and 190µA) and it can also be set to test modes with sinking. which includes the 20 input/output pins. mixer. and on the right side. The total layout area is 2.6. It is measured as perturbations in the output spectrum when the synthesizer is continuously receiving a repetitive programming word. In reality this block is included to test the sensibility to bus crosstalk. ANALOG PART Vamp V/I Bandgap regulator Vreg QCCO Rfin 2 VCCO GNDO Dual Mixer I Q 4 4 4 Sym> Assym Output stage BBI BBQ V/I 2 BNISOLATION Plus block combine I &Q Pin for external Loop Filter 2 CCOout output for Z=50Ω INTERFACE LAYER Phase Det. regulator. a pair for the analog part and another for the digital one.176 PLL Frequency Synthesizers: Phase Noise Issues and Wide Band Loops reception of a full programming word.3 Block diagram of TC2 There are 4 supply pins. Figure 8.2mm 2 . The output of the acknowledge block is equivalent to an iii I2C bus output. iii Bus crosstalk denotes the interference of the bus activity in the others blocks of the synthesizer. + Ch.4 shows a photo of a testchip TC2. input and output buffers).7) Bus data load synchronization QCCO 3 Test Bus SDA SCL ENB ACK DIV456 2 PhDetChP 4 2 Ref 2 VCC GND Biasref DIGITAL PART Figure 8. Pump #1 2 Div. the analog part (QCCO. sourcing and highimpedance outputs.1 (4.1mm2 . from the higher to the lower corner). and the active layout area equals 1. . The symmetry of the layout of the analog part is stressed to guarantee