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Digital Design Pretiminary Exam (Fall 2010) ‘Name or Student ID: Date: 10/29/2010 ‘Question No. | Percentage % Grade T 5 2 15 3 15 q 10 3 15 6 10 7 20 Problem 1: Numbers, a. Inside a computer, negative numbers are represented by 2’s complement. And subtraction can also be completed as add a negative number in 2’s complement form. Use 8-bit binary to illustrate the signed operation of -96 — 64 and explain why or why not an overflow occur? 64= Oloe0060 2S cmnphenn eck 1E=cC!l00000 “1G 1000000 -cyt lolocono ‘[oll0000 0 b. IEEE 754 standard in using 32 bits to code a floating point value has 8 bits for exponent and 23 bits for fraction. The bias is 12719. Based on this standard, below binary represents which decimal floating point value? (Show the procedure.) 01000001100101000006000000000000, ene . e-lat de COUHE(D ) e668 iocpoo| = 4240 = Il 3 J N= . il (14 0-018) (2 J °*) fee H 7-7 ---- 000000008 Problem 2: Boolean algebra and minimization methods, Design a logic eircuit that controls the elevator door in a three-story building. The circuit has four inputs. M is a logic signal that indicates when the elevator is moving (M=1) or stopped (M=0). F1, F2, and F3 are floor indicator signals that are normally LOW, and they go HIGH only when the elevator is positioned at the level of that particular floor. For example, when the elevator is lined up level with the second floor, F2=1 and FI=F3=0. The circuit output is the OPEN signal, which is normally LOW and will go HIGH when the elevator door is to be opened. Find the simplified design and draw the diagram of the elevator circuit. ‘Note: Because the elevator cannot be lined up with more than one floor at a time, the cases when more than one floor inputs are high can be treated as don’t care condition. When the elevator reaches at one floor and stops, the door opens. Utilize K map to minimize the output expression.) a F3 Elevator Circuit RRR © 0 6 ° ° \ ° 1 ° eo 4 \ 1 6 6 Ve 1 x _ acu \ t ° x omer= MF + AA + ME tos \ s oxceur = WALA eth) ce 8 ° ° co} \ ° o 4 ° ° oN ' x Lo ° ° i) + (4 o Zz Vi 1 x Problem 3: Combinational design with multiplexer. For the function f(A, B, C)= Em(0, 4, 5, 6), use Shannon’s expansion to derive an implementation using a 2-to-1 multiplexer and any other necessary gates. FOABO= Mamet Met Me = Kec + asic + age + Age! Sinnnenr F(A, BC) Feed +0.60.8,d Rec) +adec +8c 4ee) eau toes = 008 0-9-0708 iececxec! pao 0000 Te gor-e i Problem 4: Digital design and code. Use two 4-bit binary adders and other basic logic gates to build a BCD adder. This BCD adder should also have carry in and carry out bits. Binary Sure Bob uw Kz 4&2 2, CZ, Zy Ay Cm condition for correction ome t2e, + ZZ. Adend Agena - Problem 6: Design a digital combination lock for the specifications below. Specification: +2 inputs (*0” and “1” buttons) + One output (“OPEN” signal) + UNLOCK is 1 if and only if: Last 4 button pressed were Azo the “combination”: 0110 @=0; No 6 Csto o/o CJ y= fo By eee ee oe Sdn xo KE °° oO ° ° Ru © ° om | a \ oO 7 uty fe P= ty x 4 : kK uy = Wx tov a Dabpare RAN Auev)X - Problem 7: You are an engineer working for NASA. They want you to design a FSM that will test their newest rover Fido on the PVAMU camp plans to Fido, and then Fido moves according to that information, VASA wirelessly transmits the travel To design your FSM, you first select the following locations around the PVAMU campus and assign each location with a state in 3-bit binary representation: S.R. Collins Engr Bldg [000], Electrical Engr Bldg [001], C. L. WilsowGilchrist Engr Bldg [010], Chemical Engr Bldg [011], University College [100], University Village Phase 1 & 2 [101], Home Economics Building [110], and the Delco Building [111]. To simplify your test, you inform NASA to send Fido’s FSM a binary sequence for travel plans (c.g.‘1-0-0-0-1’ to cause Fido to move five times). In other words, Fido receives either “0” or ‘1’ for each move and travels to the next destination as specified below. Fido starts offat the S. R. Collins Engr Bldg for each test run, and your FSM should output Fido’s current location. S.R Collins Engr | If 0, stay at S. R. Collins Engr Bidg [IF TI, go to Electrical Engr Bldg Bldg [000] Electrical Engr Bldg | IF0 go to C. L. Wilson/Gilchrist Engr | IFT, go to University College foo1) Bldg Cr. TF0, go to Chemical Engr Bidg IFT, go to University College Wilson/Gilchrist Engr Bldg [010] Chemical Engr Bldg [IF0, stay at Chemical Engr Bldg IFT, go to S. R. Collins Engr Bldg for] “ University College [100] IFO, go to Delco Building If 1, go to University Village Phase 1&2 University Village 7 Phase 1 & 2 [101] IF0, go to Chemical Engr Bidg IFT, go to Home Economics Bldg ‘Home Economies | IF 0, go to Delco Building IF, stay at Home Economies Bldg Bldg [110] _ Deleo Building IFO, go to Electrical Engr Bldg TF, go to University Village Phase [111]. J 1&2 A. Draw the circuit for the FSM using D flip-flops. Show all work for full credit B. If Fido is forever given a sequence of ones (ie. 11111...), where will it eventually end up? Final location: * c. Xo pen Cemene!® §(\10) If Fido is forever given a sequence of 01s (i.e. 010101...), which location(s) will itnever visit?