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  ///  0 VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym for Very High Speed Integrated Circuits). *! ( *! ()'*  +*!  '  *- . It is a hardware description language that can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level.  !  **   ! + *!  . The VHDL language can be regarded as an integrated amalgamation of the following languages: sequential language + concurrent language + net-list language + timing specifications + waveform generation language => VHDL    A standalone piece of VHDL code is composed of at least three fundamental sections: ‘ r‘ .

etc. std. For example: ieee. work. " : Contains a list of all libraries to be used in the design. r‘ # $.

$": Specifies the I/O pins of the circuit. r‘ %.

$#%$ #1 Contains the VHDL code proper. which describes how the .

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 "  To declare a LIBRARY (that is. as shown in the syntax below. . and the other a use clause. one containing the name of the library. to make it visible to the design) two lines of code are needed.

are usually needed in a design: r‘ ieee. USE work. # $. The purpose of the three packages/libraries mentioned above is the following: the std_logic_1164 package of the ieee library specifies a multi-level logic system.declaration.standard. so there is no need to declare them.A semi-colon (. etc.all. Their declarations are as follows: LIBRARY ieee. while a double USE std. and r‘ work (work library). from three di¤erent libraries.std_logic_1164. std is a resource library (data types. -.).the end of a statement or LIBRARY std. -.std_logic_1164 (from the ieee library).) for the VHDL design environment. etc. the latter is only necessary when the STD_LOGIC (or STD_ULOGIC) data type is employed in the design (data types will be studied in detail in the next chapter). However. LIBRARY work. -. -. " )23 (# )2-'4*2-'4*2'3 At least three packages. and the work library is where we save our design (the . only the ieee library must be explicitly written.dash (--) indicates a comment.all. simulator. The libraries std and work shown above are made visible by default. text i/o.vhd file. r‘ standard (from the std library). plus all files created by the compiler.) indicates USE ieee.all.

..).$" An ENTITY is a list with specifications of all input and output pins (PORTS) of the circuit.. Its ENTITY can be specified as: . END entity_name. Its syntax is shown below.4. ENTITY entity_name IS PORT ( port_name : signal_mode signal_type. port_name : signal_mode signal_type. Example: Let us consider the NAND gate of figure 2.

w ile NOUï is bidiectional. OUï. NOUï. o BUFFER. ï e type of t e signal can be Bï. ata types will be discussed AïER. NïEGER. ë        . SïOGC. N and OUï ae tul unidiectional pins. BUFFER.3. on t e ot e and. is employed w en t e output signal must be used (ead) intenally. As illustated in figue 2. etc.APage ï e mode of t e signal can be N.

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ï e name c osen fo t e entit was nand gate. mode OUï). mode N) and one output (x. All t ee signals ae of t pe Bï. being two inputs (a and b.                    #5 ‘ ‘ ï e meaning of t e ENïï above i t e following: t e ci cuit as t ee / pins. .

B. CARRY:  BIT).  HALF_ADDER.  DFFå . B : in std_logic. SUM.  FULL_ADDER. CIN:  BIT. Z: BIT_VECTOR(0  3)). ENABLE:  BIT. end MUX2x1. B: in BIT.  DECODER2x4. FULL ADDER  FULL_ADDER  ' (A. Q:  STD_LOGIC). Y : out std_logic). DFF  DFF is ' ( D. S : in std_logic. B. MUX 2x1  MUX2x1 is Port ( A : in std_logic.*Page HALF ADDER  HALF_ADDER is ' (A. 2x4 DECODER  DECODER2x4  ' (A. RST:  STD_LOGIC. SUM. CLK. COUT:  BIT).

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Its syntax is the following: ARCHITECTURE architecture_name OF entity_name IS [declarations] BEGIN (code) END architecture_name. ·. 6. an entity is described as a set of interconnected components. identifier  p name  |   | |  | . and the code part (from BEGIN down).Any combination of the above three.As a set of interconnected components (to represent structure). the name of an architecture can be basically any name (except VHDL reserved words).As a set of sequential assignment statements (to represent be-hav.As a set of concurrent assignment statements (to represent dataflow). including the same name as the entity¶s. The internal details of an entity are specified by an architecture body using any of the following modeling styles: c. where signals and constants (among others) are declared. *. As shown above. Like in the case of an entity. an architecture has two parts: a declarative part (optional). ( * In the structural style of modeling.ior).$#%$ # The ARCHITECTURE is a description of how the circuit should behave (function).

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 [ | p psimple_name ] . |   | |  | .

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block_declarative_item ::= `  |p| | `  | pp| | `pp| |  `| p| | ` |p| | ||`p| |  p p| | .

  P a AER HAF ge    HASïRUCïURE of HAFAER   XOR2  (X. M:  Bï. N:  Bï).      (.   . :  Bï. Z:  Bï).

COUï:  Bï).N2:  Bï. S1:  Bï). B.S1:  Bï. FU AER    FASïRUCï of FUAER   XOR1  (A.B:  Bï. CARR). A1: AN2   (A. B.CN:  Bï.  HASïRUCïURE.    XOR2  (S1. SUM:  Bï).      (N1.      (A. SUM). N1:  Bï). X1: XOR2   (A.B:  Bï. N2:  Bï).      (CN.   .

SUM).    NAN3  (A. S1). C:  Bï.N2). A1: AN1   CN.COUï)  FASïRUCï. X1: XOR1  (A. 01: OR1 pot map (N1. . A1: XOR2   (S1.    ABAR.B. Z:  Bï).CN.S1.N2. 2x4 ECOER    ECSïR  ECOER2x4   NV  (A:  Bï. B. Z:  Bï). A2: AN2 pot map (A. BBAR: Bï.N1). B.

N1: NAN3   (ABAR. BBAR. N0: NAN3   (ABAR. ABAR). . Z(0)). ENABE. B. ENABE. Z(1)). 1: NV   (B. 0: NV   (A. BBAR).

Z(2)).  DEC_STR呑 MUX 2x1  MUX_STRUCT of mux2to1 ' AND1 ' (A. Z(3)). N3: NAND3 ' ' (A. S2:  BIT).  '3 ' INV ' (SEL:  BIT. OR: OR ' ' (S1.SEL).  '3 ' 7 ' (S1.B). ENABLE.S2:  BIT.6Page N2: NAND3 ' ' (A.SELBAR:  BIT.  '3 )* I0: INV ' ' (SEL. B. K:  BIT). MUX_STRUCT DFF . A2: AND2 ' ' (SELBAR. SELBAR).  '3 * SELBAR: BIT. A1: AND1 ' ' (A. S1:  BIT). ENABLE. Z:  BIT).SEL:  BIT.S2). ' · ' (B. BBAR.

t e flow of data t oug t e entity is expessed pimaily using concuent signal assignment statements. HAF AER    HAdataflow of HA . but it can be implicitly deduced. ï e stuctue of t e entity is not explicitly specified in t is modeling style.ÕPage  ë ! n t is modeling style.

CARR <= A  B   4 ns. x3. x4.  HAdataflow. . SUM <= A  B   8 ns. FU AER    FAdataflow OF fulladde S  x1. y1 : Bï. x2.

. 2x4 ECOER    decdataflgw  ECOER2x4   ABAR. x1 <= a AN b. S<= y1 XOR cayin. x4 <= x1 OR x2. BBAR: Bï. Cout<= x3 OR x4. y1 <= a XOR b. x3 <= b AN cayin. x2 <= a AN cayin.  FAdataflow.

ABAR "#  A.  ECAïAFOWå . Z(1 ) "#  (ABAR  B  ENABE). Z(3) Ú  (A  B  ENABE). BBAR "#  B. Z(0) Ú   (ABAR  BBAR  ENABE). Z(2) "#  (A  BBAR  ENABE).

x2.SELBAR : BIT. x2 <= SELBAR AND B. that are specified inside a process statement. This set of sequential statements. do not explicitly specify the structure of the entity but merely specifies its functionality. the behavioral style of modeling specifies the behavior of an entity as a set of statements that are executed sequentially in the specified order. A process statement is a concurrent statement that can appear within an architecture body. OUT<= x1 OR x2.DPage MUX 2x1 MUX_dataflow OF MUX_2to1 IS *x1. )* x1 <= A AND SEL . HALF ADDER ‘ . DFF + (  * In contrast to the styles of modeling described earlier. MUX_dataflow.

$  P a g e FU AER ‘ 2x4 ECOER     % & of ECOER2x4  .

B.   (A. ENABE) .

. ABAR. BBAR: Bï.

if (ENABE = '1') t en Z(3) "#  (A  B): Z(0) "#  (ABAR  BBAR). BBAR := not B. Z(2) "#  (A  BBAR). ABAR :=  A.   '"# ((         MUX 2x1 ‘ . Z(1 ) <= not (ABAR  B).

and optionally assign it a value. However in this case. and a set of future values. The object COUNT is also declared to be of Ä| |p class. Every data object belongs to one of the following three classes: c. its type. It is created by means of an object declaration.‘ Object declarations (how to associate types with objects)  $ 8#%$( A data object holds a value of a specified type. BUS_WIDTH: INTEGER := 8: . An example is +)COUNT: INTEGER.‘ Literals 3. %  Examples of constant declarations are RISE_TIME: TIME := 10ns. This value is assigned to the object before simulation starts and the value cannot be changed during the course of the simulation.Constant:An object of constant cla^s can hold a single value of a given type.‘ Data objects 2.  3  '3  LS_DFF_BEH. CLK) )*  (CLK = '1')  Q <= D. This results in the creation of a data object called COUNT which can hold integer values. Some examples of object declarations of various types and classes follow. Signal objects are typically used to model wires and flip-flops while variable and constant objects are typically used to model the behavior of the circuit. Signal objects can be regarded as wires in a circuit while variable and constant objects are analogous to their counterparts in a high-level programming language like C or Pascal.?ariable An object of variable class can also hold a single value of a given type. cc  P a g e DFF  LS_DFF_BEH  LS_DFF  )* ' (D. a current value. 6.      ** 1. different values can be assigned to the object at different times using a variable assignment statement. ·.‘ Operators 4. and its class. An  p p| | ` used to declare an object. Future values can be assigned to a signal object using a signal assignment statement.þignal:An object belonging to the signal class has a past history of values.

These are constant objects. An example of such an implicit declaration for the loop index in a . *DATA_BUS: BIT_VECTOR(0 to 7). 6. When simulation starts. If no initial value is specified for a variable object. where T is the object type and LEFT is a predefined attribute of a type that gives the leftmost value in the set of values belonging to type T. *CLOCK: BIT. The second constant declaration declares a constant BUS_WIDTH of type INTEGER with a value of 8.c·  P a g e The first declaration declares the object RISE_TIME that can hold a value of type TIME (a predefined type in the language) and the value assigned to the object at the start of simulation is 10 ns. Function parameters are constant objects or signal objects while procedure parameters can belong to any object class. (*  Here are some examples of signal declarations. In the third declaration. 0).' statement is shown.generics of an entity . There are two other types of objects that are implicitly declared. an explicit initial value has been assigned to the variable SUM. All ports are signal objects. The first declaration specifies a variable object CTRL_STATUS as an array of II elements. .   )9 Not all objects in a VHDL description are created using object declarations. with each array element of type BIT. The complete constant declaration with the associated value must appear in the corresponding package body.formal parameters of functions and procedures.. In the second declaration. SUM will have an initial value of 10. loop statement and the generate statement. a default value is used as an initial value. These other objects are declared as c. ·.  . The first signal declaration declares the signal object CLOCK of type BIT and gives it an initial value of '0' ('0' being the leftmost value of type BIT). the initial values assigned to FOUND and DONE at start of simulation is FALSE (FALSE is the leftmost value of the predefined type. COUNT  c  10 ' SUM := SUM + COUNT.ports of an entity. +)FOUND. *. +)SUM: INTEGER * O 100 := 10. This default value is T'LEFT. BOOLEAN). The interpretation for these signal declarations is very similar to that of the variable declarations. The initial value for all the array elements of CTRL_STATUS is '0'. *GATE_DELAY: TIME := 10 ns. DONE: BOOLEAN.  '3 ..a file declared by a file declaration. Such a constant is called a p p p  `|  and it can appear only inside a package declaration. Variable Declarations Examples of variable declarations are +)CTRL_STATUS: BIT_VECTOR(10 . . The value of the constant has not been specified in this case. These are the indices of a for. The third signal declaration declares a signal object GATE_DELAY of type TIME that has an initial value of 10 ns. An example of another form of constant declaration is NO_OF_INPUTS: INTEGER.

object COUNT has an implicit declaration of type INTEGER with range I to 10.. need not be explicitly declared. The object COUNT is created when the loop is first entered and ceases to exist after the loop is exited.c6  P a g e In this  ..' statement. and therefore. .

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Count. The language defines a set of reserved words. .. A legal character is an upper-case letter (A. or a lower-case letter (a. Also. COUNT. The first character in an identifier must be a letter and the last character may not be an underscore. Z). and CouNT. z). These words. all refer to the same identifier. 9) or the underscore ( _ ) character.. Examples are ² This is a comment. it ends at the end of this line. these are listed in Appendix A.. also called ‰p. Lower-case and upper-case letters are considered to be identical when used in an identifier. the comment extends to the end of the line. a separate ² comment line must be started. . ² To continue a comment onto a second line.I.-two underscore characters cannot appear consecutively. --This comment starts after the entity declaration. Some more examples of identifiers are DRIVE_BUS SelectSignal RAM_Address SET_CK_HIGH CONST32_59 r2d2 Comments in a description must be preceded by two consecutive hyphens (-). . as an example. Comments can appear anywhere within a description.#( An identifier in VHDL is composed of a sequence of one or more characters. or a digit (0 . UART  .

 $ $"#((We have complete MODULE 2 on this«So We¶ll study this later in Detail) . ` have a specific meaning in the language. cannot be used as identifiers. and therefore.

in a physical type and exponent) to be During operators are which case. result type is of the operation has When operands The result is physical type. (multiplication) (absolute)  The result types (subtraction) and / (division) operator is These for all relational operators must operators are defined for any operators are operations is be of the same predefined for both numeric type.. For  and ...e. values '0' and scalar type (e. relational operators. array types.g. the BOOLEAN. . The not comparison is example. in which either a I. characters precedence as U7cU- that of miscellaneous operators. left operand to defined for operators are addition and The multiplication be of integer or one. The also be used as case when one of right operand and remaining four unary the operands is of (i. element values dirnensional a real type object The result of a belong to a array type or an is allowed and the logical discrete type). element type. the /= same numeric The result is also defined for the They are also (inequality) type. division precedence as of the discrete array (concatenation) of an object of a the above two BOOLEAN type (i. arrays operator can be physical type by operators type.c*  P a g e # $( In the order of Increasing Precedence c-* ·- 6- * *- '* ]- - The six logical These are These are These are The operators are : ± v miscellaneous  . The with the result the same integer or (exponentiation) types BIT and = (equality) and being of the floating point type. either an integer or respectively. the same type are discrete always an array Same goes for as its operands.:   operators are  < ‘  |   <: The operands  ‘ vv‘‘  = for the + The * The ) & Ö  (addition) and . bit permitted on any operand and the is of integer or real only. The of the same type. operator has the FALSE and enumerated The operands For the division same TRUE values types) or for the & operator.e. the the second operand of integer type evaluation. operator is BOOLEAN. defined for the always numeric type operands being of The // predefined BOOLEAN. operator is a performed one > >  >> unaiy logical element at a results in an operator and time from left to array of has the same right. The result is The not logical 1' are treated as integer or be the same. type. result type must type. permitted on any subtraction operator is also floating point dimensional type except file operators may defined for the type and the arrays of BIT types. of physical type.

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$# ( c-% Comments in VHDL start with two adjacent hyphens (µ--¶) and extend to the end of the line. ·-. They have no part in the meaning of a VHDL description.

based_integer ] # [ exponent ] base ::= integer based_integer ::= extended_digit { [ underline ] extended_digit } · · p  ‰‰ extended_digit ::= digit | letter The base and the exponent are expressed in decimal. The letters A to F (upper or lower case) are used as extended digits to represent 10 to 15.real literals Based literal numbers are defined by: based_literal ::= base # based_integer [ . so the identifiers cat and Cat are the same.1111_1111_111#E+11 16#F.integer literals 0.0 *-% Literal characters are formed by enclosing an ASCII character in single-quote marks. A string can be used as a value for an object which is an array of characters. 6- ) Literal numbers may be expressed either in decimal or in a base between two and sixteen.the real number 4095. otherwise it represents an integer. To include a double-quote mark itself in a string.5 2.0 0. Identifiers in VHDL are used as reserved words and as programmer defined names. .the integer 196 2#1.4E-9 -. a pair of double-quote marks must be put together. Some examples: 2#1100_0100# 16#C4# 4#301#E1 -. They must conform to the rule: identifier ::= letter { [ underline ] letter_or_digit } Note that case of letters is not considered significant. so This_Name and ThisName are different identifiers. it represents a real number. Decimal literals are defined by: decimal_literal ::= integer [ .718_28 12.FF#E2 -. integer ] [ exponent ] integer ::= digit { [ underline ] digit } exponent ::= E [ + ] integer | E . If the literal includes a point.integer Some examples are: 0 1 123_456_789 987E6 -. The exponent indicates the power of the base by which the literal is multiplied. For example: 'A' '*' ''' ' ' ]-(* Literal strings of characters are formed by enclosing the characters in double-quote marks. Underline characters in identifiers are significant.

Functions perform sequential computations and return a value as the value of the function. When subprograms are provided in a package. Some examples: B"1010110" -. Subprograms may exist as just a procedure body or a function body. see Section 2. Both procedures and functions written in VHDL must have a body and may have declarations. Subprograms may also have a procedure declarations or a function declaration.5). equivalent to B"001_010_110" (   ( There are two kinds of subprograms: procedures and functions. # .c>  P a g e >- (* VHDL provides a convenient way of specifying literal values for arrays of type bit ('0's and '1's. the subprogram declaration is placed in the package declaration and the subprogram body is placed in the package body. O for octal and X for hexadecimal. Functions do not change their formal parameters.length is 7 O"126" -. The syntax is: bit_string_literal ::= base_specifier " bit_value " base_specifier ::= B | O | X bit_value ::= extended_digit { [ underline ] extended_digit } Base specifier B stands for binary.length is 9.2. Procedures perform sequential computations and return values in global objects or by storing values into formal parameters.

VHDL allows two subprograms to have the same name. . their base types and the corresponding formal parameter names (if named association is used) are used to determine which subprogram is meant. If the call is a function call. The subprogram name is then said to be overloaded. suppose we declared the two subprograms: check_limit(value : integer) return boolean. When a subprogram call is made using an overloaded name. the result type is also used. their order. provided the number or base types of parameters differs. Then which of the two functions is called depends on whether a value of type integer or word_8 is used as the actual parameter. For example. check_limit(value : word_32)  boolean. the number of actual parameters.

the addition operator might be overloaded to add word_32 operands by declaring a function: "+" (a.3. for example: "+" (X"1000_0010". However. X"0000_FFD0") . The latter case allows extra operand types to be defined for those operators. Note that it is also possible to call operators using the prefix notation used for ordinary subprogram calls. b : word_32)  word_32 is )* int_to_word_32( word_32_to_int(a) + word_32_to_int(b) ). since its operands are both integers. The designator used to define a subprogram can be either an identifier or a string representing any of the operator symbols listed in Section2. For example. in the expression: X"1000_0010" + X"0000_FFD0" the newly declared function is called. Within the body of this function. since the operands to the addition operator are both of type word_32. "+".c6  P a g e So test := check_limit(4095) would call the first function. and test := check_limit(X"0000_0FFF") would call the second function. the addition operator is used to add integers.

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Two categories of userdefined data types are shown below: integer and enumerated. b). TYPE color IS (red. such data type definitions can be found in the following packages / libraries:  %A #  $ $"#( standard of library std Defines BIT. -. @ * '1 TYPE my_integer IS RANGE -32 TO 32.A user-defined subset of integers or naturals. plus several data conversion functions. -.A user-defined subset of integers.  $'3 @  $'! @  $'! ()'! !  ! ! (*  *  $'!  %+ @  $' VHDL contains a series of pre-defined data types. More specifically. std_logic_signed and std_logic_unsigned of Contain functions library ieee that allow operations with STD_LOGIC_VECTOR data to be performed as if the data were of type SIGNED or UNSIGNED. std_logic_arith of library ieee Defines SIGNED and UNSIGNED data types. BOOLEAN. white). typical of finite state machines. @  '1 TYPE state IS (idle. forward. b). blue. -. -.Another enumerated data type. green. '1'. conv_signed(p. TYPE my_logic IS ('0'. and conv_std_logic_vector(p. and REAL data types. 'Z'). std_logic_1164 of library ieee Defines STD_LOGIC and STD_ULOGIC data types. conv_unsigned(p. . TYPE student_grade IS RANGE 0 TO 100. -. stop). b). respectively. backward. like conv_integer(p).An enumerated data type. specified through the IEEE 1076 and IEEE 1164 standards.A user-defined subset of std_logic. @  $' VHDL also allows the user to define his/her own data types. INTEGER.

my_color=(red. though operations between data of di¤erent types are not allowed.'W'.Recall that STD_LOGIC=('X'. two-dimensional (2D).cD  P a g e The encoding of enumerated types is done sequentially and automatically (unless specified otherwise by a user-defined attribute.'L'. white). or one-dimensional-by-one-dimensional (1Dx1D).As expected. They can also be of higher dimensions.'Z'). blue). my_logic=('0'.'1'.' -'). -. The main reason for using a subtype rather than specifying a new type is that. green. green. -. To specify a new array type: $"# '2 .Since color=(red. -.'Z'. SUBTYPE small_integer IS INTEGER RANGE -32 TO 32. NATURAL is a subtype (subset) of INTEGER. -. then -.'H'.Therefore. SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO 'Z'.'1'. ( $"# is a TYPE with a constraint. they are allowed between a subtype and its corresponding base type. but then they are generally not synthesizable.A subtype of INTEGER.  Arrays are collections of objects of the same type. Examples: SUBTYPE natural IS INTEGER RANGE 0 TO INTEGER'HIGH. They can be one-dimensional (1D). -. SUBTYPE my_color IS color RANGE red TO blue.'0'. blue.

(  " B'  2'3 To make use of the new array type: (.

a SIGNAL was declared.  *21 '2 C1: 2+D3 In the syntax above. However. Notice that the initial value is optional (for simulation only). . it could also be a CONSTANT or a VARIABLE.

(*  *  $' As mentioned earlier. DOWNTO 0). Notice that their syntax is similar to that of STD_LOGIC_VECTOR.std_logic_arith.legal (arithmetic operation OK) . SIGNAL x: OUT STD_LOGIC_VECTOR (7 .all. Since TYPE declarations are not allowed in an ENTITY.all. of the ieee library.std_logic_1164. they accept arithmetic operations. Their syntax is illustrated in the examples below. With respect to relational (comparison) operations. we might need to specify the ports as arrays of vectors. -.. #&'1 *  * ' *E*  '.. Despite their syntax. SIGNAL a: IN SIGNED (7 DOWNTO 0). required USE ieee. USE ieee. SIGNAL b: IN STD_LOGIC_VECTOR (7 SIGNAL b: IN SIGNED (7 DOWNTO 0).std_logic_1164. -. there are no restrictionsK‘ #&'1 *  * ' . necessary SIGNAL a: IN STD_LOGIC_VECTOR (7 .. Example: TYPE birthday IS RECORD day: INTEGER RANGE 1 TO 31. logical operations are not allowed..·7  P a g e   As we have seen.legal (logical operation OK) . SIGNED and UNSIGNED data types are intended mainly for arithmetic operations. END RECORD.. -..illegal (arithmetic operation not OK) w <= a AND b. Examples: SIGNAL x: SIGNED (7 DOWNTO 0). v <= a + b.all. To use SIGNED or UNSIGNED data types. the std_logic_arith package. LIBRARY ieee. with the only di¤erence that they contain objects of di¤erent types. month: month_name.  Records are similar to arrays. these types are defined in the std_logic_arith package of the ieee library. there are no pre-defined data types of more than one dimension. SIGNAL y: UNSIGNED (0 TO 3). in the specification of the input or output pins (PORTS) of a circuit (which is made in the ENTITY). DOWNTO 0).extra package . -.. DOWNTO 0).no extra package USE ieee. 2*2+- LIBRARY ieee. which will then be visible to the whole design (thus including the ENTITY). that is. the solution is to declare user-defined data types in a PACKAGE. not like that of an INTEGER. -. -. On the other hand. . must be declared. as one might have expected.illegal (logical operation not OK) v <= a + b. SIGNAL x: OUT SIGNED (7 DOWNTO 0). w <= a AND b. contrary to STD_LOGIC_VECTOR. However..

Example: Arithmetic operations with std_logic_vector. respectively.legal (logical operation OK)  $ % #(. which allow operations with STD_LOGIC_VECTOR data to be performed as if the data were of type SIGNED or UNSIGNED.legal (arithmetic operation OK). -.all. SIGNAL b: IN STD_LOGIC_VECTOR (7 DOWNTO 0).extra package included SIGNAL a: IN STD_LOGIC_VECTOR (7 DOWNTO 0).std_logic_1164. LIBRARY ieee.. unsigned w <= a AND b. . For that.std_logic_unsigned. USE ieee.. std_logic_signed and std_logic_unsigned. USE ieee. there is a simple way of allowing data of type STD_LOGIC_VECTOR to participate directly in arithmetic operations. v <= a + b.all. -. the ieee library provides two packages.·c  P a g e Despite the constraint mentioned above. -. SIGNAL x: OUT STD_LOGIC_VECTOR (7 DOWNTO 0).

r‘ +22*2+B'! ) 1 Converts a parameter p of type INTEGER. then the std_logic_1164 of the ieee library provides straightforward conversion functions. r‘ +2*B'! ) 1 Converts a parameter p of type INTEGER. despite being declared as belonging to two different type classes).error. -.. TYPE long IS INTEGER RANGE -100 TO 100. or we invoke a FUNCTION from a pre-defined PACKAGE which is capable of doing it for us. or STD_ULOGIC to an INTEGER value. They are: r‘ +2*B' : Converts a parameter p of type INTEGER. SIGNED. SIGNAL x : short. y <= 2*x + 5. etc. or STD_ULOGIC to an UNSIGNED value with size b bits.OK. Example: Legal and illegal operations with subsets.SIGNED. or STD_ULOGIC to a SIGNED value with size b bits. ( VHDL does not allow direct operations (arithmetic. result converted into type long Several data conversion functions can be found in the std_logic_arith package of the ieee library.) between data of different types. -. it is often necessary to convert data from one type to another. r‘ +2*B'! ) 1 Converts a parameter p of type INTEGER. UNSIGNED. SIGNED. or STD_LOGIC to a STD_LOGIC_VECTOR value with size b bits. If the data are closely related (that is. UNSIGNED.. . SIGNAL y : long. logical. Therefore. This can be done in basically two ways: or we write a piece of VHDL code for that. Notice that STD_LOGIC_ VECTOR is not included. UNSIGNED. both operands have the same base type. UNSIGNED. . TYPE short IS INTEGER RANGE -10 TO 10. SIGNED. type mismatch y <= long(2*x + 5).

.. SIGNAL a: IN UNSIGNED (7 DOWNTO 0). 8).std_logic_arith. . LIBRARY ieee. USE ieee. -.all.8-bit STD_LOGIC_VECTOR value.. y <= CONV_STD_LOGIC_VECTOR ((a+b). USE ieee.. .all. SIGNAL y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0). SIGNAL b: IN UNSIGNED (7 DOWNTO 0).. then assigned to y.std_logic_1164.··  P a g e Example: Data conversion.Legal operation: a+b is converted from UNSIGNED to an -.

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The initial value is not synthesizable. A PROCESS must be installed in the main code. (. FUNCTIONS. Sequential code is also called behavioral code. PROCESSES.]] BEGIN (sequential code) END PROCESS [label]. If used. and PROCEDURES are the only sections of code that are executed sequentially. WAIT. being only taken into consideration in simulations. and is executed every time a signal in the sensitivity list changes (or the condition related to WAIT is fulfilled). as a whole. One important aspect of sequential code is that it is not limited to sequential logic. except VHDL reserved words. [label:] PROCESS (sensitivity list) [VARIABLE name type [range] [:= initial_value. Indeed.  %#( VHDL code is inherently concurrent. or LOOP. CASE. and by a sensitivity list (except when WAIT is used). Its purpose is to improve code readability. any of these blocks is still concurrent with any other statements placed outside it. as indicated in the syntax above). It is characterized by the presence of IF. However. The use of a label is also optional. Its syntax is shown below. they must be declared in the declarative part of the PROCESS (before the word BEGIN. The label can be any word. with it we can build sequential circuits as well as combinational circuits. %#(( A PROCESS is a sequential section of VHDL code. VARIABLES are optional.

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. Therefore. then it must be assigned to a SIGNAL. A SIGNAL can be declared in a PACKAGE. while the value of the former can be global. That is not the case with a SIGNAL (when used in a PROCESS). while A VARIABLE canonly be declared inside a piece of sequential code (in a PROCESS. that is. the latter is always local.ENTITY or ARCHITECTURE (in its declarative part). if necessary. the update of a VARIABLE is immediate. The value of a VARIABLE can never be passed out of the PROCESS directly. On the other hand. for example). #( VHDL has two ways of passing non-static values around: by means of a SIGNAL or by means of a VARIABLE. we can promptly count on its new value in the next line of code.

·*  P a g e for its new value is generally only guaranteed to be available after the conclusion of the present run of the PROCESS. (.

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It does not correspond to any real delay and actual simulation time does not advance. events can occur at 15 ns. # * ( @ Ä| |p  p  p p`` . 27 ns+A. 15 ns+2A. Delta delay allows for ordering of events that occur at the same simulation time during a simulation. 22 ns. for example. Therefore. 27 ns. This delay models hardware where a minimal amount of time is needed for a change to occur. in performing zero delay simulation. 15 ns+3A.   A p| p| ` a very small delay (infinitesimally small). 15 ns+IA. For example. an event always occurs at a real simulation time plus an integral multiple of delta delays. . and so on. 22 ns+A. Each unit of simulation time can be considered to be composed of an infinite number of delta delays. .

For example.$ The .  `p `Ä ` .  p| p p`` . . There are three basic forms of the wait statement.  p p p`` . . . They may also be combined in a single wait statement. statement provides an alternate way to suspend the execution of a process.

  `p `Ä `  p| p p``  p p p``  Some examples of . statements are . C. -. -.  (SUM > 100)  50 ms.·]  P a g e .statement 1 .statement 4 .statement 5 .statement 2 . -.  CLOCK  20ns.  A. B.  10ns. -.statement 3 .  (A = B). -.

 An if statement selects a sequence of statements for execution based on the value of a condition. WHEN value => assignments.. and WAIT). The if statement can have zero or more else if clauses and an optional else clause. END CASE. An if statement is also a sequential statement. Its syntax is shown below. the set of sequential statements associated with this condition is executed. . % (# CASE is another statement intended exclusively for sequential code (along with IF. The condition can be any expression that evaluates to a boolean value..LOOP. the previous syntax allows for arbitrary nesting of if statements. then. % (# p  p IS WHEN value => assignments. The general form of an if statement is p| p p`` p `pp | `|pp ` [ p| p p``  `pp | `|pp ` ] [ `pp | `|pp ` ]  3 The if statement is executed by checking each condition sequentially until the first true condition is found. and therefore. .

Z <= TEMP  MUX_DELAY. B. C."11" => TEMP := D.# . . MUX  '(A. D.  ."01" => TEMP := B. % (# + . CTRL:  BIT_VECTOR(0  1). )* CTRL  .·>  P a g e A model for a 4*1 multiplexer using a case statement is shown next. . C. )* PMUX: ' (A. MUX_BEHAVIOR.  ' PMUX. CTRL) +)TEMP: BIT."00" => TEMP := A: . D:  BIT. MUX_BEHAVIOR  MUX  MUX_DELAY: TIME := 10 ns."10" :> TEMP := C. B. MUX. Z:  BIT).

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 a' statement is used to iterate through a set of sequential statements. this will generally not happen.  E 1 $ '  '  & )  - V  ‘‘  . the general tendency is for a circuit synthesized from a VHDL code based on IF not to di¤er from that based on CASE. For instance. Though in principle the presence of ELSE in the IF/ELSE statement might infer the implementation of a priority decoder (which would never occur with CASE). a multiplexer might be inferred instead. Therefore. when IF (a sequential statement) is used to implement a fully combinational circuit. after optimization. One example of this statement's use is in an if statement or in a case statement where for certain conditions.  The statementH3Iis a sequential statement that does not cause any action to take place and execution continues with the next statement. p syntax of a loop statement is [  |p : ] p | `pp ' `pp | `|pp `  ' [  |p ] . it may be useful or necessary to explicitly specify that no action needs to be performed. There are three types of iteration schemes.

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. the consequences can be more serious because incomplete specifications of the output signals might cause the synthesizer to infer latches in order to hold their previous values. registers are necessary. so will be inferred by the compiler. the compiler might display a message of the type µµsignal does not hold value after clock edge¶¶ or similar. for example²appendix A). * (F %  * %) % We have already seen that sequential code can be used to implement either sequential or combinational circuits. the circuit¶s complete truthtable can be obtained (indeed.  å‘  %4* The compiler will generally not be able to synthesize codes that contain assignments to the same signal at both transitions of the reference (clock) signal (that is. Failing to comply with rule 1 will generally cause the compiler to simply issue a warning saying that a given input signal was not included in the sensitivity list. however. With respect to rule 2. This is particularl y true when the target technology contains only single-edge flip-flops (CPLDs. Rule 2: Make sure that all combinations of the input/output signals are included in the code. In the former case. In order to satisfy the criteria above. In this case. it is a good design practice to always take rule 1 into consideration. and then proceed as if the signal were included. This fact is illustrated in the example below. at the rising edge plus at the falling edge). However. then the complete truth-table should be clearly specified in the code. make sure that. that is. this should not happen in the latter case. the following rules should be observed: Rule 1: Make sure that all input signals used (read) in the PROCESS appear in its sensitivity list. this is true for both sequential as well as concurrent code). if the code is intended for a combinational circuit. by looking at the code. Moreover. Even though no damage is caused to the design in this case.

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). Micopogamming is an odely met od of designing t e contol unit of a conventional compute (Wil es 1951). . Eac step is called    and complete set of steps equied to pocess a mac ine instuction is called t e   .   ) ) ë)* .0 ! 1 | . ï e tem micopogamming is based on t e analogy between sequence of tansfe equied to execute a mac ine instuction and t e sequence of individual instuctions in conventional use pogam.  /    !.

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n t e BMCU we use a ³one.ot´ code to select t e condition signal. t e values of contol signals ae ead fom an appopiate addess location in a ROM (instead of being geneated by combinational logic gates). ï e contents of eac addess in t e ROM ae called a ct l        5 We use two-way banc ing addess geneation Eac contol wod contains 64 bits of data ï e condition select field (CW(63:40)) contains infomation needed to select t e input condition signal t at is used to compute t e addess of t e next instuction. .      *) 1    n a ic p   ct lit.

If Ci = 0. and limits imposed by the address generation logic. ROM size is 256 words. then the memory address [MAR] is incremented to compute the next address. the number of status signals that can be handled. Every designer must observe the constraints imposed by the controller.  * * The correct sequence of control signals is obtained by generating the proper sequence of addresses at the ROM inputs.6c  P a g e If Ci is selected and Ci = 1 then address NAD field is the address of the next control word to be fetched. The address generating logic varies considerably from design to design and is a major contributor to the constraints imposed by the controller. The maximum number of control signals is 32. Timing signals for the control unit and the data unit must be closely coordinated. % . These constraints include such things as the number of control signals that can be generated. .

Usually. 2. 3.  * * *K B&' Address Generation Logic for BMCU ianbeesignesingaeitorlti lexer. .‘ Make a list of the conditions from step 1. After the assignment of ROM addresses to states. (  '*  1. the AG can be a low complexity circuit. If the controller usually goes to the next higher sequential address for the next set of control signal values (increment) with just an occasional need to parallel load a new address (branch).‘ Prepare a table showing all transitions from each state and the conditions that define each transition by scanning the statements in the VHDL description.‘ Identify a reset state.6·  P a g e The controller works best if the sequencing of addresses is relatively simple. the address generating logic circuit (AG) is a counter with the option to parallel load a new address when one wishes to jump to a new point in the control sequence. some of these conditions may not be needed.

6. 5.66  P a g e 4.‘ Remove the redundant signals from the condition list created in step2 and assign the condition signals to the condition inputs in an arbitrary manner. 7. This procedure is similar to that performed by an assembler program.  (.‘ From the list of transfers and outputs created in step 6.‘ Determine the ROM program using the information in the lists produced in steps 1-8. 9.‘ Draw a block diagram showing the condition and control signals produced.‘ Create a list of transfers during each state and a list of outputs required during each state.‘ Assign a ROM address to each state. generate a list of control signals needed to time the transfers and outputs. 8.

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