EE 671

8 bit Carry Bypass Adder
Group 8

Ashay Shah 07d07024 Kaustubh Joshi 09307610

allows us to create blocks of full adders. The Manchester chain carry adder itself is useful only when it is used in block of four bits or so. where carry signals are generated at some positions. . divided into 2 blocks. In the best case. If the carry is propagated at all positions in the block. it was decided to create an 8-bit adder using carry bypass on two blocks of four bits so as to exploit the full power of both the Manchester carry chain and the carry bypass logic. This forms the basis of the carry bypass adder.e. the addition time will only take into account the time to propagate the carry signal. as if it had been generated at the beginning of the block. 5. With a Ripple Carry Adder. 3. the propagation time can be variable. They are divided into blocks. We decided to choose the Manchester chain carry adder because the bypass adder. The carry bit is the slowest to propagate in a standard ripple adder. In this case. unlike the ripple adder. if the input bits Ai and Bi are different for all position i. Hence. 2. According to the assignment. Theory: Depending on the position at which a carry signal has been generated. the Ripple Carry Adder is as slow as it is large.Principle of operation 1. it starts to propagate through the block. Carry Skip Adders take advantage both of the generation or the propagation of the carry signal. The signal produced by this circuit will be called block propagation signal. Note that when A⊕B = 1. and the addition is completed when the carry signal has propagated through the whole adder. when there is no carry generation. where a special circuit detects quickly if all the bits to be added are different (Pi = 1 in all the block). we are required to create an 8-bit carry bypass adder using one of the full adders created apriori. As soon as the carry signal is transmitted to a block. one and only one of the inputs is high. The carry bypass adder uses a small external circuitry to speed up carry propagation in certain conditions. Circuit Specifications 1. Ripple Carry Adders are fast only for some configurations of the input words. 3. then the carry signal entering into the block can directly bypass it and so be transmitted through a multiplexer to the next block. then the carry signal is propagated at all positions (thus never generated). 4. Thus. i. Actually. 2. we can save propagation time by bypassing the carry generating circuit for this specific case. Figure shows the structure of a 8-bits Carry Skip Adder. 4. the carry directly propagates through a 1 bit full adder.

Tadder = tsetup + Mtcarry + ((N/M-1) x tbypass) + (M-1)tcarry + tsum Where M = number of bit is each block. (for our circuit M = 4) tsetup = time for G & P Generation tcarry = Propagation delay through single bit. tbypass = Delay through MUX tsum = time for final stage of sum evaluation Circuit Diagram Block Diagram 4 bit MCCA Cin 4 bit MCCA Cout Carry Skip Logic P0P1P2P3 P4P5P6P7 4 Bit MCCA ...

98mW Power Delay Product: 3.Output Values: Inverter CMOSP Lp = 0.294pW Output .38µ Delay : 47.8V Vol = 0.18 µ Wn = 0.012V Power Dissipation: 10.15ps 1-Bit MCCA Delay: 51.18µ Wp = 0.80µ CMOSN Ln = 0.3015ps 8-Bit MCCA Carry Bypass Adder Delay : 300ps (Worst Case) Voh = 1.

Spice files were then extracted from the layout so as to include parasitic components.Layout 1. 3. Layout was implemented using the open source software “MAGIC” 2. 4-bit MCCA Propagate and Generate Circuit . The layouts were then optimized to match the response of the original design.

Carry Skip Block .

Net Layout Block .

These parameters are not considered in the original spice design 3. 4.8mW 540(mW-ps) 650ps (Worst Case) 1.012V 1.8V 0. Since parasitic capacitances increase both the power and delay in a circuit. 2. Original Layout Inverter Delay 47. A comparison of the original and final parameters is given.80ps 8-Bit MCCA Carry Bypass Adder Delay VOH VOL Power Dissipation Power Delay Product 300ps (Worst Case) 1.5mW 975(mW-ps) . The layout adds parasitic components to the circuit.15ps 53.Layout Circuit Output Comparison of Outputs 1. the output of the extracted spice files is worse than that of the original circuit.798V 0V 1.

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