EE 671

8 bit Carry Bypass

Adder
Group 8

Ashay Shah 07d07024

Kaustubh Joshi 09307610
Principle of operation
1. The carry bit is the slowest to propagate in a standard ripple adder.
2. The carry bypass adder uses a small external circuitry to speed up carry propagation in certain
conditions.
3. Note that when A⊕B = 1; i.e. one and only one of the inputs is high, the carry directly propagates
through a 1 bit full adder.
4. Hence, we can save propagation time by bypassing the carry generating circuit for this specific
case.
5. This forms the basis of the carry bypass adder.

Circuit Specifications
1. According to the assignment, we are required to create an 8-bit carry bypass adder using one of
the full adders created apriori.
2. We decided to choose the Manchester chain carry adder because the bypass adder, unlike the
ripple adder, allows us to create blocks of full adders.
3. The Manchester chain carry adder itself is useful only when it is used in block of four bits or so.
4. Thus, it was decided to create an 8-bit adder using carry bypass on two blocks of four bits so as
to exploit the full power of both the Manchester carry chain and the carry bypass logic.

Theory:
Depending on the position at which a carry signal has been generated, the propagation time can
be variable. In the best case, when there is no carry generation, the addition time will only take into
account the time to propagate the carry signal.

With a Ripple Carry Adder, if the input bits Ai and Bi are different for all position i, then the carry
signal is propagated at all positions (thus never generated), and the addition is completed when the
carry signal has propagated through the whole adder. In this case, the Ripple Carry Adder is as slow as it
is large. Actually, Ripple Carry Adders are fast only for some configurations of the input words, where
carry signals are generated at some positions.

Carry Skip Adders take advantage both of the generation or the propagation of the carry signal.
They are divided into blocks, where a special circuit detects quickly if all the bits to be added are
different (Pi = 1 in all the block). The signal produced by this circuit will be called block propagation
signal. If the carry is propagated at all positions in the block, then the carry signal entering into the block
can directly bypass it and so be transmitted through a multiplexer to the next block. As soon as the carry
signal is transmitted to a block, it starts to propagate through the block, as if it had been generated at
the beginning of the block. Figure shows the structure of a 8-bits Carry Skip Adder, divided into 2 blocks.
 Tadder = tsetup + Mtcarry + ((N/M-1) x tbypass) + (M-1)tcarry + tsum

Where

M = number of bit is each block... (for our circuit M = 4)

tsetup = time for G & P Generation
tcarry = Propagation delay through single bit.
tbypass = Delay through MUX
tsum = time for final stage of sum evaluation

Circuit Diagram
Block Diagram

4 bit MCCA 4 bit MCCA

Cin Cout

P0P1P2P3 P4P5P6P7
Carry Skip Logic

4 Bit MCCA
Output Values:
Inverter
CMOSP Lp = 0.18µ Wp = 0.80µ
CMOSN Ln = 0.18 µ Wn = 0.38µ
Delay : 47.15ps
1-Bit MCCA
Delay: 51.3015ps

8-Bit MCCA Carry Bypass Adder

Delay : 300ps (Worst Case)
Voh = 1.8V
Vol = 0.012V
Power Dissipation: 10.98mW
Power Delay Product: 3.294pW
Output
Layout
1. Layout was implemented using the open source software “MAGIC”
2. Spice files were then extracted from the layout so as to include parasitic components.
3. The layouts were then optimized to match the response of the original design.

4-bit MCCA

Propagate and Generate Circuit

Carry Skip Block
Net Layout Block
Layout Circuit Output

Comparison of Outputs
1. The layout adds parasitic components to the circuit.
2. These parameters are not considered in the original spice design
3. Since parasitic capacitances increase both the power and delay in a circuit, the output of the
extracted spice files is worse than that of the original circuit.
4. A comparison of the original and final parameters is given.
Original Layout
Inverter
Delay 47.15ps 53.80ps
8-Bit MCCA Carry
Bypass Adder
Delay 300ps (Worst Case) 650ps (Worst Case)
VOH 1.8V 1.798V
VOL 0.012V 0V
Power Dissipation 1.8mW 1.5mW
Power Delay Product 540(mW-ps) 975(mW-ps)