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# HDL LAB IV Sem EC/TE

EXPERIMENT 1

## HDL code to realize all logic gates

AIM: To Simulate and realize all logic gates.
COMPONENTS REQUIRED: FPGA board, FRC’s and power supply.
THEORY :A logic gate is an electronic circuit/device which makes the logical decisions
alternatively a logic gate performs a logical operation on one or more logic inputs and
produces a single logic output. The logic normally performed is Boolean logic and is most
commonly found in digital circuits. Logic gates are primarily implemented using diodes or
transistors. The logic gates are broadly classified into 3 types:
Basic gates: AND, OR, NOT / INVERTER
Universal gates: NAND, NOR
Special gates: XOR, XNOR
Truth table with symbols

## Dept. of EC/TE, VKIT 2010 Page 1 of 64

HDL LAB IV Sem EC/TE
Generalizing,
c
a d
e
f
LOGIC
b g
GATES
h
i

Truth Table
inputs outputs
a b c d e f g h i
0 0 0 0 1 1 1 0 1
0 1 0 1 1 1 0 1 0
1 0 0 1 0 1 0 1 0
1 1 1 1 0 0 0 0 1

## VHDL CODE VERILOG CODE

library ieee; module allgates ( a, b, c, d, e, f, g, h, i);
use ieee.std_logic_1164.all; input a, b;
use ieee.std_logic_arith.all; output c, d, e, f, g, h, i;
use ieee.std_logic_unsigned.all; assign c = a & b;
assign d = a | b,
entity allgates is assign e = ~a ,
port ( a, b : in std_logic; assign f = ~(a & b),
c, d, e, f, g, h, i : out std_logic); assign g = ~(a | b),
end allgates; assign h = a ^ b;
assign i = ~(a ^ b);
architecture dataflw of allgates is endmodule
begin
c<= a and b;
d<= a or b;
e<= not a;
f<= a nand b;
g<= a nor b;
h<= a xor b;
i<= a xnor b;
end dataflw;

## Dept. of EC/TE, VKIT 2010 Page 2 of 64

HDL LAB IV Sem EC/TE
Simulation Result
Before Execution

After Execution

## User Constraint File

net “a” loc = “p74”;
net “b” loc = “p75”;
net “c” loc = “p84”;
net “d” loc = “p85”;
net “e” loc = “p86”;
net “f” loc = “p87”;
net “g” loc = “p88”;
net “h” loc = “p89”;
net “i” loc = “p90”;

## Dept. of EC/TE, VKIT 2010 Page 3 of 64

HDL LAB IV Sem EC/TE
EXPERIMENT 2
HDL codes to design and simulate combinational circuits

## COMPONENTS REQUIRED: FPGA board, FRC’s and power supply.

THEORY : A decoder is a multiple input, multiple output logic circuit that converts coded
inputs into coded outputs where the input and output codes are different. The enable inputs
must be ON for the decoder to function, otherwise its outputs assumes a ‘disabled’ output
code word. Decoding is necessary in applications such as data multiplexing, seven segment

a) 2 to 4 Decoder
Block Diagram

y0
Sel 0
Sel 1 2 to 4 y1
y2
en Decoder y3

Truth Table
inputs outputs
en Sel1=a Sel0=b y3 y2 y1 y0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
0 x x 0 0 0 0

## VHDL CODE VERILOG CODE

library ieee; module dec2_4 (y, sel, en);
use ieee.std_logic_1164.all; input en;
use ieee.std_logic_arith.all; input [1:0] sel;
use ieee.std_logic_unsigned.all; output [3:0]y;
reg [3:0]y;
always@(sel)
entity dec2_4 is begin
port (en :in std_logic ; if(en= =1)
sel : in std_logic_vector(1 downto 0); if (sel= =0) y = 4’b0001; else
y : out std_logic_vector(3 downto 0)); if (sel= =1) y = 4’b0010; else
end dec2_4; if (sel= =2) y = 4’b0100; else
if (se = =3) y = 4’b1000; else
architecture dec2 of dec2_4 is y = 4’bx;
begin end
process(en, sel) endmodule

## Dept. of EC/TE, VKIT 2010 Page 4 of 64

HDL LAB IV Sem EC/TE
begin
if(en ='1') then
y <= "0000";
else
case sel is
when "00"=> y <= "0001";
when "01"=> y <= "0010";
when "10"=> y <= "0100";
when "11"=> y <= "1000";
when others => null;
end case;
end if;
end process;
end dec2;

Simulation Result
Before Execution

After Execution

## net “en” loc = “p74”;

net “sel0” loc = “p75”;
net “sel1” loc = “p76”;
net “y0” loc = “p84”;
net “y1” loc = “p85”;
net “y2” loc = “p86”;
Dept. of EC/TE, VKIT 2010 Page 5 of 64
HDL LAB IV Sem EC/TE
net “y3” loc = “p87”;
b. 8 to 3 encoder without priority
THEORY : An encoder is a digital circuit which performs the inverse of decoder. An
encoder has 2N input lines and N output lines. In encoder the output lines generate the binary
code corresponding to input value. The decimal to BCD encoder usually has 10 input lines
and 4 output lines. The decoder decimal data as an input for decoder an encoded BCD output
is available at 4 output lines.
Block Diagram Truth Table

e I7 I6 I5 I4 I3 I2 I1 I0 y y y0
i7 n 2 1
y2 1 x x x x x x x x 1 1 1
y 0 1 1 1 1 1 1 1 1 1 1 1
1 8:3 0 1 1 1 1 1 1 1 0 1 1 1
Priority y 0 1 1 1 1 1 1 0 x 1 1 0
0 Encoder 0 1 1 1 1 1 0 x x 1 0 1
i0 0 1 1 1 1 0 x x x 1 0 0
i0 0 1 1 1 0 x x x x 0 1 1
0 1 1 0 x x x x x 0 1 0
en 0 1 0 x x x x x x 0 0 1
0 0 x x x x x x x 0 0 0
VHDL CODE VERILOG CODE
library ieee; module enc8_3 (i, en, y);
use ieee.std_logic_1164.all; input [7:0]i;
use ieee.std_logic_arith.all; input en;
use ieee.std_logic_unsigned.all; output [2:0]y;
reg [2:0]y;
entity enc83 is always @ (en, i)
port (en : in std_logic; begin
i : in std_logic_vector(7 downto 0); if(en= =0)
y : out std_logic_vector(2 downto 0)); y = 3’b0;
end enc83; else
case(i)
architecture encd of enc83 is 8’b 00000001 : y=3’b000;
begin 8’b 00000010 : y=3’b001;
process(en, i) 8’b 00000100 : y=3’b010;
begin 8’b 00001000 : y=3’b011;
if (en = ‘1’) then 8’b 00010000 : y=3’b100;
y <= “000”; 8’b 00100000 : y=3’b101;
else 8’b 01000000 : y=3’b110;
case (i) is 8’b 10000000 : y=3’b111;
when "00000001" => y <= "000"; endcase
when "00000010" => y <= "001" ; end
when "00000100" => y <= "010" ; endmodule
when "00001000" => y <= "011" ;
when "00010000" => y <= "100" ;
when "00100000" => y <= "101" ;
when "01000000" => y <= "110";
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HDL LAB IV Sem EC/TE
when "10000000" => y <= "111" ;
when others=> NULL;
end case;
end if;
end process;
end encd;

Simulation Result
Before Execution

After Execution

## net “en” loc = “p74”;

net “i0” loc = “p84”;
net “i1” loc = “p85”;
net “i2” loc = “p86”;
net “i3” loc = “p87”;
net “i4” loc = “p93”;
net “i5” loc = “p94”;
net “i6” loc = “p95”;
net “i7” loc = “p100”;
net “y0” loc = “p112”;
net “y1” loc = “p114”;
net “y2” loc = “p113”;
Dept. of EC/TE, VKIT 2010 Page 7 of 64
HDL LAB IV Sem EC/TE

## 8 to 3 encoder with priority

VHDL CODE VERILOG CODE
library ieee; module encoder (din, dout);
use ieee.std_logic_1164.all; input [7:0] din;
use ieee.std_logic_arith.all; output [2:0] dout;
use ieee.std_logic_unsigned.all; reg [2:0] dout;

## entity encoder8_3 is always @(din)

port ( enable: in std_logic; begin
d_in: in std_logic_vector(7 downto 0); casex (din)
d_out: out std_logic_vector(2 downto 0) ); 8’b00000001: dout=3’d0;
end encoder8_3; 8’b0000001x: dout=3’d1;
architecture encoder_arch of encoder8_3 is 8’b000001xx: dout=3’d2;
begin 8’b00001xxx: dout=3’d3;
process(enable,d_in) 8’b0001xxxx: dout=3’d4;
variable i :integer; 8’b001xxxxx: dout=3’d5;
begin 8’b01xxxxxx: dout=3’d6;
d_out<= “000” 8’b1xxxxxxx: dout=3’d7;
if ( enable = '1') then default: dout=3’d0;
for i in 0 to 7 loop endcase
if d_in(i)=’1’ then end
d_out<= conv_std_logic_vector(i,3); endmodule
end if;
end loop;
end if;
end process;
end encoder_arch;

## Dept. of EC/TE, VKIT 2010 Page 8 of 64

HDL LAB IV Sem EC/TE

c. 8 to 1 Multiplexer
THEORY : Multiplexer is a digital switch.It allows digital information from several sources
to be rooted on to a single output line.The basic multiplexer has several data input lines and a
single output line.The selection of a particular input line is controlled by a set of selection
lines.Normally there are 2N input lines and N selection lines whose bit combinations
determine which input is selected.Therefore multiplexer is many into one and it provides the
digital equivalent of an analog selector switch.
Block Diagram Truth Table
I0 Sel2 Sel1 Sel0 y
0 0 0 I0
I1 0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
8:1Mux 1 1 0 I6
1 1 1 I7
y

I7

sel (2 to 0)
VHDL CODE VERILOG CODE
library ieee; module mux8_1
use ieee.std_logic_1164.all; input [7:0]I;
use ieee.std_logic_arith.all; output [2:0]sel;
use ieee.std_logic_unsigned.all; output y;
input en;
entity mux8_1 is reg y;
port(I: in std_logic_vector (7 downto 0); always @(en,sel,I,y);
sel: in std_logic_vector (2 downto 0); begin
en: in std_logic; y: out std_logic); if (en= =1)
end mux8_1; begin
if (s= =000); y=I;
architecture behavioral of mux8_1 is else if (s==001); y=I;
begin else if (s==010); y=I;
process (I,sel,en) is else if (s==011); y=I;
begin else if (s==100); y=I;
if en=’1’ then else if (s==101); y=I;
if sel=”000” then y<=I(0); else if (s==110); y=I;
elsif sel=”001” then y<=I(1); else if (s==111); y=I;
elsif sel=”010” then y<=I(2); end
elsif sel=”011” then y<=I(3); else y=0;
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HDL LAB IV Sem EC/TE
elsif sel=”100” then y<=I(4); end
elsif sel=”101” then y<=I(5); end
elsif sel=”110” then y<=I(6); endmodule
else y<=I(7);
end if;
else y<=’0’;
end if;
end process;
end behavioral;

Simulation Result
Before Execution

After Execution

## User Constraint File

net “en” loc = “p74”;
net “sel0” loc = “p75”;
net “sel1” loc = “p76”;
net “sel2” loc = “p77”;
net “i0” loc = “p112”;
net “i1” loc = “p114”;
net “i2” loc = “p113”;
Dept. of EC/TE, VKIT 2010 Page 10 of 64
HDL LAB IV Sem EC/TE
net “i3” loc = “p115”;
net “i7” loc = “p117”;
net “i5” loc = “p118”;
net “i6” loc = “p121”;
net “i7” loc = “p123”;
net “y” loc = “p84”;
d. 4-Bit Binary to Gray Converter

THEORY

Binary Data: The binary number system is simply another way to count.It is less
complicated than the decimal system because it is composed of only 2 digits.The 2 binary
digits are 1 and 0.The position of 1 or 0 in a binary number indicates its weights or value
within the number, the weight of each successfully higher position in a binary number is an
increasing power of two.

Gray Code: Gray code is an unweighted code,which means that there are no specific weights
assigned to the bit positions.The gray code exibhits only a single bit change from one code
number to next. Gray code is not an arithmetic code.

The “Reflected binary code”, also known as Gray code after Frank Gray. In a Gray
code the adjacent numbers differ by one symbol. The original name reflected binary code is
derived from the fact that the second half of the values are equivalent to the first half in
reverse order, except for the highest bit, which is inverted.

Block Diagram

clk 4 bit
en Binary to q(3 downto 0)
rst
Gray

Truth Table

Rst Clk En B3 B2 B1 B0 G3 G2 G1 G0
1 x 0 0 0 0 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 1
0 1 1 0 0 1 0 0 0 1 1
0 1 1 0 0 1 1 0 0 1 0
0 1 1 0 1 0 0 0 1 1 0
0 1 1 0 1 0 1 0 1 1 1
0 1 1 0 1 1 0 0 1 0 1
0 1 1 0 1 1 1 0 1 0 0
0 1 1 1 0 0 0 1 1 0 0
0 1 1 1 0 0 1 1 1 0 1
0 1 1 1 0 1 0 1 1 1 1
0 1 1 1 0 1 1 1 1 1 0
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HDL LAB IV Sem EC/TE
0 1 1 1 1 0 0 1 0 1 0
0 1 1 1 1 0 1 1 0 1 1
0 1 1 1 1 1 0 1 0 0 1
0 1 1 1 1 1 1 1 0 0 0

## VHDL CODE VERILOG CODE

library ieee; module b2g(b,g);
use ieee.std_logic_1164.all; input [3:0] b;
use ieee.std_logic_arith.all; output [3:0] g;
use ieee.std_logic_unsigned.all; assign g=b;
assign g = (b^b);
entity B2G is assign g = (b^b);
port ( b : in std_logic_vector(3 downto 0); assign g = (b^b);
g : out std_logic_vector(3 downto 0)); endmodule
end B2G;

## architecture BG2 of B2G is

begin
g(3) <= b(3);
g(2) <= b(2) xor b(3);
g(1) <=b(1) xor b(0);
g(0) <= b(1) xor b(0);
end BG2;
Simulation Result
Before Execution

After Execution

## User Constraint File

net “b<0>” loc = “p74”;
net “b<1>” loc = “p75”;
net “b<2>” loc = “p76”;
Dept. of EC/TE, VKIT 2010 Page 12 of 64
HDL LAB IV Sem EC/TE
net “b<3>” loc = “p77”;
net “g<0>” loc = “p84”;
net “g<1>” loc = “p85”;
net “g<2>” loc = “p86”;
net “g<3>” loc = “p87”;
e.1 De-Multiplexer ( 1 to 4)
THEORY : A demultiplexer is a circuit that receives information on a single line and
transmits this information on one of 2N output lines. The selection of specific output lines is
controlled by the value of N selection lines. The single input variable din as a path to all 4
outputs but the input information is directed to only one of the output lines.
Block Diagram

i
en y(3 downto 0)
1:4
sel(1 downto 1) Demux

Truth Table
i en Sel1 Sel0 y3 y2 y1 y0
1 0 0 0 0 0 0 1
1 0 0 1 0 0 1 0
1 0 1 0 0 1 0 0
1 0 1 1 1 0 0 0
0 1 x x 0 0 0 0

## VHDL CODE VERILOG CODE

library ieee; module demux (sel, i, en, y);
use ieee.std_logic_1164.all; input en, i;
entity dec1 is input [1:0]sel;
port (enable:in std_logic;din :std_logic_vector output [3:0]y;
(1 downto 0); dout:out std_logic_vector reg [3:0]y;
(3 downto 0)); always @ (en or sel or i)
end dec1; begin
architecture dec2 of dec1 is if(en= =1)
begin y = 4’b0000;
process(enable,din) else
begin case(sel)
if(enable='1') then 2’b00 : y = i;
dout<="0000"; 2’b01 : y = i;
else 2’b10 : y = i;
case din is 2’b11 : y = i;
when "00"=>dout<="0001"; endcase
when"01"=>dout<="0010"; end
when"10"=>dout<="0100"; endmodule
when"11"=>dout<="1000";
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HDL LAB IV Sem EC/TE
when others=>dout<="0000";
end case;
end if;
end process;
end dec2;
Simulation Result

Before Execution

After Execution

## net “en” loc = “p74”;

net “i” loc = “p75”;
net “sel<0>” loc = “p76”;
net “sel<1>” loc = “p77”;
net “y<0>” loc = “p84”;
net “y<1>” loc = “p85”;
net “y<2>” loc = “p86”;
net “y<3>” loc = “p87”;

## Dept. of EC/TE, VKIT 2010 Page 14 of 64

HDL LAB IV Sem EC/TE

## e.2 1-BIT COMPARATOR

THEORY : Comparator is a special combinational circuit designed primarily to compare the
relative magnitude of 2 binary numbers. It receives 2N bit numbers A and B as inputs and the
outputs are A>B, A=B and A<B. Depending upon the relative magnitudes of the 2 numbers
one the outputs will be high.

a b L E G
a L
0 0 0 1 0
1bit
E 0 1 1 0 0
Comparat
b or 1 0 0 0 1
G 1 1 0 1 0

## VHDL CODE VERILOG CODE

library ieee; module comp1 (a, b, l, e, g);
use ieee.std_logic_1164.all; input a, b;
use ieee.std_logic_arith.all; output l, e, g;
use ieee.std_logic_unsigned.all; assign g = a & ~(b);
assign e = ~(a^b);
entity comp1 is assign l = ~(a) & b;
port( a, b: in std_logic; endmodule
g, e, l : out std_logic);
end comp1;

## architecture dtflcomp1 of comp1 is

begin
g<= a and(not b);
e<= a xnor b;
l<= (not a) and b;
end dtflcomp1;

Simulation Result

Before Execution

## Dept. of EC/TE, VKIT 2010 Page 15 of 64

HDL LAB IV Sem EC/TE

After Execution

## net “a” loc = “p74”;

net “b” loc = “p75”;
net “g” loc = “p84”;
net “e” loc = “p85”;
net “l” loc = “p86”;

## Dept. of EC/TE, VKIT 2010 Page 16 of 64

HDL LAB IV Sem EC/TE

## e.3 2-Bit Comparator

Block Diagram

a(1 to 0) x

2 bit y
Comparator
b(1 to 0) z
Truth Table
inputs outputs
a0 a1 b0 b1 a>b a=b a<b
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
VHDL CODE VERILOG CODE
library ieee; module comp(a, b, equ, grt, less);
use ieee.std_logic_1164.all; input [1:0] a,b;
use ieee.std_logic_arith.all; output equ, grt, less;
use ieee.std_logic_unsigned.all; reg equ, grt, less;
always @(a or b)
entity compar is begin
Port ( a, b : in std_logic_vector(1 downto 0); assign grt = (a &~b)|(a &
equ: out std_logic; less, ~b & ~b)| (a &
grt : buffer std_logic); b&a);
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HDL LAB IV Sem EC/TE
end compar; assign less = (~a & b)| (~a &
b & b)|(~a
architecture dtflcomp of compar is &~a & b);
begin assign eqy = ~(grt | less);
grt<= (a(0) and not b(0)) or (a(1) and not b(0) and endmodule
not b(1)) or (a(0) and not b(1) and a(1));
less<=(not a(0) and b(0)) or (not a(1) and b(0)
and b(1)) or (not a(0) and not a(1) and b(1));
equ <= grt nor less;
end dtflcomp;

Simulation Result
Before Execution

After Execution

## net “a<0>” loc = “p74”;

net “a<1>” loc = “p75”;
net “b<0>” loc = “p76”;
net “b<1>” loc = “p77”;

## Dept. of EC/TE, VKIT 2010 Page 18 of 64

HDL LAB IV Sem EC/TE
net “grt” loc = “p84”;
net “less” loc = “p85”;
net “equ” loc = “p86”;

EXPERIMENT 3
AIM: Write HDL code to describe the functions of a full Adder Using three modeling styles.

## COMPONENTS REQUIRED: FPGA board, FRC’s and power supply.

Block Diagram

a
Sum
b
FULL
c

Truth table

INPUTS OUTPUTS
a b cin SUM Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Data Flow
VHDL CODE VERILOG CODE

## Dept. of EC/TE, VKIT 2010 Page 19 of 64

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library ieee; module fulladder ( a, b, c,s,cout);
use ieee.std_logic_1164.all; input a, b,c;
use ieee.std_logic_arith.all; output s, cout;
use ieee.std_logic_unsigned.all; assign s= (a ^ b^c);
assign cout= ((a & b)|(b & c)|(c&a));
port ( a, b, cin : in std_logic;
sum, cout : out std_logic);

## architecture data of fulladder is

begin
sum<=a xor b xor cin;
cout<= ( a and b) or ( b and cin) or
( cin and a);
end data;

BEHAVIORAL STYLE

## VHDL CODE VERILOG CODE

use ieee.std_logic_1164.all; input cin,x,y;
use ieee.std_logic_arith.all; output s,co;
use ieee.std_logic_unsigned.all; reg s,co;
always@(cin or x or y)
port ( a, b, c : in std_logic; case ({cin,x,y})
sum, carry : out std_logic);
3'b001:{co,s}='b01;
architecture Behavioral of fulladder1 is 3'b010:{co,s}='b01;
begin 3'b011:{co,s}='b10;
process(a, b, c) 3'b100:{co,s}='b01;
begin 3'b101:{co,s}='b10;
if(a='0' and b='0' and c='0') then sum<='0'; 3'b110:{co,s}='b10;
carry<='0'; 3'b111:{co,s}='b11;
elsif(a='0' and b='0' and c='1') then sum<='1'; endcase
carry<='0'; end
elsif(a='0' and b='1' and c='0') then sum<='1'; endmodule
carry<='0';
elsif(a='0' and b='1' and c='1') then sum<='0';
carry<='1';
elsif(a='1' and b='0' and c='0') then sum<='1';
carry<='0';
elsif(a='1' and b='0' and c='1') then sum<='0';
carry<='1';
elsif(a='1' and b='1' and c='0') then sum<='0';

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carry<='1';
else sum<='1'; carry<='1';
end if;
end process;
end Behavioral;

STRUCTURAL STYLE

## VHDL CODE VERILOG CODE

library ieee; module fa (x, y, cin, carry, sum);
use ieee.std_logic_1164.all; input x, y, cin;
use ieee.std_logic_arith.all; output carry, sum;
use ieee.std_logic_unsigned.all; ha ha1 (y, cin, s0, c0);
ha ha2 (x, s0, sum, c1);
entity halfadder1 is or ( carry, c0, c1);
port ( x,y : in std_logic; endmodule
sum,carry : out std_logic);
module ha(a, b, s, c);
architecture behavioral of halfadder1 is input a, b;
begin output s, c;
sum<= x xor y; xor(s, a, b);
carry <= x and y; and (c, a, b);
end behavioral; endmodule

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

port (x, y, cin : in std_logic;
sum, cout : out std_logic);

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HDL LAB IV Sem EC/TE
port (x, y : in std_logic;
sum,carry : out std_logic);
end component;

## signal temp1, temp2, temp3 :std_logic;

begin
L1: halfadder1 port map (x, y, temp1,
temp2);
L2: halfadder1 port map (temp1, cin, sum,
temp3);

## cout<= temp2 or temp3;

end structural;

Simulation Result
Before Execution

After Execution

## net “x” loc = “p74”;

net “y” loc = “p75”;

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net “sum” loc = “p84”;
net “cout” loc = “p85”;

EXPERIMENT 5

AIM: Write a model for 32 bit ALU using the schematic diagram shown below.

## OPCODE ALU OPERATION

1 A+B
2 A-B
3 A Complement
4 A*B
5 A and B
6 A or B
7 A nand B
8 A xor B
9 Right shift
10 Left Shift

Block Diagram

A1(3 to 0)

B1(3 to 0)
ALU Zout (7 downto 0)

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opcode (2 to 0)

Truth table
Operation Opcode A B Zout
A+B 000 1111 0000 00001111
A-B 001 1110 0010 00001100
A or B 010 1111 1000 00001111
A and B 011 1001 1000 00001000
Not A 100 1111 0000 11110000
A1*B1 101 1111 1111 11100001
A nand B 110 1111 0010 11111101
A xor B 111 0000 0100 00000100

## VHDL CODE VERILOG CODE

library ieee; module ALU ( a, b, s, en, y );
use ieee.std_logic_1164.all; input signal [3:0]a, b;
use ieee.std_logic_arith.all; input [3:0]s;
use ieee.std_logic_unsigned.all; input en;
output signal [7:0]y;
entity alunew1 is reg y;
Port( a1,b1:in std_logic_vector(3 downto 0); always@( a, b, s, en, y );
opcode : in std_logic_vector(2 downto 0); begin
zout : out std_logic_vector(7 downto 0)); if(en==1)
end alunew1; begin
case
architecture Behavioral of alunew1 is 4’d0: y=a+b;
4’d1: y=a-b;
signal a: std_logic_vector( 7 downto 0); 4’d2: y=a*b;
signal b: std_logic_vector( 7 downto 0); 4’d3: y={4’ d0, (a & b)};
4’d4: y={4’ d0, (a | b)};
begin 4’d5: y={4’ d0, (a ^ b)};
4’d6: y={4’ d0, ~(a & b)};
a<= "0000" & a1; 4’d7: y={4’ d0, ~(a | b)};
b<= "0000" & b1; 4’d8: y={4’ d0, ~(a ^ b)};
default: begin end
zout<= a+b when opcode ="000" else end case
a-b when opcode ="001" else end
a or b when opcode ="010" else else
a and b when opcode ="011" else y=8’d0;
not a when opcode ="100" else end
a1 * b1 when opcode ="101" else endmodule
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a nand b when opcode ="110" else
a xor b;

end Behavioral;

Simulation Result
Before Execution

After Execution

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EXPERIMENT 6

AIM: Develop the HDL code for the following flip-flop: SR, JK, T, D.

## COMPONENTS REQUIRED:FPGA board, FRC’s and power supply.

THEORY :
SR flip-flop: A SR flip - flop is the simplest possible memory element. The SR flip flop has
two inputs Set and Reset. The SR flip-flop is a basic building block for other flip-flops.

D flip-flop: This is a flip - flop with a delay (D) equal to exactly equal to one cycle of the
clock. The defect with SR FF is the indeterminate output when the data inputs at S and R are
1. In order to avoid this the input to R is through an inverter from S so that the input to R is
always the complement of S and never same. The S input is redesignated as D.

JK flip-flop: The JK flip flop is called a “universal flip flop” because the other flip flops like
D, SR, T can be derived from it. The “racing or race around condition” takes place in a JK FF
when J=1 and K=1 and clock=1.

## Dept. of EC/TE, VKIT 2010 Page 26 of 64

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T flip-flop: T stands for toggling. It is obtained from JK FF by tying both the inputs J and K.

a. SR FLIP FLOP

## Block Diagram Truth Table

rst p Clk s r q qb
clk r
1 x x x x 0 1
s q 0 1 x x x 1 0
r 0 0 1 0 0 Qb Qbprevious
rst SR FF qb 0 0 1 0 1 0 1
pr 0 0 1 1 0 1 0
0 0 1 1 1 1 1

## VHDL CODE VERILOG CODE

library ieee; module srff(sr, clk, q, qb);
use ieee.std_logic_1164.all; input [1:0] sr;
use ieee.std_logic_arith.all; input clk;
use ieee.std_logic_unsigned.all; output q, qb;
reg q,qb;
entity SR_ff is always@(posedge clk)
port ( clk, s, r : in std_logic; begin
q : buffer std_logic); case (s,r)
end SR_ff; 2'd0 : q= q;
2'd1 : q=0;
architecture Behavioral of SR_ff is 2'd2 : q=1;
begin 2'd3 : q=q;
process( clk) endcase
begin qb=~q;
if (clk'event and clk = '1') then end
if (s='0' and r='0')then q<= q; endmodule
elsif (s='0' and r='1')then q<= '0';
elsif (s='1' and r='0')then q<= '1';
elsif (s='1' and r='1')then q<= 'Z';
end if ;
end if;
end process ;
end Behavioral;
Simulation Result
Before Simulation

## Dept. of EC/TE, VKIT 2010 Page 27 of 64

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After Simulation

## User Constraint File

net “s” loc = “p74”;
net “r” loc = “p75”;
net “clk” loc = “p18”;
net “q” loc = “p84”;

b. JK FLIP FLOP

## Block Diagram Truth Table

Rst Clk J K Q Qb
1 1 0 0 Previous state
1 1 0 1 0 1
JK FF 1 1 1 0 1 0
1 1 1 1 Qb Q
1 No +ve edge - - Previous state
0 - - - 0 1

j
k q

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clk qb

rst

## VHDL CODE VERILOG

library ieee; module jkff(jk, clk, q, qb);
use ieee.std_logic_1164.all; input [1:0]jk;
use ieee.std_logic_arith.all; input clk;
use ieee.std_logic_unsigned.all; output q, qb;
reg q, qb;
entity jk_ff is always@(posedge clk)
port ( clk : in std_logic; begin
jk : in std_logic_vector(1 downto 0); case (jk)
q, qb : out std_logic); 2'd1:q=q;
end jk_ff; 2'd1:q=0;
2'd2:q=1;
architecture Behavioral of jk_ff is 2'd3:q=~q;
begin endcase
process(clk) qb=~q;
variable temp1, temp2 : std_logic; end
begin endmodule
if rising_edge(clk) then
case jk is
when "01"=> temp1 :='0';
when "10"=> temp1 :='1';
when "00"=> temp1 := temp1;
when "11"=>temp1 := not temp1;
when others => null;
end case;
q<= temp1;
temp2 := not temp1;
qb <= temp2;
end if;
end process ;
end Behavioral;

Simulation Result
Before Simulation

## Dept. of EC/TE, VKIT 2010 Page 29 of 64

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After Simulation

## User Constraint File

net “jk<1>” loc = “p75”;
net “jk<0>” loc = “p76”;
net “clk” loc = “p18”;
net “q” loc = “p84”;
net “qb” loc = “p85”;

c. T FLIP FLOP

## Dept. of EC/TE, VKIT 2010 Page 30 of 64

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Block Diagram Truth Table

T Rst T Clk q
clk q 1 0 1 q
1 1 1 qb
rst qb 1 x No +ve edge Previous state
T ff 0 x x 0

## VHDL CODE VERILOG CODE

library ieee; module tff(t,clk, q);
use ieee.std_logic_1164.all; input t,clk;
use ieee.std_logic_arith.all; output q;
use ieee.std_logic_unsigned.all; reg q;
always@(posedge clk)
entity tff is begin
port ( t, clk : in std_logic; case(t)
q : buffer std_logic); 1’d0 : q = q;
end tff; 1’d1 : q = ~q;
endcase
architecture Behavioral of tff is end
endmodule
begin
process(clk)

begin
if (clk’event and clk=’1’)then
q <= not t;
end if;

end process;
end Behavioral;

Simulation Result

Before Execution

After Execution

## Dept. of EC/TE, VKIT 2010 Page 31 of 64

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## User Constraint File

net “t” loc = “p74”;
net “clk” loc = “p18”;
net “q” loc = “p84”;

d. D FLIP FLOP
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## Block Diagram Truth Table

d clk d q qb
q x 1 1 0
1 1 1 0
clk D FF qb 1 0 0 1

## VHDL CODE VERILOG CODE

library ieee; module dff(d,clk,rst,q,qb);
use ieee.std_logic_1164.all; input d,clk,rst;
use ieee.std_logic_arith.all; output q,qb;
use ieee.std_logic_unsigned.all; reg q,qb;
reg temp=0;
entity dff is always@(posedge clk,posedge rst)
port ( clk : in std_logic; begin
d : in std_logic; if (rst==0)
q : out std_logic); temp=d;
end dff; else
temp=temp;
architecture Behavioral of dff is q=temp;
begin qb=~ temp ;
process(clk) end
begin endmodule
if (clk'event and clk = '1') then
q <= d;
end if ;
end process ;
end Behavioral;

Simulation Result

Before Execution

After Execution
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## User Constraint File

net “d” loc = “p74”;
net “clk” loc = “p18”;
net “q” loc = “p84”;

EXPERIMENT 7
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AIM: Design 4 bit Binary, BCD counter (Synchronous reset and Asynchronous reset and
any sequence counters.

## COMPONENTS REQUIRED:FPGA board, FRC’s and power supply.

a)BCD COUNTER
Block Diagram Truth Table
Rst Clk Q
clk 1 x 0000
q(3 downto 0) 0 1 0001
BCD
counter 0 1 0010
rst 0 1 0011
0 1 0100
0 1 0101
0 1 0110
0 1 0111
0 1 1000
0 1 1001
VHDL CODE VERILOG CODE
library ieee; module bcd(clr,clk,dir, tc, q);
use ieee.std_logic_1164.all; input clr,clk,dir;
use ieee.std_logic_arith.all; output reg tc;
use ieee.std_logic_unsigned.all; output reg[3:0] q;
always@(posedge clk,posedge clr)
entity bcd is begin
port ( clr,clk,dir : in std_logic; if(clr==1)
q : inout std_logic_vector (3 downto 0); q=4'd0;
tc : out std_logic); else
end bcd; begin
architecture Behavioral of bcd is if (dir==1)
signal clkd:std_logic_vector(21 downto 0); q=q+1;
begin else if(dir==0)
process(clk) q=q-1;
begin if(dir==1 & q==4'd10)
if rising_edge(clk) then begin
clkd<= clkd + '1'; q=4'd0;tc=1'b1; end
end if; else if(dir==0 & q==4'd15)
end process; begin
process(clkd,clr) q=1'd9;tc=1'b1;
variable temp:std_logic_vector(3 downto 0); end
begin else tc=1'b0;
if(clr='1')then end
temp:="0000"; end
tc<='0'; endmodule
elsif rising_edge(clkd(21)) then
if (dir='1') then
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temp:=temp+1;
elsif(dir='0') then
temp:=temp-1;
end if;
if(dir='1' and temp="1010") then
temp:="0000"; tc<='1';
elsif(dir='0' and temp="1111") then
temp:="1001"; tc<='1';
else tc<='0';
end if;
end if;
q<=temp;
end process;
end Behavioral;

## User Constraint File

net “clk” loc = “p18”;
net “clr” loc = “p74”;
net “q<0>” loc = “p84”;
net “q<1>” loc = “p85”;
net “q<2>” loc = “p86”;
net “q<3>” loc = “p87”;

## Dept. of EC/TE, VKIT 2010 Page 36 of 64

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Block Diagram Truth Table
Clk Rst Qout
clk x 1 0000
1 0 0001
Binary qout(3 dt 0)
1 0 0010
rst counter 1 0 0011
1 0 0100
1 0 0101
1 0 0110
1 0 0111
1 0 1000
1 0 1001
1 0 1010
1 0 1011
1 0 1100
1 0 1101
1 0 1110
1 0 1111
VHDL CODE
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity bin_as is
port ( rst, clk : in std_logic;
q : out std_logic_vector (3 downto 0));
end bin_as;

## architecture Behavioral of bin_as is

signal temp : std_logic_vector(3 downto 0);
signal clkd : std_logic_vector(21 downto 0);
signal clkdiv : std_logic;
begin
process(clk)
begin
if clk = ‘1’ and clk’ event then
clkd<= clkd + '1';
end if;
end process;
clkdiv<= clkd(21);
process(clkdiv, rst)
begin
if clk= ‘1’ and clk’ event then
if rst = ‘1’ then
temp<=(others =>’0’);
else temp <= temp + ‘1’;

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end if;
end if;
q<=temp;
end process;
end Behavioral;

## User Constraint File

net “clk” loc = “p18”;
net “rst” loc = “p74”;
net “q<0>” loc = “p84”;
net “q<1>” loc = “p85”;
net “q<2>” loc = “p86”;
net “q<3>” loc = “p87”;

## Dept. of EC/TE, VKIT 2010 Page 38 of 64

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VHDL CODE
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity asy is
port ( rst, clk : in std_logic;
q : out std_logic_vector (3 downto 0));
end asy;

## architecture Behavioral of asy is

signal temp : std_logic_vector(3 downto 0);
signal clkd : std_logic_vector(21 downto 0);
signal clkdiv : std_logic;
begin
process(clk)
begin
if clk = ‘1’ and clk’ event then
clkd<= clkd + '1';
end if;
end process;
clkdiv<= clkd(21);
process(clkd, rst)
begin
if rst = ‘1’ then
temp<=(others =>’0’);
elsif clk = ‘1’ and clk’ event then
temp <= temp + ‘1’;
q<=temp;
end if;
end process;
end Behavioral;

## User Constraint File

net “clk” loc = “p18”;
net “rst” loc = “p74”;
net “q<0>” loc = “p84”;
net “q<1>” loc = “p85”;
net “q<2>” loc = “p86”;
net “q<3>” loc = “p87”;

INTERFACING PROGRAMS
Dept. of EC/TE, VKIT 2010 Page 39 of 64
HDL LAB IV Sem EC/TE
1. Write a HDL code to control the speed, direction of DC & Stepper
motor

DC MOTOR

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity dcmotr is
port ( dir,clk,rst : in std_logic;
pwm : out std_logic_vector(1 downto 0);
rly : out std_logic;
row : in std_logic_vector(0 to 3));
end dcmotr;

## architecture Behavioral of dcmotr is

signal countr: std_logic_vector(7 downto 0);
signal div_reg: std_logic_vector(16 downto 0);
signal ddclk,tick: std_logic;
signal duty_cycle:integer range 0 to 255;

begin
process(clk,div_reg)
begin
if(clk'event and clk='1') then
div_reg<=div_reg+'1';
end if;
end process;
ddclk<=div_reg(12);
tick<= row(0) and row(1) and row(2) and row(3);
process(tick)
begin
if falling_edge(tick) then
case row is

when"1110"=> duty_cycle<=255;
when"1101"=> duty_cycle<=200;
when"1011"=> duty_cycle<=150;
when"0111"=> duty_cycle<=100;
when others => duty_cycle<=100;
end case;
end if;
end process;
process(ddclk, rst)
begin
if rst='0'then countr<=(others=>'0');
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pwm<="01";
elsif(ddclk'event and ddclk='1') then
countr<= countr+1;
if countr>=duty_cycle then
pwm(1)<='0';
else pwm(1)<='1';
end if;
end if;
end process;
rly<='1' when dir='1' else '0';

end Behavioral;

dc motor
net "clk" loc="p18";
net "reset" loc="p74";
net "dir" loc="p75";
net "pwm<0>" loc="p5";
net "pwm<1>" loc="p141";
net "rly" loc="p3";
net "row<0>" loc="p64";
net "row<1>" loc="p63";
net "row<2>" loc="p60";
net "row<3>" loc="p58";

PRODEDURE
1. Make connection between FRC 9 and FPGA board to the dc motor connector of VTU card
2. Make the connection between FRC 7 of FPGA board to the K/B connector of VTU card 2
3. Make the connection between FRC 1 of FPGA board to the DIP switch connector of VTV
card 2.
4. Connect the down loading cable and power supply to FPGA board.
5. Then open xilinx impact s/w, select slave serial mode and select the respective bit file and
click program.
6. Make the reset switch on.
7. Press the Hex keys and analyze speed changes for dc motor.

RESULT: The DC motor runs when reset switch is on and with pressing of different keys
variation of DC motor speed was noticed.

STEPPER MOTOR
library ieee;
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HDL LAB IV Sem EC/TE
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity steppermt is
port ( clk,dir,rst : in std_logic; dout : out std_logic_vector(3 downto 0));
end steppermt;

## architecture Behavioral of steppermt is

signal clk_div:std_logic_vector(15 downto 0); -- speed is maximum at 15
signal shift_reg:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if rising_edge (clk) then
clk_div <= clk_div+'1';
end if;
end process;
process(rst,clk_div(15)) -- speed is maximum at 15
begin
if rst='0' then shift_reg<="0001";
elsif rising_edge (clk_div(15)) then
if dir='1' then
shift_reg <= shift_reg(0) & shift_reg(3 downto 1);
else
shift_reg<= shift_reg ( 2 downto 0) & shift_reg(3);
end if; end if;
end process;
dout<= shift_reg;
end Behavioral;
User Constraint File
net "clk" loc = "p18"; net "dir" loc = "p85";
net "rst" loc = "p84";
net "dout<0>" loc = "p7"; net "dout<1>" loc = "p5";
net "dout<2>" loc = "p3"; net "dout<3>" loc = "p141";
PROCEDURE
1. Make connection between FRC 9 and FPGA board to the stepper motor connector of
VTU card 1
2. Make the connection between FRC 1 of FPGA board to the DIP switch connector of
VTU card 1.
3. Then open xilinx impact s/w, select slave serial mode and select the respective bit file
and click program.
4. Make the reset switch on.
5. Visualize the speed variation of stepper motor by changing counter value in the program.

RESULT: The stepper motor runs with varying speed by changing the counter value

## Dept. of EC/TE, VKIT 2010 Page 42 of 64

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity externallc is
port ( cnt : in std_logic; light : out std_logic);
end externallc;

begin
light<=cnt;

end Behavioral;

## User Constraint File

net "cnt" loc = "p74";
net "light" loc = "p7";

PROCEDURE
1.Make the connections b/w FRC9 of fpga board to external light connector of vtu card 2
2.Make connection b/w FRC1 of fpga board to the dip switch connector of vtucard2
4.Then open the xilinx impact software select the slave serial mode and select respective
bit file and click program
5. Make the reset switch on and listen to the tick sound.

RESULT: Once the pin p74 (reset) is switched on the tick sound is heard at the external light
junction.

## 3. Write HDL code to generate different waveforms(sawtooth, sine

wave, square, triangle, ramp etc) using DAC change the frequency
and amplitude.
Dept. of EC/TE, VKIT 2010 Page 43 of 64
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SAWTOOTH
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sawtooth is
port ( clk,rst : in std_logic;dac : out std_logic_vector(0 to 7));
end sawtooth;

## architecture Behavioral of sawtooth is

signal temp:std_logic_vector(3 downto 0);
signal cnt:std_logic_vector( 0 to 7);

begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+'1';
end if;
end process;
process (temp(3),cnt)
begin
if rst='1' then cnt<="00000000";
elsif rising_edge(temp(3)) then
cnt<= cnt+1;
end if;
end process;
dac<=cnt;
end Behavioral;

## User Contraint File

net "clk" loc="p18";
net "dac_out<0>" loc="p27";
net "dac_out<1>" loc="p26";
net "dac_out<2>" loc="p22";
net "dac_out<3>" loc="p23";
net "dac_out<4>" loc="p21";
net "dac_out<5>" loc="p19";
net "dac_out<6>" loc="p20";
net "dac_out<7>" loc="p4";

SQUARE
library ieee;
use ieee.std_logic_1164.all;

## Dept. of EC/TE, VKIT 2010 Page 44 of 64

HDL LAB IV Sem EC/TE
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity squarewg is
port ( clk,rst : in std_logic; dac : out std_logic_vector(0 to 7));
end squarewg;

## architecture Behavioral of squarewg is

signal temp:std_logic_vector(3 downto 0);
signal cnt:std_logic_vector(0 to 7);
signal en: std_logic;

begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+'1';
end if;
end process;

process(temp(3))
begin
if rst='1' then cnt<="00000000";
elsif rising_edge (temp(3)) then
if cnt< 255 and en='0' then
cnt<=cnt+1;
en<='0';
dac<="00000000";
elsif cnt=0 then en<='0';
else en<='1';
cnt<=cnt-1;
dac<="11111111";
end if;
end if;
end process;
end Behavioral;

TRIANGLE
library ieee;
use ieee.std_logic_1164.all;

## Dept. of EC/TE, VKIT 2010 Page 45 of 64

HDL LAB IV Sem EC/TE
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity triangwg is
port ( clk,rst : in std_logic; dac : out std_logic_vector(0 to 7));
end triangwg;

## architecture Behavioral of triangwg is

signal temp: std_logic_vector( 3 downto 0);
signal cnt: std_logic_vector(0 to 8);
signal en:std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+1;
end if;
end process;
process( temp(3))
begin
if rst='1' then cnt<="000000000";
elsif rising_edge(temp(3)) then
cnt<=cnt+1;
if cnt(0)='1' then
dac<=cnt(1 to 8);
else
dac<= not(cnt( 1 to 8));
end if;
end if;
end process;
end Behavioral;

RAMP
library ieee;
use ieee.std_logic_1164.all;

## Dept. of EC/TE, VKIT 2010 Page 46 of 64

HDL LAB IV Sem EC/TE
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity rampwg is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end rampwg;

## architecture Behavioral of rampwg is

signal temp:std_logic_vector(3 downto 0);
signal cnt:std_logic_vector( 0 to 7);

begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+'1';
end if;
end process;
process (temp(3),cnt)
begin
if rst='1' then cnt<="00000000";
elsif rising_edge(temp(3)) then
cnt<= cnt+15;
end if;
end process;
dac<=cnt;
end Behavioral;

SINE WAVE
library ieee;
use ieee.std_logic_1164.all;

## Dept. of EC/TE, VKIT 2010 Page 47 of 64

HDL LAB IV Sem EC/TE
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sinewave is
Port ( clk,rst : in std_logic;
dac_out : out std_logic_vector(0 to 7));
end sinewave;
architecture Behavioral of sinewave is
signal temp: std_logic_vector(3 downto 0);
signal counter: std_logic_vector(0 to 7);
signal en: std_logic;
begin
process(clk) is
begin
if rising_edge (clk) then
temp<= temp+'1';
end if;
end process;
process(temp(3)) is
begin
if rst='1' then counter<="00000000";
elsif rising_edge(temp(3)) then
if counter<255 and en='0' then
counter<= counter+31; en<='0';
elsif counter=0 then en<='0';
else en<='1';
counter<= counter-31;
end if;
end if;
end process;
dac_out<= counter;
end Behavioral;

PROCEDURE:
1. Make connection between FRC 5 and FPGA and DAC connector of VTU card 2.
2. Make the connection between FRC 1 of FPGA board to the DIP switch connector of VTU
card 2.
3. Then open xilinx impact s/w, select slave serial mode and select the respective bit file and
click program.
4. Make the reset switch on.

RESULT:The waveform obtained Ramp, Saw tooth, Triangular, Sine and Square waves are
as per the graph.

display

## Dept. of EC/TE, VKIT 2010 Page 48 of 64

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; 5. User Constraint File

## entity sevkeybrd is net "clk" loc="p18";

Port ( read : in std_logic_vector(3 downto 0); net "disp_cnt<0>" loc="p30";
clk : in std_logic; net "disp_cnt<1>" loc="p29";
scan : inout std_logic_vector(3 downto 0); net "disp_cnt<2>" loc="p31";
disp_cnt : out std_logic_vector(3 downto 0); net "disp_cnt<3>" loc="p38";
disp1 : out std_logic_vector(6 downto 0)); net "disp<0>" loc="p26";
end sevkeybrd; net "disp<1>" loc="p22";
net "disp<2>" loc="p23";
architecture Behavioral of sevkeybrd is net "disp<3>" loc="p21";
signal cnt_2bit:std_logic_vector(1 downto 0);
net "disp<4>" loc="p19";
begin
process(clk) net "disp<5>" loc="p20";
begin net "disp<6>" loc="p4";
if clk='1' and clk'event then net "read_l_in<0>" loc="122";
process(cnt_2bit) net "scan_l<0>" loc="132";
begin net "scan_l<1>" loc="136";
case cnt_2bit is net "scan_l<2>" loc="134";
when "00" => scan<= "0001"; net "scan_l<3>" loc="139";
when "01"=> scan<="0010";
when "10"=>scan<="0100";
when "11"=>scan<="1000";
when others=> null;
end case;
end process;
disp_cnt<="1110";
begin
case scan is
when "0001"=>disp1<="1111110";
when "0010"=>disp1<="0110011";
when "0100"=>disp1<="1111111";
when "1000"=>disp1<="1001110";
when others =>disp1<="0000000";
end case;

## when "0010"=> case read is

when "0001"=>disp1<="0110000";
when "0010"=>disp1<="1011011";
when "0100"=>disp1<="1111011";
when "1000"=>disp1<="0111101";
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when others=>disp1<="0000000";
end case;

## when "0100"=> case read is

when "0001"=>disp1<="1101101";
when "0010"=>disp1<="1011111";
when "0100"=>disp1<="1110111";
when "1000"=>disp1<="1001111";
when others=>disp1<="0000000";
end case;

## when "1000"=> case read is

when "0001"=>disp1<="1111001";
when "0010"=>disp1<="1110000";
when "0100"=>disp1<="0011111";
when "1000"=>disp1<="1000111";
when others=>disp1<="0000000";
end case;
when others=> null;
end case;
end process;
end Behavioral;

PROCEDURE
1. Make connection between FRC 5 and FPGA board to the seven segment connector of
VTU card 1.
2. Make the connection between FRC 4 to FPGA board to K/B connector of VTU card1.
3. Then open xilinx impact s/w, select slave serial mode and select the respective bit file
and click program.
4. Make the reset switch on.
5. Change the pressing of Hex Keys to watch the display on LCD’s ranging from 0000 to
FFFF.

RESULT:The values from 0 to F were displayed on all 4 LCD’s with the respective Hex
Key being pressed.

## Dept. of EC/TE, VKIT 2010 Page 50 of 64

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FOR DC & Stepper
Xilinx FPGA MOTOR
FRC FRC1 FRC2 FRC3 FRC4 FRC6 FRC7 Xilinx FPGA
1 74 84 112 122 40 58 FRC FRC9
2 75 85 114 124 41 60 1 7
3 76 86 113 129 42 63 2 5
4 78 87 115 126 48 64 3 3
5 77 93 117 132 50 65 4 141
6 80 94 118 136 51 66 9 5V
7 79 95 121 134 56 67 10 GND
8 83 100 123 139 57 28
9 VCC VCC VCC VCC VCC VCC
10 GND GND GND GND GND GND

## FOR LCD & DAC FOR ADC

FRC FRC5 FRC8 FRC10
1 4 96 62
2 20 99 59
3 19 101 49
4 21 102 47
5 23 103 46
6 22 116 4
7 26 120 43
8 27 131 13
9 30 133 12
10 29 137 11
11 31 138 10
12 38 140 6
13 5V 5V 5V
14 -5v -5v -5v
15 3.3 3.3 3.3
16 GND GND GND

## POSSIBLE VIVA QUESTION & ANSWER

1. What is HDL?
Hardware description language is a computer aided design(CAD). Tool to design and
synthesis of digital system. HDL language is similar to language.

## 2. HDL language is similar to which language?

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It is similar to C Language.

## 3. Justify the statement "Debugging the design is easy " in HDL.

Yes, because HDL packages implementation simulator & test benches

VHDL & Verilog

## 5. What is the abbreviation of VHDL?

VHDL means Very High Speed Integrated Circuit(VHSIC) hardware description
language.

## 6. What is the VHDL standard ?

The updated standard in 1993 is IEEE standard 1076-1993.

## 7. Write the general structure of VHDL model?

entity entity_name is
port(define input and output port);
architecture architecture_name is
begin
statements;
end architecture_name;

## 8. Write the general structure for verilog?

module modulename(input and output variable);
input......;
output......;
statement;
endmodule;

## 9. Which package is attached with VHDL program?

std_logic_1164 package is attached with VHDL program.

10. What is the Verilog HDL standard and who is maintaining it?
IEEE standard 1364-1995 is the verilog HDL standard and it is maintain by verilog
international organization.

11. In VHDL, what are the modes that the ports can take?
in, out, buffer, inout.

## 12. Explain the function of the modes of the port.

in-The port is only an i/p and appears only on the right hand side of the statement.
out-The port is only an o/p and appears only on the left and right hand side of the
statement.
buffer-The port can be used as both i/p & o/p but should have only one source.
inout-The port can be used as both an i/p & o/p.

## 13. Explain the structure of the verilog module.

The verilog module has two parts, Declaration & Body.
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Declaration- name, inputs and outputs of the module are listed.
Body-shows the relationship between the inputs & outputs.

## 14. Which of two Hardware Description Language is case Sensitive?

Verilog is case Sensitive.

## 15. How should the module be terminated in verilog?

The module is terminated by the predefined word end module.

## 16. What are the modes that exists in verilog ports?

input : The port is only an i/p Port.
output : The port is only an o/p Port.
inout : The port can be used as both an i/p and o/p.

## 17. How are the operators broadly classified?

Logical- AND,OR,XOR.
Relational =,=,<,<,>,>
Arithmetic +,-,*,
Shift to move the bits of an objects in a certain direction right or left.

## 18. State the different types of Logical Operators.

Logical Operators are AND, OR, NAND, NOR, NOT and Exclusive-OR.

## 19. Write the verilog bitwise logical operators.

AND - &, OR - |, NAND - ~(&), NOR - ~(|), EX-OR - ^, EX-NOR - ~ ^, NOT- ~.

## 20. What are Boolean Logical Operators, Give example.

The Boolean Logical operators operate on 2 operands, the result is Boolean 0 or 1.
Verilog Boolean logical operators are &&-AND Operator, ||-OR Operator.

## 21. What are Reduction Operators. Give examples.

The Reduction Opetators operate on a single Operand and the result is Boolean.

## & Reduction AND

| Reduction OR
~& Reduction NAND
~| Reduction NOR
^ Reduction XOR
~^ Reduction XNOR
! Negation.

## 22. What are relational Operators. Give example.

Relational Operators are used to compare the values of two objects and the result is
Boolean 0 or 1, the VHDL relational operators are:
= Equality
/= Inequality
< Less than
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<= Less than or equal
> Greater than
>= Greater than or equal.

23. What are Arithmetic Operators. State few arithmetic Operators in HDL?
Arithmetic Operators performs various operators like.
VHDL Arithmetic Operators Verilog Arithmetic Operators

- Subtraction - Subtraction
* Multiplication * Multiplication
/ Division / Division
Mod Modulus % Modulus
rem Remainder ** Exponent
abs absolute {,} Concatenate
** Exponent

## 24. What are shift & rotate operators?

Shift Left represents multiplication by 2.
Shift Right represents division by 2.
Example of VHDL shift operators.
ASll 1 - Shift A one position left logical.
ASrl 2 - Shift A two position right logical.
ASla 1 - Shift A one position left arithmetic.
ASla 2 - Shift A two position right arithmetic.
A rol 1 - Rotate A one position left.
A rol 1 - Rotate A one position right.
Verilog Shift Operators.
A<<1 Shift a one position left logical
A>>2 Shift a two position right.

## 25. What are the different types of VHDL data types?

The VHDL data types are broadly classified into 5 types.
1) Scalar Type - Bit type
Boolean
Integer
Real
Character
Physical
User defined type
Severity type
2) Composite Type-Bit vector type
Array type
Record
3) Access Type
4) File Type
5) Other Types - Std_logic_type
Std_logic_vector type
Signed
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Unsigned

## 26. What are the different types of data types in Verilog?

Nets, Registers, Vectors, Integers, Parameters, Real, Array.

## 27. What are the different styles of writing the description?

Behavioral, Structural, Switch level, Data flow, Mixed language.

## 28. What is Behavioral Description?

Behavioral description models the system as to how the o/p's behave with the i/p's. In
behavioral description the architecture includes predefined word process in VHDL and
always/initial Verilog module.

## 29. What is Structural Description?

Structural description model the system as component or gates.
Key word component is used in the architecture(VHDL) if gate construct.
In Verilog and, or, not is included in the module.

## 30. Explain what is Switch level description?

The system is described using switches or transistors. The verilog key words nmos, pmos,
cmos, transistors describes the system.

## 31. Explain what is data flow?

The data flow describes how the systems signal flows from the inputs to the outputs. The
description is done by writing the Boolean functions of the outputs.

## 32. What are the advantages of using mixed type description?

Mixed type description use more than one type or style of the previously mentioned
descriptions.

## 33. What is the function of data flow descriptions?

Data flow descriptions simulates the system by showing how the signa flows system
inputs to outputs.

## 34. How is signal assignment done in HDL?

In VHDL the signal assignment operator <= is used & in verilog, the predefined word
assign is used.

## 35. How do you declare a constant in HDL?

A constant is VHDL is declared by using the predefined word constant and in verilog it is
declared by its type like time or integer.
To assign a value to a constant assignment operator
:=is used in VHDL & = in verilog.
36. Write a time delay signed assignment statement.
To assign a delay time to a signed - assigned statement the predefined word after is used
in VHDL & in Verilog it is # (Delay time).
Ex : S1 - sel and b after 10 nsec - VHDL.
assign # 10 S1=sel & b // Verilog.

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37. Define Vector data types.
A vector is a data type that declares an array of similar elements such as to declare an
object that has a width of more than 1 bit.

38. What is the difference between syntax error and semantic error?
Syntax error is those that result from not following the rules of the language. it
terminates compilation of the program.
A semantic error is an error in the mechanics of the statement. it may not terminate the
program, but the outcome of the program may not be as expected.

## 39. What is the function of Behavioral Description?

The behavioral description describes the system by showing how the outputs behave
according to changes in its inputs. In behavioral description one need not know the logic
diagram of the system but one should know how the output behaves in response to
change in the output.

## 40. What are the two phase of execution in HDL?

The two phases of execution in HDL are Calculation and Assignment.

## 41. What do you mean by Sequential Calculation?

Sequential calculation means the calculation of a statement will not wait until the
proceeding statement is assigned only until the calculation is done.

42. Which are the Sequential statements that are assigned with behavioral description?
If statement, else-if, loop statements, for loop, forever, report, repeat, next-exit.

## 43. State the difference between signal and variable assignment.

A process is written based on signal assignment statements and then another process is
written based on variable assignment statements. The difference can be observed by the
simulation wave forms.

## 44. When do use loop statements and what is its advantage?

Loops is used to repeat the execution of statements written inside the body. The number
of repetitions is controlled by the range of an index parameter. The loop allows the code
to be shortened.

## 45. When is Structural Description best suited?

It is best suited when the digital logic of the system hardware components is known.

## 46. What type of components are used in structural description?

Components can be gate level: AND, OR, NOT, XOR, XNOR gates. Components can be
of higher logic level such as Register Transfer Level (RTL) or processor level.

47. What type of statements are written in Structural Description and why?
Statements are “Concurrent “ in nature. At any simulation time, all statements that have
an event are executed concurrently.

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Verilog recognizes all the primitive gates such as AND, OR, NOT, XOR, XNOR. Basic
VHDL packages do not recognize any gates unless the package is limited to one more
libraries, packages that have gate description.

## 49. List the verilog built-in gates.

BUFFER, NOT, AND, NAND, OR, NOR, XOR, XNOR.

## 50. Does VHDL have built-in gates.

No, VHDL does not have built-in gates.

## 51. What is Binding?

Binding is linking segment 1 in the code to segment 2 in the same code which makes
information in segment 2 visible to segment 1.

## (i) Binding between Entry and component in VHDL

(ii) Binding between library and module in VHDL.
(iii) Binding between library and component in VHDL.
(iv) Binding between two modules in verilog.

## 53. What are State Machines?

Synchronous sequential circuits are called “State Machines”.

## 54. What are the main components of State Machines.

Latches and Flip Flops. Additional combinational components may also be present.

## 55. Which are the two types of synchronous Sequential Circuits.

Mealy and Moore Circuits.

## 56. What is a Mealy Circuit?

The output or next state of Mealy circuit depends on the inputs and the present state of
flip flops/latches.

## 57. What is Moore Circuit?

The output or next state of Moore circuit depends only on the present state. Present and
next states for particular flip-flops are the same output pin.

## 58. Define state diagram.

A diagram which shows transition between states.

## 59. What is a ‘Generate’ statement?

It is mainly used for repetition of concurrent statement.

60. Name the keyword used to define global constants in VHDL and Verilog.
Generic in VHDL and parameter in Verilog.

## 61. Disadvantage of structural description in VHDL.

(i) Structural description VHDL code looks much longer than the Verilog
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code as it dose not have built-in libraries or packages for logical gates.
(ii) The description is not suited when the number of gates becomes larger.

## 62. What is Switch Level Description?

Switch Level Description implements Switches (transistors) to describe
relatively small-scale digital systems.

## 63. Application Area of Switch level description.

Very Large Scale Integrated (VLSI) Circuit layouts.

## 64. Disadvantages of Switch Level description.

(i) Only small-scale systems can be simulated using pure switch level
description.
(ii) If the system is not small, huge number of switches are needed that
may render simulation impractical.

## 65. Are built-in-switches statements present in Verilog. If Yes? What are

they?
Yes. They are Nmos, Pmos and Cmos.

## 66. Built-in Switches statement present in VHDL?

No, but to use these statements, user built packages must be developed.

## 67. What are strong Outputs?

The o/p is either the ground or the Vdd.

## 68. What is pmos Switches?

For a strong signal it should Pass1.

## 69. What is nmos Switches?

For a strong signal it should Pass0.

## 70. What is cmos Switches?

The Switch which can pass both strong 1 and strong 0 is a Cmos Switch.

## 71. What are Bi-directional Switches?

Bi-directional Switches conduct in both ways from drain to source from
source to drain.

## 72. Application of Bi-directional Switches

Used as Bi-directional buffer(bunes).

## 73. List the three types of Bi-directional switches in Verilog.

Tran, Tranif 0, Tranif 1.
74. Operation of three types of Bi-directional Switches.
(i) Switch ‘Tran’ has no control. It conducts all the time.
(ii) Switch ‘Tranif 1’ conducts if control is 1,otherwise the o/p is put on
high impedance.
(iii) Switch ‘Tranif 0’ conducts if control is 0,otherwise the o/p is put on
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High impedance.

## 75. What is a procedure Task and functions?

Procedure and task can have more than one i/p and more than o/p,
function have a single o/p,but can have more than one i/p.

## 76. Where do procedures and functions exits in VHDL?

They can be called only from within the ‘Process’.

## 77. Where do Task and functions exits in Verilog?

Task and function in Verilog can be called only from within ‘always’
or ‘initial’.

## 79. Define Procedure.

Procedure are VHDL sub programs.

## 80. Define Functions.

Functions are behavioural statements which must be called inside process
for VHDL or always or initial for Verilog.

(i) They optimize the style of writing HDL Code.
(ii) They shorten the code.

## 82. Difference between VHDL and Verilog with reference to pocedure.

VHDL allows procedure calls to be written inside functions. Verilog
does not allow such calls.

## 83. List some of the functions available in VHDL packages.

(i) Mod : Finds modulesof X mod Y.
(ii) Abs : Finds the absolute value of a signed number.
(iii) To-INTEGER : Which return an integer value of a signed input.
(iv) To-INTEGER : Which takes an integer and returns its signed binary equivalents.

## 84. List the main characteristics of Procedures, Tasks and Functions.

The body of the procedure cannot include behavioural statement 'Process'.
The body of the task cannot include 'Always' or 'Initial', functions return a single output
with 'Return', a predefined word.
85. What is the necessity of Mixed - Type Description?
For best implementation of code in both behavioral and structural description.
Explanation with examples.
86. Mention some VHDL Pre-defined types.
Bit, Std_logic, array and natural.

## 87. Give few examples of User-Defined types.

Week days, weather or grades or classes.
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## 88. Which is Pre-defined word used to instantiate a user defined types?

Type; Ex : Type week days is (Mon, Tue,Fri);

## 90. What is the advantage of Packages?

Packages allow the usesd to access built-in constructs.

## 91. Write Syntax for Package.

Package<Package Name>is
---------------------------------------
---------------------------------------
---------------------------------------
End<Package name>
Package body <Package name>is
---------------------------------------
---------------------------------------
--------------------------------------
End <Package name>

## 92. What is described in the body of the package?

The body of the packages contains the code for all the identifiers listed in the
declaration.

93. Tone/Falls: VHDL allows for multi dimensional arrays but Verilog only allows single
dimensional arrays.

## 94. Write VHDL syntax for single dimensional array.

Type data vector is array(3 downto 0) of word array;
Sub type word array is Std_Logic_Vector(1 downto 0).

## 95. Give Syntax for verilog single dimensional array.

Reg[1:0] data vector[0:3]

File.

## 97. What is Port Direction?

Port Direction or mode of the file is nothing but the purpose of file i.e. input file or
output file. They are declared as infile or outfile.

## 98. What is Textio?

It is an IEEE packages used with the file handling programs.

## 99. Mention the built-in procedures for file handling?

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## 100. Give an Example for implementation of File- Open.

File_Open (F Status, infile, “testfile.txt”, read_mode);

## 101. Write syntax to open a text outfile by t e name of HDL.txt?

File_Open (F Status, outfile, “HDL.txt”, write_mode);

## 102. What is Write line?

Write Line is Pre-Defined procedure that writes a line into an outfile that is open for
write mode.
Ex: Writeline(outfile, temp)

## 103. Mention the Built-in tasks for accessing a file Verilog?

\$fopen, \$fdisplay, \$fmonitor, \$fclose.

## 104. Explain the statement \$monitor(ch1,”%”,quantity);

The above task monitors the variable quantity and records its value in binary in the file
testfile.txt, indicator by Ch1;

105. Give Escape characters which can be used with monitor statement?
\ n, \t, \\, \”,\.

## 106. What is Record type?

Record type is a collection of elements, the elements of which can be of the same type
or different types.

## 107. Why Mixed – Language Description?

one module.
For example : VHDL has more – Extensive file operations than verilog, including write
and read. By writing mixed – language, we can use the VHDL file operations in verilog
module.

## 108. What are the Limitations of Mixed – Language Descriptions?

1. Not all VHDL data types are supported in MLD.
2. The VHDL port type buffer is not supported.
3. Only a VHDL components constructs can invoke a Verilog module. We cannot
invoke a verilog module from any other construct in the VHDL Module.

## 109. Which data types of VHDL are supported for MLD?

Bit, Bit_Vector. Std_logic, Std_ulogic _vector and Std_ulogic_vector.

## 110. Is it possible to invoke procedure or function by verilog module?

No, A Verilog module can only invoke VHDL entity.
111. What is Synthesis?
Synthesis maps between the simulation (Software) domain and the hardware domain.

## 112. What information is carried from Entity and Module?

Provides informations on i/ps and o/ps and their types.
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## 113. Write the Entity for figure1

Entity system is
port(a, b: in unsigned(3 downto 0);
d: out integer range(-10 to 10));
end system;

always @(x)
begin y = x;
end
endmodule

## 115. Write the Verilog code for figure3

always @(a, x)
begin
if(a==1’b1)
y=x;
else
y=1’b0;
end

QUESTION BANK

1a. Write and execute an VHDL / Verilog code to realize all logic gates and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to control the speed and direction of DC Motor.
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2a. Write and execute an VHDL / Verilog code to realize 2:4 decoder and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to display message on the given seven segment
displays accepting Hex key pad input data.

3a. Write and execute an VHDL / Verilog code to realize 8:3 encoder and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to generate square waveform using DAC for different
frequency.

4a. Write and execute an VHDL / Verilog code to realize 8:1 MUX and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to generate square waveform using DAC for different
frequency.

5a. Write and execute an VHDL / Verilog code to realize 4-bit Binary to Gray code converter
b. Write and execute an VHDL code to control the speed and direction of Stepper Motor.

6a. Write and execute an VHDL / Verilog code to realize 1:8 DEMUX and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to generate triangular waveform using DAC.

7a. Write and execute an VHDL / Verilog code to realize N bit comparator and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to control the speed and direction of DC Motor.

8a. Write and execute an VHDL / Verilog code to realize Full Adder using Behavioral
modeling and download to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to control the external lights using relays.

9a. Write and execute an VHDL / Verilog code to realize Full Adder using Structural
modeling and download to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code the external lights using relays.

10a. Write and execute an VHDL / Verilog code to realize Full Adder using Data Flow
modeling and download to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code the external lights using relays.

11a. Write and execute an VHDL / Verilog code to realize SR & D-FF and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to generate square waveform using DAC for different
frequency.

12a. Write and execute an VHDL / Verilog code to realize JK FF and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to generate square waveform using DAC for different
frequency.
Dept. of EC/TE, VKIT 2010 Page 63 of 64
HDL LAB IV Sem EC/TE

13a. Write and execute an VHDL / Verilog code to realize 4-bit Synchronous counter and
b. Write and execute an VHDL code the external lights using relays.

14a. Write and execute an VHDL / Verilog code to realize 4-bit Binary counter and
b. Write and execute an VHDL code to display message on the given seven segment
displays accepting Hex key pad input data.

15a. Write and execute an VHDL / Verilog code to realize 4-bit BCD counter and download
to FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to control the speed and direction of DC Motor.

16a. Write and execute an VHDL / Verilog code to realize 4-bit ALU and download to
FPGA / CPLD with logic diagram and truth-table.
b. Write and execute an VHDL code to generate triangular waveform using DAC for
different frequency.
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