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Two-Transistor Amplifiers (6/13/00) Page 1 3.3 - TWO-TRANSISTOR AMPLIFIERS INTRODUCTION Objective The objective of this presentation is: 1.)

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Two-Transistor Amplifiers (6/13/00) Page 1 3.3 - TWO-TRANSISTOR AMPLIFIERS INTRODUCTION Objective The objective of this
Two-Transistor Amplifiers (6/13/00) Page 1 3.3 - TWO-TRANSISTOR AMPLIFIERS INTRODUCTION Objective The objective of this

3.3 - TWO-TRANSISTOR AMPLIFIERS

INTRODUCTION

Objective The objective of this presentation is:

1.) Show how two transistors are used to achieve amplifiers with improved performance 2.) Show the analysis of multiple transistor amplifiers using resistive loads

3.) Continue to build the amplifier concepts necessary to consider integrated circuit amplifiers Outline

• BJT CC-CE, CC-CC amplifiers

• Darlington transistor amplifer

• BJT-MOS amplifiers

• Cascode amplifiers

• Summary

ECE 4430 - Analog Integrated Circuits and Systemsamplifiers • Darlington transistor amplifer • BJT-MOS amplifiers • Cascode amplifiers • Summary  P.E. Allen

P.E. Allen

Two-Transistor Amplifiers (6/13/00) Page 2 BJT TWO TRANSISTOR AMPLIFIERS The Common Collector-Common Emitter Configuration Circuit: V CC Out

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Two-Transistor Amplifiers (6/13/00) Page 2 BJT TWO TRANSISTOR AMPLIFIERS The Common Collector-Common Emitter Configuration
Two-Transistor Amplifiers (6/13/00) Page 2 BJT TWO TRANSISTOR AMPLIFIERS The Common Collector-Common Emitter Configuration

BJT TWO TRANSISTOR AMPLIFIERS

The Common Collector-Common Emitter Configuration Circuit:

V CC Out In Q1 I Bias
V
CC
Out
In
Q1
I Bias

Q2

Configuration Circuit: V CC Out In Q1 I Bias Q2 B1 i in + v in

B1

i

in

Circuit: V CC Out In Q1 I Bias Q2 B1 i in + v in -

+

v in

-
-

Small-signal performance:

R in = r π1 + (1+β o1 )r π2

R out = r o2

v out

v

in

= -

g m2 (r o2 ||R L )(1+β o1 )r π2

R

in

i out

i

in

=

g m2 (1+β o1 )r π2

R

in

=

= -

+ v 1

E1 = B2

i out

- r 1 g m1 v 1 r 2 r o1
-
r 1
g m1 v 1
r 2
r o1
C2 + + v 2 g m2 v 2 v out r o2 - -
C2
+
+
v 2
g m2 v 2
v out
r o2
-
-

C1=E2

R L

2TA01

β o2 (r o2 ||R L )(1+β o1 )

r π1 + (1+β o1 )r π2

-g m2 (r o2 ||R L )

o2 (1+β o1

β

)

r π1 + (1+β o1

)r π2

β o2 (1+β o1 )

Increased input resistance and current gain.

ECE 4430 - Analog Integrated Circuits and Systems+ (1+ β o 1 ) r π 2 β o 2 (1+ β o 1

P.E. Allen

Two-Transistor Amplifiers (6/13/00) r π 1 = r π 2 = and β ο 1 V t 100·26mV

Two-Transistor Amplifiers (6/13/00) r π 1 = r π 2 = and β ο 1 V

r π1 =

r π2 =

and

β ο1 V t

100·26mV

I C1

= 11µA

β ο2 V t

100·26mV

I C2

= 100µA

= 236k,

= 26k,

g m2 = I V C t

= 100µA

26mV

= 38.4mS

Page 3

m 2 = I V C t = 100µA 26mV = 38.4mS Page 3 Example 1
m 2 = I V C t = 100µA 26mV = 38.4mS Page 3 Example 1

Example 1 - Calculation of Small-Signal Performance for the CC-CC Configuration Find the small-signal input resistance, output resistance, voltage gain, and

current gain for the composite transistor shown. Assume for both devices, that β o = 100, r b = 0, and r o = ∞. Assume for Q2 that I C = 100µA and that I bias = 10µA. Solution The small-signal model is shown. The values of the parameters are found as,

V V CC R L = 10k in Q1 I Bias =10µA
V
V
CC
R L =
10k
in
Q1
I Bias
=10µA

v

Q2

CC

100µA

v out

2TA01A

v

i i in + v 1 out B1 - E1 = B2 C2 + +
i
i
in
+ v 1
out
B1
-
E1 = B2
C2
+
+
+
r 1
in
g m1 v 1
r 2
r o1
v 2
g m2 v 2
v
out
R
L
r o2
-
-
-
C1=E2
2TA01B

R in = 236k+ (100)26k= 2.84M

R out = 10k(if R L is included)

v out

v

in

i out

i in

= -

β o2 (r o2 ||R L )(1+β o1 )

R

in

= - 100·10k·101

2.84M

= -35.56V/V

= β o2 (1+β o1 ) = 100·101 = 10,100A/A

ECE 4430 - Analog Integrated Circuits and Systems

P.E. Allen

Two-Transistor Amplifiers (6/13/00) Page 4 Common Collector-Common Collector Circuit: V CC V CC In Q1 Q2 Out I

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Two-Transistor Amplifiers (6/13/00) Page 4 Common Collector-Common Collector Circuit: V CC V CC In Q1 Q2
Two-Transistor Amplifiers (6/13/00) Page 4 Common Collector-Common Collector Circuit: V CC V CC In Q1 Q2

Common

Collector-Common

Collector

Circuit:

V CC V CC In Q1 Q2 Out I Bias
V
CC
V
CC
In
Q1
Q2
Out
I Bias

B1

i

in

Small-signal performance (I Bias <<I C2 ):

v

1

i

out

+ - E1 = B2 r 1 g m1 v 1 r o1
+
- E1 = B2
r 1
g m1 v 1
r o1
+ - + r 2 g m2 v 2 v out r o2 -
+
-
+
r 2
g
m2 v 2
v out
r o2
-

2TA02

v

2

E2

r o1 + - + r 2 g m2 v 2 v out r o2 -

+

v in

-
-

C1=C2

R in = r π1 + (1+β o1 )[r π2 +(1+β o21 )(r o2 ||R L )] (1+β o1 )(1+β o21 )(r o2 ||R L )

R out =

R S +r π1

1+β o1 + r π2

1+β o2

v out

v in

i out

i in

1

= (1+β o2 )(1+β o1 )

R S +r π1 +r π2 (1+β o1 )

= (1+β o1 ) (1+β o2 )

1

g m2

Very high input resistance and very low output resistance.

ECE 4430 - Analog Integrated Circuits and Systemsβ o 1 ) (1+ β o 2 ) ≈ 1 g m 2 Very high

P.E. Allen

Two-Transistor Amplifiers (6/13/00) Darlington Configuration Circuit: B Q1 I Bias C Q2 E Page 5 E1 = r

Darlington Configuration Circuit: B Q1 I Bias
Darlington
Configuration
Circuit:
B
Q1
I Bias

C

Q2

E

Page 5

Configuration Circuit: B Q1 I Bias C Q2 E Page 5 E1 = r o1 +
Configuration Circuit: B Q1 I Bias C Q2 E Page 5 E1 = r o1 +
E1 = r o1 + v 1 C1=C2 B1 - B2 + + + r
E1 =
r o1
+ v 1
C1=C2
B1
-
B2
+
+
+
r 1
g m1 v 1
v be
r 2
v ce
v 2
r o2
g m2 v 2
-
-
-

C1=E2

2TA03

The Darlington configuration can be CE, CB, or CC. For common-emitter (β o >>1) with a collector resistance of R L :

R in = r π1 + (1+β o1 )r π2 ,

R out r o2 ,

v o u t =

v out =

v in

v in

-β o1 β o2 R L

r π1 +β o1 r π2

Replacing r π1 and r π2 by their large-signal equivalents (r π = β ο V t I C

v out =

v in

-β o1 β o2 R L

β o1 β o2 V t + β o1 β o2 V t

I

C2

I

C2

-g m2 R L

= 2

(Input “base-emitter” voltage is divided across the two transistors)

) gives,

ECE 4430 - Analog Integrated Circuits and Systemsg m 2 R L = 2 (Input “base-emitter” voltage is divided across the two transistors)

P.E. Allen

Two-Transistor Amplifiers (6/13/00) Page 6 BiCMOS Darlington Configuration Circuit: "B" M1 I Bias "C" Q2 "E" r ds

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Two-Transistor Amplifiers (6/13/00) Page 6 BiCMOS Darlington Configuration Circuit: "B" M1 I Bias "C"
Two-Transistor Amplifiers (6/13/00) Page 6 BiCMOS Darlington Configuration Circuit: "B" M1 I Bias "C"

BiCMOS Darlington Configuration Circuit:

"B" M1 I Bias
"B"
M1
I
Bias

"C"

Q2

"E"

"B" M1 I Bias "C" Q2 "E" r ds 1 D1=C2 + v ce - S1
"B" M1 I Bias "C" Q2 "E" r ds 1 D1=C2 + v ce - S1

r ds1

M1 I Bias "C" Q2 "E" r ds 1 D1=C2 + v ce - S1 =

D1=C2

M1 I Bias "C" Q2 "E" r ds 1 D1=C2 + v ce - S1 =

+

v

ce

-

S1 =

B2

G1

+ +

v

+

be

-
-
- + g m1 v gs1 v 2 r o2 g m2 v 2 -
-
+
g m1 v gs1
v 2
r o2
g m2 v 2
-

D1=E2

v gs1

r 2

+ g m1 v gs1 v 2 r o2 g m2 v 2 - D1=E2 v

2TA04

For the common-emitter configuration (β o >>1 and r ds1 negligible) with R L >>r o2 :

R in =

R out r o2

v out

v

in

i out

i in

=

   v gs1   v in

 

out

v

gs1

v

=

=

-g

m1 +g m1 g m2 r π2

1

g

o2

1+g m1 r π2

=

-g m1 (1+g m2 r π2 )

g o2 (1+g m1 r π2 ) -g m1 ro2

if g m1 g m2

Note that the input dc voltage consists of V GS +V BE which is around 2V.

ECE 4430 - Analog Integrated Circuits and Systems1 ≈ g m 2 Note that the input dc voltage consists of V G S

P.E. Allen

Two-Transistor Amplifiers (6/13/00) BJT Cascode Amplifer Circuit and small-signal model: r Page 7 CASCODE CONFIGURATION v a v

BJT Cascode Amplifer Circuit and small-signal model:

r

Page 7

Cascode Amplifer Circuit and small-signal model: r Page 7 CASCODE CONFIGURATION v a v out Q2
Cascode Amplifer Circuit and small-signal model: r Page 7 CASCODE CONFIGURATION v a v out Q2

CASCODE CONFIGURATION

v a v out Q2 R L v in Q1 V Bias V CC
v a
v out
Q2
R L
v in
Q1
V Bias
V
CC

If β 1 β 2 and r o can be neglected, then:

R in = r π1

R out β 2 r o2

v

   v in

 

out

v

in

v

out

v

a

=

v

a

i out

i in

= α 2 β 1

=

(g m2 R L )

π2

i in i out B1 C1 = E2 C2 r o2 + + - +
i in
i out
B1
C1 = E2
C2
r o2
+
+
-
+
v
r
in
1 r o1
v a
v 2
v out
g m1 v 1
r
2
g m2 v 2
-
+
-
-
E1=B2
2TA05

R L

· -β o1

r

π1

  (g m2 R L ) (-1) = - g m2 R L

1+β o2

The advantage of the cascode is that the gain of Q1 is -1 and therefore the Miller capacitor, C µ , is not translated to the base-emitter as a large capacitor.

ECE 4430 - Analog Integrated Circuits and Systemstherefore the Miller capacitor, C µ , is not translated to the base-emitter as a large

P.E. Allen

Two-Transistor Amplifiers (6/13/00) Page 8 BJT Cascode Amplifier Frequency Response Small-Signal Model with the Miller effect applied to

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Two-Transistor Amplifiers (6/13/00) Page 8 BJT Cascode Amplifier Frequency Response Small-Signal Model with the Miller
Two-Transistor Amplifiers (6/13/00) Page 8 BJT Cascode Amplifier Frequency Response Small-Signal Model with the Miller

BJT Cascode Amplifier Frequency Response Small-Signal Model with the Miller effect applied to C µ1 assuming v a /v in = -1:

C µ1 B1 C1 = E2 r o2 C2 + + + - + 2C
C µ1
B1
C1 = E2
r o2
C2
+
+
+
-
+
2C µ1
v in
C 1
v a
v
r 1
v 1
r o1
v 2
C µ2
out
g m1 v 1
r
2
2C µ1
R
g m2 v 2
L
-
+
C 2
-
-
-
E1=B2
2TA06

Find the -3dB frequency, f -3dB using the following formula:

f -3dB

1

2π·Σ(Open-circuit time constants)

τ in = r π1 (C π1 +2C µ1 ),

f -3dB

τ interstage =

r π2

1+β o2 (C π2 +2C µ1 ),

1

and

τ out = R L C µ2

1

2πR L C µ2

2π·   r π1 (C π1 +2C µ1 ) +

r

π2

1+β o2 (C π2 +2C µ1 ) + R L C µ2

ECE 4430 - Analog Integrated Circuits and Systems+2 C µ 1 ) + r π 2 1 + β o 2 ( C

P.E. Allen

Two-Transistor Amplifiers (6/13/00) MOS Cascode Amplifier Circuit and small-signal model: v in M2 v out Page 9 g

MOS Cascode Amplifier Circuit and small-signal model:

v in

MOS Cascode Amplifier Circuit and small-signal model: v in M2 v out Page 9 g m

M2

v out

Page 9

Circuit and small-signal model: v in M2 v out Page 9 g m 2 v gs
g
g

m2 v gs2 = -g m2 v 1

D2=D3

G1 + v in = M1 V Bias v gs1 g m1 v gs1 -
G1
+
v in =
M1
V Bias
v
gs1
g m1 v gs1
-

D1=S2

+ r ds2 v 1 R L - S1=G2=G3
+
r ds2
v 1
R L
- S1=G2=G3
v gs1 g m1 v gs1 - D1=S2 + r ds2 v 1 R L -

+

v out

-
-

r ds1

2TA07

Small-signal performance (assuming a load resistance in the drain of R L ):

R in = Using nodal analysis, we can write,

[g ds1 + g ds2 + g m2 ]v 1

g ds2 v out = g m1 v in

[g ds2 + g m2 ]v 1 + (g ds2 + G L )v out = 0

Solving for v out /v in yields,

v out

v in

=

g m1 (g ds2 + g m2 )

+ G L g m2 -g m1

G

L

g ds1 g ds2 + g ds1 G L + g ds2 G L

= -g m1 R L

Note that unlike the BJT cascode, the voltage gain, v 1 /v in is greater than -1.

v 1

v in = - g m2

r ds2 ||

r

ds2 +R L

 

1+g m2 r ds2  

- r ds2 +R L

r ds2

= -

1+ R L

r

ds2

The small-signal output resistance is,

r out = [r ds1 + r ds2 + g m2 r ds1 r ds2 ]R L R L

(R L must be less than r ds2 for the gain to be -1)

ECE 4430 - Analog Integrated Circuits and Systemsds 1 r ds 2 ]  R L ≅ R L ( R L must

must be less than r d s 2 for the gain to be -1) ECE 4430

P.E. Allen

Two-Transistor Amplifiers (6/13/00) Page 10 MOS Cascode Amplifier Frequency Response Small-signal model ( g m 2 v 1

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Two-Transistor Amplifiers (6/13/00) Page 10 MOS Cascode Amplifier Frequency Response Small-signal model ( g m 2
Two-Transistor Amplifiers (6/13/00) Page 10 MOS Cascode Amplifier Frequency Response Small-signal model ( g m 2

MOS Cascode Amplifier Frequency Response Small-signal model (g m2 v 1 has been rearranged and the substitution theorem applied):

v

C 1 r ds2 G1 D1=S2 D2=D3 + + + in 1 g v g
C
1
r
ds2
G1
D1=S2
D2=D3
+
+
+
in
1
g
v
g
C 2
r
C
m1 v in
1
m2 v 1
ds3
3
v
out
R L
r
ds1
g m2
-
-
-
2TA075

C 1 = C gd 1 , C 2 = C bd 1 + C bs 2 + C gs 2 and C 3 = C bd 2 + C bd 3 + C gd 2 + C gd 3 + C L

where

The nodal equations now become:

and

Solving for V out (s)/V in (s) gives,

where

out (s) V in (s)

V

1

= 1 + as + bs 2

(g m2 + g ds1 + g ds2 + sC 1 + sC 2 )v 1 g ds2 v out = −(g m1 sC 1 )v in

(g ds2 + g m2 )v 1 + (g ds2 + g ds3 +G L + sC 3 )v out = 0

(g

m1 sC 1 )(g ds2 + g m2 )

g ds1 g ds2 + (g ds3 +G L )(g m2 + g ds1 + g ds2 )

+

a = C 3 (g ds1 + g ds2 + g m2 ) + C 2 (g ds2 + g ds3 + G L )

C 1 (g ds2 + g ds3 )

g ds1 g ds2 + (g ds3 + G L )(g m2 + g ds1 + g ds2 )

C 3 (C 1 + C 2 )

and

b =

g ds1 g ds2 + (g ds3 +G L )(g m2 + g ds1 + g ds2 )

ECE 4430 - Analog Integrated Circuits and Systems= g ds 1 g ds 2 + ( g ds 3 + G L )

P.E. Allen

Two-Transistor Amplifiers (6/13/00) Page 11 A Simplified Method of Finding an Algebraic Expression for the Two Poles Assume

Page 11

Two-Transistor Amplifiers (6/13/00) Page 11 A Simplified Method of Finding an Algebraic Expression for the Two
Two-Transistor Amplifiers (6/13/00) Page 11 A Simplified Method of Finding an Algebraic Expression for the Two

A Simplified Method of Finding an Algebraic Expression for the Two Poles Assume that a general second-order polynomial can be written as:

P(s) = 1 + as + bs 2 =

1

 

s

p

1

1

s

p

2

= 1 s

Now if |p 2 | >> |p 1 |, then P(s) can be simplified as s 2

P(s) 1

s

p 1 + p 1 p 2

1

1 +

p

1

p

2

+

s 2

p 1 p 2

Therefore we may write p 1 and p 2 in terms of a and b as

p 1 = 1

a

and

p 2 = a

b

Applying this to the previous problem gives,

p 1 =

[g ds1 g ds2 + (g ds3 +G L )(g m2

)]

+ g ds1 + g ds2

ds2 + g ds3 +G L ) −(g ds3 +G L )

C

3

g m2

C 1 + C 2

C 3 (g ds1 + g ds2 + g m2 ) + C 2 (g

ds2 + g ds3 +G L ) + C 1 (g

+ g ds3 +G L )

The nondominant root p 2 is given as

p

2 = −[C 3 (g ds1

+ g ds2 + g m2 ) + C 2 (g ds2

+ C 1 (g ds2 + g ds3 +G L )]

C 3 (C 1 + C 2 )

Assuming that C 1 , C 2 , and C 3 are the same order of magnitude, and that g m2 is greater than g ds3 , then |p 1 | is smaller than |p 2 | (closer to the origin). Therefore the approximation of |p 2 | >> |p 1 | is valid.

Note that there is a right-half plane zero at z 1 = g m 1 C 1

.

ECE 4430 - Analog Integrated Circuits and Systems| p 1 | is valid. Note that there is a right-half plane zero at z

P.E. Allen

Two-Transistor Amplifiers (6/13/00) BiCMOS Cascode Amplifier Circuits: Comparison: Page 12 v out v out M2 Q2 v in

BiCMOS Cascode Amplifier Circuits:

Comparison:

Page 12

BiCMOS Cascode Amplifier Circuits: Comparison: Page 12 v out v out M2 Q2 v in v
BiCMOS Cascode Amplifier Circuits: Comparison: Page 12 v out v out M2 Q2 v in v
v out v out M2 Q2 v in v in Q1 M1 V V Bias
v out
v out
M2
Q2
v in
v in
Q1
M1
V
V Bias
Bias
2TA08

Larger voltage gain Infinite input resistance

Smaller input resistance Q1 voltage gain greater than -1V/V

High output resistance High output resistance

Requires input current

Smaller voltage gain M1 voltage gain less than -1V/V

Does not require input current

ECE 4430 - Analog Integrated Circuits and SystemsRequires input current Smaller voltage gain M1 voltage gain less than -1V/V Does not require input

P.E. Allen

Two-Transistor Amplifiers (6/13/00) Page 13 SUMMARY Advantages of two-transistors: • Higher input resistance (BJTs) • Lower output resistance

Page 13

Two-Transistor Amplifiers (6/13/00) Page 13 SUMMARY Advantages of two-transistors: • Higher input resistance (BJTs) •
Two-Transistor Amplifiers (6/13/00) Page 13 SUMMARY Advantages of two-transistors: • Higher input resistance (BJTs) •

SUMMARY

Advantages of two-transistors:

• Higher input resistance (BJTs)

• Lower output resistance

• Higher current gain (BJTs)

Things that are important for future use:

• The upper -3dB frequency can be approximated by the reciprocal of the sum of the OTCs (p. 8)

• A quadratic can be solved algebraically by assuming the roots are widely spaced (p. 11)

ECE 4430 - Analog Integrated Circuits and SystemsOTCs (p. 8) • A quadratic can be solved algebraically by assuming the roots are widely

P.E. Allen