2010 2nd IEEE International Symposium on Power Electronics for Distributed Generation Systems

FPGA-Based Multi-level Inverter Multi-carrier Pulse Generation Theory and Implementation Method
Jinghua Zhou, Shaowei Zhang, Xiaowei Zhang, and Zhengxi Li
Power electronics and motor drives engineering center, North China University of Technology, Beijing Abstract-- Multi-module cascaded multi-level inverters are more and more widely used in high voltage and large power industrial applications. Its unique topological structure requires multi-channel drive pulse. Therefore, generating multi-channel drive pulse becomes one of the key issues. This paper presents a digital implementation method, which combines double and multicarrier horizontal phase shift PWM modulation strategy in terms of H-bridge cascaded multi-level inverter, describes the multicarrier pulse generating theory in detail, and offers the specific implementation method for a kind of general purpose multicarrier pulse generator based on FPGA. Finally, a set of multi-level inverter digital experimental system was built based on DSP and FPGA. The experimental results indicate that the multiple-pulse digital implementation method features outstanding expandability and commonality. Index Terms-- Double; multicarrier horizontal phase shift; general purpose multiple-pulse generator; FPGA.

digital experimental systems was built to solve the practical problem of how to realize the digital implementation of multicarrier PWM pulse generator. Take the implementation of the 36-channel PWM generator of 7- level inverter for example; this paper presents the generation theory, composition principle and specific implementation method of general purpose multicarrier pulse generator. The experimental results indicate that the FPGA-based multicarrier pulse generator realizes correct distribution of drive pulse, and features strong commonality and flexible configuration. II. A MODULATION STRATEGY COMBINING DOUBLE AND MULTICARRIER HORIZONTAL PHASE SHIFT METHODS This paper realizes multi-channel drive pulse using the modulation strategy that combines double and multicarrier horizontal phase shift method. Fig. 1 shows the structure of three-phase 3-module cascaded multilevel inverter. Phase A is taken for example (Fig. 2) to explain this kind of modulation strategy.

I. INTRODUCTION In recent years, multi-module cascaded multi-level inverters have been widely used in large power and high voltage applications [1]. Unlike traditional 2-level inverter, multi-level inverter features multiple drive pulses and complex calculations. Furthermore, existing digital signal processors (DSP) such as TMS320F2812 and TMS320F28335 have 12 channel PWM drive pulses, but they can only be used by up to three-level inverters, and are not applicable to multi-level inverters. Therefore, an interface problem of drive pulse occurs between DSP and switches of multi-level inverter [2]. Field programmable gate array (FPGA) includes a few hundreds to tens of thousands of logic gates, and it has several hundreds of optionally configurable registers and I/O ports. In addition, it enjoys advantages such as short development cycle, fast, high integration level and strong flexibility, etc. Therefore, it is able to realize multiple functions through flexible configurations without changing hardware circuits. Meanwhile, it is capable of optimizing and expanding the control system through deployment of DSP chip that have fast arithmetic capability and finally enhancing the commonality of the system. This paper employs a modulation strategy combining double and multicarrier horizontal phase shift functions in terms of multi-module cascaded topological structure. Based on DSP and FPGA, a set of multi-level inverter
Supported by Beijing Novel Program

Fig. 1 Structural diagram of three-phase 3-module cascaded multi-level inverter

Fig.2 Structural diagram of phase A 3-module cascaded multi-level inverter

978-1-4244-5670-3/10/$26.00 ©2010 IEEE


Fig. second and third module as shown in Fig. the calculated interruption frequency of pulse width value will be three times of carrier frequency. the first. in accordance with triangle algebraic relation. the signal of the positive and negative counting direction that reacts to reversible counting direction shall be generated firstly. sinθn is the sine value of the n sampling cycle. the trigger signals of 3 modules pulse width latches of phase A are respectively latch_1. it is critical to form the multi-carrier and accurately lock the 573 . and the difference of phase of their modulation waves is 180°. 5. In Fig. 3. N Ts U sin θ n (2) W a 1 = t1 = t 3 = (2 NTs − t 2 ) / 2 = (1 − r ) 4 UΔ Wa 2 NTs U sin θ n = t = t = (2 NTs − t ) / 2 = (1 + r ) 4 UΔ ' 1 ' 3 ' 2 In order to obtain a carrier generator with different initial phase in the FPGA and achieve carrier phaseshifting effectiveness. and that is. and then the carrier generator will be enabled to accomplish reversible counting. if the carrier amplitude is set to K. 2. In Fig. as shown in Fig. 4 Schematic diagram of double modulation method Fig. The pulse width interruption (3) Where. 2. A. with respect to 3-channel triangle carrier as required. For N module cascade. In Fig. in order to realize above-mentioned modulation strategy. MULTICARRIER PULSE GENERATION THEORY Considering the multi-module cascaded inverter. latch_2 and latch_3. This signal is actually the plus and minus counting signal of carrier counter. the carrier cycle is Tc. In Fig. the interruption interval is Tc/3. it is required to set the initial carrier value as well as initial counting direction by DSP. 6. therefore.phases between carriers to ensure satisfactory harmonic characteristics of inverter output [3].4. but its initial counting direction is increment. B. The phase shift between carriers is Ts = Tc/3. it can be observed that the carrier cycle Tc = NTs. With respect to multi-module cascaded multilevel inverter. The third channel of carrier delays 2Tc/3 compared to the first channel. (2) and (3) can be deduced accordingly. 3. Ts is a sampling cycle and also the phase shift between various carriers. 6. The schematic diagram of double modulation method adopted by each power module is shown in Fig. Wa1 and Wa2 respectively correspond to pulse width value of pulse width register of PWM_A1 and PWM_A3 in Fig. This paper presents a kind of accurate positioning method for phase relation. And the carrier phase shift principle is shown in Fig. The calculation of (2) and (3) can be performed by DSP. 2. and its initial counting direction is increment. 2 Fig. In addition. In accordance with this principle. Formation of multicarrier As shown in Fig. the harmonic waves of such modulation strategy are 2Nfc and its multiples sideband harmonic waves. Ur(t) and -Ur(t) are the modulation waves of the left and right bridge arm of some module in the Fig. 2. the initial phase of the first channel of carrier is 0. 5. III. 3 shows double modulation method and the relation of carrier phase corresponding to Fig. 6. N (1) According to (1). U Δi (t ) = U Δ1[t + (i − 1)Tc / N ] = U Δ1[t + (i − 1)Ts ] i = 1. and its initial counting direction is decrement. U△1. and it is the square wave with a cycle of Tc and the trigger signal of each pulse width latch as well. 4. the phase shift between adjacent carriers is Tc/3. the phase relation between carriers is the key to ensure the superior characteristics of this modulation strategy. and the amplitude is also 2K/3. the relation between the i triangle carrier U△i and the first carrier U△1 can be expressed by (1). the updating time for pulse width data is different due to phase shift. DSP continuously refreshes the value of two pulse width registers in Ts. more carriers can be designed only if the DSP sets the initial values and the initial counting direction of each carrier counter. Implementation method for accurate locking of phase between multicarriers In the multi-carrier horizontal phase-shifting modulation strategy. The second channel of carrier delays Tc/3 compared to the first channel in phase and the amplitude is 2K/3. 5 Schematic diagram of three-carrier phase shift Fig. namely. and takes phase A for example. U△2 and U△3 correspond to three channels of carriers. and fc refers to carrier frequency. 6. the initial value is 0. For the 3-channel carrier reversible counter. as shown in Fig. 2. the 3-channel triangle carrier can best illustrate the formation of multicarrier phase shift generator. 3 Explanatory diagram of double modulation method and carrier phase relation corresponding to Fig. In Fig.

(ⅲ) The pulse width register: It is used as a shadow register.0] Fig.0]" of LPM_COMPARE respectively connect to the pulse width latch register and carrier phase shift generator. 6.. 7.. lpm_compare0 unsigned compare Fig. “PWM_A1_en”. dead zone register and counting peak value register to realize correct distribution of different data.. as shown in Fig. The input signal is completely identical to the output signal of the above-mentioned decoder.. In Fig.0]”. “PWM_A9_en” and “PWM_A11_en” are respectively trigger signals of the phase A pulse width register. which are all supplied by DSP.0] q[15. latch_2.. Take phase A for example. the input signal contain data input "data [15. 8 Decoder diagram Fig.0] datab[15. lpm_dff1 data[15. The output signal is the data output "q [15.0] ins t6 counter_1[15.trigger signal can be obtained via latch_1. “PWM_A3_en”. “Counter_1 [15.0]".. 10 Pulse width register Fig. As shown in Fig..0] ". Fig... which can be expressed by logic formula: (latch_1 or latch_2) and (latch_2 or latch_3) and (latch_3 or latch_1).0]” to "q [15. “init_ en2” and “init_en3” are respectively initial value register Fig. "Load" is carrier initial value load trigger signal. the latch trigger signal “G” and control signal "OEN". 11 Pulse width latch Fig. and latch_3. “Latch_1”. the pulse width value which has been updated will be put into the pulse width latch. “counter_2 [15.18] rw PW M_A1_en PW M_A5_en PW M_A9_en PW M_A3_en PW M_A7_en PWM_A11_en int_en1 int_en2 int_en3 peak_en dead_en inst3 carrier_123 clk load en init_en1 peak_en init_en2 init_en3 data[15. it is allowed to assign “D [15.18]” are address bus. 6 Logic synthesis diagram of pulse width latch and interruption trigger signal for pulse width calculation. “add_low[4. 7 Phase A PWM generator structure ( ⅰ ) Decoder: It mainly performs decoding for the address bus and control signal supplied by DSP and therefore generates trigger signals of each pulse width register.0] latch_3 ( ⅳ ) The pulse width latch: When the latch trigger signal occurs.0] clock inst1 DFF reg D[15. IV. which connects to the data bus of DSP and clock signal "clock".0]".. SPECIFIC IMPLEMENTATION METHOD OF MULTICHANNEL DRIVE PULSE This paper takes 3-module cascaded three-phase inverters for example and sets up a 36-channel PWM generator. DSP can update the pulse width register during any time of the control cycle.0]” and “counter_3 [15.. it assigns the updated data “data [15.0]” to “Q [15... which connects to the pulse width register trigger signal. The two inputs "data [15. These comparisons will be respectively conducted during an incrementing and decrementing counting period. “PWM_A7_en”.0] add_high[ 23.0]”. At the rising edge of the signal “clock”. “init_ en1”. the input signal contain data input “D [15. 2 and 3 of carrier phase shift generator.. When the value of "OEN" is 1. it generates the PWM signals of different pulse width values.. 12 PWM Comparator The comparison will be performed by Quartus II parameterized comparator LPM_COMPARE module. 574 . when a latch trigger signal occurs. 2 and 3 of phase A. 8.. Accordingly.0]" and "datab [15.. trigger signals of the carrier in channel 1.. “Peak_en” is the trigger signal of carrier counting peak value register.0] G OEN inst30 Q[15....0] latch_1 counter_2[15. 10.0] latch_2 counter_3[15. “latch_2” and “latch _3” respectively correspond to the pulse width latch trigger signal of module 1. The trigger signal can be sent into the DSP external interruption INT0 to determine the updating time of pulse width data..0]” respectively correspond to the channel 1. "En" is carrier counting trigger signal..0]” and “add_high[23. Fig. 2 and 3 of the carrier counting signal. (ⅴ) The PWM comparator: In accordance with Fig..0]” is set to zero. the corresponding carrier counter starts reversible counting from 0. carrier counting value and pulse width value will be compared twice for matching purpose. As shown in Fig.8 shows the decoder realized in QuartusII. the 12channel PWM generator structure is shown in Fig.0] inst9 aleb Fig. 12. 9 Carrier phase shift generator dataa[15.. and “rw” is control signal.. PW M_decode add_low[4. otherwise “Q [15. Within one carrier cycle. 9 shows the carrier phase shift generator that is realized in QuartusII. which consists of 3 single-phase 12-channel PWM generators. “PWM_A5_en”.0]”. 11. ( ⅱ ) Carrier phase shift generator: It is used to generate multi-channel triangle carrier signals and a reversible counter..

an experimental study is performed to verify the generation theory and implementation method of multichannel drive pulse. Different kinds of registers as described in FPGA are configured by Fig. 6.5 kHz. 17 shows the 7-level step wave of 3-module cascaded inverter and its spectrum analysis.V. 13 Connection block between DSP and FPGA In Fig. and exactly is 1/3 of carrier cycle. and dead zone time is 4 µs. carrier frequency fc is 2. 16 shows the drive signals PWM_A1 and PWM_A5 of the left upper bridge arm of the module 1 and 2 in phase A. it also validates the feasibility of FPGA-based multi-channel PWM pulse generation methods.16. The spectrum analysis of Fig. Fig. 13 shows the connection block between DSP and FPGA. Fig. this method is identical to the requirement for simultaneous transmission of two channels of pulse width values to FPGA and the requirement for simultaneous generation. The DSP adopts a floating point signal processor TMS320VC33 to configure different kinds of registers in FPGA and calculate the pulse width values. 15 shows the trigger signals of pulse width latches corresponding to that of Fig. 14 Drive waveform PWM_A1 and PWM_A3 of the first module of phase A Fig. The programming software is of QuartusII. VI. the drive s PWM_A1 and PWM_A3 of the first module of phase A comply with (2) and (3) after using double modulation method. and this analysis result is identical to the theoretical analysis. 16 Drive signals PWM_A1 and PWM_A5 of left upper bridge arm of the module 1 and 2 of phase A R/ W Fig. adopting double and multicarrier horizontal phase shift modulation strategy. 6. modulation wave frequency is 50Hz. Fig. describes in detail the multicarrier pulse generation theory and specific implementation methods. 15. Theoretically. meanwhile. 15 Pulse width latch trigger signal corresponding to Fig. 17 indicates the harmonic waves that are put out by 7-level step wave are mainly located at 2Nfc = 15 kHz and its side-band harmonic waves. During the experiment. Fig. 6 575 . a kind of digital logic method is proposed for accurate positioning of multicarrier phase. CONCLUSIONS This paper presents a kind of modulation strategy that combines double and multicarrier horizontal phase shift methods in terms of multi-module cascaded multilevel inverter. and describes the constituent elements of general purpose multicarrier pulse generator. the external crystal oscillator of the FPGA chip is 15M. 14. Experimental results are completely identical to the trigger signal of pulse width latch of each module and DSP external interruption trigger signal as analyzed in Fig.5 kHz. which is identical to the above-mentioned multicarrier phase shift theory. This further proves the validity of the multicarrier phase locking method. it can be observed that the phase shift between them is one-third of the carrier cycle. In Fig. Based on FPGA. EXPERIMENTAL RESULTS Based on a digital experimental system platform combining DSP and FPGA. 17 A 7-level step wave and its spectrum analysis diagram Fig. which is used to generate PWM drive pulse. Fig. namely 133 µs. it can be observed that triple frequency signal cycle is 133 µs. The FPGA chip adopts CycloneII serial EP2C5Q208C8. solves the key issues for multilevel inverter multi-channel drive pulse. sampling frequency is 7. According to Fig.

2003. Multilevel Inverter Modulation Schemes to Elimination Common-mode Voltages [J]. Joanne A. And the configuration process is clear to the user. [3] Zhang H. 2000. et al. which are the same as the usage of registers inside the DSP. [2] Li S Mi. 2002. Xu L Y. Controls. 36 (6): 1645-1653. Multilevel Inverter: A Survey of Topologies. Finally. on Power Electronics. IEEE Trans. IEEE Trans. based on DSP and FPGA. 49 (4):724-738. on IND. and Applications [J].DSP. 7 (3): 497-505. Elect. 576 . Appl. on Ind. The experimental results prove the multicarrier pulse generation method is correct. A DSP Peripheral Design for Three-level Inverter Space Vector PWM Modulations [J]. Dai S. a digital experimental platform was built to carry out experimental verification for the above-mentioned methods. REFERENCES [1] Lai J S. IEEE Trans.