64CH SEGMENT DRIVER FOR DOT MATRIX LCD

S6B0108

INTRODUCTION
The S6B0108 (TQFP type: S6B2108) is a LCD driver LSI with 64 channel output for dot matrix liquid crystal graphic display systems. This device consists of the display RAM, 64 bit data latch, 64 bit drivers and decoder logic. It has the internal display RAM for storing the display data transferred from a 8 bit micro controller and generates the dot matrix Iiquid crystal driving signals corresponding to stored data. The S6B0108 composed of the liquid crystal display system in combination with the S6B0107 (64 channel common driver -TQFP type: S6B2107).

FEATURES
• • Dot matrix LCD segment driver with 64 channel output Input and output signal - Input: 8 bit parallel display data control signal from MPU divided bias voltage (V0R, V0L, V2R, V2L, V3R, V3L, V5R, V5L) - Output: 64 channel for LCD driving. Display data is stored in display data RAM from MPU. Interface RAM - Capacity: 512 bytes (4096 bits) - RAM bit data: RAM bit data = 1: On RAM bit data = 0: Off Applicable LCD duty: 1/32-1/64 LCD driving voltage: 8V-17V (VDD-VEE) Power supply voltage: + 5V ± 10% Interface Drivers Common S6B0107 • High voltage CMOS process. • 100QFP / 100TQFP or bare chip available. Segment Other S6B0108

• •

• • • •

Controller MPU

1

S6B0108

64CH SEGMENT DRIVER FOR DOT MATRIX LCD

BLOCK DIAGRAM
CLK1 DB<0:7> CLK2

8

8

Display On/Off
1

Busy

Instruction Decoder

6

Y-Counter
6

3

I/O Buffer

Input Register

Output Register

CS1B CS2B CS3 R/W RS E RSTB

ADC

6

Y-Counter
64

X-Decoder
8

6

64

Display Data RAM 512 × 8 = 4096bits

8

FRM

64

Data Latch

64

V0L V2L V3L V5L M LCD Driver

Page Selector

CL

Display Start Line Register

Z-Decoder

V0R V2R V3R V5R

S2

2

S64

S63

S1

64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 PIN CONFIGURATION 100 QFP RSTB CS1B CS1B CS2B CLK1 CLK2 FRM CS3 DB7 DB6 DB5 DB4 83 DB3 82 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 81 DB2 R/W NC NC NC CL E ADC M VDD V3R V2R V5R V0R VEE2 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 42 43 44 45 46 47 48 49 50 DB1 DB0 VSS V3L V2L V5L V0L VEE1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 40 S33 S42 S41 S40 S39 S38 S37 S36 S35 S34 S32 41 S31 S30 S29 S28 S27 S26 S25 S24 S23 S6B0108 3 .

4 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 . 0) X Chip size: 4090 × 4020 PAD size: 100 × 100 Unit : µm 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 V3L V2L V5L V0L VEE1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 There is mark of S6B0108 on the bottom left in the chip.S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD PAD DIAGRAM (CHIP LA YOUT FOR THE 100QFP) V3R V2R V5R V0R VEE2 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 3 VDD 2 M 1 ADC 100 FRM 99 E 98 CLK1 97 CLK2 96 CL 95 RS 94 RW 93 RSTB 92 CS1B 91 CS2B 90 CS3 89 NC 88 NC 87 NC 86 DB7 85 DB6 84 DB5 83 DB4 82 DB3 81 DB2 80 DB1 79 DB0 78 VSS Y (0.

64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 PAD CENTER COORDINA TES (100QFP) PAD Number PAD Name Coordinate X 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ADC M VDD V3R V2R V5R V0R VEE2 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 -1140 -1275 -1410 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1487 -1187 -1062 -937 -812 Y 1845 1845 1845 1809 1684 1559 1434 1309 1165 1040 915 790 665 540 415 290 165 40 -84 -209 -334 -459 -584 -709 -834 -959 -1099 -1239 -1379 -1845 -1845 -1845 -1845 -1845 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 Pad Number Pad Name Coordinate X -687 -562 -437 -312 -187 -62 62 187 312 437 562 687 812 937 1062 1187 1487 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 Y -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1379 -1239 -1099 -959 -834 -709 -584 -459 -334 -209 -84 41 166 291 416 541 666 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 CS3 SC2B SC1B RSTB R/W RS CL P2 P1 E FRM S4 S3 S2 S1 VEE1 V0L V5L V2L V3L VSS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Pad Number Pad Name Coordinate X 1882 1882 1882 1882 1882 1882 1882 1882 1882 1412 1277 1142 1007 882 757 632 507 382 NC NC NC 245 120 -5 -130 -255 -380 -505 -630 -755 -880 -1005 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 Y 791 916 1041 1166 1310 1435 1559 1684 1809 1845 1845 1845 1845 1845 1845 1845 1845 1845 5 .

S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD 100TQFP (S6B2108) VDD V3R V2R V5R V0R VEE2 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 M ADC FRM E CLK1 CLK2 CL RS R/W RSTB NC CS1B NC CS2B CS3 NC DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VSS V3L V2L V5L V0L VEE1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 6 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 S6B2108 .

0) X Chip size: 4180 × 4030 PAD size: 100 × 100 Unit : µm 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 V3L V2L V5L V0L VEE1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 There is mark of S6B2108 on the bottom left in the chip. S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 7 .64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 PAD DIAGRAM (CHIP LA YOUT FOR THE 100TQFP) VDD V3R V2R V5R V0R VEE2 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 M ADC FRM E CLK1 CLK2 CL RS R/W RSTB NC CS1B NC CS2B CS3 NC DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VSS Y (0.

5 545.1 -990.1 -173.5 1849 1849 1849 1849 1849 1849 1849 1849 1849 8 .2 -342.3 Y 1812.5 795.8 -1312.2 -1256.7 334.5 1315.5 207.1 1225.5 -1064.9 -682.2 -592.3 -1118.3 -482.5 1812.9 917.9 -227.5 1312.5 -428.3 1352.8 NC -92.7 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 Y -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1245.9 1098.7 -736.2 906 778.1 408.S6B2108) Pad Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Pad Name VDD V3R V2R V5R V0R VEE S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 Coordinate X -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1573.2 -620.5 670.5 1033.8 157.3 716.5 1562.7 970.2 467.8 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 Y 1312.7 789.4 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 Pad Number Pad Name Coordinate X -301.9 -863.5 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 RSTB RW RS CL CLK2 CLK1 E FRW ADC M CS1B CS3 CS2B VEE V0L V5L V2L V3L VSS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Pad Number Pad Name Coordinate X 1924 1924 1924 1924 1924 1450.7 80.5 -609.5 1437.S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD PAD CENTER COORDINAT ES (100TQFP.8 -366 -493.7 -1191.1 -809.6 -111.1 -354.5 420.9 -1318.7 -100.5 1687.5 1437.5 920.5 1187.8 NC 32.6 -874.7 153.5 1045.5 NC 282.5 1562.2 -217.5 1180.1 -1445.5 843.3 535.2 -842.1 589.2 270 142.2 -967.1 1044.2 -717.8 15.5 1687.3 -937.7 -555.5 26.5 1479.9 462.2 -1177.3 1171.6 -238.9 -46.9 281.8 -1002 -1129.6 524.4 -747.4 397.8 651.5 662.

92(89) 91(87) 90(86) 2(100) 1(99) CS1B CS2B CS3 M ADC Input Chip selection In order to interface data for input or output.Y63: S64 ADC = L → Y0: S64 . Data or Instruction. 5(3) 77(75). Used to execute operations for input/output of display RAM data and others. V5R V0L and V0R (V2L & V2R. V3R V5L. V5L & V5R) should be connected by the same voltage. Power Select Level V0L(R). V0R V2L. Write mode (R/W = L) → data of DB<0:7> is latched at the falling edge of E. Display synchronous signal. RS = H → DB<0:7>: Display RAM data RS = L → DB<0:7>: Instruction data Input Input 100(98) FRM Input 99(97) E Input 98(96) 97(95) 96(94) CLK1 CLK2 CL Input Input 95(93) RS Input 9 . 4(2) 75(73). V2R V3L. V5L(R) Non-Select Level V2L(R).Y63: S1 Synchronous control signal. 2 phase clock signal for internal operation. 8(6) Symbol VDD VSS VEE1. Alternating signal input for LCD driving. VDD = +5V ± 10%. Address control signal to determine the relation between Y address of display RAM and terminals from which the data is output. V3L & V3R.17V VEE1 and VEE2 is connected by the same voltage.2 Input/Output Description For internal logic circuit (+5V ± 10%) GND (0V) For LCD driver circuit VSS = 0V. VDD-VEE = 8V . 6(4) V0L. ADC = H → Y0: S1 . Read mode (R/W = H) → DB<0:7> appears the reading data while E is at high level. CS2B = L. the terminals have to be CS1B = L. V3L(R) Power 74(72).64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 PIN DESCRIPTION Table 1. Presets the 6-bit Z counter and synchronizes the common signal with the frame signal when the frame signal becomes high. Bias supply voltage terminals to drive the LCD. Pin Description Pin Number QFP(TQFP) 3(1) 78(76) 73(71). and CS3 = H. Enable signal. Display data is latched at rising time of the CL signal and increments the Z-address counter at the CL falling time. 7(5) 76(74).

ON/OFF register becomes set by 0. When RSTB=L. R/W = H → Data appears at DB<0:7> and can be read by the CPU while E = H. this condition can be changed only by instruction. . display from line 0) After releasing reset. CS2B = L and CS3 = H . (display off) . R/W = L → Display data DB<0:7> can be written at falling of E when CS1B = L. Pin Description (Continued) Pin Number QFP(TQFP) 94(92) Symbol R/W Input/Output Input Description Read or Write. (open) 10 . Three state I/O common terminal. CS1B = L.S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD Table 1. LCD segment driver output. Display RAM data 1: On Display RAM data 0: Off (relation of display RAM data & M) M L H Data L H L H Output Level V2 V0 V3 V5 93(91) RSTB Input Reset signal. 79-86 (77-84) 72-9 (70-7) DB0-DB7 S1-S64 Input/Output Output Data bus. CS2B = L and CS3 = H. 88(88) 89(90) NC No connection.Display start line register becomes set by 0 (Z-address 0 set. 87(85).

DB7. Applies to M.3 -30 to +85 -55 to +125 Unit V V V V ¡ É ¡ É Note (1) (4) (1). RSTB. VLCD=VDD-VEE.64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 MAXIMUM ABSOLUTE LIM IT Characteristic Operating voltage Supply voltage Driver supply voltage Symbol VDD VEE VB VLCD Operating temperature Storage temperature TOPR TSTG Value -0. ADC. V3L(R) and V5L(R). Based on VSS = 0V. FRM.3 to VDD+0. 11 . CS2B.3 to VDD+0. CS1B. E.3 to +7. CLK1. 3.3 VEE-0. 4. V2L(R). 2.0 to VDD+0. CS3. R/W. RS and DB0 .3 -0. Applies the same supply voltage to VEE1 and VEE2. Voltage level: VDD ≥ V0L = V0R ≥ V2L = V2R ≥ V3L = V3R ≥ V5L = V5R ≥ VEE. (3) (2) NOTES: 1. CLK2. CL. Applies to V0L(R).0 VDD-19.

4 1.5 Unit V V V V V V µA µA µA µA µA KΩ Note (1) (2) (1) (2) (3) (3) (4) (5) (6) (7) (7) (8) NOTES: 1.3VDD 0.DB7 at high impedance 6.4 -1. CLK2 2.0 100 500 7. E. frame frequency = 70HZ.VDD During display During access Access cycle = 1MHz VDD-VEE = 15V ILOAD = ± 0. CL. CS3.0 5. CS2B.DB7 3. DB0 .7VDD 2. V5L(R) 7. V S S = 0V. output: no load 8.DB7 5. V D D -V E E = 8 to 17V.5V V0L(R) > V2L(R) = VDD . DB0 .6mA VIN = VSS .0 Typ Max VDD VDD 0. CLK1. DB0 .0 2.DB7 4. CS1B. V3L(R).8 0.2/7 (VDD-VEE) > V3L(R) = VEE + 2/7 (VDD-VEE) > V5L(R) 12 . RS.0 -5.VEE = 15.1mA Min 0.0 0 0 2.0 -2. VDD .S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD ELECTRICAL CHARACTE RISTICS DC CHARACTERISTICS ( D D = +5V ± 10%. V2L(R). FCLK = 250kHz.VDD VIN = VEE . Except DB0 . FRM. V0L(R). Ta =-30 to +85°C) V Characteristic Input high voltage Symbol VIH1 VIH2 Input low voltage VIL1 VIL2 Output high voltage Output low voltage Input leakage current Three-state(off) input current Driver input leakage current Operating current VOH VOL ILKG ITSL IDIL IDD1 IDD2 On resistance RON Condition IOH = -200µA IOL = 1. R/W. 1/64 duty. M RSTB.VDD VIN = VSS .

External Clock Waveform 13 .7VDD 0.64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 AC CHARACTERISTICS (V D D = +5V ± 10%. CLK2 cycle time CLK1 "low" level width CLK2 "low" level width CLK1 "high" level width CLK2 "high" level width CLK1-CLK2 phase difference CLK2-CLK1 phase difference CLK1.3VDD tWL1 CLK2 tD21 tF tWL2 tWH2 tR tCY Figure 1.3VDD tR tD12 0.7VDD 0. Ta =-30 to +85°C) Clock Timing Characteristic CLK1. CLK2 fall time Symbol tCY tWL1 tWL2 tWH1 tWH2 tD12 tD21 tR tF Min 2. V S S = 0V. CLK2 rise time CLK1.5 625 625 1875 1875 625 625 Typ Max 20 150 150 Unit µs ns tCY tWH1 tF CLK1 0.

S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD Display Control Timing Characteristic FRM delay time M delay time CL "low" level width CL "high" level width Symbol tDF tDM tWL tWH Min -2 -2 35 35 Typ Max +2 +2 Unit us us us us tWL 0.3VDD tDF tDM 0.7VDD 0.7VDD 0.7VDD 0.3VDD Figure 2. Display Control Waveform 14 .3VDD tWH tDF 0.

8V tWL tWH tR tASU tF tAH tAH 2. MPU Write Timing 15 . CS2B.0V R/W tASU CS1B. CS3.0V 0.8V tDSU tDHW DB0 . RS 0.64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 MPU Interface Characteristic E cycle E high level width E low level width E rise time E fall time Address set-up time Address hold time Data set-up time Data delay time Data hold time (write) Data hold time (read) Symbol tC tWH tWL tR tF tASU tAH tDSU tD tDHW tDHR Min 1000 450 450 140 10 200 10 20 Typ Max 25 25 320 Unit ns ns ns ns ns ns ns ns ns ns ns tC E 2.7 Figure 3.

7 tDHR tWH tF tAH tAH Figure 4. MPU Read Timing 16 . RS tD DB0 . CS2B.S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD tC E tWL tR R/W tASU tASU CS1B. CS3.

R/W and RS select the input register. Therefore internal state is not change. The data from MPU is written into input register. But RSTB and ADC can operate regardless CS1B-CS3. When CS1B to CS3 is in active mode and R/W = H. INPUT REGISTER Input register is provided to interface with MPU which is different operating frequency. MPU can read data which is latched. Data latched for falling of the E signal and write automatically into the display data RAM by internal operation. But status read is not needed dummy read. Unless the CS1B to CS3 is in active mode. OUTPUT REGISTER Output register stores the data temporarily from display data RAM when CS1B. it needs dummy read. In first access.64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 OPERATING PRINCIPLES AND METHODS I/O BUFFER Input buffer controls the status between the enable and disable of chip. Input or output of data and instruction does not execute. twice access of read instruction is needed. RS L H R/W L H L H Instruction Status read (busy check) Data write (from input register to display data RAM) Data read (from display data RAM to output register) Function 17 . to read the data in display data RAM. That is. Then Writing it into display RAM. stored data in display data RAM is latched in output register. CS2B and CS3 are in active mode and R/W and RS = H. To read the contents of display data RAM. In second access. data in display data RAM is latched into output register. Input register stores the data temporarily before writing it into display RAM. When CS1B to CS3 are in the active mode. status data (busy check) can read out. RS = L.

When RSTB becomes low.5V tRS tR 0. Table 2.S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD RESET The system can be initialized by setting RSTB terminal at low level when turning power on. execute other instructions after making sure that DB4 = 0 (clear RSTB) and DB7 = 0 (ready) by status read instruction. • • Display off Display start line register become set by 0.3VDD RSTB 18 .7VDD 0. receiving instruction from MPU. Therefore. Power Supply Initial Conditions Item Reset time Rise time Symbol tRS tR Min 1. The Conditions of power supply at initial power up are shown in table 1.0 Typ Max 200 Unit us ns VDD 4. following procedure is occurred. No instruction except status read can be accepted. (Z-address 0) While RSTB is low.

S6B0108 can accept the data or instruction. S6B0108 is in internal operating. CLK2 frequency Busy Flag 19 .64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 Busy Flag Busy Flag indicates that S6B0108 is operating or no operating. When busy flag is high. RS R/W E Address Output register DB0-DB7 Busy check Write address N Busy check N N+1 N+2 Data at address N Read data Busy (dummy) check Data at address N+1 Data read address N + 1 Read data Busy at address check N Busy Check E Busy Flag T Busy 1/fCLK < T Busy < 3/fCLK fCLK is CLK1. DB7 indicates busy flag of the S6B0108. When busy flag is low.

Display data RAM address and segment output can be controlled by ADC signal. • • ADC = H → Y-address 0:S1 . Latched data is transferred to the Z address counter while FRM is high.Y address 63:S64 ADC = L → Y-address 0:S64 . When flip-flop is reset (logical low). Bit data (DB<0:5>) of the display start line set instruction is latched in display start line register. presetting the Z address counter. Count function is not available. To indicate on state dot matrix of liquid crystal display. write data 1. It is used for scrolling of the liquid crystal display screen. The display on/off flipflop can changes status by instruction. X Page Register X page register designates pages of the internal display data RAM. off state.S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD Display ON / OFF Flip. Y Address Counter Y address counter designates address of the internal display data RAM. Display Start Line Register The display start line register indicates of display data RAM to display top line of liquid crystal display.Flop The display on/off flip-flop makes on/off the liquid crystal display.Y address 63:S1 ADC terminal connect the VDD or VSS. The display on/off flip-flop synchronized by CL signal. non selective voltage appears on segment output terminals regardless of display RAM data. The other way. Display Data RAM Display data RAM stores a display data for liquid crystal display. An address is set by instruction. The status of the flip-flop is output to DB5 by status read instruction. When flip-flop is set (logic high). The display data at all segment disappear while RSTB is low. writes 0. An address is set by instruction and is increased by 1 automatically by read or write operations of display data. selective voltage or non selective voltage appears on segment output terminals. 20 .

Indicates the display data RAM displayed at the top of the screen.64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 DISPLAY CONTROL IN STRUCTION The display control instructions control the internal state of the S6B0108. The following table shows various instructions. Sets the X address at the X address register. Internal status and display RAM data is not affected.63) L H Busy L On / Off Reset L L L Write display data H L Write data Read display data H H Read data 21 . Instruction RS Display on/off L R / W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 L L L H H H H H L/H Function Controls the display on or off.7) Display start line (0 . Reads data (DB0:7) from display data RAM to the data bus. After writing instruction. Set address (Y address) Set page (X address) Display start line (Z address) Status read L L L H Y address (0 . L: OFF.63) L L L L H H L H H H H Page (0 . Instruction is received from MPU to S6B0108 for the display control. L Read status. H: ON Sets the Y address in the Y address counter. Y address is increased by 1 automatically. BUSY L: Ready H: In operation ON/OFF L: Display ON H: Display OFF RESET L: Normal H: Reset Writes data (DB0:7) into display data RAM.

An address is set by instruction and increased by 1 automatically by read or write operations of display data.1/64). you can make it appear by changing D = 0 into D = 1. SET ADDRESS (Y ADDRE SS) S 0 R/W 0 DB7 0 DB6 1 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0 Y address (AC0 .S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD DISPLAY ON/OFF RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 1 DB1 1 DB0 D The display data appears when D is 1 and disappears when D is 0. Though the data is not on the screen with D = 0.AC2) of the display data RAM is set in the X address register. When the display duty cycle is 1/64 or others(1/32 . the data of total line number of LCD screen. SET PAGE (X ADDRESS) RS 0 R/W 0 DB7 1 DB6 0 DB5 1 DB4 1 DB3 1 DB2 AC2 DB1 AC1 DB0 AC0 X address(AC0 . is displayed. from the line specified by display start line instruction. 22 . it remains in the display data RAM. Writing or reading to or from MPU is executed in this specified page until the next page is set.AC5) of the display data RAM is set in the Y address counter.AC5) of the display data RAM is set in the display start line register and displayed at the top of the screen. DISPLAY START LINE ( ADDRESS) Z RS 0 R/W 0 DB7 1 DB6 1 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0 Z address (AC0 . Therefore.

WRITE DISPLAY DATA RS 1 R/W 0 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0 Writes data (D0 . the display is OFF. In this condition. no instructions except status read can be accepted. ON/OFF When ON/OFF is 1.D7) into the display data RAM. the display is ON. Y address is increased by 1 automatically. the Chip is ready to accept any instructions. 23 . • • RESET When RESET is 1.64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 STATUS READ RS 0 • R/W 1 DB7 BUSY DB6 0 DB5 ON/OFF DB4 RESET DB3 0 DB2 0 DB1 0 DB0 0 BUSY When BUSY is 1. Y address is increased by 1 automatically. After reading instruction. After writing instruction. When RESET is 0.D7) from the display data RAM. the Chip is executing internal operation and no instructions are accepted. the system is being initialized. When ON/OFF is 0. initializing has finished and the system is in the usual operation condition. When BUSY is 0. READ DISPLAY DATA RS 1 R/W 1 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0 Reads data (D0 .

V4L VEE S6B0107 DIO1 DIO2 M FRM CLK1 CLK2 CL2 Open Open M FRM CLK1 CLK2 CL2 S6B0108 V0R . V5L V1R . V5L V2R . V0L V5R . VEE2 VSS VDD VDD SHL FS MS PCLK2 SD2 DS1 VSS S1 S64 C1 C64 SEG1 COM1 LCD COM64 SEG64 VDD V0 R1 V1 R1 V2 R2 V3 R1 V4 R1 V5 VEE 24 . V3L VEE1 . V1L V4R . V2L V3R .S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD APPLICATION CIRCUIT 1/64 DUTY COMMON DRIVER (S6B0107) INTERFACE CIRCUIT R1 R2 From MPU - - DB7 RSTB VDD ADC CS1B CS2B CS3 R/W RS E DB0 CR R C VDD V0 V5 V2 V3 VEE VSS V0 V5 V1 V4 VEE V0R . V0L V5R .

64CH SEGMENT DRIVER FOR DOT MATRIX LCD S6B0108 TIMING DIAGRAM (1/64 DUTY) CLK1 1 CLK2 64 Input CL FRM 1 Frame M V0 V1 C1 V4 V4 V5 V1 Common C2 V4 V0 V1 C64 V4 V5 V0 S1 V3 Segment S64 V3 V5 V0 V2 V3 V2 V3 V5 V2 V2 V4 V5 V0 V1 V1 V4 V4 V0 V5 V1 1 Frame 1 2 3 64 1 2 3 64 1 2 3 48 49 25 .

..S6B0108 64CH SEGMENT DRIVER FOR DOT MATRIX LCD LCD PANEL INTERFACEAPPLICATION CIRCUIT S6B0108 No. 2 S1 ... 9 S6B0108 . C1 C2 C3 COM65 COM66 COM67 (128 × 512dots) LCD Panel C64 S6B0107 (slave) COM128 ..... . S64 No.. S64 No.... S64 ....... 10 S6B0108 .. .... S6B0108 No. S64 S6B0108 No...... S1 ............. S1 . 8 S1 .. S6B0107 (master) C1 C2 C3 Cf Rf CR R C64 COM64 COM1 COM2 COM3 . S64 ...... 16 S6B0108 26 ... S64 No....... 1 S1 ... S1 ..