Diode-clamped Multilevel Voltage Source Converter for Medium Voltage Dynamic Voltage Restorer

P. Boonchiam and N. Mithulananthan

Abstract— This paper proposes multilevel voltage source converter based medium voltage dynamic voltage restorer. Three multilevel voltage source converters, namely diode-clamped, flying capacitor and cascaded H-bridge are compared. These topologies are well suited for high-power, high-voltage level and low harmonic. This paper also discusses the development of power semiconductors, modulation scheme and methodology to control the dynamic voltage restorer. These multilevel converters can feed power into distribution system with only one dc-link energy storage. The design of passive components of LC output filter, modulation strategies and control of dynamic voltage restorer are also presented. Simulation results show performance of dynamic voltage restorer and verify the validity of the proposed topology of diode-clamped multilevel voltage source converter for medium voltage dynamic voltage restorer. Keywords— dynamic voltage restorer, multilevel voltage source converter, voltage sags

conventional topologies [4]. However, the use of VSC in utility application has been limited because of the limited power rating of self-commutated switches when used in two-level voltage source inverter. The multilevel VSC is proposed in recent years as they can avoid the power barrier by using a modular approach in which switching devices are stacked together, in almost an unlimited fashion. The number of inverter “voltage level” is proportional to the number of dc bus capacitor tap points [1]. As more voltage levels are added to the inverter, the harmonic performance improves without increased switching losses. Hence, in this paper a multilevel VSC, namely diode clamped voltage source converter, based dynamic voltage restorer (DVR), is proposed for high voltage distribution system applications. Rest of the paper is organized as follows. A brief history on the development of power semiconductor devices that are used in custom power devices, especially in DVR, is presented in Section II. Section III compares three types of multilevel VSC topologies that can be used for DVR applications. Multi-carrier pulse width modulation scheme that is suitable for the proposed DVR topology is presented Section IV. Section V carries a brief description of design of output LC filter under practical condition. Some interesting simulation results of the proposed DVR are presented along with a discussion in Section VI. Finally, the major contributions and conclusions of the work are summarized in Section VII.

Application of multilevel voltage source converter (VSC) is becoming popular in power and energy systems as results of its high power density, excellent performance and high reliability. Some of the conventional and emerging applications of VSC include flexible AC transmission system (FACTS), custom power devices and distributed energy system (e.g. Photovoltaic, Wind, Micro turbine) in transmission and distribution systems, respectively [1]. The application of VSC in custom power devices and distributed energy system are the recent developments that going to change the entire distribution system in many ways. Custom power devices are introduced in the distribution system to deal with various power quality problems faced by industrial and commercial customers due to increase in sensitive loads such as computer and adjustable speed drives and use of programmable logic control in the industrial process. These power quality problems could range from simple flicker to long duration power interruptions. When the problems occur the associated costs, including downtime, defects, and loss of production, can be substantial [2]. Among various power quality problems, voltage sags are more serious as they can cause customer equipment to malfunction or a production shutdown. Voltage sags may be caused by remote faults, or change in loading conditions, such as motor starting and energizing capacitor or transformer [3]. The voltage sags could last as little as a few cycles, still can affect several sensitive loads such as adjustable speed drives and programmable logic controllers. As the durations of voltage sag are so short, conventional voltage control methods such as tap changing transformers or capacitors with controls are not effective. Fast, more flexible voltage control methods are needed and power electronic system based power semiconductor devices can be used. An effective way of controlling the sags is to inject power into the system using custom power devices. Ideally, the systematic power needed for voltage control could be synthesized using a voltage-sourced inverter with small reactive component. An inverter-based compensator could have higher performance, small size, lower cost, and lower harmonic than the

The rating of power semiconductor device is important for power system applications due to the need of high voltage and high power level. At present, the voltage levels of distribution system range from 11 to 69 kV, but the highest nominal voltage of the semiconductor devices is only about 9 kV with a maximum nominal current of 8 kA [5]. Hence, there is a need for selection of appropriate power converter topology for the medium and high voltage applications. Figure 1 shows development of power semiconductor from 1980’s to present by representing their highest operating voltage and current. Power semiconductor devices based on switching operation can be classified as Insulated Gate Bipolar Transistor (IGBT), Gate Turn-off Thyristor (GTO), Insulated Gate Commutated Turn-off (IGCT), MOS Turn-off (MTO) and MOS Controlled Thyristor (MCT). In custom power applications, only three types of semiconductor can be used, namely IGBT, GTO, and GCT. GTO is the most popular device used in custom power devices, whereas IGCT is emerging due to its a lower losses capability comparing to others. IGBT can not be used in custom power since it has high losses than other devices [6].

Paisan Boonchiam is with the Energy field of study, Asian Institute of Technology, P.O. Box 4, Klong Luang, Pathumthani 12120, Thailand. email st101633@ait.ac.th Nadarajah Mithulananthan is with the Energy field of study, Asian Institute of Technology, P.O. Box 4, Klong Luang, Pathumthani 12120, Thailand. email mithulan@ait.ac.th

in practical applications.max VD .max maximum nominal voltage requirement of the devices. the nominal voltage of the clamping diodes is higher than the voltage of one level. In order to compare the different multilevel topologies. 3: One-leg five-level multilevel topologies. 2: Power semiconductors devices. As can be seem from Fig.3(b). The number of single capacitors NC is N C = ceil ( N index ) and number of main switching devices is NSW = 2×ceil ( N index ) (3) (4) 3. the . there has been steady growth multilevel converter topology as they can suit for the high voltage and high power applications. Many literatures [6-12] have shown the relative on-state losses of different semiconductors. B. This fact introduces practical problems such as parasitic inductances or package difficulties [14]. the switches can install in all applications of custom power depended on the rating of power and the zone of power distribution system. in practice. Thus. For a Nlevel-level inverter. Multilevel VSC are the attractive technology for the medium voltage application. These are diodeclamped multilevel voltage source converter (DC-VSC). 3. A. in DC-VSC. flying capacitor multilevel voltage source converter (FC-VSC) and cascaded H-bridge multilevel voltage source converter (CHVSC) [8-10]. a Nlevellevel inverter leg needs the following number of clamping diodes. These multilevel topologies can generate multilevel output voltages with low harmonics.max In contrast to main devices. Two capacitors with two switching devices are in single commutation cell. Capacitors voltages are chosen in such a way that the difference between two capacitors corresponds to the nominal voltage of the devices VN(t).Figure 2 shows pictures of power semiconductors used in the custom power devices. DIODE-CLAMPED VSC (DC-VSC) Figure 3(a) depicts one leg circuit diagram of a five-level DC-VSC. This topology also allows multilevel output voltages. Therefore. some papers propose that. If rated voltage of a clamping diode equals rate voltage of the main switching devices. capacitors are connected in series. 1: Development of power semiconductor device. (c) (b) (a) Fig. different topologies use different solutions to expend the output voltage range up to several levels. FLYING-CAPACITOR VSC (FC-VSC) The circuit configuration of five level FC-VSC is shown in Fig. In medium voltage applications. it becomes necessary to place several diodes in series to achieve the required voltage. It becomes obvious that IGCT and GTO are a much better choice for custom power devices because they have much lower on-state losses.Clamp = ( N level -1)( N level -2 ) (5) However. the number of cell (Ncell) in one leg is: N cell =N level -1 (1) Where Vdc. The clamping (6) The cell voltage could be VN(t) or 0.MTO 150 mm 125 mm GTO IGBT MCT GTO 100 mm MCT Module IGBT Module Vdc 4 1980 1985 1990 1995 2000 2005 Year Fig. IGBT is easy to implement the driver circuits for switching devices by using the voltage source but they still have a problem with onstate losses and rating of power devices. N D. more diodes are needed due to the voltage derating of the series connection of up to (Nlevel-2) diodes. The most well-known multilevel topologies developed so far are shown in Fig. This topology uses clamping diodes to limit dynamic and static overvoltage for switching devices. Instead of diode clamping. Consequently. The DC-VSC generates different voltage levels for output voltage in the ranging between positive and negative of Vdc/2. the number of levels should be limited to seven or nine levels maximum. However. a quantity called Nindex is defined as given in (1). diodes are connected to taps of dc bus capacitor. which includes power quality and power conditioning applications in the distribution system. MULTILEVEL VSC TOPOLOGIES During the last 10 years. The symbol ceil(x) represents the ceiling number of x. voltage sharing is realized by floating additional capacitors.max is the maximum dc bus voltage and VD. depending on the switching state of the two switching devices in a cell. The number of levels Nlevel is N level = ceil (N index )+1 (2) (a) IGCT (b) GTO (c) IGBT Fig. dc bus voltage is so high therefore Vfw / V 9000 8000 7000 6000 5000 4000 3000 2000 1000 500 53 mm 77 mm 10 kV MTO Ifw / A 8000 7000 6000 5000 4000 3000 2000 1000 500 Vdc 4 Vdc 4 3Vdc 4 Vdc 4 Vdc 2 N Vdc 2 Vdc 4 Vdc 4 Vdc 2 Vdc 4 & IGCT GCT. 3. N index = Vdc .

I0max is the ˆ maximum output current and fsw is the switching frequency.max (9) Therefore.max ⎠ DC-VSC n5level level A 6(n-1) 24 B 6(n-2) 18 C n-1 4 Vdc/ Vdc/4 D (n-1) E 2n-1 9 F n3 125 FC-VSC n5level level 6(n-1) 24 0 0 3n-5 10 Vdc/ Vdc/4 (n-1) 2n-1 9 23(n-1) 4096 CH-VSC n5level level 6(n-1) 24 0 0 3n/2-1. This redundancy could be used to limit the charging or discharging of a capacitor during one voltage level. but the CH-VSC does not. ma = and Am A c ( N-1) (12) N cell (N cell +1)(2N cell +1) (12) 6 For example.. . For electrical vehicles.output voltage of the inverter (VO(t)) is the sum of all cell voltages Vk(t). C: capacitors. the amplitude modulation index (ma) and the frequency ratio (mf) are defined by (12) and (13). As a consequence. However. that floating capacitor topology is not practical for this application. the five-level FC-VSC needs 30 capacitors.5 6 Vdc/ Vdc/4 (n-1) 2n-1 9 23(n-1) 4096 And the capacitance of the clamping capacitors can be determined for a specific maximum voltage deviation by substituting equations (10) and (8): Cmin = (1 − ηx ) ⋅ I 0 max ηx ⋅ VDC . but on the power characteristics of the converter. D: maximum voltage applies. as follows: voltage stress and neutral pole balance voltage. ˆ Vmax = I 0 max Ck N cell f SW (8) However. A: Switches. B: diodes. In order to balance the power provided by the dc voltage sources. Table 1-Characteristic of multilevel VSC. VO ( t ) = ∑ Vk ( t ) k =1 N cell (7) It is obvious. The most popular and simple switching scheme for multilevel voltage source converter is Multi-carrier-PWM (MCPWM). Each unit is fed by a separate dc capacitor. which can be provided either by a transformer with multiple isolated secondary or by several transformers. MODULATION METHOD When it comes to multilevel voltage source converters. For an N-level converter. The simplicity and modularity of this structure brings many practical effects. It can be shown. N-1 carrier signals with the same frequency fc and peak-to-peak amplitude Ac are placed in such a way. Nevertheless. waveform has a peak-to-peak amplitude Am and frequency fm. CASCADED H-BRIDGE VSC (CH-VSC) The last circuit configuration shown in Fig. In multilevel converters. the fact that the dc link voltage must be isolated is the major drawback for the application of these structures. Therefore. its low number of reactive components is usually preferred from the economical point of view. batteries or fuel cells can also be used. early developments in this area demonstrated the relatively straightforward nature of multilevel PWM. C.525 mF and have to operate at 1 kHz switching frequency. since this topology requires multiple isolated dc power supplies. The example shows.max ⎞ ⎛V ⎞ ⎛N ⎞ N cell = ceil ⎜ DC . Several independent dc power supplies are required. increases dramatically: 2 N C =1+2 2 +. the number of cells can be calculated: ⎛ VDC . the DC-VSC is selected for dynamic voltage restorer applications. In medium-voltage converters. In a medium voltage application with 20 kV dc bus voltage. The voltage reference is continuously compared with each of the carrier signals. that the maximum overvoltage is given by (8). loaded with the dc voltage (Vdc). where Ck is the capacitance of clamping capacitors. 3(c) is a five level CH-VSC. The circuit topology is a cascaded structure consisting of full bridge inverter units connected in series.+N cell = Where. The FC-VSC also shares this advantage.max ⋅ f SW (11) Note that size of the capacitors depends not on the number of cells. and it is centered in the middle of the carrier set.. or modulation. The flying capacitor topology is better for higher voltage and lower currents applications. 4. The voltage reference. 16% voltage deviation and 2000A output current the capacitors have to 0. E: line-to-line output voltage levels and F: states of the inverter (total vectors of output voltages). the number of capacitor (NC) needed for the clamping capacitors. that there are more than one possibility to generate one specific output level. As can be seen from the table DC-VSC topology uses a low number of capacitors compared to other two topologies.max ⎟ = ceil ⎜ ⎟ = ceil ⎜ index ⎟ (10) ⎜V VD ⎠ (1 − ηx ) ⎟ (1-ηx ) ⎠ ⎝ ⎝ ⎝ D . It can be connected to a single dc link voltage. that they occupy continuous bands between the positive and negative dc rail of the inverter. Although this topology requires some additional clamping diodes. maximum device operating voltage of 4 kV. This means that capacitors with higher voltage rating have to be unit by series connection of multiple single capacitors. the maximum voltage of a capacitor typically has the same voltage rating as semiconductor devices. some practical experience with this topology reveals technical difficulties that complicate its application. in this paper. No additional circuits to balance the voltage matching of the switching devices are necessary. Table 1 summarizes the general characteristics of the three multilevel VSC topologies. Another benefit of this circulating method is that it achieves the same switching frequencies for all of the devices. respectively. the first notion is that need for a large number of switches that may lead to complex pulse-width modulation (PWM) switching scheme. Vmax is often defined as a percentage (ηx) of the maximum nominal voltage of the switching devices: ˆ Vmax = ηx ⋅ VD . each cell can be used in a cyclic way throughout each semi-cycle of a line period.

the influence of frequency ratio and the number of converter level for the generated harmonics were considered. the modulation strategy must be considered by using single-phase condition to inject the voltage via the three single phase injection transformers. mf should be odd to achieve a high symmetry of the output voltage. f o < f r < f sw (16) VLf(t) iL(t) Lf i (t) C Vinv(t) iinj(t) Rf Cf VC(t) iload(t) Vinj(t) 2Ac Reference Ac Carrier 2 0 Carrier 3 Ac Carrier 4 2Ac 0 5 10 Time (ms) 15 20 or L f ≤ 0. 5. • If mf is even. It comprises four-carrier triangle waveform and the reference sinusoidal waveform which can generate the pulse width modulation for driving the five-level voltage source converter. The lower order filter is desirable from the power of view of the total number of components. 5: Single-phase equivalent circuit of DVR’s multilevel inverter.5 is chosen since the series capacitor and resistor combination reduces the power losses across the damping resistor. The output filter is designed by considering the rating of . DESIGN OF OUTPUT LC FILTER There are several polynomial low-pass filter configurations with different shapes of amplitude-versusfrequency responses. • If there is an odd number of levels. fr = 1 2π L f C f . since the filter capacitor Cf will represent a short circuit at high frequencies. Fourth step: considers the filter resistor Rf that is designed for the filter component values to result in an overdamped circuit.9 and mf = 40. where the carriers above the zero reference are in phase. 4. in general are the components at fsw. The output voltage can be calculated by considering the dominant voltage of the inverter PWM voltage which. Third step: calculate filter’s capacitance Cf with the given filter’s resonance frequency (fr) and the switching frequency of the inverter (fsw). H ( jω ) = Related to the way the carrier waves are placed in relation to the reference signal. the POD-method generates the lowest THD value. filter size. Second step: selects the inductance Lf by taking into account the voltage drop VLf: VLf = 2π f o L f I rated < 5% of rated voltage (17) (18) Fig. In addition. and weight. If the output voltage Vinj exceeds the specification. where all the carriers are in phase. For the multilevel voltage source converter. the POD method is the best method as shown in Fig. for a five-level converter. • Phase Opposition Disposition (POD). but shifted by 180° from those carriers below the zero reference. the filter’s capacitor (Cf) can be derived from condition given in (16). the PD-method generates the lowest Total Harmonic Distortion (THD) value. • In-Phase Disposition (PD). = Vinject ( jω ) Vinv ( jω ) 1 + jω R f C f (14) 1 − ω 2 L f C f + jω R f C f Where the effective attenuation in decibels is G = 20log 1 H ( jω ) (15) To design the output LC filter. the transfer function H(jω) which defines the behavior of the It can be seen from (14) that the output voltage mainly depends on the impedance of the designed filter. mf should be even to achieve a high symmetry of the output voltage. 5. the following design procedure is used.4: Multilevel phase opposition disposition PWM technique for ma = 0. • If mf is odd. Rf is set equal to the characteristic impedance of the cable to absorb the reflected energy. three cases can be distinguished: • Alternative Phase Opposition Disposition (APOD).05 ⋅ Vrated = L f max 2π f o I rated To Load Carrier 1 Fig. Including the reason of unbalance waveform. From Fig. The design procedure contains four steps as follows: First step: chooses the resonance frequency of the filter that the resonance of the filter will be allocated between the fundamental frequency (fo=50 Hz) and the switching frequency (fsw ≤ 400 Hz) of the multilevel inverter. cost.mf = fc fm (13) circuit can be written as equation (14). mf should be a multiple of three • If there is an even number of levels. Thus. and the side-band frequency (2fsw). the filter’s inductance (Lf) or fsw should be increased. The equivalent circuit as shown in Fig. where each carrier band is shifted by 180° from the adjacent bands. The above three modulation methods are compared and given the main result as follows: • If there is three-phase systems.

supply voltage Vs(t).1 mF Rf = 0.c V load. Figure 7 shows the performance of multilevel voltage source inverter that composes the output voltage of multilevel inverter.b Vinj. Vload(t).9 DC-Link voltage VDC = 18 kV Carrier frequency fc = 1200 Hz Filter parameters Lf = 6 mH Cf = 0. the filter resistor is considered to be 100 mΩ.a Vinv. As the ratings of various power electronic switches are limited.5 p.9PF.b Vload. notice that the DVR is able to inject appropriate voltage component to correct the voltage anomalies within fraction of a cycle. 8. fsw : 400 Hz – 1200 kHz. sw frequency fsw = 400Hz Load parameters VLoad = 22 kV Sload = 10 MVA Power Factor = 0. As a result of the appropriate injection by the DVR. This is for 50 Hz distribution systems in most of the Asian countries. Table 2-Parameters of simulated system. the output current of inverter iinv(t).. 50 Hz).a Vinj. secondly. the load voltage can be kept at the nominal value as indicated in the third wave form in Fig. Vs(t) is augmented by a injection voltage. The series voltage provides boost compensation during sags to deliver rated voltage to the load. 260 A. 7.b -10 Lf iL. Lfmax is limited to 6.a Vload. • Termination of the trigger pulses when the system event has passed.1 mF. 6 in which the distribution supply. Fig.7 mH (11 kV.u. The output voltage of inverter has fivelevel of voltages between +9 kV to -9 kV dc link voltage. 22 kV and assuming the DVR can inject the voltage 0. Vinv(t). consider threephase voltage sag of 20% depth.a Cf Cf PT Sensitive Load iload. Voltage (kV).c 10MVA 0. • Generation the voltage with sinusoidal PWM based on multilevel VSC. • Correction the load voltage via the series voltage injection. the load voltage Vload(t) and the load current iload(t) by using the parameters in Table 2. Firstly. Current (A/10) 10 Vinv Vload iload 0 iinv 6. multilevel voltage source converter topologies are useful for high voltage and high power To illustrate a typical response of DVR. Therefore. from the rating of load and inverter and the condition (18). 8 shows the voltage injection by the DVR. that means DVR can inject the voltage at 11 kV maximum. the injected voltage Vinj(t) and the load voltage VL(t) of the system with the proposed DVR are shown in Fig. namely.6 has been implemented with MATLAB/Simulink and tested with the parameters in table 2. from its nominal value. the designed inductance Lf is 6 mH and capacitance is 0. Supply PT Vinj.c Vdc 4 DC Source Stationary reference frame Vdc 4 Fig. a voltagesag is created at 150 ms by simulating a remote three phase fault.a Lf iL. The voltage sag is a balanced one with a reduction of voltage magnitude of 0.u. The load voltage and current are near the sinusoidal waveform due to the design of good LC filter and use of the multilevel inverter. 7: Output waveform of 5-level voltage source inverter of DVR. CONCLUSION This paper presents a multilevel voltage source converter based Dynamic Voltage Restorer. 50 Hz VS Lf iL. Nominal frequency f = 50 Hz Max. the resonance frequency of filter fr is chosen to be 200 Hz. the system shown in Fig. in order to see the effectiveness of the proposed DVR. The functional procedure of a controller in a DVR is the following: • Detection of voltage sags in the distribution system. pf 0.b Controller + PWM Vdc 4 Fig. fsw is set to 400 Hz. 6: Scheme of DVR for voltage sag and swell mitigation.9 lag. The feed forward control .1 mΩ Various voltage wave forms.c Vdc 4 5 10 15 20 Time (ms) 25 30 35 Vinv. DVR SIMULATION RESULTS The proposed DVR of DC multilevel VSC based DVR is shown in Fig.b iload. The second wave form in Fig. To validate the proposed DVR.c Cf iload. Vinv. • Computation of the compensating voltage using synchronous reference frame. 50 Hz. Also. 8: Compensation of DVR when three phase balance fault occurred.. Here. is selected for DVR control as it can be implemented easily compared to other control techniques. Finally. 8. Secondly.lag PT 22kV.load: 10 MVA. Vinj(t).2 p.

in Electrical Engineering from Rajamangala University of Technology Thanyaburi (RMUTT). Conf. REFERENCES [1] T. .” presented at Power System Technology.” presented at Spectrum. V. “Recent Power Electronic Developments for FACTs and Costumed Power. U. [3] Hingorani. Thailand. IEEEISIE. “Comparison of Hard-switched Multi-Level Inverter Topologies for a STATCOM by Loss-Implemented Simulation and Cost Estimation. [12] Reed. 2000. He has worked as an electrical engineer at the Generation Planning Branch of the Ceylon electricity Board. Conference Record . Thailand. De Doncker. 1995. 2004. Kashani and R. [4] Xu. “Power Electronics for Modern Medium-Voltage Distribution Systems. 2000. Nadarajah Mithulananthan (M’02) received his Ph. he worked as research associate at Institut fuer Stromrichtertechnik und Elektrische Antriebe (ISEA). Nov.” presented at 4th International Power Electronics and Motion Control Conference (IPEMC). available at http://www. and as a researcher at Chulalongkorn University. 2005. on Ind. F. [9] J.December 2003. Menzies. Mexico.M. Meyer and R. “Control Strategies for Multilevel Voltage Source Converters for a MediumVoltage DC Transmission Systems. namely. Peng and J. V.” presented at Southcon/94. E.. pp. 1992.. Woodford and R. three topologies. “CUSTOM POWER-EPRI's response to power quality issues. He has worked as lecturer at the Department of Electrical Engineering of RMUTT since June 1997. Recife Brasil. “Multilevel Converter. [8] F.abb. “Applications of voltage source inverter (VSI) based technology for FACTS and custom power installations.F. Germany. Schwarzer and R. O. and at el.G. De Doncker.381-386.” presented at CIGRE. 1995.” presented at International Symposium on Industrial Electronics.. from University of Waterloo in Electrical and Computer Engineering in 2002. A. respectively. and Chulalongkorn University.Z. De Doncker.com/ [15] Power Transmission and Distribution. Xi'an (China). Thailand.H. G. Diode-Clamped.” presented at Japan. Power Electronic System and Optimization Techniques. on Power Electronics Vol.A. available at http://www.15..Recent.Bernet and S. Dr.S. [5] R. De Doncker. Nagoya. IEEE Int. Rheinisch Westfaelische Technische Hochschule Aachen. 1994.com/ Paisan Boonchiam received his B. 2000.2000. Fujii.” presented at IEEE Power Electronics Specialist Conference PESC 05. [2] M.Eng. N. H. [11] K.” presented at IEEE-IAS Conf. “Optimization of Multilevel Voltage Source Converters for MediumVoltage DC Transmission Systems. He is currently a doctoral student at the Asian Institute of Technology. His main research interests are applications of FACTS and Custom Power Controllers.siemens.” presented at Harmonics and Quality of Power. Puebla. IEEE. Flying-Capacitor and Cascaded H Bridge that can be used for DVR application are compared. Among existing multilevel voltage source converters. and M.A new Breed of Power Converters. and Acha. Anaya-Lara. “Development of High Power Converters for Industry and Traction Application.M. [7] D.A.applications along with low harmonics. von Bloh. In November 2001... “Introducing custom power. Ryan.G.10. von Bloh and R. Agelidis.” IEEE Trans. R. The simulation results show the capabilities of proposed DVR along with the low pass filer in mitigating voltage sag in a 22 kV distribution system. “Development of prototype custom power devices for power quality enhancement.. Power Quality Monitoring. De Doncker.Eng. Lai. 22-28.D. Japan.. and H. 1994. [14] Low voltage controls and distribution. Diode-Clamped multilevel voltage source converted is selected for DVR application as the number of capacitors needed and switching states are less compared to other topologies. 2000. [10] J. presented at Security and Power Quality of Distribution Systems. L. Kitchin. Mehta. [13] Sundaram.. Mithulananthan is currently an Assistant Professor at the Asian Institute of Technology and his research interests are voltage stability and oscillation studies on practical power systems and applications of power electronics controllers in transmission and distribution systems.Reliability: “Custom power technology in distribution systems: an overview Osborne”. Control and Instrumentation (IECON). Bangkok. in April 1997 and April 2000. and Tahiliani. 2000 [6] C. “Controlling a Back to Back DC-Link to Operate as a Phase Shift Transformer. Electronics.