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2844 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO.

6, JUNE 2019

Optimal Tuning of Memristor Conductance


Variation in Spiking Neural Networks for
Online Unsupervised Learning
Bowei Chen, Hui Yang, Fuwei Zhuge, Yi Li , Ting-Chang Chang , Yu-Hui He ,
Weijian Yang, Nuo Xu , and Xiang-Shui Miao

Abstract — In unsupervised learning (UL)-oriented spik- Among various kinds of synaptic functions, the spike-timing-
ing neural network (SNN) designs, the initial conductance dependent plasticity (STDP) effect, which describes the
variation of the synapses is usually necessary, with which synapse strength modulation depending on the timing interval
temporally differentiated responses of the output neurons
can be achieved given the same input patterns, in order to between the pre- and postneuron spikes, has attracted increas-
implement the important lateral inhibition function. We take ing research interests recently [4]–[6]. The STDP is based
a lithium silicate memristor as an example and demon- on the causality of temporally correlated events and supports
strate through a motion-style recognition task that, without for asynchronous computing infrastructures with ultrahigh
regulating the initial conductance variation of memristor energy efficiency [7]. Demonstrating the STDP with mem-
synapses, several types of errors will occur: too large
conductance variance leads to the deactivation of some ristor devices may greatly extend the spiking neural network
output neurons and the incomplete learning of the motion (SNN) application scenarios to generic temporal tasks, such
routes, while too small variance causes duplicated learnings as dynamic pattern classification [8], [9], motion sensing [10],
of the same pattern. By tuning the memristor conductance and autonomous driving [11].
variance through the forming voltages, it is found that the UL A practical concern of designing memristor synapses is that
capacity can be optimized, indicating a promising approach
to enhance the UL performance of a memristor-based SNN. the initial conductance of devices is usually distributed in
a wide range. For unsupervised learning (UL) tasks in the
Index Terms — Lithium silicate (LiSiOx ) memristor, spike- SNN, this initial variation of synapse strengths will result
timing-dependent plasticity (STDP), spiking neural network
(SNN), unsupervised learning (UL). in differentiated responding time of output neurons given
the same input pattern. On one side, it may be beneficial
to the implementation of lateral inhibition (LI) since now
I. I NTRODUCTION the earliest firing neuron is able to prevent other slower
neurons from learning the same patterns. On the other side,
O WING to their capability of history-dependent conduc-
tance tuning, memristors have been intensely studied as
artificial synapses used in neuromorphic computing [1]–[3].
the destructive consequences of initial conductance variation
on UL performance especially on the temporal tasks have
not been studied. To optimize the learning performance, it is
Manuscript received December 27, 2018; revised March 7, 2019; important to systematically investigate the impact of the initial
accepted March 13, 2019. Date of publication April 23, 2019; date
of current version May 21, 2019. This work was supported by the conductance variation on the learning performance. In this
National Natural Science Foundation of China under Grant 61841404 paper, we take lithium silicate (LiSiOx )-based memristors as
and Grant 51732003. The review of this paper was arranged by Editor an example to investigate this issue. We first fabricated LiSiOx
B. Iñiguez. (Bowei Chen and Hui Yang contributed equally to this work.)
(Corresponding author: Nuo Xu.) memristor synapses and demonstrated their STDP function.
B. Chen, H. Yang, Y. Li, Y.-H. He, and X.-S. Miao are with Based on their performance, we designed and evaluated a
the Wuhan National Research Center for Optoelectronics, School of UL task of motion-style recognition system. We studied the
Optical and Electronic Information, Huazhong University of Science
and Technology, Wuhan 430074, China (e-mail: heyuhui@hust.edu.cn; impact of initial weight variation of LiSiOx synapses and
miaoxs@hust.edu.cn). developed the method of tuning synapse conductance variance
F. Zhuge is with the School of Materials Science and Technology, to optimize the learning accuracy and efficiency.
Huazhong University of Science and Technology, Wuhan 430074, China.
T.-C. Chang is with the Department of Physics, National Sun Yat-sen
University, Kaohsiung 804, Taiwan. II. SNN D ESIGNS AND E XPERIMENT
W. Yang is with the Department of Electrical and Computer Engineer- Fig. 1(a) shows the schematic of SNN designs for imple-
ing, University of California at Davis, Davis, CA 95616 USA.
N. Xu is with the Department of Electrical Engineering and Computer menting motion-style recognition task via the STDP leaning
Sciences, University of California at Berkeley, Berkeley, CA 94720 USA rule. A layer of dynamic vision sensors (DVSs) monitoring the
(e-mail: kainexu@gmail.com). light changes due to moving objects serves as the input to the
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. SNNs [12], [13]. Each sensor is connected to the postneuron
Digital Object Identifier 10.1109/TED.2019.2907541 layer via two synapses as shown in Fig. 1(b), among which one

0018-9383 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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CHEN et al.: OPTIMAL TUNING OF MEMRISTOR CONDUCTANCE VARIATION IN SNNs FOR ONLINE UL 2845

Fig. 2. Timing chart of the WTA learning algorithm. Owing to the initial
variation of synapse strengths, output neuron Ok will reach threshold
faster than others like Om given the same input pattern. The firing of
Ok triggers LI signals which discharge other neurons like Om and thus
prevent them from firing and learning the same patterns. A1–A4 are the
same DVS sensors as those shown in Fig. 1(a) and emit spikes as the
ON signals (red) and as the OFF signals (blue) from timing t1 –t4 during
the object passing by.

neurons learn the input patterns in a “winner-take-all” (WTA)


manner as illustrated in Fig. 2. Here, the initial distribution
of synaptic weights plays an important role in UL. With the
initial conductance variance of memristors, output neurons
respond to the same input patterns with different time lags.
The neuron that reaches the voltage threshold at the earliest
will fire a spike. Not only will this postsynaptic spike triggers
modulation of this neuron’s synapse strengths according to the
STDP but also will it be sent to other slower neurons in the
same layer via inhibitive lateral connections to prevent them
Fig. 1. (a) Schematic of SNN designed to implement motion-style
recognition task. Inputs are a layer of 128 × 128 DVSs, in which
from possible firing. A1–A4 are the DVS sensor addresses as
every sensor is connected to the output neuron with two synapses, for shown in Fig. 1(a). The synaptic strength of inhibitive lateral
transmitting ON (red) and OFF (blue) signals, respectively. (b) Design of connections should neither be too large nor be too small.
hardware neural network where a crossbar array of memristors serves
as synapses connecting input neurons (blue rounds) to output neurons
The weight of inhibitory synapses has been optimized in an
(pink rounds). The output neurons connect with each other through LI to appropriate range, as listed in Table I. During an event of
prevent duplicated learning of the same input patterns. object passing by, they emit spikes from timing t1 –t4 , where
the red spikes are the ON signals, while the blue ones are the
OFF signals. As a result, the input pattern is memorized by the
synapse is for transmitting the ON signals when the moving earliest firing neuron, and duplicated learning by other neurons
object passes by and screens the corresponding sensors (red can be avoided. Note that in the real circuits, the time spent
pixels), whereas the other synapse is for the OFF signals by the LI signals is nonnegligible. Since the design purpose of
when the object shifts away and the sensors recover (blue LI signals is to prevent other neurons from firing by reducing
pixels). The gradual color change of A1–A4 in Fig. 1(a) their membrane potentials, the discharging of target neuron
indicates that a series of spike events with different timings membranes would take time to execute. In addition, this time
are fired sequentially on the path where the object passes by. duration would scale up with neural network circuits due to the
After receiving a series of DVS spikes, postlayer neurons will increasing parasitic resistance and capacitance. In this paper,
fire so that the associated synapses are modified according this WTA-SNN simulation is performed using Brian2 [14] and
to STDP rules [7]–[10]. Here, leaky integrate-and-fire (LIF) the transmission time of LI τi is normalized with the time
neurons are employed with the characteristics that the neurons constant τm of LIF neurons as τi /τm = 1/3000.
are reset and kept inactive for a refractory period Trefrac Experimentally, the synapses are TiN(10 nm)/Li:SiOx
after successful firing. After sufficient learning, the memristor (10 nm)/Pt(200 nm) trilayer memristors as shown in
synapses of different output neurons are expected to track Fig. 3(a) and (b). The TiN bottom electrode (BE) is deposited
different traces of the moving object. In this way, the output on the Ti/SiO2 /Si substrate and patterned by the lithography
neurons will selectively fire for different traces of the object. process. Another patterning is used to form the vias on the
Without the supervision of target neuronal responses, output top of the 200-nm insulating SiOx . The 10-nm LiSiOx thin
2846 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO. 6, JUNE 2019

TABLE I
D ESCRIPTION AND VALUE OF THE N EURONAL PARAMETERS FOR
M OTION -S TYLE R ECOGNITION

Fig. 4. (a) and (b) I–V curves before/after forming voltage treatment,
respectively. Inset plot shows the conducting channels within LiSiOx
memristor. (c) and (d) Corresponding distribution of memristor conduc-
tance before/after forming voltage treatment, respectively.

Fig. 5. Experimentally measured LiSiOx conductance variance σg as a


Fig. 3. (a) Schematic and (b) transmission electron microscopic view of function of forming voltage V.
the LiSiOx memristor.

film is deposited by physical vapor deposition followed by


the top electrode (TE) forming process [15]. Input stimulus is
always applied on the TiN BE while the Pt TE is grounded.
The hysteresis current–voltage (I –V ) curves [Fig. 4(a) and
(b)] of the devices are measured in the dc voltage sweeping.
Fig. 4(c) and (d) shows the distribution of high resistance
before/after forming voltage treatment. Moreover, the depen-
dence of experimentally measured LiSiOx conductance vari- Fig. 6. (a) Waveforms of the pre-/postsynaptic spikes and their superpo-
ance σg on the applied forming voltage V is quantitatively sition with different time lags (Δt). (b) STDP demonstrated by the LiSiOx
shown in Fig. 5. Here, σg is defined as follows: memristor synapse. The initial conductance G0 is set from 1 to 100 μS
to cover the whole range of HRS distribution.
σg = S/M
potentiation (LTP) measurements of the STDP function, nearly
where S is the standard deviation, and M is the mean value the same values of low-resistance states (LRSs) will be
of initial LiSiOx conductance. Due to the fact that both the attained given various quantities of initial high-resistance
device-to-device (D2D) and cycle-to-cycle (C2C) variations of states (HRSs). Note that in our STDP curves, a long-term
memristor conductance result from the random formation and depression (LTD) is unnecessary compared with other designs
disrupture of conducting filaments within the functional layer where the LTD is used to prevent output neurons from
[16]–[18], it is reasonable to estimate the D2D conductance learning more than one pattern [8]. Instead, neurons with
variance through the measurement of C2C and vice versa. adaptive thresholds are employed to achieve this goal in
In this paper, the initial D2D variance was obtained from the SNN simulation [19], [20]. The neuronal parameters of this
C2C variance shown in Fig. 4(c) and (d). simulation are summarized in Table I. The waveforms of the
The STDP behaviors of the devices are measured in the pre-/postsynaptic spikes are designed as shown in Fig. 6(a) to
voltage pulse modes. It is found that during the long-term obtain STDP properties from LiSiOx memristors. Clearly, the
CHEN et al.: OPTIMAL TUNING OF MEMRISTOR CONDUCTANCE VARIATION IN SNNs FOR ONLINE UL 2847

LiSiOx synapses are excitatory synapses. It should be noticed


that the waveforms of the pre-/postsynaptic spikes are not the
same as the waveform of neuron spikes in Table I. The para-
meter matching between the more biological-like neuron and
the memristive synapses are solved by an additional electronic
circuit [21]. Forming voltages with various amplitudes are
applied onto LiSiOx devices to tune the conductance variation.
Fig. 7. Synaptic weight maps of every output neuron shown in Fig. 1
consisting of two submaps with the left one showing the synaptic weights
III. R ESULTS AND D ISCUSSION of ON events and the right one showing the synaptic weights of OFF
events.
Note that in the real integrated circuits, the large scale of
SNN will lead to a nontrivial transmission delay of the LI
signals. Fig. 2 shows that a successful SNN design requires
that the firing time difference between any two output neurons
in response to the same input patterns should be larger than the
delay of the LI transmission. Therefore, the pattern capacity
(Np ) of SNN is estimated as
N p ≈ (τmax − τmin )/τi
where Np denotes the number of input motion routes that can
be learned by the SNN, τmax / min is the longest/shortest delay
from output neurons responding to the same input patterns
and τi is the time (e.g., RC delays in SNN circuits) required
for transmitting LI signals. The degree of the temporally
differentiated neuronal responses (τma − τmin ) is determined
by the magnitude of initial conductance variance σg . In the
following, LiSiOx memristors are used to investigate the
relation between σg and Np , for developing a feasible approach
to maximize Np .
Without any adjustment, the conductance of the LiSiOx
synapses ranges from 10−7 to 10−4 S as shown in Fig. 4(c).
By employing the voltage forming process, the conductance
variance is reduced by about two orders of magnitude as
shown in Fig. 4(d). The underlying physics is regarded as the
reshaping effect of conducting filaments under the forming
voltages as in the insets of Fig. 4(a) and (b) [22]–[24]. When
a small forming voltage is applied, the conducting filaments
inside the LiSiOx memristors are irregularly shaped, and
hence, σg of the HRS is large; on the other hand, by increasing Fig. 8. Synapses connected to 12 neurons in the output layer after UL.
the forming voltages, σg can be greatly suppressed. Several (a) Without optimizing the conductance variance of LiSiOx memristors,
1 neuron is inactive (i.e., has not learned anything, marked by the
methods, such as SET and RESET, have been reported to blue frame) and 3 neurons learned incomplete motion routes (marked
regulate the conductance variation [25], [26], and in this paper, by red frames). (b) With over-reduced variance, 3 pairs of neurons
forming voltage treatment is employed. Here, the consideration have duplicated learnings (marked by the red arrows). (c) After the
optimization, every neuron has learned a unique motion route.
is that due to D2D variation, an invariant SET or RESET
voltage can hardly achieve the required memristor conductance
distribution, while the same forming (or reforming) voltages is the incomplete learning, i.e., only a portion rather than the
applied to each memristor devices can. whole route of the motion is learned as marked by the red
The impact of different magnitudes of synapse σg on the UL rectangles in Fig. 8(a). By analyzing the synapse conductance
capacity is demonstrated for a motion-style learning task. The of the output neuron, it is concluded that too large synapse
synaptic weight maps of output neurons are plotted in Fig. 7. conductance will lead to the immature firing of the associated
The synaptic weight maps of every output neuron consist of neuron and thus leave the rest of the motion route unrecorded.
two submaps, in which the black one shows the conductance This kind of error occurs uniquely in the UL of dynamic
of synapses for transmitting the “ON” signals, while the white patterns due to the latency coding of input messages. The
ones for the “OFF” signals. Fig. 8(a)–(c) shows the simulated other type of error is the neuron deactivation as marked by
synapse response maps of the 12 output neurons after UL, with the blue rectangle in Fig. 8(a), i.e., some output neurons do
different σg values of LiSiOx synapses. From Fig. 8(a), it is not respond at all throughout the learning process, which is
identified that two types of learning errors will occur if large ascribed to the too small synapse conductance to cause the
initial σg (≥1) is with the synapses. The first type of error firing of the output neuron. These findings indicate that very
2848 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 66, NO. 6, JUNE 2019

simulations, providing “explainable” insights to diagnose the


failure mechanisms during the training of SNNs.

IV. C ONCLUSION
We have demonstrated that the initial conductance variation
of memristor-based synapses plays a deterministic role in the
pattern capacity of UL tasks. We have illustrated that in a
UL task of dynamic pattern recognition, incomplete learning
and deactivation of output neurons will occur given too large
Fig. 9. UL capacity defined as the percentage of successfully learned initial variation of the memristor conductance, while dupli-
motion routes Np /Ninput as a function of the measured LiSiOx conduc- cated learning given too small variation. Through adjusting
tance variance σg as shown in Fig. 5. The variance of UL capacity the forming voltages, conductance variance tuning of LiSiOx
(error bars) is caused by the randomness of LiSiOx synapses with
the same σg . synapses is demonstrated. SNN simulations are used to verify
that the learning capacity will be optimized at an appropriate
memristor’s conductance and its variance values so that errors,
such as incomplete, inactive, or duplicated learnings of the
large σg of memristor synapses will lead to a waste of the
dynamic patterns, can be minimized. Although, in this paper,
SNN computing resources in the sense that output neurons
the LiSiOx memristors are used for demonstration, and the
with too large/small synapse conductance do not contribute
proposed method is generic for the memristor-based UL design
to the learning. On the other hand, duplicated learnings will
due to the universality of initial conductance variation in
occur if the initial variance σg is too small (≤0.01) as indicated
electron devices, provided such a variation to be systematically
by double-head arrows in Fig. 8(b), which is explained by
experimentally investigated.
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