MULTI-STACKED THROUGH-SILICON-VIA EFFECTS ON SIGNAL INTEGRITY AND POWER INTEGRITY FOR APPLICATION OF 3-DIMENSIONAL STACKED

-CHIP-PACKAGE
Jun So Pak, Chunghyun Ryu and Joungho Kim
Paper Number: 2218 Terahertz Interconnection and Package Lab., Dept. of EECS, KAIST, Daejeon, Korea E-mail) chitoong@eeinfo.kaist.ac.kr

Terahertz Interconnection and Package Laboratory

Abstract

We investigate the multi-stacked through-silicon-via (TSV) effects on signal integrity (SI) and power integrity (PI) depending on the number of stacked TSVs. A single SG (Signal/Ground)-TSV-pair shows very small serial inductance (< 30 pH) due to its small height (80 µm), but very large serial resistance (70 mΩ) due to its small diameter (~80 µm) and shunt capacitance (> 4 pF) due to its thin SiO2 (0.2 µm) between TSV and silicon substrate. In multi-stacked TSV case of high frequency application, SI becomes worse due to its large resistance and large capacitance, but PI becomes better due to its small inductance and large capacitance.

3D Stacked Chip Package
Planar Type Multi-Chip Package (2-D) Low System Speed & Large Size Package - Large Space between Chips (2-D) Development of 3-D Stacked Chip Package Another Motivations

TSV (Through Silicon Via)
Definition

- To Increase Density: Mobile Application - To Increase Electrical Performance Shortest Interconnection Length Best Isolation between Chips - To Get Heterogeneous Integration in Small Area RF + Memory + Logic + Sensor Different Substrate - To Reduce Development Cost

3rd Chip (Thinned Substrate)

2nd Chip (Thinned Substrate)

E T
TSV

A R

a L

- TSV Through Silicon Via - Route the electrical signal through all die in the stack, rather than wire bonding around lower die to the substrate below
- Shortest interconnection distance
Pitch=150㎛ Cu/Sn Bump Si Substrate (ρ=10 Ω•cm)

o b

a r

o t

y r

2nd Chip

TSV
h=90㎛ ∅=75㎛

1st Chip

PKG Substrate

Advantages • Short Interconnection
Reduced RC Delays Low Impedance for Power Distribution Network Low Power Consumption Good Heat Dissipation (Shortest Thermal Via)

Under fill Dielectric

• No Space Limitation for Interconnection
Dielectric Under fill

1st Chip

Multi-level On-chip Interconnect SiO2 Si-Substrate

High Density Chip Wiring No Limitation of I/O Number No Limitation of I/O Pitch Small Area Package

• Simple Interposer
Short Redistribution Interconnection No Limitation of Vertical Interconnect Number

3-D TSV Stacked Chip Package

2 V 200 psec.1 1E 9 1 3 0.75 -1.75 -1.6 n H H 3E 9 nH 1.8 75 75 75 375 335 320 2.50 -0.5 GHz PKG PKG + 2 Stacked PKG + 5 Stacked PKG + 10 Stacked 75 105 191 360 1.1 0.50 -0.75 1. Choose Shorter Length TSV and Thinner SiO2 to Reduce Inductance & Increase Capacitance tal d To & ease Incr citance a Cap istance Res 0.8 n 1E 8 0.00 -1.25 -0.69 75 pF 36 0 p F 430 MHz 1E 7 1. PSP Impedance of Wire-bonding & TSV onC PackageInp ut P S P Im p e d a nc e Substrate o m p a ris o n o f 2. 200 psec.2 µm Embedded TSV : 80 µm 0.00 -0.01 0.1 o b 200 psec.1 1E 9 1 3 TSV pF @ 10 MHz Wire-bonding nH @ 1.5 GHz MHz 430 425 445 440 pF @ 10 MHz MHz nH @ 1.73 1.5 2.00 1E8 0.3 0.6 Package Substrate (20 mm × 20 mm) Reducing PSP Impedance PKG Dominant Raising PSP Impedance .5 S21 Magnitude [dB] 2 Stacked Voltage [V] 5 Stacked Increased Insertion Loss -0.1 0. Choose Larger Size TSV and Thicker SiO2 to Reduce Resistance & Capacitance To Enhance PI of 3-D TSV Stacked Chip Package.50 -0.4 0.3 2.3-D Electrical Model of TSV Structures of SG-TSV-Pair Si Thickness: 80 µm Pitc h: 2 00 µ m Insertion Loss of SG-TSV-Pair S21 Magnitude [dB] S21 magnitude [dB] Exposed TSV : 1 µm SiO2: 0. 1E 8 F re q ue nc y [H z ] a r 3E 9 5 Stacked Increased Signal Loss due to Larger Capacitance & Resistance 0.1 1E 7 y r 75 pF 1E10 10 3E10 30 10 Stacked N = # of Stacked Chips Conclusions Investigated Multi-Stacked TSV (Through Silicon Via) Effects on SI (Signal Integrity) & PI (Power Integrity) To Enhance SI of 3-D TSV Stacked Chip Package.2 0.25 -0.1 Large Resistance Large Capacitance (Large Slope) Large Insertion Loss TSV Height: 82 µm Si E Si R dge Terahertz Interconnection and Package Laboratory TSV Size tivit : 80 y: 1 µm Len 0Ω gth: ⋅ cm 1m m esis 1E9 1 Frequency [Hz] Frequency [GHz] SI (Signal Integrity) of Multi-Stacked TSVs MultiTSVs Insertion Loss of Multi-Stacked SG-TSV-Pairs 0.00 0.00 0.01 Frequency [GHz] Frequency [GHz] F re q ue nc y [H z ] 0.75 -0.69 1.0 10 Stacked 10 30 0.00 Variation of Eye Diagram depending on Number of Stacked SG-TSV-Pairs 2 Stacked 0.4 V 1 Frequency [GHz] PI (Power Integrity) of Multi-Stacked TSVs MultiTSVs Input PSP Impedance with TSVs Power TSV Ground Impedance [Ohm] Impedance [Ω] Impedance [Ohm] Impedance [Ω] Input PSP Impedance with Wire-bondings Power Ground 200 µm Ground Plane Power Plane Package Substrate (20 mm × 20 mm) E T N × 82 µm φ = 300 µm φ = 300 µm A R Wire-bonding Ground Plane Power Plane PSP Impedance pofaPackageeSubstrate Inp ut P S P Im e d nc e o f P a c ka g S ub s tra te 5E 5002 1E 1002 1E 1 a L 10 1 1 1 E -1 0.3 V o t 5E 5002 1E 1002 1E 1 10 1 1 1 E -1 0.25 -0.

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