Computer Organization – Functional Units of a Computer

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Functional Units of a Computer

1. The ______ format is usually used to store data.
a) BCD
b) Decimal
c) Hexadecimal
d) Octal
Answer: a
Explanation: The data usually used by computers have to be stored and represented in a
particular format for ease of use.

2. The 8-bit encoding format used to store data in a computer is ______

a) ASCII
b) EBCDIC
c) ANCI
d) USCII
Answer: b
Explanation: The data to be stored in the computers have to be encoded in a particular way
so as to provide secure processing of the data.

3. A source program is usually in _______

a) Assembly language
b) Machine level language
c) High-level language
d) Natural language
Answer: c
Explanation: The program written and before being compiled or assembled is called as a
source program.

4. Which memory device is generally made of semiconductors?

a) RAM
b) Hard-disk
c) Floppy disk
d) Cd disk
Answer: a
Explanation: Memory devices are usually made of semiconductors for faster manipulation of
the contents.

5. The small extremely fast, RAM’s are called as _______

a) Cache
b) Heaps
c) Accumulators
d) Stacks
Answer: a
Explanation: These small and fast memory devices are compared to RAM because they
optimize the performance of the system and they only keep files which are required by the
current process in them

6. The ALU makes use of _______ to store the intermediate results.

a) Accumulators
b) Registers
c) Heap
d) Stack
Answer: a
Explanation: The ALU is the computational center of the CPU. It performs all the
mathematical and logical operations. In order to perform better, it uses some internal memory
spaces to store immediate results.

7. The control unit controls other units by generating ____

a) Control signals
b) Timing signals
c) Transfer signals
d) Command Signals
Answer: b
Explanation: This unit is used to control and coordinate between the various parts and
components of the CPU.

8. ______ are numbers and encoded characters, generally used as operands.

a) Input
b) Data
c) Information
d) Stored Values
Answer: b
9. The Input devices can send information to the processor.
a) When the SIN status flag is set
b) When the data arrives regardless of the SIN flag
c) Neither of the cases
d) Either of the cases
Answer: a
Explanation: The input devices use buffers to store the data received and when the buffer has
some data it sends it to the processor.
10. ______ bus structure is usually used to connect I/O devices.
a) Single bus
b) Multiple bus
c) Star bus
d) Rambus
Answer: a
Explanation: BUS is a bunch of wires which carry address, control signals and data. It is used
to connect various components of the computer.

11. The I/O interface required to connect the I/O device to the bus consists of ______
a) Address decoder and registers
b) Control circuits
c) Address decoder, registers and Control circuits
d) Only Control circuits
Answer: c
Explanation: The I/O devices are connected to the CPU via BUS and to interact with the BUS
they have an interface.

12. To reduce the memory access time we generally make use of ______
a) Heaps
b) Higher capacity RAM’s
c) SDRAM’s
d) Cache’s
Answer: d
Explanation: The time required to access a part of the memory for data retrieval

13. ______ is generally used to increase the apparent size of physical memory.
a) Secondary memory
b) Virtual memory
c) Hard-disk
d) Disks
Answer: b
Explanation: Virtual memory is like an extension to the existing memory.

14. MFC stands for ___________

a) Memory Format Caches
b) Memory Function Complete
c) Memory Find Command
d) Mass Format Command
Answer: b
Explanation: This is a system command enabled when a memory function is completed by a
process.
15. The time delay between two successive initiation of memory operation _______
a) Memory access time
b) Memory search time
c) Memory cycle time
d) Instruction delay
Answer: c
Explanation: The time is taken to finish one task and to start another.

Basic Operational Concept

1. The decoded instruction is stored in ______
a) IR
b) PC
c) Registers
d) MDR
Answer: a
Explanation: The instruction after obtained from the PC, is decoded and operands are fetched
and stored in the IR.

2. The instruction -> Add LOCA, R0 does _______

a) Adds the value of LOCA to R0 and stores in the temp register
b) Adds the value of R0 to the address of LOCA
c) Adds the values of both LOCA and R0 and stores it in R0
d) Adds the value of LOCA with a value in accumulator and stores it in R0
Answer: c
3. Which registers can interact with the secondary storage?
a) MAR
b) PC
c) IR
d) R0
Answer: a
Explanation: MAR can interact with secondary storage in order to fetch data from it.

4. During the execution of a program which gets initialized first?

a) MDR
b) IR
c) PC
d) MAR
Answer: c
Explanation: For the execution of a process first the instruction is placed in the PC.

5. Which of the register/s of the processor is/are connected to Memory Bus?

a) PC
b) MAR
c) IR
d) Both PC and MAR
Answer: b
Explanation: MAR is connected to the memory BUS in order to access the memory

6. ISP stands for _________

a) Instruction Set Processor
b) Information Standard Processing
c) Interchange Standard Protocol
d) Interrupt Service Procedure
Answer: a
7. The internal Components of the processor are connected by _______
a) Processor intra-connectivity circuitry
b) Processor bus
c) Memory bus
d) Rambus
Answer: b
Explanation: The processor BUS is used to connect the various parts in order to provide a
direct connection to the CPU.

8. ______ is used to choose between incrementing the PC or performing ALU operations.

a) Conditional codes
b) Multiplexer
c) Control unit
d) None of the mentioned
Answer: b
Explanation: The multiplexer circuit is used to choose between the two as it can give different
results based on the input.

9. The registers, ALU and the interconnection between them are collectively called as _____
a) process route
b) information trail
c) information path
d) data path
Answer: d
Explanation: The Operational and processing part of the CPU are collectively called as a data
path.

10. _______ is used to store data in registers.

a) D flip flop
b) JK flip flop
c) RS flip flop d) None of the mentioned Answer: a
 BUS Structure
1. The main virtue for using single Bus structure is ____________
a) Fast data transfers
b) Cost effective connectivity and speed
c) Cost effective connectivity and ease of attaching peripheral devices
d) None of the mentioned
Answer: c
Explanation: By using a single BUS structure we can minimize the amount of hardware (wire)
required and thereby reducing the cost.

2. ______ are used to overcome the difference in data transfer speeds of various devices.
a) Speed enhancing circuitory
b) Bridge circuits
c) Multiple Buses
d) Buffer registers
Answer: d
Explanation: By using Buffer registers, the processor sends the data to the I/O device at the
processor speed and the data gets stored in the buffer. After that the data gets sent to or
from the buffer to the devices at the device speed.

3. To extend the connectivity of the processor bus we use ________

a) PCI bus
b) SCSI bus
c) Controllers
d) Multiple bus
Answer: a
Explanation: PCI BUS is used to connect other peripheral devices which require a direct
connection with the processor.

4. IBM developed a bus standard for their line of computers ‘PC AT’ called _____
a) IB bus
b) M-bus
c) ISA
d) None of the mentioned
Answer: c
5. The bus used to connect the monitor to the CPU is ______
a) PCI bus
b) SCSI bus
c) Memory bus
d) Rambus
Answer: b
Explanation: SCSI BUS is usually used to connect the video devices to the processor.
6. ANSI stands for __________
a) American National Standards Institute
b) American National Standard Interface
c) American Network Standard Interfacing
d) American Network Security Interrupt
Answer: a
7. _____ register Connected to the Processor bus is a single-way transfer capable.
a) PC
b) IR
c) Temp
d) Z
View Answer
Answer: d
Explanation: The Z register is a special register which can interact with the processor BUS
only.
8. In multiple Bus organisation, the registers are collectively placed and referred as ______
a) Set registers
b) Register file
c) Register Block
d) Map registers
Answer: b
9. The main advantage of multiple bus organisation over a single bus is _____
a) Reduction in the number of cycles for execution
b) Increase in size of the registers
c) Better Connectivity
d) None of the mentioned
Answer: a

10. The ISA standard Buses are used to connect ___________

a) RAM and processor
b) GPU and processor
c) Harddisk and Processor
d) CD/DVD drives and Processor
Answer: c

Performance of a System
1. During the execution of the instructions, a copy of the instructions is placed in the ______
a) Register
b) RAM
c) System heap
d) Cache
Answer: d
2. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose
A can execute an instruction with an average of 3 steps and B can execute with an average of 5
steps. For the execution of the same instruction which processor is faster?
a) A
b) B
c) Both take the same time
d) Insufficient information
Answer: a
Explanation: The performance of a system can be found out using the Basic performance
formula.

3. A processor performing fetch or decoding of different instruction during the execution of another
instruction is called ______
a) Super-scaling
b) Pipe-lining
c) Parallel Computation
d) None of the mentioned
Answer: b
Explanation: Pipe-lining is the process of improving the performance of the system by
processing different instructions at the same time, with only one instruction performing one
specific operation.

4. For a given FINITE number of instructions to be executed, which architecture of the processor
provides for a faster execution?
a) ISA
b) ANSA
c) Super-scalar
d) All of the mentioned
Answer: c
Explanation: In super-scalar architecture, the instructions are set in groups and they’re
decoded and executed together reducing the amount of time required to process them.

5. The clock rate of the processor can be improved by _________

a) Improving the IC technology of the logic circuits
b) Reducing the amount of processing done in one step
c) By using the overclocking method
d) All of the mentioned
Answer: d
Explanation: The clock rate(frequency of the processor) is the hardware dependent quantity it
is fixed for a given processor.

6. An optimizing Compiler does _________

a) Better compilation of the given piece of code
b) Takes advantage of the type of processor and reduces its process time
c) Does better memory management
d) none of the mentioned
Answer: b
Explanation: An optimizing compiler is a compiler designed for the specific purpose of
increasing the operation speed of the processor by reducing the time taken to compile the
program instructions.

7. The ultimate goal of a compiler is to ________

a) Reduce the clock cycles for a programming task
b) Reduce the size of the object code
c) Be versatile
d) Be able to detect even the smallest of errors
Answer: a
8. SPEC stands for _______
a) Standard Performance Evaluation Code
b) System Processing Enhancing Code
c) System Performance Evaluation Corporation
d) Standard Processing Enhancement Corporation
Answer: c
Explanation: SPEC is a corporation started to standardize the evaluation method of a
system’s performance.

9. As of 2000, the reference system to find the performance of a system is _____

a) Ultra SPARC 10
b) SUN SPARC
c) SUN II
d) None of the mentioned
Answer: a
Explanation: In SPEC system of measuring a system’s performance, a system is used as a
reference against which other systems are compared and performance is determined.

10. When Performing a looping operation, the instruction gets stored in the ______
a) Registers
b) Cache
c) System Heap
d) System stack
Answer: b
Explanation: When a looping or branching operation is carried out the offset value is stored
in the cache along with the data.

11. The average number of steps taken to execute the set of instructions can be made to be less
than one by following _______
a) ISA
b) Pipe-lining
c) Super-scaling
d) Sequential
Answer: c
Explanation: The number of steps required to execute a given set of instructions is
sufficiently reduced by using super-scaling. In this method, a set of instructions are grouped
together and are processed.

12. If a processor clock is rated as 1250 million cycles per second, then its clock period is ________
a) 1.9 * 10-10 sec
b) 1.6 * 10-9 sec
c) 1.25 * 10-10 sec
d) 8 * 10-10 sec
Answer: d
13. If the instruction, Add R1, R2, R3 is executed in a system which is pipe-lined, then the value of S
is (Where S is a term of the Basic performance equation)
a) 3
b) ~2
c) ~1
d) 6
Answer: c
Explanation: S is the number of steps required to execute the instructions.

14. CISC stands for _______

a) Complete Instruction Sequential Compilation
b) Computer Integrated Sequential Compiler
c) Complex Instruction Set Computer
d) Complex Instruction Sequential Compilation
Answer: c
Explanation: CISC is a type of system architecture where complex instructions are grouped
together and executed to improve the system performance.

15. As of 2000, the reference system to find the SPEC rating are built with _____ Processor.
a) Intel Atom SParc 300Mhz
b) Ultra SPARC -IIi 300MHZ
c) Amd Neutrino series
d) ASUS A series 450 Mhz
Answer: b
 Addressing Modes
1. The instruction, Add #45,R1 does _______
a) Adds the value of 45 to the address of R1 and stores 45 in that address
b) Adds 45 to the value of R1 and stores it in R1
c) Finds the memory location 45 and adds that content to that of R1
d) None of the mentioned
Answer: b
Explanation: The instruction is using immediate addressing mode hence the value is stored
in the location 45 is added.

2. In the case of, Zero-address instruction method the operands are stored in _____
a) Registers
b) Accumulators
c) Push down stack
d) Cache
Answer: c
Explanation: In this case, the operands are implicitly loaded onto the ALU.

3. Add #45, when this instruction is executed the following happen/s _______
a) The processor raises an error and requests for one more operand
b) The value stored in memory location 45 is retrieved and one more operand is requested
c) The value 45 gets added to the value on the stack and is pushed onto the stack
d) None of the mentioned
Answer: b
4. The addressing mode which makes use of in-direction pointers is ______
a) Indirect addressing mode
b) Index addressing mode
c) Relative addressing mode
d) Offset addressing mode
Answer: a
Explanation: In this addressing mode, the value of the register serves as another memory
location and hence we use pointers to get the data.

5. In the following indexed addressing mode instruction, MOV 5(R1),LOC the effective address is
______
a) EA = 5+R1
b) EA = R1
c) EA = [R1].
d) EA = 5+[R1].
Answer: d
Explanation: This instruction is in Base with offset addressing mode.
6. The addressing mode/s, which uses the PC instead of a general purpose register is ______
a) Indexed with offset
b) Relative
c) direct
d) both Indexed with offset and direct
Answer: b
Explanation: In this, the contents of the PC are directly incremented.

7. When we use auto increment or auto decrements, which of the following is/are true?
1) In both, the address is used to retrieve the operand and then the address gets altered
2) In auto increment, the operand is retrieved first and then the address altered
3) Both of them can be used on general purpose registers as well as memory locations
a) 1, 2, 3
b) 2
c) 1, 3
d) 2, 3
Answer: d
Explanation: In the case of, auto increment the increment is done afterward and in auto
decrement the decrement is done first.

8. The addressing mode, where you directly specify the operand value is _______
a) Immediate
b) Direct
c) Definite
d) Relative
Answer: a
9. The effective address of the following instruction is MUL 5(R1,R2).
a) 5+R1+R2
b) 5+(R1*R2)
c) 5+[R1]+[R2].
d) 5*([R1]+[R2])
Answer: c
Explanation: The addressing mode used is base with offset and index.

10. _____ addressing mode is most suitable to change the normal sequence of execution of
instructions.
a) Relative
b) Indirect
c) Index with Offset
d) Immediate
Answer: a
Explanation: The relative addressing mode is used for this since it directly updates the PC.
 Numbers and Arithmetic Operations
1. Which method/s of representation of numbers occupies a large amount of memory than others?
a) Sign-magnitude
b) 1’s complement
c) 2’s complement
d) 1’s & 2’s compliment
Answer: a
Explanation: It takes more memory as one bit used up to store the sign.

2. Which representation is most efficient to perform arithmetic operations on the numbers?

a) Sign-magnitude
b) 1’s complement
c) 2’S complement
d) None of the mentioned
Answer: c
Explanation: The two’s complement form is more suitable to perform arithmetic operations as
there is no need to involve the sign of the number into consideration.

3. Which method of representation has two representations for ‘0’?

a) Sign-magnitude
b) 1’s complement
c) 2’s complement
d) None of the mentioned
Answer: a
Explanation: One is positive and one for negative.

4. When we perform subtraction on -7 and 1 the answer in 2’s complement form is _________
a) 1010
b) 1110
c) 0110
d) 1000
Answer: d
Explanation: First the 2’s complement is found and that is added to the number and the
overflow is ignored.

5. When we perform subtraction on -7 and -5 the answer in 2’s complement form is ________
a) 11110
b) 1110
c) 1010
d) 0010
Answer: b
Explanation: First the 2’s complement is found and that is added to the number and the
overflow is ignored.
6. When we subtract -3 from 2 , the answer in 2’s complement form is _________
a) 0001
b) 1101
c) 0101
d) 1001
Answer: c
Explanation: First the 2’s complement is found and that is added to the number and the
overflow is ignored.

7. The processor keeps track of the results of its operations using a flags called ________
a) Conditional code flags
b) Test output flags
c) Type flags
d) None of the mentioned
Answer: a
Explanation: These flags are used to indicate if there is an overflow or carry or zero result
occurrence.

8. The register used to store the flags is called as _________

a) Flag register
b) Status register
c) Test register
d) Log register
Answer: b
Explanation: The status register stores the condition codes of the system.

9. The Flag ‘V’ is set to 1 indicates that,

a) The operation is valid
b) The operation is validated
c) The operation has resulted in an overflow
d) None of the mentioned
Answer: c
Explanation: This is used to check the overflow occurs in the operation.

10. In some pipelined systems, a different instruction is used to add to numbers which can affect the
flags upon execution. That instruction is _______
a) AddSetCC
b) AddCC
c) Add++
d) SumSetCC
Answer: a
Explanation: By using this instruction the condition flags won’t be affected at all.
11. The most efficient method followed by computers to multiply two unsigned numbers is _______
a) Booth algorithm
b) Bit pair recording of multipliers
c) Restoring algorithm
d) Non restoring algorithm
Answer: b
12. For the addition of large integers, most of the systems make use of ______
a) Fast adders
b) Full adders
c) Carry look-ahead adders
d) None of the mentioned
Answer: c
Explanation: In this method the carries for each step are generated first.

13. In a normal n-bit adder, to find out if an overflow as occurred we make use of ________
a) And gate
b) Nand gate
c) Nor gate
d) Xor gate
Answer: d
14. In the implementation of a Multiplier circuit in the system we make use of _______
a) Counter
b) Flip flop
c) Shift register
d) Push down stack
Answer: c
Explanation: The shift registers are used to store the multiplied answer.

15. When 1101 is used to divide 100010010 the remainder is ______

a) 101
b) 11
c) 0
d) 1
Answer: d

Memory Locations and Addresses

1. The smallest entity of memory is called _______
a) Cell
b) Block
c) Instance
d) Unit
Answer: a
Explanation: Each data is made up of a number of units.

2. The collection of the above mentioned entities where data is stored is called ______
a) Block
b) Set
c) Word
d) Byte
Answer: c
Explanation: Each readable part of data is called as blocks.

3. An 24 bit address generates an address space of ______ locations.

a) 1024
b) 4096
c) 248
d) 16,777,216
Answer: d
Explanation: The number of addressable locations in the system is called as address space.

4. If a system is 64 bit machine, then the length of each word will be _______
a) 4 bytes
b) 8 bytes
c) 16 bytes
d) 12 bytes
Answer: b
Explanation: A 64 bit system means, that at a time 64 bit instruction can be executed.

5. The type of memory assignment used in Intel processors is _____

a) Little Endian
b) Big Endian
c) Medium Endian
d) None of the mentioned
Answer: a
Explanation: The method of address allocation to data to be stored is called as memory
assignment.

6. When using the Big Endian assignment to store a number, the sign bit of the number is stored in
_____
a) The higher order byte of the word
b) The lower order byte of the word
c) Can’t say
d) None of the mentioned
Answer: a
7. To get the physical address from the logical address generated by CPU we use ____
a) MAR
b) MMU
c) Overlays
d) TLB
Answer: b
Explanation: Memory Management Unit, is used to add the offset to the logical address
generated by the CPU to get the physical address.

8. _____ method is used to map logical addresses of variable length onto physical memory.
a) Paging
b) Overlays
c) Segmentation
d) Paging with segmentation
Answer: c
Explanation: Segmentation is a process in which memory is divided into groups of variable
length called segments.

9. During the transfer of data between the processor and memory we use ______
a) Cache
b) TLB
c) Buffers
d) Registers
Answer: d
10. Physical memory is divided into sets of finite size called as ______
a) Frames
b) Pages
c) Blocks
d) Vectors
Answer: a

Memory Operations and Management

1. Add #%01011101,R1 , when this instruction is executed then _________
a) The binary addition between the operands takes place
b) The Numerical value represented by the binary value is added to the value of R1
c) The addition doesn’t take place, whereas this is similar to a MOV instruction
d) None of the mentioned
Answer: a
Explanation: This performs operations in binary mode directly.
2. If we want to perform memory or arithmetic operations on data in Hexa-decimal mode then we
use ___ symbol before the operand.
a) ~
b) !
c) $
d) *
Answer: c
3. When generating physical addresses from a logical address the offset is stored in _____
a) Translation look-aside buffer
b) Relocation register
c) Page table
d) Shift register
Answer: b
Explanation: In the MMU the relocation register stores the offset address.

4. The technique used to store programs larger than the memory is ______
a) Overlays
b) Extension registers
c) Buffers
d) Both Extension registers and Buffers
Answer: a
Explanation: In this, only a part of the program getting executed is stored on the memory and
later swapped in for the other part.

5. The unit which acts as an intermediate agent between memory and backing store to reduce
process time is _____
a) TLB’s
b) Registers
c) Page tables
d) Cache
Answer: d
Explanation: The cache’s help in data transfers by storing most recently used memory pages.

6. The Load instruction does the following operation/s,

a) Loads the contents of a disc onto a memory location
b) Loads the contents of a location onto the accumulators
c) Load the contents of the PCB onto the register
d) None of the mentioned
Answer: b
Explanation: The load instruction is basically used to load the contents of a memory location
onto a register.

7. Complete the following analogy:- Registers are to RAM’s as Cache’s are to _____
a) System stacks
b) Overlays
c) Page Table
d) TLB
Answer: d
8. The BOOT sector files of the system are stored in _____
a) Harddisk
b) ROM
c) RAM
d) Fast solid state chips in the motherboard
Answer: b
Explanation: The files which are required for the starting up of a system are stored on the
ROM.

9. The transfer of large chunks of data with the involvement of the processor is done by _______
a) DMA controller
b) Arbitrator
c) User system programs
d) None of the mentioned
Answer: a
Explanation: This mode of transfer involves the transfer of a large block of data from the
memory.

10. Which of the following technique/s used to effectively utilize main memory?
a) Address binding
b) Dynamic linking
c) Dynamic loading
d) Both Dynamic linking and loading
Answer: c
Explanation: In this method only when the routine is required is loaded and hence saves
memory.

Instructions and Instruction Sequencing

1. RTN stands for ___________
a) Register Transfer Notation
b) Register Transmission Notation
c) Regular Transmission Notation
d) Regular Transfer Notation
Answer:a
Explanation: This is the way of writing the assembly language code with the help of register
notations.
2. The instruction, Add Loc,R1 in RTN is _______
a) AddSetCC Loc+R1
b) R1=Loc+R1
c) Not possible to write in RTN
d) R1<-[Loc]+[R1].
Answer:d
3. Can you perform addition on three operands simultaneously in ALN using Add instruction?
a) Yes
b) Not possible using Add, we’ve to use AddSetCC
c) Not permitted
d) None of the mentioned
Answer:c
Explanation: You cannot perform addition on three operands simultaneously because the
third operand is where the result is stored.

4. The instruction, Add R1,R2,R3 in RTN is _______

a) R3=R1+R2+R3
b) R3<-[R1]+[R2]+[R3].
c) R3=[R1]+[R2].
d) R3<-[R1]+[R2].
Answer:d
Explanation: In RTN the first operand is the destination and the second operand is the
source.

5. In a system, which has 32 registers the register id is ____ long.

a) 16 bit
b) 8 bits
c) 5 bits
d) 6 bits
Answer:c
Explanation: The ID is the name tag given to each of the registers and used to identify them.

6. The two phases of executing an instruction are __________

a) Instruction decoding and storage
b) Instruction fetch and instruction execution
c) Instruction execution and storage
d) Instruction fetch and Instruction processing
Answer:b
Explanation: First, the instructions are fetched and decoded and then they’re executed and
stored.

7. The Instruction fetch phase ends with _________

a) Placing the data from the address in MAR into MDR
b) Placing the address of the data into MAR
c) Completing the execution of the data and placing its storage address into MAR
d) Decoding the data in MDR and placing it in IR
Answer:d
Explanation: The fetch ends with the instruction getting decoded and being placed in the IR
and the PC getting incremented.

8. While using the iterative construct (Branching) in execution ____ instruction is used to check the
condition.
a) TestAndSet
b) Branch
c) TestCondn
d) None of the mentioned
Answer:b
Explanation: Branch instruction is used to check the test condition and to perform the
memory jump with help of offset.

9. When using Branching, the usual sequencing of the PC is altered. A new instruction is loaded
which is called as ______
a) Branch target
b) Loop target
c) Forward target
d) Jump instruction
Answer:a
10. The condition flag Z is set to 1 to indicate _______
a) The operation has resulted in an error
b) The operation requires an interrupt call
c) The result is zero
d) There is no empty register available
Answer:c
Explanation: This condition flag is used to check if the arithmetic operation yields a zero
output.

Assembly Language
1. ____ converts the programs written in assembly language into machine instructions.
a) Machine compiler
b) Interpreter
c) Assembler
d) Converter
Answer: c
Explanation: An assembler is a software used to convert the programs into machine
instructions.
2. The instructions like MOV or ADD are called as ______
a) OP-Code
b) Operators
c) Commands
d) None of the mentioned
Answer: a
Explanation: This OP – codes tell the system what operation to perform on the operands.

3. The alternate way of writing the instruction, ADD #5,R1 is ______

a) ADD [5],[R1];
b) ADDI 5,R1;
c) ADDIME 5,[R1];
d) There is no other way
Answer: b
Explanation: The ADDI instruction, means the addition is in immediate addressing mode.

4. Instructions which won’t appear in the object program are called as _____
a) Redundant instructions
b) Exceptions
c) Comments
d) Assembler Directives
Answer: d
Explanation: The directives help the program in getting compiled and hence wont be there in
the object code.

5. The assembler directive EQU, when used in the instruction: Sum EQU 200 does ________
a) Finds the first occurrence of Sum and assigns value 200 to it
b) Replaces every occurrence of Sum with 200
c) Re-assigns the address of Sum by adding 200 to its original address
d) Assigns 200 bytes of memory starting the location of Sum
Answer: b
Explanation: This basically is used to replace the variable with a constant value.

6. The purpose of the ORIGIN directive is __________

a) To indicate the starting position in memory, where the program block is to be stored
b) To indicate the starting of the computation code
c) To indicate the purpose of the code
d) To list the locations of all the registers used
Answer: a
Explanation: This does the function similar to the main statement.

7. The directive used to perform initialization before the execution of the code is ______
a) Reserve
b) Store
c) Dataword
d) EQU
Answer: c
8. _____ directive is used to specify and assign the memory required for the block of code.
a) Allocate
b) Assign
c) Set
d) Reserve
Answer: d
Explanation: This instruction is used to allocate a block of memory and to store the object
code of the program there.

9. _____ directive specifies the end of execution of a program.

a) End
b) Return
c) Stop
d) Terminate
Answer: b
Explanation: This instruction directive is used to terminate the program execution.

10. The last statement of the source program should be _______

a) Stop
b) Return
c) OP
d) End
Answer: d
Explanation: This enables the processor to load some other process.

11. When dealing with the branching code the assembler ___________
a) Replaces the target with its address
b) Does not replace until the test condition is satisfied
c) Finds the Branch offset and replaces the Branch target with it
d) Replaces the target with the value specified by the DATAWORD directive
Answer: c
Explanation: When the assembler comes across the branch code, it immediately finds the
branch offset and replaces it with it.

12. The assembler stores all the names and their corresponding values in ______
a) Special purpose Register
b) Symbol Table
c) Value map Set
d) None of the mentioned
Answer: b
Explanation: The table where the assembler stores the variable names along with their
corresponding memory locations and values.

13. The assembler stores the object code in ______

a) Main memory
b) Cache
c) RAM
d) Magnetic disk
Answer: d
Explanation: After compiling the object code, the assembler stores it in the magnetic disk
and waits for further execution.

14. The utility program used to bring the object code into memory for execution is ______
a) Loader
b) Fetcher
c) Extractor
d) Linker
Answer: a
Explanation: The program which is used to load the program into memory.

15. To overcome the problems of the assembler in dealing with branching code we use _____
a) Interpreter
b) Debugger
c) Op-Assembler
d) Two-pass assembler
Answer: d
Explanation: This creates entries into the symbol table first and then creates the object code.

Subroutines and Nesting

1. The return address of the Sub-routine is pointed to by _______
a) IR
b) PC
c) MAR
d) Special memory registers
Answer: b
Explanation: The return address from the subroutine is pointed to by the PC.

2. The location to return to, from the subroutine is stored in _______

a) TLB
b) PC
c) MAR
d) Link registers
Answer: d
Explanation: The registers store the return address of the routine and is pointed to by the PC.

3. Subroutine nesting means,

a) Having multiple subroutines in a program
b) Using a linking nest statement to put many subroutines under the same name
c) Having one routine call the other
d) None of the mentioned
Answer: c
4. The order in which the return addresses are generated and used is _________
a) LIFO
b) FIFO
c) Random
d) Highest priority
Answer: a
Explanation: That is the routine called first is returned first.

5. In case of nested subroutines the return addresses are stored in __________

a) System heap
b) Special memory buffers
c) Processor stack
d) Registers
Answer: c
Explanation: In this case, there will be more number of return addresses it is stored on the
processor stack.

6. The appropriate return addresses are obtained with the help of ____ in case of nested routines.
a) MAR
b) MDR
c) Buffers
d) Stack-pointers
Answer: d
Explanation: The pointers are used to point to the location on the stack where the address is
stored.

7. When parameters are being passed on to the subroutines they are stored in ________
a) Registers
b) Memory locations
c) Processor stacks
d) All of the mentioned
Answer: d
Explanation: In the case of, parameter passing the data can be stored on any of the storage
space.
8. The most efficient way of handling parameter passing is by using ______
a) General purpose registers
b) Stacks
c) Memory locations
d) None of the mentioned
Answer: a
Explanation: By using general purpose registers for the parameter passing we make the
process more efficient.

9. The most Flexible way of logging the return addresses of the subroutines is by using _______
a) Registers
b) Stacks
c) Memory locations
d) None of the mentioned
Answer: b
Explanation: The stacks are used as Logs for return addresses of the subroutines.

10. The wrong statement/s regarding interrupts and subroutines among the following is/are ______
i) The sub-routine and interrupts have a return statement
ii) Both of them alter the content of the PC
iii) Both are software oriented
iv) Both can be initiated by the user
a) i, ii and iv
b) ii and iii
c) iv
d) iii and iv
Answer: d

Parameter Passing and Stack Frame

1. The private work space dedicated to a subroutine is called as ________
a) System heap
b) Reserve
c) Stack frame
d) Allocation
Answer: c
Explanation: This work space is where the intermediate values of the subroutines are stored.

2. If the subroutine exceeds the private space allocated to it then the values are pushed onto
_________
a) Stack
b) System heap
c) Reserve Space
d) Stack frame
Answer: a
Explanation: If the allocated work space is exceeded then the data is pushed onto the system
stack.

3. ______ pointer is used to point to parameters passed or local parameters of the subroutine.
a) Stack pointer
b) Frame pointer
c) Parameter register
d) Log register
Answer: b
Explanation: This pointer is used to track the current position of the stack being used.

4. The reserved memory or private space of the subroutine gets deallocated when _______
a) The stop instruction is executed by the routine
b) The pointer reaches the end of the space
c) When the routine’s return statement is executed
d) None of the mentioned
Answer: c
Explanation: The work space allocated to a subroutine gets deallocated when the routine is
completed.

5. The private space gets allocated to each subroutine when _________

a) The first statement of the routine is executed
b) When the context switch takes place
c) When the routine gets called
d) When the Allocate instruction is executed
Answer: c
Explanation: When the call statement is executed, simultaneously space also gets allocated.

6. _____ the most suitable data structure used to store the return addresses in the case of nested
subroutines.
a) Heap
b) Stack
c) Queue
d) List
Answer: b
7. In case of nested subroutines, the stack top is always _________
a) The saved contents of the called sub routine
b) The saved contents of the calling sub routine
c) The return addresses of the called sub routine
d) None of the mentioned Answer: a
8. The stack frame for each subroutine is present in ______
a) Main memory
b) System Heap
c) Processor Stack
d) None of the mentioned
Answer: c
Explanation: The memory for the work space is allocated from the processor stack.

9. The data structure suitable for scheduling processes is _______

a) List
b) Heap
c) Queue
d) Stack
Answer: c
Explanation: The Queue data structure is generally used for scheduling as it is two
directional.

10. The sub-routine service procedure is similar to that of the interrupt service routine in ________
a) Method of context switch
b) Returning
c) Process execution
d) Method of context switch & Process execution
Answer: d
Explanation: The Subroutine service procedure is the same as the interrupt service routine in
all aspects, except the fact that interrupt might not be related to the process being executed.

Accessing I/O Devices

1. In memory-mapped I/O ____________
a) The I/O devices and the memory share the same address space
b) The I/O devices have a separate address space
c) The memory and I/O devices have an associated address space
d) A part of the memory is specifically set aside for the I/O operation
Answer: a
Explanation: Its the different modes of accessing the i/o devices.

2. The usual BUS structure used to connect the I/O devices is ___________
a) Star BUS structure
b) Multiple BUS structure
c) Single BUS structure
d) Node to Node BUS structure
Answer: c
Explanation: BUS is a collection of address, control and data lines used to connect the
various devices of the computer.
3. In intel’s IA-32 architecture there is a separate 16 bit address space for the I/O devices?
a) False
b) True
Answer: b
Explanation: This type of access is called as I/O mapped devices.

4. The advantage of I/O mapped devices to memory mapped is ___________

a) The former offers faster transfer of data
b) The devices connected using I/O mapping have a bigger buffer space
c) The devices have to deal with fewer address lines
d) No advantage as such
Answer: c
Explanation: Since the I/O mapped devices have a separate address space the address lines
are limited by the amount of the space allocated.

5. The system is notified of a read or write operation by ___________

a) Appending an extra bit of the address
b) Enabling the read or write bits of the devices
c) Raising an appropriate interrupt signal
d) Sending a special signal along the BUS
Answer: d
Explanation: It is necessary for the processor to send a signal intimating the request as
either read or write.

6. To overcome the lag in the operating speeds of the I/O device and the processor we use
___________
a) BUffer spaces
b) Status flags
c) Interrupt signals
d) Exceptions
Answer: b
Explanation: The processor operating is much faster than that of the I/O devices, so by using
the status flags the processor need not wait till the I/O operation is done. It can continue with
its work until the status flag is set.

7. The method of accessing the I/O devices by repeatedly checking the status flags is ___________
a) Program-controlled I/O
b) Memory-mapped I/O
c) I/O mapped
d) None of the mentioned
Answer: a
Explanation: In this method, the processor constantly checks the status flags, and when it
finds that the flag is set it performs the appropriate operation.
8. The method of synchronising the processor with the I/O device in which the device sends a signal
when it is ready is
a) Exceptions
b) Signal handling
c) Interrupts
d) DMA
Answer: c
Explanation: This is a method of accessing the I/O devices which gives the complete power
to the devices, enabling them to intimate the processor when they’re ready for transfer.

9. The method which offers higher speeds of I/O transfers is ___________

a) Interrupts
b) Memory mapping
c) Program-controlled I/O
d) DMA
Answer: d
Explanation: In DMA the I/O devices are directly allowed to interact with the memory without
the intervention of the processor and the transfers take place in the form of blocks increasing
the speed of operation.

10. The process wherein the processor constantly checks the status flags is called as
a) Polling
b) Inspection
c) Reviewing
d) Echoing
Answer: a

Interrupts – 1