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MCP3204/3208

2.7V 4-Channel/8-Channel 12-Bit A/D Converters


with SPI Serial Interface
Features Description
• 12-bit resolution The Microchip Technology Inc. MCP3204/3208
• ± 1 LSB max DNL devices are successive approximation 12-bit Analog-
• ± 1 LSB max INL (MCP3204/3208-B) to-Digital (A/D) Converters with on-board sample and
hold circuitry. The MCP3204 is programmable to
• ± 2 LSB max INL (MCP3204/3208-C)
provide two pseudo-differential input pairs or four
• 4 (MCP3204) or 8 (MCP3208) input channels single-ended inputs. The MCP3208 is programmable
• Analog inputs programmable as single-ended or to provide four pseudo-differential input pairs or eight
pseudo-differential pairs single-ended inputs. Differential Nonlinearity (DNL) is
• On-chip sample and hold specified at ±1 LSB, while Integral Nonlinearity (INL) is
• SPI serial interface (modes 0,0 and 1,1) offered in ±1 LSB (MCP3204/3208-B) and ±2 LSB
(MCP3204/3208-C) versions.
• Single supply operation: 2.7V - 5.5V
• 100 ksps max. sampling rate at VDD = 5V Communication with the devices is accomplished using
a simple serial interface compatible with the SPI
• 50 ksps max. sampling rate at VDD = 2.7V
protocol. The devices are capable of conversion rates
• Low power CMOS technology: of up to 100 ksps. The MCP3204/3208 devices operate
- 500 nA typical standby current, 2 µA max. over a broad voltage range (2.7V - 5.5V). Low current
- 400 µA max. active current at 5V design permits operation with typical standby and
• Industrial temp range: -40°C to +85°C active currents of only 500 nA and 320 µA,
• Available in PDIP, SOIC and TSSOP packages respectively. The MCP3204 is offered in 14-pin PDIP,
150 mil SOIC and TSSOP packages. The MCP3208 is
offered in 16-pin PDIP and SOIC packages.
Applications
• Sensor Interface Package Types
• Process Control PDIP, SOIC, TSSOP
• Data Acquisition
CH0 1 14 VDD
• Battery Operated Systems CH1 2 13 VREF
MCP3204

CH2 3 12 AGND
CH3 4 11 CLK
Functional Block Diagram
NC 5 10 DOUT
NC 6 9 DIN
VDD VSS
DGND 7 8 CS/SHDN
VREF

CH0 PDIP, SOIC


CH1 Input
Channel CH0 1 16 VDD
DAC
Mux CH1 2 15 VREF
CH7*
MCP3208

CH2 3 14 AGND
Comparator CH3 4 13 CLK
12-Bit SAR CH4 5 12 DOUT
Sample
and CH5 6 11 DIN
Hold CH6 7 10 CS/SHDN
CH7 8 9 DGND
Shift
Control Logic Register

CS/SHDN DIN CLK DOUT

* Note: Channels 5-7 available on MCP3208 Only

© 2008 Microchip Technology Inc. DS21298E-page 1


MCP3204/3208
1.0 ELECTRICAL †Notice: Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
CHARACTERISTICS a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
Absolute Maximum Ratings† operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
VDD...................................................................................7.0V device reliability.
All inputs and outputs w.r.t. VSS ............... -0.6V to VDD +0.6V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD protection on all pins.............................................> 4 kV

ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, VREF = 5V,
TA = -40°C to +85°C,fSAMPLE = 100 ksps and fCLK = 20*fSAMPLE
Parameters Sym Min Typ Max Units Conditions
Conversion Rate
Conversion Time tCONV — — 12 clock
cycles
Analog Input Sample Time tSAMPLE 1.5 clock
cycles
Throughput Rate fSAMPLE — — 100 ksps VDD = VREF = 5V
— — 50 ksps VDD = VREF = 2.7V
DC Accuracy
Resolution 12 bits
Integral Nonlinearity INL — ±0.75 ±1 LSB MCP3204/3208-B
— ±1.0 ±2 MCP3204/3208-C
Differential Nonlinearity DNL — ±0.5 ±1 LSB No missing codes
over-temperature
Offset Error — ±1.25 ±3 LSB
Gain Error — ±1.25 ±5 LSB
Dynamic Performance
Total Harmonic Distortion — -82 — dB VIN = 0.1V to 4.9V@1 kHz
Signal to Noise and Distortion — 72 — dB VIN = 0.1V to 4.9V@1 kHz
(SINAD)
Spurious Free Dynamic — 86 — dB VIN = 0.1V to 4.9V@1 kHz
Range
Reference Input
Voltage Range 0.25 — VDD V Note 2
Current Drain — 100 150 µA
— 0.001 3.0 µA CS = VDD = 5V
Analog Inputs
Input Voltage Range for CH0- VSS — VREF V
CH7 in Single-Ended Mode
Input Voltage Range for IN+ in IN- — VREF+IN-
pseudo-differential Mode
Note 1: This parameter is established by characterization and not 100% tested.
2: See graphs that relate linearity performance to VREF levels.
3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity
performance, particularly at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock
Speed”, “Maintaining Minimum Clock Speed”, for more information.

DS21298E-page 2 © 2008 Microchip Technology Inc.


MCP3204/3208
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, VREF = 5V,
TA = -40°C to +85°C,fSAMPLE = 100 ksps and fCLK = 20*fSAMPLE
Parameters Sym Min Typ Max Units Conditions
Input Voltage Range for IN- in VSS-100 — VSS+100 mV
pseudo-differential Mode
Leakage Current — 0.001 ±1 µA
Switch Resistance — 1000 — Ω See Figure 4-1
Sample Capacitor — 20 — pF See Figure 4-1
Digital Input/Output
Data Coding Format Straight Binary
High Level Input Voltage VIH 0.7 VDD — — V
Low Level Input Voltage VIL — — 0.3 VDD V
High Level Output Voltage VOH 4.1 — — V IOH = -1 mA, VDD = 4.5V
Low Level Output Voltage VOL — — 0.4 V IOL = 1 mA, VDD = 4.5V
Input Leakage Current ILI -10 — 10 µA VIN = VSS or VDD
Output Leakage Current ILO -10 — 10 µA VOUT = VSS or VDD
Pin Capacitance CIN,COUT — — 10 pF VDD = 5.0V (Note 1)
(All Inputs/Outputs) TA = 25°C, f = 1 MHz
Timing Parameters
Clock Frequency fCLK — — 2.0 MHz VDD = 5V (Note 3)
— — 1.0 MHz VDD = 2.7V (Note 3)
Clock High Time tHI 250 — — ns
Clock Low Time tLO 250 — — ns
CS Fall To First Rising CLK tSUCS 100 — — ns
Edge
Data Input Setup Time tSU 50 — — ns
Data Input Hold Time tHD 50 — — ns
CLK Fall To Output Data Valid tDO — — 200 ns See Figures 1-2 and 1-3
CLK Fall To Output Enable tEN — — 200 ns See Figures 1-2 and 1-3
CS Rise To Output Disable tDIS — — 100 ns See Figures 1-2 and 1-3
CS Disable Time tCSH 500 — — ns
DOUT Rise Time tR — — 100 ns See Figures 1-2 and 1-3 (Note 1)
DOUT Fall Time tF — — 100 ns See Figures 1-2 and 1-3 (Note 1)
Power Requirements
Operating Voltage VDD 2.7 — 5.5 V
Operating Current IDD — 320 400 µA VDD=VREF = 5V, DOUT unloaded
— 225 — VDD=VREF = 2.7V, DOUT unloaded
Standby Current IDDS — 0.5 2.0 µA CS = VDD = 5.0V
Note 1: This parameter is established by characterization and not 100% tested.
2: See graphs that relate linearity performance to VREF levels.
3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity
performance, particularly at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock
Speed”, “Maintaining Minimum Clock Speed”, for more information.

© 2008 Microchip Technology Inc. DS21298E-page 3


MCP3204/3208
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 5V
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA -40 — +125 °C
Operating Temperature Range TA -40 — +125 °C
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 14L-PDIP θJA — 70 — °C/W
Thermal Resistance, 14L-SOIC θJA — 95.3 — °C/W
Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W
Thermal Resistance, 16L-PDIP θJA — 70 — °C/W
Thermal Resistance, 16L-SOIC θJA — 86.1 — °C/W

tCSH

CS
tSUCS
tHI tLO

CLK

tSU tHD
DIN MSB IN

tDO tR tF tDIS
tEN
DOUT Null Bit MSB OUT LSB

FIGURE 1-1: Serial Interface Timing.

DS21298E-page 4 © 2008 Microchip Technology Inc.


MCP3204/3208

1.4V Test Point


VDD
3 kΩ tDIS Waveform 2
Test Point 3 kΩ VDD/2
DOUT DOUT tEN Waveform

CL = 100 pF 100 pF tDIS Waveform 1


VSS

Voltage Waveforms for tR, tF


Voltage Waveforms for tEN
VOH
DOUT VOL
CS
tR tF

CLK 1 2 3 4
Voltage Waveforms for tDO
DOUT B11

CLK tEN

tDO
Voltage Waveforms for tDIS
DOUT
VIH
CS

FIGURE 1-2: Load Circuit for tR, tF, tDO. DOUT


90%
Waveform 1*
TDIS

DOUT 10%
Waveform 2†
* Waveform 1 is for an output with internal
conditions such that the output is high,
unless disabled by the output control.
† Waveform 2 is for an output with internal
conditions such that the output is low,
unless disabled by the output control.

FIGURE 1-3: Load circuit for tDIS and tEN.

© 2008 Microchip Technology Inc. DS21298E-page 5


MCP3204/3208
NOTES:

DS21298E-page 6 © 2008 Microchip Technology Inc.


MCP3204/3208
2.0 TYPICAL PERFORMANCE CHARACTERISTICS
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE, TA = +25°C.

1.0 2.0
0.8 Positive INL VDD = VREF = 2.7 V
1.5
0.6
1.0
0.4 Positive INL

INL (LSB)
0.5
INL (LSB)

0.2
0.0 0.0
-0.2 -0.5
Negative INL
-0.4 Negative INL -1.0
-0.6
-1.5
-0.8
-2.0
-1.0
0 10 20 30 40 50 60 70 80
0 25 50 75 100 125 150
Sample Rate (ksps) Sample Rate (ksps)

FIGURE 2-1: Integral Nonlinearity (INL) FIGURE 2-4: Integral Nonlinearity (INL)
vs. Sample Rate. vs. Sample Rate (VDD = 2.7V).

2.5
2.0
2.0
1.5
1.5 Positive INL
1.0
1.0
INL (LSB)

Positive INL
INL (LSB)

0.5 0.5

0.0 0.0

-0.5 -0.5
-1.0 Negative INL -1.0
Negative INL
-1.5 -1.5
-2.0
-2.0
0 1 2 3 4 5
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VREF (V) VREF (V)

FIGURE 2-2: Integral Nonlinearity (INL) FIGURE 2-5: Integral Nonlinearity (INL)
vs. VREF . vs. VREF (VDD = 2.7V).

1.0 1.0
0.8 VDD = VREF = 2.7 V
0.8
FSAMPLE = 50 ksps
0.6 0.6
0.4 0.4
INL (LSB)
INL (LSB)

0.2 0.2
0.0 0.0
-0.2 -0.2
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1.0 -1.0
0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096
Digital Code Digital Code

FIGURE 2-3: Integral Nonlinearity (INL) FIGURE 2-6: Integral Nonlinearity (INL)
vs. Code (Representative Part). vs. Code (Representative Part, VDD = 2.7V).

© 2008 Microchip Technology Inc. DS21298E-page 7


MCP3204/3208
Note: Unless otherwise indicated, VDD = VREF = 5 V, VSS = 0 V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE, TA = +25°C.

1.0 1.0
VDD = VREF = 2.7 V
0.8 0.8
Positive INL FSAMPLE = 50 ksps
0.6 0.6
Positive INL
0.4 0.4

INL (LSB)
INL (LSB)

0.2 0.2

0.0 0.0

-0.2 Negative INL -0.2

-0.4 -0.4

-0.6 -0.6 Negative INL


-0.8 -0.8

-1.0 -1.0
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Temperature (°C) Temperature (°C)

FIGURE 2-7: Integral Nonlinearity (INL) FIGURE 2-10: Integral Nonlinearity (INL)
vs. Temperature. vs. Temperature (VDD = 2.7V).

1.0 2.0
VDD = VREF = 2.7 V
0.8 1.5
0.6
1.0
0.4
DNL (LSB)

DNL (LSB)
0.5
0.2
Positive DNL Positive DNL
0.0 0.0
-0.2 -0.5
Negative DNL
-0.4
Negative DNL -1.0
-0.6
-0.8 -1.5

-1.0 -2.0
0 25 50 75 100 125 150 0 10 20 30 40 50 60 70 80
Sample Rate (ksps) Sample Rate (ksps)

FIGURE 2-8: Differential Nonlinearity FIGURE 2-11: Differential Nonlinearity


(DNL) vs. Sample Rate. (DNL) vs. Sample Rate (VDD = 2.7V).

3.0 3.0
VDD = VREF = 2.7 V
2.0 2.0 FSAMPLE = 50 ksps

Positive DNL
1.0 1.0
DNL (LSB)
DNL (LSB)

Positive DNL

0.0 0.0

-1.0 Negative DNL -1.0 Negative DNL

-2.0 -2.0

-3.0 -3.0
0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
VREF (V) VREF (V)

FIGURE 2-9: Differential Nonlinearity FIGURE 2-12: Differential Nonlinearity


(DNL) vs. VREF . (DNL) vs. VREF (VDD = 2.7V).

DS21298E-page 8 © 2008 Microchip Technology Inc.


MCP3204/3208
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE, TA = +25°C.

1.0 1.0
VDD = VREF = 2.7 V
0.8 0.8
FSAMPLE = 50 ksps
0.6 0.6
0.4 0.4
DNL (LSB)

DNL (LSB)
0.2 0.2
0.0 0.0
-0.2 -0.2
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1.0 -1.0
0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096
Digital Code Digital Code

FIGURE 2-13: Differential Nonlinearity FIGURE 2-16: Differential Nonlinearity


(DNL) vs. Code (Representative Part). (DNL) vs. Code (Representative Part,
VDD = 2.7V).

1.0 1.0
0.8 0.8 VDD = VREF = 2.7 V
FSAMPLE = 50 ksps
0.6 0.6
0.4 Positive DNL 0.4 Positive DNL
DNL (LSB)

DNL (LSB)
0.2 0.2
0.0 0.0
-0.2 -0.2
-0.4 -0.4
Negative DNL Negative DNL
-0.6 -0.6
-0.8 -0.8
-1.0 -1.0
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Temperature (°C) Temperature (°C)

FIGURE 2-14: Differential Nonlinearity FIGURE 2-17: Differential Nonlinearity


(DNL) vs. Temperature. (DNL) vs. Temperature (VDD = 2.7V).

4 20
3 18
VDD = VREF = 2.7 V
16
Offset Error (LSB)

FSAMPLE = 50 ksps
Gain Error (LSB)

2
14 VDD = VREF = 5V
1 FSAMPLE = 100 ksps
12
0 10
-1 8 VDD = VREF = 2.7V
6 FSAMPLE = 50 ksps
-2 VDD = VREF = 5 V
FSAMPLE = 100 ksps 4
-3
2
-4 0
0 1 2 3 4 5 0 1 2 3 4 5
VREF (V) VREF (V)

FIGURE 2-15: Gain Error vs. VREF . FIGURE 2-18: Offset Error vs. VREF .

© 2008 Microchip Technology Inc. DS21298E-page 9


MCP3204/3208
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE, TA = +25°C.

0.2 2.0
0.0 VDD = VREF = 2.7 V 1.8
FSAMPLE = 50 ksps VDD = VREF = 5 V
-0.2 1.6

Offset Error (LSB)


Gain Error (LSB)

FSAMPLE = 100 ksps


-0.4 1.4
-0.6 1.2
-0.8 1.0
0.8 VDD = VREF = 2.7 V
-1.0
FSAMPLE = 50 ksps
-1.2 VDD = VREF = 5 V 0.6
FSAMPLE = 100 ksps
-1.4 0.4
-1.6 0.2
-1.8 0.0
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Temperature (°C) Temperature (°C)

FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-22: Offset Error vs.
Temperature.

100 100
90 VDD = VREF = 5 V VDD = VREF = 5 V
90
FSAMPLE = 100 ksps FSAMPLE = 100 ksps
80 80
70 70

SFDR (dB)
SNR (dB)

60 60
50 50 VDD = VREF = 2.7 V
FSAMPLE = 50 ksps
40 VDD = VREF = 2.7V 40
30 FSAMPLE = 50 ksps 30
20 20
10 10
0 0
1 10 100 1 10 100
Input Frequency (kHz) Input Frequency (kHz)

FIGURE 2-20: Signal-to-Noise (SNR) vs. FIGURE 2-23: Signal-to-Noise and


Input Frequency. Distortion (SINAD) vs. Input Frequency.

0
80
-10 VDD = VREF = 5 V
70 FSAMPLE = 100 ksps
-20
-30 60
VDD = VREF = 2.7V
SINAD (dB)
THD (dB)

-40 FSAMPLE = 50 ksps 50 VDD = VREF = 2.7 V


-50 40 FSAMPLE = 50 ksps
-60
30
-70
20
-80
VDD = VREF = 5V
-90 FSAMPLE = 100 ksps 10

-100 0
1 10 100 -40 -35 -30 -25 -20 -15 -10 -5 0
Input Frequency (kHz) Input Signal Level (dB)

FIGURE 2-21: Total Harmonic Distortion FIGURE 2-24: Signal-to-Noise and


(THD) vs. Input Frequency. Distortion (SINAD) vs. Input Signal Level.

DS21298E-page 10 © 2008 Microchip Technology Inc.


MCP3204/3208
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE, TA = +25°C.

12.0
12.00
11.75 11.5
11.50
11.25 11.0

ENOB (rms)
ENOB (rms)

11.00 VDD = VREF = 5 V 10.5


10.75 VDD = VREF = 2.7 V FSAMPLE =100 ksps VDD = VREF = 5 V
10.50 FSAMPLE = 50 ksps 10.0 FSAMPLE = 100 ksps
10.25
9.5
10.00
9.75 9.0 VDD = VREF = 2.7 V
9.50 FSAMPLE = 50 ksps
9.25 8.5
9.00 8.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 10 100
VREF (V) Input Frequency (kHz)

FIGURE 2-25: Effective Number of Bits FIGURE 2-28: Effective Number of Bits
(ENOB) vs. VREF. (ENOB) vs. Input Frequency.

100 0

Power Supply Rejection (dB)


VDD = VREF = 5 V
90 -10
FSAMPLE = 100 ksps
80
-20
70
SFDR (dB)

-30
60
VDD = VREF = 2.7 V -40
50
FSAMPLE = 50 ksps
40 -50
30
-60
20
-70
10
0 -80
1 10 100 1 10 100 1000 10000
Input Frequency (kHz) Ripple Frequency (kHz)

FIGURE 2-26: Spurious Free Dynamic FIGURE 2-29: Power Supply Rejection
Range (SFDR) vs. Input Frequency. (PSR) vs. Ripple Frequency.

0 0
-10 VDD = VREF = 5 V -10 VDD = VREF = 2.7 V
-20 FSAMPLE = 100 ksps -20 FSAMPLE = 50 ksps
FINPUT = 9.985 kHz -30 FINPUT = 998.76 Hz
-30
4096 points 4096 points
Amplitude (dB)

-40
Amplitude (dB)

-40
-50 -50
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
-110 -110
-120 -120
-130 -130
0 10000 20000 30000 40000 50000 0 5000 10000 15000 20000 25000
Frequency (Hz) Frequency (Hz)

FIGURE 2-27: Frequency Spectrum of FIGURE 2-30: Frequency Spectrum of


10 kHz input (Representative Part). 1 kHz input (Representative Part, VDD = 2.7V).

© 2008 Microchip Technology Inc. DS21298E-page 11


MCP3204/3208
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE, TA = +25°C.

500 100
450 VREF = VDD VREF = VDD
90
All points at FCLK = 2 MHz, except All points at FCLK = 2 MHz except
400 80
at VREF = VDD = 2.5 V, FCLK = 1 MHz at VREF = VDD = 2.5 V, FCLK = 1 MHz
350 70
IDD (µA)

300

IREF (µA)
60
250 50
200 40
150 30
100 20
50 10
0 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V) VDD (V)

FIGURE 2-31: IDD vs. VDD. FIGURE 2-34: IREF vs. VDD.

400 100
90 VDD = VREF = 5 V
350
80
300
VDD = VREF = 5 V 70
250

IREF (µA)
60
IDD (µA)

200 VDD = VREF = 2.7 V 50


40
150 VDD = VREF = 2.7 V
30
100
20
50 10
0 0
10 100 1000 10000 10 100 1000 10000
Clock Frequency (kHz) Clock Frequency (kHz)

FIGURE 2-32: IDD vs. Clock Frequency. FIGURE 2-35: IREF vs. Clock Frequency.

400 100
VDD = VREF = 5 V VDD = VREF = 5 V
350 90
FCLK = 2 MHz FCLK = 2 MHz
80
300
70
250
IDD (µA)

IREF (µA)

60
200 50
VDD = VREF = 2.7 V
150 40
FCLK = 1 MHz VDD = VREF = 2.7 V
30
100 FCLK = 1 MHz
20
50
10
0 0
-50 -25 0 25 50 75 100 -50 -25 0 25 50 75 100
Temperature (°C) Temperature (°C)

FIGURE 2-33: IDD vs. Temperature. FIGURE 2-36: IREF vs. Temperature.

DS21298E-page 12 © 2008 Microchip Technology Inc.


MCP3204/3208
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE, TA = +25°C.

80 2.0

Analog Input Leakage (nA)


VREF = CS = VDD 1.8
70
1.6
60
1.4
50
IDDS (pA)

1.2 VDD = VREF = 5 V


40 1.0 FCLK = 2 MHz

30 0.8
0.6
20
0.4
10 0.2
0 0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -50 -25 0 25 50 75 100
VDD (V) Temperature (°C)

FIGURE 2-37: IDDS vs. VDD. FIGURE 2-39: Analog Input Leakage
Current vs. Temperature.
100.00
VDD = VREF = CS = 5 V

10.00
IDDS (nA)

1.00

0.10

0.01
-50 -25 0 25 50 75 100
Temperature (°C)

FIGURE 2-38: IDDS vs. Temperature.

© 2008 Microchip Technology Inc. DS21298E-page 13


MCP3204/3208
NOTES:

DS21298E-page 14 © 2008 Microchip Technology Inc.


MCP3204/3208
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
MCP3204 MCP3208

PDIP, SOIC, Symbol Definition


PDIP, SOIC
TSSOP
1 1 CH0 Analog Input
2 2 CH1 Analog Input
3 3 CH2 Analog Input
4 4 CH3 Analog Input
— 5 CH4 Analog Input
— 6 CH5 Analog Input
— 7 CH6 Analog Input
— 8 CH7 Analog Input
7 9 DGND Digital Ground
8 10 CS/SHDN Chip Select/Shutdown Input
9 11 DIN Serial Data In
10 12 DOUT Serial Data Out
11 13 CLK Serial Clock
12 14 AGND Analog Ground
13 15 VREF Reference Voltage Input
14 16 VDD +2.7V to 5.5V Power Supply
5, 6 — NC No Connection

3.1 Digital Ground (DGND) 3.5 Serial Data Input (DIN)


Digital ground connection to internal digital circuitry. The SPI port serial data input pin is used to load
channel configuration data into the device.
3.2 Analog Ground (AGND)
Analog ground connection to internal analog circuitry. 3.6 Serial Data Output (DOUT)
3.3 Analog Inputs (CH0 - CH7) The SPI serial data output pin is used to shift out the
results of the A/D conversion. Data will always change
Analog inputs for channels 0 - 7 for the multiplexed on the falling edge of each clock as the conversion
inputs. Each pair of channels can be programmed to be takes place.
used as two independent channels in single-ended
mode or as a single pseudo-differential input, where 3.7 Chip Select/Shutdown (CS/SHDN)
one channel is IN+ and one channel is IN. See
Section 4.1 “Analog Inputs”, “Analog Inputs”, and The CS/SHDN pin is used to initiate communication
Section 5.0 “Serial communications”, “Serial Com- with the device when pulled low and will end a
munications”, for information on programming the conversion and put the device in low power standby
channel configuration. when pulled high. The CS/SHDN pin must be pulled
high between conversions.
3.4 Serial Clock (CLK)
The SPI clock pin is used to initiate a conversion and
clock out each bit of the conversion as it takes place.
See Section 6.2 “Maintaining Minimum Clock
Speed”, “Maintaining Minimum Clock Speed”, for con-
straints on clock speed.

© 2008 Microchip Technology Inc. DS21298E-page 15


MCP3204/3208
NOTES:

DS21298E-page 16 © 2008 Microchip Technology Inc.


MCP3204/3208
4.0 DEVICE OPERATION 4.2 Reference Input
The MCP3204/3208 A/D converters employ a For each device in the family, the reference input
conventional SAR architecture. With this architecture, (VREF) determines the analog input voltage range. As
a sample is acquired on an internal sample/hold the reference input is reduced, the LSB size is reduced
capacitor for 1.5 clock cycles starting on the fourth accordingly. The theoretical digital output code pro-
rising edge of the serial clock after the start bit has been duced by the A/D converter is a function of the analog
received. Following this sample time, the device uses input signal and the reference input, as shown below.
the collected charge on the internal sample/hold
capacitor to produce a serial 12-bit digital output code. EQUATION 4-1:
Conversion rates of 100 ksps are possible on the
4096 × V IN
MCP3204/3208. See Section 6.2 “Maintaining Mini- Digital Output Code = ---------------------------
mum Clock Speed”, “Maintaining Minimum Clock V REF
Speed”, for information on minimum clock rates. Where:
Communication with the device is accomplished using
VIN = analog input voltage
a 4-wire SPI-compatible interface.
VREF = reference voltage
4.1 Analog Inputs
The MCP3204/3208 devices offer the choice of using When using an external voltage reference device, the
the analog input channels configured as single-ended system designer should always refer to the
inputs or pseudo-differential pairs. The MCP3204 can manufacturer’s recommendations for circuit layout.
be configured to provide two pseudo-differential input Any instability in the operation of the reference device
pairs or four single-ended inputs, while the MCP3208 will have a direct effect on the operation of the A/D
can be configured to provide four pseudo-differential converter.
input pairs or eight single-ended inputs. Configuration
is done as part of the serial command before each
conversion begins. When used in the pseudo-
differential mode, each channel pair (i.e., CH0 and
CH1, CH2 and CH3 etc.) is programmed to be the IN+
and IN- inputs as part of the command string transmit-
ted to the device. The IN+ input can range from IN- to
(VREF + IN-). The IN- input is limited to ±100 mV from
the VSS rail. The IN- input can be used to cancel small
signal common-mode noise which is present on both
the IN+ and IN- inputs.
When operating in the pseudo-differential mode, if the
voltage level of IN+ is equal to or less than IN-, the
resultant code will be 000h. If the voltage at IN+ is equal
to or greater than {[VREF + (IN-)] - 1 LSB}, then the
output code will be FFFh. If the voltage level at IN- is
more than 1 LSB below VSS, the voltage level at the
IN+ input will have to go below VSS to see the 000h
output code. Conversely, if IN- is more than 1 LSB
above VSS, then the FFFh code will not be seen unless
the IN+ input level goes above VREF level.
For the A/D converter to meet specification, the charge
holding capacitor (CSAMPLE) must be given enough
time to acquire a 12-bit accurate voltage level during
the 1.5 clock cycle sampling period. The analog input
model is shown in Figure 4-1.
This diagram illustrates that the source impedance (RS)
adds to the internal sampling switch (RSS) impedance,
directly effecting the time that is required to charge the
capacitor (CSAMPLE). Consequently, larger source
impedances increase the offset, gain and integral
linearity errors of the conversion (see Figure 4-2).

© 2008 Microchip Technology Inc. DS21298E-page 17


MCP3204/3208

VDD
Sampling
Switch
VT = 0.6V
RSS CHx SS RS = 1 kΩ

CSAMPLE
VA CPIN ILEAKEAGE = DAC capacitance
VT = 0.6V
7 pF ±1 nA = 20 pF

VSS
Legend
VA = Signal Source Ileakage = Leakage Current At The Pin
Due To Various Junctions
Rss = Source Impedance SS = Sampling switch
CHx = Input Channel Pad Rs = Sampling switch resistor
Cpin = Input Pin Capacitance Csample = Sample/hold capacitance
Vt = Threshold Voltage

FIGURE 4-1: Analog Input Model.

2.5

VDD = 5 V
Clock Frequency (MHz)

2.0

1.5

1.0
VDD = 2.7 V

0.5

0.0
100 1000 10000

Input Resistance (Ohms)

FIGURE 4-2: Maximum Clock Frequency


vs. Input resistance (RS) to maintain less than a
0.1 LSB deviation in INL from nominal
conditions.

DS21298E-page 18 © 2008 Microchip Technology Inc.


MCP3204/3208
5.0 SERIAL COMMUNICATIONS TABLE 5-1: CONFIGURATION BITS FOR
THE MCP3204
Communication with the MCP3204/3208 devices is
accomplished using a standard SPI-compatible serial Control Bit
interface. Initiating communication with either device is Selections Input Channel
done by bringing the CS line low (see Figure 5-1). If the Configuration Selection
Single/
device was powered up with the CS pin low, it must be D2* D1 D0
Diff
brought high and back low to initiate communication.
The first clock received with CS low and DIN high will 1 X 0 0 single-ended CH0
constitute a start bit. The SGL/DIFF bit follows the start 1 X 0 1 single-ended CH1
bit and will determine if the conversion will be done
1 X 1 0 single-ended CH2
using single-ended or differential input mode. The next
three bits (D0, D1 and D2) are used to select the input 1 X 1 1 single-ended CH3
channel configuration. Table 5-1 and Table 5-2 show 0 X 0 0 differential CH0 = IN+
the configuration bits for the MCP3204 and MCP3208, CH1 = IN-
respectively. The device will begin to sample the 0 X 0 1 differential CH0 = IN-
analog input on the fourth rising edge of the clock after CH1 = IN+
the start bit has been received. The sample period will
0 X 1 0 differential CH2 = IN+
end on the falling edge of the fifth clock following the
CH3 = IN-
start bit.
0 X 1 1 differential CH2 = IN-
Once the D0 bit is input, one more clock is required to
CH3 = IN+
complete the sample and hold period (DIN is a “don’t
care” for this clock). On the falling edge of the next * D2 is a “don’t care” for MCP3204
clock, the device will output a low null bit. The next 12
clocks will output the result of the conversion with MSB TABLE 5-2: CONFIGURATION BITS FOR
first, as shown in Figure 5-1. Data is always output from THE MCP3208
the device on the falling edge of the clock. If all 12 data Control Bit
bits have been transmitted and the device continues to Selections Input Channel
receive clocks while the CS is held low, the device will
Single Configuration Selection
output the conversion result LSB first, as shown in D2 D1 D0
Figure 5-2. If more clocks are provided to the device /Diff
while CS is still low (after the LSB first data has been 1 0 0 0 single-ended CH0
transmitted), the device will clock out zeros indefinitely.
1 0 0 1 single-ended CH1
If necessary, it is possible to bring CS low and clock in
1 0 1 0 single-ended CH2
leading zeros on the DIN line before the start bit. This is
often done when dealing with microcontroller-based 1 0 1 1 single-ended CH3
SPI ports that must send 8 bits at a time. Refer to 1 1 0 0 single-ended CH4
Section 6.1 “Using the MCP3204/3208 with Micro- 1 1 0 1 single-ended CH5
controller (MCU) SPI Ports” for more details on using
1 1 1 0 single-ended CH6
the MCP3204/3208 devices with hardware SPI ports.
1 1 1 1 single-ended CH7
0 0 0 0 differential CH0 = IN+
CH1 = IN-
0 0 0 1 differential CH0 = IN-
CH1 = IN+
0 0 1 0 differential CH2 = IN+
CH3 = IN-
0 0 1 1 differential CH2 = IN-
CH3 = IN+
0 1 0 0 differential CH4 = IN+
CH5 = IN-
0 1 0 1 differential CH4 = IN-
CH5 = IN+
0 1 1 0 differential CH6 = IN+
CH7 = IN-
0 1 1 1 differential CH6 = IN-
CH7 = IN+

© 2008 Microchip Technology Inc. DS21298E-page 19


MCP3204/3208

tCYC tCYC
tCSH
CS

tSUCS
CLK

SGL/
DIN Start DIFF D2 D1 D0 Don’t Care Start SGL/
DIFF D2

HI-Z Null HI-Z


DOUT Bit B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
tCONV

tSAMPLE tDATA **

* After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output LSB
first data, followed by zeros indefinitely (see Figure 5-2 below).
** tDATA: during this time, the bias current and the comparator power down while the reference input becomes
a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros.

FIGURE 5-1: Communication with the MCP3204 or MCP3208.

tCYC

tCSH
CS
tSUCS
Power Down
CLK

Start
DIN D2 D1 D0 Don’t Care
SGL/
DIFF

HI-Z Null * HI-Z


DOUT Bit
B11B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10B11
(MSB)
tCONV tDATA **
tSAMPLE

* After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeros
indefinitely.
** tDATA: During this time, the bias circuit and the comparator power down while the reference input becomes a
high impedance node, leaving the CLK running to clock out LSB first data or zeroes.

FIGURE 5-2: Communication with MCP3204 or MCP3208 in LSB First Format.

DS21298E-page 20 © 2008 Microchip Technology Inc.


MCP3204/3208
6.0 APPLICATIONS INFORMATION As is shown in Figure 6-1, the first byte transmitted to
the A/D converter contains five leading zeros before
the start bit. Arranging the leading zeros this way
6.1 Using the MCP3204/3208 with
allows the output 12 bits to fall in positions easily
Microcontroller (MCU) SPI Ports manipulated by the MCU. The MSB is clocked out of
With most microcontroller SPI ports, it is required to the A/D converter on the falling edge of clock number
send groups of eight bits. It is also required that the 12. Once the second eight clocks have been sent to the
microcontroller SPI port be configured to clock out data device, the MCU’s receive buffer will contain three
on the falling edge of clock and latch data in on the unknown bits (the output is at high impedance for the
rising edge. Because communication with the first two clocks), the null bit and the highest order four
MCP3204/3208 devices may not need multiples of bits of the conversion. Once the third byte has been
eight clocks, it will be necessary to provide more clocks sent to the device, the receive register will contain the
than are required. This is usually done by sending lowest order eight bits of the conversion results.
‘leading zeros’ before the start bit. As an example, Employing this method ensures simpler manipulation
Figure 6-1 and Figure 6-2 illustrate how the MCP3204/ of the converted data.
3208 can be interfaced to a MCU with a hardware SPI Figure 6-2 shows the same thing in SPI Mode 1,1,
port. Figure 6-1 depicts the operation shown in SPI which requires that the clock idles in the high state. As
Mode 0,0, which requires that the SCLK from the MCU with mode 0,0, the A/D converter outputs data on the
idles in the ‘low’ state, while Figure 6-2 shows the falling edge of the clock and the MCU latches data from
similar case of SPI Mode 1,1, where the clock idles in the A/D converter in on the rising edge of the clock.
the ‘high’ state.

CS
MCU latches data from A/D
converter on rising edges of SCLK
SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Data is clocked out of A/D


converter on falling edges
SGL/
DIN Start DIFF D2 D1 DO Don’t
Don’tCare
Care

HI-Z NULL
DOUT BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

Start
MCU Transmitted Data Bit
(Aligned with falling 0 0 0 0 0 SGL/ D2
SGL/
1 DIFF D1
D1 DO X X X X X X X
edge of clock) DIFF D2 DO X X X X X X X

MCU Received Data


(Aligned with rising ? ?
? ?
? ?
? 0
0 B11 B10 B9 B8 B7 B6
B6 B5
B5 B4
B4 B3
B3 B2
B2 B1
B1 B0
B0
(Null) B11 B10 B9 B8 B7
? ? ? ? ? ? ?
edge of clock)

Data stored into MCU receive Data stored into MCU receive Data stored into MCU receive
register after transmission of first register after transmission of register after transmission of last
X = “Don’t Care” Bits 8 bits second 8 bits 8 bits

FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).

© 2008 Microchip Technology Inc. DS21298E-page 21


MCP3204/3208

CS
MCU latches data from A/D converter
on rising edges of SCLK

SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Data is clocked out of A/D
converter on falling edges
SGL/
DIN D2 D1 DO Don’t Care
Start DIFF

HI-Z NULL
DOUT BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

Start
MCU Transmitted Data Bit
(Aligned with falling 0 0 0 0 0 1 SGL/ D2 D1 DO X X X X X X X X X X X X X X
edge of clock) DIFF

MCU Received Data


(Aligned with rising 0
? ? ? ? ? ? ? ? ? ? ? (Null) B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
edge of clock)

Data stored into MCU receive Data stored into MCU receive Data stored into MCU receive
register after transmission of first register after transmission of register after transmission of last
X = “Don’t Care” Bits 8 bits second 8 bits 8 bits

FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).

6.2 Maintaining Minimum Clock Speed 6.3 Buffering/Filtering the Analog


When the MCP3204/3208 initiates the sample period,
Inputs
charge is stored on the sample capacitor. When the If the signal source for the A/D converter is not a low
sample period is complete, the device converts one bit impedance source, it will have to be buffered or inaccu-
for each clock that is received. It is important for the rate conversion results may occur (see Figure 4-2). It is
user to note that a slow clock rate will allow charge to also recommended that a filter be used to eliminate any
bleed off the sample capacitor while the conversion is signals that may be aliased back into the conversion
taking place. At 85°C (worst case condition), the part results, as is illustrated in Figure 6-3, where an op amp
will maintain proper charge on the sample capacitor for is used to drive the analog input of the MCP3204/3208.
at least 1.2 ms after the sample period has ended. This This amplifier provides a low impedance source for the
means that the time between the end of the sample converter input, and a low pass filter, which eliminates
period and the time that all 12 data bits have been unwanted high frequency noise.
clocked out must not exceed 1.2 ms (effective clock
Low-pass (anti-aliasing) filters can be designed using
frequency of 10 kHz). Failure to meet this criterion may
Microchip’s free interactive FilterLab® software. Filter-
introduce linearity errors into the conversion outside
Lab will calculate capacitor and resistor values, as well
the rated specifications. It should be noted that during
as determine the number of poles that are required for
the entire conversion cycle, the A/D converter does not
the application. For more information on filtering
require a constant clock speed or duty cycle, as long as
signals, see AN699, “Anti-Aliasing Analog Filters for
all timing specifications are met.
Data Acquisition Systems”.

DS21298E-page 22 © 2008 Microchip Technology Inc.


MCP3204/3208

VDD
10 µF
4.096V
Reference

0.1 µF 1 µF
MCP1541
1 µF

IN+ VREF
MCP3204
C1 IN-
R1 MCP601
VIN +
R2
-
C2
R4
R3

FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a second order anti-aliasing
filter for the signal being converted by the MCP3204.

6.4 Layout Considerations


VDD
When laying out a printed circuit board for use with
analog components, care should be taken to reduce Connection
noise wherever possible. A bypass capacitor should
always be used with this device, placed as close as
possible to the device pin. A bypass capacitor value of
1 µF is recommended.
Digital and analog traces should be separated as much
as possible on the board, with no traces running Device 4
Device 1
underneath the device or the bypass capacitor. Extra
precautions should be taken to keep traces with high
frequency signals (such as clock lines) as far as
possible from analog traces.
Use of an analog ground plane is recommended in Device 3
order to keep the ground potential the same for all
devices on the board. Providing VDD connections to
devices in a “star” configuration can also reduce noise
by eliminating return current paths and associated Device 2
errors (see Figure 6-4). For more information on layout
tips when using A/D converters, refer to AN688,
“Layout Tips for 12-Bit A/D converter Applications”. FIGURE 6-4: VDD traces arranged in a
‘Star’ configuration in order to reduce errors
caused by current return paths.

© 2008 Microchip Technology Inc. DS21298E-page 23


MCP3204/3208
6.5 Utilizing the Digital and Analog
Ground Pins
The MCP3204/3208 devices provide both digital and
analog ground connections to provide another means
of noise reduction. As shown in Figure 6-5, the analog
and digital circuitry is separated internal to the device.
This reduces noise from the digital portion of the device
being coupled into the analog portion of the device. The
two grounds are connected internally through the
substrate, which has a resistance of 5 -10Ω.
If no ground plane is utilized, then both grounds must
be connected to VSS on the board. If a ground plane is
available, both digital and analog ground pins should
be connected to the analog ground plane. If both an
analog and a digital ground plane are available, both
the digital and the analog ground pins should be
connected to the analog ground plane. Following these
steps will reduce the amount of digital noise from the
rest of the board being coupled into the A/D converter.

VDD

MCP3204/08

Digital Side Analog Side


-SPI Interface -Sample Cap
-Shift Register -Capacitor Array
-Control Logic -Comparator
Substrate
5 - 10Ω

DGND AGND
0.1 µF

Analog Ground Plane

FIGURE 6-5: Separation of Analog and


Digital Ground Pins.

DS21298E-page 24 © 2008 Microchip Technology Inc.


MCP3204/3208
7.0 PACKAGING INFORMATION
7.1 Package Marking Information

14-Lead PDIP (300 mil) (MCP3204) Example:

XXXXXXXXXXXXXX MCP3204-B
XXXXXXXXXXXXXX I/P e3
YYWWNNN 0819256

14-Lead SOIC (150 mil) (MCP3204) Example:

XXXXXXXXXXX MCP3204-B
XXXXXXXXXXX I/SL e3
XXXXXXXI/XXXX
YYWWNNN 0819256

14-Lead TSSOP (4.4mm)* (MCP3204) Example:

XXXXXXXX 3204-C
YYWW 0819
NNN 256

Legend: XX...X Customer-specific information


Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

© 2008 Microchip Technology Inc. DS21298E-page 25


MCP3204/3208
Package Marking Information (Continued)

16-Lead PDIP (300 mil) (MCP3208) Example:

XXXXXXXXXXXXXX MCP3208-BI/P e3
XXXXXXXXXXXXXX
YYWWNNN 0819256

16-Lead SOIC (150 mil) (MCP3208) Example:

XXXXXXXXXXXXX MCP3208-B
XXXXXXXXXXXXX I/SL e3
XXXXIXXXXXX
YYWWNNN 0819256

DS21298E-page 26 © 2008 Microchip Technology Inc.


MCP3204/3208


    
     


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DS21298E-page 32 © 2008 Microchip Technology Inc.


MCP3204/3208

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© 2008 Microchip Technology Inc. DS21298E-page 33


MCP3204/3208
NOTES:

DS21298E-page 34 © 2008 Microchip Technology Inc.


MCP3204/3208
APPENDIX A: REVISION HISTORY

Revision E (September 2008)


The following is the list of modifications:
1. Updated package outline drawings in
Section 7.0 “Packaging Information”.

Revision D (January 2007)


The following is the list of modifications:
1. Undocumented changes

Revision C (May 2002)


The following is the list of modifications:
1. Undocumented changes

Revision B (August 1999)


The following is the list of modifications:
1. Undocumented changes

Revision A (November 1998)


• Initial release of this document.

© 2008 Microchip Technology Inc. DS21298E-page 35


MCP3204/3208
NOTES:

DS21298E-page 36 © 2008 Microchip Technology Inc.


MCP3204/3208
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. –X X /XX
Examples:
Device Grade Temperature Package a) MCP3204-BI/P: ±1 LSB INL,
Range Industrial Temperature,
PDIP package.
b) MCP3204-BI/SL: ±1 LSB INL,
Device MCP3204: 4-Channel 12-Bit Serial A/D Converter
MCP3204T: 4-Channel 12-Bit Serial A/D Converter Industrial Temperature,
(Tape and Reel) SOIC package.
MCP3208: 8-Channel 12-Bit Serial A/D Converter c) MCP3204-CI/ST: ±2 LSB INL,
MCP3208T: 8-Channel 12-Bit Serial A/D Converter Industrial Temperature,
(Tape and Reel)
TSSOP package.

Grade: B = ±1 LSB INL a) MCP3208-BI/P: ±1 LSB INL,


C = ±2 LSB INL Industrial Temperature,
PDIP package.
Temperature Range I = -40°C to +85°C (Industrial) b) MCP3208-BI/SL: ±1 LSB INL,
Industrial Temperature,
SOIC package.
Package P = Plastic DIP (300 mil Body), 14-lead, 16-lead
SL = Plastic SOIC (150 mil Body), 14-lead, 16-lead
c) MCP3208-CI/ST: ±2 LSB INL,
ST = Plastic TSSOP (4.4mm), 14-lead Industrial Temperature,
TSSOP package.

© 2008 Microchip Technology Inc. DS21298E-page 37


MCP3204/3208
NOTES:

DS21298E-page 38 © 2008 Microchip Technology Inc.


Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks


applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
ensure that your application meets with your specifications.
PICSTART, rfPIC, SmartShunt and UNI/O are registered
MICROCHIP MAKES NO REPRESENTATIONS OR trademarks of Microchip Technology Incorporated in the
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions
QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology
FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard,
devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, In-Circuit Serial
hold harmless Microchip from any and all damages, claims, Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
suits, or expenses resulting from such use. No licenses are Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
conveyed, implicitly or otherwise, under any Microchip PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
intellectual property rights. PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide


headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

© 2008 Microchip Technology Inc. DS21298E-page 39


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01/02/08

DS21298E-page 40 © 2008 Microchip Technology Inc.