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1.1 Project Overview

The present project work wireless Industrial data communication on Ethernet network is
basically a security system that can monitor multiple entry points(maximum 35 with
AVR8515 microcontroller) into a building. we detect the status of doors/windows. The
allowable status are 1. Door Broke Open, 2. Window Broken, 3. Both Are Broken.The status
information is transmitted through wireless modules to a supervisory monitoring station.
In the project work, for the demonstration purpose, a door and a window was
considered for monitoring. A magnetic reed sensor detects when the door or window is
opened and a signal is sent to the interrupt pin of the microcontroller.

The microcontroller senses the interrupt and depending on the status of the flag bits,
the microcontroller sends information to the receiver through wireless module. The
microcontroller connected to the receiver analyses the information received and turns the
buzzer on and also displays corresponding message on an LCD and that data is send through
the Ethernet module (WIZ105SR) to the system.

The low-cost of this system makes it viable for ready real time application as against the
high priced solutions available today.

The required DC power supply for the proper operation of the electronic circuitry in the
demo module is derived from AC 230v 50Hz main line. This unit consists of an adapter,
rectifier and regulator circuits. The overall demo modules is simple and requires less


The major area of application of wireless Industrial data communication on Ethernet

network is industrial/home security systems. This can be used to monitor many doors and
windows of a building. Using wireless transmitter and receiver, the building can be
monitored from a distant place as well. The wireless technology can be used for a variety of
applications like monitoring hazardous places, which help to take preemptive measures.









Fig1.2 Block Diagram of Industrial Data Communication on Ethernet Network





STT-433 and STR-433 modules These are the wireless transmitter and receiver which
operates at 433MHZ, developed by SUNROM

AVR Microcontroller The AT Mega 8515 is a low power CMOS 8 bit

microcontroller based on the AVR enhanced
RISC architecture.

MAX 232 IC Port for USART It is Used for communication between the avr
With 9 Pin db Connector. microcontroller to PC.

WIZ105SR Ethernet module WIZ105SR is a gateway module between serial

device and Ethernet.It can transmit serial data to
Ethernet and vice versa.

Power Supply To design power supply of 5Volts to controller as

well to RF Modules.

Table 2.1 Hardware Requirements


Table 2.2 Software Requirements


WIN AVR Win Avr is a suite of executable ,open

source software development tools for the
Atmel AVR series of RISC microprocessors
hosted on the Windows platform. It includes
the GNU GCC compiler for C,C++..

AVR Studio The AVR Simulator is software simulatorfor

the avr architecture and devices.It
simulates the cpu,including all
instructions,interrupts and most
of the on chip I/O modules.

WIZ105SR Configuration Tool WIZ105SR Configuration Tool is used to

configure ip address.
Version 2.1.0.

EDIT PLUS EditPlus is a text editor, HTML editor and

programmer’s editor for Windows. While it can
serve as a good Notepad replacement, it also
offers many powerful features for Web page
authors and programmers.




The reed switch is an electrical switch operated by an applied magnetic field. It was invented
at Bell Telephone Laboratories in 1936 by W. B. Ellwood. It consists of a pair of contacts on
ferrous metal reeds in a hermetically sealed glass envelope. The contacts may be normally
open, closing when a magnetic field is present, or normally closed and opening when a
magnetic field is applied. The switch may be actuated by a coil, making a reed relay, or by
bringing a magnet near to the switch. Once the magnet is pulled away from the switch, the
reed switch will go back to its original position.

An example of a reed switch's application is to detect the opening of a door, when used as a
proximity switch for a burglar alarm

Wireless Magnetic Door / Window Contact Sensor

The Wireless Magnetic Door / Window Contact Sensor is a protective device that can send
notification when the opening and closure of doors and windows occurs. It is designed to
send a wireless signal to a compatible home security system when the contact between the
transmitter and corresponding magnetic sensor is broken.

Fig 3.1 Magnetic Door/Window Contact Sensor

 Magnetic contact used to monitor normally closed entry points such as doors and
 Wirelessly communicates with a compatible home security system up to 300 feet away
 Adjustable radio frequency settings and built-in technology prevent missed signals and
transmission errors.

3.1.1 Reed Switch features

 Ability to switch up to 10,000 Volts

 Ability to switch currents up to 5 Amps
 Ability to switch or carry as low as 10 nanoVolts without signal loss
 Ability to switch or carry as low as 1 femptoAmp without signal loss

 Ability to switch or carry up to 7 GigaHertz with minimal signal loss
 Isolation across the contacts up to 1015 W
 Contact resistance (on resistance) typical 50 milliOhms (mW)
 In its off state it requires no power or circuitry
 Ability to offer a latching feature
 Operate time in the 100 ms to 300 ms range
 Ability to operate over extreme temperature ranges from –55oC to 200oC
 Ability to operate in all types of environments including air, water, vacuum, oil, fuels,
and dust laden atmospheres
 Ability to withstand shocks up to 200 Gs
 Ability to withstand vibration environments of 50 Hz to 2000 Hz at up to 30 Gs
 Long life. With no wearing parts, load switching under 5 Volts at 10 mA, will operate
well into the billions of operations.

3.2 TRANSMITTER (433 MHz RF Transmitter STT-433)


The STT-433 is ideal for remote control applications where lowcost and longer range is
required. The transmitter operates from a 1.5-12V supply, making it ideal for battery-
powered applications.The transmitter employs a SAW-stabilized oscillator, ensuring accurate
frequency control for best range performance. Output power and harmonic emissions are easy
to control, making FCC and ETSI compliance easy. The manufacturing-friendly SIP style
package and low-cost make the STT-433 suitable for high volume applications.

This is the wireless transmitter which operates at 433MHZ frequency, developed by

SUNROM technologies. Theoretical range is around 100 meters.STT-433 consists of 4pins
viz., antenna, ground, data, VCC. The information to be transmitted is given to data pin of
transmitter and wireless transmission is done through antenna pin.



Fig 3.2.2 Assembled View of Transmitter(STT-433MHZ)


Fig 3.2.3 Transmitter Schematic


Fig 3.2.4 Transmitter Board


 433.92 MHz Frequency

 LOW Cost

 1.5-12V operation

 11mA current consumption at 3V

 Small size

 4 dBm output power at 3V



Table 3.2.6 STT-433 Pin Configurations



OOK(On Off Keying) modulation is a binary form of amplitude modulation. When a

logical 0 (data line low) is being sent, the transmitter is off, fully suppressing the carrier. In
this state, the transmitter current is very low, less than 1mA. When a logical 1 is being sent,

the carrier is fully on. In this state, the module current consumption is at its highest, about
11mA with a 3V power supply.

OOK is the modulation method of choice for remote control applications where power
consumption and cost are the primary factors. Because OOK transmitters draw no power
when they transmit a 0, they exhibit significantly better power consumption than FSK
OOK data rate is limited by the start-up time of the oscillator. High-Q oscillators which have
very stable center frequencies take longer to start-up than low-Q oscillators. The start-up time
of the oscillator determines the maximum data rate that the transmitter can send.

Data Rate

The oscillator start-up time is on the order of 40uSec, which limits the maximum data rate to
4.8 kbit/sec.

Typical Application

Fig 3.2.7 Typical Application for STT-433

3.3 RECIEVER (433 MHz RF Reciever STR-433)

The STR-433 is ideal for short-range remote control applications where cost is a primary
concern. The receiver module requires no external RF components except for the antenna. It
generates virtually no emissions, making FCC and ETSI approvals easy. The super
regenerative design exhibits exceptional sensitivity at a very low cost. The manufacturing-
friendly SIP style package and low-cost make the STR-433 suitable for high volume
This is the wireless transmitter which operates at 433MHZ frequency, developed by
SUNROM technologies. Theoretical range is around 100 meters.STT-433 consists of 4pins
viz., antenna, ground, data, VCC. The antenna pin of receiver receives the data and sends it to
microcontroller through data pin.


Fig 3.3.2 Assembeled View of Reciever(STR-433MHZ)

Fig 3.3.3 Reciever Schematic


Fig 3.3.4 Reciever Board

 LOW Cost

 5 volts operation

 3.5mA current drain

 No External Parts are required

 Receiver Frequency: 433.92 MHZ

 Typical sensitivity: -105dBm

 IF Frequency: 1MHz



Table 3.3.6 STR-433 Pin Configurations


Super-Regenerative AM Detection:
The STR-433 uses a super-regenerative AM detector to demodulate the incoming AM carrier.
A superregenerative detector is a gain stage with positive feedback greater than unity so that
it oscillates. An RC-time constant is included in the gain stage so that when the gain stage
oscillates, the gain will be lowered over time proportional to the RC time constant until the
oscillation eventually dies. When the oscillation dies, the current draw of the gain stage
decreases, charging the RC circuit, increasing the gain, and ultimately the oscillation starts
Data Slicer:
The data slicer converts the base-band analog signal from the super-regenerative detector to a
CMOS/TTL compatible output. Because the data slicer is AC coupled to the audio output,
there is a minimum data rate. AC coupling also limits the minimum and maximum pulse
width. Typically, data is encoded on the transmit side using pulse-width modulation (PWM)
or non-return-to-zero (NRZ).

Antenna Input:
It will support most antenna types, including printed antennas integrated directly onto the
PCB and simple single core wire of about 17cm. The performance of the different antennas
varies. Any time a trace is longer than 1/8th the wavelength of the frequency it is carrying, it
should be a 50 ohm microstrip.

Power Supply:
The STR-433 is designed to operate from a 5V power supply. It is crucial that this power
supply be very quiet. The power supply should be bypassed using a 0.1uF low-ESR ceramic

capacitor and a 4.7uF tantalum capacitor. These capacitors should be placed as close to the
power pins as possible. The STR-433 is designed for continuous duty operation. From the
time power is applied, it can take up to 750mSec for the data output to become valid

Typical Application:

Fig 3.3.7 Typical Application for STR-433



The ATmega8515 is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega128 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general purpose working
registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed in one
clock cycle. The resulting architecture is more code efficient while achieving throughputs up
to ten times faster than conventional CISC microcontrollers.

The ATmega8515 provides the following features: 128K bytes of In-System

Programmable Flash with Read-While-Write capabilities, 4K bytes EEPROM, 4K bytes
SRAM, 53 general purpose I/O lines, 32 general purpose working registers, Real Time
Counter (RTC), four flexible Timer/Counters with compare modes and PWM, 2 USARTs, a

byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential
input stage with programmable gain, programmable Watchdog Timer with Internal
Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for
accessing the On-chip Debug system and programming and six software selectable power
saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI
port, and interrupt system to continue functioning. The Power down mode saves the register
contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or
Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the
user to maintain a timer base while the rest of the device is sleeping. The ADC Noise
Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC,
to minimize switching noise during ADC conversions. In Standby mode, the
Crystal/Resonator Oscillator is running while the rest of the device is sleeping.
This allows very fast start-up combined with low power consumption. In Extended Standby
mode, both the main Oscillator and the Asynchronous Timer continue to run.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed in-system through an
SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip
Boot program running on the AVR core. The boot program can use any interface to download
the application program in the application Flash memory. Software in the Boot Flash section
will continue to run while the Application Flash section is updated, providing true Read-
While-Write operation. By combining an 8-bit RISC CPU with In-System Self-
Programmable Flash on a monolithic chip, the Atmel ATmega128 is a powerful
microcontroller that provides a highly flexible and cost effective solution to many embedded
control applications.

The ATmega8515 AVR is supported with a full suite of program and system
development tools including: C compilers, macro assemblers, program debugger/simulators,
in-circuit emulators, and evaluation kits.


->High-performance, Low-power AVR 8-bit Microcontroller

->Advanced RISC Architecture
->130 Powerful Instructions – Most Single Clock Cycle Execution

->32 x 8 General Purpose Working Registers + Peripheral Control Registers
->Fully Static Operation
-> Up to 16 MIPS Throughput at 16 MHz
->On-chip 2-cycle Multiplier

• Nonvolatile Program and Data Memories:

– 8K Bytes of In-System Reprogrammable Flash
Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– 512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 512 Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
– SPI Interface for In-System Programming
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface

• Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
– Three PWM Channels
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources

– Three Sleep Modes: Idle, Power-down and Standby
• I/O and Packages
– 35 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad ML

• Operating Voltages
– 2.7 - 5.5V for ATmega8515L
– 4.5 - 5.5V for ATmega8515

• Speed Grades
0 - 8 MHz for ATmega8515L
0 - 16 MHz for ATmega8515


Fig 3.4.3 ATMEGA8515 Pin configuration

Pin Descriptions:
VCC: Digital supply voltage

.GND: Ground.

Port A (PA7...PA0):
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit). The Port A output buffers have symmetrical drive characteristics with both high
sink and source capability. As inputs, Port A pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset
condition becomes active, even if the clock is not running. Port A also serves the functions of
various special features of the ATmega8515.

Port B (PB7...PB0):
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit). The Port B output buffers have symmetrical drive characteristics with both high
sink and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running. Port B also serves the functions of
various special features of the ATmega8515.

Port C (PC7...PC0):
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit). The Port C output buffers have symmetrical drive characteristics with both high
sink and source capability. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running. Port C also serves the functions of
special features of the ATmega8515.

Port D (PD7...PD0) :
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit). The Port D output buffers have symmetrical drive characteristics with both high
sink and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running. Port D also serves the functions of
various special features of the ATmega8515.

Port E(PE2..PE0) :
Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit). The Port E output buffers have symmetrical drive characteristics with both high
sink and source capability. As inputs, Port E pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Reset input. A low level on this pin for longer than the minimum pulse length will
generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to
generate a reset.

XTAL1: Input to the inverting Oscillator amplifier and input to the internal clock operating
XTAL2: Output from the inverting Oscillator amplifier.
3.4.4 AVR CPU CORE Introduction

This section discusses the AVR core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able to access
memories, perform calculations, control peripherals and handle interrupts. Block Diagram of the AVR Architecture:

Fig Block Diagram of the AVR Architecture Architectural Overview:

In order to maximize performance and parallelism, the AVR uses a Harvard

architecture – with separate memories and buses for program and data. Instructions in the
program memory are executed with a single level pipelining. While one instruction is being
executed, the next instruction is pre-fetched from the program memory. This concept enables
instructions to be executed in every clock cycle. The program memory is In-System
Reprogrammable Flash memory.

The fast-access Register file contains 32 x 8-bit general purpose working registers
with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)
operation. In a typical ALU operation, two operands are output from the Register file, the
operation is executed, and the result is stored back in the Register file – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for
Data Space addressing – enabling efficient address calculations. One of the these address
pointers can also be used as an address pointer for look up tables in Flash Program memory.
These added function registers are the 16-bit X-register, Y-register and Z-register, described
later in this section.

The ALU supports arithmetic and logic operations between registers or between a
constant and a register. Single register operations can also be executed in the ALU. After an
arithmetic operation, the Status Register is updated to reflect information about the result of
the operation.

Program flow is provided by conditional and unconditional jump and call instructions,
able to directly address the whole address space. Most AVR instructions have a single 16-bit
word format. Every program memory address contains a 16- or 32-bit instruction. Program
Flash memory space is divided in two sections, the Boot Program section and the Application
Program section. Both sections have dedicated Lock bits for write and read/write protection.
The SPM instruction that writes into the Application Flash Memory section must reside in the
Boot Program section. AVR ATmega 8515 Memories:

This section describes the different memories in the ATmega8515. The AVR
architecture has two main memory spaces, the Data Memory and the Program memory space.
In addition, the ATmega8515 features an EEPROM Memory for data storage. All three
memory spaces are linear and regular.

In-System Reprogrammable Flash Program memory:

The ATmega8515 contains 8K bytes of On-chip In-System Reprogrammable Flash

memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is

organized as 4K x 16. For software security, the Flash Program memory space is divided into
two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles.

TheATmega8515 Program Counter (PC) is 12 bits wide, thus addressing the 4K Program
memory locations. The operation of Boot Program section and associated Boot Lock bits for
software protection.

Fig: Flash Program Memory of ATmega8515

SRAM Data Memory:

The lower 608 Data Memory locations address the Register File, the I/O Memory, and
the internal data SRAM. The first 96 locations address the Register File and I/O Memory, and
the next 512 locations address the internal data SRAM.

An optional external data SRAM can be used with the ATmega8515. This SRAM will
occupy an area in the remaining address locations in the 64K address space. This area starts
at the address following the internal SRAM. The Register File, I/O, Extended I/O and

Internal SRAM occupies the lowest 608 bytes in normal mode, so when using 64KB (65536
bytes) of External Memory, 64928 Bytes of External Memory are available.

When the addresses accessing the SRAM memory space exceeds the internal
Datamemory locations, the external data SRAM is accessed using the same instructions as for
the internal Data memory access. When the internal data memories are accessed, the read and
write strobe pins (PD7 and PD6) are inactive during the whole access cycle. External SRAM
operation is enabled by setting the SRE bit in the MCUCR Register.

Accessing external SRAM takes one additional clock cycle per byte compared to
access of the internal SRAM. This means that the commands LD, ST, LDS, STS,LDD, STD,
PUSH, and POP take one additional clock cycle. If the Stack is placed in external SRAM,
interrupts, subroutine calls and returns take three clock cycles extra because the two-byte
Program Counter is pushed and popped, and external memory access does not take advantage
of the internal pipe-line memory access. When external SRAM interface is used with wait-
state, one-byte external access takes two, three, or four additional clock cycles for one, two,
and three wait-states respectively. Interrupts, subroutine calls and returns will need five,
seven, or nine clock cycles more than specified in the instruction set manual for one, two, and
three wait-states.

The five different addressing modes for the Data memory cover: Direct, Indirect with
Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the
Register File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space. The Indirect with Displacement
mode reaches 63 address locations from the base address given by the Y- or Z-register. When
using register indirect addressing modes with automatic pre-decrement and post increment,
the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, and the 512 bytes of
internal data SRAM in the ATmega8515 are all accessible through all these addressing

Fig RAM Organization of ATmega8515



WIZ105SR is a gateway module between serial device and Ethernet. It can transmit
serial data to Ethernet and vice versa. With WIZ105SR, We can connect the serial device
with Ethernet via WIZ105SR provides interface quite easier and shorten our development
periodto obtain more gains.
This provide full functional configuration tools for WIZ105SR. We can set
WIZ105SR upon our needs by using serial configuration command when WIZ105SR is in

serial configuration mode or using provided configuration tool via Ethernet to make
WIZ105SR embedded in our products well.


 High speed Serial-to-Ethernet gateway module with an RJ-45 jack

 High stability and reliability Ethernet connection solution
 10/100Mbps Ethernet interface supported with full hardwired TCP/IP stack
chip W5100
 Up to 230Kbps serial communication interface
 Serial configuration commands support
 Simple command frame format
 Comprehensive & readable command set for network and serial settings
 On-site configuration without PC
 Powerful remote configuration tool
 RoHS compliant


WIZ105SR Module:

WIZ105SR uses a high performance 8051 compatible microcontroller which feathers

62K in chip Flash, 16K in chip SRAM and 2K EEPROM. WIZ105SR feathers our fast
hardwired TCP/IP stack chip W5100 and most of TCP/IP protocols such as TCP, UDP, IP,
ARP, ICMP, IGMP, PPPoE and Ethernet MAC are all supported. 10Mbps and 100Mbps
Ethernet are all supported and one standard Ethernet Jack is mounted in WIZ105SR. One
serial port is provided in WIZ105SR via 12-pin connector which feathers standard RS-232
specification. WIZ105SR can be powered by a DC 3.3V power supply with at least 200mA
current supply. The detailed specifications are listed in below Table

Table WIZ105SR Module Specification
Connector Pin Assignment:

WIZ105SR provides an external connector to connect it with your application board. The pin
assignment and definition of the connector are introduced in Figure.1 and the specification of
each pin is described in below Table.

Figure WIZ105SR Connector Pin Assignment and Definition

Table Pin Assignment

RJ-45 Pin Assignment:

The pin assignment of Ethernet Jack RJ-45 is described in Figure 2, and description of each
pin is introduced in below Table.

Fig Pin Assignment of RJ-45 in WIZ105SR

Table Pin Definition of RJ-4


This chapter describes the configuration steps of WIZ105SR. The following listed items
which are included in your WIZ105SR-EVB package will be required in configuration.
Power Adapter (included in the WIZ105SR-EVB package)
Serial and Ethernet Cable (included in the of WIZ105SR-EVB package)
A computer with Network Interface Card ( NIC) and/or one RS232 serial port
If you have prepared those things, the configuration of WIZ105SR can be getting started.
The board connection steps are introduced in section 4.2.1

4.2.1 Hardware Installation Procedure

The following steps are required while to set up the configuration environment for
WIZ105SR and the connection diagram is shown in Figure

Fig 4.2.1 WIZ105SR Configuration

STEP 1: Connect the WIZ105SR module to the test board by using the 12pin cable.
STEP 2: Connect the 3.3V DC power line to the power jack of the test board.
STEP 3: Use the RJ45 Ethernet cable in order to connect the module to an Ethernet
STEP 4: Use the serial data cable to connect the test board to a serial device.

4.2.2 Network Configuration

Fig 4.2.2. Configuration Tool (Network Config)

Version : Displays firmware version.

Enable Serial Debug Mode : If this mode is checked, you can monitor the status module
and socket message (listen OK, connect fail etc.) through serial terminal. If Debug mode is
on, debug message can cause abnormal operation of the serial device. Therefore, just use this
mode only for Debug mode.
Board List : If you click “Search” button, all the MAC addresses on a same subnet, will be
IP Configuration Method: Select IP setting mode, you can select one of Static, DHCP,
PPPoE mode.

Static: “Static” is option for setting WIZ105SR IP with static IP address. Firstly, select MAC
address which you wanted to set as static IP in the ‘board list’. Then “Local IP, Subnet,
Hardwired Internet Connectivity Wizard (WIZnet, Inc.)
Gateway box will be enabled. Input Static IP address and click “setting” button. Then set the
IP address as you wanted. (PPPoE ID, Password box is disabled)

DHCP: Set this option to use DHCP mode. Firstly, check ‘DHCP’ and click ‘Setting’ button.
If IP address is successfully acquired from DHCP server, the MAC address will be displayed
on the configuration window. (It takes some time to acquire IP address from DHCP server)
When a module on the board list is selected, IP address, Subnet mask and Gateway are
displayed. If module could not acquire network information from DHCP server, IP address,
Gateway Address and Subnet mask will be initialized to

PPPoE : WIZ105SR supports PPPoE for ADSL user. When you select PPPoE at the “IP
Configuration Method”, PPPoE ID & Password box is enabled.
1. To set PPPoE, connect PC to WIZ105SR directly and execute Configuration Tool program
on PC. (Configuration Tool Version should be 2.1 or above)
2. Select ‘PPPoE’ of the “IP Configuration Method” tab and input ID & Password.
3. Click “setting” button to apply.
4. Connect Module to ADSL Line.
5. If “Enable Serial Debug Mode” is selected, you can see PPPoE access status via serial

Local IP/Port : WIZ105SR’s IP address and Port number for network connection
Subnet : WIZ105SR’s subnet mask
Gateway : WIZ105SR’s Gateway address
PPPoE ID/Password : If you select ‘PPPoE’ mode, input ID/Password which you received
from ISP company.
Server IP/Port : When WIZ105SR is set as “Client mode” or Mixed mode”, server IP and
port should be set. WIZ105SR attempts to connect this IP address.
Network mode:
client/server/mixed : This is to select the communication method based on TCP. TCP is the
protocol to establish the connection before data communication, but UDP just processes the
data communication without connection establishment.

The Network mode of WIZ105SR can be divided into TCP Server, TCP Client and Mixed
mode according to the connection establishing method. At the TCP server mode,
WIZ105SR operates as server on the process of connection, and waits for the connection trial
from the client. WIZ105SR operates as client at the TCP Client mode on the process of
connection, and tries to connect to the server’s IP and Port. Mixed modes supports both of
Server and Client. The communication process of each mode is as below.

TCP server mode Communication

Fig42.2.1. TCP Server mode

At the TCP Server mode, WIZ105SR waits for the connection requests. TCP Server mode
can be useful when the monitoring center tries to connect to the device (where WIZ105SR is
installed) in order to check the status or provide the commands. In normal time WIZ105SR is
on the waiting status, and if there is any connection request (SYN) from the monitoring
center, the connection is established (ESTABLISH), and data communication is processed
(Data Transanction). Finally connection is closed (FIN).

In order to operate this mode, Local IP, Subnet, Gateway Address and Local Port Number
should be configured first.
As illustrated in the above figure, data transmission proceeds as follows,
1. The host connects to the WIZ105SR which is configured as TCP Server mode.

2. As the connection is established, data can be transmitted in both directions – from the host
to the WIZ105SR, and from the WIZ105SR to the host.

TCP client mode Communication

Fig . TCP Client mode

If WIZ105SR is set as TCP Client, it tries to establish connection to the server.

To operate this mode, Local IP, Subnet, Gateway Address, Server IP, and Server port number
should be set. If server IP had domain name, use DNS function.
In TCP Client mode, WIZ105SR can actively establish a TCP connection to a host computer
when power is supplied.
As illustrated in the above figure, data transmission proceeds as follows:
1. As power is supplied, WIZ105SR board operating as TCP client mode actively establishes
a connection to the server.
2. If the connection is complete, data can be transmitted in both directions – from the host
to the WIZ105SR and from WIZ105SR to the host.

4.2.3 Serial configuration

Fig 4.2.3. Configuration Tool (Serial Config.)

Serial Configuration value of selected module is displayed.In order to change the serial
configuration of WIZ105SR, this menu can be used.
Option configuration

Fig4.2.3.1. Configuration Tool (Option Config.)

Fig Operation Mode for Password Setting
Data Transmission
Run terminal emulator program (e.g. Hyper terminal) on Test PC. Set the baud rate as the
same value of WIZ105SR.

Fig Serial Terminal Program configuration

Execute another Hyper terminal and set the IP address and port number.

Type some character on the serial Hyper terminal screen. In this example, “01234567890”
is entered. Make sure this data is shown on the Network Hyper terminal window. (Serial to

Fig Received Data by Network Terminal Program




Some early telegraph schemes used variable-length pulses and rotating clockwork
mechanisms to transmit alphabetic characters. The first UART-like devices (with fixed-
length pulses) were rotating mechanical switches (commutators). These sent 5-bit Baudot
codes for mechanical teletypewriters, and replaced morse code. Later, ASCII required a
seven bit code. When IBM built computers in the early 1960s with 8-bit characters, it became
customary to store the ASCII code in 8 bits.

The Universal Asynchronous Receiver/Transmitter (UART) controller is the key component

of the serial communications subsystem of a computer. The UART takes bytes of data and
transmits the individual bits in a sequential fashion. At the destination, a second UART re-
assembles the bits into complete bytes.

Serial transmission is commonly used with modems and for non-networked communication
between computers, terminals and other devices.

There are two primary forms of serial transmission: Synchronous and Asynchronous.
Depending on the modes that are supported by the hardware, the name of the communication
sub-system will usually include a A if it supports Asynchronous communications, and a S if it
supports Synchronous communications. Both forms are described below.

Some common acronyms are:

UART Universal Asynchronous Receiver/Transmitter

USART Universal Synchronous-Asynchronous Receiver/Transmitter

5.1.2 Synchronous Serial Transmission

Synchronous serial transmission requires that the sender and receiver share a clock
with one another, or that the sender provide a strobe or other timing signal so that the receiver
knows when to “read” the next bit of the data. In most forms of serial Synchronous
communication, if there is no data available at a given instant to transmit, a fill character must
be sent instead so that data is always being transmitted. Synchronous communication is
usually more efficient because only data bits are transmitted between sender and receiver, and

synchronous communication can be more costly if extra wiring and circuits are required to
share a clock signal between the sender and receiver.

A form of Synchronous transmission is used with printers and fixed disk devices in
that the data is sent on one set of wires while a clock or strobe is sent on a different wire.
Printers and fixed disk devices are not normally serial devices because most fixed disk
interface standards send an entire word of data for each clock or strobe signal by using a
separate wire for each bit of the word. In the PC industry, these are known as Parallel

The standard serial communications hardware in the PC does not support Synchronous
operations. This mode is described here for comparison purposes only.

5.1.3 Asynchronous Serial Transmission

Asynchronous transmission allows data to be transmitted without the sender having to

send a clock signal to the receiver. Instead, the sender and receiver must agree on timing
parameters in advance and special bits are added to each word which are used to synchronize
the sending and receiving units.

When a word is given to the UART for Asynchronous transmissions, a bit called the
"Start Bit" is added to the beginning of each word that is to be transmitted. The Start Bit is
used to alert the receiver that a word of data is about to be sent, and to force the clock in the
receiver into synchronization with the clock in the transmitter. These two clocks must be
accurate enough to not have the frequency drift by more than 10% during the transmission of
the remaining bits in the word. (This requirement was set in the days of mechanical
teleprinters and is easily met by modern electronic equipment.)

After the Start Bit, the individual bits of the word of data are sent, with the Least
Significant Bit (LSB) being sent first. Each bit in the transmission is transmitted for exactly
the same amount of time as all of the other bits, and the receiver “looks” at the wire at
approximately halfway through the period assigned to each bit to determine if the bit is a 1 or
a 0. For example, if it takes two seconds to send each bit, the receiver will examine the signal
to determine if it is a 1 or a 0 after one second has passed, then it will wait two seconds and
then examine the value of the next bit, and so on.

The sender does not know when the receiver has “looked” at the value of the bit. The sender
only knows when the clock says to begin transmitting the next bit of the word.

When the entire data word has been sent, the transmitter may add a Parity Bit that the
transmitter generates. The Parity Bit may be used by the receiver to perform simple error
checking. Then at least one Stop Bit is sent by the transmitter.

When the receiver has received all of the bits in the data word, it may check for the
Parity Bits (both sender and receiver must agree on whether a Parity Bit is to be used), and
then the receiver looks for a Stop Bit. If the Stop Bit does not appear when it is supposed to,
the UART considers the entire word to be garbled and will report a Framing Error to the host
processor when the data word is read. The usual cause of a Framing Error is that the sender
and receiver clocks were not running at the same speed, or that the signal was interrupted.

Regardless of whether the data was received correctly or not, the UART automatically
discards the Start, Parity and Stop bits. If the sender and receiver are configured identically,
these bits are not passed to the host.

If another word is ready for transmission, the Start Bit for the new word can be sent as soon
as the Stop Bit for the previous word has been sent.

Because asynchronous data is “self synchronizing”, if there is no data to transmit, the

transmission line can be idle.

5.1.4 USART ON AVR (ATMega 8515)


USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter
(USART) is a highly flexible serial communication device. The main features are:
• Full Duplex Operation (Independent Serial Receive and Transmit Registers)
• Asynchronous or Synchronous Operation
• Master or Slave Clocked Synchronous Operation
• High Resolution Baud Rate Generator
• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
• Odd or Even Parity Generation and Parity Check Supported by Hardware
• Data Overrun Detection
• Framing Error Detection
• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

• Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete
• Multi-processor Communication Mode
• Double Speed Asynchronous Communication Mode

5.1.5 USART Block Diagram

Fig 5.1.5 Usart Block Diagram

The dashed boxes in the block diagram separate the three main parts of the USART (listed
from the top): Clock Generator, Transmitter, and Receiver. Control registers are shared by all
units. The clock generation logic consists of synchronization logic for external clock input
used by synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock)
pin is only used by Synchronous Transfer mode. The Transmitter consists of a single write
buffer, a serial Shift Register, parity generator and control logic for handling different serial
frame formats. The write buffer allows a continuous transfer of data without any delay
between frames. The Receiver is the most complex part of the USART module due to its
clock and data recovery units. The recovery units are used for asynchronous data reception.
In addition to the recovery units, the receiver includes a parity checker, control logic, a Shift
Register and a two level receive buffer (UDR). The receiver supports the same frame formats
as the Transmitter, and can detect frame error, data overrun and parity errors.

Clock Generation
The clock generation logic generates the base clock for the transmitter and receiver. The
USART supports four modes of clock operation: Normal Asynchronous, Double Speed
Asynchronous, Master Synchronous, and Slave Synchronous mode. The UMSEL bit in
USART Control and Status Register C (UCSRC) selects between asynchronous and
synchronous operation. Double speed (Asynchronous mode only) is controlled by the U2X
found in the UCSRA Register. When using Synchronous mode (UMSEL = 1), the Data
Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is
internal (Master mode) or external (Slave mode). The XCK pin is only active when using
Synchronous mode.

Internal Clock Generation –The Baud Rate Generator

Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The USART Baud Rate Register (UBRR) and the down-counter connected to it
function as a programmable prescaler or baud rate generator. The down-counter, running at
system clock (fosc), is loaded with the UBRR value each time the counter has counted down
to zero or when the UBRRL Register is written. A clock is generated each time the counter
reaches zero. This clock is the baud rate generator clock output (= fosc/(UBRR+1)). The
transmitter divides the baud rate generator clock output by 2, 8, or 16 depending on mode.
The baud rate generator output is used directly by the receiver’s clock and data recovery

units. However, the recovery units use a state machine that uses 2, 8, or 16 states depending
on mode set by the state of the UMSEL, U2X and DDR_XCK bits.
Table below contains equations for calculating the baud rate (in bits per second) and for
calculating the UBRR value for each mode of operation using an internally generated
clock source.

Table 5.1.6 Equation for Baud rate Setting

BAUD Baud rate (in bits per second, bps)
fOSC System Oscillator clock frequency
UBRR Contents of the UBRRH and UBRRL Registers

5.1.7 Frame Formats

A serial frame is defined to be one character of data bits with synchronization bits (start and
stop bits), and optionally a parity bit for error checking. The USART accepts all 30
combinations of the following as valid frame formats:
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
A frame starts with the start bit followed by the least significant data bit. Then the next data
bits, up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the
parity bit is inserted after the data bits, before the stop bits. When a completeframe is
transmitted, it can be directly followed by a new frame, or the communication line can be set
to an idle (high) state. Figure 5.2 illustrates the possible combinations of the frame formats.
Bits inside brackets are optional.

Possible Combinations Of Frame Format:

Fig 5.1.7 Frame Format

St Start bit, always low.
(n) Data bits (0 to 8).
P Parity bit. Can be odd or even.
Sp Stop bit, always high.

IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high.
The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in
UCSRB and UCSRC. The receiver and transmitter use the same setting. Note that changing
the setting of any of these bits will corrupt all ongoing communication for both
the receiver and transmitter.
The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame.
The USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selection
between one or two stop bits is done by the USART Stop Bit Select (USBS) bit. The receiver
ignores the second stop bit. An FE (Frame Error) will therefore only be detected in the cases
where the first stop bit is zero.
















Fig 6.1 Project Flow Chart





/ * RF transmission routine for 433MHz RF transmitter.

Transmit sequence 0xaa ,address, data,check sum - sequence 0xaa is the start character.
Data pin of RF transmitter connected to TX pin (PD1) of UART0 in Atmega8515
Transmission is done at a baud rate of 1200 bps .Here, int is generated when window
or door is open detected thru int0 and int1, when int occurs , send appropriate code on tx
ex: when normal send 'n'; door open send 'd' and window open send 'w' */
#include <avr/io.h>

#include <avr/delay.h>
int i;
unsigned static volatile char intr0,intr1;
unsigned char address,data;
PORTB = 0X10;
GICR=0XC0; //int 0 and 1 are enabled
MCUCR=0X0f; // for falling edge put 0x0A:: for rising edge put 0x0f
//EMCUCR=0X01;// ck this???
UBRRL=63; // for baud rate of 1200 UBRR value = 575=>512+63
UCSRB=0X08; //only tx is enabled
UCSRC=0X86; // 8 bit data
UDR= address; // address


UDR= 'N'; // address
else if(intr0==0&&intr1==1)
else if(intr0==1&&intr1==0)
UDR= 0xaa; // start character


UDR= address; // address

while(!(UCSRA && 0X20));

UDR=data; //data

UDR= address + data; // check_sum


PORTB = 0X55;
//send code on uart
intr0=1; //For Window

PORTB = 0X0f;
intr1=1; //For Door

// send code on uart


/* Receive routine for 433 MHz RF receiver
Baud Rate = 1200 bps
Data pin of RF receiver connected to RX (PD0) of UART0 of ATmega8515
initially all leds on portb are OXFF. if start, addr and checksum are correct and data
received is 'A' and PORTB leds are thrown 0x50 :- all lower nibble leds and alternate leds in
upper nibble will glow LEDs connected to PORTB */
#include <avr/io.h>
#include <avr/pgmspace.h>
#include <string.h>
#include <avr/delay.h>

#define sbi(ADDR,BIT) ADDR = (ADDR | (1<<BIT))

#define cbi(ADDR,BIT) ADDR = (ADDR & ~(1<<BIT))
void lcd_init();
void lcd_cmd(unsigned char);
void lcd_data(unsigned char);
void toggle();
void display(unsigned char *);
void delay();
unsigned char data1;


unsigned char start,address,data,chksum;

unsigned char *door1, *window1 , *normal1,*both1;

normal1 = PSTR("normal");
door1 = PSTR("door broke open");
window1 =PSTR(" window broken");
both1=PSTR("both are broken");

UBRRL=63; // for baud rate of 1200 UBRR value = 575 = 512 + 63
UCSRB=0X10; //only rx is enabled
UCSRC=0X86; // 8-bit data

DDRA = 0xFF;
DDRC = 0xFF;

DDRB = 0XFF; // for LEDs

UDR = 0;
start = UDR;
PORTB = start;
if(start == 0xaa)
UDR = 0;
address = UDR;

UDR = 0;
data = UDR;

UDR = 0;
chksum = UDR;

if(address == 0x86)

if(chksum == address+data)

if(data == 'W')

else if(data=='D')

// delay();
else if(data=='B')
else if(data=='N')


else break;

}//end of main
// End of the program
void lcd_init()
}//end lcd_init

void lcd_cmd(unsigned char c)
PORTC = c;
cbi(PORTA,0); //rs = 0
cbi(PORTA,1); //rw = 0
sbi(PORTA,2); //en = 1
cbi(PORTA,2); //en = 0

}//end lcd_cmd

void lcd_data(unsigned char d)


PORTC = d;
sbi(PORTA,0); //rs = 1
cbi(PORTA,1); //rw = 0
sbi(PORTA,2); //en = 1
cbi(PORTA,2); //en = 0

void delay()
/*int k,l;

void toggle()
sbi(PORTD,3); //send a low and high signal
cbi(PORTD,3); //clear the bit

void display(unsigned char *str)

unsigned char i;
// _delay_ms(100);

for(i=0;pgm_read_byte(&str[i]) != '\0';i++)

}//end display



Option Explicit
Dim iSockets As Integer
'Dim sItemData(3) As String
Dim stat As String

Dim sServerMsg As String

Dim i As Integer
Dim sRequestID As String

Private Sub Form_Load()

lblHostID.Caption = Socket(0).LocalHostName
lblAddress.Caption = Socket(0).LocalIP
Socket(0).LocalPort = 5000
sServerMsg = "Listening to port: " & Socket(0).LocalPort
List1.AddItem (sServerMsg)

End Sub

Private Sub socket_Close(Index As Integer)

sServerMsg = "Connection closed: " & Socket(Index).RemoteHostIP
List1.AddItem (sServerMsg)
Unload Socket(Index)

iSockets = iSockets - 1
lblConnections.Caption = iSockets

End Sub

Private Sub socket_ConnectionRequest(Index As Integer, ByVal requestID As Long)

sServerMsg = "Connection request id " & requestID & " from " &
If Index = 0 Then
List1.AddItem (sServerMsg)
sRequestID = requestID
iSockets = iSockets + 1
lblConnections.Caption = iSockets
Load Socket(iSockets)
Socket(iSockets).LocalPort = 5000
Socket(iSockets).Accept requestID
End If

End Sub
Private Sub socket_DataArrival(Index As Integer, ByVal bytesTotal As Long)

Dim sItemData1 As String

Dim strData As String

Dim strOutData As String
Dim strConnect As String

Socket(Index).GetData stat, vbString

'i = i + 1
'If i < 3 Then

'Exit Sub
'End If
'i = 0
' get data from client
'Socket(Index).GetData sItemData1, vbString
'Socket(Index).GetData sItemData2, vbString
'Socket(Index).GetData sItemData3, vbString

'sServerMsg = "Received: " & sItemData & " from " & Socket(Index).RemoteHostIP & "("
& sRequestID & ")"

If stat = "d" Then

sItemData1 = "Door broke open"

ElseIf stat = "w" Then

sItemData1 = "window broken"

ElseIf stat = "b" Then

sItemData1 = "both are broken"

End If

List1.AddItem (sItemData1)

'strConnect = "Provider=Microsoft.Jet.OLEDB.4.0;Data Source=D:\students.mdb;Persist

Security Info=False"
Dim strPath As String

'Change the database path in the text file

Dim fso As New FileSystemObject, txtfile, _
fil1 As File, ts As TextStream

Set fil1 = fso.GetFile("path.txt")

' Read the contents of the file.
Set ts = fil1.OpenAsTextStream(ForReading)
strPath = ts.ReadLine
Set fso = Nothing

strConnect = "Provider=Microsoft.Jet.OLEDB.4.0;" & _

"Persist Security Info=False;Data Source=" & strPath & _
"; Mode=Read|Write"

Dim rs As New ADODB.Recordset

' Get clients request from database

strData = "SNo = '" & i & "'"

rs.Open "select * from door_status", strConnect, adOpenKeyset, adLockOptimistic

rs.Find strData
'strOutData = rs.Fields("Name")

rs!Status = sItemData1
rs!Time = Time$

'send data to client

'sServerMsg = "Sending: " & strOutData & " to " & Socket(Index).RemoteHostIP
'List1.AddItem (sServerMsg)
'Socket(Index).SendData strOutData

End Sub


Option Explicit

Private Sub cmdClose_Click()

shpGo.Visible = False
shpWait.Visible = False
shpError.Visible = True
End Sub

Private Sub cmdConnect_Click()

Winsock1.RemoteHost = "" 'Change this to host ip
Winsock1.RemotePort = 5000
shpGo.Visible = True
End Sub

Private Sub go_Click()

If Winsock1.State = sckConnected Then
Winsock1.SendData txtItem.Text
shpGo.Visible = True
Label3.Caption = "Sending Data"
shpGo.Visible = False
shpWait.Visible = False
shpError.Visible = True
Label3.Caption = "Not currently connected to host"
End If

End Sub

Private Sub Winsock1_DataArrival(ByVal bytesTotal As Long)

Dim sData As String
Winsock1.GetData sData, vbString
'Label1.Caption = sData
'txtPrice.Text = sData
Label3.Caption = "Received Data"
shpGo.Visible = True
shpWait.Visible = False
shpError.Visible = False
End Sub

Private Sub Winsock1_SendComplete()

Label3.Caption = "Completed Data Transmission"
End Sub



Fig 8.1: Programming in Avr Studio.

Fig 8.2: Implimentation on Avr Boards with RF Modules

Fig 8.3 : Output as WINDOW BROKEN ON LCD

Fig 8.4 : Output as DOOR BROKE OPEN ON LCD

Fig 8.5 : Output as BOTH ARE BROKEN ON LCD

Fig 8.6: Data sent Through Ethernet Module to System

Fig 8.7: Connection success from Client (Ethernet) when Server is run.

Fig 8.8 : Data updated in the system with Time.


This project gives an insight into implementation of wireless Industrial data communication
on Ethernet network. is basically a security system that can monitor multiple entry
points(maximum 35 with AVR8515 microcontroller) into a building. we detect the status of
doors/windows. The allowable status are 1. Door Broke Open, 2. Window Broken, 3. Both
Are Broken.The status information is transmitted through wireless modules to a supervisory
monitoring station.

The microcontroller senses the interrupt and depending on the status of the flag bits,
the microcontroller sends information to the receiver through wireless module. The
microcontroller connected to the receiver analyses the information received and turns the
buzzer on and also displays corresponding message on an LCD and that data is send through
the Ethernet module (WIZ105SR) to the system.

The low-cost of this system makes it viable for ready real time application as against the high
priced solutions available today.

With this technology learnt we can design many applications based on RF Modules like
 Open door detection in Industries.
 Home security systems
 Monitoring hazardous places etc


The present project can be extended to a full fledged home automation system by
increasing the number of monitoring doors and windows. Further more, powerful transmitter
and receivers can be used to wirelessly transmit the information over larger distances. The
data being wirelessly transmitted can be encrypted to prevent hackers from entering the
system and thus increase the security manifold.


Programming and Customizing the AVR Microcontroller by Dhananjay V. Gadre

AVR: An Introductory Course by John Morton.

Datasheet of the STT-433

1. Datasheet of the STR-433

2. Web site of Atmel with information about AVR ATmega8515

3. Datasheet of the Ethernet Module WIZ105SR