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Ryerson Polytechnic University

Department of Electrical and Computer Engineering

COE 328 – Digital Systems

Lab 4 – Scanning Encoder 20 marks (1 Week)

Due Date: Week 9

1 Objectives:

 To construct a hexadecimal keyboard encoding system using PAL

2 Pre-Lab Preparation

The ultimate approach in implementing digital circuits is to use programmable devices as much as
possible, thereby reducing time and cost. Currently for this lab, we use GAL16V8 chips. To illustrate the
power of this approach we will do the hex keypad scanning decoder, using only two GAL chips pro-
grammed for PAL16V8 configuration.
Recalling the PAL16V8 configuration has up to 16 input lines and up to 8 D-FF elements, we pro-
ceed to partition the circuit on Figure 1 into two blocks. The first block consists of the 4-bit counter, the
4-bit buffer, and all necessary interconnections between these two modules. This block fits nicely into
the capability of a single PAL16V8 chip, which has the required 8 flip-flops. The second block consists
of the remaining combinational circuits: the 2-bit decoder, the 4-to-1 MUX and the necessary intercon-

Figure 1

The PALASM data files of these two chips are listed below:

The entire design procedure is listed below:

 Partition the circuit into modules suitable for PAL implementation (see Figure 2).
 Create each PAL data file according to the result of each partition.
 Run PALASM: compile each data file successively and generate the corresponding JEDEC file

 Program your PALs.

Figure 2

In the PAL, an output may be designated a logical combination of inputs by the simple use of the
equal sign (simple mode). Refer again to the example on page 4 of lab1.
If, on the other hand, an output is to be registered, i.e. stored as a D flip-flop output, whose input is a
logical combination of various inputs, then the equal sign is replaced by the : = symbol. A simple D flip-
flop would be represented as Qn : = Dn and one with a synchronous active high CLEAR would be repre-
sented by Qn : = Dn*/CLEAR. When at least one output is registered, pin 1 becomes the clock input,
CLOCK, and pin 11 becomes an active low output enable, /OE, (registered mode).
1) This circuit in Figure 1 implements the keypad pattern given in example No. 1 on page 3. You
are asked to modify this circuit to achieve the keypad pattern that is assigned to you from the
group on pages 6 & 7. The first modification is to be done on Figure 3, where you assume the
circuit consists of discrete TTL components. The second method to achieve this modification is
when PALs are used as discussed above. Here modification is done by altering the decoder and
multiplexer equations. For example, in example No. 1, CO was to be active when both L0 and
L1 were LOW so the equation for CO was CO = /Ll*/L0. In example No.7, CO is to be active
when L3 and L2 are both HIGH, giving the equation CO = L3*L2. See the Keypad Experiment -
help file following.
2) Show the logic equation for the 4 to 1 Multiplexer circuit.
3) Draw the schematic diagram for the Multiplexer circuit.
4) Show the logic equations for the Decoder circuit.
5) Draw the schematic diagram for the Decoder circuit.
6) Prepare a lab4a.pds file for the counter-buffer function. (See instructions for using PALS at the
end of Project 1). You need only modify the file, which will be made available to you.
7) Prepare a lab4b.pds file for the decoder-multiplexer function. You will have to modify the given
decoder and multiplexer equations to accommodate your keypad pattern.

Figure 3. Hexadecimal Scanning Encoder Schematic

3 Procedure

Show results of part 3 to your instructor. See examples following these lab notes.
1) Use PALASM to compile your lab4x.pds files. This process will create files lab4x.hst and
lab4x.jed. Program your PALS.
2) Use a 1 kHz clock to drive your circuit.
3) Demonstrate it to your instructor showing the desired keypad configuration.

Figure 4. Keyboard

Figure 5. Assigned Keypad Configurations


Figure 6. Assigned Keypad Configurations


Keypad Experiment - help file

R. W. Solenka


A guide to describe the design of a PAL interface circuit to read an assigned keypad configuration
in order to determine which key has been pressed. The keypad consists of a matrix of 16 switches (0 -> F
keys) and each key when pressed makes a connection between a row and a column on the keypad.


The counter output (Q0 – Q3 PAL #1) addresses each row and column of a keypad in sequence.
When a key is pressed and "matches" the counter output, a LOW level from a column output (/CO - /C3,
PAL #2) is connected to an appropriate row input (I0 - I3, PAL #2). A control signal from PAL #2 (Z=0)
then stops the counter and the count (Q0 – Q3) is displayed on the LEDS. Releasing the pressed key en-
ables the counter to resume counting.


The connections between the counter (PAL #1) and the scanner (PAL #2) are common for all key-
pad configurations. However the design equations for PAL #2 are dependent on the keypad configuration
used. The assigned HEX keypad is converted into binary notation to facilitate the determination of the
PAL #2 design equations.


 Odd/Even Keypad
 Counter output Q3Q2QlQ0

Figure 7: Keypad Layout



Refer to the following PALASM “.pds” file.

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The design method described, using a PAL device as a keypad interface circuit, can be applied to a
keypad of any configuration, random or otherwise.


1. Using the binary notation for the keypad, express the variables CN and RN in terms of the coun-
ter outputs ((Q3 – Q0) as sum-of-products expressions.
2. By inspection or with the aid of a Karnaugh map or Boolean algebra, simplify the SOP expres-
3. Alternately, use the unsimplified SOP expressions for CN and RN in the PALASM design equa-
tions. PALASM uses the Quine-McCluskey method to simplify the expressions.


From the design example on page 8:

NOTE: If a particular keypad is used with a PAL interface circuit designed for a different
keypad, the result can be considered as a "scrambled" or encoded output.