DEPARTAMENTO DE INGENIERÍA ELÉCTRICA Y ELECTRÓNICA

–UNIVERSIDAD NACIONAL DE COLOMBIA

TALLER DE ELECTRÓNICA DIGITAL II
DOCENTE: DIEGO ALEXANDER TIBADUIZA BURGOS

1. Para las siguientes instrucciones, dibuje el diagrama esquemático como se muestra a

continuación en función de los ciclos de la señal de reloj que muestre si existe
posibilidades de riesgo en la ejecución del código descrito en un procesador pipelined. De
la misma manera indique en cual o cuales ciclos habría ese riesgo.

lw $s2, 40($0)

add $s3, $t1,

$t2

and $s2,
$s3,$s2

or $t1, $s4, $s0

sub $t2, $s0,

$s5

2. Ben Bitdiddle is contemplating building the single-cycle MIPS processor in a 65 nm CMOS

manufacturing process. He has determined that the logic elements have the delays given in
the following table. Help him compute the execution time for a program with 100 billion
instructions. Assume that Tc is defined for a single-cycle processor as:

3. Suponga que tiene un procesador MIPS multiciclo cuyas operaciones consisten en

aproximadamente el 25% de loads, 10% de stores, 11% de branches, 2% de jumps y 52%
de instrucciones tipo R. Determine el promedio del factor CPI para este procesador
 sabiendo que el CPI promedio es la suma de los diferentes CPI multiplicados por su
respectivo porcentaje para cada tipo de instrucciones. Asuma que cada tipo de instrucción
toma las siguientes ciclos:
Tipo de instrucciones CPI
jumps, branch 3
Instrucciones tipo R y store 4
load 5

4. Ben Bitdiddle is wondering whether he would be better off building the multicycle
processor instead of the single-cycle processor. For both designs, he plans on using a 65 nm
CMOS manufacturing process with the delays given in Table of the exercise 2. Help him
compare each processor’s execution time for 100 billion instructions. Assume that Tc for a
multicycle processor is given by the following equation:

and, seconds/cycle=325*10-12 s/cycle.

5. Ben Bitdiddle needs to compare the pipelined processor performance to that of the single-
cycle and multicycle processors considered in the previous exercises. Most of the logic
delays were given in Table in exercise 2. The other element delays are 40 ps for an equality
comparator, 15 ps for an AND gate, 100 ps for a register file write, and 220 ps for a
memory write. Help Ben compare the execution time of 100 billion instructions. Please
suppose that average CPI for this processor is 1.15 and Tc can be calculated as: