Lab No 9:

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Objective
The main objective of this lab is to study common source JFET amplifier and
measure and calculate -VGS and ID. IDSS, VG (off) measure by multi meter and record
them and also to get graph using oscilloscope and built all figures in multisim.
Procedure
• In first step, create the circuit in multisim and measured the IDSS and then
recorded it
IDSS= 6.25
• In second step, VGS (off) measured and then created circuit in multisim and
used ammeter to measure ID and vary VGG until ID becomes zero.
VGS (off)=-1.095
• In next step, measured all the resistors of fig-9-3 and then recorded it.
• In next step, constructed the dc portion of the circuit of fig-9-3 on a
breadboard and the measured ID and VGS.
ID=1.345m VGS=-2.005
• In last step, measured voltage gain to added the ac portion of the amplifier in
figure 9-3 and then took screenshot.

Data

Figure 9-1: Circuit

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Figure 9-2: Circuit

Figure 9-3: Circuit

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ID=VS/RS=2.005/1.5K=0.0013
ID=VS/RS=3.01/1.5K=0.002
ID=VS/RS=3.91/1.5K=0.0026
ID=VS/RS=3.99/1.5K=0.0027
VGS=-(VG-VS)=-(6.1-3.21)=-2.89
VGS=-(VG-VS)=-(6.1-3.29)=-2.81
VGS=-(VG-VS)=-(6.1-3.41)=-2.69
VGS=-(VG-VS)=-(6.1-3.55)=-2.55
ID=VS/RS=5.105/1.5K=0.00189
ID=VS/RS=6.115/1.5K=0.00166
ID=VS/RS=6.95/1.5K=0.00159
ID=VS/RS=7.10/1.5K=0.00149

VGS=-(VG-VS)=-(6.1-3.65)=-2.611
VGS=-(VG-VS)=-(6.1-3.95)=-2.571
VGS=-(VG-VS)=-(6.1-3.55)=-2.532
VGS=-(VG-VS)=-(6.1-3.55)=-2.499
Voltage gain;
Av=-RD/RS=4.7K/1.5K=-3.133

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 ID -VGS
Measured (step 2) 0 -4.2
Calculated 0.0013 -2.89
Calculated 0.002 -2.81
Calculated 0.0026 -2.69
Calculated 0.0027 -2.55
Measured(Q-point), (step 4) 0.00179 -2.614
Calculated 0.00189 -2.611
Calculated 0.00166 -2.571
Calculated 0.00159 -2.532
Calculated 0.00149 -2.499
Measured (step 1) 0.011 0

Table 9-1

Graph: JFET

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Discussion
In this lab, we discussed common source of JFET amplifiers. Since the N-Channel
JFET is a depletion mode device and is normally “ON”, a negative gate voltage
with respect to the source is required to modulate or control the drain current. This
negative voltage can be provided by biasing from a separate power supply voltage
or by a self-biasing arrangement if a steady current flow through the JFET even
when there is no input signal present and Vg maintains a reverse bias of the gate-
source PN junction. The input signal, (Vin) of the common source JFET amplifier
is applied between the Gate terminal and the zero volts rail, (0v). With a constant
value of gate voltage Vg applied the JFET operates within its “Ohmic region”
acting like a linear resistive device. The drain circuit contains the load resistor, Rd.
The output voltage, Vout is developed across this load resistance. The efficiency of
the common source JFET amplifier can be improved by the addition of a resistor,
Rs included in the source lead with the same drain current flowing through this
resistor. Resistor, Rs is also used to set the JFET amplifiers “Q-point”. One of the
main disadvantages of using Depletion-mode JFET is that they need to be
negatively biased. Should this bias fail for any reason the gate-source voltage may
rise and become positive causing an increase in drain current resulting in failure of
the drain voltage, Vd.
Conclusion
To conclude this lab, learned common source of JFET amplifiers and also
calculated some values. The control of the Drain current by a negative Gate
potential makes the Junction Field Effect Transistor useful as a switch and it is
essential that the Gate voltage is never positive for an N-channel JFET as the
channel current will flow to the Gate and not the Drain resulting in damage to the
JFET. The principals of operation for a P-channel JFET are the same as for the N-
channel JFET, except that the polarity of the voltages need to be reversed.