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NEW ERA UNIVERSITY

College of Engineering and Technology
Department of Computer Science

DIGITAL COUNTER

Project Presented for
CS 231L Digital Design (Laboratory)

REGINALD N. HERNANDEZ
DONN LESTER J. REGALADO

SEPTEMBER 2009

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Karnaugh Maps. . . . . . . 9 Project Grade Sheet. . 1 State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii Project Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Equipment List . . . . . . . . . . . . . .i Acknowledgement . . . . . . . . . . . . . . . . . . . . . . . . 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Excitation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Digital Counter Still Photographs . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Designers’ Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table of Contents Title Page . . . . . .

Jerry Esperanza. Thanks also to our friend who help us to troubleshoot and to finish the project. support and guidance. We wishes to express our gratitude to our professor. ii . assistance. who was abundantly helpful and offered invaluable teaching from the start until now.ACKNOWLEDGEMENT This project would n t have been possible without the support of many people.

On this case. The documentation shows the step by step process on how the digital counter was designed in theory and applied in building the actual counter. ICs and its PIN were properly numbered/tagged to avoid confusion during the debugging/troubleshooting process. The following were produced as per completion of each stage: State Diagram Excitation Table Karnaugh Maps Circuit Diagram Equipment List Circuit Diagram was the sole basis in producing the needed materials and in plotting the circuit on the breadboard. Theoretical design was divided into 5 stages. The designers wish that this project be put in to good use and a reference guide to future students of New Era University Computer Science Digital Design class. 1 . The designers tested first the binary output sequence of the counter (using LEDs) before they attempted to connect it to the deco der of the 7 -segment display. the designers attempted to design the sequence 1 3 5 7 9. Output of the binary sequence was decoded using a 7447 decoder and a 7-segment dis lay.flops. The project attempted to apply all the theoretical aspects learned on Digital Design offered for a Computer Science course.Project Overview The designers wished to design a digital counter using JK flip.

State Diagram 1 0001 9 3 1001 0011 7 5 0111 0101 2 .

Excitation Table Qprevious Qnext d c b a DCBA DCBA J K J K J K J K 0001 0011 0 X 0 X 1 X X 0 0011 0101 0 X 1 X X 1 X 0 0101 0111 0 X X 0 1 X X 0 0111 1001 1 X X 1 X 1 X 0 1001 0001 X 1 0 X 0 X X 0 KARNAUGH MAPS J(D) K(D) AB AB 00 01 11 10 00 01 11 10 CD CD 00 0 0 1 0 00 X X X X 01 X X X X 01 X X X X 11 X X X X 11 X X X X 10 X X X X 10 X X X X JD = QAQB KD = 1 J(C) K(C) AB AB 00 01 11 10 00 01 11 10 CD CD 00 0 1 X X 00 X X 1 0 01 0 X X X 01 X X X X 11 X X X X 11 X X X X 10 X X X X 10 X X X X JC = QB KC = QB 4 .

J(B) K(B) AB 00 01 11 10 AB 00 01 11 10 CD CD 00 1 X X 1 00 X 1 1 X 01 0 X X X 01 X X X X 11 X X X X 11 X X X X 10 X X X X 10 X X X X JB = QB KB = 1 J(A) K(A) AB AB 00 01 11 10 00 01 11 10 CD CD 00 X X X X 00 0 0 0 0 01 X X X X 01 0 X X X 11 X X X X 11 X X X X 10 X X X X 10 X X X X JA = 1 .

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CIRCUIT DIAGRAM .

01 µF ceramic capacitor 1 Mega resistor ¼ watts (2 pieces) 470 ohms resistors ¼ watts (7) 7-Segment LED Display common anode Solid-core wire (gauge 22.Equipment List Prototyping board (breadboard) DC Power Supply 5V or 9V Battery 1 µF capacitor 0. 2 meter long) Digital IC: 555 Timer IC 7408 AND gate 7447 7-segment Decoder 74LS73 (2) JK Flip flop 6 .

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Joseph Subdivision New Era.Designers’ Resume DONN LESTER J. Diliman. Windows 7. REGALADO New Era men’s dorm 2. Quezon City Mobile (0926) 3843013 E-mail : donn_kmc10@yaho o. Open office. Java. 1991 Weight: 180 lbs Height 5’7 Civil Status: Single 7 . MS office. Turbo C and HTML PERSONAL Date of birth: October 16. New Era. Quezon City PROJECT/TECHNICAL EXPERIENCE Database Design Analyst September 2010 Computer Science Student Record Webpage design February 2009 Project in Webpage Design ICT SKILLS Windows XP. Prefer a position in data managing where my skills in mathematics and computer programming can be applied and contribute to new systems.com CAREER OBJECTIVE To use and enhance my computer skill for data management and computer programming. EDUCATION Bachelor of Science in Computer Science 2009 – present New Era University 9 St.

REGINALD N. Culiat. Quezon City PROJECT/ TECHNICAL EXPERIENCE Database Design Analyst September 2010 Computer Science Student Record Case Study in DBMS Webpage design February 2009 Project in Webpage Design PERSONAL Date of Birth: July 5.1.com CAREER OBJECTIVE To use my computer science training in webpage designing for designing and developing websites. Joseph Subdivision New Era. Tandang Sora Avenue. Quezon City Email: shockwave082408@yahoo. EDUCATION Bachelor of Science in Computer Science 2010 New Era University (NEU) 9 St. 1992 Height: 5’6” Weight: 140 pounds Civil Status: Sing le Gender: Male 8 . Prefer position in webpage designer where creativity is required. HERNANDEZ High-Rise Bldg.

75 54-50 3. Proj ect Grade Sheet PARTIAL ONLY FULL (Half of points FULL Full NONE equivalent POINTS points) 0 point THEORETICAL DESIGN Documentation has the following: 1 Cover page 2 [ ] [ ] [ ] 2 Table of Contents 2 [ ] [ ] [ ] 3 Project Overview 2 [ ] [ ] [ ] 4 State diagram 6 [ ] [ ] [ ] 4 Excitation table 8 [ ] [ ] [ ] 5 Karnaugh Maps 10 [ ] [ ] [ ] Circuit Design (all ICs and pin assignments were 6 numbered/ tagged properly) 12 [ ] [ ] [ ] 7 Equipment List 4 [ ] [ ] [ ] Still photograph of finished project (at least 2 on 8 different angle/sequence) 2 [ ] [ ] [ ] 9 Designers' resume 2 [ ] [ ] [ ] DESIGN APPLICATION No spaghetti / protruding 10 wirings 12 [ ] [ ] [ ] 11 Counter counts as per design.25 64-60 3.00 90-87 1.00 9 .00 71-69 2.25 44-40 4.75 77-72 2.25 DATE: 86-82 1.96 1.00 68-65 2. ESPERANZA John Erick Lester Sumugat 95-91 1. Gabion Score Equivalent Score Equivalent 100.50 59-55 3. 4 [ ] [ ] [ ] 14 Designers were confident and organized. 2 [ ] [ ] [ ] Total 100 Team Members: Grade Grade Rhys Anton T.50 <= 39 5.00 49-45 3. 30 [ ] [ ] [ ] FEEDBACK ON DESIGNERS 12 Answered panel questions in respectful manner. 2 [ ] [ ] [ ] 13 All questions were answered correctly.50 81-78 2.75 PANEL: JEREMIAS C.