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Gregory P. Stone (State Bar No. 078329) Steven M. Perry (State Bar No. 106154) Sean Eskovitz (State Bar No. 241877) MUNGER, TOLLES & OLSON LLP 355 South Grand Avenue, 35th Floor Los Angeles, California 90071-1560 Telephone: (213) 683-9100 Facsimile: (213) 687-3702 Email: gregory.stone@mto.com; steven.perry@mto.com; sean.eskovitz@mto.com Peter A. Detre (State Bar No. 182619) Carolyn Hoecker Luedtke (State Bar No. 207976) Jennifer L. Polse (State Bar No. 219202) MUNGER, TOLLES & OLSON LLP 560 Mission Street, 27th Floor San Francisco, California 94105 Telephone: (415) 512-4000 Facsimile: (415) 512-4077 Email: peter.detre@mto.com; carolyn.luedtke@mto.com; jen.polse@mto.com Attorneys for RAMBUS INC.

Rollin A. Ransom (State Bar No. 196126) SIDLEY AUSTIN LLP 555 West Fifth Street, Suite 4000 Los Angeles, California 90013-1010 Telephone: (213) 896-6000 Facsimile: (213) 896-6600 Email: rransom@sidley.com Pierre J. Hubert (Pro Hac Vice) Craig N. Tolliver (Pro Hac Vice) McKOOL SMITH PC 300 West 6th Street, Suite 1700 Austin, Texas 78701 Telephone: (512) 692-8700 Facsimile: (512) 692-8744 Email: phubert@mckoolsmith.com; ctolliver@mckoolsmith.com

RAMBUS INC.’S SUPPLEMENTAL BRIEF REGARDING “CLOCK CYCLE” PHRASE OF THE WARE PATENTS CASE NOS. C 05-00334 RMW, C 05-02298 RMW, C 06-00244 RMW

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UNITED STATES DISTRICT COURT NORTHERN DISTRICT OF CALIFORNIA SAN JOSE DIVISION ) ) Plaintiff, ) vs. HYNIX SEMICONDUCTOR INC., HYNIX) SEMICONDUCTOR AMERICA INC., HYNIX) SEMICONDUCTOR MANUFACTURING) AMERICA INC., ) ) SAMSUNG ELECTRONICS CO., LTD.,) SAMSUNG ELECTRONICS AMERICA,) INC., SAMSUNG SEMICONDUCTOR, INC., SAMSUNG AUSTIN SEMICONDUCTOR,) ) L.P., ) NANYA TECHNOLOGY CORPORATION,) NANYA TECHNOLOGY CORPORATION) U.S.A., ) Defendants. ) ) RAMBUS INC., ) ) Plaintiff, ) v. SAMSUNG ELECTRONICS CO., LTD., ) SAMSUNG ELECTRONICS AMERICA, ) INC., SAMSUNG SEMICONDUCTOR, INC., ) SAMSUNG AUSTIN SEMICONDUCTOR, ) L.P., ) ) Defendants. ) ) Case No. C 05-00334 RMW RAMBUS INC.’S SUPPLEMENTAL BRIEF REGARDING “CLOCK CYCLE” PHRASE OF THE WARE PATENTS Judge: Hon. Ronald M. Whyte Trial: January 19, 2009 Courtroom: 6, 4th Floor

Case No. C 05-002298 RMW

) ) Plaintiff, ) vs. MICRON TECHNOLOGY, INC. and MICRON) ) SEMICONDUCTOR PRODUCTS, INC., ) ) Defendants. ) )

Case No. C 06-00244 RMW

RAMBUS INC.’S SUPPLEMENTAL BRIEF REGARDING “CLOCK CYCLE” PHRASE OF THE WARE PATENTS CASE NOS. C 05-00334 RMW, C 05-02298 RMW, C 06-00244 RMW

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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 I.

Pursuant to the Court’s July 25th Order, Dkt. No. 1985, Rambus submits its Supplemental Brief Regarding the “Clock Cycle” Phrase of the Ware Patents. The “Clock Cycle” Phrase should be given its plain meaning, and not be construed with the Manufacturers’ limitation to “only” certain types of half clock cycles. The intrinsic and extrinsic evidence are consistent with Rambus’s interpretation, and do not support the Manufacturers’ limitation that the Court has recognized is “plagued” with problems. See July 25th Order at 21. Claim Term Rambus The Manufacturers “during a Phrase does not require separate Only between two adjacent clock first/second half of construction, but is construed in edges beginning with a rising edge of a clock cycle of an view of the terms therein, plus the clock signal and ending at the external clock plain meaning. next falling edge of the clock signal signal” or beginning with a falling edge of the clock signal and ending at the next rising edge. Regardless of which party’s interpretation is applied, however, the Manufacturers’ noninfringement argument fails.1 The Manufacturers’ motion for summary judgment of non-

infringement should be denied, and in view of the July 25th Order on the other Ware patent terms, Rambus’s motion for summary judgment of infringement now should be granted. THE COURT SHOULD ADOPT RAMBUS’S INTERPRETATION AND REJECT THE MANUFACTURERS’ LIMITATION A. The Intrinsic Evidence is Contrary to the Manufacturers’ Limitation

Rambus’s position is consistent with the intrinsic evidence. It is undisputed that there is 20 no disclaimer, express or implied, in the Ware specification regarding whether one half of a 21 22 23 24 25 26 27 28 1
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clock cycle must begin on an edge.2 As the Court noted in its July 25th Order, the patent merely Given that the Manufacturers infringe under either construction of the “Clock Cycle” Phrase, Rambus saw no need to avail itself of the opportunity presented by the Court’s July 25th Order to seek a stipulation to extend the Final Infringement Contentions for the Ware patents. 2 Notably, although the Manufacturers moved for summary judgment for lack of written description on what amounts to dozens of terms in this litigation, the Manufacturers have never contested on summary judgment that the Ware specification describes the full scope of the “clock cycle” limitation as understood by Mr. Murphy and Rambus, i.e., that a person of ordinary skill in the art at the time of the invention would have known that a clock cycle was not restricted to being measured from a rising or falling edge.
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speaks to the two transfer operations occurring within a single clock cycle. See July 25th Order at 21; see, e.g., U.S. Patent No. 6,493,789 at 3:24-25 (“allowing two transfer operations to occur within a single clock cycle”); 7:22-23 (“allowing two transfer operations to occur within a single clock cycle”); 10:19 (“received by the DRAM in only one-half of a clock cycle”); 12:24-25 (“transferred during the same half clock cycle as the respective WE bit”); 12:27-28 (“transferred during the same half clock cycles”). Other evidence from the intrinsic record shows “one clock cycle” not coinciding with rising or falling edges. Cited U.S. Patent No. 5,339,276 to Takasugi shows signal S90 going positive for “one clock cycle” where S90 clearly does not coincide with rising or falling edges of the clock. See Murphy Decl. ¶ 5. The terms “rising edge” and “falling edge” do not appear in the Ware patent specification.3 What would be clear to a person of ordinary skill familiar with the art, however, is that in the relevant timeframe, both Rambus and the Ware patent inventors were capable of using the language “rising edge” and “falling edge” when they chose, and in the Ware patents, they chose to not use that language. Cf. Murphy Decl. ¶ 6; U.S. Patent No. 6,378,020 (assigned to Rambus Inc. and litigated in Hynix I) at 19:16-17 (“rising edge … falling edge”); U.S. Patent No. 6,516,365 (Hampel) at 11:49, 16:45, 19:35 (“rising edge”), 16:45-46 (“falling edge”); U.S. Patent No. 6,209,071 (Hampel) at 8:32-33, 8:57, 8:61, 12:4, 12:5, 12:26 (“rising edge”), 6:56, 6:58, 7:2 (“falling edge”); U.S. Patent No. 6,788,593 (Stark) at 1:37, 2:19, 2:25 (“rising edge”), 16:52, 16:40, 18:2 (“falling edge”); U.S. Patent No. 6,470,405 (Griffin) at 2:29, 2:30 (“rising edge”).4

The Manufacturers do not explain from where or why they import this limitation, or why they chose to import a limitation of rising and falling edges instead of peaks and troughs (just to give another example of cycle features that could be present in the waveform of a real-world signal). 4 Rambus notes that the term “clock cycle” did not receive construction in claims tried in the Hynix I case. Although the Ware patents were not at issue there, not construing the term “clock cycle” in the context of the Ware patents would not be inconsistent, given that the Ware patent specification imparts no special meaning to “clock cycle.” 2
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B.

Dictionary Evidence is Contrary to the Manufacturers’ Limitation

Rambus’s interpretation is consistent with dictionary extrinsic evidence, which generally does not limit a half clock cycle to being measured between edges. For example, the Oxford Dictionary of Computing (4th ed. 1997) at 77, provides: “A clock cycle is considered to be one complete cycle of the clock signal and will always contain one active transition of the clock.” Murphy Decl. ¶ 7. Nothing in that definition requires measurement from a rising edge to a falling edge or from a falling edge to a rising edge. Moreover, the dictionary cited in the Court’s July 25th Order is easily reconciled with Rambus’s interpretation. The 1996 IEEE Dictionary defines “clock cycle” as “one period of the [clock] signal, beginning with the rising edge of the signal and ending on the following rising edge of the signal.” That definition may be understood as stating that a clock cycle is “one period of a clock,” and that one way to measure that period is “beginning with a rising edge of the signal and ending on the following rising edge of the signal,” given that edges of an idealized signal are easily-identified reference points. Murphy Decl. ¶ 8. To the extent the 1996 Dictionary is read more narrowly to require that a clock cycle must “begin[] with the rising edge,” that definition is (i) contrary to the Ware specification that has no such limitation, and (ii) even contrary to the Manufacturers’ and Mr. McAlexander’s position that the Ware specification teaches a clock cycle can begin and end on a falling edge. See Manufacturers’ Proposed Construction; see Dkt. No. 514, ¶ 220 (figure). C. Other Extrinsic Evidence Indicates the Manufacturers’ Limitation is Plagued with Problems and Should Be Rejected

As the Court pointed out in its July 25th Order, the Manufacturers’ proposed construction is “plagued” by practical questions such as, “When is the beginning of a rising edge?” The question of whether a rising edge begins upon a voltage increase invites the question of when the voltage is increasing, given that voltages may fluctuate. Murphy Decl. ¶ 10. The issue of a voltage crossing a midpoint, presumes either a reference at a midpoint or differential clocks crossing at a midpoint, not required by the claims but not precluding infringement. Id. Rambus

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respectfully submits that these questions are answerable through the eyes of a person of ordinary skill in the art in the context of a specific system. Id. Although these questions do not preclude infringement even under the Manufacturers’ construction as set forth later in this Brief, Rambus nevertheless continues to dispute the Manufacturers’ limitation--not just because the Manufacturers’ limitation is incorrect as a legal and technical matter--but also because Rambus believes the Manufacturers will attempt to apply their construction in ways that no person of ordinary skill in the art would.5 1. One of Ordinary Skill in Art Would Have Known that It is Impossible to Have a System with a Perfect Square-Wave Idealized Clock, Instantaneous Latching, and Zero Tolerance

The Manufacturers may be misinterpreting their own construction to require a perfect, physically unrealizable system. The Manufacturers state in their Motion that there is a

“data/mask bit relationship required by the asserted claims -- namely that the mask bit and the data bit be received exactly within the boundaries of a half cycle of the external clock,” and then the Manufacturers immediately introduce a hand-drawn figure showing a timing diagram from a system having a perfect square-wave idealized clock, instantaneous latching, and zero tolerance. Mfs. Br.6 at 12-13. One of ordinary skill in the art reading the Ware patent specification would know that it is physically impossible to have these characteristics. Murphy Decl. ¶ 11. The Manufacturers appear to apply their construction in a way that excludes real-world systems that would necessarily allow for some margin of error with respect to the timing of the receipt of signals. The Manufacturers’ attempted application of their construction therefore excludes any

For example, Rambus notes that the Manufacturers already allege nearly three-hundred (300) separate purported references. In view of that number, it is highly likely that the Manufacturers will attempt to apply their construction in ways that no person of ordinary skill in the art applying the Manufacturers’ construction would. Despite the Court’s July 16th Order indicating that Court expects the Manufactures “to significantly narrow[] the number of prior art references,” the Manufacturers continue to add, rather than subtract, to their number of alleged prior art references, having just provided Rambus an additional 10 references days ago on July 28th. 6 Manufacturers’ Motion for Summary Judgment, Dkt. No. 504 (“Mfs. Br.”). 4
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embodiment that could actually be realized, including the preferred embodiment. The Court should reject the Manufacturers’ limitation. 2. One of Ordinary Skill in the Art Would Not Have Understood a Rising Edge and a Falling Edge to Delineate Half of a Clock Cycle for All Possible Duty Cycles

Not only do the Manufacturers attempt to misapply their own proposed construction so that it covers only systems that are not physically realizable, but the Manufacturers may attempt to misapply their construction in particular systems with extreme duty cycles. “Duty cycle” may be understood to be a ratio between when a system is on (or “high”) and off (or “low”). Murphy Decl. ¶ 12. In one example of a possible misapplication of the Manufacturers’ construction, assuming arguendo some particular alleged prior art system having a clock with a 90/10 duty cycle, the Manufacturers could attempt to argue that the 10% portion of the clock cycle would be “half of a clock cycle” in that system, where no person of ordinary skill in the art considering that particular system would have understood 10% of the clock cycle to be “half of the clock cycle.” Again, the Manufacturers’ limitation is not helpful, and should be rejected. 3. One of Ordinary Skill in the Art Would Have Known that One Half of a Clock Cycle Need Not Begin on a Rising Edge or Falling Edge, as Evidenced by the Manufacturers’ Own Contemporaneous Datasheets

The Manufacturers’ own datasheets contain example parameters measured in half of a clock cycle and then show those parameters not beginning on a rising or falling edge. See, e.g., Murphy Decl. ¶ 13 (discussing Micron datasheet showing a parameter tRPST having a nominal value of half of a clock cycle, i.e., 0.5 tck, but where the timing diagram shows that the parameter does not begin or end on a rising or falling edge of the clock). Hence the

Manufacturers’ own literature recites examples of half of a clock cycle inconsistent with the Manufacturers’ proposed definition. II. REGARDLESS OF THE CONSTRUCTION OF THE “CLOCK CYCLE” PHRASE, THE MANUFACTURER’S MOTION SHOULD BE DENIED AND 5
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RAMBUS’S MOTION FOR SUMMARY JUDGMENT OF INFRINGEMENT SHOULD BE GRANTED Under application of either the Manufacturers’ proposed construction or Rambus’s plain meaning interpretation, the Manufacturers’ non-infringement argument fails. The

Manufacturers’ motion for summary judgment of non-infringement should be denied, and in view of the Court’s July 25th Order on the other Ware patent terms, Rambus’s motion for summary judgment of infringement on the Ware patents now should be granted. A. THE MANUFACTURERS’ MOTION FOR SUMMARY JUDGMENT SHOULD BE DENIED

The Manufacturers’ non-infringement argument is summarized on pages 12-15 of the Manufacturers’ Brief. The Manufacturers argue that “the data mask signal DM is sensed

synchronously with the differential data strobe signal DQS, /DQS…,” id. at 14, and that “[t]he asserted claims, in contrast, require the data to be sensed synchronously with respect to the external clock signal--a signal that is different from the differential data strobe….” Id. at 14-15. The Manufacturers further argue that because “the data mask signal [DM] spans more than one clock cycle, …it is not received ‘during’ a half clock cycle, but is rather [sic] present on the pins over portions of two different half-clock cycles.” Id. at 15. Hence, the Manufacturers’ purported non-infringement argument has two aspects, and it fails for the following two reasons: (1) the presence of a strobe with an external clock signal does not preclude infringement where the claims require an external clock signal (and the Manufacturers apparently have abandoned their synchronicity argument);7 and (2) the presence of a signal on a pin for portions of two half-clock cycles (even under the Manufacturers’ construction of “clock cycle”) does not preclude a bit being received during one of those half clock cycles. Rambus treats these seriatim. The Manufacturers apparently have abandoned their non-infringement argument regarding synchronicity with an external clock. Compare Mfs. Br. at 14-15 (“The asserted claims, in contrast, require the data to be sensed synchronously with respect to the external clock signal…”) with Mfs. Reply, Dkt. No. 728, at 9 (“Rambus’s arguments regarding synchronism are red herrings … it is not a requirement of the asserted claims.”) What the Manufacturers’ Reply calls a “red herring” is the Manufacturers’ own argument. 6
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1.

Under Either Party’s Proposed Construction, the Presence of a Strobe Does Not Preclude Infringement

First, the Manufacturers argue the presence of a strobe in the Accused Devices. See, e.g., id. at 14-15 (“the data mask signal DM is sensed synchronously with the differential data strobe… [t]he asserted claims, in contrast, require the data to be sensed synchronously with respect to the external clock signal--a signal that is different from the differential data strobe….”). The claims do not, however, prohibit the presence of a strobe, under either party’s interpretation. The presence of additional elements in an Accused Device (e.g., a data strobe) does not preclude infringement of an open-ended claim so long as the elements of the claim (e.g., an external clock signal) are present. See, e.g., Crystal Semiconductor Corp. v. Tritech

Microelectronics Int'l, Inc., 246 F.3d 1336, 1353 (“Basic patent law holds that a party may not avoid infringement of a patent claim using an open transitional phrase, such as comprising, by adding additional elements.”). The Manufacturers have not disputed that the Accused Devices contain an “external clock signal,” an example of which is depicted on the same page of the Nanya Representative Product Datasheet excerpted in the Manufacturers’ Motion (where the Manufacturers’ excerpt does not show that clock). Dkt. No. 514, Ex. 24 at NTCR-00054447. The Manufacturers’ argument fails. 2. Under Either Party’s Proposed Construction, the Data Mask Signal Being “Present” on the Pins For Some Portions of Two Different Half Clock Cycles Is Irrelevant to Infringement, Because the Claims Only Require that the Successive Mask Bits and Data Bits Be “Received” During Successive Half Clock Cycles

Second, the Manufacturers argue that the data mask DM “spans more than one clock cycle; in other words, it is not received ‘during’ a half clock cycle, but is rather present on the pins over portions of two different half clock cycles.” Mfs. Br. at 15. The Manufacturers argument that the signal is “present” on the pins before the bit is read is simply irrelevant.8
8

To analogize, a shipping and receiving company may clock something as received when it is scanned into inventory, regardless of how long it has been sitting at the loading dock. See Murphy Decl. ¶ 17. 7
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In the Accused Devices, the DM signal is “received” at an instant in time, as specified by the strobe, during a half clock cycle. See Murphy Decl. ¶ 16. The Manufacturers’ Accused Device literature is positively replete with indications that DM is “received” on edges of DQS and thus during a half clock cycle as the claims require: “DM is sampled on both edges of DQS.”9 Id. (emphasis added). Confronted with this, the Manufacturers argue that “sampling” somehow is different from “receiving” and that “receiving” takes place continuously. See, e.g., Manufacturers’ Reply, Dkt. No. 728, at 9-10 (“While ‘sensing’ [sic] or ‘sampling’ may happen during a specific point in time, a signal will be continuously ‘received’ by a device as long as it is present at the pin.”). The Manufacturers’ own datasheets use “sampling” and “receiving” interchangeably, indicating that “receiving” is done on an edge--not “continuously” as the Manufacturers argue. See, e.g., Hynix GDDR4 Data Sheet at 5, 18, 73 (“Address is received on two consecutive rising edges of CK.”) (emphasis added); Samsung GDDR4 Data Sheet at 32 (“Address is received on two consecutive rising edges of CK”) (emphasis added). To illustrate, Rambus has annotated the figure of the “Burst Write Operation with Data Mask” timing diagram found on the same page of the Nanya Representative Product Datasheet as the timing diagram that the Manufacturers excerpt in their Motion, see Mfs. Br. at 14:

See Hynix DDR2 Data Sheet at 8 (“Input Data is masked when DM is sampled High coincident with that input data during a WRITE access. DM is sampled on both edges of DQS.”); Hynix DDR3 Data Sheet at 8 (same); Hynix GDDR4 Data Sheet at 68 (“Input Data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on the rising and falling edges of WDQS.”); Micron DDR2 Data Sheet at 11, Table 3 (“Input data is masked when DM is concurrently sampled HIGH during a WRITE access. DM is sampled on both edges of DQS.”); Micron GDDR3 Data Sheet at 7, Table 3 (“Input data is masked when DM is sampled HIGH along with that input during a write access. DM is sampled on the rising and falling edges of WDQS.”); Micron RLDRAM II Data Sheet at 14, Table 4 (“Input data is masked when DM is sampled HIGH. DM is sampled on both edges of DK”); Micron DDR3 Data Sheet at 4, Table 4 (“Input data is masked when DM is sampled HIGH along with that input data during a write access.); Nanya DDR2 Data Sheet at 4 (“Input Data is masked when DM is sampled high coincident with that input data during a Write access. DM is sampled on both edges of DQS.”); Nanya DDR Data Sheet at 7 (same); Nanya DDR3 Data Sheet at 5 (same); Samsung DDR2 Data Sheet at 10 (“Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS”); Samsung DDR3 Data Sheet at 11 (same); Samsung GDDR3 Data Sheet at 6 (“Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of clock”); Samsung GDDR4 Data Sheet at 6 (same). 8
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Under Either Party’s Construction, the Accused Devices Meet the “Clock Cycle” Phrase

The dotted lines in the original figure delineate half clock cycles under the Manufacturers’ construction. DM and DQ are received on the annotated bold lines (on crossing of DQS, /DQS) during successive half clock cycles even under the Manufacturers’ construction.

See also Dkt. No. 514, Ex. 24 at NTCR-00054447 (unannotated figure). According to the datasheet, “the first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. … The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed.” Id. at NTCR-00054444. The successive transitions of DQS where DQ and DM are received occur within successive halfcycles of the external clock signal CK that are delineated by the dotted lines. See Murphy Decl.

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¶ 20.10 Hence the Accused Device receives successive mask bits and data bits during successive halves of a clock cycle, and the Manufacturers’ non-infringement argument fails.11 B. RAMBUS’S MOTION FOR SUMMARY JUDGMENT SHOULD BE GRANTED

In view of the Court’s July 25th Order on the other Ware patent terms, and because the Accused Devices meet the “Clock Cycle” Phrase regardless of which party’s proposed interpretation is adopted, Rambus’s motion for summary judgment of infringement on the Ware patents now should be granted. III. CONCLUSION For the foregoing reasons, and for all the reasons set forth in the briefing and supporting papers, the Court should reject the Manufacturers’ proposed limitation on the “Clock Cycle” Phrase, deny the Manufacturers’ Motion for Summary Judgment of Non-infringement, Dkt. No. 504, and grant Rambus’s Motions for Summary Judgment of Infringement, C 05-00334 Dkt. Nos. 503, 505, 506, 507, 509, 510, C 06-00244 Dkt. Nos. 200, 201, C 05-02298 Dkt. No. 355.

Another figure illustrating infringement under either party’s construction is shown in Rambus’s Opposition, Dkt. No. 665, at 21. To illustrate using that figure, in the example of the tDQSS MAX case, a first DQ bit and first DM bit are received during the time between T4 and T4n on an edge of DQS, and a second DQ bit and second DM bit are received during the time between T4n and T5 on the successive edge of DQS. 11 In view of the evidence of literal infringement that Rambus believes is not genuinely disputed, Rambus does not repeat its arguments regarding doctrine of equivalents herein, and instead refers to its Opposition Brief for those additional arguments. 10
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Dated: August 1, 2008

Respectfully submitted, MUNGER, TOLLES & OLSON LLP SIDLEY AUSTIN LLP MCKOOL SMITH

/s/ Pierre J. Hubert Pierre J. Hubert Attorneys for Rambus Inc.
Austin 45214v4

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