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An Introduction to the
LPC2100 Architecture

This document gives an overview of the ARM7®

features and should be helpful for the user when
designing an ARM-7-based system.

Architecture: ARM
Author: Trevor Martin /Hitex UK
Revision: 06/2006 - 002 - 01/2005 - 002

© Copyright 2006 - Hitex Development Tools GmbH

All rights reserved. No part of this document may be copied or reproduced in any form or by any means without prior written consent of Hitex Development Tools. Hitex Development Tools retains
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1 Overview 3
2 ARM-7-Based System Design 3
2.1 Memory Access 3
2.2 Memory Accelerator Module (MAM) 4
2.3 32-bit and 16-bit Instruction Sets 4
2.4 Clock Problems 5
2.5 Vectored Interrupt Controller (VIC) 5
2.6 Power Consumption 6
2.7 Bootloader 6
2.8 "Real Monitor" Software Kernel 6
2.9 Embedded Trace Macrocell (ETM) 7
2.10 Derivatives and Features 7
3 Support 7

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1 Overview
Since its inception the ARM7 core has primarily been available as an IP core for incorporation into
custom system-on-chip designs. With the launch of the LPC2106 the first member of the LPC2100
family Philips has introduced a standard chip featuring the 32 bit ARM7 processor with on-chip FLASH
and SRAM with a range of general purpose peripherals in low pin count packages. However this on its
own does not necessarily make a successful microcontroller and as always the devil is in the detail.
This article will look at some of the key features of the LPC2100 family that help to successfully
integrate the ARM7 CPU into a standard microcontroller architecture.

2 ARM-7-Based System Design

2.1 Memory Access

One of the key design considerations when designing an ARM-7-based system is memory access.
The ARM7 core is capable of running up to 80 MHz with single-cycle execution of many instructions.
However the on-chip FLASH memory has an access time of 50 ns which would limit processor
execution to 20 MHz. Clearly running from FLASH would throw a lot of processor performance away.
The easy way to get round this would be to boot the code into on-chip SRAM and run at full speed
from RAM. This gives an increased boot-up time and an unacceptable loss of valuable SRAM. Another
solution would be to have an on-chip cache. Although this would be transparent to the user, it is
complicated to design and detracts from the inherent simplicity of the ARM7 processor. A cache would
also reduce the determinism of code run time, something not very desirable in a device designed to be
used in real-time embedded systems. It also has a large silicon footprint and logic gates that could
more effectively be used for on-chip peripherals. In order to overcome these problems, Philips have
designed a Memory accelerator Module (MAM).

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2.2 Memory Accelerator Module (MAM)

On the LPC2106 this splits the 12K of FLASH into two banks of 128 bit wide memory. This allows the
memory accelerator module to fetch four instructions for every FLASH access, further enhanced by
the interleaving of the code between the two banks. The memory accelerator module allows the ARM7
to run at maximum speed for sequential code, with, branches and calls to addresses not held in the
MAM buffers causing an instruction miss that requires a new chain of bytes to be loaded from the
FLASH. These instruction misses can be reduced by buffering FLASH data in a branch-trail buffer and
by speculative reads into a prefetch buffer. This approach is very well tailored to the ARM7 core as
small branches are eliminated as each instruction is conditionally executed.
The memory accelerator module improves the chip’s execution rate from 20 MHz to 60 MHz. It would
be possible to provide this clock directly from an external oscillator but having a 60 MHz oscillator on
the board would increase EMC problems and overall cost of the PCB. The LPC2100 family have an
on-chip PLL that can generate clock frequencies up to the full 60 MHz from a simple external oscillator
in the range 10 MHz to 25 MHz.

2.3 32-bit and 16-bit Instruction Sets

The first members of the LPC2100 family are true single-chip microcontrollers. Future variants will
have an external bus so this makes the on-chip FLASH memory very valuable. Crucially the ARM7
also has two instruction sets: the ARM (32 bit) and Thumb (16 bit). The 32-bit instruction set allows
high performance processing whilst the 16-bit provides code compression for non time-critical code.
This ability to mix performance with space saving is vital for a single-chip microcontroller with limited
on-board memory resources.

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2.4 Clock Problems

Having the processor running with a 60 MHz clock is all well and good. However this clock itself
becomes a problem when trying to run the on-chip peripherals at this speed. For this reason, there is a
separate VLSI peripheral bus within the LPC2100 devices that allows peripheral to be clocked at half
or quarter the CPU rate, without becoming a bottleneck for the processor. It is also worth noting that
the ROM and RAM are placed on the CPU local bus and not the AHB bus, as in many ARM7
implementations. Data accesses on the AHB bus can be stalled for several cycles, resulting in an
overall decrease in performance. This does not happen on the local bus. Despite having several
internal busses, the programmer’s memory map is completely flat.

2.5 Vectored Interrupt Controller (VIC)

The ARM7 core only has two possible external interrupt lines. A fast interrupt request (FIQ) and a
general purpose interrupt request (IRQ). In a typical system, normally only one interrupt source would
generate an FIQ request and this will be serviced very quickly by the processor. However all the other
interrupt sources are effectively OR’ed on the IRQ line. This leads to a poor response for most
interrupt sources. To combat this, Philips have added a vectored interrupt controller, similar to that
found in conventional CPU’s. This unit allows any interrupt source to be nominated as an FIQ interrupt
for fast processing. Thus up to 16 other interrupt sources can be handled as vectored interrupts on the
remaining IRQ interrupt line. The address of the Interrupt service routine for each vectored interrupt is
stored in the VIC.

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Should a peripheral generate an interrupt for one of these vectored interrupt sources, the address of
its interrupt service routine is loaded into the vector address register. When the ARM7 responds to the
exception and jumps to the IRQ vector, the processor can immediately jump to the correct ISR in one
instruction, without having to determine the source of the IRQ interrupt. The vector interrupt controller
is absolutely essential for achieving any kind of real-time performance.

2.6 Power Consumption

The ARM7 processor currently boasts the best Watts per MIP ratio currently available, making it ideal
for low power and hand held applications. The LPC2100 has enhanced this low-power design by
running the processor at 1.8V and the peripherals at 3.3V, so reducing the switching power
consumption of the processor.
To further reduce power consumption the clock to each peripheral can be switched off to halt its
operation. The CPU also has an IDLE mode which stops the processor but keeps the peripherals
running and a power-down mode that halts the clocks on both the CPU and the peripherals, with a
“wake-up” being generated by an external interrupt.

2.7 Bootloader
The LPC2100 devices are fitted with a FLASH bootloader which runs through the on-chip UART’s.
This allows easy in-circuit programming and reprogramming of devices for development and
production. The bootloader code is often the poor relation when it comes to software development in a
project and it often gets forgotten, only to be developed in a panic at the last minute. Having a fully
featured bootloader already in place at the beginning of a project is a real godsend!
The bootloader functions are available as an API to the application code and may also be used for in
application programming. This includes a RAM to FLASH transfer so that new code can be loaded into
the chip by any method and not just by the UART’s.

2.8 "Real Monitor" Software Kernel

The ARM7 processor is widely supported by all the major compiler vendors. Debugging support is
provided by a JTAG port. This is a serial debugging interface that provides basic run control,
breakpointing and viewing of memory locations.

The ARM "Real Monitor" software kernel is also programmed into a reserved area of the device
memory. This is a debug program that can be triggered by events within the embedded ICE. It
provides pseudo-real-time access to on-chip memory so you can view and update memory ‘on the fly’,
something that is extremely useful when developing real-time applications.

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2.9 Embedded Trace Macrocell (ETM)

However unlike many other ARM7 implementations, Philips have also fitted the embedded Trace
macrocell. This allows debuggers to provide trace information and set more complex triggers. It thus
allows software to be developed to a higher level of confidence, suitable for the most demanding
applications such as medical and aerospace.

2.10 Derivatives and Features

The first devices which are released are the LPC2106, LPC2105 and LPC2104, featuring 128K of
FLASH with 64K/32K/16K of SRAM (LPC2106/5/4) and up to 32 GPIO pins.
There are also: serial interfaces comprising two UARTS, one with a modem interface, plus SPI and
I2C interfaces; three general purpose timers, one with a PWM unit for symmetrical and single-edge
PWM. A real-time clock/calendar with alarm and a watchdog are also present. Future variants are
planned to feature A/D converters, CAN peripherals, and an Ethernet controller.

3 Support
For more information on this new microcontroller family and a free CD containing evaluation
development tools, datasheets, application notes and program examples please contact Trevor Martin
at Hitex UK or any Hitex branch (for addresses see front page).

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