Electronics Digest 1987 Summer PDF

SUMMER 1987 VOL 8 NO 1 AN ARGUS SPECIALIST PUBLICATION £2.
75
IN
NICTS
411111.
DATA ISSUE
DEDICATED DEVICES
SPECIAL PURPOSE ICs FOR:
MUSIC
COMPUTERS
DOMESTIC
AUDIC
TIMING
RADIO
air
et4 0.4
-414. Zito
4`090,
sm6 tod"s0.
0 0,
te o-04
fvois
FAIRCHILD
A SchluMberger COMpAr,y luAV22
1200 bps Full Duplex Modem
Description Connection Diagram
The pAV22 1200 bps full duplex modes I.C. is fabricated 28 -Lead Dip
in Fairchild's advanced Double -Poly Silicon -Gate CMOS (Top View)
process. The monolithic I.C. performs all the signal pro-
cessing functions required of a CCITT V.22, alternative B
compatible modem. Handshaking protocols, dialing control SLIM V00
and mode control functions can be handled by a general
LIM Vss
purpose, single chip µC. The µAV22, µC and several com-
ponents to perform the telephone line interface and con- R X IN 3 AGND
trol provide a high performance, cost effective and DOT TKO

ultra -low power solution for V.22 -compatible modem de-
ETC 0/A
signs.
SYNC 6 TSSO
The modem chip performs the modulation, demodulation, EDET 7 SCT

filtering and certain control and self -test functions required MS M001
for a CCITT V.22 -compatible modem, as well as additional
enhancements. Both 550 Hz and 1800 Hz guard tones SCR M M002
and notch filters and DTMF tone generator are on -chip. TED 10 TEST
Switched -capacitor filters provide channel isolation, spectral X712 11 DOND
shaping and fixed compromise equalization. A novel
XTL 1 12 NSK2
switched -capacitor modulator and a digital coherent de-
modulator provide 1200 DPSK operation. SCR 13 NSA 1
RED 14 RLST
The receive filter and energy detector may be configured
for call progress tone detection (dialtone, busy, ringback,
voice) providing the front end for a smart dialer.
Order Information
Functions as a CCITT V.22 -compatible modem Device Code Package Code Package Description
Interfaces to Single Chip pC Which Handles
µAV22DC FM Ceramic DIP
Handshaking Protocols and Mode Control Functions µAV22PC * Molded DIP
DTMF Tone Generation and Call Progress Tone I.LAV220C Molded Surface Mount
Detection for Smart Dialer Applications
1300 Hz Calling Tone Generator On Chip *Consult Factory
Pin and function compatible with the pA212A
On Chip Oscillator Uses 3.6864 MHz Crystal
Few External Components Required
Operates from +5 and -5 Volt Supplies
Low Operating Power: 35 mW Typical
550 Hz and 1200 Hz guard tones and notch filters
are on -chip
Absolute Maximum Ratings

VDD to DGND or AGND 7.0 V
Vss to DGND or AGND - 7.0 V
Voltage at any Input VDD + 0.3 to
Vss -0.3 V
Voltage at any Digital Output VD0 + 0.3 V to
DGND -0.3V
Voltage at any Analog Output VD0 + 0.3 V to
V5 -0.3 V
Operating Temperature Range 0°C to 70°C
Storage Temperature Range -65°C to +150°C
Lead Temperature (soldering, 10
seconds) 300°C
Data supplied by Fairchild Semiconductor Ltd. ,c Fairchild Semiconductor.
Electronics Digest Summer 1987

,MCS
IGEZT Volume 8 No. 1
Edited by:
Ron Keeley
Group Editor: Welcome to the Summer of 1987. In this issue of Electronics Digest
Dave Bradshaw we present full data sheets for more than a dozen selected ICs. They
Editorial Director: have only one thing in common: each is a complete electronic
Ron Moulton sub -system on a chip, performing multiple functions that, not too
Managing Director: long ago, would have required a circuit board of discrete elements.
Peter Welham The selection ranges from relatively simple devices such as smoke
and fluid detectors, through single chip AM and FM radios to a
Typesetting by: KAMSET universal timer employing a 4 -bit computer. Audio circuits include a
Typesetting, Brentwood, digitally controlled graphic equaliser IC, a programmable compandor,
Essex and a number of sound synthesisers. The datasheets reveal the inner
Originated by: Argus Design working of the various devices and provide all the information
Printed by: Garden City needed by an adventurous constructor to design and build a simple
Press, Letchworth radio, tunes synthesizer, DC motor controller etc.
© 1987
Subscription rates upon
application to Electronics Digest,
Subscriptions Dept., Infonet
Ltd., Times House, 179 The
Marlowes, Hemel Hempstead,
Herts HP1 1BB
Contents
Published by: Argus Specialist
Publications, 1 Golden Square, µAV22 V.22 Modem 2
London W1 R 3AB.
TDA7000 FM radio 4
Distributed by: Argus Press Sales
& Distribution Ltd., 12-18 Paul
Street, London EC2A 4JS (British
AA7392 DC motor speed controller X 7
Isles) M112 polyphonic sound generator 10

NE572 programmable compandor 20
© Argus Specialist Publications
Ltd 1987. All material is subject AY -3-1350 tunes synthesizer 24
to worldwide copyright
protection. All reasonable care is LMC835 graphics equaliser 34
taken in the preparation of the
magazine content but the p.A212 300/1200 board Modem 43
publishers cannot be held legally
responsible for errors. Where
mistakes do occur, a correction TMS1121 universal timer controller ISM 50
will normally be published as
soon as possible afterwards. All ZN414 AM radio 63
prices and data contained in the
advertisements are accepted by LM1801 smoke detector 69
us as correct at time of going to
press. Neither the advertisers LM1830 fluid detector 71
not the publishers can be held
responsible, however, for any AY -3-8910/8912 programmable sound generators Opt4
variations which may occur after
publication had closed for µA2240 universal timer '11°P 86
press.
Thanks to Mullard/Signetics, National Semiconductor, Fairchild, Texas Instruments, General Instrument,

Ferranti, SGS-ATES, and Maplin, for their assistance in compiling this edition of Electronics Digest.
Note. While every effort has been made to ensure that the data contained in this issue of Electronics Digest is accurate, neither the Publisher nor the
Manufacturer will accept any liability in respect of the use of the consequences of the us a of any data publishei here. All data (t, the manufacturer.
Electronics Digest Summer 1987 3

TDA7000 Signetics
FM Radio Circuit PIN CONFIGURATION

DESCRIPTION FEATURES
The TDA7000 is a monolithic integrated circuit R.F. Input stage
for mono FM portable radios where a minimum Mixer
of peripheral components is important (small Local oscillator
dimensions and low costs) I.F. amplifier/limiter
Phase demodulator
The IC has an FLL (Frequency -Locked -Loop) Mute detector
system with an intermediate frequency of 70 Mute switch
kHz. The I F selectivity is obtained by active
RC filters The only function which needs align-
ment is the resonant circuit for the oscillator,
thus selecting the reception frequency.
Spurious reception is avoided by means of a
mute circuit, which also eliminates too -noisy
input signals. Special precautions are taken
to meet the radiation requirements.
FUNCTIONAL PIN DESCRIPTION

PIN NO NAME AND FUNCTION
1 Muting capacitor
ABSOLUTE MAXIMUM RATINGS 2 Audio frequency output
3 Noise source
SYMBOL AND PARAMETER RATING UNIT
4 Loop filter capacitor
5 Supply voltage
Ycc Supply voltage (pin 5) 12 V
6 VCO
V6,5 Oscillator voltage (pin 6) Vcc-0.5 to V004-0.5 V 7 1st integrator capacitor (to pin 9)
8 2nd integrator capacitor
Total power dissipation See derating curve Figure 2 9 1st integrator capacitor (to pin 7)
10 IF filter capacitor (to pin 11)
TSTO Storage temperature range -55 to +150 C 11 IF filter capacitor
12 IF limiter capacitor
1.4 Operating ambient temperature range 0 to +60 °C
13 RF input
14 Mixer
15 Current source capacitor
16 Ground
17 Demodulator capacitor
18 Correlator capacitor
BLOCK DIAGRAM
RF INPUT
1 13 12
CORRE.
LATOR
2.75 1.4V
105 10K
700K
HA.
I 700K
W1/ IF FILTER
125
AP 41 AP
IF LIMITER
4.75 4.75
DEMODULATOR
2.25 2.2K
11311K
MIXER
141/11104,11 .1
MUTE CONTRO UTE LOOFILTER
VCO
-7
NOISE
SOURCE
V cc
i1
Co
I
I
)14
Cs CS
vcc 0
.4 eV)
AF OUTPUT
4 Electronics Digest Summer 1987

TDA7000 Sionetics
DC ELECTRICAL CHARACTERISTICS vcc = 4.5V; TA = 25°C: measured in Figure 3; unless otherwise specifiec
TDA7000
SYMBOL AND PARAMETER TEST CONDITION UNIT
MIn Typ Max
Vcc Supply voltage (Pin 5) 2.7 4.5 10 V
lec Supply current Vcc - 4.5V 8 mA
le Oscillator current (Pin 6) 280 MA
V1416 Voltage (Pin 14) 1.35 V
12 Output current (Pin 2) 60 14A
V2-16 Output voltage (Pin 2) RL - 22 kg 1.3 V
AC ELECTRICAL CHARACTERISTICS vcc = 4.5 V; TA = 25C; measured in Figure 3 (mute switch open, enabled); Id - 96
MHz (tuned to max. signal at 5 0./ emi.f.) modulated with cif ±22.5 kHz; f, 1 kHz;
EMF - 0.2 mV (e.m.f. voltage at a source impedance of 75 0); r.m.s. noise voltage
measured unweighted (f - 300 Hz to 20 kHz); unless otherwise specified.
TDA7000
SYMBOL AND PARAMETER TEST CONDITION UNIT
Min Typ Max
-3 dB limiting; muting disabled 1.5

Sensitivity (see Figure 2)
EMF -3 dB muting 6 NV
(e.m.f. voltage)
S/N .. 26 dB 5.5
EMF Signal handling (e.m.f. voltage) THD < 10%; of i s 75 kHz 200 mV
S/N Signal-to-noise ratio 60 dB
Of - ±22.5 kHz 0.7

THD Total harmonic distortion %
of - ±75 kHz 2.3
(ratio of the AM output signal referred to the FM

output signal)
AMS AM suppression of output voltage 50 dB
FM signal: f, - 1 kHz; af - ±75 kHz
AM signal: f, - 1 kHz; m .ii 80%
RR Ripple rejection (iiVcc - 100 mV. f - 1 kHz) 10 dB
Ve.e(,e) Oscillator voltage (r.m.s. value) (Pin 61 250 mV
Ofeec Variation of oscillator frequency Supply voltage (aVec - 1V) 60 kHzN
S.= 45
Selectivity dB
35
iifd A.F.C. range ±300 kHz
B Audio bandwidth
AVo -3 dB
10 kHz
measured with pre -emphasis (t 50 jas)
1/0") A.F. output voltage (r.m.s. value) RI_ - 22 k0 75 mV
Vec - 4 5V 22
Rj. Load resistance k0
Vez .. 9 OV 47
NOTES:
1. The muting system can be disabled by feeding a current of about 20 MA into pin 1.
2. The interstation noise level can be decreased by choosing a law -value capacitor at pin 3. Silent tuning can be achieved by omitting this capacitor.
1.5
it
0.5
0
-so SO 100 150
TWO
Figure 1. Power Denning Curve.

TDA7000 Signetics
S N
0
2
-8 20
40 10
TOD
NO SE
so
10-5 10 S 10-4 10-3 10-3 10-1
EllAF (V) at Rs 75 0
Figure 2. AF output voltage (V0) and total harmonic distortion (THD) as a function of
the e.m.f. Input voltage (EN F) with a source Impedance (Rs) of 75 0: (1) muting
system enabled; (2) muting system disabled.
Conditions: OdB = 75mV; fri = 96 MHz

for S + N curie: ± 22.5 kHz f, = 1 kHz
for THD curve = ± 75 kHz f,1 = 1 kHz
NOTES
1 The muting system can be disabled by feeding a current of about 2OptA into pin 1
2 The interstation noise levell zan be decreased by choosing a Icw-value capacitor at pin 3 Silent tuning can be achieved by omitting this capacitor
fa EMF
220pF 150pF
75
- 220pF 330pF 100nF 220pF 3.3nF

7- 330pF
Is 17 16 IS 14 13 12 10
CORRE.
LATOR
2.7K
1.4V
10K 10K
700K 7 700K
IF FILTER
AP 12K
IF LIMITER
4.7K # 4.7K
DEMODULATOR
2.2K 2.2K
13 OK
MIXER
MUTE CONTROL UTE LOOP

FILTER
VCO
Vcc
NO SE
SOURCE
Vcc 5 7
LI 55 nH 3.3nF
10K
-- 150
nF
iR 11.5nF -- 22nF -10nF Co
22K 1
ENABLED 60
= 1:184F
Cv Cs
Vcc 0
MUTE SWITCH
AF OUTPUT
Figure 3. Test Circuit

FAIRCHILD
A Schiumberger Company p. A 7 3 9 2
DC Motor Speed Control Circuit

The u.A7392 is designed for precision, closed loop, motor 14 -Lead DIP
speed control systems. It regulates the speed of capstan (Top View)
drive motors in automotive and portable tape players and
is useful in a variety of industrial and military control appli- 14
cations, e.g., floppy disc drive systems and data cartridge MOTOR STALL TIMER
DRIVE IN
drive systems. The device is constructed using the
Fairchild Planar Epitaxial process. -MOTOR WC
DRIVE IN
The µA7392 compares actual motor speed to an externally

-TECH IN DLIT EMITTER
presettable reference voltage. The motor speed is deter-
mined by frequency to voltage conversion of the input sig-
MOTOR DRIVE
nal provided by the tachometer generator. The result of OND
OUT
the comparison controls the duty cycle of the pulse width
modulated switching motor drive output stage to close the TACH IN CLAMPING DIODE
system's negative feedback loop.

PULSE TIMING V
Thermal and over voltage shutdown are included for self-

protection, and a stall -timer feature allows the motor to be PULSE OUT
REGULATOR
OUT
protected from burn out during extended mechanical lams.
Precision Performance
High Current Performance
Wide Range Tachometer Input Order Information
Device Code Package Code Package Description
Thermal Shutdown, Over Voltage And Stall
Protection pA7392DV 64 Ceramic DIP
Internal Regulator ).1A7392PV 94 Molded DP
Wide Supply Voltage Range 6.3 V To 16 V

Storage Temperature Range Voltage Applied Between Leads 3
Ceramic DIP -65°C to +175°C and 5 (Tachometer Inputs) ± 6.0 V
Molded DIP -65°C to + 150°C Ccntinuous Current through
Operating Temperature Range -40°C to +85°C Leads 11 and 12 Motor Drive
Lead Temperature Output ON 0.3 A
Ceramic DIP (soldering, 60 s) 300°C Repetitive Surge Curren: through
Molded DIP (soldering, 10 s) 265°C Leads 11 and 12 (Motor Drive ON) 1.0 A
Internal Power Dissipation' -3 Repetitive Surge Current through
14L -Ceramic DIP 1.36 W Leads 10 and 11 (Motor Drive OFF) 0.3 A
14L -Molded DIP 1.04 W
Notes
Supply Voltage (V+), V9, . 150°C for the Molded DIP, and 175°C for the Ceramic DIP
Vt0, Vii 24 V 2 Ra9ngs apply to ambient temperature at 25°C. Above this temperature,
Regulator Output Current, 18 15 mA derate the 14L -Ceramic DIP at 9.1 mW/*C, the 14L.A471ded DIP at
Voltage Applied to Lead 6 83 mW/°C
7.0 V 3 Internally Limited
(Tachometer Pulse Timing)
Block Diagram
SUPPLY
VOLTAGE
PULSE TIMING
OUTPUT
I MOTOR
DRIVER
INPUTS
SPEED
ADJUST
CLAMPING
DIODE
TACHOMETER
INPUTS A 111 os2K
MOTOR
DRIVE
OU-PUTS
PULSE
GENERATOR COMPARATOR
FREQUENCY TO
VOLTAGE CONVERTER MOTOR DRIVE
SECTION SECTION
EMITTER
'EMITTER
THERMAL
V SENSOR
REGULATOR
OUTPUT OVER
VOLTAGE VOLTAGE
REGULATOR SENSOR
PROTECTIVE
CIRCUITS
STALL TIMING
VOLTAGE REGULATOR THRESHOLD
SECTION AND LATCH
STALL TIMER

iimmummimmi
FAIRCHILD
µA7392 A Schiumberger Company
µA7392
Electrical Characteristics TA = 25°C, V+ = 14.5 V, unless otherwise specified.
Symbol Characteristic Condition Min Typ Max Unit
Voltage Regulator Section (Test Circuit 1)
Icc Supply Current Excluding Current into Lead 11 7.5 10 mA
VR" Regulator Output Voltage 4.5 5.0 5.5 V
LINER88 Regulator Output Line V+ - 10 V to 16 V 6.0 20 mV

Regulation (AV8)
V+ = 6.3 V to 16 V 12 50
LOADReg Regulator Output Load i8 from 10 mA to 0 40 mV
Regulation (AV8)
Frequency to Voltage Converter Section (Test Circuit 2)
VIN Tachometer (-) Input Bias 2.4 V
Voltage
'IN Tachometer ( + ) Input Bias V5 - V3 1.0 10 µA

Current
VDIFF Tachometer Input Positive (V5 - V3) 10 25 50 mVP-P
Threshold
Vily Tachometer Input Hysteresis 20 50 100 mVP-P
R Pulse Timing ON Resistance V6 - 1.0 V 300 500 SI
VTH Pulse Timing Switch Threshold 45 50 55 %V8

4 Output Pulse Rise Time 0.3 PS
tf Output Pulse Fall Time 0.1 tiS
VSet-LOW Pulse Output LOW Saturation 0.13 0.25 V

(V7)
VSat-Hi Pulse Output HIGH Saturation 0.12 0.2 V

(Vs - V7)
lsoorce Pulse Output HIGH Source V7 = 1.0 V -340 -260 -180 PA
Current
SVS Frequency -to -Voltage Conversion VF -v - 0.25 V82 0.1 %
Supply Voltage Stability' V, . 10 V to 16 V
TS Frequency -to -Voltage Conversion VFN - 0.25 V82 0.3 %
Temperature Stability3 TA - -40°C to +85°C
Motor Drive Section
Vic Input Offset Voltage 20 mV
ilB Input Bias Current 0.1 10 AlA
CMR Common Mode Range 0.8 2.5 V
Vskr Motor Drive Output Saturation Iii = 300 mA 1.3 2.0 V
'LEAK Motor Drive Output Leakage V11 -V10= 16 V 5.0 mA

ID Flyback Diode Leakage V10 - 16 V, V11= 0 V 30 ;A
VD Flyback Diode Clamp Voltage III = 300 mA 1.1 1.3 V
Motor Drive Output OFF
Protective Circuits
J-T°C Thermal Shutdown 160 °C
Junction Temperature
Over Voltage Overvoltage Shutdown's '8 21 24 V
VTH Stall Timer Threshold Voltages 2.5 2.9 3.5 V
ITH Stall Timer Threshold Currents 0.3 3.0 PA
Note*
1 Frequency -to -voltage conversoon, supply voltage stability is defined Is.
VR(16 V) VFy(10 V) VF(14.5 V)
x 100%
V.(16 V) V.(10 V) V.(14 5 V)
2 VFii is the integrated DC output voltage from the pulse generator
(Lead 7)
3. Frequency -to -voltage convensron temperature stability is defined as
VFy(85°C) VFy(-40°C) VFv(25°C)
x 100%
Ve(85°C) Ve(-40°C) Ve125°C)
4 Motor Drive ClfiClairy ,s disabled when these limits are exceeded. If the
condibon continues for the durabon set by the external stall toner
components, the circuit is latched off until reset by temporanly opelinq
the power supply input line
5 If stall toner protection is not required. lead 14 should be grounder

FAIRCHILD
µA7392 A Schlumberger Company
Typical Performance Curves

Overvoltage Shutdown Voltage vs Stall Timer Threshold Voltage vs Stall Timer Threshold Current vs
Junction Temperature Junction Temperature Junction Temperature
0.1
26
V 14.6 V v. 14 IV
1.4 0.7
I )4 I
S 12 a0$
S 1D
U
0
0.4
g"
g11
22Zi
"
17
-10 -25 0 as 50
JUNCTION TEMPERATURE -
75 ISO 125 150
26
12
2.0
-50
\\N\-25 0 25 SO
Jam.C75014 TEINERATURE -
75 100 125 150
I 63
6.2
Cl
0
so -25 0 25 SO 75
JUNCTION TEMPERATURE -
IN 125 1St
.1.1111, PC31113..
Supply Current vs Regulator Output Voltage vs Regulator Output Voltage Vs
Supp y Voltage Supp y Voltage Junction Temperature

12
V. 14.3 v
TJ 216C- T.5 NM -
10 s
16
2
r'
oo
4 S 52 54 20 24 't) 4 0 12 III 20 24
4.6
-r -M 0 M 50 70 100 in
SUPPLY 000TAGE - v SUPPLY VOLTAGE - V JUNCTION TEMPERATURE -
10311:1,01, Nam"
Tachometer Input Hysteresis vs Flyback Diode Current (D3) vs Motor Drive Output ON Current vs
Junction Temperature Flyback Diode Voltage Motor Drive Output ON Voltage
SOO 1106
V. 14-11 V
V. 14.5J 1 V.. 541 J
700
l',5 TA WIC
1 MN T, TA arc
MO
1""
u roe
V 100 r g
i
S
0 444 1100
8 NI
5 sm 12
t MO
i 'lc
; NM
0 0
-36 0 NI 60 76 100 in ISO
0 0
JUNCTION TEMPERATURE - FLYBACK 01001 VOLTAGE -V MOTOR DRIVE OUTPUT ON VOLTAGE -V

oere..31. .13014Xf
Motor Drive Output ON Voltage vs Typical Application Using Magnetic Tachometer

Ambient Temperature
330 on
1.Y
Rs C
I I.44
0.1 90 SPIED
ADJUST
1.42
100 90
0 10 150 14
1.40
0.01 0 I
2 13
110
200 3 12
MOTOR
4 11
1.34
10
1.32 SO 10 0 TO 16 V
103 150
5.30
-50 -26 60 100 is)
0 26
AmoieNT TEMPERATURE - C
75 120
Ts
TG
100 ILO
TYPI0.01 000.111060nt velum
1
4 R Pf Iw TACHOMETER
V(I NOMINAL
C7 10 C P IP 1000 Co rorono on TACHOMETER
systol requweenonts FREQUENCY)
2 0 $1511 0u1 -out
Cs Rs
50
9
M112
Polyphonic Sound Generator

8µP PROGRAMMABLE SOUND GENERATOR CHANNELS
2MHz CLOCK
INTERNAL TOS WITH POSSIBILITY OF EXTERNAL SYNCHRONIZATION FOR MULTICHIP USE
6 COMPLETE OCTAVE KEYBOARDS (72 KEYS)
FIVE HOMOGENEOUS FOOTAGES µP PROGRAMMABLE BY ADDING A CONSTANT K TO
THE KEYBOARD SITUATION
SEVEN OCTAVE RELATED OUTPUTS ENVELOPED WITHOUT CONSTANT DC LEVEL (4
FOOTAGES)
SEVEN FOOTAGE RELATED OUTPUTS WITH DIFFERENT CONFIGURATIONS FOR:
FOOTAGES WITH ENVELOPE (WITHOUT CONSTANT DC LEVEL) AND
FOOTAGES WITHOUT ENVELOPE (WITH CONSTANT DC LEVEL) AND
VARIOUS SOUND CHANNEL DIVISIONS (SEE OPTION I, II AND III).
POSSIBILITY OF EXCLUDING ONE OR MORE SOUND CHANNELS FROM THE NON ENVEL-
OPED FOOTAGE OUTPUTS
ONE MONOPHONIC OUTPUT NON ENVELOPED RELATED TO SOUND CHANNEL 1 WITH
THE POSSIBILITY OF CHOOSING THE FOOTAGE (TWO ADDITIONAL MONOPHONIC OUT-
PUTS ON OPTION II).
50% DUTY CYCLE ON ALL OUTPUTS
DIGITAL DRAWBAR CONTROL (32 LEVELS)
ATTACK -DECAY -SUSTAIN -RELEASE (ADSR) ENVELOPE DEFINITION WITH DIGITAL CON-
TROL ON A.D.R. AND ANALOG CONTROL ON S
ADDITIONAL ANALOG CONTROL ON RELEASE
ANALOG PERCUSSION INPUT TO ENVELOPE ONE FOOTAGE (M2) ON THE QCTAVE RE-
LATED OUTPUTS
SPECIAL EXTERNAL ENVELOPE POSSIBILITY USING HOLD AND/OR RELEASE 00.
HOLD AND RELASE 00 ARE DEDICATED TO DECAY AND PEDAL EFFECT.
N -CHANNEL TECHNOLOGY - 12V SINGLE SUPPLY.
The M112 is a polyphonic sound generator that combines eight generators with envelope shapers and
drawbar circuitry in a single package.
This versatile circuit simplifies the design of a wide range of polyphonic instruments and, interfacing
directly with a microcomputer chip, gives designers an unprecedented degree of flexibility.
The M112 is realized on a single monolithic silicon chip using low threshold N -channel silicon gate MOS
tecnology. It is available in a 40 lead plastic package.
ABSOLUTE MAXIMUM RATINGS

,.DD Supply voltage -0.3 to 20 V
VI Input voltage -0.3 to VDD
VO(off) Off state output voltage -0.3 to 20 V
Ptot Total package power dissipation 500 mW
TStg Storage temperature -65 to 150 °C
Top Operating temperature 0 to 70 °C
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this' specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
All voltages are with respect to V55.
MECHANICAL DATA (Dimension in mm) PIN CONNECTIONS

ANALOO GROUSAND
V
7---LI-770)016
vSS 2 )056
STRODE -SW 3 3e)oa
OCTAVE
RESET 4 37 )06E
OUTPUTS
CLOCK 5 16102E
01 6 036
131 7 07E
02 8 33 CMS
DATA
SUS 04 9 12 CM6
DS 0 31 CH7
06 II 30 CMV 'CAPACITORS
ADP CONTROL -VT is FOR ENVELOPE
2 CMS
V00 3 28 Cu,
FLLI 271CM1
8082 IS 2 CNI
F021 16 25 3K4A.ANALDG RELEASE
FOOTADES 'HIE
OUTPUT
17 24 34,5,8 Ac.,
FH1E 23 VSUSTAINfrONTROL
FLE 19 22 )PERC 02
FL 20 2, )Cllr -MONOPHONIC OuT
5.160
RECOMMENDED OPERATING CONDITIONS

Values
Parameter Test conditions Unit
Min. NIL Mex.
VDD Highest Supply Voltage 11.4 12 12.6 V

M112 us
BLOCK DIAGRAM
Fig. 1 -
PHASE
- GENERATOR
11:11-1==
Na VffllOnD
OVIPUIS
MULTIPLEXER FOOTAGE thiVE.0.10

VCA OuITVIS
ADSR
CHANNEL I
OC TA VE Bun
KA OHMS
Rf =."; MR
REG I -II
SIAM - SOUND
CHANNEL 7
CRAPPML
WO CONTROL AT
OK. 'AL
REG CONTROLS FCRI
ONWARDS ENVELOPES .ksuo.
CONTROL
AND MAC 612
DRAWBARS al.1.011M
Vitt.%
rryA
RtstI
STATIC ELECTRICAL CHARACTERISTICS

(VDD = 12V ± Vss = OV, Tamb = 0 to 50°C unless otherwise specified)
Parameter Test conditions Min. Typ. Max. Unit
INPUT SIGNALS
VIH Input High Voltage Pins 3, 6 toll 2.4 VDD V
All other inputs 6 VDD V
VIL Input Low Voltage Pins 3, 6 to 11 -0.3 0.8 V
All other inputs -0.3 1 V
VSA Analog Ground R< Ion C= 100µF 0 0 1 V
VT ADR Control Time R = 1K C = 1µF 0 VDD V
VAR Analog Release R = 10K C = 0.1µ 0 VDD V
Vreg Control OFF Asymptote R < 10f1 C = 100p 0 0 1 V
VSUST Control Level Sustain R = 1K C = 100µ 0 VDD V

Perc. M2 Control Level Percussion R = 10K 0 VDD V
/LI Input Leakage Current Vi = VDD 1 . 0A
OUTPUT SIGNALS (One key pressed)

IOL Output Low current - Vol_ ` VDD/2-1v (note 1) 10 30 50 1.1A
VOH . V DD/2+1 v (note 1) 10 30 50 µA

1 OH Output High Current VOH 10y (note 2) 100 300 500 pA
VOH = 10V 10 30 50 pA
Vo VDD (all output pins) 1 uA
loot f) Off state output current
Vo = Vgg (pins 14-15-20 in -1 uA
3rd state)
POWER DISSIPATION
100 Supply current Tamb' 25°C 50 mA
Notes: 1. Refers only to FL, FM1, FM2 (pins 20, 15, 14).
2. Refers only to octave outputs with drawbar max.
DYNAMIC ELECTRICAL CHARACTERISTICS

Parameter Test conditions MM. Typ. Max. Unit
CLOCK
fl Input Clock Frequency 250 2000 24 2.300 kHz
tr, tf Rise and Fall Times 10% to 90% 30 ns
ton, tort ON and OFF Times 150 ns
RESET
tw Pulse Width Clock = 2 MHz 10 me
ti Fall Time 30 ns
OUTPUT SIGNALS
ton, toff Outptu duty cycle 50

M112
GENERAL DESCRIPTION
The M112 contains a microprocessor interface, eight programmable sound generator channels, a top
octave synthesiser, a divider chain and control circuitry, (see fig. 1). Each generator consists of logic to
select the desired notes and harmonics from 96 frequencies obtained by division, an ADSR envelope
generator and two voltage -controlled amplifiers. Programmable attenuators are included for drawbar
control of the harmonic content of the sound.
To simplify system design the signals generated in each channel are directed to octave separated outputs
and footage outputs. Two voltage -controlled amplifiers are provided for each channel to keep the octave
and footage outputs separate.
The attack time, decay time, release time and sustain level are set for all eight channels by common
controls. Tone selection, the attack, decay, release parameters, drawbars and special effects are all soft-
ware controlled.
In a typical configuration (fig. 2), one or more M112s are connected to a microprocessor which scans
the keyboard and front panel controls in a matrix arrangement. When the microprocessor detects a key
depression chooses one of the sound generators and allocates it to that note. If another key is pressed
the microprocessor allocates another sound generator and so on. This process can be repeated until there
are no more free channels, i.e. when 8N keys are pressed simultaneously where N is the number of
M112s used.
When one of the keys is released the microprocessor resets a control bit in the appropriate generator
channel which will then be re -allocated to another key when needed.
Fig. 2
KE,OO.00S Dl ,o 126
040 Ncu'' M112

COm.ANOS
S222COES SIO
M112
M112
OUTPUTS
The M112 has 15 music output pins. Seven of these are octave outputs, seven are footage outputs and
the last is a monophonic output from channel ore. This standard configuration can be changed under
program control.
The octave outputs, which are enveloped, are so called because there is one output for each octave, i.e.
output signals from all eight channels that fall within the same octave are routed to the same output.
These outputs are provided to simplify the generation of sinewaves from the squarewaves generated by
the M112s digital circuitry. Since each of these outputs handles a limited range of frequencies - exactly
one octave - a simple low pass or bandpass filter will do the job. The blend of harmonics sent to the
octave outputs is controlled by the drawbar attenuators.
The footage outputs are related to the five footages generated by the M112. These are referred to as L,
Ml, M2, H1 and H2 = Low, M = mid, H = high) and can be programmed to give the three different
ranges given in table 1, adding a constant K (number of half tones) to the keyboard information.
All five footages can be obtained from these outputs but only four are mixed by the drawbar circuitry
and routed to the octave outputs.
TABLE 1 - THE THREE FOOTAGE RANGES OF THE M112

Enveloped footage outputs (option 21
Octave outputs
Non Enveloped Footage Outputs
Footags
L M1 M2 H1 H2
K
0 16' 8' 4' 2' 1'
7 10 2/3' 5 1/3' 2 2/3' 1 1/3' 2/3'
4 12 4/5' 6 2/5' 3 1/5' 1 3/5' 4/5'

M112
Fig. 3 - Example of octave related output "EVEN" and "ODD" with Percussion input.
124
M112 °I sh 32 -123 Hz
02 130-246 Hz
(WOW 21
03 261-493 Hz
04 hr 923 -9117Hz
Perc (4') OS 1046-197511z
06 7093 -396111z
07 o 4166- 7902Hz
Note All the notes higher

than 7902Hz are available
M112 01 divided bye
213.5113' ,2r3)1(2') 02
03
04
OS
- Fi.rc (22")
06
07
In no case will the maximum frequency be higher than 7902 Hz (with a 2 MHz clock).
The output configuration for the octave and footage outputs can be changed under program control as
mentioned above. There are three options, including the standard configuration, and these are:
Option 1, the normal configuration gives four enveloped footage outputs, LE, M1E, M2E, H1E, and
three non -enveloped outputs, L, M1 and M2. All eight channels are present on each output.
Option 2 is a special configuration for sawtooth generation (sawtooth waveforms are frequently used
in sound synthesis). In this case channels two and three appear only on the outputs FM1 and FM2
(footages M1 and M2) and are excluded from the rest. All five footages are available as enveloped
outputs.
Option 3 is intended for sophisticated automatic accompaniment circuits. All the channels appear on
three non -enveloped outputs (FL, FM1, FM2) for chord generation and can be disconnected or
command. Channels 4, 5, 6 and 7 appear on four enveloped outputs for arpeggi. The octave outputs
are used for the bass and include only channel 8.
TABLE 2 - OUTPUT CONFIGURATIONS
Pin I Option I Option II Option III Option IV
15 FM2 FM2 (Channel 31 FM2 FM2 (Ch. 3)

All channels
14 FM1 FM1 (Channel 2) FM1 FM1 (Ch. 2)
(see note 31
20 FL FH2E FL FH2E (Ch. 4, 5, 6, 7,8)
18 FH1E FH1E FH1E FH1E
16 FM2E FM2E FM2E only channels FM2E only channels
17 FM1E FM1E FM1E 4-5-6-7 FM1E 4-5-6-7
19 FLE For the FLE FLE FLE
40 01E 8 channels 01E 01E 01E
Only channels
36 02E 02E 1-4-5-6-7-8 02E 02E
35 03E 03E 03E 03E
04E 04E only channel 8 04E only channel 8
38 04E
39 05E 05E 05E 05E
37 06E 06E 06E 06E
34 07E 07E 07E 07E
21 Monophonic out Mono Mono Mono
(channel 1) (channel 1) (channel 1) (channel 1)
Standard use Special for sawtooth Special for high class Only for Information
generation etc. accompaniment (no musical meaning)
- FL, FM1, FM2 are footage outputs not enveloped (with constant DC level)
- FLE, FM1E, FM2E, FH1E, FH2E are enveloped (without constant DC level).
Notes: 1) H2 is available only in option 2 on FH2 enveloped outputs. It is not available on octave related outputs.
2) In the option 2 the Sound channels 2 and 3 are available oily on pins 14 and 15 and consequently are
excluded from the other outputs.
3) Each channel can be disconnected with commands NC1 to NC8 (register 10).

M112
DRAWBARS AND EFFECTS
One of the significant features of the M112 is the implementation of drawbar control circuitry. This
consists of our programmable attenuators, one for each of the footages routed to the octave outputs,
which are used to blend harmonics to produce the desired sound.
Other featu-es of the MI12 include hold, pedal end percussion effects, all of which are enabled/disabled
under software control. Hold, when active, inter-upts the decay of the ADSR envelope and Pedal inter-
rupts the release curve. Hold and pedal permit external control of the envelope. This feature can be
used, for example, to synthesize very realistic piano and harpisichord sounds.
A piano effect can be produced by suitably programming the envelope shapers but by using the hold
and pedal controls and a few external componerts much greater realism can be obtained. Fig. 4 shows
a simplified schematic of one of the envelope shapers together with the type of envelope generated. The
envelope parameters are controlled by RA, RD, RR and Vsus (RA, RD and RR are programmed resistors
controlling attack, decay and release). Disabling the natural decay and release and adding a handful
of components a close approximation to the ideal waveform can be produced (fig. 5). RI is a very large
resistance (typically 3 MS2) to give the long (several -seconds) time constant for the second decay.
Fig. 4 - Witn an external capacitor the MI12's envelope shapers produce the standard ADSR envelope.
M112
1.1411
Fig. 5 - Disabling the normal decay and release and adding a few external components a realistic piano
envelope can be produced.
MIIl
s -S140
INPUTS
Eight pins on the M112 are used to define the elementary time interval of the ADSR envelope shapers
(Pins 26 to 33). Capacitors, nominally 11.1F, are connected to these pins. Eight separate capacitors are
necessary because the envelope shapers are independently triggered. Analog inputs are also provided to
adjust the asymptotic release level (Vres, pin 24) and the charge/discharge current for attack, decay and
release (VT pin 12) in order to compensate the differences of ADR time constant between several
M112s used in the same instrument.
The sustain level is fixed by the voltage at pin 23.
The release time constant, digitally controlled by software, can also be fine adjusted by a trimmer con-
nected at pin 25.
PROGRAMMING
The M112 is programmed using five basic commands:
CHANNEL PROGRAM
ADSR PROGRAM
NON -ENVELOPED OUTPUT MASK
LOAD CONTROL REGISTER
DRAWBAR PROGRAM

M112
These commands all consist of 12 bits transferred to the M112 (or one of the M112s) in two six -bit
bytes through six data lines. Data is latched into the M112 synchronously by a strobe signal. The M112
can be connected directly to an M387X series microcomputer.
Each command contains the address of the Register in which data is to be memorized (there are 16 re-
gisters) and the data.
Channel program commands consist of the channel code (4 bits), octave code (3 bits), note code (4 bits)
and a control bit, KP (key pressed). KP must be set if the key has just been pressed and reset if the note
has just been released.
DI D6
CHANNEL KP 02 CHANNEL
PROGRAM
01 00 NOTE
Resetting KP does not necessarily silence the channel because the sound continues after the key has been
released if the release time is non -zero. To stop a channel completely the unused note and octave codes
are used.
If an unused note code is programmed the channel is turned off with the output transistor in the ON
state and if an unused octave code is used the channel is turned off with the output transistor in the
OFF state. Six octave codes and twelve note codes are recognized, giving a keyboard span of 72 keys.
For example, to tell an M112 that channel three is to play F# in the third octave the command is:
Dl D6
CHANNEL 3 CODE IS 0010
0 0 1 0 1 0 OCTAVE 3 CODE IS 011
F It NOTE CODE IS 0110
1 1 0 1 1 0 KP IS SET
The ADSR Program command sets the attack, decay and release times for all the envelope shapers.
This command takes the form:
DI D6
1 r3 r2
ADSR
PROGRAM
rl d2 dl a3 a2 al
The code 1000 selects the ADSR control register, a3/a2/a1 is the attack time, d2/d1 is the decay time
and r3/r2/r1 is the relase time. These times are all multiples of the time interval set by external ca-
pacitors. With the suggested 1µF values this time interval is 15ms. The release code 000 is used to enable
the pedal effect.
The Non -Enveloped Output Mask command is used to select which channels are to -be routed to the
non -enveloped footage outputs. Any or all of the eight channels can be excluded by setting the appro-
priate bit.
DI D6
1 0 0 1 NC8 NC7 OUTPUT

MASK
NC6 NC5 NC4 NC3 NC2 NC1
The Load Control Register command selects the footage and output options and enables/disables the
hold and percussion facilities.
DI 06
1 0 1 0 PO
LOAD CONTROL
REGISTER
HOLD OP3 OP2 NC1m m2 m1
"NCIm" is a control bit that excludes channel one from all outputs except the three non -enveloped
footages outputs. PO is the percussion disable bit, m2/m1 is the footage option select code for the mo-
nophonic output and OP2/0P1 the output configuration select code.
The drawbar -controlled attenuators are set independently for each footage using the Dravigbar Program
Command which has the form:
DI 06
FOOTAGE DRAWBAR
PROGRAM
ATTENUATION
Footage is selected by addressing registers R12 to R15.

Attenuation is controlled in 32 linear steps which can be conveniently reduced to the conventional 16 or
8 -step logarithmic scale using a lookup table.
APPLICATIONS
The M112 is intended for a wide range of applications ranging from simple single -keyboard organs to
2-3 manual instruments with sophisticated synthesis and accompaniment facilities. It can also be used
in electronic pianos, harpsichords, string synthesizers etc.

M112
DESCRIPTION
Pin 1 - VSA Analog ground
Ground connection of all outputs. It is typically connected to Vss. By adjusting its value with respect
to Vss (plus/minus) it is possible to modify the output current and compensate the differences in cur-
rent between several M112s used in the same applications.
Pins 2 and 13 - Vss, VDD

Power supply connections. VDD is nominally 12V; Vss is to be connected to GND.
Pin 4 - Reset input

It is used to synchronize various M112s in multichip use. The reset is activated when the input is at H
Level. In this condition the chip is blocked.
Pin 5 - Clock input
It has to be ccnnected to an external oscillator of 2 MHz.
Pin 6 to 11 - D1, D6 Data bus input

Pin 3 - STD Data Strobe input
These pins are used to transfer the 12 bits of data from the microprocessor to the registers of various
M112s using a two phase procedure.
The first six bits of data are latched on the positive edge of STD, while the other six bits are latched on
the negative edge of STD.
-06
CIED=CIIf
>0, ?, ips >0 z2,..
S MO<
Each 2 x 6 bit of information contains the address of the register (4 bit/16 registers) and the data up to
8 bits to be memorized in the selected register.
161 PHASE 20d PHASE
0, 06 01 06
A3 A2 Al AC X S 6 6 X S 1I
ADDRESS OFT THE DATA

REGISTER
St ,5
TABLE 3 - REGISTER SELECTION

AO Al A2 A3 Register n° Register function
o o 0 0 1
1 0 0 0 2
o 1 0 0 3
1 1 0 0 4 Note -octave etc.
0 0 1 0 5 For Sound channel
1 0 1 0 6
0 1 1 0 7
1 1 1 Q 8
0 0 0 1 9
1 0 0 1 10
0 1 0 1 11
1 1 0 1 12 Control Commands
0 0 1 1 13
1 0 1 1 14
0 1 1 1 15
1 1 1 1 16 Used for test
This address sets the Ic in a test condition that can only be modified by a Reset command on pin 4.
Registers 1 to 8
There registers are related to the sound channels
Bus Data
D1 A3 must be "0"
D2 A2 Sound
PHASE 1
D3 Al Channel
D4 AO Selection
D5 KP
D6 02
01 01
Key
D2 00 information
D3 N3
PHASE 2 D4 N2
D5 N1
D6 NO
AO -A2: Sound channel selection with reference to table 3, register 1 is related to channel 1, register 2 to
channel 2 and so on up to channel 8.

M112
KP : 1 = pressed key 0 = related key

00-01-02: Octave code of the note (Table 4).
TABLE 4 00 01 02 Cods Octave
0 0 0 0 Note OFF
1 0 0 1 1
0 1 0 2 2
1 1 0 3 3 Output
transistor
0 0 1 4 4 "OFF"
1 0 1 5 5
0 1 1 6 6
1 1 1 7 Note OFF
N0 -N1 -N2 -N3 = Note Code (Table 5)

TABLE 5 NO N1 N2 N3 Code Note
0 0 0 0 0 DO
1 0 0 0 1 DO#
0 1 0 0 2 RE
1 1 0 0 3 RE#
0 0 1 0 4 MI
1 0 1 0 5 FA
0 1 1 0 6 FA#
1 1 1 0 7 SOL
0 0 0 1 8 SOL#
1 0 0 1 9 LA
0 1 0 1 10 LA#
1 1 0 1 11 SI
0 0 1 1 12 Note "OFF"
1 0 1 1 13 Note "OFF" Output
0 1 1 1 14 Note "OFF" transistor
"ON"
1 1 1 1 15 Note "OFF"
Register 9 to 15
These registers are related to the various control commands
TABLE 6
Register
Data R9 R10 R11 R12 R13 R14 R15 R16
Bus
DI 1 1 1 1 1 1 1 1
02 0 0 0 0 1 1 1 1
D3 0 0 1 1 0 0 1 1
PHASE 1
D4 0 1 0 1 0 1 0 1
D5 r3 NC8 X X X X X X
06 r2 NC7 PO X X X X X
01 rl NC6 HOLD X X X X X
D2 d2 NC5 OP3 L5 MI 5 M2 5 HI 5 X
D3 dl NC4 OP2 L4 MI 4 M2 4 H1 4 X
PHASE 2
04 a3 NC3 Not m L3 MI 3 M2 3 H1 3 X
05 a2 NC2 m2 L2 MI 2 M2 2 H1 2 X
D6 al NC1 ml LI M1 1 M2 1 HI 1 X
Envelope Channel Various Drawbar level on four Test

off footages only for
octave outputs
Register 9 - R9 selects the ADR envelope parameters for ADSR control (see fig. 6)
Attack - al - a2 - a3 = 3 bit
Decay - dl - d2 = 2 bit 8 bit
Release - rl - r2 - r3 = 3 bit
Fig. 6 - ADSR envelope control
KEY
PRESSED 1
WITH HOLD (SEE REGISTER10)
VSUSTAIN PEDAL EFFECT (SEE TABLE 7)
ENVELOPE ASYMPI LEVEL v

(PIN 24)
ATTACJC I DECAY I, SUSTAIN RELEASE
3 BIT 2 BIT I (CONTROLLED 313IT
Cal a2a311 (dl d2) BY VOLTAGE (01.20)
ON PIN 23)

M112
Table 7 shows the various time constants for Attack, Decay and Release.
TABLE 7
a3 a2 at Attack
d2 dl Decay
r3 r2 rl Release
0 0 0 T/2 47 00
0 0 1 T 8T T
0 1 0 2T 16T 2T
0 1 1 41 321 4T
1 0 0 8T 8T
1 0 1 16T 16T
1 1 0 32T 32T
1 1 1 64T 64T
In this case it is possible to obtain the pedal effect.

T = 3 ms is the typical time constant unit with 8 external capacitors of
1 ALF connected to pins 26 to 33.
Register 10 -Contains 8 commands to exclude the corresponding sound channel from the non -enveloped
footage outputs (FL-FM1-FM2)
0 = ON 1 =OFF
Register 11 - Contains the following 8 commands: ml and m2 select one of the four footages available
for the monophonic output (C1m) according to table 8.
TABLE 8
ml 0 1 0 1
m2 0 0 1 1
0 16' 8' 4' 2'

K 7 10 2/3' 5 1/3' 2 2/3. 1 1/3'
4 12 4/5' 6 2/5' 3 1/5' 1 3/5'
OP2-0P3 - Select the four output options described in table 1 according to table 9.
TABLE 9
r--------____ BIT
OP2 OP3
OPTION
I 0 0
II 1 0
III 0 1
IV 1 1
HOLD - If 0, disconnects the external 8 capacitors of envelope (1 pF) and the V SUSTAIN Pin (pin 23)
in the decay phase.
PO (Percussion Off) - If 1, the percussion input is inhibited (see pin 22 description).
NC1m-I f 1, eliminates channel 1 from all outputs except the 3 footage outputs not enveloped (it can be
eliminated from these outputs through the command NC1 of register 10).
N.B. NC1m command is inoperative on the monophonic output (C1m) where channel 1 is always pre-
sent.
Registers 12-13-14-15
These registers contain the drawbar control for 4 footages on the octave related output.
Footages L, M1, M2 and H1 are controlled in 32 linear levels or for example, using conversion table in
the microprocessor in 8 or 16 logarithmic levels.
Table 10 shows an example of footage L with 32, 16 and 8 step control in dB.
Pin 12 - VT - ADR Control

It is used to adjust the ADR time constant for several M112s used in the same application. Using a single
M112 it has to be connected to VD°.

M112
TABLE 10
L
5 4
L.1.1-
3 2
L
1
Animation in dB
32 steps 16 steps a stps
0 0 0 0 0 OFF OFF OFF
0 0 0 0 1 -29.8 -29.8 -29.8
0 0 0 1 0 -23.8 -23.8 -23.8
0 0 0 1 1 -20.3 -20.3 -20.3
0 0 1 0 0 -17.8 -17.8
0 0 1 0 1 -15.8 -15.8
0 0 1 1 0 -14.3 -14.3 -14.3
0 0 1 1 1 -12.9
0 1 0 0 0 -11.8 -11.8
0 1 0 0 1 -10.7
0 1 0 1 0 -9.8 -9.8
0 1 0 1 1 -9.0 -9.0
0 1 1 0 0 -8.2 -8.2
0 1 1 0 1 -7.5
0 1 1 1 0 -6.9 -6.9
0 1 1 1 1 -6.3
1 0 0 0 0 -5.7 -5.7
1 0 0 0 1 -5.2
1 0 0 1 0 -4.7
1 0 0 1 1 -4.2 -4.2 -4.2
1 0 1 0 0 -3.8
1 0 1 0 1 -3.4
1 0 1 1 0 -3.0 -3.0
1 0 1 1 1 -2.6
1 1 0 0 0 -2.2
1 1 0 0 1 -1.9
1 1 0 1 0 -1.5 -1.5
1 1 0 1 1 -1.2
1 1 1 0 0 -0.9
1 1 1 0 1 -0.58
1 1 1 1 0 -0.29
1 1 1 1 1 0 0 0
Pin 14 to 20 - FM1, FM2, FM2E, FM1E, FH1E, FLE, FL (Footages output)

The "wired -or" function is possible on all outputs.
The non enveloped outputs (with constant DC level) are push-pull current generators.
The enveloped outputs (with non constant DC level) are open drain sink current generators. Output duty
cycle is 50%.
Pin 21 - C1m
Monophonic output of channel 1 (always present). Duty cycle of the waveform is 50%.
Pin 22 - Percussion M2
Using a specific signal on this input it is possible to have a percussion effect on M2 footage for the octa-
ve related output.
Pin 23 - V SUSTAIN
This input defines the level of sustain (see fig. 6).
Pin 24 - \inn
This pin controls the asymptote of V RELEASE through the gate of a transistor which discharges the en-
velope capacitor. If the performance at the end of release time is considered satisfactory, this pin must
be connected to Vss. Otherwise this input can be connected to a voltage not higher than 1V.
Pin 25 - VAR Analog release
This pin is intended for analog control of the release time constant when it is required in addition to the
digital one controlled by software.
men
s-sve
It allows intermediate values not included in table 7 (see explanation of register 9). In the case of pedal
effect connect this input to Vss.
Pin 26 to 33 - CH1, CH8 Envelope capacitor inputs

8 capacitors (typical value = 1µF) have to be connected for the ADSR envelopes.
Pin 34 to 40 - 01E, 07E Octave Outputs

Octave related outputs. Duty cycle is 50%.

NE572 Signetics
Programmable Analog Compandor

DESCRIPTION BLOCK DIAGRAM
The NE572 is a dual channel, high perfor-
mance gain control circuit in which either
channel may be used for dy-iamtc range
compression or expansion. Each channel 17,91 (510
has a full wave rectifier to det act the aver- IS B11
age value of input signal; a linearized, tem- (6.10)

perature compensated variatle gain cell
(..1G) and a dynamic time corstant buffer.
The buffer permits independent control of
dynamic attack and recovery tine with mini-
mum external components and improved low Owed CELL
frequency gain control ripple distortion over

previous compandors. (1.15)
The NE572 is intended for noise reduction in (3.131

high performance audio systems. It can also
be used in a wide range of communication
101( BUFFER 106
systems and video recording applications. 270 RECTIFIER
11111
(161 VW 5iZ
PS
FEATURES
Independent control of attack and
recovery time.
Improved low frequency gall control (al (4.12) (2.14)
ripple
Complementary gain compression and
expansion with external Op Amp Note
I Supplied only in large SO (Small Outline) package.
Wide dynamic range-greater than
110dB
Temperature compensated gain
control ABSOLUTE MAXIMUM RATINGS
Low distortion gain cell PARAMETER RATING UNIT
Low noise -64V typical Supply voltag a 22
VCC VDC
Wide supply voltage rang -6V -22V TA Operating terrperature range 0 to 70 °C
System level adjustable with external Power dissipation 500
PD mW
components.
AUDIO SIGNAL PROCESSING IC control ripple for low frequency signals is

APPLICATIONS
much lower than that of a simple RC ripple
Dynamic noise reduction system COMBINES VCA AND FAST AT- filter As a result the residual third harmonic
Voltage control amplifier TACK -SLOW RECOVERY LEVEL distortion of low frequency signal in a two
Stereo expandor SENSOR quad transconductance amplifier is greatly
Automatic level control
In high performance audio ga n control appli- improved. With the 1.0µF attack capacitor
High level limiter cations it is desirable to independently con- and 4.7uF recovery capacitor for a 100HZ
Low level noise gat trol the attack and recovery lime of the gain signal the third harmonic distortion is im-
State variable filter control signal This is true, for example, in proved by more than 10db over the simple
compandor applications for noise reduction RC ripple filter with a single 1.00F attack
In high end systems the input signal is usual- and recovery capacitor, while the attack
ly split into two or more frequency bands to time remains the same.
PIN CONFIGURATION optimize the dynamic behavior for each The NE572 is assembled in a standard 16 pin
band This reduces low frequency distortion dual in line plastic package and in oversized
D, N PACKAGE
due to control signal ripple, phase distor- SO (Small Outline) package. It operates over
tion, high frequency channe overload and wide supply range from 6V to 22V. Supply cur-
TRACK TRW A
noise modulation Because of the expense rent is less than 6mA. The NE572 is designed
UCC
in hardware, multiple band signal process- for consumer application over a temperature
RECOV CAP A TRACK TRIP B
ing up to now was limited to professional range 0-70°C. The SA572 is intended for appli-
RECT A RiEcov CAP B audio applications cations from - 40°C to 85°C.
ATTACK CAP A RECT IN With the introduction of the Signetics NE572
,G OUT A ATTACK CAP 11 this high performance noise reduction con-
cept becomes feasible for consumer hi fi NE572 BASIC APPLICATIONS
TiC TRW A .s OUT B
applications The NE572 is a dual channel Description
aG IN IC RW5
gain control IC. Each channel has a linear- The NE572 consists of two linearized, tem-
GROUND _1.2 INS
ized, temperature compensated gain cell perature compensated gain cells (..1G) each
and an improved level sensor In conjunction with a full -wave rectifier and a buffer amplifi-
(Top view) with an external low noise op amp for current
er as shown in the block diagram. The two
to voltage conversion, the VCA features low channels share a 2.5V common bias refer-
ORDER PART NO.
distortion, low noise and wide dynamic ence derived from the power supply but oth-
NE572N SA572N
SA572F NE5720 SA572D
range. The novel level sensor which pro- erwise operate independently. Because of
vides gain control current for the VCA gives inherent low distortion, low noise and the
lower gain control ripple and independent capability to linearize large signals. a wide
control of fast attack, slow recovery dynam- dynamic range can be obtained. The buffer
ic response. An attack capac for CA with an amplifiers are provided to permit control of
internal tOK resistor RA defines the attack attack time and recovery time independent
time TA The recovery time TR of a tone of each other. Partitioned as shown in the
burst is defined by a recovery capacitor CR block diagram, the IC allows flexibility in the
and an internal 10K resistor RR. Typical at- design of system levels that optimize DC
tack time of aMS for the high frequency shift, ripple distortion, tracking accuracy
spectrum and 40MS for the low frequency and noise floor for a wide range of applica-
band can be obtained with luF and 1 OAF tion requirements.
attack capacitors respectively. Recovery
time of 200MS can be obtained with a 4.75F Gain Cell
external capacitor With the recovery ca- Figure shows the circuit configuration of
1
pacitor added in the level sensor, the gain the gain cell. Bases of the differential pairs
20
NE572 Signetics
01 - 02 and 03 - 04 are both tied to the

output and inputs of OPA Al The negative BASIC GAIN CELL SCHEMATIC
feedback through 01 holds the VBE of 01 -
02 and the VBE of 03 - 04 equal. The
following relationship can be derived from
the transistor model equation in the forward
active region.
VBE-3
- 04 '113E01- 02
(VBE = VT In IC/1S)
VT In
2 T 10) IG 10)
\ is / VT
\ /
= VT In
1
t
+ fin
- VT
1,(12 - I -
IS
-(2)
VI=
where fin =
= 6 8K
I1= i4OAA
12 = 280AA
10 is the differential output current of the

gain cell and 1G is the gain control current of
the gain cell.
If all transistors 01 through 04 are of the
same size, equation (2) can be simplfiec to
2
10 = 1-; Im 10 - (12 - 211) 1G 131
The first term of eqn. (3) shows the multiplier SIMPLIFIED RECTIFIER SCHEMATIC
relationship of a linearized two quadrant
transconductance amplifier The second
term is the gain control feed through due to
the mismatch of devices. In the design this
has been minimized by large matched de-
vices and careful layout. Offset voltage is
caused by the device mismatch and it leads
to even harmonic distortion. The offset volt-
VRE
age can be trimmed out by feeding a current
source within 2 25µA into the THD trim pin.
The residual distortion is third harmonic dis-
tortion and is caused by gain control ripple
In a compandor system, available control of
fast attack and slow recovery improves rip-
ple distortion significantly At the unity gain
level of 100mV, the gain cell gives THD (to-
tal harmonic distortion) of 17% TYP. Output
noise with no input signals is only SAN in the
audio spectrum (10HZ-20KHZ) The output
current 10 must feed the virtual ground input
of an operational amplifier with a resistor
from output to inverting input. The non -invert-
ing input of the operational amplifier has to 31
be biased at VREF if the output current 10 is

dc coupled
Rectifier
The rectifier is a full -wave design as shown Figure 2
in Figure 2 The input voltage is converted to
current through the input resistor R2 and
turns on either 05 or 06 depending on the Butter Amplifier Neglecting diode impedance the gain Galt)
signal polarity. Deadband of the voltage to In audio systems, it is desirable to have last for AG can be expressed as follows.
current converter is reduced by the loop attack time and slow recovery time for a -t
gain of the gain block A2. If AC coupling is tone buret input. The fast attack time re- Galt) (GaiNT CIFNL) rA + GsFNL
used, the rectifier error comes only from in- duces transient channel overload but also GaiNT - Initial Gain
put bias current of gain block A2 The input causes low frequency ripple distortion. The
bias current is typically about 70nA Fre- low frequency ripple distortion can be im- rA - RA CA w IC% CA GRFNL =Final Gain
quency response of the gain block A2 also proved with the slow recovery time. If differ- where rA is the attack time constant and RA
causes second order error at high frequen- ent attack times are implemented in corre- is a 10K interns! resistor. Diode D15 opens
cy. The collector current of 06 is mirrored sponding frequency spectrums in a split the feedback loop of A3 for a negative going
and summed at the collector of 05 to form band audio system, high quality perfor- signal if the value DI capacitor CR is larger
the full wave rectified output current IR The mance can be achieved. The buffer amplifier than capacitor CA. The recovery time de-
rectifier transfer function is is designed to make this feature available pends only on CR RR. If :he diode imped-
Yu, VREF with minimum external components. Refer- ance is assumed negligible, the dynamic
ring to Figure 3, the rectifier output current is
R2 (4) gain GR (t) for AG is expressed as follows
mirrored into the input and output of the
II Vin is A.C. coupled, then the equation will unipolar buffer amplifier A3 through 05. Og
be reduced to.
and 010. Diodes D 11 and 012 improve '3(410 11. ((3R INT - 0R FNL) 111 rA + 0R FNL
Vin (AVG) tracking accuracy and provide common
inaC rR - RR CR w 10K CR
R2 mode bias for A3 For a 3ositive going input
The internal bias scheme limits the maxi- signal, the buffer amplifier acts like a volt- where iFt is the recovery 1 me constant and
mum output current IR to be around 3006A age follower. Therefore. the output imped- RR is a 10K internal resistor. The gain con-
Within a ± 1dB error bend the input range of ance of A3 makes the contribution of ca trol current is mirrored to the gain cell
the rectifier is about 52dB pacitor CR to attack time insignificant through 014. The low level gain errors due

N E572 Signet's=
to input bias current of A2 and A3 can be

trimmed through the tracking trim PIN into
A3 with a current source of ± 3mA.
Basic Expandor
Figure 4 shows an application of the circuit
as a simple expandor. The gain expression
of the system is given by
Vow- 2 R3VIN(AVG)
(5)
VIN I, Relli (II . 140µA)
Both the resistors R 1 and R2 are tied to

internal summing nodes. R1 is a 8.8K inter-
nal resistor. The maximum input current into
the gain cell can be as large as 140µA. This
corresponds to a voltage level of 140µA
8.8K 952mV peak. The input peak current
into the rectifier is limited to 300AA by the
internal bias system. Note that the value of
R1 can be increased to accommodate high-
er input level. R2 and R3 are external resis-
tors. It is easy to adjust the ratio of R3 /1,12
for desirable system voltage and current
levels. A small R2 results in higher gain con-
trol current and smaller static end dynamic
tracking error. However, an impedance buff-
er Al may be necessary if the input is volt-
age drive with large source impedance.
The gain cell output current feeds the sum-
ming node of the external OPA A2. R3 end
A2 convert the gain cell output Current to the
output voltage. In high performance applica-
tions, A2 has to be low noise, high speed
and wide band so that the high performance
output of the gain cell will not be degraded. BASIC COMPRESSOR SCHEMATIC
The non -inverting input of A2 can be biased ROC 1 ROC2
VB.
at the low noise internal reference PIN 6 or
10. Resistor R4 is used to biased up the
output DC level of A2 for maximum swing.
NA/.
9 11(
I CDC
10,F
9 11(
The output DC level of A2 is given by C2 1,F

R3 R3
VODC VREF 1 T R4 ) v8 R4 (6) DI D2
CIN1
VB can be tied to a regulated power supply

V1N (2-----1 I
2 2,F
w
:335 VOUT
for a dual supply system and be grounded 2 2,F
for a single supply system. CA sets the at-
tack time constant and CR sets the recovery
time constant. 11( 55
16.101 VREF
Basic Compressor
Figure 5 shows the hook-up of the circuit as RI 17.91
a compressor. The IC is put in the feedback
6 BB C1N2
loop of the OPA A1. The system gain ex- 2 2,F
pression is as follows:
(5.111
VOUT /11
R2 RI '12
(7)
VIN - 2 R3 Vw (AVG) 12.141
C11113
14..21 BUFFER 2 2,F
RDC RDC2, and CDC form a dc feedback
I,
for Ai. The output DC level of Ai is given by

RDCI + ROC2 3 36
VODC VREF R2
R4
CR CA
- VB
( ROC RDC2
(8)
10,F 1,F (3.131
R4
The zener diodes DI and D2 are used for tai VCC (IS)
channel overload protection.
Figure 5
Basic Compandor System
The above basic compressor and expandor
can be applied to systems such as
tape /disc noise reduction, digital audio,
bucket brigade delay lines. Additional sys-
tem design techniques such as bandlimiting,
band splitting, pre -emphasis, de -emphasis
and equalization are easy to incorporate.
The IC is a versatile functional block to
achieve a high performance audio system.
Figure 6 shows the system level diagram for
reference.

N E572 Signetics
BASIC EXPANDOR SCHEMATIC
114 53
VIN VOUT
Figure 4 +Vcc
ELECTRICAL CHARACTERISTICS S andard Teat Conditions (unless otherwise noted) Vcc 15V TA - 25°C Expandor mode (see test
circuit) Input signals at unity gain ievel (0d13)=100mV RMS at 1KHz, V, - V2. R2 3 3K, R3 .4 17.3K
LIMITS
PARAMETER TEST CONDITIONS UNIT
Min Typ Max
VCC Supply voltage 6 22 VDc
ICC Supply current No Signal 6 mA
Internal voltage reference 2.3 2.5 2.7 VDC
THD (untrimmed) 1kHz CA = 1.00F .2 1.0 %

THD (trimmed) 1kHz CR - 100F .05 %
THD (trimmed) 100Hz .25 %
No signal output noise Input to V1 and V2 grounded (20.20kHz) 6 25 uV
DC level shift (untrimmed) Input change from no signal to 100mV RMS ± 20 ± 50 MV
Unity gain level -1 0 +I dB
Large signal distortion V1 - V2 = 400mV 0.7 3.0 %
Tracking error (measured relative Rectifier input ±.2 dB

to value at unity gain output) - V2 - + 6dB, V, - OdB
(V0 - Vo(unity gain)) dB - V2 (dBm) V2 - - 30dB, V, - OdB ± .5 -7.5
+.8
Channel crosstalk 200mV RMS into channel A, measured output on 60 dB
channel B
Power supply rejection ratio 120Hz 70 dB
NE572 SYSTEM LEVEL
V RMS
[ [ J2 REL LEVEL ASS LEVEL
COMPRESSION EXPANDOR 011 MMA

OUT
3.0V +29.54 - +11.75-

INPUT TO 6G
ANO RECT
547 6MV +1477- -3.00 -

400 MV +120- -5.75-
100 MV 00- -- 17.71 --
10 MV -20 --. -37 76 -
I NV -40 -57 75 -
1005V 60 -77 711
- 10V Figure 6 -SO - -9775

General
Instrument AY -3-1350
TUNES SYNTHESIZER
PIN CONFIGURATION
28 LEAD DUAL IN LINE
FEATURES
TOP VIEW
- 25 Different Tunes Plus 3 Chimes
- Mask Programmable with Customer Specified Tunes
for Toys, Musical Boxes, etc.
GND C 1 28 3RESEF
//UDC 2 27 705C
- Minimal External Components
//DOC 3 26 3CLKOUT
- Automatic Switch -Off Signal at End of Tune for
GND C 4 25 7Tune Select A
Power Savings
GINDC 24 7Tune Select B
- Sequential Tune Mode
Play IC 6 23 7Tune Select C
Envelope Control to Give Organ or Piano Quality
Play 2C 7 22 ]Tune Select D
- 4 Door Capability When Used as Doorchime
CaptestC 8 21 7Tune Select E
- Operation with Tunes in External PROM if Required
Tune Select 4C 9 20 ]Tune Select 1
- Single Supply Operation

Next TuneC 10 19 ]Tune Select 2
DISCRGC 11 18 ]Tune Select 3
On/OffC 12 17 3RESTART
DESCRIPTION
EnvelopeC 13 16 ]Switch Group Select
Tune OutputC 14 15 7Tune Select Strobe
The AY -3-1350 is an N -Channel MOS microcomputer
based synthesizer of preprogramed tunes for
applications in toys, musical boxes, and door -
chimes. The standard device has a set of 25
different popular and classical tunes chosen for
their international acceptance. In addition there
are 3 chimes making a total of 28 tunes.
The chip is mask-programable during manufacture

enabling the quantity user to select his own music.
Lip to 28 tunes of varying length can be chosen.
TUNES
The standard AY -3-1350 contains the following tunes:

AO Toreador A3 0 Sole Mio
BO William Tell B3 Santa Lucia
CO Hallelujah Chorus C3 The End
DO Star Spangled Banner D3 Blue Danube
ED Yankee Doodle E3 Brahma' Lullaby
Al John Brown's Body A4 Hell's Bells

B1 Clementine B4 Jingle Bells O
Cl God Save the Queen C4 La Vie en Rose 46q)
Dl Colonel Bogey D4 Star Wars Q)

El Marseillaise E4 Beethoven's 9th O
A2 America, America Chime X Westminster Chime

40'
82 Deutschland Leid Chime Y Simple Chime Cb
C3 Wedding March Chime 2 Descending Octave Chime Eo

Lwct,
D2 Beethoven's 5th
0
E2 Augustine Q

General
PIN FUNCTIONS
Pin O's Signal Function
1,4,5 GND Ground.
2,5 ADD Primary supply voltage.
6 Play 1 When activated by a logic low, it generates Decending Octave Chime.
7 Play 2 When activated by a logic low, it venerates one of the five tunes depending
upon selection of rune Select A through lune Select F pins (Tunes APT -FN).
If Tune Select A thru Tune Select F is not selected, simple chime is played.
Captest Works in conjunction with signal DISCRG to determine the speed of the lune.
Depending upon the rise time of the voltage at this pin, the tune will play
faster or slower.
20,19,1E1,9 lune Select I
thru Tune When power is applied to pin 2, the Chip scans Play 1, Play 2, lune Select A
Select 4 thru F and lune Select 1 thru 4 (Ref. fable 2, 5, et 4) and plays the tune
21,22,25, Tune Select A as selected by these pins.
24,25 thru Tune
Select F
10 Next Tune Scanned externally by lune Select 4 (Pin 9). If Pin /10 is at a logic low,
then the next tune selected will play.
11 DISCRG Works in conjunction with Captest (Pin 13). Controls the speed of the tine.
12 On/Off At power on, it is logic low voltage. At the end of the tune, it que!; to
npen. this pin can he used to control the power of the chip.
15 Envelope Controls overall volume and quality of the tune. Relates to the tapering of
the musical notes.
14 Tune Output Outputs the tune.
15 lune Select Detects selection of lune Select 1-4. If none is selected, lone Select Irt it
Strobe assumed.
16 Switch Group Rased upon the connection of this pin to Tune Select 1-4, one of the five
Select tunes will he played. The tunes selected are based upon the position of the
Tune Select A thru F (Reference fable I).
17 RESTART Scanned externally by lune Select 4 (Pin 9). If RESIART is at a logic low,
then the same tune will play providing power is continued to he applied to
the chip.
26 CLKOUI Signal timing of frequency equal to oscillator frequency (Pin 27) divided by
(output) four. May he used by external devices to synchronize to the oscillator
27 OSC (input) Oscillator input. this signal can he driven by an external oscillator if a
precise frequency of operation is required or an external RC network coo INS
used to set the frequency of operation of the internal clock gniierator.
This is a Schmitt trigger input. Oscillator frequency determines the pitch
of the tune.
28 RESET Resets the system and initializes it.

General
OPERATION SUMMARY chip is to put ON/OFF (pin 12) to logic O. This

Use of the AY -3-1350 can be split into three groups maintains the power through the PNP, even after the
which are described in detail in separate sections: switch is released. The device can turn off its
own power at the end of a tune by raising ON/OFF to
ONE CHIP STANDARD AY -3-1350 SYSTEM generating 25 logic 1.
tunes plus 3 chimes which have been preprogramed
into the standard device. Figure 1 shows only a typical one -chip implementa-
tion. Further options come from use of different
ONE. CHIP CUSTOM TUNES SYSTEM generating any number switching and/or from use of the next tune
of tunes desired. This involves mask programing facilities built into the chip. These will now be
during manufacture and is usually not suitable for considered in turn.
small quantity production.
Switching Options
TWO CHIP STANDARD AY-3-1350/PROM SYSTEM generating In figure 1 the Switch Group Select pin (16) is
any tunes desired as Shove, hut using the standard not connected, and one of the five tunes (AO
device so that applications, including small through E0) will play if switch C is activated.
quantities, become feasible. Other number groups' can be chosen by connecting the
Switch Group Select pin as follows:
ONE CHIP STANDARD AY -3-1350 SYSTEM
TABLE 1
Typical Implementation
There are many ways to connect the standard device Switch Group Select pin (16)
depending on the exact application. Figure 1 shows is connected to: Tunes
just implementation of the device in a door -
one no other pin AO -E0
chime. This circuit gives access to all 25 tunes Tune Select 1 (pin 20) Al -El
from switch A and one of 5 tunes from switch C as Tune Select 2 (pin 19) A2 -E2
well as the descending active chime from switch B. Tune Select 3 (pin 18) A3 -E3
The tune selected for switch A follows the tunes lune Select 4 (pin 9) A4 -E4
list according to the setting of the two tune
select switches (A -E and 0-4). The tune selected Which of the five possible tunes will be played
from switch C in Figure is one of the five tunes
1
depends an the current setting of the letter
AO through Ell depending on the setting of the switch A -E.
letter switch. Switch B always selects Descending
Octave Chime independent of Tune Select switches. Switch Group Selection can he made by hard -wire
For example, with the letter switch set at E and connection for a permanent selection or a third
number switch set at 4, the tunes available will switch can he added for an additional group selec-
be: tion feature.
Next Tune Facilities
Switch A: Beethoven's 9th (E4)
At the end of tune play, the circuit of Figure 1
Switch C: Yankee Doodle (E0)
powers down because ON/OFF (pin 12) is raised to a
Switch B: Descending Octave Chime (Chime Z)
logic 1. The simplified flow diagram in Figure
shows that before the power down there is a test
When the letter switch is in position F there will
for connection between NEXT TUNE (pin 10) or
he chimes on all doors independent of the number
RESTART (pin 17) with TUNE SELECT 4 (pin 9). At
switch setting as follows:
this time NEXT TUNE (pin 10) then RESTART (pin 17),
which are normally at logic 1, output a logic O.
Switch A: Westminster Chime
This is looked for at input TUNE SELECT 4 (pin 9).
Switch C: Simple Chime
If neither is found the power down system is
Switch It: Descending Octave Chime
reached as in Figure 1.
!here is virtually no power consumption in the
standby condition (external transistor leakages A NFU TONE (pin 10) - TUNE SELECT 4 (pin 9)
only). When any door switch is activated the connection at the moment
of test causes the next
circuit powers up, plays a tune, and then automat- tune in the list to be played after a short pause
ically powers down again to conserve the battery, (equal to a musical breve - the actual time depends
even if the operator keeps his finger on the switch on the setting of the tune speed control). The
to the end of the tune. He must release it and re- order of the tunes is AO to E4 as given in the
press to play again with the circuit in Figure 1. listing of standard AY -S-1550 tunes. If the last
Activating any of the door switches will pull point tune (E4) was played then the circuit will go on
A to ground turning on the PNP transistor in the to play the first tune AO (and then successive
power supply line. This causes +5V to be applied ones). The chimes are not included in the cycling
to the AY -3-1350 and the first operation of the sequence.

General
Fig. 1 SYSTEM DIAGRAM

4-5%, PITCH
LETTER
R2 SWITCH
TUNE SELECT
A BC D EF SWITCHES
0 +9V
RI
tNUMBER
SWITCH
R3
0 1 2 3 4
I CS
O 16V
1R7
Cl 1 C2
2 t7
1 215 1
26 24
213 1 211
22
1
20
1
1H 16
15
C4
AY -3-1350 I I
+5V
C4
5 67 2
11 14
0 R9
H it
9V +5V SPEED
R14
R10
SW A R16
R11
000R SW B
SWITCHES R12 3
SW C Q2
R13
PARTS LIST
Resistors Iransistors
Reference Value Reference Value
R1 100K11(1/4 or 1/2w) 01 PNP Iransistor

R2 25K11(P01) (MPS 2907)
R3 4K/1(1/4 or 1/2w) Q2,3 NPN lransistor
R4,I6 10K/1(1/4 or 1/2w) (MPS 3904)
R5,6,7 3.3K41(1/4 or 1/2w) Q4 Darlington
R8 471(11(1/4 or 1/2w) transistor
R9 2.21(11(1/4 or 1/2w) (MPS A13)
R10 0111(POI)
R11 3301(11(1/4 or 1/2w)
R12,13,14 331(11(1/4 or 1/2w) Diodes
R15 27 11(1/2w)
D1 Zener Diode (5.1V)
(IN4733)
Capacitors D2011, 04 Diodes
(1N914)
CI 0.1 0 (ceramic)
C2 47 pi
C3 0.22 pF
C4, 5 10 pF Speaker 8 ohms

General
A RESTART (pin 17) - TUNE SELECT 4 (pin 9) connec-

tion at the moment of test at the end of a tune
Fig. 4 NOTE LENGTH TABLE
causes the same selected tune to be played again.

Figure S shows that in this case the tune sensing Musical
mechanism is passed through once more so the tune Name Notation Octal Binary
would he different the second time if the switches

Sixteenth note I1P 0 000
were altered while the first tune was playing.
The connections referred to cannot he permanent be-
Ftqhth note It 1 001
Ihree-sixteenth note ere 2 010
cause otherwise the circuit would never stop play-
Quarter note 4 3 011
ing tunes. Figure 2 shows how transistors are used
to make the connection in a practical application. Ihree-eighths note J 4 ion
Half note d 5 101
Fig. 2 Three-quarter note d. 6 110

28 17 15 Whole note 0 7 Ill
I
AY -3-1350
I
Fig. 5 PROM Memory Allocation
S 7
Address DATA
0 377 (tunes select timeslot)

w
33K 1
lune 1
2000iF
16V
577 (end of tune marker)

1
PIN FUNCTION Tune 2
6 PLAY 1
DOOR PUSHES
PI AY 2
9 I SE1 EC( 4 377 (end of tune marker)
1
Ill NI XI IUNE
17 RI 'IART More tunes
ONE CHIP CUSTOM TUNES SYSTEM
Customizing the Tunes Last lune

The AY -5-1550 pre-programmed tunes, hut the
has
device is mask programmable during manufacture with
any music required. A minimum of tune to a I 377 (end of tune marker)
maximum of 211 tunes can be incorporated. Examples 376 (end of listing)
as follows: 000
000
Total No. of notes, Average notes 000 Not used
Tunes all tunes t ether per tune 000
1
1 252 252 377 125 (external ROM enable key)

2 251 126
5 248 50 Fig. 6 STAR SPANGLED BANNER - MUSIC
10 24 5 24
20 255 12
25 228 9
(The general formula is Total No. of notes = 255 -
No. of tunes.)
-r
$43 203 all 885

General
Fig. 3 SIMPLIFIED FLOM DIAGRAM
POWER APPLIED
ON/OFF (PIN 12)

10 LOGIC 0 10
MAINTAIN POWER
I
INTERROGATE EXTERNAL PROM 10 GET CORRECT INTERROGATE INTERNAL PROM TO GET CORRECT
SELECTION ACCORDING 10 SETTINGS OF LETTER, SELECTION ACCORDING 10 SETTINGS OF LEITER,
NUMBER, AND BACKDOOR GROUP SELECT NUMBER, AND BACKDOOR GROUP start
SWITCHES SWITCHES
PLAY SELECTED TUNE
DELAY
SELECIED NEXT TUNE
THIRD DOOR
SELECT TUNE AO REQLESTED?
LAST
CYCLING NEXT TUNE
TUNE PLAYED? REQLESTED?
DELAY
RESTART
OR BACKDOOR
REQUESTED?
ON/OFF SPIN 12) 10 RH IFF POWER

IF USING AUTO -SHUTDOWN AS IN F1G. 1)
3mS SINCE
POWER OFF?

General
TABLE 2
SELECTION OF CHIMES
TUNE SELECT TUNE SELECT PLAY 1 PLAY 2 TUNE PLAYED
A H C D E I 2 5 4
1 I 1 1 1 X X X X 1 I Westminster Chime
1 1 1 1 1 X X X X 0 1 Descending Octave Chime
1 I 1 1 1 X X X X 1 0 Simple Chime
TABLE 3
SELECTION OF TUNES*
TUNE SELEC1* TUNE SELECT PLAY 1 PLAY 2 TUNE PLAYED
A B C D E 1 2 5 4 1 1
0 I 1 1 1 I 1 1 I I 1
AO
01111
0
0
1
1
1
1
1
1
1
I
0
1
I
1
0
I
I
0
1
1
1
1
1
I
I
Al
A2
A3
0 I 1 1 1 1 1 1 0 I 1 A4
1 0 1 1 1 1 I 1 1 1 I
BO
1 I 1 1 0 1 I 1 0 I I E4
*These tunes are activated when power is applied to the chip. In Fig. 1, it is achieved when switch A is
depressed. Also, switch B = PLAY and switch C = PLAY 2
1
TABLE 4
SELECTION OF TUNES
TUNE SELECT TUNE SELECT PLAY 1 PLAY 2 TUNE PLAYED
A B C D E 1 2 5 4
I I I 1 I X X X X 1 (1 Simple Chime
0 1 1 1 1 X X X X I Ti AO
1 11 1 I 1 X X X X I 0 Bo
I 1 0 1 1 X X X X 1 0 CO
1 1 1 0 1 X X X X 1 0 DO
I 1 1 1 0 X X X X 1 0 E0
X X X X X X X X X 0 X Descending Chimes
KI Y: 0 = Switch activated
I = Switch not activated
X = Do not care

General
As an indication, about 90 seconds of music can be Fig. 7 NOTE PITCH TABLE

Incorporated. All musical rests are counted as one
note. Semiquavers, quavers, dotted quavers, FREQUENCY
crotchets, dotted crotchets, minims, dotted minims NAME (Hz) OCTAL BINARY
and semibreves can all be accommodated. the range
is about 2 1/2 octaves. the position of these F 175 00 00000
octaves can be chosen by the user up to a maximum Fl 185 01 00001
pitch of Ac 176011z. C 196 02 00010
CO 208 03 00011
Applications for Customized Tunes A 220 04 00100
If the number of tunes is less than the number of Al 233 05 00101
switch positions then the circuit will automatically H 247 06 00110
proceed directly to power down if this power down C (middle C) 262 07 00111
mode is being used, or will find the next available CO 277 10 01000
tune if in the sequential mode. I) 294 11 01001
DM 311 12 01010
All the different facilities described are still 1 330 13 01011
available when user tunes are masked into the F 349 14 01100
dev ice. Fl 370 15 01101
C 392 16 01110
For toys, sequential tune playing adds variety and Gil 415 17 01111
reduces the number of switches required, keeping A (international A) 440 20 10000
costs to a minimum. Al 466 21 10001
B 494 22 10010
For musical boxes, playing the same tune repeatedly C 523 23 10011
preserves the traditional features. r# 554 24 10100
0 587 25 10101
TWO CHIP STANDARD AY-3-1350/PROM SYSTEM no 622 26 10110
F 659 27 10111
Introduction F 698 30 11000
With the addition of an external ROM or PROM the 10 740 31 11001
standard AY -3-1350 will play almost any tune or 784
G 32 11010
tunes desired. 28 tunes averaging 9 notes each or Cl 831 33 11011
one tune of up to 252 notes is available, providing 880 34 11100
A
in all, about to 2 minutes worth of music. General
1
Al 932 35 11101
Instrument can later integrate the external tunes 0 988 36 11110
into the main synthesizer to give a one chip system. Rest Silent 37 11111
Overall Coding Scheme

Fig. 8 STAR SPANGLED BANNER - CODING
the external PROM should he 256 x 8 hits and of any
static IlL compatible type.
OCTAL DATA BINARY DATA
It can have more words, hut the tunes synthesizer

232 10011010
will only use 256 x 8 bits at a time, e.g. if PROM
200 10000000
type 2716 is used (2K x 8 bits), the three higher
143 01100011
order address lines should be connected to ground or
203 10000011
switches put on them to give 8 times the amount of
233 10011011
music (see logic diagram Figure 9). the rest of
305 11000101
this article will assume a 256 x R bit PROM, and the
377 11111111
addresses will be referred to as 000 to 377. Octal
notation is used throughout.
'The last 377 is the end of tune code
the PROM address 000 must contain data 377 and

address 377 must contain data 125 which is a key to
open up the external PROM features. All other
addresses can contain tune data.
Fach tune consists of series of notes with one

a
byte of PROM for each. Every tune must have a tune

end marker byte 377 after the last nnte, and the
final tune must have a byte 376 after the 377 end

General
marker. The memory allocation is shown diagrammat- lengths. In practice one pitch code is allocated
ically in Figure 5. Tunes ran he of any length and as silence to allow musical rests of different
there ran he any number of them subject only to the lengths to he implemented. Figure 4 gives the
memory limit (28 max.). length table and Figure 7 the note pitch table. It
can be seen that the lengths from a sixteenth to a

Fach note of a tune occupies byte (8 hits) of I whole note, and 2 1/2 octaves of notes can he pro -
PROM, and this can be considered as split into two duced. the pitches shown assume that the on -chip
fields: clock of the AY -3-1350 is trimmed to 1MHz. the
pitches can he made lower by using a slower clock.
7 6 5 4 3 2 1 Every reduction by 5.61257% decreases the pitch by
a semitone. the note pitches produced by the
pitch length AY -3-1350 are approximately eqpi-tempered. It
should he noted that codes 377 and 376 are used as

the three least significant hits specify the length end of tune markers and are illegal as notes. they
(half note, quarter note, etc.) and the five most correspond to whole and three-quarter note rests
significant bits specify the pitch. !his gives which can, however, be made up by combining two
25 : 32 different pitches and 23 = P different smaller rests in place of the required 377.
Fig. 9 PLAYING YOUR OW TUNES WITH EXTERNAL PROM (OR INTERNAL TUNES)
ALL TRANSISTORS TO HAVE INA >80 @ loA

+5v
*A8, A9, A10 ON 2716 CAN BE 1 TUNE BLOCK.

UTILIZED TO INCREASE MEMORY 21 18 19 SELECT
FOR MORE TUNES. A10 Aul22-
24
VCC 'PP CE A9 22
AO 8
Al 7
A2 6
A3 5
2716 A4 4
12 GND 4011
20 OE A5 3
A6 2
A7 +5 CND
D7 D6 D5 D4 03 D2 Dl DO 3 4 5 2 4011 1 14 7
+5v 13.2
17 16 15 14 13 11 10 9 4078 14 7
0 S2
4078
25K C 0 1
PITCH D005
100K OWTROL E0 R16 S
F
R4 +5
2,7K
R3 515
3K INT
D4
3 3
O. Iuf - 50
- 03
4
CI
T PF
C2
+9V
2A n 23 f4 23 22 fl 0 18 17 16 15
3. 3K
R18
AY -3-1350 uxe MN
TUNES SYNTHESIZER
45
C6 If 47K
+9V D3
47K 7 9 19 4
A Q2
+5v +5V
RS 470 nic
ea
5
DI
R6
uf1
= D2
4I1P
C3 = 3KS R11
33K
33K
C4:;: SPEED CONTROL

1
S4 1\ 470K O.22 10K
2200uf = 5
4- +5V -"14.-"14-
1" TTHIRD4 rlAcK
R8 C 2N 3704 R10

General
ELECTRICAL CHARACTERISTICS
Maximum Ratings* *Exceeding these ratings could cause permanent

Ambient temperature Under Bias 125°C damage to the device. This is a stress rating only
Storage Temperature -55°C to +150°C and operation of this device at these
functional
Voltage on any pin conditions is not implied -- operating ranges art
with Respect to Vss -0.3V to +10.0V specified in Standard Conditions. Exposure to
Power Dissipation (Note 1) 1000mW absolute maximum rating conditions for extended
periods may affect devr.ce reliability.
Standard Conditions (unless otherwise stated):
Data labeled "typical" is presented for design
DC CHARACTERISTICS guidance only and is not guaranteed.
Operating Temperature TA = 0°C to +70°C
Characteristic Sym Min Typ* Max Units Conditions
Primary Supply Voltage VDD 4.5 - 7.0 V
Primary Supply Current ID° - 30 50 met All 1/0 pins 0 VDD

Input Low Voltage VIL -0.2 - 0.8 V
Input High Voltage (except RISE!,

OSC, /4 pins 6, 7 and 8) VIH 2.4 - VDD V (Note 2)
Input Low -to -High Threshold
Voltage (RESET & OSC) VILH VDD-1 2.6 VDD V
Output High Voltage (Note 3) VOH 2.4 - VDD V ION' 100pA (Note I)
3.5 - VDD
V 10H=0
Output Low Voltage VOL - 0.45 V .10L=1.6mA, Vxx=4.5V
Input leakage Current (RESET,
pins 6, 7, & 8) -5 - +5 VSS < VIN < VDD
ILC NA
Output leakage Current (open
drain I/O pins 12 & 13) IOLC - - 10 kiA V55 < VpIN < 10V.
Input Low Current (all I/O ports) IIL -0.2 -0.6 -1.6 rrbA VIL=0.4V internal pullup
Input High Current (all 1/0 ports) IN -0.1 -0.4 -1.4 mA VN=2.4V
*Typical data is at TA = 25°C, VOD = 5.0V
NOTES:
1. Positive current indicates current into pin. Negative current indicates current out of pin.
2. Pins 6, 7 and 8 have open drain inputs (no internal pullup resistor).
S. Except pins 12 and 13 which have open drain outputs.
Hardware Implementations As a specific example, the music for the first part
lo play the 28 internal tunes of the AY -3-1350 of Star Spangled Banner is shown in Figure 6 with
tunes Synthesizer, the device should he connected up the notes coded in octal below the music. Figure 8
as shown in the One Chip Standard AY -3-1350 System represents just one of the tunes shown in the
section. To play tunes Which you have written into overall memory scheme of Figure 5 and it shows the
the PROM in the manner described above, the actual data that would have to be incorporated into
AY -3-1350 and the PROM should he interconnected as the external PROM to get a tune consisting of these
shown in Figure 9. This can be used for demonstra- 6 notes.
tions, on -off implementations or small scale pro-
ductions. this circuit will also play the internal
tunes (See internal/external switch).
One Chip Implementation

For manufacturing purposes, send PROM and code
listing to General Instrument and we will incor-
porate your tunes into a sperially made one chip
tunes Synthesizer in place of the standard 2H
tunes.

National
LMC835 ilra Semiconductor
Digital Controlled Graphic Equalizer Connection Diagram

Dual-In-Une Package
General Description Features
The LMC835 is a monolithic, digitally -controlled graphic No volume controls required A G110
NMI
equalizer CMOS LSI for Hi-Fi audio. The LMC835 consists Three -wire interface
of a Logic section and a Signal Path section made of analog hat
14 bands, 25 steps each
switches and thin-film silicon -chromium resistor networks. ±12 dB or ±6 dB gain ranges 4.3 NMI
The LMC835 is used with external resonator circuits to Low noise and distortion AIMI
make a stereo equalizer with seven bands, ± 12 dB or i 6 A1114
TTL, CMOS logic compatible

dB gain range and 25 steps each. Only three digital inputs LCI LCI
are needed to control the equalization. The LMC835 makes
it easy to build a µP -controlled equal zer. Applications LC2 LCI
The signal path is designed for very low noise and distor-
Hi-Fi equalizer LC3 LCIO
tion, resulting in very high performance, compatible with Receiver

LC4 LC11
PCM audio. Car stereo
Musical instrument LCD LC12
Tape equalization LCI LCI3

Mixer LC7 LC14
Volume controller
V1I VUO
(MO DATA
CLOCK 51605E
Block Diagram Top View
`lil 14 LEVEL DO
01
02 4 -TO -16 DECODER

LATCH
5.Bit 03
SHIFT
REGISTER 0 F
16 LEVEL DS
S11111 06 I I
DATA
2
07
4-0
it
Ouu066uuuuLA 41.0 11
11
-
it
NMI 0
r ---4-;T 44.
1111C
7 30 :41
3 lk V 4 AS 116 A? 51
A013
LATCH Al
Rd2
7.31
[ELECTOR Al OIC
ROOST OUT
RN MC
3 IR 341
sa
xf 1111
23
A GOIO 01
Sb
1155 551
116C 611 0-`1VIIVId-41111140 251
3.41 3 4k
25
0-.-.0V1V1kr R30 16k
A1.17 0 vys, 620 1 1 1
RIO W. 141661
7 3k .411/V- ROb 31
NMI O
20 1-1 L.J L.J Lr..1
062
7 3k
27
Ain 0
05 07 05 05 010 011 024 03 on 021 020 01, 010
LC I LC2 LC3 LC4 LCS LC. LC7 LCI LC9 LCIO LC11 1C12 LCI3 LC14
Absolute Maximum Ratings Operating Ratings

Supply Voltage, VDD - VSS 18V Supply Voltage, VDD - VSS 5V to 16V
Allowable Input Voltage (Note 1) Vss - 0.3V Digital Ground (Pin 13) Vss to VDD
to VDD + 0.3V Digital Input (Pins 14, 15, 16) VSS to VDD
Storage Temperature, Te19 - 60°C to + 150°C Analog Input (Pins 1, 2, 3, 4, 25, 26, 27)
Lead Temperature (Soldering, 10 sec), TL +300°C (Note 1) Vss to VDD
Operating Temperature, Tope - 40°C to + 85°C
Data supplied by National Semiconductor.
National Semiconductor.

MI National
LMC835 Semiconductor
Electrical Characteristics (Note 2) VDD - 7.5V, Vss = 7 5V, A GND OV

LOGIC SECTION
Tested Design
Unit
Symbol Parameter Test Conditions Typ Limit Limit
(Limit)
(Note 3) (Note 4)
IDOL Supply Current Pins 14, 15, 16 are 0), 0.01 0.5 0.5 mA (Max)
ISSL Pins 14, 15, 16 are 0), 0.01 0.5 0.5 mA (Max)
IDDH Pins 14, 15, 16 are 5V 1.3 5 5 mA (Max)
ISSH Pins 14, 15, 16 are 5).$ 0.9 5 5 mA (Max)
VIH High -Level Input Voltage @Pins 14, 15, 16 1.8 2.3 2.5 V (Min)
VII_ Low -Level Input Voltage @Pins 14, 15, 16 0.9 0.6 0.4 V (Max)
to Clock Frequency @Pin 14 2000 500 500 kHz (Max)
tvi(STSI
Width of STe Input See Figure 1 0.25 1 1 i.i.S (Min)
tsetup Data Setup Time See Figure 1 0.25 1 1 i.i.S (Min)
thold Data Hold Time See Figure 1 0.25 1 1 i.i.S (Min)
tcs Delay from Rising Edge of CLOCK See Figure 1 0.25 1 1 siS (Min)
to SIT
IIN Input Current @Pins 14, 15, 16 OV< VIN <5V ± 0.01 ±1 u.A (Max)
GIN input Capacitance @Pins 14, 15, 16 f = 1 MHz 5 pF

Note 1: Pins 2, 3 and 26 have a maximum input voltage range of t 22V for the typical applicabon shown in Figure 7.
Note 2 Bold numbers apply at temperature extremes. All other numbers apply at TA- 25*C, Vdo- 7.5V, Vss= -7.5V,D.GND- A.GND = Or as shown in the test
circuit Figures 3 and 4.
Note 3: Guaranteed and 100% producbon tested.
Note 4: Guaranteed (but not 100% production tested) over the operabng temperature range These limits are not used to calculate outgoing quality levels.
Timing Diagram
SV
CLOCK INPUT
OV
5V
DATA iNPUI
OW
K. (5141
5V
STROBE INPut
OV
n.swws.ss
Note: To change the gain or the presently selected band, rt is not necessary to send DATA 1 (Band Selection) each time.
FIGURE 1
Test Circuits
+15V -15V
tOn
Vies
470
0 soon
100k 114433
1008 1001
OA A
r--
riso ikso issolssaiNf sea
TAO 6
121 127 26 25 24 23 22 21 20 16 11 17 6 15 CLO R"" GENE1150/04

A 050 Asps 04N. A.57 LC& ICI LCtO LC11 I. 17 LC13 IC11 V00 I) TA sspapp
0 6ND I
LIAM&
L. - J
Ansi *4112 A4113 Ater LC1 LCI 1C3 LC4 L.C5 LC6 LC7 vii 0 ONO CLOCK
2 3 4 5 6 7 11 11 12 13 14
650 650 610 610 610 650 610

1000 1009
1001. 1001
LM/33
470
LA1433
0 VautA
Via*
On
+1St -15V FIGURE 3. Teat Circuit for AC Measurement

M National
LMC835 WA Semiconductor
Electrical Characteristics (Note 2) Voo = 7.5V, Vss = - 7.5V, D.GND= A.GND = OV

SIGNAL PATH SECTION
Tested Design
Unit
Symbol Parameter Test Conditions Typ Umit Limn
(Note 3) (Note 4)
(Limb)
AAv Gain Error Ay= 0 dB @ ± 12 dB Rance 0.1 0.5 0.5 dB (Max)

Ay= 0 dB @ t 6 dB Range 0.1 1 1 dB (Max)
Ay = ± 1 dB @ ± dB Range 0.1 0.5 0.6 dB (Max)
(Rbs or R< is ON)
Ay= ± 2 dB 0 ± 12 dB Range 0.1 0.5 0.6 dB (Max)
(Rtm or /Ica is ON)
Ay= ± 3 dB 0 i 12 dB Range 0.1 0.5 0.8 dB (Max)
(R03 or Rcos is ON)
Ay= ± 4 dB 0 ± 12 dB Range 0.1 0.5 0.7 d8 (Max)
(Rb2 or Ra is ON)
Ay = ± 5 dB 0 ± 12 dB Range 0.1 0.5 0.7 dB (Max)
(Rbl or Rcl is ON)
Ay= ± 9 dB 0 ± 12 dB Range 0.2 1 1.3 dB (Max)
(Fib° or Flso is ON)
THD Total Harmonic Ay= 0 dB 0 ± 12 dB Range 0.0015 56
VIN=4V,s, f = 1 kHz
Ay - 12 dB® ± 12 dB Range
VIN= 1 Vmis, f = 1 kHz 0.01 0.1 % (Max)
VIN=1Vm13, f = 20 kHz 0.1 0.5 % (Max)
Ay= -12 dB 0 ± 12 dB Range
VIN = 4Vrms, f= 1 kHz 0.01 0.1 % (Max)
V1N= 4Vm,s, f = 20 kHz 0.1 0.5 % (Max)
Vo max Maximum Output Voltage Ay= 0 dB 0 ± 12 dB Range 5.5 5.1 5 Vmt, (Min)
THD <1%, t --- 1 kHz
S/N Signal to Noise Ay = 0 dB @ ± 12 dB Range 114 dB
\leo = 1 Vees
Ay = 12 dB 0 i 12 dB Range 106 dB
Vret = 1 Vrms
Ay= -12 dB @ t 12 dB Range 116 dB
Vref = 1V,m5
'LEAK Leakage Current Ay = 0 dB 0 ± 12 dB Range

(All internal switches are OFF)
Pin 2 + 3, Pin 26 500 nA (Max)
Pin 5 - Pin 11, Pin 18 - Pin 24 50 nA (Max)
Notre 1: Pma 2. 3 and 26 NM) a MaYlITUT V fp the typical applocabon shown in Figue 7
Mote Boldface numbers apply at temperature extremes All other flUrnbOrS apply at TA = 25T, V00 = 7.5V. Vss = - 7.5V, D.GND= A.GND= OV as shown m the
test crust. Frpt.res 3 and 4
Mots 3 Guaranteed arid 100% production tested
Mote 4: Guaranteed (but not 100% production tested) over tIre operating temperature range These limns are not used to calculate outgoing quality levels.
Timing Diagrams
-DATA SETS
DATA I 'BAND SELECT10141 DATA II (GAM SELECTION)
CLOCK
DATA
00000000 00000000
STROBE
Note: To Menge Me gam of the xesenty selected band, t is not necessary I send DATA 1 (Band Selection) each time 6753 4
FIGURE 2
Test Circuits (Continued)
I
Vat
L...J
I
I
r
I
Iiiiill
V1.24 8112
lrII lf lfII
11
V121 tLTI
I I/V0 11/V ggl/V g g I/V gg I/V 111/V 101/V

I ei 11
II
II
9128
II
II
A1,,
ir
II
II
v111 + 7 SW
I
I
FIGURE 4. Test Circuit for Leakage Current Measurement
DATA r
L
STROBE
-1
WORD I
17t 27 25 125 22 Ii5
A DID AN5 Am, A.
124
LC8
23
LC9 LCIO
21
LCI 1 1
20
12 LC13
19 111
1C14 V0
IT 5
0 TA MWE
CLOCK GENERATOR
I r -1
CND I
LMC835
- -J
ILK
Aou ts1 A1/44 LCI LCD LC3 LC4 LCD LC6 LC1 V15 0 ND CLOCK
6 9 10 12 13 114
r
I I
vz- 1.40r-irdor1sr
I II II II II I/ II
11 VI II viii VIII V11l VIII Viii
I i II II 11 II 11 II I
JL J
vusul -iim a 105
.
V15 V14 9L7 V11 VII V110 Kt" - 5v FIGURE 5. Ito V Converter

M National
LMC835 'Ka Semiconductor
Truth Tables
DATA I (Band Selection)
D7 D6 D5 D4 D3 D2 01 DO
(Ch A: Band 1 - 7, Ch B: Band 8- 14)
H X L L L L L L
H X L L L L L H
Ch A ± 12 dB Range, Ch B ± 12 dB Range, No Band Selection
H X L L L L H L
Ch A ± 12 dB Range, Ch B ± 12 dB Range, Band 1
H X L L L L H H
H X L L L H L L
H X L L L H L H
H X L L L H H
L
H X L L L H H H
H X L L H L L L
H X L L H L L H
H X L L H L H L
Ch A 3 12 dB Range, Ch B ± 12 dB Range, Band 9
H X L L H L H H
H X L L H H L L
H X L L H H L H
H
HHI-1
H X L L H H L
H X L L H
Ch A ± 12 dB Range, Ch B ± 12 dB Range, No Band Selection
H X L H Valid Binary Input
H X HL Valid Binary Input
Ch A ± 12 dB Range, Ch B ± 6 dB Range, Band 1 - 14
Ch A ± 6 dB Range, Ch B ± 12 dB Range, Band 1- 14
H X H H Valid Binary Input
Ch A ± 6 dB Range, Ch B ± 6 dB Range, Band 1 - 14
4- Band Code
O O DATA II (Gain Selection)
0 DATA 1 D7 003 D5 D1 D3 D2 D1 DO
O Don't Care
Flat L X L L L L L L
Ch A ±6 dB/ t 12 dB Range
1 dB Boost L H H L L L L L
Ch B t 6 dB/ ± 12 dB Range
2 dB Boost L H L H L L L L
3 dB Boost L H L L H L L L
4 dB Boost L H L L L H L L
This is the gain if the ± 12 dB range is 5 dB Boost L H L L L L H L
selected by DATA I. If the ±6 dB
HL HLHL HL
6 dB Boost L H L H L L H L
range is selected, then the values 7 dB Boost L H H L
shown must be approximately halved. 8 dB Boost L H H L
See the characteristics curves for 9 dB Boost L H L L L L L H
more exact data.
10 dB Boost L H H L H L L H
O DATA II 11 dB Boost L H H L H H L H
O Boost/Cut 12 dB Boost L H H L H H H H
1 dB 12 dB Cut L L Valid Above Input
I- Gain Code
II 0
CLOCK CLOCK
11
a
3
CK 0 .11 CK CK 0
3
CK
KC74 MC74 MC74 DATA
12 MC/4
START 0 0 12
a
RC 0
MC163 MC165 MC74

LOAD LOAD 0 T
4
()STROBE
A B C 0 A B C F
10 11 11 13 14 3 1 5 6
*V .v00000doo
07 D6 05 04 03 Dl 01 DO
FIGURE 6. Simple Word Generator

National
LMC835 "KA Semiconductor
Typical Performance Characteristics
Supply Current vs Supply Current vs Input Capacitance vs

Supply Voltage Temperature Input Voltage
1.11 10
TA.25.0 01 -2750 PINS 14. IS. 15
1.1 MI. DATA =ITI.sy 1
01.004.1TI.gy 9
Vs. 2 7 50. TA =311%F-
8.111111.11.8110N 1.6 0 IND .A.11110.1111 GNO A ENO .311
i 1I
1.4 I-1 11142
3. 1.4 7
12 1 6 -
0 1.8 5
01 1.5 4
I6 0.1 3
11 5.4
Si 8.2
1234587 I 9 II -N -u N 71 IN 125 3 4 5 5 7 6 tI
SUPPLY MIME (55) TEMPER/TUN (%) INKIJT VOLTAGE 1111
Maximum Output Voltage Maximum Ot.tput Voltage Nominal Resistor

vs Supply Voltage vs Temperature vs Temperature
10 1 05
TA. 25.0 Vim 2 7 511
101
12 OS RANGE FLAT 2 12 OS RANGE LAT
1.1 kHz, T141)<I% 1.1 IN5, TOO > 1% 3 I07
7 1. 1.02
It _- 6 P. 1.51
t
4 It 009
3 3 111
8 g 0 57
SON
o 95
I 2 3 4 5 6 7 1 10 -69 -N S 15 51 75 1N 125 -N -25 11 21 158 TS IN 125
SUPPLY VOLTAGE I ± V) TEN/FUTURE )C) TEIONIATUME (C)
Distortion vs Frequency Distortion vs Frequency Distortion vs Output Voltage

± 12 dB Range 6 dB Range O ± 12 dB Range
0 01 0.1
7 SY. TA - 25C Vs.. 27.SY. TA 25O
;_':
0 Os
002
212 OS RANGE
-2121
FLAT
I
//1110111
Sims
01111111
.1 111111 ;
0 05
0 02
-
2616 RAMIE
FLAT
is NI
--
-""
-
'
E 002
0.05
00, 111111 1=11 11111' 1111111

g
P. 111
.n.:.. i.-7d1 111,1; 001
d=ii:..ILHYr
111
g 0 005 FM 511i;;:t.....,
MII1161, Ell Weill. gum-
11111
0 DOS
mem mNowl.1185111' i el III 7.7,
a
5 005
fIS
0 002 11111111=1.1111
:
1111
0 002 1 :: Er :.,.
111 Ellil I
. ..
NI
1 III
0 002
0 001
Ilk 0 001
C=31111111 0 001
10 IN 1K 11111 1101 10 15 11111 11101 0I 8.1 1 2 5 10
FINOUENCY (NE) FREQUENCY (NI) OUTPUT MYR* (Om)
-
Distortion vs Output Voltage Gain vs Frequency Gain vs Frequency
1 6 dB Range ± 12 dB Range (Boost) 12 dB Range (Cut)
01 15 3
--
Ys . ± 7 55. TA. nn-m 96.6611.16.106t 111.11111 1111111111
111.11111 .1111111
y... .6 4.1Y1 N1ININEINO1110
4,11111: 111.1111(111.1151111
/ i 13 RAM 13 a Mel Mil
-
o 05 II ICECII1 MI1111111 410951111151511111
04444111
FLAT
J11111 it M111111114131/_111, u:'1111
-1 Menu NISsommsotti, ammo
- 211 NI /111111
M11111,102,2_.111 111111:4.
outicar_stu Nosi:..
NOINNuNIONINIE[111111 wow
. 0, masesimmisioarAiii01111t,
1111111CLUM1
§ 001 oinimprzioni 7
10511III CLAIN 111111:!Ii 3
MIRNIMI1111111111111111111X111111 0017,
MNIIIM111.11.011115111111ILII
0005
-=-7;i-F-1--"" 5
1011111CLEJ111 moo,. 5
NIENNIYIN ININImatifill111111'0,
I7 .111111.11.11111111111[31111101151,
MUM 411.111111111-411111 /11011
Mi. AINIM1171 3
11111011111 ZELJ11111 IN51111 11111//0111
alb . z- PalliPaini 150111111110M11111 111114.;!.. Num ros,,111
minamossincsusioeivr;,,,
0 002
0 001
1Illih1iii1:110II
01 52 11.5 1 5
-1
18 IN
11111111 CEL.11111 11115.;:1'
1.1111111 IP-111111 1111411..:
MIN41111.1111111111 005111111
10 IN INK
-I1muswissuiv.au_nw,
-12 alun-Hutivisesiniiiii11111
1S IN 10 IN
Ii
INK
OUTFIT VOLUME (Ores) FREQUENCY FREOUENCY (14z)
Gain vs Frequency Gain vs Frequency

6 dB Range (Boost) a ±6 de Range (Cut) Gain vs Temperature
10
7 4.14.1 wet 1111
__i__J
41411. 1111 I
ill MEN MeV 5. NM Po V. ±7.111/
I 11NIMM..k.
1111
.1 -.,
III 111111
OM
151
S 2121 RANGE
I 1 4
3
IN
SN
2
2N
I OS
masu5nElormm
1151
=.241:...
1141.1115a/ 0
FLAT
10 108 IX tOK 1000 1110 IN 11115 INK -N -20 0 25 50 75 100 125

TEMPERATURE VC)
FREQUENCY (No) FREOUDICT (Ho
38
National
LMC835 rddrA Semiconductor
Typical Applications
+15V -15V
771
Vim 0 'AA. It
27k
pr-.007-r0....1
II II is II si
r--
I 11 I
l
I 21 . 122 I I Z3 " 24 11 15 11 26 I l Z7 I
Ilk I 1I II II 11 II 11 I DATA
-r-.----1- ?I l:, 21 21'

11 1 Il l
24 73 72 21
Il
20 1911 II 6 115
TROIEI mom
ESATC 11
I
I IMO 44144 Irms 441T ICI LCI LC1O LC11 L 12 LCI3 L 14 V0 DATA 5T17NR
LIIC136 -3
A4111 Au A14 LC1 LC2 LC3 1C4 LCD LCI LC7 Wu 0 6110 :LOCK
106 4 1 p 16 p p0 pi 12 114
i-IIIL L I LILL J-11

3 3
t5
1 I1 11 II IS II II I
+ 47,, + 43,
I Zi 111211 13
el III 24 is
11 25 a2f 11 17
it is I
amen. m.1 -JL.AL -JL -JL -J
loo IMP
240
27kf ADJ
1001 1001
-7 5V L111371 - 154
I. UT IN
LI1/33
470
166 O VOUTA
27k
111A 0 VIA, It
Vs
*-1
1114
+ I5V -150
IL, HM3753 - 1
FIGURE 7. Stereo 7 -Band Equalizer
TABLE I: Tuned Circuit Elements

MN LC P11230020
00= 3.5, 012d0 = 1.05
L0 -C1 AL RO
Z1 to (Hz) Co (F) CL (F) RL (dl) Ro (a)
Z1 83 1µ 0.1µ 100k 680
Z2
Z3
160
400
O.47µ
0.15µ
0.033µ
0.015µ
100k
100k
680
680
ao_a
Z4 1k 0.068µ 0.0068µ 82k 680 12 dB
Ro +°0 1510
Z5 2.5k 0.022µ 0.0033µ 82k 680
Z6 6.3k 0.01µ 0.0015µ 62k 680
Z7 16k 0.0047µ 680p 47k 680 L=
(150012551/1611e1111,111/
.J
kill
TL/H/6:53-12
FIGURE 8. Tuned Circuit for Stereo

7 -Band Equalizer (Figure 7)
Performance Characteristics (Circuit of Figure 7)
LM835 Galn vs Frequency LM835 Gain vs Frequency LM835 Gain vs Frequency LM835 Gain vs Frequency
Cs ± 12 dB Range 12 dB Range g 6 dB Range ±6 dB Range
(All Boost or Cut) 1 kHz Boost or Cut) (All Boost or Cut) (1 kHz Boost or Cut)
TO
12
5111 .IIIIDIIIHIIIN III
16
12
myIU
Mil 11.011111 I alimi sow
Iii 1
Mil 06091111p mum I mom
Ell 0 1111111w N511111b M51111i.
INN II, 01111' 611111160.10,1 U.S II 611111111 A11111111 0111116
0..ii mu Ih 1511111' '11111011111111116 IN1110 6.1110 1111161 Me111x1
./.1rAvo. mom on
it IN/
4
1111111 6111111/ 1111111E1111m
U.S ob. '1111111111161 811111 ..4. Ono 111111111
4
r.v..'. 4
1111 DIP -6 .16 .106- ',Mow 2
IN11 he' ...rte IIll1111110
0
U.S
.666111 .1MOSte.
711/1I SUM g0 a
2
0
NON ."1....
MIN ..7.68NOIs."
wm
3 -4
-1 "ostI
1.1
A
11.1, ism
3 -4
Mai
nil /11061111.III
,1111111MNIIII
M11110101811.
1111111101 6
4111411N Ill -2
3-2
4
Win II
.111111
- 17 -12 U.S III 1111, ''41111111601Niiiii
U.S 11401111m .111111164.81011 -6 -1 Min
111111A1111116606/8iiAINI1101 - IA 1111111101111611111111Milliii6 -
110 100 IK 10K 100K 10 00 1K 100 100K is 100 IR 104 10011 10 100 1K 10K 100K
FREQUENCY INT) FREOUENCY IRO FREOUFNCY 11411 FREQUENCY 1111

M National
LMC835 AEA Semiconductor
Typical Applications (Continued)
6 6k
276
INA 0 'A&
7 470
Ytte 0 ANT
276
_L
ii..mi
I
I
II
IIIII
Is
11 II is 1111611 zii111121
II I` I
II II
10k + 7 Ai
2Lri Ir 1 Li
10 01005
I 10 DATA
STO 1f pm IC - 1.111 is
21 2112{125 23 2 21 20 11 17 11 15
A 000 A1111 AIMS A1117 ICI LCI LCIO LCII LC12 LC13 1014 VA OAT* iffir'n
LIAC135
Lo' CL Rt. Ro
Atm Amu Aim A1114 LC1 LC2 LC3 LC4 105 LO6 17 Wis D ONO
12 13 4 5 11 7 1 0 10 11 12 13 I4 CLOCK 00 rc0-1°R02
17 D OND
Ro00
-750 1 01263
1L"1 ;11L1X.1171)..
II I
L
I II 11 11
g Z1 1 g 22 11 2 ig 24 11 25 1 116 1 1 27
II II (t590055k21611011kAllk# kil)
IL/H/6753-15
I el II II II I II II
Lama/ 1.10.11.1111..ma.4.4 4.4..m.11 FIGURE 10. Tuned Circuit for
FIGURE 9. 12 -Band Equalizer 12 -Band Equalizer (Figure 9)
Performance Characteristics (Circuit of Figure 9) TABLE II. Tuned Circuit Elements

00 = 4.7, 012 dB = 1.4
12 Band Eql alizer Application
LM835 Gain vs Frequency fo (Hz) Co (F) CL (F) RL. (a) Ro (n)
C ± 6 dB Range
Z1 16 3.3µ 0.47µ 100k 680
(All Boost or Cut)
1/,' 1, ...a-mit, Z2 31.5 15µ 0.22µ 110k 680
/41111111.141111111101111111M1111
UI
Z3 63 1µ 0.1µ 100k 680
Alit= 8. 11'11.0.11. a AI"
1111111111111.r.rgil Z4 125 0.39µ 0.068µ 91k 680
4
iv .,..1 111M/11111
p .s.v 0.4. a.. .5 ra
Z5
Z8
Z7
250
500
1k
0.22µ
0.1µ
0.047µ
0.0331.4
0.015p.
0.01p.
82k
100k
82k
680
680
680
_2 .ti 4.11.
W*11.4 WO 1 It 11 Z8 2k 0.022µ 0.0047µ 91k 680
_4 111.'2/1.0041. 1/.11.V.' if Al
II ell 'IV 111 11 I. Z9 4k 0.01p 0.0022p. 110k 680
-1 101111115111111111111111111111111101 Z10 8k 0.0068µ 0.001p 82k 680
_1 5111111151111111 011111111111111 1111
Z11 16k 0.0033p. 680p 82k 680
20 ISO tK 10K 1001 Z12 32k 0.0015p. 470p 68k 510
FREOUEICY IRO
LM835 12 Band E.Q. Application 12 Band Equalizer Application 1.11835 12 Band E.O. Application
Gain vs Frequency LM835 Galn vs Frequency Gain vs Frequency
C ± 12 dB Range ID ± 12 dB Range ±111d13 Range
(1 kHz Boost or Cut) (All Boost or Cut) 1 kHz Boost or Cut)
16 16
111101111111111111 [NOM 11 /el agO11i1 511111 11111 Mill NOM
11111114111111110 11111111 1E1111111 4/104110 11111 ..00011.14114 IMMiu Sill 5111111
12 12
'014 6
Will 5011111
6
1111111 11111N11111 .111111 71111:11
01111.1111'
11111111.111'. 1111 1111111111
111111 01111 11
W
.11' VIA
h A'
l II
1:01 11 A'1'.1 410.
I
4 05111
11II,Sell'
11111 11111
11111
r.1%.4'.1. A 47. .V.,....1411.1 Maui Nom
z
4
0
111.111111111
Sam
11011 1
1111119111111111
t ' "Aro 46 ".*..' .. MR14, 2
Mel
581
Main.
0
11111111n
mow.
3
11/1 1,1si
S....11
41111,111111
VOL".
61!/'''1.'4'1' '84' 1.1 I'A III
04 0
-2 1111176O111
M1111 111
O1111
ll 011111
11101111 1I 0111111111111111
1.111111 111111 111111111111111
-6 S111or11" 11.1. 11 .00;1 1.1.111'
H. a 11111 411111 111/1111'4 -4 IN111111,1111
10111111 51111
. IOW 1.11111
111111 M1111
-12 Sill 11 1.111111 A111111 -12 17 IVO A.4:J 4:111:/li4
UMW MUM; Mimi Innis' -6 111111111 1111111 /111111
IN111111 M1111.1 51111 51111
1111111
11111111111111111111 M11 111111111i
511111, 110111111 ilM11111 "7.611111
-s 11111 155111.1 000111 1111111
16 - 16
11 100 IR 1011 2006 10 100 70 ITN 100K 70 101 IK 100K
F1E0UEKC1(Hz) t51001001 IN) TNEWENCY INT)

National
LMC835 XASemiconductor
10n
1,
184°2:1 I EACH INPUT
LN$33 I 410
SELECTABLE
GAIN IS OFF
41/1V 0 00971 - 17 dB TO .14 dB
11180
47, 41,, r-ir-ir-lr

II II II II
r
II II
r-' I
I 11 11 zt I I Z3 Id 24 11 25 11 ZE g 1 Z7 I V44 BV TO 15V
Ilk a II II II II II II I
OATH
F.+ STROBE
21 It 15 25 f24 12:1121 12.111201..1791 17 6
A 0110 Own 4104 I L9 ICIO LC11 LC12 L:13 1C14 V. 0 TA STACIE
LIIC435
5 11 Ami Aift/ 403 AIN4 LC1 1C2 1C3 1 4 LC5 ICS 1 7 V. 0 090 CLOCK
STRIAE
12_4,,
_t
100 7 8 9
; ;_
CLOCK
47 47, , II is"
1
Is 1 1
;_ J
1
i 0 680
CLOCK
1 11 11 12 11 Z3 11 24 1 1 15 1 1 16 1 1 17 1 0 GOO
I II II II II II II I
100p 111000 L-JL-JL-JL-J L-JL-JL-J
Tt 01 6753 16
1000 FIGURE 12. Stereo 7-Input/1-Output Mixers
1006 1000 (THD is not as low as equalizer circuit)
004 ion
000971
111833
tr
VIMA 081.1 I 01113
FIGURE 11. Single Supply Stereo Equalizer
.5V
IIH, 30 011 - 30 dll
12
V
VOW.
STROBE 83
25
0 080
16
4
STROBE
14
CLOCK
TUN/8753-20 87 IP 0 GNO
FIGURE 14. LMC835-COP404L CPU Interface 1
TL/H/6753-10
FIGURE 13. Stereo Volume Control, Very Low THD
Application Hints
HOW TO AVOID SWITCHING NOISE DUE TO LEAKAGE
SWITCHING NOISE CURRENT (Refer to Figures 7 and 8)
The LMC835 uses CMOS analog switches that have small To avoid switching noise due to leakage currents when
leakages (less than 50 nA). When a band is selected for flat changing the gain, it is recommended to put RLEAK = 100
gain, all the switches in that band are open and the resona- Kft between Pin 3 and Pin 5-11 each, Pin 26 and Pin 12-
tor circuit is not connected to the LMC835 resistor network 24 each. The resistor limits tie voltage that the capacitor
It is only in the flat mode that the small leakage currents can can charge to, with minimal effects on the equalization. The
cause problems. The input to the resonator circuit is usually frequency response change die to RLEAK are shown n Fig-
a capacitor and the leakage currents will slowly charge up ure 15. The gain error is only 0.2 dB and 0 er-or is only 5%
this capacitor to a large voltage if there is no resistive path at 12 dB boost or cut.
to limit it. When the band is set to any value other than flat,
the charge on the capacitor will be discharged by the resis-
tor network and there will be a transient at the output. To
limit the size of this transient, RLEAK is necessary

M National
LMC835 Am Semiconductor

Sample Subroutine Program for Figure 14, LMC835-COP404L CPU Interface
HEX
CODE LABEL MNEMONICS COMMENTS
3F LMC835: LBI 3F ;POINT TO RAMADDRESS 3F
05 SEND LD ;RAADATA TO A
22 SC ; SET CARRY
335F OGI ;SET PORT G= 1111, OPEN THE AND GATES
4F XAS ;SWAP A AND SIO, CLOCK START
05 LD ;RAII:DATA TO A , MAKE SURE A = DATA
07 XDS :SWAP A AND RAMDATA, RAMADDRESS=FtAAIADDFtESS-1
05 LD ;RAIDATA TO A
4F RAS ;SWAP A AND SIO
05 LD ;RAMDA TA TO A, MAKE SURE A=NEWDATA
07 XDS ;SWAP A AND RAMDATA , RAMADDRESS=RAMADDRESS-1
32 RC ;RESET CARRY
4F XAS ;SWAP A AND SIO, CLOCK STOP
335D OGJ 13 ;SET PORT G=1101, MAKE STROBE LOW
335B OGI 11 ;SET PORT G=1011, MAKE STROBE HIGH, CLOSE THE
GATES
4E CBA ;BD TO A
43 AI SC 3 ;RAIIADDFtESS < 3C THEN RETURN
48 RET
80 JP SEND
RAM
ADDRESS COMMENTS
3C DATA ;GAIN DATA D4 -D7
3D DATA ;GAIN DATA DO -D3
3E DATA ;BAND DATA D4 -D7
3F DATA ;BAND DATA DO -D3
Application Hints (Continued)

REDUCING EXTERNAL COMPONENTS
The typical application shown in Figure 7 is switching noise amps. Selecting a low Ibis and Voryset op amp can minimize
free. The DC -coupled circuit in Figure 16 is also switching the switching noise due to the 12 dB/6 dB switch. The DC -
noise free, except at 12 dB/6 dB switch turn ON/OFF. This coupled application can also eliminate the FF= 100k resis-
switching noise is caused by the lbcas and Voesetof the op tors with only a 0.5 dB gain error at 12 dB boost or cut.
L141-33
0 VOW
1004
1001
1004
r"Aq V011i
47,, j_
1001 -.-
Z. 27 26 75
44.114,
24
Rau
7 31.4"..411rrik.\.
341 341 LI0C135
0 0
1101
17 01/6 41
FrY07771 -1-r10
644
TUH/6753 21
DC COUPLING MODEL
AC COUPLING TUH/6753-21
FIGURE 16. Reducing External Components

12 0
00
/ 10 -0 10.0
FIGURE 15. Effect of RLEAK RESULT TL/H/8753-22

FAIRCHILD
A Schlumberger Company i,tA212A, µ,A212AT
1200/300 bps Full duplex Modem

The pA212A and the pA212AT 1200 bps modem circuits 28 -Lead Dip
are fabricated in Fairchild's advanced Double -Poly Silicon - (Top View)
Gate CMOS process. Either monolithic chip performs all
signal processing functions required for a Bell 212A/103
compatible modem. Dialing, handshaking protocols, and SLIM 1 25 Voc
mode control functions can be provided by a general pur-
LIM 2 V Vie
pose single -chip pC. The pA212A or pA212AT and pC;
along with several components to handle the control and UXIN 29 10110
telephone line interfaces, provide a high performance, iSbT TEO
cost-effective solution for an intelligent Bell 212A -compati-
ETC 34 oi5
ble modem design.
rTM 23
Either modem chip performs the modulation, demodulation, ESiFf 22 !CT

filtering and certain control and self -test functions required 21 MOn31
for a Bell 212A -compatible modem, as well as additional
functional enhancements. Switched capacitor filters provide SCRIM 20 11002
channel isolation, spectral shaping and fixed compromise rE5 10 10 111T

equalization for both high and low speed modes. ETU 11 11 MEW
XTLI 12 17 1751.2
A novel switched -capacitor modulator and a digital coher-
ent demodulator provide 1200 bps QPSK operation while a SCR '14 1441. 1
separate digital FSK modulator and demodulator handle RED 11 ji

the 0-300 bps requirement. The pA212AT includes an inte-
(Avow
gral DTMF tone generator on -chip. The pA212A without
DTMF generator, is cost optimal for answer -only applica-
tions or if an external dialer is present. The pA212A and
pA212AT are otherwise pin and firmware compatible. Exist-
ing pA212A applications can be easily upgraded to the Order information
Temperature
pA212AT with minor software changes (see technical bul-
Type Range Code Package
letin M-1 appended.) The receive filter and energy detector
may be configured for call progress tone detection (dial - pA212ATDC 0 to +70°C FM 28 -Lead Ceramic DIP
tone, busy, ringback, voice), providing the front end for a pA212ATDV -40°C to +85°C FM 28 -Lead Ceramic DIP
smart dialer on either the pA212A or pA212AT. pA212ATPC 0 to + 70°C 28 -Lead Molded DIP
A...A212ATOC 0 to +70°C 28 -Lead Molded
Functions as 212A and 103 Compatible Modem Surface Mount
Performs all Signal Processing Functions pA212ADC 0 to +70°C FM 28 -Lead Ceramic DIP
Interfaces to Single Chip pC Which Handles pA212ADV -40°C to +85°C FM 28 -Lead Ceramic DIP
Handshaking Protocols and Mode Control Functions pA212APC 0 to +70°C 28 -Lead Molded DIP
DTMF Tone Generation (pA212AT) 'Consult Factory
pA212A Is Pin and Firmware Compatible with the
pA212AT for Easy Upgrade Absolute Maximum Ratings
Call Progress Tone Detection for Smart Dialer VDD to DGND or AGND 7.0 V
Applications Vss to DGND or AGND -7.0 V
On Chip Oscillator Uses Standard 3.6884 MHz Crystal Voltage at any Input VDD + 0.3 to
Few External Components Required Vss -0.3 V
industrial Temperature Range Option (-40°C to Voltage at any Digital Output VDD + 0.3 V to
+85°C) DGND -0.3 V
Operates from +5 and -5 Volt Supplies Voltage at any Analog Output VDD + 0.3 V to
Low Operating Power: 35 mW Typical Vss -0.3 V
28 -Lead Ceramic DIP, 28 -Lead Plastic DIP, and Operating Temperature Range 0°C to 70°C
28 -Lead Surface Mount Packages Storage Temperature Range - 65°C to +150°C
A pA212A Designer's Kit is Available Lead Temperature (soldering, 10 a) 300°C
Pin No. Pin Description Pin No. Pin Description
28 VDD Positive power supply VDD - +5 V
26 AGND Analog Ground 9 SCRM Scrambler. "0" disables scrambler
and descrambler for testing pur-
18 DGND Digital Ground poses.
27 Vss Negative power supply Vss = -5 V 12 XTL1 Frequency control. 3.6834 MHz
3 RXIN Line signal to modem. From active 11 XTL2 XTAL oscillator, operating parallel
or passive Hybrid output. mode. Provides trning, sample
clocks and L.O.'s.
25 TXO Line signal from modem. To active
or passive Hybrid input. 8 HS Selects modem speed. selects
1
1200 bps. 0 selects 300 bps. (Note)

24 0/A Orig/answer Mode Select. Assigns
channels to XMTRS/RCVRS. 6 SYNC Selects CHAR ASYNC or BIT SYNC
1 - Originate mode, 0 - Answer mode. 1 ASYNC mode: enables
mode. (Note) XMIT & RCV buffers, sets character
length according to M001, MOD2
23 TXSZ Squelch XMTRS in date mode. pins. 0 SYNC mode: disables buf-
0 = Both XMTRS off; 1 - turns on fers, selects TX clock source ac-
XMTR selected by HS pin. cording to MODI, MOD2 pins.
pA212AT: In dialer mode, 0 = DTMF Active only if HS - 1.
generator OFF/call progress detec-
tion. 1 = DTMF generator ON. 21 MOD1 Selects character length (ASYNC) or
piA212A: In dialer mode call prog- Note
ress detection only. nT3-05 must be For (rA212AT dialer mode. D/A. HS. MOD1 and MOD; select the OTME
set to 0. to be generated (see Table 2)

FAIRCHILD
A Schlumberger Company
µA21 2A, ,u,A21 2AT
Pin No. Pin Description Functional Description*

Refer 'o Figure 1
20 MOD2 TX clock (SYNC). In ASYNC mode,
selects 8, 9, 10 or 11 bit character
Transmitter
length; in SYNC mode, selects inter- The transmitter consists of high-speed and low -speed mod-
nal, external or recovered RCV ulators, a transmit butter and scrambler, and a transmit
clock as XMTR data clock source
filter a -id line driver. In high-speed asynchronous mode,
Active only if HS = 1. (See Table 1)
transmit data from the Data Terminal Equipment enters the
(Note)
transmit buffer, which synchronizes the data to the internal
10 XD XMIT Data. Serial data from host. 1200 bps clock. Data which is underspeed relative to 1200
Disconnected when in digital loop bps periodically has the last stop bit sampled twice result-
14 RXD RCVD Data. Serial data to host, In- ing in an added stop bit. Similarly, overspeed input data
ternally clamped to mark ( = 1) periodically has unsampled - and therefore deleted - stop
when modem is in digital loop or bits. The MOD1 and MOD2 pins choose 8, 9, 10 or 11 bit
EDET is inactive ( = 1). character lengths. In synchronous mode the transmit buffer
is disabled. The transmitter clock source may be chosen
22 SCT Serial Clock Transmit. 1200 Hz
by MOD1 and MOD2 internal, external or derived from the
clock providing XMTR timing in
recovered received data. A scrambler preceeds encoding
SYNC mode. SCT source (INT.,
to ensure that the line spectrum is sufficiently distributed
EXT., SLAVE) selected by MOD1,
to avoid interference with the in -band supervisory single-
MOD2 pins. TXD changes on nega-
frequelcy signaling system employed in most Bell System
tive edge, sampled on positive
toll tanks. The randomized spectrum also facilitates timing
edge. Internal clock provided in
recovery in the receiver. The scrambler is characterized by
ASYNC mode.
the following recursive equation:
5 ETC External Transmit Clock. 1200 Hz
external clock providing XMTR tim- Vi" Xi ®Yi-14 ®Yi-17
ing in SYNC mode, selected by
MOD1, MOD2 pins. TXD changes where Xi is the scrambler input bit at time i. Y, is the
on negative edge, sampled on posi- scrambler output bit at time and 0 denotes the XOR
i
tive edge. Provided on SCT pin if operat on.

selected.
13 SCR Serial Clock Receive. In SYNC 212A -type modems achieve full -duplex 1200 bps operation
mode, 1200 Hz bit clock recovered by encoding transmitted data by bit -pairs (dibits), thereby
from RCVD signal. May be pin -se- halving the apparent data rate. The resultant reduced
lected (MOD1, MOD2) as local spectral width allows both frequency channels to coexist in
transmit clock (SLAVE mode); pro- a limitad bandwidth telephone channel with practical levels
vided on SCT pin if selected. RXD of filtering. The four unique dibits thus obtained are gray -
changes on negative edge, sampled coded and differentially phase modulated onto a carrier at
on positive edge. Undefined in AS- either 1200 Hz (originate mode) or 2400 Hz (answer
YNC mode mode) Each dibit is encoded as a phase change relative
7 EDET Energy Detect. In data mode, to the phase of the preceding signal dibit element:
EDET = 0 if valid signal above
threshold is present for 155 4 50 Dibit Phase Shift (deg)
ms, EDET = I if signal below
00 +90
threshold for - 17 7 ms. In dialer 01 0
mode, follows on/off variations of 1 I -90
call -progress tones, when TXSO = 0 10 180
15 T Remote Loop Status, used in RDL
mode. Responding modem: sets At the receiver, the dibits are decoded and the bits are
RLST - 0 upon receipt of unscram- reassembled in the correct sequence. The left-hand digit
bled mark for 154 - 231 ms. initiat- of the dibit is the one occurring first in the data stream as
ing modem: asserts RLST 0 upon it enters the modulator after the scrambler. The lowspeed
receipt of scrambled mark for transmitter generates phase -coherent FSK using one of
231- 308 ms. (See Table 3). two programmable tone generators. Answer mode mark
SLIM Soft Limiter Output. Connect exter- (2225 Hz) is also utilized as answer tone in both low and
nal 0.033 NF capacitor here. high speed operation.
2 LIM Comparator input. Connected exter- In Die er mode, both tone generators are employed to
nal 0.033 uF capacitor here. generate DTMF tone pairs. The summed modulator outputs
4 DOT If HS - 1, forces a 1200 bps dotting drive a lowpass filter which serves as a fixed compromise
pattern on the transmit path, for use amplitude and delay equalizer for the phone line and re-
when programming the 212AT high duces output harmonic energy well below maximum speci-
speed self -test mode. Both RCV fied levels. The filter output drives an output buffer
and XMIT paths are in SYNC mode amplifier with low output impedance. The buffer provides
during dotting transmission, overrid- 700 rrVrms in data mode, for a nominal -9 dBm level at
ing the setting of SYNC, and of the line, assuming 2 dB loss in the data access arrange-
HSK1, HSK2. If HS - 0, DOT forces ment.
a 155 bps dotting pattern for use in
lowspeed self -test mode. 1 - Normal DTMF Tone Generation
The mA212AT includes on -chip DTMF generation, using
Path, 0 - Dotting.
two programmable tone generators. Dialer mode must be
19 TEST When the TEST pin is inactive selected on TEST, HSK1 and HSK2 for DTMF dialing. The
16 HSK1, (high), HSK1 and HSK2 select one 0/A, HS, MOD1 and MOD2 pins are used to select the
17 HSK2 of four transmit conditions, for use required digit according to the encoding scheme shown in
when programming the Handshake Table 2, and the tones are turned on and off by the logic
sequences. (See Table 1). When level cn TXSO. The generated tones meet the applicable
TEST is active (low), the HSK1 and CCITT and EIA requirement for tone dialing. DTMF output
HSK2 pins select one of three test levels are 1.0 Vrms (low group) and 1.25 Vrms (high
conditions, or, alternatively, the dial- group)
er mode used for call progress tone
detection and DTMF tone genera- For ecl-fitiortel informabon contact sales office for Applications Note ASP -1
tion, pA212AT only. Theory of Operation- pA2 1 2 A " and Technical Bulletins 1.41, M3 S AAA

FAIRCHILD
A Schiumberger Company aA21 2A, p. A21 2AT
Figure 1 Block Diagram
03M
EDET
WM UM I
DEPOT
RECEIVE FILTER DETECTOR
SALANC-ED
faxER
ANTI -ALIAS NM - OPSK DONT
FILTER
DESCRAMBLER SCAM
FILTER SANC...S$FILTER DEMODULATOR DE CODER
SOFT
LIMITER
SEIM Um CARRIER RECEIVE

LIMITER
pLL BUFFER
XTL2
1I
[=1 CLOCK RECOVERY

CRYSTAL CLOCK TEST
3SPF rrit OSCILLATOR GENERATOR C IRC L/TR LOOP/FM(
DEMODULATOR
MUX Ere
1041.10) ETC
SCT -
Fit LPF, ORMIAL
SLICER LOOP
TRANSMIT OPSK TRANSMIT

TX° E NC 00E SCRAAUER M
FILTER MOOULAT OR Muffin
FSK DTMF
MOCKILAT OR /GE ME RATOP
1111
AGAID OGNO TOO Vss TESO
f
HSK I
flrif
HSK 2 TEST DOT M001 M002
t
HS
pA2 1 2A T only
Receiver mode the descrambler output is identically tie received

The received signal from the line -connection circuitry pass- data, while in asynchronous mode the descrambler output
es through a lowpass filter which performs anti-aliasing stream is selectively processed by the receive butter. Un-
and compromise amplitude and delay equalization of the derspeed data presented to the transmitting modem pass-
incoming signal. Depending upon mode selection (origi- es essentially unchanged through the receive buffer.
nate/answer) the following mixer either passes or down Overspeed data, which had stop bits deleted at the trans-
converts the signal to the 1200 Hz bandpass filter. In ana- mitter, has those stop bits reinserted by the receive buffer.
log loopback mode, the receiver originate and answer (Generally, stop bit lengths will be elastic). -he receive
mode assignments are inverted, which forces the receiver buffer output is then presented to the receive data pin
to operate in the transmitter frequency band. The 1200 Hz (RXD) at a nominal intracharacter rate of 1219.05 bps.
bandpass filter passes the desired received signal while
attenuating the adjacent transmitted signal component re- Master Clock/Oscillator/Divider Chain
flected from the line (talker echo). The chosen passband The µ4212A or pA212AT may be controlled by either a
shape converts the spectrum of the received high-speed quartz crystal operating in parallel mode or by an external
signal to 100% raised cosine to minimize intersymbol inter- signal source at 3.6864 MHz. The crystal should be con-
ference in the recovered data. Following the filter is a soft nected between XTL1 and XTL2 pins, with a 30 pF ca-
limiter and a signal energy detector. An external capacitor pacitor from each pin b digital ground (see Figure 1).
is used to eliminate offset between the soft limiter output Crystal requirements; Rs < 150 ohms, CL - 13 pF, parallel
and the following limiter. mode, tolerance (accuracy, temp, aging) less than ± 75
ppm. An external TTL drive may be applied to the XTL2
The energy detector provides a digital indication that ener- pin, with XTL1 grounded. Internal divider chains provide
gy is present within the filter passband at a level above a the timing signals required for modulation, demodulation,
preset threshold. Approximately 3 dB of hysteresis is pro- filtering, buffering, encoding/decoding, energy detection and
vided between on and off levels to stabilize the detector remote digital loopback. Timing for line connect and dis-
output. In dialer mode, the detector output is used to pro- connect sequences (handshaking) derves frcm the host
vide logic level indication of the presence of call progress controller, ensuring maximum applications flexibility.
tones.
Control Considerations
The limiter output drives the QPSK demodulator and the The host controller, whether a dedicated microcontroller or
carrier and clock recovery phase -locked loops. The low a digital interface, controls the p.A212A or pA212AT as
speed FSK demodulator shares part of the clock recovery well as the line connect circuit and other IC s. On -chip
loop. The QPSK demodulator and carrier loop form a digi- timing and logic circuitry has been specifically designed to
tal coherent detector. This technique otters a 2 dB advan- simplify the development of control firmware.
tage in error performance compared to a differential
demodulator. The demodulator output are in -phase (I) and Operating and Test Modes
quadrature (0) binary signals which together represent the Table indicates the operating and test modes defined by
1
recovered dibit stream. The dibit decoder circuit utilizes the the eight control pins. The pA212A and pA212AT (togeth-
recovered clock signal to convert this dibit stream to serial er with the host controller) supports analog loopback, and
data at 1200 bps. local and remote digital loopback modes. Arelog loopback
forces the receiver to the transmitter channel. The control-
The recovered bit stream is then descrambled, using the ler forces the line control circuit on -hook but continues to
inverse of the transmit scrambler algorithm. In synchronous monitor the ring indicator. This mode is available for low-

FAIRCHILD
A Schiumberger Company µA21 2A,[tA21 2AT
speed, highspeed synchronous and highspeed asynchro- (TEST = HSK1 HSK2 - 1), RCS. 'T is set to
nous operation. In local digital loop, the modem I.C. 0. Upon detecting this the controller
isolates the interface, slaves the transmit clock to SCR responds by setting TEST and HSK2 to 0,
(high-speed mode), and loops received data back to the and the modem I.C. isolates )17i5, clamps
transmitter. In remote digital loop, local digital loop is initi- riXD to 1, and transmits a 1200 bps
ated in the tar -end modem by request of the near -end scrambled dotting pattern. At this point,
modem, if the far -end modem is so enabled. The pA212A upon receipt of a scrambled mark signal,
and µA212AT includes the handshake sequences required the modem I.C. internally loops RCVR data
for this mode; the controller merely monitors RUST and and clock to the XMTR, and sets InTgr
controls remote loopback according to Table 3. Remote back to 1. (See Table 3)
loop is only available in high-speed mode.
31aler Mode The µA212AT provides DTMF tone
generation and energy indication at EDET
Answer Tons In this mode, 2225 Hz answer tone is
pin to identity call progress tones, i.e. dial,
transmitted provided TYM is inactive high
busy and ringback. The DTMF digit is
( - 1). Receive speed is selected as normal
selected by the levels on 0/A, HS. MOD1
with the HS pin. This permits the speed of
and MOD2 according to Table 2. Tone
the originating modem to be determined
generation is turned on and off by the
while answer tone is continuously
level on TXSO. 1 = on, 0= off. The
transmitted.
i.,A212A provides call progress indication
Force Disconnects TO pin from the transmitter only. TXSO must be set to 0.
Continuous and forces the signal internally to a mark
Mark (logic 1). Table 2 DTMF Encoding2 (µA212AT only)
Force Disconnects T715 pin from the transmitter 0/A HS MOD1 MOD2 DTMF Digit
Continuous and forces the signal internally to a space
Space (logic 0). 0 0 0 0
0 0 0 1
Analog Loop Receiver is forced to the transmitter 0 0 0 2

channel. With modem on -hook 0 0 3
(disconnected from line) signal from TXO is. 0 0 0 4
reflected through hybrid to RXIN. 0 0 5
Local Digital Internally connects AZ to n05 and SCR 0 0 6
Loop to SCT. Transmitted data (nrs) and clock 0 7
(ETC) are ignored. SCR and SCT are 0 0 0 8

provided. 1;715 is forced to 1. 0 0 9
0 0
Remote Initiating modem: If RDL is initiated 0
Digital (TEST - 0, HSK1 - 1, HSK2 - 0), T7E5 is 0 0 A
Loop isolated, FIXD is clamped to a and1
0 B
unscrambled mark is transmitted. When 0 C
high speed scrambled dotting pattern is D
detected, scrambled mark is transmitted. At
this point, upon receipt of scrambled mark, Notes
ALST is set to 0. I DIM' digit is selected according to Table 2 for the HA212AT. 17M
enaPes the tone generator 1- ON, 0 - OFF TXSO -0 allows energy
detectton of call progress tone in both the p.A212A and yA212AT
Responding modem: Upon receipt of 2 For DTMF to operate dialer mode must be asserted. TEST HSK1 and
unscrambled mark when in data mode HSK2 must be - 0
Electrical Characteristics Unless otherwise noted: VDD = 5.0 V ± 5%, Vss = -5.0 V ± 5%, DGND = AGND = 0
V, TA = 0°C to 70°C, typical characteristics specified at VDD = 5.0 V, Vss -5.0 V,
TA = 25°C; all digital signals are referenced to DGND, all analog signals are
referenced to AGND.
Table 1 Operating and Test Modes

NW HS SYNC MOD1 MOD2 TEE -ST HSK1 HSK2 Description SCT
0 - X X X 1 1 1 Dotting Pattern (155 or 1200 bps) INT
1 - - - - 1 0 0 Answer Tone X
1 - - - 1 0 1 Force Continuous Mark X
1 - - - - 1 1 0 Force Continuous Space X
1 1 1 0 0 1 1 1 ASYNC, 8 Bit INT
1 1 1 0 1 1 1 1 ASYNC, 9 Bit INT
1 1 1 1 1 1 1 1 ASYNC, 10 Bit INT
1 1 1 1 0 1 1 1 ASYNC, 11 Bit INT
1 1 0 1 1 1 1 1 SYNC, Internal INT
1 1 0 1 0 1 1 1 SYNC, Slave SCR
1 1 0 0 1 1 1 1 SYNC, External ETC
- - - - - 0 0 1 Analog Loop ETC
1 - X X X 0 1 1 Local Digital. Loop SCR
1 1 X X X 0 1 0 Response to Far End Request for RDL SCR
1 0 X X X - - - Low Speed Mode X
1 X X X X 0 0 0 Dialer Mode, Note 1 X
1 1 - - 0 1 0 9emote Digital Loop Initiate X
Key:
SCT - TX Buffer and PSK Modulator Clock INT - Internal 1200 Hz Clock
SCR -Recetve Clock X -Don'. Care
ETC - External Clock Input - - Set as appropriate for desired operating condition.

FAIRCHILD
A Schlumberger Company ptA212A µA212AT
Table 3 Remote Digital Loopback (RDL) Command Sequences

Modem Action Controller Action TEST HSK1 HSK2 Flat
Data Mode 1 1 1 1
Initiate RDL: "INITIATE RDL" 0 1 0 1
Disable scrambler
Disconnect XD
Force 1 on R705
Transmit unscrambled mark (U.M.)
Recognize Dotting for 231 - 308 ms

Enable scrambler
Transmit scrambled mark (S.M.)
Recognize S.M. for 231 - 308 ms

Connect T
Unclamp R
"RDL ESTABLISHED" 0 1 0 0
Response to far end request: 1 1 1 0

U.M. recognized for 154 -231 ms
"RDL REQUESTED" "RDL RESPONSE OK" 0 1 I 0 0
Disconnect 'OM
Force on RXD
1
Force Sync Slave Mode

Transmit Dotting
S.M. recognized
Internally loop Receiver to Transmitter
"RDL ESTABLISHED" 0 1 0 1
Terminate RDL: TX-SZ active 80 ms 1 1 1' 0

Reset to Data Mode 1 1 1
*TEST- HSK1 - HSK2 - 1 may be asserted at anytime after "RDL ESTABLISHED' and before terminating.
Energy Detector
Symbol Characteristic Condition Min Typ Max Units
Vthon Off/On Threshold Voltage Level at RXIN 6.5 mVrms
Vthott On/Ott Threshold Pin In Data Mode 5.2
ton Energy Detect Time Data Mode at EDET Pin 105 155 205 ms
toff Loss of Energy Detect Time 10 17 24 ms
Vthon Dialer Mode

vthon Off/On Threshold Dialtone Voltage Level at RXIN 10 mVrms
Vtnon Ott/On Threshold Busy/Ringback Pin in Dialer Mode 4.6
too Energy Detect in the Dialer Mode At EDET Pin 25 30 35 ms

(Detecting Call Progress Tones)
ton Energy Detect in the Dialer Mode 30 36 42 ms
(Detecting Call Progress Tones)
System Performance
BER Blt Error Rate: SNR required for Plane - -30 dBm 13 dB
BER - 10-5 CO 1200 bps on a Plow - -44 dBm 14 dB
3002 -CO line, with 5 kHz white noise
referred to 3 KHz. Figures shown are
for originate mode. (Note: Pi,43 values
assume 4 dB net gain from line to
RXIN)
Telegraph Distortion Back -to -Back. 300 bps 10 % Peak
(Low Speed Mode)
Analog Line interface

Vi,o Output Level at TXO: Data Mode 0.7 Vrms
Vtonh Output Level at TXO: DTMF HIGH Group 1.1 Vrms
Vtonl Output Level at TXO: DTMF LOW Group 0.9 Vrms
Vitygn Output level at TXO: 0.5 mVrms
Pcort Extraneous frequency output relative to Any DTMF digit -20 dB
DTMF power.
Voo Output Offset at TXO 5.0 mV

FAIRCHILD
A Schiumberger Company µ,A21 2A µA21 2AT
Masterclock input
Symbol Characteristic Condition Min Typ Max Unita
Fclock Clock Frequency 3.6864 MHz

Clock Frequency Tolerance - .01 + .01
Tolclk 1
Vexth 1 External Clock Irput HIGH XTL2 driven and XTL1 4.5 V
I
grounded
Vextl 1 External Clock Input LOW XTL2 driven and XTL1 0.5 V
grounded
I
Digital Interface
Symbol L Characteristic Condition Min Typ Max Units
VII_ I Input Voltage LOW 0.6 V
Va.' Input Voltage HIGH 2.2 V
VOL Output Voltage LOW IL = 2.0 mA 0.6 V
VON Output Voltage HIGH IL = -2.0 mA 3.0 V
IL Input Current LOW DGND < Vit.t < VIA, -100 PA
All Digital Inputs
liri Input Current HIGH VIN < Vast < VDD -50 PA
1pp Operating Current VDD = 5.0 V 4.3 10 rnA
No Analog Signals
ISS Operating Current Vss - -5.0 V -2.7 -5.0 mA
No Analog Signals
Transmit Buffer (Character Asynchronous Mode)

Lacher Input Character Length Start bit + data 8 11 bits
bits + stop bit
Rbrcher Intracharacter Signaling Rate At TO pin 1170 1200 1212 bps
1-43,3ak input Break Sequence Length At T5( 5 pin 23 bits
Receive Buffer (Character Asynchronous Mode) Carrier Frequencies and Signaling Rates
Rachel Intracharacter Signaling Rate At FIT1',5( pin 1219.05 bps
Fcxr (ORIG) HS Cxr Freq. (Orig. Mode) Unmoculated Carrier 1200 Hz
F", (ANS) HS Cxr Freq. (Ans. Mode) Unmoculated Carrier 2400 Hz
Baud Dibit Rate High Speed Mode 600 Baud
Frnark (ORIG) Mark Frequency Originate Mode (1270) Low Speed Mode 1289.42 Hz
Fspece (ORIG) Space Frequency Originate Mode (1070) Low Speed Mode 1066.67 Hz
Frna,k (ANS) Mark Frequency Low Speed Mode 2226.09 Hz

Answer Mode.'Answer Tone (2225)
F,pace (ANS) Space Frequency Answer Mode (2025) Low Speed Mode 2021.05 Hz
Farm DTMF Low Frequency Tone Group Dialer Mode 698.2 Hz

771.9
853.3
942.3
Ftonh DTMF High Frequency Tone Group Dialer Mode 1209.4 Hz
1335.7
1476.9
1634.0
TN Tolerance of ail above
Frequencies/Data Rates -0.01 +0.01 %
bps Data Rate Low Speed Mode 0 300 bps
as Electronics Digest Summer 1987

FAIRCHILD
A Schlumberger Company A212A µA212AT
Figure 2 Bit Error Rate vs Signal -to -Noise Ratio

,oi
Pod a -30dElm
I
10
a
a
10'a
a
101
1\k.. LINE TYPE C2 C2

CHANNEL LOW HIGH L" HIGH
...0 CO
10'
4 6 a 10 12 14 16
SIGNAL TO NOISE RATIO ISNR) - dB

moan.
Note
BER measured In synchronous mode, using an AEA S3A channel simulata
DTMF Dialing, the Mode Vexo(rms) Relative (dB)

Data 0.70 0
µA212A and µA212AT DTMF Low 0.88 +2
DTMF High 1.11 +4
The pA212A - the world's first and lowest power 1200/
300 b/s single -chip modem - will be joined, at about mid- Therefore, if Data mode output power to a 600 S2 load is
year, by the µA212AT. The second in a series of Fairchild -9 dBm, tone output dower is -7 dBm (Low group) and
modem IC products, the pA212AT is pin -compatible with -5 dBm (HIGH group). These levels, as well as harmonic
the pA212A with the addition of an integral DTMF tone and out -of -band energy values conform to :he require-
generator. This Bulletin summarizes factors to be consid- ments of EIA RS -496.
ered in current pA212A-based modem designs for migra-
tion to the pA212AT. uA212AT Design -In Considerations
The pA212A and pA212AT are pin-:ompatble and func-
DTMF Access tionally identical for ail modes except DTMF tone genera-
The pA212AT DTMF tone generator is accessed via the tion. The pA212AT can therefore replace the pA212A in
Dialer mode, which is asserted by setting all current and future designs, provided that the following
TEST = HSK1 = HSK2 = 0. In the pA212A, Dialer mode of- considerations are observed:
fers only call -progress tone detection, but, in the
pA212AT, both call -progress tone detection and DTMF Ensure Proper Control Of The 'f-0 Pin When In
tone generation are provided. The DTMF output is enabled Dialer Mode. See Table 1.1.
by TXSO = 1 and disabled by TXSO = 0; Orr should be Provide µController Lines For The 0/A, HS, MOD1
ignored when DTMF tones are being generated. See And MOD2 Pins, if any are not presently provided.
Table 1.1. Plan For Replacement Of The Present Tone Dialing
Scheme. Current pA212A designs with DTMF dialing
Table 1.1. Dialer Mode often employ a dialer chip or a DAC. Ensure that
downstream removal of such parts will lot affect the
I.,A212A µA212AT
design.
0 Call -progress Call -progress Allow ROM Space. Since DTMF contrcl code replaces
Call -progress DTMF generation the previous scheme, this should not u>ually be a
problem.
DTMF Tone -Pair Selection Table 1.3 DTMF Encoding Matrix

The pA212AT employs 4 pins (0/A, HS, MOD1, and REST = HSK1 = HSK2 = 0, )1T-ZO = 1)
MOD2) to generate each of the 4 LOW and 4 HIGH
1
0/A H/S MOD1 MOD2 DTMF Digit
group DTMF tones; nominal tone frequencies are shown in
Table 1.2. Table 1.3 displays the DTMF Encoding matrix. 0 0 0 0 0
0 1
Table 1.2 Tone Frequencies (Hz) 0 2

3
Low Group High Group
0 1 0 0 4
F (Nom.) F (Act.) F (Nom.) F (Act.) 0 5
697 698.2 1209 1209.4 0 6

771.9 7
770 1336 1335.7
852 853.3 1477 1476.9 1 0 0 0 8
941 942.3 1633 1634.0 0 9
0
Output Characteristics 1 1 0 0
Table 1.4 summarizes nominal output levels at the TXO 0 B
pin for Data mode, and for the DTMF Low and High tone
0 C
groups. Absolute values and values relative to Data mode D
are shown.

TEXAS INSTRUMENTS TMS1121
1. TMS 1121 UNIVERSAL TIMER CONTROLLER INTRODUCTION
The TMS 1121 Universal Timer Controller is a mask -programmed version of the TMS 1000 Family 4 -bit single chip
microcomputer providing the function of a programmable time of day, day of week controller. When the TMS 1121 is
used to implement the general purpose timer controller function, as shown in Figure 1, the system features:
18 daily or weekly programmable timer sets

Memory display of programmed timer sets for switches and day of week
4 independent switch outputs with buffer
Display day of week, AM/PM, switch, clock, ON/OFF/SLEEP status
Key entry for clock set and timer set
50 Hz or 60 Hz clock synchronization
The system is configured with a keyboard for user inputs, a 4 -digit LED clock display, and LED's to indicate AM/PM,
day of week, switches, and ON/OFF/SLEEP status. The device operates from a 9 -volt power supply, and is packaged
in a 28 -pin plastic package. A system incorporating the TMS 1121 is capable of performing both as a digital clock and
as a timer/controller.
CLOCK OPERATION
The TMS 1121 operates as a real-time clock which displays the time of day, AM or PM, and the day of the week. The
accuracy of the clock is defined by the variation of the 50/60 Hz signal supplied to the device. Time of day and day of
the week are entered through the keyboard and displayed on a 4 -digit LED display.
TIMER/CONTROLLER
The TMS 1121 is capable of retaining up to 18 timer sets (programs) which are entered through the keyboard. Each of
these timer sets can control one of four independent output switches which, in turn, can be used to control external
devices.
Timer sets can be segregated into two types: (1) Fixed time programs which toggle an output switch at a specific time,
and (2) Interval programs which toggle an output switch after a specified interval of time has elapsed. Each timer
set will toggle only one switch. The SLEEP function SLP) is used to turn a switch ON for one hour and then OFF,
thereby using one timer set to perform two functions and thus saving one timer set. Interval programs are automatically
deleted from memory upon execution. Fixed -time programs will be retained in memory and repeatedly executed.
The TMS 1121 has been designed so that the user can easily interface with the system via the keyboard (Figure 2). For
example, using the keyboard the user can turn any output switch ON or OFF without programming the action into
memory, thus providing direct control of the switches. Additionally, the user can change the timer settings by either
selectively deleting all the timer sets which refer to one day or one switch, or by deleting all timer sets in order to start
programming into a cleared memory. Finally, any program in memory can be called to the display with the proper key-
board sequence in order to verify that the TMS 1121 had been programmed correctly.
2. OPERATION
2.1 POWER -UP
When the TMS 1121 is powered up, the internal clock is automatically initialized to 12:00 PM on Sunday with all
switches OFF and no programs stored. If the AC signal is 60 Hz, the clock setting is displayed immediately, if the
AC signal is 50 Hz, the CLK key must be pressed to start and display the clock. After power -up the clock setting may
be changed to a new value at any time.
Data supplied by Texas Instruments Limited. C Texas Instruments.

r- SVV1 SUN PM
I
SW2 MON AM
SW3 TUE
CI 11 00 171
SW4 WED 11 CI LI
THU ON
FRI OFF
SAT SLP
DRIVER
DRIVER
-0*-00-111111-
R5 R4 Ro
0
DA SUN MON TUE WED THU FRI
0 1 6
I I
SAT EE SW
AM PM
7 DISP DISP 0
TMS 1121
MEM
ON OFF SLP CLR CLK K4
CLR
AC 50/60 Hz
INIT OSC OSC R R9 R10 VSS VDD
For 60 Hz, the jumper (J) between R6 OV -9V

and K4 must be connected. For 50 Hz, DRIVER
the jumper must not be connected.
OV
SW1 SW2 SW3 SW4
9V
FIGURE 1. UNIVERSAL TIMER BLOCK DIAGRAM

EDAY SUN MON TUE WED THU FRI

0 2 3 4 5 6
SAT WEEK SW
8 9 AM PM
7 DISP DISP
MEM
ON OFF SLP CLR CLK
CLR
Double functions key inputs Single function key inputs
EDAY/0 Everyday or Numeric 0 8 Numeric 8

SUN/1 Sunday or Numeric 1 9 Numeric 9
MON/2 Monday or Numeric 2 AM AM setting
TUE/3 Tuesday or Numeric 3 PM PM setting
WED/4 - Wednesday or Numeric 4 ON ON setting
THU/5 Thursday or Numeric 5 OFF OFF setting
FRI/6 Friday or Numeric 6 SLP SLEEP setting
SAT/7 Saturday or Numeric 7 CLR Clear entry and error
SW/DISP Switch or Display of memory for switch MEM CLR Clear Memory
WEEK/DISP - Week or Display of memory for day of week and everyday CLK Clock Setting
FIGURE 2. KEYBOARD FOR THE UNIVERSAL TIMER CONTROLLER
2.2 SETTING THE CLOCK
A typical key sequence for setting the clock would be:
MON WEEK PM 5 0 0 CLK
which would start the clock at 5 00 PM on Monday. The pattern for the key sequence is always the same. A day of
of the week is registered with WEEK 1 key. An AM or PM key is pressed and the desired time is entered,
then the CLK key is pressed. Because the clock is not actually started from the new value until the CLK .1 key
is pressed, the timer clock may easily be synchronized with another clock. The value of the clock will only be changed
if the key sequence has been correct, otherwise, the CLK key returns the display to the previous value of the
clock, updated to the time the CLK 1 key is pressed.
Errors in the key sequence may also be corrected before the CLK key is pressed. Correction Procedures are explain.
ed in the ERRORS section (2.5).
2.3 PROGRAMMING THE TIMER
2.3.1 FIXED -TIME PROGRAMS
Fixed -time programs change the state of a switch when the clock reaches a preset time. A typical key sequence for
entering a fixed -time program would be:
1 SW MON WEEK PM 5 1 0 ON , which would turn on
switch number one on Monday at 5:10 PM. Keys 1 2 3 or 4 select the switch affected when
followed by the t SW key. The day and time are entered next, in the same order as the clock setting entry (section
2.2). The last key assigns a function to the program: ON ,1 OFF 1, or SLP 1 ON Or OFF
turns the affected switch on or off at the programmed time. I SLP I causes the switch to be turned on at the time
setting that has been entered, then turned off one hour later.
As the key sequence is entered, the digital readout and LED indicators display the program settings. The day of the
week, time of day, switch number, and function of the program may remain on display without halting the operation
of the timer; the clock runs and the switches are turned on or off regardless of the display status. Clock information
may be redisplayed by pressing the CLK key.

If the next program is completely different from its predecessor, the above key sequence must be repeated in its entirety
with the new parameters. If the switch affected and the day of the week are the same, a shortened key sequence suf-
fices to store the program. An example of the shortened key sequence would be:
PM 5 1 5 OFF
If this sequence followed the above long sequence, output number one would be turned off at 5:15 PM on Monday.
The shortened key sequence must follow the lung one directly, without pressing the CLK I key between programs.
A succession of short sequences may follow each other, to program several actions of cne switch on one day.
The EDAY key may be used in fixed -time programming in place of a day -of -the -week key. Programming an action
with EDAY causes that action to occur at the programmed time on every day of the week.
2.3.2 INTERVAL PROGRAMS

In an interval program, the switch number, time interval (in hours and minutes) and function are entered. The function
is performed after the time interval has passed. A typical interval program key sequence would be:
3 SW 2 0 0 ON
In this case, switch number three would be turned on two hours after the ON key was pressed. Either the
[ ON OFF , or SLP functions may be used with an interval program. If SLP is used, the switch is
turned on after the programmed interval, then turned off one hour later. As with fixed -time programs, a shortened key
sequence may be used for a succession of programs following one with the ordinary sequence, as long as the switch is
the same. An example of the short sequence for interval programs would be:
2 0 1 OFF
Following the above entry, this sequence would turn switch three off two hours and one minute after the OFF key
was pressed. The maximum time length for any interval is 11 hours, 59 minutes.
2.3.3 OVERLAPPING PROGRAMS

Programs may be overlapped in time. When several functions are programmed to occur at the same time on the same
day, all of them are ignored except the last one. For example, if the memory contained the following programs
1 SW MON WEEK AM 0 ON
SW MON WEEK AM 0 OFF
1 SW MON WEEK AM 0 ON
the result would be to turn on switch one on Monday at 1:00 AM. Another example. the set of programs.
4 [sw EDAY WEEK PM

CI CD 5 ON
4 SW SAT WEEK PM
El C:J 5 OFF
turns switch four on at 6:45 PM every day of the week except Saturday. Finally, the set of programs
SW FRI WEEK AM lD 0 SLP
2 SW FRI WEEK [ AM 3 0 OFF
would turn switch two off at 7:30 AM on Friday instead of 8:00 AM.
2.4 DIRECT SWITCH CONTROL
A switch may be operated directly from the keyboard. A sample Key sequence would be.
SW SLP
In this case, the SLP function would ne immediately executed on switch number two This switch would be
turned on as soon as the SLP key is pushed and turned off one hour later. Any of the three functions may be
specified for any of the four switches in this manner. The direct manipulations .ire not stored in RAM as programs.

2.5 ERRORS
The usual error indication is 99:99 on the display. This occurs if the key sequence is incorrect or if a program is
attempted with an invalid time. The timer will convert times from the 24 -hour system to 12 -hour times for both clock
setting and programming. The 12 hour time is found by subtracting 12 hours from a 24 hour time. If a 24 -hour time,
e.g. 22:10, is entered, it will be accepted as its 12 hour analog, 10:10, but the AM/PM selection is not affected by
this conversion. Time values incorrect in both the 12 -hour and 24 -hour systems result in the 99:99 error indication.
The time conversion also holds true in interval programs and for this reason the interval length is limited to 11 hours,
59 minutes. Intervals up to 23 hours, 59 minutes will be accepted but corrected to 12 -hour time -lengths. Again, interval
programs incorrect in both systems will produce 99:99 on the display. The indication of 88:88 on the display occurs if
an attempt is made to store more than 18 programs.
During program input, errors may be corrected by several methods. Depressing the CLK key will display the cur-
rent clock setting and erase program or change of clock attempts that have not yet been stored, i.e. before keys
ON ,
OFF SLP or MEM CLR are pressed. The CLR key clears the display, and may there-
fore be used to clear errors before a program is stored. When more than four digits are entered from the keyboard, the
leftmost digit is rolled off the display. Only the digits shown on the display when a key sequence is completed will be
stored.
2.6 PROGRAM DISPLAY
The programs stored in memory can be displayed by depressing the DISP keys twice. For example, the key
sequence:
1 SW/DISP SW/DISP
disp ays the programs for switch number one. One program is displayed for every two times SW/DISP is pressed.
The programs for a day of the week are displayed in the same way but using the WE E KID ISP 1 key. A key sequence
for Wednesday would be:
WED WEEK/DISP WEE K/DISP
Programs entered with the EDAY are displayed using that key and the WEEK/DISP key. For example,
EDAY WEEK/DISP WEEK/DISP
This key sequence only displays programs originally entered with EDAY . Programs entered on a specific day of
the week must be displayed with the key corresponding to that day.
When a program is displayed, the digital readout shows the programmed time of the switch state change and the LED
indicators show the day of the week, the number of the switch affected, and the function programmed. Both fixed -time
and interval programs (before execution) can be displayed. When an interval program is shown, the display shows the
programmed time of its execution, i.e. the time of day and day of the week corresponding to the end of the interval.
When programs using the SLP function are displayed, the display changes with the progress of the program execu-
tion. For example, the following key sequence would be used to turn switch three on for one hour on Friday at
10:00 AM.
3 SW FRI WEEK AM 1 0 0 0 SLP
Before this program is executed, displaying it would show it as a SLP 1 program. The LED's would indicate
switch three, Friday, 10:00 AM, and SLP Between 10:00 and 11:00 AM on Friday, however, when the
.
switch is on, displaying the program shows the time when the switch is to be turned off. In this case the LED's would
show switch three, Friday, 11:00 AM, and OFF. After this time, the program display returns to the SLP settings.
Each time the switch state of a SLP program changes, the program display is updated to show the next change in
the switch state.

2.7 PROGRAM DELETE
The memory may be cleared entirely or selectively using the MEM CLR key. When pressed twice, this key clears
everything stored in the RAM. The programs for an individual switch or day of the week may also be cleared without
disturbing other stored programs.
1 SW MEM CLR
is an example of a key sequence for deleting all the programs for switch number one.
THU WEEK MEM CLR
would delete the programs for Thursday. Programs stored specifically with the EDAY key are cleared using that
key in place of a day of the week.
3. APPLICATIONS EXAMPLES
The TMS 1121 Universal Timer Controller can be used in systems designed for industrial, consumer and other applica-
tions. The four switches of the TMS 1121 can be used to control (turn ON and OFF) lights, sound signals, home
appliances, etc.
The examples given below are intended only as illustrations to show how systems with TMS 1121 can be used and pro-
grammed. Design and implementation details are not discussed here and are left to the user's discretion.
3.1 TRAFFIC SIGNAL LIGHTS AT A SCHOOL ZONE (example)
Suppose it is desired that the timer control the signal lights at a street intersection near a school. For two hours in the
morning and two hours in the afternoon, five days a week, the regular traffic signal at the intersection is to be turned
off, to allow traffic to be manually directed, and special warning lights are to be turned on.
A block diagram of the system would be:
SW1 SPECIAL WARNING LIGHTS

TMS 1121
NORMAL TRAFFIC SIGNALS
SW2
O
O
A set of programs for the TMS 1121 would begin by turning the traffic signal on initially with the sequence:
2 I svi I ON
The operation of the normal traffic signal would be governed by the set of programs:
2 SW EDAY WEEK AM 7 0 0 OFF
AM 9 1 0 0 ON
PM 2 0 0 OFF
PM 4 0 0 ON
2 SW SAT WEEK AM 7 0 0 ON
PM 2 0 0 ON I
2 SW SUN WEEK AM 7 0 0 ON
PM 2 0 0 ON

This program set would turn the traffic signal off between 7:00 AM and 9:00 AM and between 2.00 PM and
4:00 PM, Monday through Friday. The signal would operate normally on Saturday and Sunday. In order to minimize
memory usage, overlapping programs are used to keep the signal from being turned off over the weekend.
The operation of the special warning lights would be governed by the set of programs:
1 SW EDAY WEEK 7 0 0 ON
AM 9 0 L1 I OFF
PM 2 j
0 0 ON
PM 0 OFF
1 SW SAT WEEK AM 7 OFF
PM 0 OFF
SW SUN WEEK AM 7 OFF
I PM 2 0 0 OFF
This set operates in the same manner as the previous one. In all, 16 programs are used.
3.2 HOME SECURITY (example)
The timer can be used to control the lighting in a home as a deterrent to potential burglars. The timer can be used to
turn on lights and other electrical devices and make the house seem occupied when the residents are away. One problem
with the implementation of this idea is that patterns in the lighting control are recognizable; the TMS 1121 has an ad-
vantage in this respect because of the number of programs that can be stored, and the long weekly cycle.
A block diagram of a system to control lights and other devices in a house would be:
TV OR STEREO
SW1
LIGHT 3
SW2
TMS 1121 LIGHT 2
SW3
LIGHT 1
00
SW4
Programs operating the lights and television may be spread through a week in any order. An example for one evening
might be:
1 SW TUE I WEEK PM 7 0 0 SLP
SW TUE WEEK PM 6 1 7 ON
PM 1 0 0 6 OFF.
3 SW TUE WEEK PM 6 3 3 ON
PM 7 2 5 OFF
4 SW TUE WEEK PM 8 1 1 ON
PM 1 1 1 6 OFF

3.3 KITCHEN APPLIANCES (example)
A timer has numerous applications in the kitchen. In the control of an oven especially, timing is important. One example
of connection to kitchen appliances is shown by the block diagram.:
SW1 OVEN
TMS 1121 SW2 BURNER
SW3 ALARM
In this example the sequence:
SW ON
1 SW 5 OFF
would turn the oven on when the ON key was pressed and off 25 minutes later.
The sequence
sw rn 5 ON
6 OFF
entered at the same time as the oven program would sound the alarm for a minute atter the oven has been turned off.
The alarm could be stopped from the keyboard, before the minute was up, by the sequence
SW OFF
Turning the oven on for 25 minutes could also be accomplished with fixed -time programs. They would turn the oven
on between specific times of the day. The set of programs:
I. SW TUE WEEK PM
PM
6
6
0
2
0
5
ON
[ OFF I
3 SW TUE WEEK PM 6 2 5 1
ON
PM 6 2 I.
6 I_ OFF _I
is an example for turning on the oven on Tuesday night between 6:00 and 6:25 PM.
A timed burner could be used in several ways. After turning it on the sequence
1E11 SW ON
the cook could wait until it came up to a desired temperature before starting the timer. After this period, the program
SW 3 0 OFF
could be used to insure that the burner only remained on for thirty minutes, and an alarm could be sounded at the end
of this period with
SW Li] 0 ON
0 OFF

4. TMS 1121 ELECTRICAL SPECIFICATIONS
4.1 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE -AIR TEMPERATURE RANGE
(Unless Otherwise Noted)*
VOItdcle appi led to any device terminal (see Note 1) 15V

Supply voltage, VDD 15 V to 0.3 V
Data input voltage --15 V to 0.3 V
Clock input voltage -15 V to 0.3 V
Average output current (see Note 2)
0 outputs -24 mA
R outputs -14 mA
Peak output current: 0 outputs -48 mA
R outputs. - 28 mA
Continuous power dissipation: TMS 1121NLL 400 mW
Operating free -air temperature range 0°C to 70°C
Storage temperature range -55°C to 150°C
'Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in
the "Recommended Operating Conditions- section of this specification is not implied. Exposure to absolute maximum
rated conditions for extended periods may affect device reliability.
4.2 RECOMMENDED OPERATING CONDITIONS
PARAMETER MIN NOM MAX UNIT

Supply voltage, VDD (see Note 3) -8 -9 -10 V
High-level input voltage, V 1 H K -1.0 -0.8 0.3 V
(see Note 41 INIT or Clock -1.0 -0.8 0.3
K VDD -4
Low-level input voltage, VII_ V
INIT or Clock VDD -9 -6
Clock cycle time, tc (')/ 2.8 3 10 Ps
Instruction cycle time, tc 17 60 Ps
Pulse width, clock high, tw (OH) 1.2 ps
Pulse width, clock low, tw IOU 1.2 ps
Sum or rise time and pulse width,
1.4 ps
clock high, tr + tw IOW
Sum of fall time and pulse width,
1.4 ps
clock low, ti + tw (01_1
Oscillator frequency, tosc 250 350 kHz
Operating free -air temperature, to 0 70 °C
NOTES 1.Unless otherwise noted all voltages are with respect to VSS.
2. These average values apply for any 100 ms period.
3. Ripple must not exceed 0.2 volts peak to peak in the Operating frequency range.
4. The algebraic convention where the most -positive (least -negative) limit is designated as maximum is used in this specification for
voltage levels only.
VSS
VlH (o)
VDD--4H--- I,
et -101- ti t
I I
I
k---tw (a)L1,,4 tw km -0,4

tc (0)
FIGURE 3. EXTERNALLY DRIVEN CLOCK INPUT WAVEFORM

4.3 ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE -AIR TEMPERATURE RANGE
(Unless Otherwise Noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

II Input current, K inputs Vi = 0 V 40 200 350 µA
High-level output voltage 0 outputs 10 = -6 mA -0.6
-1.1
VON V
(see Note 1) R outputs ID = -1.2 mA -0.75 -0.4
IOL Low-level output current VOL = VDD -100 µA
IDD Average supply current from VDD All outputs opel -5 -10 mA
P(AV) Average power dissipation All outputs open 45 100 mW
foss Internal oscillator frequency Rext = 50K,f2, Cext = 47 pF 250 300 350 kHz
Ci Small -signal input capacitance, K inputs Vi = 0, f = 1 kHz 10 pF
Ci(o) Input capacitance, clock input Vi = 0, f = 100 kHz 25 pF
'All typical values are at VDD = -9 V. TA = 25°C.

NOTE: 1. The algebraic convention where the most -positive (least -negative) limit is designated as maximum is used in this specification for
logic voltage levels only
4.4 SCHEMATICS OF INPUTS AND OUTPUTS 4.6 TERMINAL ASSIGNMENTS
TMS 1121
TYPICAL OF ALL 0 AND R
TYPICAL OF ALL K INPUTS OPEN -DRAIN OUTPUTS
VSS
R8 Ci1 281] Al
R9 E2 27:] R6
R10 c[143 261] R5
VDD 25.] R4
241J R3
I
K1 a.-15
K2 [16 23,j R2
H OOUTPUT K4 22]Rl
K8 C8 21 ] RO
INIT C 9 20,] VSS
07 10 19] OSC2
The 0 outputs have nominally 60 SZ on -state impedance. 06 C 11 18 ,] OSC1
05 E 12 17]00
4.5 INTERNAL CLOCK 04 C 13 16 ] 01
03 [114 15:] 0?
TYPICAL INTERNAL OSCILLATOR FREQUENCY
VS
EXTERNAL RESISTANCE
400
I
VDD- -15 V
TA ., X5°C
300 ialk
%IF
X
RECOMMENDED
OPERATING
POINT
F
2 -C,....100 pF 47 pF 27 pF 10 pF Op
CONNECTION FOR INTERNAL OSCILLATOR

cet
OSC 10
I I( 0 VSS
100 OSC2 0 W 0 voo

0 20 40 60 80 100 120 140 160 180 200 Re.,
A.55 - External Flresistanc - kil
To use the internal oscillator, the OSC1 and OSC2 Lerminals are shorted together and tied to an external resistor to
VDD and a capacitor to VSS.

P2
12V r 100 100 /
LL 9V 11WI I1W1
9V to
12011
11W1
4 7,F 01.F
I 120V1 PI
470 141 0272222
r - 'I -arC1.7.071
SIG GNO 10 OV
00
17 I I
1
.
KI
1.,,_
GND 41 A SEG
1
i I 1
16 I I
01
i I L,
50/60 Hz EISEG
I
L___
I 1
15 I I I
02
1 I i C SEG
I
14
03 1,,,A1! :(1
L_J L -_J .1 D SEG
E SEG
05
P1 F SEG
r - - --;
KBM 1 14,
06
G SEG
10
07
KBM 2
.1 o P
L_J L_ -J
470 14) 0272222
KBM 3 106 IC I F91/1
L II S975492 L
1006 Ro
21
r 5vs7 MI
MODE DG
r
Kg
19914 22
-I 111
23
-wl 1st DG
R2 2nd DG
EI L 0212222
24
I 1609s R3 4 3,4 DG
E2 L.; SS
R4
25 C> 4th DC
05_F 47 pF
WEEK DG
1911
1006 18
L GY../
19914 0 01.F OSCI
M SW DG
I I
0272222
L -.J
0212222 19914
9
OSC2 686 P2
476
686
OV
sw,
VDD 28
R7
19914 SW2
KBM I
KBM 6
KBM c
L
L I
iI
I
L_J
I CI
1.1 5W3
KBM d r 4 I
KBM .r SW/1
I KEW I I. 1 1 1K
is,
I KBM p L
1/..
6 86 141
.1
r- , L_J
1
0272222
I
NOTE: All resistors values are ±5%, Y.1N

L "1:
6 811 14/
I_
s
Unless otherwise specified
E1, E2 connection for 60Hz operation FIGURE 4. UNIVERSAL TIMER CONTROLLER SYSTEM DIAGRAM
120 V IN4002 4
AC 12
100V/120V 100V
2800 1pF
OV
$,F
(25V)
-(50y)
GND
p A7808
330 5
1 pF
(50V)
200 51
(SIG GND)
FIGURE 5. TYPICAL POWER SUPPLY FOR THE UNIVERSAL TIMER CONTROLLER
CONTROLLED A.C. OUTLETS
0
TO A.G. LINE
+ 12
IN645
SW 1
K2 i ; IN645
-J SW 2
1N645
SW 3
K4 IN645
L_-J SVV 4 )
NOTE. R AND C ARE CONTACT ARCING SUPPRESSOR

R 10 20 51
IT VP)
CO. 1 #.2F
FIGURE 6. TYPICAL A.C. OUTLET SWITCHING CIRCUIT FOR THE UNIVERSAL TIMER CONTROLLER
6. TMS 1122
These are the functional differences between the TMS 1121 and TMS 1122 TIMER circuits.
POWER UP display by flashing LED, connected across 06 and R5 outputs.

SET CLOCK by depressing "CLK" (across the matrix points K2/R4). AM/PM keys and LED's do not exist.
MAXIMUM interval timer set remains at 11 hours 56 minutes.
ERROR DISPLAY of 9999 when entry exceeds "24" hours.

LED TIL220(7) LED TIL223(4)
SUN MON TUE WED THU FRI SAT SW1 SVV2 SW3 SW4
P1 Il Atv a's Al' alv

COLON
A SEG .10
B SEG is
C SEG 14
D SEG is
E SEG 1.
F SEG F
G SEG
D.P. r
LED
40-TIL209A
(2)
LED 7 6 4 2 1 9 10 7 6 4 2 1 9 10 7 6 42 1 9 10 76
TIL209A PM AM ON OFF SLP
(2)
/ T// Tilr/It/
/ / / 1
I_.
MODE DG COLON
V LED IL220(3)
lstDG
2ndDG
3rdDG I.
4thDG F. NUMERIC DISPLAY TIL322(4)
WEEK DG
SW DG
EDAY SUN MON TUE WED THU FRI

0 1
5_,
KBM 1 I. 4r wr
KBM 2
SAT
7
-- AL/1}) P111.,
WEEK
DIS
fo
SW
14
OFF
_A CIA
KBM 3
KBM a lo
KBM
I KBM c I4
KBM d
KBM e L
KBM f
KBM g
-J
FIGURE 7. TMS 1121 DISPLAY AND KEYBOARD DIAGRAM

FERRANTI
semiconductors ZN414Z
ZN415E, ZN416E AM Radio Receivers

FEATURES ZN415E
ZN416E
Single cell operation (1.1 to 1.6 volt operating range)
Low current consumption
150kHz to 3MHz frequency range
(i.e. full coverage of medium and long wavebands)
Easy to assemble, no alignment necessary
Simple and effective AGC action
Will drive crystal earphone direct (ZN414Z)
Will drive headphones direct (ZN415E and ZN416E)
Excellent audio quality
Typical power gain of 72dB (ZN414Z)
Minimum of external components required
GENERAL DESCRIPTION
The ZN414Z is a 10 transistor tuned radio frequency (TRF) circuit

packaged in a 3 -pin TO -92 plastic package for simplicity and space
economy.
The circuit provides a complete R.F. amplifier, detector and AGC circuit which requires only six
external components to give a high quality A.M. tuner. Effective AGC action is available and is
simply adjusted by selecting one external resistor value. Excellent audio quality can be achieved,
and current consumption is extremely low. No setting -up or alignment is required and the circuit
is completely stable in use.
The ZN415E retains all the features of the ZN414Z but also incorporates a buffer stage giving
sufficient output to drive headphones directly from the 8 pin DIL.
Similarly the ZN416E is a buffered output version of the ZN414Z giving typically 120mV(r.m.s.)
output into a 6452 load. The same package and pinning is used for the ZN416E as the ZN415E.
1 3V (appros)
RAGCF503n (appro4
1001in
Output to
0
audio amplifier
vci
RF RF
Input amp amp mp
C2
Very high input
impedance stage
L Earth
0
transistor detector
The ZN414Z is within the dotted area
3624
ZN414Z System Diagram
=100kn 1kn clip+
-16
_z I I *Oka 11in
77200 VCC
ZN414
OUTPUT TO 18dB
HEADPHONES 5
BUFFER OUTPUT TO
(2 x32n) STAG HEADPHONES
I 2 x 32tx
T0 01,uF
L 3 71 2 3 4 7
7)JF
01))F11--..-1 01pF 17301,uF

OV
0 DV
THE ZN415E IS WITHIN THE DOT TED AREA 6 900 THE ZN416E IS W THIN THE DOTTED AREA 6699
ZN415E System Diagram ZN418E System Diagram
©FERRANTI plc 1986

The copyright in this work is vested in Ferranti plc and this document is issued for the purpose only for which it is supplied. No
licence is implied for the use of any patented feature. It must not be reproduced in whole or in part, or used for tendering or
manufacturing purposes except under an agreement or with the consent in writing of Ferranti plc and then only on the condition
that this notice is included in any such reproduction. Information furnished is believed to be accurate but no liability in respect
of any use of it is accepted by Ferranti plc.

1! FE RRA_NTI
Li" semiconductors ZN414Z
DEVICE SPECIFICATIONS Tamb = 25°C, \ice = 1.4V. Parameters apply to all types unless
otherwise stated.
Parameter Min. Typ Max. Units
Supply voltage, Vcc 1.1 1.4 1.6 volts

Supply current, Is ZN414Z 0.3 0.5
with 64 1 ZN415E - 2.3 3 mA
headphones ,ZN416E 4 5
Input frequency range 0.15 - 3.0 MHz
Input resistance 4.0 - Mil

Threshold sensitivity (Dependant on Q of coil) 50 µV
Selectivity 4.0 kHz
Total harmonic distortion - 3.0 %
AGC range - 20 dB
Power gain (ZN414Z) 72 dB
Voltage gain of output stage ZN415E 6 . dB

ZN416E 18
Output voltage into 4700 ZN414Z 60

Output voltage into 641 load N415E 120 mVpp
before clipping ZN416E 340
Upper cut-off frequency of output stage,A
20 kHz
No capacitor, (ZN41 5E and ZN416E1 j
With 0.01µF between pin 7 and OV (ZN415E) 6 - kHz
With 0.01AF between pin 7 and OV (ZN416E) 10 kHz
Lower cut-off frequency of output stage

0.1µF between pins 2 and 3 for ZN415E '
50 Hz
0.47µF between pins 2 and 3 for ZN416E
Quiescent output voltage ZN415E BO mV
ZN416E 200
(See page 5 for ZN414Z)
Operating temperature range 0 70 °C
Maximum storage temperature -65 125 °C
ZN414Z CHARACTERISTICS - All measurements performed with 30% modulation, FM =400Hz
Gain and AGC characteristics

60
111111i li 3675/1
-
1 I I I I
70 look RL Vcc
0 01,u
60 vOUT
'7513 ZN414Z
i
50
RL =1500n
40
RL . 670n
30
Vcc = IA Volts
tc . 455k Hz
20 f modulated - 400112
Moduloton = 30% RL .10013
10
0
10,u 00p lm 10m 100m
VIN (rms) Volts
See operating notes for explanation of AGC action.

FERRANTI
semiconductorsi® ZN414Z
ZN414Z CHARACTERISTICS - (Continued)
Frequency response of the ZN414Z

30 13711
Vcc z 16V
m=301.
100 Attenuation
on Input
20
lOmV
10
6mV
lmV 3mV
0
0 1004 1M 10M
fc -(Hz)
Note that this graph represents the chip response, and

not the receiver bandwidth.
Gain variation with supply volts.
l H III
Input Frequency r 1MHz
3835
In
O Modulation Frequency r 400 Hz
E 30 Modulation Depth =30%
An= 05mV rms.
RL= lkn
1. CL= 0-1pF
2
I 20
10
a
0
09 1.0 11 12 13 14 15 16
Supply Voltage - Volts
D.C. level at output
14
306
13
12
11
RL = 470n
10a
09
R1..1 5411
06
1004
07 001,u
IVcc .1 4 W118
fc =455kHz
'modulated 40011z
1 Modulation 30%
1 I 1 1 1 1 11 1 1 1 1 1 11 I 1 1 111111
10m 133p lm 10m
Input Voltage -Volts rats

.71
semiconductors ZN414Z
LAYOUT REQUIREMENTS
As with any high gain R.F. device, certain basic layout rules must be adhered to if stable and reliable
operation is to be obtained. These are listed below:
1. The output decoupling capacitor should be soldered as near as possible to the output and earth
leads of the ZN414Z. Furthermore, its value together with the AGC resistor (RAGc) should be
calculated at = 4kHz, i.e.:
C (farads) = 1
27, RAGC 4 103

2. All leads should be kept as short as possible, especially those in close proximity to the ZN414Z.
3. The tuning assembly should be some distance from the battery, loudspeaker and their associated
leads
4. The 'earthy' side of the tuning capacitor should be connected to the junction of the 100k0
resistor and the 0.01µF capacitor.
OPERATING NOTES
la) Selectivity
To obtain good selectivity, essential with any T.R.F. device, the ZN414Z must be fed from an
efficient, high 'Q' coil and capacitor tuning network. With suitable components the selectivity is
comparable to superhet designs, except that a very strong signal in proximity to the receiver may
swamp the device unless the ferrite rod aerial is rotated to "null -out" the strong signal.
Two other factors affect the apparent selectivity of the device. Firstly, the gain of the ZN414Z
is voltage sensitive (shown on page 5) so that, in strong signal areas, less supply voltage will be
needed tc obtain correct AGC action. Incorrect adjustment of the AGC causes a strong station
to occupy a much wider bandwidth than necessary and in extreme cases can cause the RF stages
to saturate before the AGC can limit RF gain. This gives the effect of swamping together with
reduced AF output. All the above factors have to be considered if optimum performance is to be
obtained.
lb) Ferrite aerial size

Because of the gain variation available by altering supply voltage, the size of the ferrite rod is relatively
unimportant. However, the ratio of aerial rod length to diameter should ideally be large to give
the receiver better directional properties. Successful receivers have been constructed with ferrite
rod aerials of 4cm (1 .5" ) and up to 20cm (8" I.
lc) Trimmer
A suitable variable capacitor with a range of 10-1 2OpF is available from Murata as the TZO3R1214.
1. Resistive Divider 2. Diode Drive 3. Transistor Drive
93 93
4 7krk 220kn
3 9kn
ZTX 300
I
DI
56kn
I
F 02
01pf
RAGC RAGC
680n lap 250n 1RAGc
I P1,-&
To ZN414Z output
To ZN414Z output To ZN414Z output
38211 3825 31126
Current consumption = 2mA Current consumption... 1.5mA

Note: Replacing the 6800 resistor with a D1 = D2 = Any general purpose silicon diode Current consumption is virtually that which
5000 resistor and a 2500 preset, sensitivity Rp = Optional sensitivity control, a is taken by the ZN414Z (0.3mA)
may be adjusted and will enable optimum recommended value being 2500.
reception to be realised under
most conditions.
DRIVE CIRCUITS
Three types of drive circuit are shown, each has been used successfully. The choice is largely
an economic one, but circuit 3 is recommended wherever possible, having several advantages
over the other circuits. Values for 9V supplies are shown, simple calculations will give values for
other supplies.

ZN414Z
RECOMMENDED CIRCUITS
la) Earphone radio
The ZN414Z will drive a sensitive earpiece directly. In this case, an earpiece of equivalent impedance
to RAGc is substituted for RAGc in the basic tuner circuit. Unfortunately, the cost of a sensitive
earpiece is high, and unless an ultra -miniature radio is wanted, it is considerably cheaper to use
a low cost crystal earpiece and add a single gain stage. One further advantage of this technique
is that provision for a volume control can be made. A suitable circuit is shown below.
Ynpedarloe
Crystal
10Cbo Earpiece
15v_
ZN414Z
= 0 OlpF Ci .150pF
3.29
L1 .80 turns of 0.3mm dia. enamelled copper wire on a 5cm or 7.5cm long ferrite rod. Do not
expect to adhere rigidly to the coil -capacitor details given. Any value of L1 and C1 which will give
a high 'Q' at the desired frequency may be used.
Volume Control: a 2500 potentiometer in series with a 1000 fixed resistor substituted for the 2700
emitter resistor provides an effective volume control.
(b) Domestic portable receiver

The circuit shown is capable of excellent quality, and its cost relative to conventional designs is
much lower.
33tra
Note The earthy

3. I. I
sad, of (moons, Tmk' V1PF
sect,on)n,ust be
connected to C1)1116
EIFS60
I
R16 lOko
iLt LSI
-C1=001
tOn
Lt oppros 551 an a 15cm fernte rod

313211
The complete circuit diagram of the Triffid receiver
(bli
Ferrite rod
55 turns 250 turns
/tone layer
edium wave coil wave coil
To 2144142
28 swg Wire input
FERRITE ROD 6" , dia. *To give a better frequency response
Coil winding details and waveband selection

iii FERRANTI]
semiconductors 10 ZN414Z
(cl Use in model control receiver

The circuit below shows a ZN414Z used as an I.F. amplifier for a 27MHz superhet receiver.
5V
Ceramic Resonator-
Mallard LP 1175/2 or Murata 10kn
27423 zsloo equovalent SFD 455B 10krt 10krt
/- 1 100Itn
51rns 25tr rts ITX I
O'0 i
--
312 I
L
33pFI0
O033pF
1
I 0 1,oF
Tk nr OV
1.
27 turns on a
= 68pF 7kn titr arnrrt)
former
0
X rs a 26 74 1.1117 crystal 2
Tel1}AF
12kn 3030
Performance Details:
Sensitivity = 2.5µV for a 5V p.t.p. output measured at fc = 27.21MHz,
100% modulated with 100Hz square wave.
Selectivity: + 5kHz for < 100mV p.t.p. output.
Input Signal Range: 2.5µV to 25mV (i.e. 80dB)
Supply Current: 2.4.5mA.
Id) Broadcast band superhet using ZN414Z

The ZN414Z coupled with the modern ceramic resonators offers a very good I.F. amplifier at modest
cost, whilst maintaining simplicity and minima alignment requirements. A typical circuit is shown
below:
1kta
0
9V
25
22kn :I 3 3kra 10423
100k n
II
( J--
H
I
A/ B
I I
Z TX
312 :L2 ZN414Z - audio
amp
Ferrite I
rod F1171-
I
aerial 003 900E , ---

F
T.
2-30
t /j, - 1:r-
hEII
4 7kn
PF e iII itgz
S)1
/'
pF
Murata
5F0 4558
C ." 25k n
PF PF
L J 352311
- 6dB Bandwidth = 6kHz

30dB Bandwidth = 8kHz
AGC Range = 40dB
(For 10dB change in A.F. output).
FURTHER APPLICATIONS
The ZN414Z is an extremely versatile device and, in a data sheet, it is not possible to show all
its varied applications. A comprehensive applications note on the device is available which gives
full details of various radio receivers, I.F. amplifiers and frequency standards together with
comprehensive technical information.

National
'Ara Semiconductor LM1830
Fluid Detector Logic and Connection Diagrams

Metal Can Package
General Description Features OSP
DAP
The LM1830. is a monolithic bipolar integrated circuit Low external parts count
designed for use in fluid detection systems. The circuit is Wide supply operating range
ideal for detecting the presence, absence, or level of
One side of probe input can be grounded
water, or other polar liquids. An ac signal is passed
through two probes within the fluid. A detector deter- ac coupling to probe to prevent plating
mines the presence or absence of the fluid by comparing Interna ly regulated supply
the resistance of the fluid between the probes with the ac or dc output GNO
resistance internal to the integrated circuit. An ac signal TOP VIE*
is used to overcome plating problems incurred by using a Order Number LM1830H

dc source. A pin is available for connecting an external Sim NS Package H 10C
resistance in cases where the fluid impedance is of a Applications
different magnitude than that of the internal resistor. Beverage dispensers Radiators Dual -In -line Package
When the probe resistance increases above the preset Water softeners Washing machines OSCIE ,T(114
aalue, the oscillator signal is coupled to the base of the vC
OUTPUT DETECTOR EiL TER
Irrigation Reservoirs AREn OUTPUT 0110 INPUT CAP

open -collector output transistor. In a typical application,
the output could be used to drive a LED, loud speaker Sump pumps Boilers Ti
or a low current relay. Aquaria

DETECTOR
DIAS
ARE,
Absolute Maximum Ratings OUTPUT
OSCILLATOR
Supply Voltage 28V

Power Dissipation (Note 1) 300 mW Is I1
11
Output Sink Current 20 mA 05011 ATOM MC NC RC OSCIEIATOR MC DSCiL ATOM
CAPAC TOR OUTPUT CAPACITOR
Operating Temperature Range -40°C to +85°C TOP VIDA
Storage Temperature Range -40°C to +150°C Order Number LMIEt3ON

Lead Temperature (Soldering, 10 seconds) 300°C See NS Package N14A
Electrical Characteristics (V+ = 16V, TA = 25°C unless otherwise specified)
PARAMETER CONDITIONS MIN TYP MAX UNITS

Supply Current 55 10 mA
Oscillator Output Voltage
Low 1 1 V
High 4.2 V
Internal Reference Resistor 8 13 25 kit

Detector Threshold Voltage 680 mV
Detector Threshold Resistance 5 10 15 kft

Output Saturation Voltage 10 = 10 mA 0.5 2.0 V
Output Leakage VPIN 12 = 16V 10 µA

Oscillator Frequency C1 = 0.001µF 4 7 12 kHz
Note 1: The maximum junction temperature rating of the IM1830N is 150°C. For operation at elevated temperatures, devices in the dualinline
plastic package must be dented based on a thermal resistance of 175°C/W.
Schematic Diagram
OSCILLATOR OPTIONAL
OSCILLATOR OUTPUT DOTE TOR Fl TER
`la OUTPUT (SREF) INPUT CAPACITOR OUTPUT
Probe Threshold Resinanc Oscillator VON and VOL

vs Temperature va Ambient Temperature
13
Vcc ISV
VCC*1"
12
VON
11
to
VOL
-40 -25 5 20 AO MI 80 100 -44 -28 0 20 48 N 10 lot

AMBIENT TEMPERATURE i CI TEMPERATURE 1 CI
CI GOO CI
Data supplied by National Semiconductor. O National Semiconductor.

National
NA Semiconductor LM 1 830
Application Hints Typical Performance

The LM1830 requires only an external capacitor to com- It is possible to calculate the resistance of any aqueous Characteristics
plete the oscillator circuit. The frequency of oscillation solution of an electrolyte for different concentrations,
Reference Resistor vs Ambient
is inversely proportional to the external capacitor value. provided the dimensions of the electrodes and their Temperature
Using 0.001i.iF capacitor, the output frequency is spacing is known.
20
approximately 6 kHz. The output from the oscillator is
available at pin 5. In normal applications, the output is The resistance of a simple parallel plate probe is given 18
taken from pin 13 so that the internal 13k resistor can by:
be used to compare with the probe resistance. Pin13 is 16
coupled to the probe by a blocking capacitor so that 1000 d a 11

R
there is no net dc on the probe.
c.p A
12
Since the output amplitude from the oscillator is where

10
A = area of plates (cm2)
approximately 4 VBE, the detector (which is an emitter
d = separation of plates (cm)
base junction) will be turned "ON" when the probe c = concentration (gm. mol. equivalent/litre) -40 -25 0 20 45 NN 100
resistance to ground is equal to the internal 13 1(2 p = equivalent conductance AMBIENT TEMPERATURE 1 CI
resistor. An internal diode across the detector emitter
In 1 cm2 equiv.-1)
base junction provides symmetrical limiting of the Detector Threshold Voltage
detector input signal so that the probe is excited with (An equivalent is the number of moles of a substance that vs Temperature
±2 VBE from a 13 kf/ source. In cases where the 13 kSZ gives one mole of positive charge and one mole of nega-
resistor is not compatible with the probe resistance VCC 16V-
tive charge. For example, one mole of NaCI gives Na+ +
range, an external resistor may be added by coupling the CI so the equivalent is 1. One mole of CaCl2 gives 01
probe to pin 5 through the external resistor as shown in Ca++ + 2CI- so the equivalent is 1/2.)
Figure 2. The collector of the detecting transistor is
brought out to pin 9 enabling a filter capacitor to be Usually the probe dimensions are not measured
connected so that the output will switch "ON" or physically, but the ratio d/A is determined by measuring 0.4
"OFF" depending on the probe resistance. If this the resistance of a cell of known concentration c and
capacitor is omitted, the output will be switched at equivalent conductance of 1. A graph of common 0.2
approximately 50% duty cycle when the probe resis- solutions and their equivalent conductances is shown
tance exceeds the reference resistance. This can be useful for reference. The data was derived from D.A. Maclnnes,
when an audio output is required and the output -40 -20 0 21 45 60 80 IN
"The Principles of Electrochemistry,- Reinhold
transistor can be used to directly drive a loud speaker. Publishing Corp., New York., 1939.
AMBIENT TEMPERATURE 1 CI
In addition, LED indicators do not require dc excita-

Output Saturation Voltage vs
tion. Therefore, the cost of a capacitor for filtering can In automotive and other applications where the power Output Current
be saved. source is known to contain significant transient voltages,
In the case of inductive loads or incandescent lamp
the internal regulator on the LM1830 allows protection
to be provided by the simple means of using a series
11..
loads, it is recommended that a filter capacitor be
Egrallii;EN111;11:11;111;1
resistor in the power supply line as illustrated in Figure 4.
employed.
If the output load is required to be returned directly
.
to the power supply because of the high current required,
171:113114E1Y.OESIZIiii
In a typical application where the device is employed it will be necessary to provide protection for the output
111.1111111Wieig111.11111111
for sensing low water level in a tank, a simple steel
probe may be inserted in the top of the tank with the
transistor if the voltages are expected to exceed the data
sheet limits.
" =2;;;;%!2;;;;;Zroan;;;;;
IMMeo;,,
tank grounded. Then when the water level drops below
11111111111111111111111111
the tip of the probe, the resistance will rise between the Although the LM1830 is designed primarily for use in a 80151
10 IN
probe and the tank and the alarm will be operated. This sensing conductive fluids, it can be used with any varia-
1
is illustrated in Figure 3. In situations where a non- ble resistance device, such as light dependent resistor or OUTPUT CURRENT PIN 1211mA/
conductive container is used, the probe may be designed thermistor or resistive position transducer.
in a number of ways. In some cases a simple phono plug Oscillator Frequency vs
can be employed. Other probe designs include conduc- The following table lists some common fluids which may Ambient Temperature
tive parallel strips on printed circuit boards. and may not be detected by resistive probe techniques. 20
18 Vec 16v -
16
J
Conductive Fluids Non -Conductive Fluids 12
City water Pure water

Sea water Gasoline
Copper sulphate solution Oil
Weak acid Brake fluid
Weak base Alcohol
Household ammonia Ethylene glycol
Water and glycol mixture Paraffin
-4$ -26 8 26 40 60 N IN
AMBIENT TEMPERATURE( Cl
Wet soil Dry soil
Coffee Whiskey
Equivalent Resistance vs
Concentration of Several
Normalized Oscillator Frequenty Threshold Resistance vs Supply Power Supply Current vs Solutions
vs Supply Voltage Voltage Supp y Voltage
500
115 25 It 458
I
TA 25C TA 25 C TA -40 C 400
20 10
Ise
3011
105 IS
250
200
10 6
I54
TA 25C 100
095
N
05 2 O001 001
5 10 IS 20 25 30 5 10 15 20 25 30 0 5 10 15 20 25 38
CONCENTRATION (GRAM MOLECULAR
SUPPLY VOLTAGE 1V1 SUPPLY VOLTAGE 1V1 SUPPLY VOLTAGE 151 EOUIVALENTS/LITRE)

01 National
KAI Semiconductor LM1830
Application Hints (Continued)
61CC 16W
wtc
LEO
LIO
FIGURE 1. Teat Circuit FIGURE 2. Application Using External Reference Resistor
vcc
Slit
I PHOTO
TRANSISTOR
I MR
FIGURE 3. Basic Low Level Warning Device Output is activated when 6,60 7.; 1 /3 RREF
with LEO Indication FIGURE 4. Direct Coupled Applications
TIC
Typical Applications
OPTIONAL
II RELAY OR
SO1E11010
TRANSIENT
PROTECTION
RESISTOR
5011,F
NS NI
The output is suitable for driving a sump pump

or opening a drain valve, etc
Low Level Warning with Audio Output High Leval Warning Device

AY -3-8912 General
AY -3-8910 Instrument
Programmable Sound PIN CCIWIGURATION

Generator 40 LEAD DUAL IN LINE
AY -3-8910A Top View

FEATURES:
Full software control of sound generation

VSS (G/',10)C 81 V 40 :)Vcc (+5V)
No ConnectC 2 39 pNo Connect
Interfaces to most B -bit and 16 -bit micropro-
Analog Channel BC 3 38 0Analog Channel
cessors
Analog Channel AC 4 37 :)DA0
Three independently programmable analog outputs
No ConnectC 5 36 n DAi
- One or two 8 -bit I/O ports
I OB7C 6 35 DA2
- Single 5 volt supply
I OB6C 7 34 ODA3
- Full 0' to 70'C operation
1085C 8 33 DA4
- 40 pin or 28 pin package ootion
1084q 9 32 DA5
1083C 10 31 DA6
DESCRIPTION
1082C 11 30 ]1:)A7
10B1C 12 29 BC1
The AY-3-8910A/8912A Programable Sound Generator
IOBOC 13 28 BC2
(PSG) is circuit which can produce a wide
an LSI
10A7C 14 27 0 BD I R
variety of complex sounds under software control.
I 0A6C 15 26 No Connect
The AY-3-8910A/8912A is manufactured in the General
I0A5C 16 25 A8
Instrument Microelectronics +-Channel Ion Implant
I 0A4C 17 24
Process. Operation requires a single .5V power
1 0A3C 18 23 grcer
supply, a T IL compatible clock, and a microproces-
10A2C 19 22 Clock
sor controller, such as the General Instrument 16 -
10A 1 C 20 21 3 i0A0
bit CP1610 or one of the PIC1650 series of 8 -bit
microcomputers.
28 LEAD DUAL IN LINE

The PSG is easily interfacec to any bus oriented
system. .Its flexibility makes it useful in
AY -3-8912A Top View
applications such as music synthesis, sound
effects generation, audible alarms, tone signaling,
Analog Channel CE:a1 28 DAO
and home computer usage. In order to generate
No ConnectC2 270 Dm
sound effects while allowilg the processor to
VCC (+5V)C 3 263 DA2
perform other tasks, the 'SG can continue to
Analog Channel BC4 25,7 DA3
produce sound after the initial commands have been
Analog Channel AC5 24,3 DA4
given by the control processor. The fact that
Vss (GND)C 6 233 DA5
realistic sound production often involves more than
I0A7C 7 22.0 DA6
one component is satisfied by the three independ- DA7
1046C,8 21
tly controllable analog sound output channels
10A5C9 zoo 8C1
available in the PSG. These analog sound output
I0A4C 10 193 BC2
channels can each provide 4 bits of logarithmic 18CBDIR
I0A3C 11
digital to analog conversion, greatly enhancing
10A2C 12 170 A8
the dynamic range of the sounds produced.
10AIC 13 16,0 RSET
oAoc 15 Clock
All circuit control signals are digital in nature
and may be provided directly by a microprocessor/
microcomputer. Therefore, ore PSG can produce the
full range ofsounds with no change in
required
external circuitry. Since the frequency response
of the PSG ranges from sub -audible at its lowest
Address 9, Address 8
frequency to post -audible at its highest frequency,
A8 (input): Pin 25 (AY -3-8910A)
there are few sounds which are beyond reproduction.
Pin 17 (AY -3-8912A)
XT" (input): Pin 24 (AY -3-8910A)
PIN FUNCTIONS
High order address bits 0 and A8 ere fixed to

DAT --OA° (Input/Output/High Imsedsnom)
recogni2e a "01" code. They may be Left unconnect-
Data/Address Bits 7-0: Pins 30-37 (AY -3-8910A)
e d, as each is provided with either an onchip
Pins 21-28 (AY -3-8912A)
pull -down (D) or pull-up (A8) resistor. In noisy
e nvironments, however, it is recommended that r;
These 8 lines comprise the 8 -bit bidirectional bus
and A8 be tied to external ground and +5V
used by the microprocessor to send both data and respectively, if they are not to be used.
addresses to the PSG, and to receive data from the
PSG. In the address mode, DA3--0A0 select the
This input is not- available on the AY -3-8912A.
internal register address (0--179) and DA7 --DAS
in conjunction with address inputs A9 and A8, fore
the chip select function. When the high order
address bits are "incorrect", the bidirectional
buffers are forced to a high impedance state.

AY -3-8912 General
L-

AY -3-8912 General
RESET (Input): Pin 23 (AY -3-8910A) Analog Channel A, B, C (Outputs):

Pin 16 (AY -3-8912A) Pins 4,3,38(AY-3-8910A)
Pins 5,4.1 (AY -3-8912A)
For initialization/power-on purposes, applying a
low level input to the Argr pin will reset all Each of these signals is the output of its corres-
registers to 08. The firgr pin is provided with ponding digital to analog converter, and provides
en on -chip pull-up resistor. IV peak -peak (max) signal representing the complex
sound waveshape generated by the PSG.
CLOCK (Input): Pin 22 (AY -3-8910A)
Pin 15 (AY -1-8912A) Pine 2,5,26,39 (AY -5-8910A). Pine 2 (AY -5-41912A)
This III. compatible input supplies the timing These pins are for General Instrument test purposes
reference for the Tone, Noise, end Envelope only and should be left open. Do not use as
Generators.
tie -points.
ODIR, 8C2, 8C1 (Inputs): Pins 27,28,29 (AY -3-8910A:

lict: Pin 40 (AY -3-8910A), Pin 3 (AY -3-8912A)
Pins 18,19,20 (AY -3-8912A)
Nominal +5 Volt power supply to the PSG.
BUS Direction, BUS Control 2, Bus Control 1
Pin 1 (AY -3-8910A), Pin 6 (AY -3-8912A)

These bus control signals are generated directly VSSI
Ground reference for the PSG.
by the CP1610 microprocessor to control all bus
operations internal and external to the PSG.
ARCHITECTURE:
CP1600 PSG
8D1R 0C2 DC1 FUNCTION FUNCTION
The AY-3-8910A/8912A register oriented Pro-
is a
gramable Sound Communication

Generator
(PSG).
0 0 0 NACT INACTIVE. See 010 (IAB) below.
betweer the processor and the PSG is based on the
0 0 1 ADAR LATCH ADDRESS. See 111 (IN'AK)
concept of memory -mapped I/O. Control commands are
below.
issued to the PSG by writing to 16 memory -mapped
0 IAB INACTIVE-. The PSG/CPU bus is
registers. Each of the 16 registers within the P50
inactive. DA7 -CIAO are in a nigh
is also readable so that the microprocessor can
impedance state.
This determine, as necessary, present states or stored
0 1 1 DTB READ FROM PSC. signal
data values. All functions of the PSG are
causes the contents of the
which currently controlled through the 16 registers which, once
register is
addressed to appear on the PSG/ programmed, generate and sustain the sounds, thus
CPU bus. DA7-DA0 are in the freeing the system processor for otner tasks.
output mode.
1 0 0 BAR LATCH ADDRESS. See 111 (INTAK) REGISTER ARRAY:
below.
1 0 1 DM INACTIVE. See 010 (IAB) above. The principal element of the PSG is the array of
1 I 0 CMS WRITE TO PSG. This signal indi- 16 read/write control registers. Tnese 16 regis-
cates that the bus contains ters look to the CPU as a block of memory and, as
register data which should be such, occupy a 16 word block out of 1,024 possible
latched into the currently addresses. The 10 address bits (8 bits on the
addressed register. DA7--DAO common data/address bus, and 2 separate address
are in the input mode. bits) are decoded as follows:
1 1 1 MAK LATCH ADDRESS. This signal
indicates that the bus contains A9 A8 DA7 DA6 DA5 044 DA3 DA2 DA1 DAD
a register address which should 0 1 0 0 o 1 o 0 0 0 0
be latched in the PSG. DA7 - -
THROUGH
DAD are in the input mode.
0 1 0 0 0 0 1 1 1
While interfacing to a processor other then the

HIGH LOW
CP1600 would simply require simulating the above
ORDER ORDER
decoding, the redundancies in the PSG functions vs.
(Chip Select) (Register No.)
bus control signals can be used to advantage in
that only four of the eight possible decoded bus
functions are required by the PSG. This could
simplify the programming of the bus control signals
to the following, which would only require that the
processor generate two bus control signals (801R
and BC1, with BC2 tied to +5V):
PSG PSG
DDIR 8C2 BC1 FUNCTION
0 1 0 INACTIVE.
0 1 READ FROM PSG. FROM
1 0 WRITE TO PSG. PROCESSOR
1 1 1 LATCH ADDRESS.

AY -3-8912 General
The four low order address bits select one of the 1221E121 Registers, Function
16 registers (RO-R178). The six high order
address bits function as chip selects to control lone Generator RO--R5 Program tone periods
the tri-state bidirectional buffers (when the high Control
order address bits are incorrect, the bidirection- Noise Generator R6 Program noise period
al buffers are forced to a hig0 impedance state). Control
High order address bits n, A8 are fixed in the PSG Mixer Control R7 Enable tone and/or
design to recognize a "01" code; high order address noise on selected
bits DA7--DA4 are programmed to recognize only a channels
"0000" code. All addresses are latched internally. Amplitude R10 -R12 Select fixed or
This internally latched address is updated and modi- Control variable (envelope)
fied on every latch address signal presented to the amplitudes
Envelope R13 -R15 Program envelope
PSG via the BDIR, BC2, end BC1 inputs. A latched
Generator period end select
address will remain valid until the receipt of a new
Control envelope pattern
address, enabling multiple reads and writes of the
same register contents without the need for redun-
Tone Generator Control
dant re -addressing.
(Registers RO, R1, R2, R3, R4, R5)

Conditioning of the Register Address Latch/Decoder
and the Bidirectional Buffers to recognize the bus
The frequency of each square wave generated by the
function required (Inactive, Latch Address, Write
three Tone Generators (one each for Channels A, B,
Data), is accomplished by the Bus Control Decode and C) is obtained by first dividing the input
block. clock by 16 then by further dividing the result by
the programed 12 bit Tone Period value. Each 12 -
SOUND GENERATING BLOCKS: bit tone period value is obtained by combining the
contents of the respective Coarse and Fine Tune
The basic blocks in the PSG which produce the registers, as illustrated:
programed sounds include:
Coarse Tune Fine Tune
Tone Generators Produce the basic square wave Register Channel Register
tone each RI A RO
frequencies for
R3 R2
channel (A, B, C).
R5 R4
Noise Generator Produces a pulse width modulat-
ed pseudo -random square wave
COARSE TUNE FINE TUNE
output.
87 86 B5184 83 82181 BO 87 96 85 84 83 82 81 BO
Mixers Combine the outputs of the Tone
Generators and the Noise
Not Used
Generator; per channel (A, B,
TP TP
TP TP Tio TP TP
C).
11 10 9 8 7 6 5 a 3 1 0
Envelope Generator Produces an envelope pattern
which can be used to amplitude 12 -bit Tone Period (TP) to Tone Generator
modulate the output of each
Mixer. The period of the output of the tone generator is
Amplitude Control Provides the D/A Converters therefore determined by:
with either a fixed or variable
amplitude pattern. Fixed 16 x TP x P where P s the period of the input clock.
amplitude is under direct CPU
control. Variable amplitude is NOTE: If the Coarse and Fine Tune registers are
accomplished via the output of both set to 0008, the resulting period
the Envelope Generator. will be minimum, i.e., the generated tone
D/A Converters The three D/A Converters each period will be as if the Coarse Tune
produce a 16 level (max) output register was set to 0008 and the Fine Tune
signal as determined by the register set to 0018.
Amplitude Control.
OPERATIC/1s
Since all PSG functions are processor controlled

by writing to the internal registers, a detailed
description of the PSG operation soy best be
accomplished by relating each PSG function to
control of the corresponding register. The
function of cresting or programing specific
sound effect logically follows the control
sequence listed:

AY -3-8912 General
Noise Generator Control NOTE: Disabling noise end tone does not turn off
channel. fuming a channel off can only be accom-
(Register R6) plished by writing all zeros into the corresponding
Amplitude Control Register.
The frequency of the noise source is obtained by
dividing the input clock by 16, then by further Amplitude Control
dividing the result by the programed 5 bit Noise
Period value. This 5 bit value consists of the (Registers R10, 1111, R12)
lower 5 bits (B4--80) of register R6, as illus-
traded: The amplitude of the signals generated by each of
the three D/A Converters (or" each for Channels
Noise Period A, B, end C) is determined by -the content of the
Register R6 Lowers bits (84-80) of registers R10, R11, and
R12 as illustrated.
87 1 86 B4 1 83l B2 1 B 1 1 BO These five bits consist of a 1 -bit mode select ("M"

bit) and a 4 -bit "fixed" amplitude level (L3 -L0).
When the M bit is low, the output level of the
Not Used 5 -bit Noise Period (NP) analog channel is defined by the 4 -bit "fixed"
to Noise Generator
amplitude level of the Amplitude Control Register.
Mixer Control - I/O Enable This amplitude level is fixed in the sense that the
amplitude level is under direct control of the
(Register R7) system processor. When the M bit. is high, the out-
put level of the analog channel is defined by the
Register R7 is a multi -function man register 4 -bits of the Envelope Generator (bits E3 -E0). The
which controls the three Noise/Tone Mixers. amplitude mode bit can also be thought of as an
"envelope enable" bit.
The Mixers, as previously described, combine the
noise and tone frequencies For each of the three Amplitude Control Register Channel
channels. The determination of combining neither/ R10 A
either/both noise and tone frequencies on each R11 B
channel is made by the state of bits B5 --B0 of R12 C
register R7, as illustrated.

1 B6 1 85 B4 83 1 B2 I 81 i BO
The direction (input or output) of the general
purpose I/O ports (I/0A end I/08) is determined by Not used
the state of bits 87 and B6 of R7, es illustrated. M L3 i L2 i LI i LO
dA\L--11
MIXER CONTROL REGISTER - R7 Amplitude 4 bit fixed

Mode Amplitude Level
0 0 0 0 0 Amplitude Defined
By L0 -L3
Function:
Port: 0 1 1 1 1
X X X X Amplitude Defined
Function: By ED -E3
Channel: ENVELOPE GENERATOR CONTROL
NOISE ENABLE TRUTH TABLE TONE ENABLE TRUTH TABLE to accomplish the generation of complex envelope
R7 Bits Noise Enabled R7 Bits lone Enabled patterns, two independent methods of control are
B5 B4 B2 on Channel 82 81 BO on Channel provided: first, it is possible to vary the
0 0 0 C B A 0 0 0 CBA frequency of the envelope using registers R13 and
0 0 1 C 8 0 0 1 C 8 R14; second, the relative shape and cycle pattern
0 1 0 C A 0 1 0 C A of the envelope can be varied using register R15.
0 1 1 C - 0 1 1 C - the following paragraphs explain the details of the
1 0 0 B A 1 0 0 8 A envelope control functions, describing first the
1 0 1 8 - 1 0 1 8 - envelope period control and then the envelope
1 1 0 A 1 1 0 A shape/cycle control. (See Figure 1 and 2).
1 1 1 -- 1 1 1 ---
I/O PORT TRUTH TABLE
R7 Bits I/O Port Status
B7 B6 I/OB I/0A
0 0 Input Input
0 Input Output
0 Output Input
Output Output

AY -3-8912 General
ENVELOPE PERIOD CONTROL
(Registers R13, R14)
The frequency of the envelope is obtained by first lope Period value. This 16 bit value is obtained
dividing the input clock by 256, then by further by combining the contents of the Envelope Coarse
dividing the result by the programed 16 bit Enve- end Fine Tune registers, es illustrated:
Envelope Envelope
Coarse Tune Fine Tune
Register R14 Register R13
87 86 85 84 83 87 86 85 BA 83 B2
EP15 EP14 1EP13 1 EP12 EP1 1 EP10 1EP9 I CP8 EP7 EP6 EPS EPS_ EP31 EP2 EP1 I EPO
16 -bit Envelope Period (EP) to Envelope Generator

Thus the envelope period is given by:
256 x EP x P Where P z period of input clock
NOTE: If the Coarse end Fine Tune registers are both set to 0008, the resulting period will be minimum,
i.e., the generated tone period will be es if the Coarse Tune register was set to 0008 end the
Fine Tune register set to 0018.
ENVELOPE SNAPE/CYCLE CONTROL
(Register R15) Bit 0: HOLD When this is set high (logic 1)

the envelope is limited to one
The Envelope Generator further divides the envelope cycle, tme value of the envelope
period by 16, producing a 16 -Mate per cycle at the end o; the cycle being
envelope pattern as defined by the 4 -bit counter held.
output, E3, E2, El end EC. The particular shape
and cycle pattern of any desired envelope is Bit 1: ALTERNATE When set high (logic 1) the
accomplished by controlling the count pattern of envelope counter reverses direc-
the 4 -bit counter. (See Figure 4 and 5). tion at end of each cycle (i.e.
performs es an up/down counter).
This envelope shape/cycle control is contained in
the lower 4 bits (83 --80) of register R15. Each Bit 2: ATTACK When set high (logic 1) the
of these 4 bits controls a function in the envelope envelope counter will count uo
generator, as illustrated: (attack). When set low (logic
0) the counts- will count down
Envelope Shape/Cycle (decay).
Control Register (R15)
Bit 3: CON'INUE When se: high !logic I) the
87 B6 185 B3 B2 BI BO Function cycle pa:tern will be defined by
Mold the HOLD bit. When set low
Not Used (logic C) the envelope counter
Alternate To will reset to 0000 after one
Envelope cycle,'end hold that value.
Attack Generator
Continue

AY -3-8910 General
D/A CONVERTER OPERATION

..comAL int
Aal
Since the primary use of the PSG is to produce

sound For the non-linear amplitude detection 010.1 ENVELOPE 0.11.-
..0181 AND 70111ES
mechanism of the human ear, the D/A conversion is ME DISABLED -
performed in logarithmic steps with a normalized

voltage range from 0 to 1 volt. fhe specific
amplitude control of each of the three D/A Conver-
Typical reflo trip, ono slop
ters 16 accomplished by the three sets of 4 bit If tno mix/ loser step Is: 1.2/1.7
outputs of the Amplitude Control block, while the
Mixer outputs provide the base signal frequency
DOLCANN
(Noise and/or tone). (See Fig. 3). 0.13[71,10
9
man
a a IV OW
V C 00 Now. Coq 0"

I PPP, t
I. 1.
I. 1...110.1.111.00
P55.3 D/A CONVERTER OUTPUT
11 ,N"...
Il t .5 1. I we. 0.1 wNoo

0.01 CC-1
Rig. I ENVELOPE INAP1./CYCLE OPERATION
Pls. 5 MIXTURE Of TNPIIIE TONES

WITH FIXED AMPLITUDES

AY -3-8910 General
ELECTRICAL CHARACTERISTICS
Mexiaue Ratings *Exceeding these ratings could cause permanent

Storage Temperature -55.0 to .150'c deluge to the device. Thu is a stress rating only
Operating Temperature o'c to .70"C and functional operation of this device at these
VCC and all other Input/Output conditions is not implied-operating ranges are
Voltages with Respect to Vss... . -0.3V to .8.0V specified in Standard Conditions. Exposure to
absolute maximum rating conditions for extended
Standard Conditions (Unless otherwise noted) periods may effect device reliability. Data labeled
VCC z +5V 5% 411 "typical" is presented for design guidance only and
Vss CND is not guaranteed.
Operating Temperature r 0"C to .70"C
DC CHARACTERISTICS
Characteristics Sys Kin Tvp" Max Units Conditions
All Input,
Low Level VIL -0.2 - 0.8 V
High Level VIM 2.2 -

VCC V
Dots Bus (DA7...DAO) Output Levels

Low Level 0 - 0.4 V Ioi = 1.6mA, 150pr
VOL
Migh Level 2.4 - V loN z 100yA, 150pr
VOM VCC
Data Bus (DA7...0A0)
Input Leakage I/AL -10 - 10 +A VIN s 0.4V to VCC
Analog Channel Outputs
Output Volume Vo 0 - 60 dB Test Circuit: Fig. 6
Power Supply Current 'CC - 70 90 leA
I/O Poets
Pull Up Current Low 1IL 20 - ZOO yA VIM z 0.4V, Outputs disabled
Pull Up Current Migh 11M 10 - 100 FA VIN z 3.5V
As Outputs (A7 -A0, 87-90)
Low Level VOL 0 - 0.5 V 'IL z 1.6mA
High Level VOHh 3.5 - VCC V 10Hh z -'0+A See
VOMI 2.4 - VCC v INI z 850 Note I
As Inputs (A7 -A0, B7-80)

Low Level VIL 0 - 0.8 V
High Level 2.4 - V

VIM VCC
Al and Ramat Input
Pullup Current IILN -10 - -100 PA VIN s 0.4V
1lHpu -10 - -50 yA VIN z 2.4V
sif
Pull dawn Current 'Nod 10 - 100 yA VIM z 2,4V
8C1,11DIR, Clock Inputs
Input Leakage 1 1 a
-10 - 10 pA VIM s 0.4V to VCC
Analog Outputs
Mex. Current (per channel) - 0.4 2.0 - EA VOLT s 0.7V, Amplitude
Control Set To r
'Typical values are at .25'C en nominal voltages.
NOTE 1:
The active pull-up during an output operation will up current will reduce significantly and further
achieve a logic 1 of 2.4 volts in a time of edge transition will be highly dependent upon load
typically 1 microsecond. However, from 2.4 volts capacitance.
to the high level of 3.5 volts the available pull

AY -3-8912 General
ELECTRICAL CHARACTERISTICS (continued...)
AC CHARACTERISTICS
Characteristics Sym TVP Units Conditions
Clock Input
Frequency fc
1 - 2 141z
Rise Time tr - - 50 ns Fig. 7
Fall Time tf - - 50 ns
Duty Cycle - 40 50 60 %
Bus Signals (8DIR, 8C2, BC1)
Associative Delay Time tRto - - 40 ns
Reset
Reset Pulse Width tRW 500 - - ns Fig. 8
A9, AS, DA7..DA0 (Address Mode)
Address Setup 'ism tAS 300 - - ns
Address Hold Time 65 - ns Fig. 9
tAH
DA7...DA0 (Write Mode)
Write Data Pulse Width tfyw 500 10,000 ns
Write Data Setup Time tDS 300 - - ns Fig. 10
Write Data Hold Time tDH 65 - - ns
DA7...DA0 (Read Mode)
Data Access Time from DTB tDA - - 200 ns Fig. 11
DA7...DA0 (Inactive Mode)

Tri -state Delay Time from DTB tys - - 100 ns
I/O Ports (A7 -A0, 67-80)
Pull -Up Recovery Time tpN - - 50 usec V0H : 3.5V
CLOAD = 100p f
See Note 2
**Typical values are at .25.c and nominal voltages
NOTE 2?
Pull-up recovery time is defined as the time volts. This recovery time is conditional on the
required for any I/O pin A7 -A0 or B7-80 to change output function of Port A or Port B being
up to a 100pf capacitor load from 0.0 volts to 3.5 deselected via Bits B7 and B6 of register R10.
STATE TIMING
While the state flow for many microprocessors can be somewhat involved for certain operations, the
sequence of events necessary to control the PSG is simple and straightforward. Each of the three major
state sequences (Latch Address, Write to PSG, and Read from PSG) consists of several operations (indicated
below by rectangular blocks), defined by the pattern of bus control signals (BDIR, BC1).
INACTIVE OUTPLT INACTIVE OUTPUT INACTIVE

ADDRESS DATA
amonammormom.
Address and Write Data

to PSG Sequence
INACTIVE INACTIVE INPUT INACTIVE

DATA
Address and Read Data

From PSG Sequence

AY -3-8912 General
The functional operation and relative timing of the PSG control sequences are described in the following
paragraphs.
ADDRESS PSG REGISTER SEQUENCE
The Latch Address sequence is normally an integral part of the write or read sequences, but for simplicity
is illustrated here as in individual sequence. Depending upon the processor used, the program sequence
will normally require four principal' microstates: (1) send NACT (inactive); (2) send INTAK (latch
address): (3) put address on bus; (4) send PACT (inactive).
IDIR
//
'Cl
BUS
CONTROL NACT INTAK
0A7-0/0 DON'T
CARE
WRITE DATA TO PSG SEQUENCE
The Write to PSG sequence, which would normally follow immediately after an address sequence, requires
four principal microstates: (1) send MCI (inactive); (2) put data on bus; (3) send DNS (write to PSC);
(4) send NACT (inactive).
BDIR
BC1
BUS
NACT DVS NACT
CONTROL
READ DATA FROM PSG SEQUENCE
As with the Write to PSG sequence, the Read from PSG sequence would also normally follow immediately
after an address sequence. The four principal microstates of the read sequence are: (1) send NACt
(inactive); (2) send DfB (reed from PSG); (3) reed data on bus; (4) send NACT (inactive).
BDIR
8C1
BUS
CONTROL MALT r,1 018 NACT
0A7 -DAD

AY -3-8912 General
TIMING DIAGRAMS
Vfl
MIR/
BC1
VIL
tBD
v
iH
BDIR/
BC'
V
IL
a. b.
Fig. 7 CLOCK AND BUS SIGNAL TIMING
FIRM H
RESLI
VIL
FIG. 8 RESET TIMING
BUS
CONTROL INACTIVE LATCH INACTIVE
DECODE A ADDRESS
tAM
VIM
A9 AB
DA7-040
V1L
p77 BUS CONTROL 6901R sci

iiy_d SIGNALS CHANGING 1 1
-.1 50ns Mex., Including Skew.
Fig. 9 LATCH ADDRESS TIMING

AY -3-8912 General
WRITE TO PSG* INACTIVE

BUS
CONTROL
INACTIVE
7/7
DECODE tOW er
tDS
VIN
PREVIOUS VALID DATA INPUT
STATE VIL
pfh BUS CDNIRCIL

SIGNALS CHANGING
./.1
5Ons MAX, M3DIR Bc1
Including Skew 1 0
FIG. 10: WRITE DATA TIMING
BUS
CONTROL INACTIVE READ FROM PSG' INACTIVE
1/
DECODE
rrs 1.411"
40H
DA7 - -DAD PREVIOUS READ VALID DAIA fRISTATE
STATE Jot.
tRA 40H
VOL
15216 MAX, Including Skew
°BDIR BC1
BUS CONTROL
SIGNALS CHANGING 0
FIG. 11t READ DATA TIMING

FAIRCHILD
A2240 A Schlumberger Company
Programmable Connection Diagram

16 -Lead DIP
Counter/Timer (Top View)
Description
0o VCC
The pA2240 Programmable Timer/Counter is a monolithic
15
controller capable of producing accurate microsecond to REGULATOR
01
five day time delays. Long delays, up to three years, can OUT
easily be generated by cascading two timers. The timer 14
0, Tsa-aAsa
consists of a time -base oscillator, programmable 8 -bit OUT
counter and control flip-flop. An external resistor capacitor 13
RESISTOR/
(RC) network sets the osciNator frequency and allows de- Oi -2 CARACROR IN
lay times from 1 RC to 255 RC to be selected. In the 12
astable mode of operation, 255 frequencies or pulse pat- 04.

rouLAnos
terns can be generated from a single RC network. These 11
frequencies or pulse patterns can also easily be synchro- 032C,_: TRIGGER IN

nized to an external signal. The trigger, reset and outputs 10
are all TTL and DTL compatible for easy interface with
digital systems. The timer's high accuracy and versatility in
Ow CONTROL rD RESET
FLIP-FLOP
producing a wide range of time delays makes it ideal as a
ONO
direct replacement for mechanical or electromechanical de-
vices.
Accurate Timing From Microseconds To Days

Programmable Delays From 1 RC To 255 RC Order Information
TTL, DTL And CMOS Compatible Outputs Device Code Package Code Package Description
Timing Directly Proportional To RC Time Constant (.1A2240DC 78 Ceramic DIP
High Accuracy pA2240PC 9B Molded DIP
External Sync And Modulation Capability
Wide Supply Voltage Range
Excellent Supply Voltage Rejection

Storage Temperature Range
Ceramic DIP -65°C to + 175°C
Molded DIP -65°C to + 150°C
Operating Temperature Range 0°C to 70°C
Lead Temperature
Ceramic DIP (soldering, 60 s) 300°C
Molded DIP (soldering, 10 s) 265°C
Internal Power Dissipationl 2
16L -Ceramic DIP 1.50 W
16L -Molded DIP 1.04 W
Supply Voltage 18 V
Output Current 10 mA
Output Voltage 18 V
Regulator Output Current 5.0 mA
Notes
I T, . 150T for the Molded DIP, and 175T for the Ceramic DIP
2 Ratings apply to ambient temperature at 25T Above this temperature.
derate the 16L -Ceramic DIP at 10 mW/T. and the 16LMolded DIP at
63 mWiT
Block Diagram
REGULATOR
COMP 1 OUT
R2 1
aM 161
FLS'ILO MM. y. 2 CONTROL
LOGIC
RESET
TRIGGER IN
Ti OUT Oo 02 ova
TIME DRURY mix.
SASE COUKTER HcomFUP-FLOP
Data supplied by Fairchild Semiconductor Ltd. Fairchild Semiconductor.

FAIRCHILD
Functional Description Figure 3 Basic Circuit Connection

(Figure 1 and Block Diagram) for Timing Applications
When power is applied to the pA2240 with no trigger or Monostable: SI Closed
reset inputs, the circuit starts with all outputs HIGH. Appli- Astable: S1 Open
cation of a positive going trigger pulse to trigger lead 11,
initiates the timing cycle. The trigger input activates the
time -base oscillator, enables the counter section and sets
the counter outputs LOW. The time -base oscillator gener-
ates timing pulses with a period T = 1 RC. These clock
pulses are counted by the binary counter section. The tim-
ing sequence is completed when a positive going reset TRIGGER
pulse is applied to Reset, lead 10.
Once triggered, the circuit is immune from additional trig-

ger inputs until the timing cycle is completed or a reset
input is applied. If both the reset and trigger are activated
simultaneously, the trigger takes precedence.
Figure 2 gives the timing sequence of output waveforms

at various circuit terminals, subsequent to a trigger input.
When the circuit is in a reset state, both the time -base
and the counter sections are disabled and all the counter 1 T To 255T
WHERE T RC
outputs are HIGH. TRIGGER
Figure 1 Logic Symbol

12
1 0.02411l
RC MOO
11 TRIO
.A2:240 V510 16
Note: Under the conditions of high supply voltages
10
(Vcc > 7.0 V) and low values of timing capac tor
TOO Oa 02 04 Os (CT < 0.1µF), the pulse width of TEI0 may be too narrow
to trigger the counter section. This can be corrected by
14 1 2 3 4 5 6 7 II connecting a 600 pF capacitor from TB() (lead 14) to
ground (lead 9).
VCC Leal 18
GNID Lead 9
CA0200.1f Reset (lead 10) stops the time -base oscillator.
Outputs (00.. 0120 (leads 1 - 8) sink 2.0 mA current

with VOL <0.4 V.
Figure 2 Timing Diagram of Output Waveforms
For use with external clock, minimum clock pulse ampli-
n - I
TRIGGER
IN
tude should be 3.0 V, with greater than 1.0 us pulse dura-
tion.
LEAD 11
TIME BABE
111111111111111111111111 OUT
LEAD 14
Circuit Controls
COUNTER
- OUT
Counter Outputs (00... 012s, leads 1 thru 8)
LEAD 1
- LEAD 2
The binary counter outputs are buffered open collector
type stages, as shown .n the block diagram. Each output
is capable of sinking 2.0 mA at 0.4 V Vol.. 11 the reset
Ion condition, all the counter outputs are HIGH or in the non-
conducting state. Following a trigger input, the outputs
--a I LEAD 4 change state in accordance with the liming diagram of
h LEAD II
Cl101110,
Figure 2. The counter outputs can be used individually, or
can be connected together in a wired -OR configuration, as
described in the programming segment of this data sheet.
In most timing applications, one or more of the counter Reset and Trigger Inputs (R and TRIG, 10 and 11)
outputs are connected to the reset terminal with S1 The circuit is reset or triggered with positive going control
closed (Figure 3). The circuit starts timing when a trigger pulses applied to leads 10 and 11 respectively. The
is applied and automatically resets itself to complete the threshold level for these controls is approximately two di-
timing cycle when a programmed count is completed. If ode drops (--t, 1.4 V) above ground. Minimum pulse widths
none of the counter outputs are connected back to the for reset and trigger inputs are shown in the Performance
reset terminal (switch S1 open), the circuit operates in an Curves. Once triggered, the circuit is immune to additional
astable or free running mode, following a trigger input. trigger inputs until the end of the timing cycle.
Important Operating Information Modulation and Sync Input (MOD, lead 12)
The oscillator time -base period (T) cal be modulated by
Ground connection is lead 9. applying a DC voltage to MOD, lead 12 (see Performance
Curves). The time -base oscillator can be synchronized to
Reset (R) (lead 10) sets all outputs HIGH an external clock by applying a sync pulse to MOD, lead
12, as shown in Figure 4. Recommended sync pulse
Trigger (TRIG) (lead 11) sets all outputs LOW. widths and amplitudes are also given.
Time -base output (TBO) (lead 14) can be disabled by Figure 4 Operation with External Sync Signal
bringing the RC input (lead 13) LOW via a 1 0 kQ resis- 1.4 1.42.- 0.3 T Tp < T
tor.
Normal TBO (lead 14) is a negative going pulse greater

than 500 ns.

FAIRCHILD
µ,A2240 A Schlumberger Company
The time -base can be synchronized by setting T to be an 4 1.4 V. The counter section can be disabled by clamp-
integer multiple of the sync pulse period (Ts). This can be ing the voltage level at lead 14 to ground.
done by choosing the timing components R and C at lead
13 such that: When using high supply voltages (Vcc > 7.0 V) and a
small value timing capacitor (CT < 0.1 pF), the pulse width
T = RC = (Ts/m) at TBO lead 14 may be too narrow to trigger the counter
secton. This can be corrected by connecting a 600 pF
where: capacitor from lead 14 to ground.
m is an integer. 1.0 < m < 10 Regular Output (VREG, lead 15)

The regulator output VREG is used internally to drive the
Figure 5 gives the typical pull -in range for harmonic syn- binary counter and the control logic. This terminal can
chronization for various values of harmonic modulus, m. also be used as a supply to additional pA2240 circuits
For m c 10, typical pull -in range is greater than ± 4% of when several timer circuits are cascaded (see Figure 6) to
time -base frequency. minimize power dissipation. For circuit operation with an
external clock, VREG can be used as the Vcc input termi-
RC Terminal (lead 13) nal !o power down the internal time -base and reduce pow-
The time -base period T is determined by the external RC er dssipation. When supply voltages less than 4.5 V are
network connected to RC, lead 13. When the time -base is used with the internal time -base, lead 15 should be short-
triggered, the waveform at lead 13 is an exponential ramp ed to lead 16.
with a period T = 1 RC. Monostable Operation
Time -Base Output (TBO, lead 14) Predsion Timing
The time -base output is an open -collector type stage as In precision timing applications, the pA2240 is used in its
shown in the block diagram, and requires a 20 162 pull-up monostable or self -resetting mode. The generalized circuit
resistor to lead 15 for proper circuit operation. In the reset connection for this application is shown in Figure 3. The
state, the time -base output is HIGH. After triggering, it pro- output is normally HIGH and goes LOW following a trigger
input. It remains LOW for the time duration (To) and then
duces a negative going pulse train with a period T = RC,
as shown in the diagram of Figure 2. The time -base out- returns to the HIGH state. The duration of the timing cycle
put is internally connected to the binary counter section To is given as:
and can also serve as the input for the external clock
signal when the circuit is operated with an external time To nT NRC
base. The counter section triggers on the negative going
edge of the timing or clock pulses generated at TBO, lead where T - RC is the time -base period as set by the
14. The trigger threshold for the counter section is choice of timing components at RC lead 13 (see Perfor-
mance Curves) and n is an integer in the range of
Figure 5 Typical Pull -in Range for 1 5 n <255 as determined by the combination of counter
Harmonic Synchronization outputs (00. 012s), leads through 8, connected to the
1
output bus.
20 Courier Output Programming
0 The binary counter outputs, 00... 012e, leads 1 through 8
C
91 I 14
are cpen collector type stages and can be shorted togeth-
er to a common pull-up resistor to form a wired -OR con-
nection; the combined output will be LOW as long as any
to one of the outputs is LOW. The time delays associated
with each counter output can be added together. This is
S
done by simply shorting the outputs together to form a
common output bus as shown in Figure 3. For example, if
only lead 6 is connected to the output and the rest left
2 14 open, the total duration of the timing cycle, To, is 32 T.
Similarly, if leads 1, 5, and 6 are shorted to the output
0
bus, the total time delay is To (1 + 16 + 32) T 49 T. In
0 4 S 1 10 12 this manner, by proper choice of counter terminals con-
RATIO OF TIME -SASE PERIOD TO nected to the output bus, the timing cycle can be pro-
SYNC -PULSE PERIOD - VT.
grammed to be 1 T <To <255 T.
Figure 6 Low Power Operation of Cascaded Timm

vcc vcc Vcc
RL
47 to 30 to
TRIGGER
TRIG
RC MOO
111 1610
RC
vA2240 r2
MOO
Vnao
RESET
7S0 0o 00 0.
'..121°04 ON" 0420m VC::
OUT
$6 MO
VCC Lead 18
ONO Lud 9
CWOTOSOF

FAIRCHILD
A2240 A Schlumberger Company
Ultra Long Time Delay Application Figure 8 Operation with Trigger

Two pA2240 units can be cascaded as shown in Figure 7 and Reset inputs (Note 1)
to generate extremely long time delays. Total timing cycle
vcc
of two cascaded units can be programmed from To = 256
RC to To = 65,536 RC in 256 discrete steps by selectively RL
10 AD
shorting one or more of the counter outputs from Unit 2
to the output bus. In this application, the reset and the
001 .F
trigger terminals of both units are tied together and the
Unit 2 time base is disabled. Normally, the output is HIGH
TRIGGER
when the system is reset. On triggering, the output goes
LOW where it remains for a total of (256)2 or 65,536 cy- __ RC MOD
TRIG
cles of the time -base oscillator.
-A2240
In cascaded operation, the time -base section of Unit 2 can RESET

R TOO 00 0? 04 Oa 01,032 0114 0 In 20 Arl
be powered down to reduce power consumption by using
the circuit connection of Figure 6. In this case, the Vcc
terminal (lead 16) of Unit 2 is left open, and the second
unit is powered from the regulator output of Unit by 1
connecting the VREG (lead 15) of both units together. OUT
Astable Operation
The pA2240 can be operated in its astable or free running
mode by disconnecting the reset terminal (lead 10) from
the counter outputs. Two typical circuits are shown in Fig-
Figure 9 Free Running or
ures 8 and 9. The circuit in Figure 8 operates in its free
Continuous Operation (Note 1)
running mode with external trigger and reset signals. It
starts counting and timing following a trigger input until an dcc 40.0 vcc
external reset pulse is applied. Upon application of a posi-

tive going reset signal to lead 10, the circuit reverts back
to its reset state. This circuit is essentially the same as
that of Figure 3 with the feedback switch S1 open,
The circuit of Figure 9 is designed for continuous opera-

tion. It self triggers automatically when the power supply is
turned on, and continues to operate in its free running
mode indefinitely. In astable or free running operation, 0.047 .F
each of the counter outputs can be used individually as
synchronized oscillators, or they can be interconnected to
generate complex pulse patterns.
Binary Pattern Generation

In astable operation, as shown in Figure 8, the output of
the pA2240 appears as a complex pulse pattern. The
waveform of the output pulse train can be determined di-
rectly from the timing diagram of Figure 2 which shows Figure 10 Binary Pulse Patterns Obtained
the phase relations between the counter outputs. Figures by Shorting Various Counter OJtputs
10 and 11 show some of the complex pulse patterns that A. 2 LEAD PATTERNS
can be generated. The pulse pattern repeats itself at a
rate equal to the period of the highest counter bit con-
nected to the common output bus. The minimum pulse I- 13tT RC
4.411*-
LE ADS 1 AND 2 SHORTED
-HT he- ho- ST -H.- TT -Owl
width contained in the pulse train is determined by the
B 3 LEAD PATTERN
lowest counter bit connected to the output.
31.4-04.-5T ZIT
LEADS 1, 3, AND 5 SHORTED
C.4 LEAD PATTERN
Note
I Vcc Lead 16
3T [A4-40- 57 4+-410---Z1T +T I 5T -471'.--"T GND Lead 9
Figure 7 Cascaded Operation for Long Delays
vcc vcc vcc
RL
10 50
RC MOD
TRIGGER TRIG
.A2240 1 Vraga
TWO 00 02 0,/, 04 0,4033 OW 012111
RESET OUT
vec lead 16 TO
GND Lead 9

FAIRCHILD
Figure 11 Continuous Free run Operation Examples of Output Typical Performance Curves
vcc 'cc Supply Current vs
Supply Voltage In Reset Condition
IS
1 12
0
0 2 4 0 10 12 14 10
rYYrrYOYYMPiell
S 10
RC WAVEFORM SUPPLY VOLTAGE -V
1.031C01,
T1MIESASE OUTPUT
I I 1 1 1 1 1 1 1 1 I I I 1
0. OUTPUT
Minimum Trigger Pulse Width vs
Trigger and Reset Amplitude
20
2/3C
I 2.5
2_0
mmc
1110 00 0, 0. 0. 0..0.
Yne0 15
75C
VC
-
iviiii 10
to 15 20 2.5
TRIGGER OR RESET AMPLITUDE -V
3.0
vrma Normalized Change in Time -Base

1110 0. 0. O. 0. Period vs Modulation Voltage
2.1
1111110 -.I 2 RC 1.12.201*C 2 AC i..--

2.0
VU 5 V
-210 RC /
...1
as
RC -H
2 3 1 5
Vc, Lew
GNO Coal 9
16 _J L MOOULA71044 VOLTAGE -V
Recommended Range of Time -Base Period Drift vs Time -Base Period vs

Timing Component Values Supply Vol age Temperature
lo 10 2.0
V00 5 V
C 0.10
10 14
2.0 10
C
100 K
, .- .
O to
*
S C 01,,
a 10 u11
V
re V R 1 Id)
10 1.0
II 10 MO
10 K 10 20
1
100 -20 3.0

0001 CUM 0.1 1.0 10 100 10,00 12 14 0 as 50 73 100
TIMING CAPACITOR - SUPPLY VOLTAGE -V TEMPERATURE -
PC0111Yff

FAIRCHILD
liA2240 A Schlumberger Company
Electrical Characteristics TA 25°C, Vcc - 5.0 V, R - 10 kS2, C - 0.1 µF, unless otherwise speci9ed.
General Claracteristic
Vcc Supply Voltage For Vcc <4.5 V, Short Lead 15 to 4.0 15 V
Lead 16
Icc Supply Total Circuit Vcc - 5.0 V, VTR -0 V, VRs - 5.0 V 4.0 7.0 mA
Current
Vcc - 15 V, VTR -0 V, VRs 5.0 V 13 18
Counter Only 1.5
VREG Regulator Output Measured at Lead 15 Vcc - 5.0 V 3.9 4.4 V
Vcc - 15 V 5.8 6.3 6.8

Time -Base
tACC Timing Accuracy' VRS 0, VTR - 5.0 V 3.5 5.0 %
At/AT Temperature Drift 0°C < Tj 75°C Vcc - 5.0 V 200 ppm/°C
Voc - 15 V 80
At/ AV Supply Drift Vcc 8.0 V (See Performance Curves) 0.08 0.3 %/V
thtax Max Frequency R - 1.0 kS2, C = 0.007 µF 130 kHz
Vuoo Modulation Voltage Level Measured at Lead 12 Vcc - 5.0 V 2.80 3.50 4.20 V
Vez = 15 V 10.5
Rr Recommended Range of (See Performance Curves) 0.001 10 MS2

Timing Components Timing
Resistor
Electrical Characteristics TA 25°C, Vcc - 5.0 V, R 10 kS2, C - 0.1 uF, unless otherwise spected
CT Timing Capacitor 0.01 1)00 µF
Trigger/Reset Controls
VTR Trigger Threshold Measured at Lead 11, VRS 0V 1.4 2.0 V
ITR Trigger Current VRS 0 V, VTR 2.0 V 10 PA
ZT Trigger Impedance 25 kS2
tRSPT Trigger Response Time2 1.0 AS
VRS Reset Threshold Measured at Lead 10, VTR 0V 1.4 2.0 V
IR Reset Current VTR 0 V, VRS 2.0 V 10 PA
ZR Reset Impedance 25 ka
tRSPT Reset Response Time2 0.8 As
Counter
TRp Max Toggle Rate Measured at Lead 14 1.5 MHz
VRS -0 V, VTR 5.0 V
Z1 Input Impedance 20 kit
VTR Input Threshold 1.0 1.4 V
4 Output Rise Time Measured at Leads 1 through 8 180 ns

RL - 3.0 kS2, Cu- 10 pF
tt Fall Time 180
IQ- Sink Current Vot. < 0.4 V 2.0 4.0 mA

Ice( Leakage Current VoR .. 15 V 0.01 15 µA
Notes
1 Timing error solely introduced by µA2240 measured as of ideal rime -base period of T=RC.
2 Propagation delay from application of trigger (or reset) input to col respond,ng change of state in counter output at lead 1
Time -Base Period vs Minimum Trigger/Retrigger Timing Time -Base Period vs

External RC vs Timing Capacitor Temperature
100
R-R z 2_0
16 V
VCc
R10 kA C 0.1
10
Vcc IS If / /
//
I
1 Id/
1.0
I
01
/ occ.6.1
MIMMUM TRIGGER DELAY
10 Mn
A TIME SUSSEGLIENT TO
,/ APPLICATION OF POWER
MINIMUM RETRIGGER
1 Mn
Mn S TIME {uRREOIJERT TO A
RESET INPUT
0.01
10 100 m 1.1 ma 10 ma 100 ow 1.0 s 10 . 100 0 0.1 1.3 10 100 23 SO /5 100
TIME EASE PER100 TIMING CAPACITOR - TEMPERATURE - C
PON. C.,

Electronics Digest 1987 Summer PDF

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Electronics Digest 1987 Summer PDF

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SUMMER 1987 VOL 8 NO 1 AN ARGUS SPECIALIST PUBLICATION £2.

trol provide a high performance, cost effective and DOT TKO

The modem chip performs the modulation, demodulation, EDET 7 SCT

Absolute Maximum Ratings

Data supplied by Fairchild Semiconductor Ltd. ,c Fairchild Semiconductor.

Electronics Digest Summer 1987

Isles) M112 polyphonic sound generator 10

Thanks to Mullard/Signetics, National Semiconductor, Fairchild, Texas Instruments, General Instrument,

Electronics Digest Summer 1987 3

FM Radio Circuit PIN CONFIGURATION

FUNCTIONAL PIN DESCRIPTION

MUTE CONTRO UTE LOOFILTER

4 Electronics Digest Summer 1987

Vcc Supply voltage (Pin 5) 2.7 4.5 10 V

lec Supply current Vcc - 4.5V 8 mA

le Oscillator current (Pin 6) 280 MA

V1416 Voltage (Pin 14) 1.35 V

12 Output current (Pin 2) 60 14A

V2-16 Output voltage (Pin 2) RL - 22 kg 1.3 V

-3 dB limiting; muting disabled 1.5

S/N Signal-to-noise ratio 60 dB

Of - ±22.5 kHz 0.7

(ratio of the AM output signal referred to the FM

Ve.e(,e) Oscillator voltage (r.m.s. value) (Pin 61 250 mV

Ofeec Variation of oscillator frequency Supply voltage (aVec - 1V) 60 kHzN

iifd A.F.C. range ±300 kHz

1/0") A.F. output voltage (r.m.s. value) RI_ - 22 k0 75 mV

Figure 1. Power Denning Curve.

Electronics Digest Summer 1987 5

Conditions: OdB = 75mV; fri = 96 MHz

- 220pF 330pF 100nF 220pF 3.3nF

MUTE CONTROL UTE LOOP

Figure 3. Test Circuit

6 Electronics Digest Summer 1987

DC Motor Speed Control Circuit

The µA7392 compares actual motor speed to an externally

system's negative feedback loop.

Thermal and over voltage shutdown are included for self-

Absolute Maximum Ratings

Electronics Digest Summer 1987 7

LINER88 Regulator Output Line V+ - 10 V to 16 V 6.0 20 mV

'IN Tachometer ( + ) Input Bias V5 - V3 1.0 10 µA

R Pulse Timing ON Resistance V6 - 1.0 V 300 500 SI

VTH Pulse Timing Switch Threshold 45 50 55 %V8

VSet-LOW Pulse Output LOW Saturation 0.13 0.25 V

VSat-Hi Pulse Output HIGH Saturation 0.12 0.2 V

Vskr Motor Drive Output Saturation Iii = 300 mA 1.3 2.0 V

'LEAK Motor Drive Output Leakage V11 -V10= 16 V 5.0 mA

VTH Stall Timer Threshold Voltages 2.5 2.9 3.5 V

ITH Stall Timer Threshold Currents 0.3 3.0 PA

8 Electronics Digest Summer 1987

Typical Performance Curves

Supply Current vs Regulator Output Voltage vs Regulator Output Voltage Vs

Supp y Voltage Supp y Voltage Junction Temperature

JUNCTION TEMPERATURE - FLYBACK 01001 VOLTAGE -V MOTOR DRIVE OUTPUT ON VOLTAGE -V

Motor Drive Output ON Voltage vs Typical Application Using Magnetic Tachometer

Polyphonic Sound Generator

ABSOLUTE MAXIMUM RATINGS

MECHANICAL DATA (Dimension in mm) PIN CONNECTIONS

RECOMMENDED OPERATING CONDITIONS

10 Electronics Digest Summer 1987

MULTIPLEXER FOOTAGE thiVE.0.10

STATIC ELECTRICAL CHARACTERISTICS