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VHDL (EC-406) Question Bank ECE 8th Semester Prepared By: Er. J.S.

Walia

1. Introduction
2 marks questions • What type of language is VHDL? • What do all VHDL designs begin with? • Which block describes a design's interface? • What is the difference between simulation and synthesis? • Which data type describes a bus? • Which data type defines a single logic signal? • What is SUBTYPING used for? • Which symbol is used to end all VHDL statements? • What are the two primary ways to describe a logic circuits function within an architecture block? • How do signal declarations differ from port interface declarations? • What are the numerical data types? • What is the purpose of a SIGNAL declaration? 5 marks questions • What is the basic building unit of a VHDL design? • What are the IEEE STD_LOGIC_1164 data types for single logic signals and buses? • Create the use data type DAYS and assign it the values: MON, TUE, WED, THU, FRI, SAT and SUN. • Create the entity block for a three input XOR gate. Create the integer constant included in an entity block, called BUS_SIZE and assign it a value of 32. • Create the architecture block for the 3-input XOR gate of question 21.

2. VHDL Statements
2 marks questions • In an if..then..else construct, which statements are executed if the condition is TRUE and which if it is FALSE? • What reserved word is used to nest if..then..else statements? • Write the process block that separately tallies positive and negative transitions of the signal TIME_OUT.

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What is the purpose of a for loop? What is the basic building element of a structure design? What is meant by instantiating a component? Which standard library does not require a library or use statement? Write is the general rule for component declarations? When is a PACKAGE BODY used? Write an assignment statement that assigns the contents of s(5) to t(2). What are the requirements for a for loop? What is a PACKAGE? What are the results of using CLK'event as a condition in the if statement of the DEF example?

5 marks questions • Write a package declaration called OPERATOR to hold the following items: o type op_code ( ADD, SUB, MULT, NULL); o constant word_count : integer := 0; o constant op_start : op_code := null; • Write a process block that uses a for loop to set a zero flag high if all the bits in a sixteen (16) bit word are low (zero).

3. Combinational Circuit Design
2 marks questions • Write the component declaration for the XOR gate • Write a VHDL model for an AND gate • Write a VHDl model for xor gate using other gates. • Write a VHDL code for Half adder and Full adder. 5 marks questions • Write a VHDL moel for 8 bit Multiplexer and demultiplexers • Write VHDL Code for 2 complements • Describe VHDL model for binary to gray converter. • Design a VHDL code for Subtractor and Comparator

4. Sequential Circuit Design
2 marks questions • Which is the default architecture block in a multiple architecture design? • What is a shift register and Flip Flops. • What is a Multiplexer. • What is a Process statement • Compare different Architecture modeling styles. 5 marks questions

A design for my_mux has three architecture blocks: mux2bit, mux8bit, and mux16bit. The my_mux design is part of the my_ics library. Write the library and use statements to use the 8-bit mux architecture in a component declaration of my_mux. • Write a VHDL model for SR Flip Flop. • Design a VHDL code for D Flip Flop • Design a VHDL model for Shift Register 10 marks questions • Design a 6 bit up-down binary counter using minimum number of gates. Aslo write a VHDL code for the counter using a PLA. • Write a structural model of the state machine in VHDL that contains the interconnection of the gates and JK Flip flops. • Write a VHDL model that describes a 16 bit serial-in, serial-out shift register with inputs SI, EN and CK and a serial output SO.

5. Design of Microcomputer
2 marks questions • Draw the block diagram of a microcomputer. • What is ALU and CPU of a microcomputer. 5 marks questions • Write a VHDL code for a Register used in Microcomputer. • Write a VHDL code for Data path in Microcomputer. 10 marks questions • Implement the traffic light controller using a 74163 counter with added logic • Describe the functioning of a microcomputer in detail. • Write a VHDL code for ALU and CPU of a microcomputer.

5. Design with FPGA’s and CPLD’s
2 marks questions • Define PEEL and Gal • Define PLA’s and PAL’s • Give an example of PLD. • What are ROM and RAM. • Define FPGA and CPLD. 5 marks questions • Write a VHDL code for a ROM using a D flip flop. • Write a VHDL code for PLA. 10 marks questions

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Differentiate between FPGA and CPLD Implement the MUX using a FLEX 10K device. How many logic elements are required. The following state table is implemented using a ROM and two D Flip flops (falling edge triggered) Q1Q2 Q+1Q+2 X=0 X=1 Z X=0 0 1 1 X=1 1 1 0

00 01 10 01 10 00 10 00 01 Write VHDL code for the system. Describe in detail FPGA and CPLD.