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**ADSD PROBLEM SHEET 1 KARTHIK.S
**

1A. The diagram shows three gates in which one input (CONTROL) is being used to modify a signal at the other input (DATA). Complete the timing diagram by drawing the waveforms of X, Y and Z. Describe in words the effect each of the gates has on DATA when CONTROL is low and when it is high.

DATA CONTROL

1

C

D

1D C1

Y

&

DATA X CONTROL

≥1

DATA Y CONTROL

=1

Z

5B.

DATA CONTROL

The circuits below are a D-latch and a D-flipflop with their outputs connected to their inputs via an inverter. Draw the waveforms of X and Y assuming that they are both low initially and that C is a uniform square wave. (One of these circuits is a disaster and should never be used)

1

2B. The symbol in a gate generally indicates how many of the inputs need to be high to make the output high. Guess the truth tables of the following gates from their symbols. Explain why any one of them could be considered as a 3-input XOR gate.

A B C 2n+1 P A B C = Q A B C =1 R

1D C C1

X C

1

1D C1

Y

6B.

In the circuit below the propagation delay of the flipflops may vary between 4 and 7 ns while the propagation delay of the gates may vary between 2 and 6 ns. Calculate the minimum and the maximum propagation delays from each of A and C to each of P, Q and R and S.

3A.

The circuits below are a D-latch and a D-flipflop. Complete the timing diagram by drawing the waveforms of X and Y assuming that they are both low initially.

A C

D C 1D C1 X D C 1D C1 Y

1D C1

P

1

Q

1D C1

R

&

S

C D

7C.

4B.

The circuit below forms a ÷2 counter. If the inverter has a propagation delay of 5 ns and the propagation delay, setup time and hold time of the flipflop are 8 ns, 4 ns and 2 ns respectively, calculate the highest clock frequency for reliable operation.

In the circuit below the setup and hold times of the flipflops are 5 ns and 1 ns respectively. The propagation delay of the flipflops may vary between 4 and 7 ns while the propagation delay of the gates may vary between 2 and 6 ns. Calculate the minimum and the maximum propagation delays between C and U. Hence calculate the maximum frequency of the clock, C.

Rev: Oct-06

Digital Electronics II: Problem Sheet 1

Page 1

Identify which of the circuits will not work reliably and determine the maximum clock frequency for each of the others. Complete the timing diagram by drawing the waveform of Q. (a) D C 1D C1 1D C1 (b) D C 1D C1 The springing contacts in switches always bounce when they close and sometimes do so when they open as well. 11C. The signal C is a symmetrical square wave. This contact bounce can last for several milliseconds. If SET and RESET are both high. Design a similar circuit for a 3-contestant game show. 0 1 0 UP DOWN Q S R UP DOWN 1 1 1D C1 The circuit shows a circuit to indicate who pressed their button first in a 2-contestant game show. In the six circuits below the setup and hold times of the flipflops are 5 ns and 1 ns respectively. The dual NOR-gate circuit shown below is called a Set-Reset latch and has the symbol shown at right. The propagation delay of the flipflops may vary between 4 and 7 ns while the propagation delay of the gates may vary between 2 and 6 ns. . Complete the timing diagram by showing the waveforms of Q and N assuming that Q is initially low. You should measure all times from the rising edge of CLOCK.S SET A 1 Q P & & R S ≥1 N SET RESET Q N S R B C 1D C1 & T & U 1D C1 V RESET ≥1 Q SET RESET 10A.S KARTHIK. An SR-latch can be used to debounce switch signals in the following circuit. say which one of these inputs dominates as far as Q is concerned and as far as N is concerned. team A 0 team B 0 clear BUTTONA LIGHTA (c) D 1D C 1D C1 (d) D C 1D C1 S R 1D ≥1 1 C1 1 C1 (e) D 1D C 1D C1 (f) D C BUTTONB 0 1D C1 1D S R LIGHTB 1 1 C1 1 C1 ≥1 9B. Write down the setup and hold inequalities that relate to the second flipflop in each circuit. The SR-latches use the circuit from question 9.KARTHIK. 8C.

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