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The MIPS 5-stage Pipeline (adapted from Sweetman, 1.

Evie’s Fish & Chips shop

Each customer would go to the front of the line and ask for some combination of fried cod, chips, mushy peas, and a cup of tea.

Line got too long, so Evie rented shop next door with more tables, but that didn’t help.

Got a longer counter, and broke up the transaction into stations. Evie: gave a plate with fish Bert: chips Wasif: mushy peas Lorena: tea/cash


Potential problems:
Some don’t want peas (just wait there, then proceed to next stage)

Alex likes to count his change before leaving since he doesn’t trust anyone. memory caches are used. This is a resource conflict and slows down the pipeline. Ahmed first. The MIPS Pipeline Description: IF: (instruction fetch) gets the next instruction from the instruction cache (Icache) RD: (read registers) fetches the contents of the CPU registers whose numbers are in the two possible source register fields of the instruction. Every stage should take the same amount of time.If Wasif takes longer than the others. This is a dependency (a. There are separate instruction and data caches so it can fetch an instruction and read/write a memory variable simultaneously. Ahmed & Sunghee always arrive together. a pipeline bubble) The need for Caching A CPU can add 2 64-bit numbers about 10 times faster than it can fetch data from memory (potential resource conflict). To solve this.a.k. ALU: (arithmetic/logic unit) performs an arithmetical or logical operation in one clock cycle (divide & multiply are an exception to this) . pipeline slows down. and share their lunches. Sunghee won’t get chips unless Ahmed orders tea. so Sunghee waits at Bert’s stage until Ahmed finishes.

. so they can be fetched in constant time (32 bits) Instructions cannot operate directly on memory variables. On average 3 out of 4 instructions do nothing in this stage. WB: (write back) stores the resulting value from the operation back to the register file. Implications All instructions must be same length.MEM: read/write memory variables in the data cache (D-cache). This gives rise to what is called the load/store architecture. but only on registers.