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The objective of this project is to design an embedded system

which can control appliances remotely. This project is designed

to study the basic implementation of DTMF (Dual Tone Multi


The DTMF signal is composed of high frequencies & low

frequencies. Each key is assigned a low frequency and a high

frequency. When a particular key is pressed, the frequencies

those are specific to that particular key are transmitted.

Therefore, no two keys will have a same set of low & high


We use DTMF encoder & decoder to develop this switch. The

DTMF encoder transmits the set of two frequencies related to a

particular key and the decoder on receiving the set, converts it

to related digital signals. These digital signals are fed to

Microcontroller, and can be used to control appliances or nodes

remotely. The embedded software for the controller is

implemented using ‘C’ language.

The system is designed and developed using 8051 µController.


Telephone Controlled Switch or DTMF based remote switch implies control of

devices at a remote location via circuit interfaced to the remote telephone
line/device by dialing specific DTMF (dual tune multi frequency) digits from a
local telephone. Using this system the user can access any load from a remote
location. Each load will be given a code number. All he has to do is dial the
corresponding code through a local phone.

This system can selectively turn on or off multiple loads one at a time or switch
off all the loads simultaneously. It also provides you feedback when the circuit
is in energized state and also sends an acknowledgement indicating action with
respect to the switching on of each load and switching off of all loads
(together). This is a micro controller aided system where a ring detector, auto
lifter and DTMF decoder work together to place a call and a relay driver
connects the required load. This makes the task of the various operators easy as
they can sit anywhere and control the status of the various loads.
In the existing system if an operator in and industry has to control a certain
load there is no other method than being physically present at the site of the
load. If he has to switch off a system after a particular period he will have to
wait till the completion of the operation. But our project titled "Telephone
controlled switch" rectifies this disadvantage of conventional systems. This
system as its name suggests help the user to control the status of various loads
from any remote location through a telephone connection.

As mentioned this system implies control of devices at a remote location via

circuit interfaced to the remote telephone line/device by dialing specific DTMF
(dual tune multi frequency) digits from a local telephone. For this each of the
loads that the operator intends to control is given a code number and is
connected to the telephone line through relay drivers and micro controller. So
when the user dials the respective codes the corresponding loads can be
accessed. Then its status can be controlled using some other code. All this is
made possible by programming the micro controller.

This project telephone controlled load activator has the following features.

1. It can control multiple load (on/off/status of each load)






An embedded system is a special-purpose computer system

designed to perform one or a few dedicated functions,
sometimes with real-time computing constraints. It is usually
embedded as part of a complete device including hardware
and mechanical parts. In contrast, a general-purpose
computer, such as a personal computer, can do many different
tasks depending on programming. Embedded systems have
become very important today as they control many of the
common devices we use.
Since the embedded system is dedicated to specific
tasks, design engineers can optimize it, reducing the size and
cost of the product, or increasing the reliability and
performance. Some embedded systems are mass-produced,
benefiting from economies of scale.

Physically, embedded systems range from portable

devices such as digital watches and MP3 players, to large
stationary installations like traffic lights, factory controllers, or
the systems controlling nuclear power plants. Complexity
varies from low, with a single microcontroller chip, to very high
with multiple units, peripherals and networks mounted inside a
large chassis or enclosure.

In general, "embedded system" is not an exactly defined

term, as many systems have some element of
programmability. For example, Handheld computers share
some elements with embedded systems — such as the
operating systems and microprocessors which power them —
but are not truly embedded systems, because they allow
different applications to be loaded and peripherals to be

An embedded system is some combination of computer

hardware and software, either fixed in capability or
programmable, that is specifically designed for a particular
kind of application device. Industrial machines, automobiles,
medical equipment, cameras, household appliances, airplanes,
vending machines, and toys (as well as the more obvious
cellular phone and PDA) are among the myriad possible hosts
of an embedded system. Embedded systems that are
programmable are provided with a programming interface, and
embedded systems programming is a specialized occupation.

Certain operating systems or language platforms are

tailored for the embedded market, such as Embedded Java and
Windows XP Embedded. However, some low-end consumer
products use very inexpensive microprocessors and limited
storage, with the application and operating system both part of
a single program. The program is written permanently into the
system's memory in this case, rather than being loaded into
RAM (random access memory), as programs on a personal
computer are.


We are living in the Embedded World. You are
surrounded with many embedded products and your daily life
largely depends on the proper functioning of these gadgets.
Television, Radio, CD player of your living room, Washing
Machine or Microwave Oven in your kitchen, Card readers,
Access Controllers, Palm devices of your work space enable
you to do many of your tasks very effectively. Apart from all
these, many controllers embedded in your car take care of car
operations between the bumpers and most of the times you
tend to ignore all these controllers.

In recent days, you are showered with variety of

information about these embedded controllers in many places.
All kinds of magazines and journals regularly dish out details
about latest technologies, new devices; fast applications which
make you believe that your basic survival is controlled by
these embedded products. Now you can agree to the fact that
these embedded products have successfully invaded into our
world. You must be wondering about these embedded
controllers or systems. What is this Embedded System?

The computer you use to compose your mails, or create a

document or analyze the database is known as the standard
desktop computer. These desktop computers are
manufactured to serve many purposes and applications.
You need to install the relevant software to get the
required processing facility. So, these desktop computers can
do many things. In contrast, embedded controllers carryout a
specific work for which they are designed. Most of the time,
engineers design these embedded controllers with a specific
goal in mind. So these controllers cannot be used in any other
Theoretically, an embedded controller is a combination of a
piece of microprocessor based hardware and the suitable
software to undertake a specific task.
These days designers have many choices in
microprocessors/microcontrollers. Especially, in 8 bit and 32
bit, the available variety really may overwhelm even an
experienced designer. Selecting a right microprocessor may
turn out as a most difficult first step and it is getting
complicated as new devices continue to pop-up very often.

In the 8 bit segment, the most popular and used

architecture is Intel's 8031. Market acceptance of this
particular family has driven many semiconductor
manufacturers to develop something new based on this
particular architecture. Even after 25 years of existence,
semiconductor manufacturers still come out with some kind of
device using this 8031 core.
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What is the difference between a Microprocessor and

Microcontroller? By microprocessor is meant the general
purpose Microprocessors such as Intel's X86 family (8086,
80286, 80386, 80486, and the Pentium) or Motorola's 680X0
family (68000, 68010, 68020, 68030, 68040, etc). These
microprocessors contain no RAM, no ROM, and no I/O ports on
the chip itself. For this reason, they are commonly referred to
as general-purpose Microprocessors.

A system designer using a general-purpose

microprocessor such as the Pentium or the 68040 must add
RAM, ROM, I/O ports, and timers externally to make them
functional. Although the addition of external RAM, ROM, and
I/O ports makes these systems bulkier and much more
expensive, they have the advantage of versatility such that the
designer can decide on the amount of RAM, ROM and I/O ports
needed to fit the task at hand. This is not the case with

A Microcontroller has a CPU (a microprocessor) in

addition to a fixed amount of RAM, ROM, I/O ports, and a timer
all on a single chip. In other words, the processor, the RAM,
ROM, I/O ports and the timer are all embedded together on one
chip; therefore, the designer cannot add any external memory,
I/O ports, or timer to it. The fixed amount of on-chip ROM, RAM,
and number of I/O ports in Microcontrollers makes them ideal
for many applications in which cost and space are critical.
In many applications, for example a TV remote control,
there is no need for the computing power of a 486 or even an
8086 microprocessor. These applications most often require
some I/O operations to read signals and turn on and off certain

In the Literature discussing microprocessors, we often

see the term Embedded System. Microprocessors and
Microcontrollers are widely used in embedded system
products. An embedded system product uses a microprocessor
(or Microcontroller) to do one task only. A printer is an example
of embedded system since the processor inside it performs
one task only; namely getting the data and printing it. Contrast
this with a Pentium based PC. A PC can be used for any
number of applications such as word processor, print-server,
bank teller terminal, Video game, network server, or Internet
terminal. Software for a variety of applications can be loaded
and run. Of course the reason a pc can perform myriad tasks is
that it has RAM memory and an operating system that loads
the application software into RAM memory and lets the CPU
run it.

In an Embedded system, there is only one application

software that is typically burned into ROM. An x86 PC contains
or is connected to various embedded products such as
keyboard, printer, modem, disk controller, sound card, CD-ROM
drives, mouse, and so on. Each one of these peripherals has a
Microcontroller inside it that performs only one task. For
example, inside every mouse there is a Microcontroller to
perform the task of finding the mouse position and sending it
to the PC. Table 1-1 lists some embedded products.

The generic 8051 architecture supports a Harvard

architecture, which contains two separate buses for both
program and data. So, it has two distinctive memory
spaces of 64K X 8 size for both programmed and data. It is
based on an 8 bit central processing unit with an 8 bit
Accumulator and another 8 bit B register as main
processing blocks. Other portions of the architecture
include few 8 bit and 16 bit registers and 8 bit memory

Each 8051 device has some amount of data RAM

built in the device for internal processing. This area is
used for stack operations and temporary storage of data.
This bus architecture is supported with on-chip
peripheral functions like I/O ports, timers/counters,
versatile serial communication port. So it is clear that
this 8051 architecture was designed to cater many real
time embedded needs.


 Optimized 8 bit CPU for control applications and

extensive Boolean processing capabilities.

 64K Program Memory address space.

 64K Data Memory address space.

 128 bytes of on chip Data Memory.

 32 Bi-directional and individually addressable I/O

 Two 16 bit timer/counters.

 Full Duplex UART.

 6-source / 5-vector interrupt structure with priority


 On chip clock oscillator.

Now we may be wondering about the non-mentioning of

memory space meant for the program storage, the most
important part of any embedded controller. Originally
this 8051 architecture was introduced with on-chip, ‘one
time programmable’ version of Program Memory of size
4K X 8. Intel delivered all these microcontrollers (8051)
with user’s program fused inside the device. The
memory portion was mapped at the lower end of the
Program Memory area. But, after getting devices,
customers couldn’t change any thing in their program
code, which was already made available inside during
device fabrication.

Figure 4.1 - Block Diagram of the 8051 Core

So, very soon Intel introduced the 8051 devices with

re-programmable type of Program Memory using built-in
EPROM of size 4K X 8. Like a regular EPROM, this memory
can be re-programmed many times. Later on Intel started
manufacturing these 8031 devices without any on chip
Program Memory.
ALE/PROG: Address Latch Enable output pulse for latching
the low byte of the address during accesses to external
memory. ALE is emitted at a constant rate of 1/6 of the
oscillator frequency, for external timing or clocking purposes,
even when there are no accesses to external memory.
(However, one ALE pulse is skipped during each access to
external Data Memory.) This pin is also the program pulse
input (PROG) during EPROM programming.
PSEN : Program Store Enable is the read strobe to external
Program Memory. When the device is executing out of external
Program Memory, PSEN is activated twice each machine cycle
(except that two PSEN activations are skipped during accesses
to external Data Memory). PSEN is not activated when the
device is executing out of internal Program Memory.
EA/VPP: When EA is held high the CPU executes out of
internal Program Memory (unless the Program Counter
exceeds 0FFFH in the 80C51). Holding EA low forces the CPU to
execute out of external memory regardless of the Program
Counter value. In the 80C31, EA must be externally wired low.
In the EPROM devices, this pin also receives the programming
supply voltage (VPP) during EPROM programming.
XTAL1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.
The 8051’s I/O port structure is extremely versatile and
flexible. The device has 32 I/O pins configured as four
eight bit parallel ports (P0, P1, P2 and P3). Each pin can
be used as an input or as an output under the software
control. These I/O pins can be accessed directly by
memory instructions during program execution to get
required flexibility.
These port lines can be operated in different modes
and all the pins can be made to do many different tasks
apart from their regular I/O function executions.
Instructions, which access external memory, use port P0
as a multiplexed address/data bus. At the beginning of
an external memory cycle, low order 8 bits of the
address bus are output on P0. The same pins transfer
data byte at the later stage of the instruction execution.

Also, any instruction that accesses external Program

Memory will output the higher order byte on P2 during
read cycle. Remaining ports, P1 and P3 are available for
standard I/O functions. But all the 8 lines of P3 support
special functions: Two external interrupt lines, two
counter inputs, serial port’s two data lines and two timing
control strobe lines are designed to use P3 port lines.
When you don’t use these special functions, you can use
corresponding port lines as a standard I/O. Even within a
single port, I/O operations may be combined in many ways.
Different pins can be configured as input or outputs
independent of each other or the same pin can be used
as an input or as output at different times. You can
comfortably combine I/O operations and special
operations for Port 3 lines.

All the Port 3 pins are multifunctional. They are not only
port pins, but also serve the functions of various special
features as listed below:
Port Pin Alternate Function
P3.0 RxD (serial input port)
P3.1 TxD (serial output port)
The alternate functions can only be activated if the
corresponding bit latch in the port SFR contains a 1. Otherwise
the port pin remains at 0.All 80C51 devices have separate
address spaces for program and data memory, as shown in
Figures 1 and 2. The logical separation of program and data
memory allows the data memory to be accessed by 8-bit
addresses, which can be quickly stored and manipulated by an
8-bit CPU. Nevertheless, 16-bit data memory addresses can
also be generated through the DPTR register.

Program memory (ROM, EPROM) can only be read, not

written to. There can be up to 64k bytes of program memory.
In the 80C51, the lowest 4k bytes of program are on-chip. In
the ROM less versions, all program memory is external. The
read strobe for external program memory is the PSEN
(program store enable). Data Memory (RAM) occupies a
separate address space from Program Memory. In the 80C51,
the lowest 128 bytes of data memory are on-chip. Up to 64k
bytes of external RAM can be addressed in the external Data
Memory space. In the ROM less version, the lowest 128 bytes
are on-chip. The CPU generates read and write signals, RD and
WR, as needed during external Data Memory accesses.

External Program Memory and external Data Memory

may be combined if desired by applying the RD and PSEN
signals to the inputs of an AND gate and using the output of
the gate as the read strobe to the external Program/Data
A number of 8052 registers can be considered "basic."
Very little can be done without them and a detailed
explanation of each one is warranted to make sure the reader
understands these registers before getting into more
complicated areas of development.

The Accumulator: If you've worked with any other assembly

language you will be familiar with the concept of an
accumulator register.

The Accumulator, as its name suggests, is used as a

general register to accumulate the results of a large number of
instructions. It can hold an 8-bit (1-byte) value and is the most
versatile register the 8052 has due to the sheer number of
instructions that make use of the accumulator. More than half
of the 8052's 255 instructions manipulate or use the
Accumulator in some way. For example, if you want to add the
number 10 and 20, the resulting 30 will be stored in the
Accumulator. Once you have a value in the Accumulator you
may continue processing the value or you may store it in
another register or in memory.
The "R" Registers: The "R" registers are sets of eight
registers that are named R0, R1, through R7. These registers
are used as auxiliary registers in many operations. To continue
with the above example, perhaps you are adding 10 and 20.
The original number 10 may be stored in the Accumulator
whereas the value 20 may be stored in, say, register R4. To
process the addition you would execute the command:
After executing this instruction the Accumulator will contain
the value 30. You may think of the "R" registers as very
important auxiliary, or "helper", registers. The Accumulator
alone would not be very useful if it were not for these "R"
The "R" registers are also used to store values temporarily. For
example, let’s say you want to add the values in R1 and R2
together and then subtract the values of R3 and R4. One way
to do this would be:
MOV A, R3 ; Move the value of R3 to accumulator
ADD A, R4 ; add the value of R4
MOV R5, A ; Store the result in R5
MOV A, R1 ; Move the value of R1 to Acc
ADD A, R2 ; add the value of R2 with A
SUBB A, R5 ; Subtract the R5 (which has R3+R4)
As you can see, we used R5 to temporarily hold the sum of R3
and R4. Of course, this isn't the most efficient way to calculate
(R1+R2) - (R3 +R4) but it does illustrate the use of the "R"
registers as a way to store values temporarily.
As mentioned earlier, there are four sets of "R" registers-
register bank 0, 1, 2, and 3. When the 8052 is first powered up,
register bank 0 (addresses 00h through 07h) is used by
default. In this case, for example, R4 is the same as Internal
RAM address 04h. However, your program may instruct the
8052 to use one of the alternate register banks; i.e., register
banks 1, 2, or 3. In this case, R4 will no longer be the same as
Internal RAM address 04h. For example, if your program
instructs the 8052 to use register bank 1, register R4 will now
be synonymous with Internal RAM address 0Ch. If you select
register bank 2, R4 is synonymous with 14h, and if you select
register bank 3 it is synonymous with address 1Ch.
The concept of register banks adds a great level of
flexibility to the 8052, especially when dealing with interrupts
(we'll talk about interrupts later). However, always remember
that the register banks really reside in the first 32 bytes of
Internal RAM.

The B Register The "B" register is very similar to the

Accumulator in the sense that it may hold an 8-bit (1-byte)
value. The "B" register is only used implicitly by two 8052
instructions: MUL AB and DIV AB. Thus, if you want to quickly
and easily multiply or divide A by another number, you may
store the other number in "B" and make use of these two
Aside from the MUL and DIV instructions, the "B" register
are often used as yet another temporary storage register much
like a ninth "R" register.

The Program Counter The Program Counter (PC) is a 2-

byte address that tells the 8052 where the next instruction to
execute is found in memory. When the 8052 is initialized PC
always starts at 0000h and is incremented each time an
instruction is executed. It is important to note that PC isn't
always incremented by one. Since some instructions are 2 or 3
bytes in length the PC will be incremented by 2 or 3 in these

The Program Counter is special in that there is no way to

directly modify its value. That is to say, you can't do something
like PC=2430h. On the other hand, if you execute LJMP 2430h
you've effectively accomplished the same thing.
It is also interesting to note that while you may change
the value of PC (by executing a jump instruction, etc.) there is
no way to read the value of PC. That is to say, there is no way
to ask the 8052 "What address are you about to execute?" As
it turns out, this is not completely true: There is one trick that
may be used to determine the current value of PC. This trick
will be covered in a later chapter.

The Data Pointer: The Data Pointer (DPTR) is the 8052ís only
user-accessible 16-bit (2-byte) register. The Accumulator, "R"
registers, and "B" register are all 1-byte values. The PC just
described is a 16-bit value but isn't directly user-accessible as
a working register.

DPTR, as the name suggests, is used to point to data. It is

used by a number of commands that allow the 8052 to access
external memory. When the 8052 accesses external memory it
accesses the memory at the address indicated by DPTR.

While DPTR is most often used to point to data in external

memory or code memory, many developers take advantage of
the fact that it's the only true 16-bit register available. It is
often used to store 2-byte values that have nothing to do with
memory locations.

The Stack Pointer: The Stack Pointer, like all registers except
DPTR and PC, may hold an 8-bit (1-byte) value. The Stack
Pointer is used to indicate where the next value to be removed
from the stack should be taken from.
When you push a value onto the stack, the 8052 first
increments the value of SP and then stores the value at the
resulting memory location. When you pop a value off the stack,
the 8052 returns the value from the memory location indicated
by SP and then decrements the value of SP.

This order of operation is important. When the 8052 is

initialized SP will be initialized to 07h. If you immediately push
a value onto the stack, the value will be stored in Internal RAM
address 08h. This makes sense taking into account what was
mentioned two paragraphs above: First the 8051 will
increment the value of SP (from 07h to 08h) and then will store
the pushed value at that memory address (08h).

The addressing modes in the 80C51 instruction set are as

Direct Addressing: In direct addressing the operand is

specified by an 8-bit address field in the instruction. Only
internal Data RAM and SFRs can be directly addressed.

Indirect Addressing: In indirect addressing the instruction

specifies a register which contains the address of the operand.
Both internal and external RAM can be indirectly addressed.
The address register for 8-bit addresses can be R0 or R1 of the
selected bank, or the Stack Pointer. The address register for
16-bit addresses can only be the 16-bit “data pointer” register,

Register Instructions The register banks, containing

registers R0 through R7, can be accessed by certain
instructions which carry a 3-bit register specification within the
opcode of the instruction. Instructions that access the registers
this way are code efficient, since this mode eliminates an
address byte. When the instruction is executed, one of the
eight registers in the selected bank is accessed. One of four
banks is selected at execution time by the two bank select bits
in the PSW.

Register-Specific Instructions Some instructions are

specific to a certain register. For example, some instructions
always operate on the Accumulator, or Data Pointer, etc., so no
address byte is needed to point to it. The opcode itself does
that. Instructions that refer to the Accumulator as A assemble
as accumulator specific opcodes.

Immediate Constants
The value of a constant can follow the opcode in Program
Memory. For example,
MOV A, #100
loads the Accumulator with the decimal number 100. The same
number could be specified in hex digits as 64H.

Indexed Addressing
Only program Memory can be accessed with indexed
addressing, and it can only be read. This addressing mode is
intended for reading look-up tables in Program Memory A 16-
bit base register (either DPTR or the Program Counter) points
to the base of the table, and the Accumulator is set up with the
table entry number. The address of the table entry in Program
Memory is formed by adding the Accumulator data to the base
pointer. Another type of indexed addressing is used in the
“case jump” instruction. In this case the destination address of
a jump instruction is computed as the sum of the base pointer
and the Accumulator data.


The CPU is the brain of the microcontrollers reading user’s
programs and executing the expected task as per
instructions stored there in. Its primary elements are an
8 bit Arithmetic Logic Unit (ALU ) , Accumulator (Acc ) ,
few more 8 bit registers , B register, Stack Pointer (SP ) ,
Program Status Word (PSW) and 16 bit registers, Program
Counter (PC) and Data Pointer Register (DPTR).

The ALU (Acc) performs arithmetic and logic

functions on 8 bit input variables. Arithmetic operations
include basic addition, subtraction, and multiplication and
division. Logical operations are AND, OR, Exclusive OR as
well as rotate, clear, complement and etc. Apart from all
the above, ALU is responsible in conditional branching
decisions, and provides a temporary place in data
transfer operations within the device.

B-register is mainly used in multiply and divides

operations. During execution, B register either keeps one
of the two inputs or then retains a portion of the result.
For other instructions, it can be used as another general
purpose register.

Program Status Word (PSW) keeps the current status

of the ALU in different bits. Stack Pointer (SP) is an 8 bit
register. This pointer keeps track of memory space where
the important register information is stored when the
program flow gets into executing a subroutine. The
stack portion may be placed in any where in the on-chip
RAM. But normally SP is initialized to 07H after a device
reset and grows up from the location 08H. The Stack
Pointer is automatically incremented or decremented for
all PUSH or POP instructions and for all subroutine calls
and returns.

Program Counter (PC) is the 16 bit register giving

address of next instruction to be executed during
program execution and it always points to the Program
Memory space. Data Pointer (DPTR) is another 16 bit
addressing register that can be used to fetch any 8 bit
data from the data memory space. When it is not being
used for this purpose, it can be used as two eight bit


8051 has two 16 bit Timers/Counters capable of working

in different modes. Each consists of a ‘High’ byte and a
‘Low’ byte which can be accessed under software. There
is a mode control register and a control register to
configure these timers/counters in number of ways.

These timers can be used to measure time

intervals, determine pulse widths or initiate events with
one microsecond resolution up to a maximum of 65
millisecond (corresponding to 65, 536 counts). Use
software to get longer delays. Working as counter, they
can accumulate occurrences of external events (from DC
to 500 KHz) with 16 bit precision.

Each 8051 microcomputer contains a high speed full

duplex (means you can simultaneously use the same port
for both transmitting and receiving purposes) serial port
which is software configurable in 4 basic modes: 8 bit
UART; 9 bit UART; inter processor Communications link
or as shift register I/O expander.

For the standard serial communication facility, 8051 can

be programmed for UART operations and can be
connected with regular personal computers, teletype
writers, modem at data rates between 122 bauds and 31
kilo bauds. Getting this facility is made very simple using
simple routines with option to elect even or odd parity.
You can also establish a kind of Inter processor
communication facility among many microcomputers in a
distributed environment with automatic recognition of
address/data. Apart from all above, you can also get
super fast I/O lines using low cost simple TTL or CMOS
shift registers.

A microprocessor as a term has come to be known is a
general-purpose digital computer central processing unit.
Although popularly known as a computer on a chip.
The microprocessor contains arithmetic and logic unit,
program counter, Stack pointer, some working registers, clock
timing circuit and interrupt circuits.

To make a complete computer one must add memory

usually RAM & ROM, memory decoders, an oscillator and
number of I/O devices such as parallel and serial data ports in
addition special purpose devices such as interrupt handlers
and counters.

The key term in describing the design of the

microprocessor is “general purpose”. The hardware design of a
microprocessor CPU is arranged so that a small or very large
system can be configured around the CPU as the application

The prime use of microprocessor is to read data, perform

extensive calculations on that data and store those
calculations in a mass storage device. The programs used by
the microprocessor are stored in the mass storage device and
loaded in the RAM as the user directs. A few microprocessor
programs are stored in the ROM. The ROM based programs are
primarily are small fixed programs that operate on peripherals
and other fixed device that are connected to the system


Micro controller is a true computer on a chip the design

incorporates all of the features found in a microprocessor
CPU: arithmetic and logic unit, stack pointer, program
counter and registers. It has also had added additional
features like RAM, ROM, serial I/O, counters and clock circuit.
Like the microprocessor, a microcontroller is a general
purpose device, but one that is meant to read data, perform
limited calculations on that data and control it’s environment
based on those calculations. The prime use of a
microcontroller is to control the operation of a machine using
a fixed program that is stored in ROM and that does not
change over the lifetime of the system.
The design approach of a microcontroller uses a more
limited set of single byte and double byte instructions that
are used to move code and data from internal memory to
ALU. Many instructions are coupled with pins on the IC
package; the pins are capable of having several different
functions depending on the wishes of the programmer.

The microcontroller is concerned with getting the data

from and on to its own pins; the architecture and instruction
set are optimized to handle data in bit and byte size.

1. The first and foremost criterion for choosing a

microcontroller is that it must meet task at hands
efficiently and cost effectively. In analyzing the needs of
a microcontroller based project we must first see
whether it is an 8-bit, 16-bit or 32-bit microcontroller and
how best it can handle the computing needs of the task
most effectively. The other considerations in this
category are:
(a) Speed: The highest speed that the microcontroller
(b) Packaging: Is it 40-pin DIP or QPF or some other
packaging format?
This is important in terms of space, assembling
and prototyping the
End product.
(c) Power Consumption: This is especially critical for
(d) The amount of RAM and ROM on chip
(e) The number of I/O pins and timers on the chip.
(f) Cost per unit: This is important in terms of final
product in which a microcontroller is used.
2. The second criteria in choosing a microcontroller are how
easy it is to develop products around it. Key
considerations include the availability of an assembler,
debugger, a code efficient ‘C’ language compiler,
emulator, technical support and both in house and
outside expertise. In many cases third party vendor
support for chip is required.

3. The third criteria in choosing a microcontroller is it

readily available in needed quantities both now and in
future. For some designers this is even more important
than first two criteria’s. Currently, of leading 8–bit
microcontrollers, the 89C51 family has the largest
number of diversified (multiple source) suppliers. By
suppliers meant a producer besides the originator of
microcontroller in the case of the 89C51, which was
originated by Intel, several companies are also currently
producing the 89C51. Viz: INTEL, ATMEL, These
companies include PHILIPS, SIEMENS, and DALLAS-
SEMICONDUCTOR. It should be noted that Motorola, Zilog
and Microchip Technologies have all dedicated massive
resource as to ensure wide and timely availability of their
product since their product is stable, mature and single
sourced. In recent years they also have begun to sell the
ASIC library cell of the microcontroller.
The 89C51/89C52/89C54/89C58 contains a non-volatile FLASH
program memory that is parallel programmable. All three
families are Single-Chip 8-bit Microcontrollers manufactured in
advanced CMOS process and are derivatives of the 80C51
microcontroller family. All the devices have the same
instruction set as the 80C51.

• 80C51 Central Processing Unit.
• On-chip FLASH Program Memory
• Speed up to 33 MHz
• Fully static operation
• RAM expandable externally up to 64 Kbytes
• 4 interrupt priority levels
• 6 interrupt sources
• Four 8-bit I/O ports
• Full-duplex enhanced UART
 Framing error detection
 Automatic address recognition
• Three 16-bit timers/counters T0, T1 (standard 80C51) and
additional T2 (capture and compare)
• Power control modes
 Clock can be stopped and resumed
 Idle mode
 Power down mode
• Programmable clock out
• Second DPTR register
• Asynchronous port reset
• Low EMI (inhibit ALE)
• Wake up from power down by an external interrupt


VSS 20 I Ground: 0 V reference.
VCC 40 I Power Supply: This is the power supply voltage
for normal, idle, and power-down operation.
P0.0– 39– I/O Port 0: Port 0 is an open-drain, bidirectional I/O
0.7 32 port. Port 0 pins that have 1s written to them
float and can be used as high-impedance
inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to
external program and data memory. In this
application, it uses strong internal pull-ups
when emitting 1s.
P1.0– 1–8 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port
P1.7 with internal pull-ups. Port 1 pins that have 1s
written to them are pulled high by the internal
pull-ups and can be used as inputs. As inputs,
port 1 pins that are externally pulled low will
source current because of the internal pull-
1 I/O ups. Alternate function for Port 1:
T2 (P1.0): Timer/Counter2 external count
0 I input/clockout (see Programmable Clock-
T2EX (P1.1): Timer/Counter2
reload/capture/direction control.
P2.0– 21– Port 2: Port 2 is an 8-bit bidirectional I/O port
P2.7 28 with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal
pull-ups and can be used as inputs. As inputs,
port 2 pins that are externally being pulled low
will source current because of the internal pull-
ups. (See DC Electrical Characteristics: IIL).
Port 2 emits the high-order address byte
during fetches from external program memory
and during accesses to external data memory
that uses 16-bit addresses (MOVX @DPTR). In
this application, it uses strong internal pull-ups
when emitting 1s. During accesses to external
data memory that uses 8-bit addresses (MOV
@Ri); port 2 emits the contents of the P2
special function register.
P3.0– 10– I/O Port 3: Port 3 is an 8-bit bidirectional I/O port
P3.7 17 with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal
pull-ups and can be used as inputs. As inputs,
port 3 pins that are externally being pulled low
will source current because of the pull-ups.
(See DC Electrical Characteristics: IIL). Port 3
I also serves the special features of the
10 O 89C51/89C52/89C54/89C58, as listed below:
11 I RxD (P3.0): Serial input port
12 I TxD (P3.1): Serial output port
13 I INT0 (P3.2): External interrupt
14 I INT1 (P3.3): External interrupt
15 O T0 (P3.4): Timer 0 external input
16 O T1 (P3.5): Timer 1 external input
17 WR (P3.6): External data memory write
RD (P3.7): External data memory read
RST 9 I Reset: A high on this pin for two machine
cycles while the oscillator is running, resets
the device. An internal diffused resistor to VSS
permits a power-on reset using only an
external capacitor to VCC.
ALE 30 O Address Latch Enable: Output pulse for
latching the low byte of the address during an
access to external memory. In normal
operation, ALE is emitted at a constant rate of
1/6 the oscillator frequency, and can be used
for external timing or clocking. Note that one
ALE pulse is skipped during each access to
external data memory. ALE can be disabled by
setting SFR auxiliary.0. With this bit set, ALE
will be active only during a MOVX instruction.
PSEN 29 O Program Store Enable: The read strobe to
external program memory. When executing
code from the external program memory,
PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped
during each access to external data memory.
PSEN is not activated during fetches from
internal program memory.
EA/VPP 31 I External Access Enable/Programming Supply
Voltage: EA must be externally held low to
enable the device to fetch code from external
program memory locations 0000H to the
maximum internal memory boundary. If EA is
held high, the device executes from internal
program memory unless the program counter
contains an address greater than 0FFFH for 4 k
devices, 1FFFH for 8 k devices, 3FFFH for 16 k
devices, and 7FFFH for 32 k devices.
The value on the EA pin is latched when RST is
released and any subsequent changes have no
effect. This pin also receives the 5V/12V
(±10%) programming supply voltage (VPP)
during FLASH programming.
XTAL1 19 I Crystal 1: Input to the inverting oscillator
amplifier and input to the internal clock
generator circuits.
XTAL2 18 O Crystal 2: Output from the inverting oscillator

NOTE: To avoid “latch-up” effect at power-on, the voltage on

any pin (other than VPP) at any time must not be higher than VCC
+ 0.5 V or VSS – 0.5 V, respectively.
General Description

The 89C51/89C52/89C54/89C58 FLASH reliably stores memory

contents even after 10,000 erase and program cycles. The cell
is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced tunnel
oxide processing and low internal electric fields for erase and
programming operations produces reliable cycling.

• FLASH EPROM internal program memory with Chip Erase.
• Up to 64 k byte external program memory if the internal
program memory is disabled (EA = 0).
• Programmable security bits.
• 10,000 minimum erase/program cycles for each byte.
• 10 year minimum data retention.
• Programming support available from many popular

XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an
on-chip oscillator. To drive the device from an external clock
source, XTAL1 should be driven while XTAL2 is left
unconnected. There are no requirements on the duty cycle of
the external clock signal, because the input to the internal
clock circuitry is through a divide-by-two flip-flop. However,
minimum and maximum high and low times specified in the
data sheet must be observed.
A reset is accomplished by holding the RST pin high for at least
two machine cycles (24 oscillator periods), while the oscillator
is running. To insure a good power-on reset, the RST pin must
be high long enough to allow the oscillator time to start up
(normally a few milliseconds) plus two machine cycles. At
power-on, the voltage on VCC and RST must come up at the
same time for a proper start-up. Ports 1, 2, and 3 will
asynchronously be driven to their reset condition when a
voltage above VIH1 (min.) is applied to RST. The value on the
EA pin is latched when RST is deasserted and has no further


Stop Clock Mode
The static design enables the clock speed to be reduced down
to 0 MHz (stopped). When the oscillator is stopped, the RAM
and Special Function Registers retain their values. This mode
allows step-by-step utilization and permits reduced system
power consumption by lowering the clock frequency down to
any value. For lowest power consumption the Power Down
mode is suggested.

Idle Mode
In the idle mode (see Table 2), the CPU puts itself to sleep
while all of the on-chip peripherals stay active. The instruction
to invoke the idle mode is the last instruction executed in the
normal operating mode before the idle mode is activated. The
CPU contents, the on-chip RAM, and all of the special function
registers remain intact during this mode. The idle mode can be
terminated either by any enabled interrupt (at which time the
process is picked up at the interrupt service routine and
continued), or by a hardware reset which starts the processor
in the same manner as a power-on reset.

Power-Down Mode
To save even more power, a Power Down mode (see Table 2)
can be invoked by software. In this mode, the oscillator is
stopped and the instruction that invoked Power Down is the
last instruction executed. The on-chip RAM and Special
Function Registers retain their values down to 2.0 V and care
must be taken to return VCC to the minimum specified
operating voltages before the Power Down Mode is terminated.
Either a hardware reset or external interrupt can be used to
exit from Power Down. Reset redefines all the SFRs but does
not change the on-chip RAM. An external interrupt allows both
the SFRs and the on-chip RAM to retain their values. To
properly terminate Power Down the reset or external interrupt
should not be executed before VCC is restored to its normal
operating level and must be held active long enough for the
oscillator to restart and stabilize (normally less than 10ms).
With an external interrupt, INT0 and INT1 must be enabled and
configured as level-sensitive. Holding the pin low restarts the
oscillator but bringing the pin back high completes the exit.
Once the interrupt is serviced, the next instruction to be
executed after RETI will be the one following the instruction
that put the device into Power Down.
Design Consideration
When the idle mode is terminated by a hardware reset, the
device normally resumes program execution, from where it left
off, up to two machine cycles before the internal reset
algorithm takes control. On-chip hardware inhibits access to
internal RAM in this event, but access to the port pins is not
inhibited. To eliminate the possibility of an unexpected write
when Idle is terminated by reset, the instruction following the
one that invokes Idle should not be one that writes to a port
pin or to external memory.

The ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems without the device having to be
removed from the circuit. The ONCE Mode is invoked by:
1. Pull ALE low while the device is in reset and PSEN is high;
2. Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into a
float state, and the other port pins and ALE and PSEN are
weakly pulled high. The oscillator circuit remains active. While
the device is in this mode, an emulator or test CPU can be
used to drive the circuit.
Normal operation is restored when a normal reset is applied.

Programmable Clock-Out
A 50% duty cycle clock can be programmed to come out on
P1.0. This pin, besides being a regular I/O pin, has two
alternate functions. It can be programmed:
1. to input the external clock for Timer/Counter 2, or
2. to output a 50% duty cycle clock ranging from 61Hz to
4MHz at a 16MHz operating frequency.
To configure the Timer/Counter 2 as a clock generator, bit C/T2
(in T2CON) must be cleared and bit T20E in T2MOD must be
set. Bit TR2 (T2CON.2) also must be set to start the timer. The
Clock-Out frequency depends on the oscillator frequency and
the reload value of Timer 2 capture registers (RCAP2H,
RCAP2L) as shown in this equation:

Oscillator Frequency

4x (65536 - RCAP2H, RCAP2L)

Where (RCAP2H, RCAP2L) = the content of RCAP2H and

taken as a 16-bit unsigned integer.

UART The UART in the AT89S52 operates the same way as the
UART in the AT89C51 and AT89C52.
Enhanced UART operation
In addition to the standard operation modes, the UART can
perform framing error detect by looking for missing stop bits,
and automatic address recognition. The UART also fully
supports multiprocessor communication. When used for
framing error detect the UART looks for missing stop bits in the
communication. A missing bit will set the FE bit in the SCON
register. The FE bit shares the SCON.7 bit with SM0 and the
function of SCON.7 is determined by PCON.6 (SMOD0). If
SMOD0 is set then SCON.7 functions as FE. SCON.7 functions
as SM0 when SMOD0 is cleared. When used as FE SCON.7 can
only be cleared by software.

Automatic Address Recognition

Automatic Address Recognition is a feature which allows the
UART to recognize certain addresses in the serial bit stream by
using hardware to make the comparisons. This feature saves a
great deal of software overhead by eliminating the need for
the software to examine every serial address which passes by
the serial port. This feature is enabled by setting the SM2 bit in
SCON. In the 9 bit UART modes, mode 2 and mode 3, the
Receive Interrupt flag (RI) will be automatically set when the
received byte contains either the “Given” address or the
“Broadcast” address. The 9 bit mode requires that the 9th
information bit is a 1 to indicate that the received information
is an address and not data. The 8 bit mode is called Mode 1. In
this mode the RI flag will be set if SM2 is enabled and the
information received has a valid stop bit following the 8
address bits and the information is either a given or broadcast
address. Mode 0 is the Shift Register mode and SM2 is ignored.
Using the Automatic Address Recognition feature allows a
master to selectively communicate with one or more slaves by
invoking the given slave address or addresses. All of the slaves
may be contacted by using the Broadcast address. Two special
Function Registers are used to define the slave’s address,
SADDR, and the address mask, SADEN. SADEN is used to
define which bits in the SADDR are to be used and which bits
are “don’t care”. The SADEN mask can be logically ANDed with
the SADDR to create the “Given” address which the master will
use for addressing each of the slaves. Use of the given address
allows multiple slaves to be recognized while excluding others.
The following examples will help to show the versatility of this
Slave0 SADDR = 1100 0000
SADEN = 1111 1101
Given = 1100 00X0

Timer 0 and 1 Timer 0 and Timer 1 in the AT89S52 operate

the same way as Timer 0 and Timer 1 in the AT89C51 and
Timer 2 Timer 2 is a 16-bit Timer/Counter that can operate as
either a timer or an event counter. The type of operation is
selected by bit C/T2 in the SFR T2CON (shown in Table 2).
Timer 2 has three operating modes: capture, auto-reload (up
or down counting), and baud rate generator. The modes are
selected by bits in T2CON, as shown in Table 5.
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the
Timer function, the TL2 register is incremented every machine
cycle. Since a machine cycle consists of 12 oscillator periods,
the count rate is 1/12 of the oscillator frequency.

In the Counter function, the register is incremented in

response to a 1-to-0 transition at its corresponding external
input pin, T2. In this function, the external input is sampled
during S5P2 of every machine cycle. When the samples show a
high in one cycle and a low in the next cycle, the count is
incremented. The new count value appears in the register
during S3P1 of the cycle following the one in which the
transition was detected.
Since two machine cycles (24 oscillator periods) are required
to recognize a 1-to-0 transition, the maximum count rate is
1/24 of the oscillator frequency. To ensure that a given level is
sampled at least once before it changes, the level should be
held for at least one full machine cycle.
Capture Mode In the capture mode, two options are selected
by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer
or counter which upon overflow sets bit TF2 in T2CON. This bit
can then be used to generate an interrupt. If EXEN2 = 1, Timer
2 performs the same operation, but a 1-to-0 transition at
external input T2EX also causes the current value in
TH2 and TL2 to be captured into RCAP2H and RCAP2L,
respectively. In addition, the transition at T2EX causes bit EXF2
in T2CON to be set. The EXF2 bit, like TF2, can generate an
interrupt. The capture mode is illustrated in Figure 1.

Auto-reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when
configured in its 16-bit auto reload mode. This feature is
invoked by the DCEN (Down Counter Enable) bit located in the
SFR T2MOD (see Table 6). Upon reset, the DCEN bit is set to 0
so that timer 2 will default to count up. When DCEN is set,
Timer 2 can count up or down, depending on the value of the
T2EX pin.
Figure 2 shows Timer 2 automatically counting up when DCEN
= 0. In this mode, two options are selected by bit EXEN2 in
T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then
sets the TF2 bit upon overflow. The overflow also causes the
timer registers to be reloaded with the 16-bit value in RCAP2H
and RCAP2L. The values in Timer in Capture ModeRCAP2H and
RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload
can be triggered either by an overflow or by a 1-to-0 transition
at external input T2EX. This transition also sets the EXF2 bit.
Both the TF2 and EXF2 bits can generate an interrupt if
Setting the DCEN bit enables Timer 2 to count up or down, as
shown in Figure 2. In this mode, the T2EX pin controls the
direction of the count. A logic 1 at T2EX makes Timer 2 count
up. The timer will overflow at 0FFFFH and set the TF2 bit. This
overflow also causes the 16-bit value in RCAP2H and RCAP2L
to be reloaded into the timer registers, TH2 and TL2,
respectively. A logic 0 at T2EX makes Timer 2 count down. The
timer underflows when TH2 and TL2 equal the values stored in
RCAP2H and RCAP2L. The underflow sets the TF2 bit and
causes 0FFFFH to be reloaded into the timer registers. The
EXF2 bit toggles whenever Timer 2 overflows or underflows
and can be used as a 17th bit of resolution. In this operating
mode, EXF2 does not flag an interrupt.
Baud Rate Generator Timer 2 is selected as the baud rate
generator by setting TCLK and/or RCLK in T2CON (Table 2).
Note that the baud rates for transmit and receive can be
different if Timer 2 is used for the receiver or transmitter and
Timer 1 is used for the other function. Setting RCLK and/or
TCLK puts Timer 2 into its baud rate generator mode. The baud
rate generator mode is similar to the auto-reload mode, in that
a rollover in TH2 causes the Timer 2 registers to be reloaded
with the 16-bit value in registers RCAP2H and RCAP2L, which
are preset by software.
The baud rates in Modes 1 and 3 are determined by Timer 2’s
overflow rate according to the following equation.

The Timer can be configured for either timer or counter

operation. In most applications, it is configured for timer
operation (CP/T2 = 0). The timer operation is different for
2 when it is used as a baud rate generator. Normally, as a
timer, it increments every machine cycle (at 1/12 the oscillator
frequency). As a baud rate generator, however, it increments
every state time (at 1/2 the oscillator frequency). The baud
rate formula is given below.
where (RCAP2H, RCAP2L) is the content of RCAP2H and
RCAP2L taken as a 16-bit unsigned integer.

Timer 2 as a baud rate generator is shown in Figure 4.

This figure is valid only if RCLK or TCLK = 1 in T2CON. Note
that a rollover in TH2 does not set TF2 and will not generate an
interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in
T2EX will set EXF2 but will not cause a reload from (RCAP2H,
RCAP2L) to (TH2, TL2). Thus, when Timer 2 is in use as a baud
rate generator, T2EX can be used as an extra external
Note that when Timer 2 is running (TR2 = 1) as a timer in the
baud rate generator mode, TH2 or TL2 should not be read from
or written to. Under these conditions, the Timer is incremented
every state time, and the results of a read or write may not be
accurate. The RCAP2 registers may be read but should not be
written to; because a write might overlap a reload and cause
write and/or reload errors. The timer should be turned off
(clear TR2) before accessing the Timer 2 or RCAP2 registers.

Interrupts The AT89S52 has a total of six interrupt vectors:

two external interrupts (INT0 and INT1), three timer interrupts
(Timers 0, 1, and 2), and the serial port interrupt. These
interrupts are all shown in Figure 6. Each of these interrupt
sources can be individually enabled or disabled by setting or
clearing a bit in Special Function Register IE. IE also contains a
global disable bit, EA, which disables all interrupts at once.
User software should not write a 1 to this bit position, since it
may be used in future AT89 products. Timer 2 interrupt is
generated by the logical OR of bits TF2 and EXF2 in register
T2CON. Neither of these flags is cleared by hardware when the
service routine is vectored to. In fact, the service routine may
have to determine whether it was TF2 or EXF2 that generated
the interrupt, and that bit will have to be cleared in software.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of
the cycle in which the timers overflow. The values are then
polled by the circuitry in the next cycle. However, the Timer 2
flag, TF2, is set at S2P2 and is polled in the same cycle in
which the timer overflows.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier that can be configured for use as an on-chip
oscillator, as shown in Figure 7. Either a quartz crystal or
ceramic resonator may be used. To drive the device from an
external clock source, XTAL2 should be left unconnected while
XTAL1 is driven. There are no requirements on the duty cycle
of the external clock signal, since the input to the internal
clocking circuitry is through a divide-by-two flip-flop, but
minimum and maximum voltage high and low time
specifications must be observed.

Idle Mode In idle mode, the CPU puts itself to sleep while all
the on-chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and the entire
special functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset. Note that when idle mode is
terminated by a hardware reset, the device normally resumes
program execution from where it left off, up to two machine
cycles before the internal reset algorithm takes control. On-
chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write to a port pin when idle mode
is terminated by a reset, the instruction following the one that
invokes idle mode should not write to a port pin or to external

Power-down Mode In the Power-down mode, the oscillator is

stopped, and the instruction that invokes Power-down is the
last instruction executed. The on-chip RAM and Special
Registers retain their values until the Power-down mode is
terminated. Exit from Powerdown mode can be initiated either
by a hardware reset or by an enabled external interrupt. Reset
redefines the SFRs but does not change the on-chip RAM. The
reset should not be activated before VCC is restored to its
normal operating level and must be held active long enough to
allow the oscillator to restart and stabilize.
Note: 1. C1, C2 = 30 pF and 10 pF for Crystals
= 40 pF and 10 pF for Ceramic Resonators

Program Memory Lock Bits

The AT89S52 has three lock bits that can be left
unprogrammed (U) or can be programmed (P) to obtain the
additional features listed in the following table.

When lock bit 1 is programmed, the logic level at the EA pin is

sampled and latched during reset. If the device is powered up
without a reset, the latch initializes to a random value and
holds that value until reset is activated. The latched value of
EA must agree with the current logic level at that pin in order
for the device to function properly.


Dual-tone multi-frequency (DTMF) signaling is used for

telephone signaling over the line in the voice-frequency band
to the call switching center. The version of DTMF used for
telephone tone dialing is known by the trademarked term
Touch-Tone (canceled March 13, 1984), and is standardized by
ITU-T Recommendation Q.23. Other multi-frequency systems
are used for signaling internal to the telephone network.

As a method of in-band signaling, DTMF tones were also used

by cable television broadcasters to indicate the start and stop
times of local commercial insertion points during station
breaks for the benefit of cable companies.


The DTMF keypad is laid out in a 4×4 matrix, with each row
representing a low frequency, and each column representing a
high frequency. Pressing a single key (such as ‘1’) will send a
sinusoidal tone of the two frequencies (697 and 1209 hertz
(Hz)). The original keypads had levers inside, so each button
activated two contacts. The multiple tones are the reason for
calling the system multi-frequency. These tones are then
decoded by the switching center to determine which key was

DTMF keypad frequencies (with sound clips)

1209 1336 1477 1633
Hz Hz Hz Hz
697 Hz 1 2 3 A
770 Hz 4 5 6 B
852 Hz 7 8 9 C
941 Hz * 0 # D

DTMF event frequencies

Low High
frequency frequency
Busy signal 480 Hz 620 Hz
Dial tone 350 Hz 440 Hz
440 Hz 480 Hz

The tone frequencies, as defined by the Precise Tone Plan, are

selected such that harmonics and intermodulation products
will not cause an unreliable signal. No frequency is a multiple
of another, the difference between any two frequencies does
not equal any of the frequencies, and the sum of any two
frequencies does not equal any of the frequencies. The
frequencies were initially designed with a ratio of 21/19, which
is slightly less than a whole tone. The frequencies may not
vary more than ±1.8% from their nominal frequency, or the
switching center will ignore the signal. The high frequencies
may be the same volume or louder as the low frequencies
when sent across the line. The loudness difference between
the high and low frequencies can be as large as 3 decibels (dB)
and is referred to as "twist". The minimum duration of the tone
should be at least 70 msec, although in some countries and
applications DTMF receivers must be able to reliably detect
DTMF tones as short as 45ms.

Synonyms include multi-frequency pulsing and multi-frequency


• Operating voltage: 2.5V~5.5V
• Minimal external components
• No external filter is required
• Low standby current (on power down mode)
• Excellent performance
• Tristate data output for MCU interface
• 3.58MHz crystal or ceramic resonator
• 1633Hz can be inhibited by the INH pin

Block diagram of HT1907 DTMF Receiver

The HT9170B/D are Dual Tone Multi Frequency (DTMF)
receivers integrated with digital decoder and band split filter
functions as well as power-down mode and inhibit mode
operations. Such devices use digital counting techniques to
detect and decode all the 16 DTMF tone pairs into a 4-bit code
output. Highly accurate switched capacitor filters are
implemented to divide tone signals into low and high group
signals. A built-in dial tone rejection circuit is provided to
eliminate the need for pre-filtering.

The HT9170B/D tone decoders consist of three band pass

filters and two digital decode circuits to convert a tone (DTMF)
signal into digital code output. An operational amplifier is built-
in to adjust the input signal
The pre-filter is a band rejection filter which reduces the dialing
tone from 350Hz to 400Hz. The low group filter filters low
group frequency signal output whereas the high group filter
filters high group frequency signal output. Each filter output is
followed by a zero-crossing detector with hysteresis. When
each signal amplitude at the output exceeds the specified
level, it is transferred to full swing logic signal.
When input signals are recognized to be effective, DV becomes
high, and the correct tone code (DTMF) digit is transferred.
Steering control circuit
The steering control circuit is used for measuring the effective
signal duration and for protecting against drop out of valid
signals. It employs the analog delay by external RC time-
constant controlled by EST. The EST pin is normally low and
draws the RT/GT pin to keep low through discharge of external
RC. When a valid tone input is detected, EST goes high to
charge RT/GT through RC. When the voltage of RT/GT changes
from 0 to VTRT (2.35V for 5V supply), the input signal is
effective, and the correct code will be created by the code
detector. After D0~D3 are completely latched, DV output
becomes high. When the voltage of RT/GT falls down from V DD
to VTRT (i.e.., when there is no input tone), DV output becomes
low, and D0~D3 keeps data until a next valid tone input is
produced. By selecting adequate external RC value, the
minimum acceptable input tone duration (tACC) and the
minimum acceptable inter-tone rejection (tIR) can be set.
External components (R, C) are chosen by the formula:

where tACC: Tone duration acceptable time
tDP: EST output delay time (“L” → “H”)
tGTP: Tone present time
tIR: Inter-digit pause rejection time
tDA: EST output delay time (“H” → “L”)
tGTA: Tone absent time
The most commonly used Character based LCDs are based on
Hitachi's HD44780 controller or other which are compatible
with HD44580. In this tutorial, we will discuss about character
based LCDs, their interfacing with various microcontrollers,
various interfaces (8-bit/4-bit), programming, special stuff and
tricks you can do with these simple looking LCDs which can
give a new look to your application.

Pin Description
The most commonly used LCD’s found in the market today are
1 Line, 2 Line or 4 Line LCDs which have only 1 controller and
support at most of 80 characters, whereas LCDs supporting
more than 80 characters make use of 2 HD44780 controllers.

Most LCDs with 1 controller has 14 Pins and LCDs with 2

controller has 16 Pins (two pins are extra in both for back-light
LED connections). Pin description is shown in the table below.

Pin No. Name Description

Pin no. 1 VSS Power supply (GND)
Pin no. 2 VCC Power supply (+5V)
Pin no. 3 VEE Contrast adjust
0 = Instruction input
Pin no. 4 RS
1 = Data input
0 = Write to LCD module
Pin no. 5 R/W
1 = Read from LCD module
Pin no. 6 EN Enable signal
Pin no. 7 D0 Data bus line 0 (LSB)
Pin no. 8 D1 Data bus line 1
Pin no. 9 D2 Data bus line 2
Pin no. 10 D3 Data bus line 3
Pin no. 11 D4 Data bus line 4
Pin no. 12 D5 Data bus line 5
Pin no. 13 D6 Data bus line 6
Pin no. 14 D7 Data bus line 7 (MSB)
DDRAM - Display Data RAM
Display data RAM (DDRAM) stores display data represented in
8-bit character codes. Its extended capacity is 80 X 8 bits, or
80 characters. The area in display data RAM (DDRAM) that is
not used for display can be used as general data RAM. So
whatever you send on the DDRAM is actually displayed on the
LCD. For LCDs like 1x16, only 16 characters are visible, so
whatever you write after 16 chars is written in DDRAM but is
not visible to the user.

CGROM - Character Generator ROM

Now you might be thinking that when you send an ASCII value
to DDRAM, how the character is displayed on LCD? So the
answer is CGROM. The character generator ROM generates 5 x
8 dot or 5 x 10 dot character patterns from 8-bit character
codes (see Figure 5 and Figure 6 for more details). It can
generate 208 5 x 8 dot character patterns and 32 5 x 10 dot
character patterns. User defined character patterns are also
available by mask-programmed ROM.

As you can see in both the code maps, the character code from
0x00 to 0x07 is occupied by the CGRAM characters or the user
defined characters. If user wants to display the fourth custom
character then the code to display it is 0x03 i.e. when user
sends 0x03 code to the LCD DDRAM then the fourth user
created character or pattern will be displayed on the LCD.
CGRAM - Character Generator RAM
As clear from the name, CGRAM area is used to create custom
characters in LCD. In the character generator RAM, the user
can rewrite character patterns by program. For 5 x 8 dots,
eight character patterns can be written, and for 5 x 10 dots,
four character patterns can be written.

BF - Busy Flag
Busy Flag is a status indicator flag for LCD. When we send a
command or data to the LCD for processing, this flag is set (i.e.
BF =1) and as soon as the instruction is executed successfully
this flag is cleared (BF = 0). This is helpful in producing and
exact amount of delay for the LCD processing.

To read Busy Flag, the condition RS = 0 and R/W = 1 must be

met and The MSB of the LCD data bus (D7) act as busy flag.
When BF = 1 means LCD is busy and will not accept next
command or data and BF = 0 means LCD is ready for the next
command or data to process.

Instruction Register (IR) and Data Register (DR)

There are two 8-bit registers in HD44780 controller Instruction
and Data register. Instruction register corresponds to the
register where you send commands to LCD e.g. LCD shift
command, LCD clear, LCD address etc. and Data register is
used for storing data which is to be displayed on LCD. When
send the enable signal of the LCD is asserted, the data on the
pins is latched in to the data register and data is then moved
automatically to the DDRAM and hence is displayed on the
Data Register is not only used for sending data to DDRAM but
also for CGRAM, the address where you want to send the data,
is decided by the instruction you send to LCD.

4-bit programming of LCD

In 4-bit mode the data is sent in nibbles, first we send the
higher nibble and then the lower nibble. To enable the 4-bit
mode of LCD, we need to follow special sequence of
initialization that tells the LCD controller that user has selected
4-bit mode of operation. We call this special sequence as
resetting the LCD. Following is the reset sequence of LCD.

 Wait for about 20mS

 Send the first init value (0x30)
 Wait for about 10mS
 Send second init value (0x30)
 Wait for about 1mS
 Send third init value (0x30)
 Wait for 1mS
 Select bus width (0x30 - for 8-bit and 0x20 for 4-bit)
 Wait for 1mS

The busy flag will only be valid after the above reset sequence.
Usually we do not use busy flag in 4-bit mode as we have to
write code for reading two nibbles from the LCD. Instead we
simply put a certain amount of delay usually 300 to 600uS.
This delay might vary depending on the LCD you are using, as
you might have a different crystal frequency on which LCD
controller is running. So it actually depends on the LCD module
you are using.

In 4-bit mode, we only need 6 pins to interface an LCD. D4-D7

are the data pins connection and Enable and Register select
are for LCD control pins. We are not using Read/Write (RW) Pin
of the LCD, as we are only writing on the LCD so we have made
it grounded permanently. If you want to use it, then you may
connect it on your controller but that will only increase another
pin and does not make any big difference. Potentiometer RV1
is used to control the LCD contrast. The unwanted data pins of
LCD i.e. D0-D3 are connected to ground.

Sending data/command in 4-bit Mode

We will now look into the common steps to send
data/command to LCD when working in 4-bit mode. In 4-bit
mode data is sent nibble by nibble, first we send higher nibble
and then lower nibble. This means in both command and data
sending function we need to separate the higher 4-bits and
lower 4-bits.

The common steps are:

 Mask lower 4-bits

 Send to the LCD port
 Send enable signal
 Mask higher 4-bits
 Send to LCD port
 Send enable signal


A variable regulated power supply, also called a variable

bench power supply, is one where you can continuously
adjust the output voltage to your requirements. Varying
the output of the power supply is the recommended way
to test a project after having double checked parts
placement against circuit drawings and the parts
placement guide.
This type of regulation is ideal for having a simple variable
bench power supply. Actually this is quite important
because one of the first projects a hobbyist should
undertake is the construction of a variable regulated
power supply. While a dedicated supply is quite handy e.g.
5V or 12V, it's much handier to have a variable supply on
hand, especially for testing.
Most digital logic circuits and processors need a 5 volt
power supply. To use these parts we need to build a
regulated 5 volt source. Usually you start with an
unregulated power To make a 5 volt power supply, we use
a LM7805 voltage regulator IC (Integrated Circuit). The IC
is shown below.

The LM7805 is simple to use. You simply connect the

positive lead of your unregulated DC power supply
(anything from 9VDC to 24VDC) to the Input pin, connect
the negative lead to the Common pin and then when you
turn on the power, you get a 5 volt supply from the Output


Brief description of operation: Gives out well regulated

+5V output, output current capability of 100 mA
Circuit protection: Built-in overheating protection shuts
down output when regulator IC gets too hot
Circuit complexity: Very simple and easy to build
Circuit performance: Very stable +5V output voltage,
reliable operation
Availability of components: Easy to get, uses only very
common basic components
Design testing: Based on datasheet example circuit, I have
used this circuit succesfully as part of many electronics
Applications: Part of electronics devices, small laboratory
power supply
Power supply voltage: Unreglated DC 8-18V power supply
Power supply current: Needed output current + 5 mA
Component costs: Few dollars for the electronics
components + the input transformer cost


The schematic is divided into four sections microcontroller
section, DTMF receiver module, controlling section and power
supply section

Micro controller section contains Micro-controller P89C51 and a

crystal of 11.0592 MHz for oscillator. Micro controller works on
the program inside the memory. . As the controller keeps all
the memory and I/O ports inside it, it contains very less
components in its outer configuration. Power to the IC
supplied is +5v DC.

The microcontroller is connected to the output pins of DTMF

receiver. The input to the DTMF receiver is from the telephone
line. The ground wire of telephone line is connected to the
ground of the circuit. A crystal oscillator of 3.579545 MHz is
used in the clock circuit of DTMF receiver

Power supply is an important part of operation of the

Microcontroller. The heart of the power supply is LM7805 3-
terminal regulator. Microcontroller operates at +5v DC.

This circuit controls the application when we dial a number on

a landline or mobile which is situated remotely. This is
particularly helpful for receiving any number over the phone
lines. The DTMF signal—generated by the phone on dialing a
number—is decoded by DTMF decoder , which converts the
received DTMF signal into its equivalent BCD number that
corresponds to the dialed number. This binary number is
stored sequentially in microcontroller registers each time a
number is dialed from the phone.
The microcontroller is programmed in such a way that
depending on the number dialed, the microcontroller sends a
control signal to the relay which in turn controls the
application. A DC power supply block is also shown which
supplies required power for all electronic components

SDCC is a re-targetable, optimizing ANSI-C compiler that

targets the Intel 8051, Maxim 80DS390, Zilog Z80 and the
Motorola 68HC08 based MCUs. SDCC is Free Open Source
Software, distributed under GNU General Public License (GPL).


• ASXXXX and ASLINK, a Freeware, retargetable assembler

and linker.
• Extensive MCU specific language extensions, allowing
effective use of the underlying hardware.
• a host of standard optimizations such as global sub
expression elimination, loop optimizations (loop
invariant, strength reduction of induction variables and
loop reversing ), constant folding and propagation, copy
propagation, dead code elimination and jump tables for
'switch' statements.
• MCU specific optimizations, including a global register
• Adaptable MCU specific backend that should be well
suited for other 8 bit MCUs
• Independent rule based peep hole optimizer.
• A full range of data types: char (8 bits, 1 byte), short (16
bits, 2 bytes), int (16 bits, 2 bytes), long (32 bit, 4 bytes)
and float (4 byte IEEE).
• The ability to add inline assembler code anywhere in a
• The ability to report on the complexity of a function to
help decide what should be re-written in assembler.
• A good selection of automated regression tests.

SDCC also comes with the source level debugger SDCDB, using
the current version of Daniel's s51 simulator.

SDCC was written by Sandeep Dutta and released under a GPL

license. Since its initial release there have been numerous bug
fixes and improvements. As of December 1999, the code was
moved to SourceForge where all the "users turned developers"
can access the same source tree. SDCC is constantly being
updated with all the users' and developers' input.

AVR and gbz80 ports are no longer maintained.


SDCC and the included support packages come with fair

amounts of documentation and examples. When they aren't
enough, you can find help in the places listed below. Here is a
short check list of tips to greatly improve your chances of
obtaining a helpful response.

1. Attach the code you are compiling with SDCC. It should

compile "out of the box". Snippets must compile and
must include any required header files, etc. Incomplete
information will hamper your chance of a timely
2. Specify the exact command you use to run SDCC, or
attach your Makefile.
3. Specify the SDCC version (type "sdcc -v"), your platform
and operating system.
4. Provide an exact copy of any error message or incorrect
SDCC Memory Models
SDCC basically has two memory models: Small and Large
• The large memory model will allocate all variables in
external RAM byDEFAULT
“Variables stored in internal RAM must be declared with the
“data” or “near” keyword
• The small memory model will allocate all variables in
internal, directly addressable
RAM by default
“Variables stored in external RAM must be declared with the
“xdata” or “far” keyword
! SDCC recommends the use of the small memory model for
more efficient code.
However, for this class, since we are using combined program
and data memory spaces, I think it is safer to use the large
memory model.
! Be aware that, regardless of the memory model you choose,
if you do not explicitly declare a pointer as data/near or
xdata/far it will be 3 bytes!

SDCC Basics

Assuming that the location of SDCC is defined in your path, you

can use the following syntax for your header files:

#include <stdio.h>

To use SDCC on the command line, use command line syntax

similar to the following (note: a more complete list of flags is
shown in the example makefile later):
sdcc --code-loc 0x6000 --xram-loc 0xB000 file.c
 SDCC will generate the following output files:
file.asm – Assembler file created by the compiler
file.lst – Assembler listing file created by the assembler
file.rst – Assembler listing file updated by the linkage editor
file.sym – Symbol listing created by the assembler
file.rel – Object file created by the assembler, Input to the
linkage editor – Memory map for the load module created by the
file.mem – Summary of the memory usage
file.ihx – This is the load module in Intel hex format
 By default SDCC uses the small memory model
 The assembler is given the memory locations as .area
directives instead of ORG statements.
 You must remember to use the --code-loc and --ram-loc
directives because this tells the linker where to place
things in memory!
 You can examine the file.rst and output
files to verify that your code and data are assigned to
the correct location.

SDCC standard library routines

Most standard routines are present (printf, malloc, etc…)
" printf depends on putchar() which is not implemented.
• You must implement putchar()
• This allows you to decide where printf is displayed (on a
terminal via serial port, on an LCD, etc…)
• The putchar () function must have the following format:
void putchar(char c);
• If you need a getchar() function, the format is:
char getchar(); malloc depends on having heap space created
but SDCC does not automatically create heap space for your
• You must provide heap space for malloc to allocate
memory from.
• This can be done by:
#include <malloc.h>
#define HEAP_SIZE 4000
unsigned char xdata heap[HEAP_SIZE];
void main()
init_dynamic_memory((MEMHEADER xdata *)heap,


 To write an ISR in C, create a function similar to the
following format:
void isr_foo() interrupt 1

“This format tells SDCC to generate an interrupt vector (at

offset0x0B from the --code-loc address) that calls isr_foo in
response to interrupt 1.
“It also tells SDCC to generate a RETI instruction instead of a
RET instruction to return from a call to isr_foo(). The standard
code generated for the interrupt is not very efficient. SDCC
takes a conservative view and will save registers on the stack
before executing any of your code in the ISR and it will restore
those registers before executing the RETI instruction.
“You can use the keyword “_naked” to make your interrupt
This keyword will prevent SDCC from generating any entry/exit
code to save registers for your ISR.
• WARNING: If you use the _naked keyword you must save and
restore any registers that are modified by your ISR or you must
guarantee that no registers are used by your ISR.
• I would only recommend using the _naked keyword if your
ISR only contains inline assembly in which case you know
explicitly which registers are used or you are setting a single
bit (such as a port pin) in which case no registers are used.
• You can use the _naked keyword on any function, not just for
ISRs. In non-ISR routines you must be aware of the calling
convention used and save/restore the registers you used
within your function as appropriate.
! SDCC serial port initialization
There is no support routine built into SDCC to initialize the
serial port
If you want to use the serial port with your C program that you
burn into EPROM you will have to initialize the hardware first.

Flash Magic is a PC tool for programming flash based

microcontrollers from NXP using a serial protocol while in the
target hardware.

Flash Magic is a feature-rich Windows based tool for the

downloading of code into NXP flash microcontrollers. It utilizes
a feature of the microcontrollers called ISP, which allows the
transfer of data serially between a PC and the device.

Flash Magic can erase devices, program them, read data and
read and set various configuration information. Rather than
providing the basic features of ISP, Flash Magic adds additional
features and intelligence, allowing complex operations to be
performed. For example, erasing can be any collection of
pages, blocks, the hex file to be programmed or the entire
device. Some devices store the ISP boot loader in flash
memory, so Flash magic implements methods to protect this
code from being erased.

Additional advanced features of Flash Magic include the

automatic programming of checksums, entering ISP mode via
a serial command, execution of Just in Time modules allowing
endless flexibility in the data programmed, control over RS232
signals to place devices into ISP mode, and control over the
timing of such signals.

Flash Magic has been available for free for over six years and
supports all current 8-bit (8051), 16-bit (XA) and 32-bit (ARM)
flash microcontrollers from NXP.
Possible Uses

Some ideas for applications built on the Flash Magic platform:

• Custom ISP tool for in-house use, for example production

line programming where it is essential the user interface
is simplified as much as possible
• End user ISP tool for updating the firmware of products.
You can build the hex file into the application or allow it
to be fetched over the internet. Adverts for new products
could be displayed to the user. Use one tool for all your
products involving potentially multiple NXP
• Gang programming tool. Invoke multiple instances of the
Flash Magic DLL in separate threads, each using a
different COM port to allow parallel ISP programming
• Future-proofing products. Rather than write your own ISP
tool and have to keep updating it for new NXP devices,
updates to the DLL will automatically add new devices


• Straightforward and intuitive user interface

• Five simple steps to erasing and programming a device
and setting any options desired
• Programs Intel Hex Files
• Automatic verifying after programming
• Fills unused Flash to increase firmware security
• Ability to automatically program checksums. Using the
supplied checksum calculation routine your firmware can
easily verify the integrity of a Flash block, ensuring no
unauthorized or corrupted code can ever be executed
• Program security bits
• Check which Flash blocks are blank or in use with the
ability to easily erase all blocks in use
• Read the device signature
• Read any section of Flash and save as an Intel Hex File
• Reprogram the Boot Vector and Status Byte with the help
of confirmation features that prevent accidentally
programming incorrect values
• Display the contents of Flash in ASCII and Hexadecimal
• Single-click access to the manual, Flash Magic home
page and NXP Microcontrollers home page
• Ability to use high-speed serial communications on
devices that support it. Flash Magic calculates the highest
baud rate that both the device and your PC can use and
switches to that baud rate transparently
• Command Line interface allowing Flash Magic to be used
in IDEs and Batch Files
• Manual in PDF format
• Supports half-duplex communications
• Verify Hex Files previously programmed
• Save and open settings
• Able to reset Rx2 and 66x devices (revision G or higher)
• Able to control the DTR and RTS RS232 signals when
connected to RST and /PSEN to place the device into
BootROM and Execute modes automatically. An example
circuit diagram is included in the Manual. Essential for ISP
with target hardware that is hard to access.
• Able to send commands to place the device in BootROM
mode, with support for command line interfaces. The
installation includes an example project for the Keil and
Raisonance 8051 compilers that show how to build
support for this feature into applications.
• Able to play any Wave file when finished programming.
• Built in automated version checker - helps ensure you
always have the latest version.
• Powerful, flexible Just In Time Code feature. Write your
own JIT Modules to generate last minute code for
programming. Uses include:
o Serial number generation
o Copy protection and copy authorization
o Storing program date and time - manufacture date
o Storing program operator and location
o Lookup table generation
o Language tables or language selection
o Centralized record keeping
o Obtaining latest firmware from the Corporate Web
site or project intranet
• Sponsored by NXP Semiconductors
• Features automatically updating Internet links including
links to related technical documents, software updates,
utilities and code examples, using EmbeddedHints
• Displays information about the selected Hex File,
including the creation and modification dates, flash
memory used, percentage of the current device used
• Completely free!
• Flash Magic works on any versions of Windows, except
Windows 95. 10Mb of disk space is required

Source code

In this system, the applications can be controlled through

remote area i.e. applications + controlling can be somewhere
and the controlling signal can be send through a landline or a
mobile. So, when we enter / dial a number on the phone this
signal would be detected by a telephone which is connected to
the controlling part in turn an application would be controlled.

Here the system works perfectly.