SAURABH DARGAN

E-mail: saurabh.dargan13@gmail.com, Contact No.: +91 7760639806,7760639078

Flat # 2,Vikasipura Lane, Near Metro Mall, Kanakpura Road, Bangalore -
560076

~CORE COMPETENCY~

Basic System Verilog Verilog , VHDL

RTL Design ModelSim Mentor Graphics

FPGA/ASIC Design Flow Xilinx ISE, Leonardo

Spectrum

~SUMMARY~

 PG in DVLSI from CDAC, Pune.

 B.E. in ELECTRONICS AND TELECOMMUNICATION from Marudhar
Engineering College, University of Rajasthan in.
 Done a project on VGA CONTROLLER, Spartan-3E kit in CDAC.
 Done a project on ROBOTICS, based on assembly language in B.E.
 Apprentice Training in B.S.N.L, Bikaner.

~OBJECTIVES~

To achieve excellence in working as dynamic professional offering solutions

to business using the best available where my analytical ability and
analysing quest are used maximum for growth of the organization and to
grow with the organization. Seeking a challenging position in well
established company that offers ample opportunity to learn and enrich my
competencies.

~TECHNICAL EXPERTISE~

Languages : System Verilog, Verilog, VHDL

Operating System : Windows XP
Simulation Tools : ModelSim Mentor Graphics.
Synthesis Tools : Xilinx ISE, Leonardo Spectrum.
Layout tools : Microwind.
Target Devices : CPLD (XC9572), FPGA (Spartan-2, Spartan-3E).

~QUALIFICATION~

Degree/Qualificatio Institute/board Year of passing Percentage

n
PG DVLSI CDAC, Pune 2010 68
B.E. ELECTRONICS Marudhar 2008 65.81
AND Engineering
TELECOMMUNICATI College,
ON University of
Rajasthan.
H.S.C R.S.V. School, 2004 53
Bikaner, Raj
Board.
 Bal Badi School, 2002 72.33
S.S.C Bikaner, Raj
Board.

~CAREER HIGHLIGHTS ~

 Currently working with Autotec Systems Pvt Ltd, Bangalore as VLSI

Engineer Trainee (RTL designing) from 1 Sep 2010

~PROJECTS ~

CDAC PROJECT-
VGA CONTROLLER Dec 2009 - Jan 2010
 VHDL based design and implementation of VGA controller on XILINX
SPARTAN 3E KIT using XILINX ISE. Design of synchronization and pixel
generation circuit to match working of a basic CRT display.
 ASCII character display using Tile Mapped Pixel Generation Scheme.
 Design of ROM to store the fonts for characters in a resolution of 16 X 8
pixels.
 Development of programmable CPLD XC-9572 PC84 board

BE PROJECT-
ROBOTICS Feb 2008 - Apr 2008
 Based on assembly language.
 Detects obstacles in the way and line follower (with sensors).
 It could control through mobile also.

~ACHIEVEMENTS~

 Was coordinator of Annual Function during college.

 Was captain of cricket team of college.
 Have always been active participant in blood donation campaign.
 Other Hobbies are soft music, movies (all types) and nature walks.

~PERSONAL SKILLS~

 Positive Attitude, Determined, High Energies.

 Ability and willingness to learn and adapt.
 Good decision making and analytical skills.
 Patient and effective response under team work.

~PERSONAL PROFILE~

Name Saurabh Dargan

Father’s Name Devendra Kumar Verma
Mother’s Name Prem Verma
Date of birth 13/01/1986
Age 23 years
Gender Male
Nationality Indian
Languages Known English, Hindi, Punjabi.
Permanent Address Street No-15, Rathkhana Colony, Bikaner,
Rajasthan.
Passport Valid Passport