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Jing Guo,a) Sebastien Goasguen, Mark Lundstrom, and Supriyo Datta

1285 Electrical Engineering Building, Purdue University, West Lafayette, Indiana 47907

共Received 14 January 2002; accepted for publication 28 June 2002兲

Carbon nanotube metal–insulator–semiconductor capacitors are examined theoretically. For the

densely packed array of nanotubes on a planar insulator, the capacitance per tube is reduced due to

the screening of the charge on the gate plane by the neighboring nanotubes. In contrast to the silicon

metal–oxide–semiconductor capacitors, the calculated C – V curves reflect the local peaks of the

one-dimensional density-of-states in the nanotube. This effect provides the possibility to use C – V

measurements to diagnose the electronic structures of nanotubes. Results of the electrostatic

calculations can also be applied to estimate the upper-limit on-current of carbon nanotube

field-effect transistors. © 2002 American Institute of Physics. 关DOI: 10.1063/1.1502188兴

The carbon nanotube field-effect transistor 共CNTFET兲1–3 the same threshold voltage V T for the CNT and MOS capaci-

is a promising candidate for future electron devices. Rapid tors.

progress in the field has recently made it possible to fabricate The nanotube capacitance versus gate voltage is com-

digital and analogue CNTFET-bases circuits, such as logic puted as follows. For an assumed potential of the nanotube,

gates, static memory cells, and ring oscillators.4,5 To explore the charge density, Q L , was obtained from

the role of CNTFETs in future integrated circuits, it is

important to evaluate their performance as compared

to the metal–oxide–semiconductor field-effect transistor

Q L ⫽ 共 ⫺e 兲 • 冕⫺⬁

⫹⬁

dE•sgn共 E 兲 D 共 E 兲 f 共 sgn共 E 兲关 E⫺Ẽ F 兴 兲 ,

mance metric, is the product of the charge induced by the

where e is the electron charge, sgn(E) is the sign function,

gate and the average carrier velocity,6 so the first step is to

D(E) is the density-of-states 共DOS兲 of the nanotube10 and

understand the gate-controlled electrostatics of a carbon

Ẽ F ⫽eV CNT is the position of Fermi level relative to the

nanotube metal–insulator–semiconductor 共MIS兲 capacitor.

middle of the energy gap 共we assume an intrinsic nanotube兲,

Theoretical studies of carbon nanotube electrostatics

and V CNT is the average potential of the nanotube. We adopt

have focused on two-terminal devices and the electrostatics

a semiclassical approach in which the effect of gate voltage

along the nanotube direction.7,8 The planar gate-controlled

is to move the subbands of the nanotube rigidly up and down

electrostatics has been treated approximately in experimental

without changing the D(E), the nanotube DOS. This as-

studies in order to qualitatively explain or fit measured

sumption is valid for the coaxial geometry because the cy-

data.5,9 In this letter, the MIS electrostatics of carbon nano-

lindrical symmetry produces the same potential for each car-

tube capacitors in three different geometries is analyzed by

bon atom. But for a planar geometry, potential drops across

solving the two-dimensional Poisson equation self-

the nanotube can perturb its band structure.11 As long as the

consistently with carrier statistics of nanotubes. The results

potential variation across a ⬃1 nm diameter nanotube is be-

show that for the densely packed array of nanotubes on a low 0.8 V, the effect is small,11 so our use of a 0.4 V power

planar insulator, the capacitance per tube is reduced due to supply, as required for high-density digital systems,12 sug-

the screening of the charge on the gate plane by the neigh- gests that band structure perturbations will be small in this

boring nanotubes. In contrast to silicon, planar MOS capaci- case.

tors, the capacitance is strongly influenced by the nanotube’s

one-dimensional density-of-states. The results also show that

careful electrostatic design will be critical for the perfor-

mance of CNTFETs.

The three nanotube capacitors examined in this study,

each with a semiconducting nanotube having a diameter of

D⫽1 nm, are shown in Fig. 1. In the third dimension 共out of

the page兲 the nanotube is assumed to be connected to ground,

which supplies the carriers to balance the charge on the gate.

For comparison to a silicon MOS capacitor, we assume a

silicon doping of N A ⫽1018 cm⫺3 , insulator thickness t ins

⫽1 nm and a dielectric constant of ins⫽4. It is important

that results be compared at the same gate overdrive, (V G

⫺V T ), so the gate work functions were selected to produce FIG. 1. Three geometries of nanotube MIS capacitors: 共i兲 the single nano-

tube planar capacitor, 共ii兲 a periodic array of nanotubes, and 共iii兲 the coaxi-

ally gated capacitor. Nanotube diameter D⫽1 nm, insulator thickness t ins

a兲

Electronic mail: guoj@purdue.edu ⫽1 nm, and a dielectric constant ins⫽4 are the same for all capacitors.

Downloaded 12 Oct 2002 to 128.211.134.159. Redistribution subject to AIP license or copyright, see http://ojps.aip.org/aplo/aplcr.jsp

Appl. Phys. Lett., Vol. 81, No. 8, 19 August 2002 Guo et al. 1487

sumed nanotube potential, the corresponding gate voltage is

VG 共2兲

constant independent of gate voltage兲, V G is the gate voltage,

and V fb the flatband voltage as determined by the gate metal

to nanotube work function difference and any insulator–

nanotube surface states. Because V fb depends on specifics of

experimental conditions, all results will be plotted as a func-

tion of V G⬘ except otherwise specified. By solving Eqs. 共1兲

and 共2兲 self-consistently, the Q L (V G ) relation is obtained and FIG. 2. The insulator capacitance C ins versus the tube density 共normalized

to max⫽1/D, the close-packed case兲 for an array of parallel nanotubes,

the gate capacitance is C G ⫽⫺dQ L /dV G . This procedure is compared to C ins⫽ ins 0 /t ins of the MOS capacitor 共dotted line兲. The solid

analogous to the one commonly used to compute MOS C G line assumes classical charge distribution, and dash line one subband quan-

versus V G characteristics.6 tum limit.

Before the C G versus V G characteristic can be evaluated,

the insulator capacitance must be specified. There is a Figure 3共a兲 shows the one-dimensional 共1D兲 charge den-

simple, analytical expression for the coaxial geometry,13 but ⬘ for the

sity Q L as a function of the effective gate voltage V G

planar capacitors require a numerical solution of two- coaxial nanotube capacitor, which provides the optimum ge-

dimensional Poisson equation because two different dielec- ometry for gate control in a MISFET.15 The charge density is

tric constants above the metal plate 共the insulator and air兲 approximately linear with gate voltage above the threshold

invalidate the simple, analytical expression. The numerical voltage and can, therefore be expressed as Q L ⬇C G (V G

solution was first evaluated for a classical conducting cylin- ⫺V T ). The effective gate capacitance per unit length, C G

der on the top of an infinite conducting plane with a uniform ⬇1.65 pF/cm, is only 80% of the insulator capacitance,

dielectric material between them, and the result agreed well C ins⫽2.03 pF/cm, because the gate capacitance is the series

with the exact analytical solutions.13 The single nanotube combination of the insulator and nanotube capacitance. For

planar geometry, which has two dielectric materials 关case 共i兲 very large gate voltages 共where our semiclassical treatment

in Fig. 1兴 was then simulated. Two limits were considered: needs to be critically examined兲, electrons occupy the second

共1兲 a classical distribution of charge in the nanotube, which

assumes the charge redistribute itself to establish an equal

potential over the nanotube like a classical metal and 共2兲 a

single subband quantum distribution, which assumes that the

charge distributes symmetrically around the nanotube. In the

classical limit, we find C ins⫽0.61 pF/cm and in the quantum

limit, C ins⫽0.53 pF/cm.

The significant difference between the classical and

quantum limits occurs because the quantum charge distribu-

tion 共the center of the nanotube兲 is located further from the

metal gate than is the classical charge centroid, and the nano-

tube diameter is comparable to t ins . Note that in most of the

experimental planar nanotube capacitors explored to date1,3

the difference between the classical and quantum limits will

be small because the nanotube diameter 共typically ⬃1 nm兲 is

much smaller than insulator thickness 共typically ⬃100 nm兲.

The difference may become important, however, for the very

thin insulators that will be used near the scaling limit.

Figure 2 shows the insulator capacitance of an array of

parallel nanotubes 关case 共ii兲 in Fig. 1兴 versus the nanotube

density, ⫽1/S, where S is the spacing between neighboring

nanotubes. For small packing densities, the capacitance per

unit area is proportional to the packing density. The largest

capacitance per unit area 共still 20%–50% below C ins of the

planar silicon MOS capacitor兲 is achieved when the tubes are

close packed, but increasing the normalized packing density

above 0.5, does not result in the proportional increase of

capacitance because each nanotube images to a narrower

width and, therefore, a smaller fraction of the charge on the FIG. 3. Charge vs. gate voltage for the coaxial capacitor, 共a兲 charge density

Q L and 共b兲 the gate capacitance C G versus the effective gate voltage V G⬘ .

gate. When the nanotubes are closely packed, the capacitance The inset in 共a兲 shows location of the Fermi level in the first and second

per tube decreases due to the screening of the gate charge by subbands at V G⬘ ⫽1 V, and 3 V. The dotted line in 共b兲 indicates the insulator

the neighboring nanotubes.14 capacitance C ins .

Downloaded 12 Oct 2002 to 128.211.134.159. Redistribution subject to AIP license or copyright, see http://ojps.aip.org/aplo/aplcr.jsp

1488 Appl. Phys. Lett., Vol. 81, No. 8, 19 August 2002 Guo et al.

nanotube capacitors may be improved by embedding nano-

tubes inside the gate insulator,14 which results in comparable

performance to the silicon, planar MOS capacitor. On the

right axis, we compare the charge for a single tube in a

planar geometry, case 共i兲 in Fig. 1, to that in a coaxial geom-

etry. The results show a clear advantage for the coaxial ge-

ometry and suggest that careful electrostatic design should

be important for CNTFETs.

In summary, we have presented numerical studies of the

MIS electrostatics of carbon nanotube capacitors and have

shown that the capacitance versus voltage characteristics are

quite different from those of standard, planar, silicon MOS

FIG. 4. Charge density vs. gate voltage V G . On the left axis, the close-

packed array of nanotubes 共dashed line兲 is compared to the silicon MOS

capacitors. The difference arises from the 1D density of

capacitor 共solid line兲. On the right axis, the coaxially gated capacitor 共solid states in the nanotube, which leads to local maxima in the

line with circles兲 is compared to the single nanotube planar geometry C G versus V G characteristic. We show that the planar nano-

共dashed with circles兲. To make a fair comparison, the gate workfunction of tube capacitors offer comparable performance to the silicon

each capacitor is adjusted to produce a common threshold voltage, V T

⬇0.1 V.

MOS capacitors, but the coaxial gate geometry promises sig-

nificantly higher performance. These results support a recent

study based on a drift-diffusion analysis, which suggests that

conduction band as shown in the inset of Fig. 3共a兲. The sub- CNTFETs can be competitive with MOSFETs.3 The electro-

band spacing decreases with increasing nanotube diameter, static calculations also allow us to estimate the upper-limit

but for typical diameters of about 1 nm and operating volt- on-current of CNTFETs based on a simple 1D model.17,18

ages of ⬍0.5 V, only a single subband will be occupied. The

one-subband approximation, therefore, can be used in the This material is based upon work supported by the Na-

calculation. tional Science Foundation under Grant No. 0085516. Helpful

Figure 3共b兲 shows the computed C G versus V G charac- discussions with M. P. Anantram of NASA Ames Research

teristic of the coaxial nanotube capacitor. The striking differ- Center and P. McEuen, Cornell, through the MARCO

ence from that for a MOS capacitor on an intrinsic substrate /DARPA Focus Center on Materials, Structures, and Devices

is due to the 1D DOS of the nanotube. The origin of local are also acknowledged.

maxima is apparent when the nanotube capacitance is calcu-

1

lated at zero temperature C CNT (V CNT)⫽⫺dQ L /dV CNT R. Martel, T. Schimidt, H. R. Shea, T. Hertel, and Ph. Avouris, Appl. Phys.

Lett. 73, 2447 共1998兲.

⫽e 2 D(eV CNT), where D(E) is the DOS of the nanotube. 2

W. Choi, J. Chu, K. Jeong, E. Bae, and J. Lee, Appl. Phys. Lett. 79, 3696

Although the peaks in the 1D DOS are smoothed out by 共2001兲.

3

temperature, and the insulator capacitor in series, they still R. Martel, H.-S. P. Wong, K. Chan, and P. Avouris, Tech. Dig. Int. Elec-

display local maximums on the C – V curve at room tempera- tron Devices Meet. 2001, 159 共2001兲.

4

V. Derycke, R. Martel, J. Appenzeller, and Ph. Avouris, Nano Lett. 9, 453

ture. Experimental measurement of C – V curves, especially 共2001兲.

at low temperature using liquid-ion gating9 which provides a 5

A. Bachtold, P. Hadley, T. Nakanishi, and C. Dekker, Science 294, 1317

high insulator capacitance, could generate useful diagnostic 共2001兲.

information on the DOS of the nanotube.

6

Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices 共Cam-

bridge University Press, Cambridge, UK, 1998兲.

Figure 4 is an attempt to compare silicon MOS capaci- 7

F. Leonard and J. Tersoff, Phys. Rev. Lett. 83, 5174 共1999兲.

tors with carbon nanotube MIS capacitors. The MOS C G 8

A. Odintsov, Phys. Rev. Lett. 85, 150 共2000兲.

9

versus V G characteristic was computed by a self-consistent M. Kruger, M. Buitelaar, T. Nussbaumer, and C. Schonenberger, Appl.

Schrödinger–Poisson solver so that quantum confinement ef- Phys. Lett. 78, 1291 共2001兲.

10

J. W. Mintmire and C. T. White, Phys. Rev. Lett. 81, 2506 共1998兲.

fects were included.16 The same threshold voltage V T , and 11

Y. H. Kim and K. J. Chang, Phys. Rev. B 64, 153404 共2001兲.

the power supply voltage V DD , were assumed for all capaci- 12

International Technology Roadmap for Semiconductors, 共SEMATECH,

tors. On the left axis, we show that the effective gate capaci- Austin, TX, 2001兲, available at http://public.itrs.net.

13

tance of the nanotube array 共the slope of the curve above S. Ramo, J. R. Whinnery, and T. V. Duzer, Field and Waves in Commu-

nication Electronics 共Wiley, New York, 1994兲.

threshold兲 is 66% of that of the silicon MOS capacitor be- 14

S. J. Wind, J. Appenzeller, R. Martel, V. Derycke, and Ph. Avouris, Appl.

cause geometrical effects and quantum charge distribution Phys. Lett. 80, 3817 共2002兲.

reduce the insulator capacitance, as discussed earlier. 共For

15

C. Auth and J. Plummer, IEEE Electron Device Lett. 18, 74 共1997兲.

16

D. Vesileska, D. K. Schroder, and D. K. Ferry, IEEE Trans. Electron

thicker gate insulator, a planar nanotube capacitor can out-

Devices 44, 584 共1997兲.

perform the corresponding silicon MOS capacitor because 17

K. Natori, J. Appl. Phys. 76, 4879 共1994兲.

the capacitance decreases more slowly with the insulator 18

J. Guo, M. Lundstrom, and S. Datta, Appl. Phys. Lett. 80, 3192 共2002兲.

Downloaded 12 Oct 2002 to 128.211.134.159. Redistribution subject to AIP license or copyright, see http://ojps.aip.org/aplo/aplcr.jsp

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