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# 16

**Logic Design Examples
**

Charles E. Chang

Conexant Systems, Inc.

**16.1 Design of MESFET and HEMT Logic Circuits ..............16-1
**

Direct-Coupled FET Logic (DCFL) • Source-Coupled FET Logic (SCFL) • Advanced MESFET/HEMT Design Examples

Meera Venkataraman

Troika Networks, Inc.

**16.2 HBT Logic Design Examples..........................................16-10
**

III-V HBT for Circuit Designers • Current-Mode Logic • Emitter-Coupled Logic • ECL/CML Logic Examples • Advanced ECL/CML Logic Examples • HBT Circuit Design Examples

Stephen I. Long

University of California at Santa Barbara

**16.1 Design of MESFET and HEMT Logic Circuits
**

The basis of dc design, deﬁnition of logic levels, noise margin, and transfer characteristics were discussed in Chapter 16 using a DCFL and SCFL inverter as examples. In addition, methods for analysis of highspeed performance of logic circuits were presented. These techniques can be further applied to the design of GaAs MESFET, HEMT, or P-HEMT logic circuits with depletion-mode, enhancement-mode, or mixed E/D FETs. Several circuit topologies have been used for GaAs MESFETs, like direct-coupled FET logic (DCFL), source-coupled FET logic (SCFL), as well as dynamic logic families,1 and have been extended for use with heterostructure FETs. Depending on the design requirements, whether it be high speed or low power, the designer can adjust the power-delay product by choosing the appropriate device technology and circuit topology, and making the correct design tradeoffs.

**Direct-Coupled FET Logic (DCFL)
**

Among the numerous GaAs logic families, DCFL has emerged as the most popular logic family for highcomplexity, low-power LSI/VLSI circuit applications. DCFL is a simple enhancement/depletion-mode GaAs logic family, and the circuit diagram of a DCFL inverter was shown in Fig. 16.2. DCFL is the only static ratioed GaAs logic family capable of VLSI densities due to its compactness and low power dissipation. An example demonstrating DCFL’s density is Vitesse Semiconductor’s 350K sea-of-gates array. The array uses a two-input DCFL NOR as the basic logic structure. The number of usable gates in the array is 175,000. A typical gate delay is speciﬁed at 95 ps with a power dissipation of 0.59 mW for a buffered two-input NOR gate with a fan-out of three, driving a wire load of 0.51 mm.2 However, a drawback of DCFL is its low noise margin, the logic swing being approximately 600 mV. This makes the logic sensitive to changes in threshold voltage and ground bus voltage shifts. DCFL NOR and NAND Gate The DCFL inverter can easily be modiﬁed to perform the NOR function by placing additional enhancement-mode MESFETs in parallel as switch devices. A DCFL two-input NOR gate is shown in Fig. 16.1. If any input rises to VOH, the output will drop to VOL. If n inputs are high simultaneously, then VOL will be decreased because the width ratio W1/WL in Fig. 16.2 has effectively increased by a factor of n. There is a limit to the number of devices that can be placed in parallel to form very wide NOR functions. The

16-1

© 2003 by CRC Press LLC

16-2

Analog Circuits and Devices

FIGURE 16.1

DCFL two-input NOR gate schematic.

drain capacitance will increase in proportion to the number of inputs, slowing down the risetime of the gate output. Also, the subthreshold current contribution from n parallel devices could become large enough to degrade VOH, and therefore the noise margin. This must be evaluated at the highest operating temperature anticipated because the subthreshold current will increase exponentially with temperature according to:3,4

È Ê cV ˆ ˘ È Ê bV ˆ ˘ È Ê aV ˆ ˘ I D = I S Í1 - expÁ DS ˜ ˙ ÍexpÁ DS ˜ ˙ ÍexpÁ GS ˜ ˙ Ë VT ¯ ˙ Í Ë VT ¯ ˙ Í Ë VT ¯ ˙ Í ˚ ˚Î Î ˚Î

(16.1)

The parameters a, b, and c are empirical ﬁtting parameters. The ﬁrst term arises from the diffusion component of the drain current which can be ﬁt from the subthreshold ID–VDS characteristic at low drain voltage. The second and third terms represent thermionic emission of electrons over the channel barrier from source to drain. The parameters can be obtained by ﬁtting the subthreshold ID–VDS and ID–VGS characteristics, respectively, measured in saturation.5 For the reasons described above, the fan-in of the DCFL NOR is seldom greater than 4. In addition to the subthreshold current loading, the forward voltage of the Schottky gate diode of the next stage drops with temperature at the rate of approximately –2mV/degree. Higher temperature operation will therefore reduce VOH as well, due to this thermodynamic effect. A NAND function can also be generated by placing enhancement-mode MESFETs in series rather than in parallel for the switch function. However, the low voltage swing inherent in DCFL greatly limits the application of the NAND function because VOL will be increased by the second series transistor unless the widths of the series devices are increased substantially from the inverter prototype. Also, the switching threshold VTH shown in Fig. 16.1 will be slightly different for each input even if width ratios are made different for the two inputs. The combination of these effects reduces the noise margin even further, making the DCFL NAND implementation generally unsuitable for VLSI applications. Buffering DCFL Outputs The output (drain) node of a DCFL gate sources and sinks the current required to charge and discharge the load capacitance due to wiring and fan-out. Excess propagation delay of the order of 5 ps per fanout is typically observed for small DCFL gates. Sensitivity to wiring capacitance is even higher, such that unbuffered DCFL gates are never used to drive long interconnections unless speed is unimportant. Therefore, an output buffer is frequently used in such cases or when fan-out loading is unusually high. The superbuffer shown in Fig. 16.2(a) is often used to improve the drive capability of DCFL. It consists of a source follower J3 and pull-down J4. The low-to-high transition begins when VIN = VOL. J4 is cut off

© 2003 by CRC Press LLC

2(b) shows a modiﬁed superbuffer design that prevents this problem through the addition of a clamp transistor. Thus. J5 limits the gate potential of J3 when the output reaches VOH . and transient characteristics of SCFL circuits. The high-speed capability of SCFL stems from four properties of this logic family: small input capacitance. and the output can be pulled to VOL = 0 V in steady state. Figure 16. First. and J3 becomes active. The differential input signaling also improves the dc. therefore. 15. the power supply noise is greatly reduced as compared to other logic families. it is during this transition that the superbuffer can produce a current spike between VDD and ground.7 V. SCFL is a low-density logic family due to the complex gate topology. VOUT follows the DCFL inverter output. This occurs when Vout = VOH = 0.7 V is easily obtained on J3 . J4 attempts to discharge the load capacitance before the DCFL gate output has cut off J3 . ac. thus preventing the overdriving problem. has two drawbacks. Since this occurs one propagation delay after the input switched from low-to-high. even with the high functional equivalence taken into account. limited by forward conduction of the gate diodes being driven. superbuffers can become an on-chip noise source.2 (a). fast discharging time of the differential stage output nodes. a maximum VGS = 0. and (b) modiﬁed superbuffer with clamp transistor. J5 will limit the output current when Vout > 0. 16. J5 . driving the output to VOH.6 SCFL. so ground bus resistance and inductance must be controlled. Second. however. good drive capability. a buffered version of the basic differential ampliﬁer cell shown in Fig.7 V. SCFL dissipates more power than DCFL. is shown in Fig.Logic Design Examples 16-3 FIGURE 16. SCFL is characterized by high functional equivalence and reduced sensitivity to threshold voltage variations.5a The current-mode approach used in SCFL ensures an almost constant current consumption from the power supplies and. An SCFL inverter. and high Ft .4. J4 is driven into its linear region. Superbuffer schematic. This would degrade VOL of the subsequent stage due to voltage drop across the internal source resistance. Source-Coupled FET Logic (SCFL) SCFL is the preferred choice for very-high-speed applications. For a supply voltage of 2 V.3. There is also a risk that the next stage might be overdriven with too much input current when driven by a superbuffer. leading to the possibility of excess static current ﬂowing into the gates. This could happen because the source follower output is capable of delivering high currents when its VGS is maximum. J3 is cut off when the DCFL output (drain of J1) switches from high to low. In addition to higher speed. For the output high-to-low transition. © 2003 by CRC Press LLC .

3 Schematic diagram of SCFL inverter with source follower output buffering. level-shifting networks using diodes or source followers are required.16-4 Analog Circuits and Devices FIGURE 16. Series logic such as this also requires higher supply voltages in order to keep the devices in their saturation region. the resulting circuit — a 2-to-1 MUX.4. FIGURE 16. XOR gates. O A) are fed back to the A2 inputs. 2-to-1 MUXs. the clock is connected to B and the A outputs (OA. forming a new input AIN and A1 = A2 to complementary new input AIN . an XOR gate is created by – – – connecting A1 = A2 . The resulting circuit is a D-latch as seen in Fig. thus. The inputs to the two levels require different dc offsets in order for the circuit to function correctly. © 2003 by CRC Press LLC . If is the data are fed to the A1 input. If the A inputs are tied to the data signals and the B inputs are tied to the select signal.5. Finally. 16. This will increase the power dissipation of SCFL.4 SCFL two-level series-gated circuit. 16. and D-latches and ﬂip-ﬂops can be conﬁgured using this basic structure. SCFL Two-Level Series-Gated Circuit A circuit diagram of a two-level series-gated SCFL structure is shown in Fig.

sat .3) (16. a larger noise margin. levelshifting is needed between nodes A and B and the input to the next gate. VSW is calculated assuming all the current from T3 ﬂows only through T2. 16.2. and T4-T7 saturated. it needs to be noted that the larger switch transistors means increased input capacitance and decreased speed. Idss3 . since no current ﬂows through the other transistor.L ) are determined from the voltage drop across R3 and Eq.Y = Ids3 R1 = Idss3 R1 (16. in order to keep T1. VX. 16.5 SCFL D latch schematic. VSW is set by the ratio between the sizes of the switch transistors (T1. Assuming the saturation drain-source current of an FET can be described by the simpliﬁed square-law equation: Ids = bW(Vgs – VT ) 2 (16. The logic high and low levels on node X (VX. VS settles at a potential such that the drainsource current of the conducting transistor is exactly equal to the bias current. the sizes of all the switch transistors are kept the same size. Two cascaded latch cells with opposite clock phasing constitute a masterslave ﬂip-ﬂop.H) is © 2003 by CRC Press LLC . T3 is kept in saturation if the potential at node S is higher than VSS + Vds.Logic Design Examples 16-5 FIGURE 16.4) The noise margin is the difference between the minimum voltage swing required on the inputs to switch the current from one branch to the other (VSW) and the logic swing DVX. The potential at node S is determined by the input voltages to T1 and T2. Although a better noise margin is desirable.L = V dd – [Idss3 (R1 + R3)] (16. and b is a process-dependent parameter. The logic swing of the circuit shown in Fig. V X. the logic swing on nodes X and Y is DVX.2) where Idss3 is the saturation current of T3 at Vgs = 0 V. Depending on the design speciﬁcations.Y .6) For a ﬁxed current source size (W3). T4-T7) and T3. Assuming T3 is in saturation. Since all FETs need to be kept in the saturation region for the correct operation of an SCFL gate. T2.H. The minimum logic high level at the output node B (VOB. the smaller the voltage swing required to switch the current and. noise margin and speed need to be traded off. W is the FET width. hence.H = Vdd – (Idss3 R3) V X. the larger the size of the switch transistors.4 is determined by the size of the current source T3 and the load resistors R1 and R2 (R1 = R2).5) where VT is the threshold voltage.T2. For symmetry reasons. VSW = VT (W 3 W 2) (16.

less power to the differential © 2003 by CRC Press LLC .min – (VOA. The saturation condition for the upper switch transistors.9 shows that the lower switch transistors are kept in saturation if the level-shifting difference between the A and B outputs is larger than the FET saturation voltage.H ≥ Vds. is determined by the minimum voltage at nodes A and B and the drain voltage of T1 and T2. Only W3 in the differential stage and W9 among the level-shifters are unknown at this stage. consequently. the voltage drop across the diodes is partially determined by the ratio (WD /W9).2 to 16.H – VOA.sat + Vgs = V ss + Vds.sat ( )) ( ) (16. 16.sat Substituting Eq.sat + VSW (16. Since diodes are used for levelshifting. poor reproducibility of VD will result in this case.11 allows the determination of the minimum amount of level-shifting required between nodes A and B to the outputs VA. the drain voltages of T1 and T2 are determined by the voltage applied to the A inputs.13. VA. Vgs8 should be kept below 0. the ratio between the power dissipated in the differential stage and the output buffers determines how fast the outputs are switched.sat + VSW + Vth To keep T9 and T11 in saturation.sat (16. however. Since this resistance is often process dependent and difﬁcult to reproduce.H ≥ V ss + Vds. the current sources (W9.sat > VD. 16. 16. and the diode (WD).13 can be used for designing the level shifters. The ratio between the widths of the source follower and the current source (W8/W9) determines the gate-source voltage of the source follower (Vgs8).11 using Eq. Operating Schottky diodes at high current density will result in higher voltage drop.10 yields (16.13) Equations 16. VD. Assuming the current source width (W9) is ﬁxed. the minimum difference between the two outputs is one diode voltage drop. The relation between W3 and W9 can be determined only by considering transient behavior.H ≥ V ds. This ratio should not be made too small.VSW . 16.H ≥ Vss + V ds. If fast switching at the outputs is desired. Ratios between most device sizes can be determined by choosing the required noise margin and logic swing.H – VOB. more diodes are required between the A and B outputs.H . All other device sizes can be expressed in terms of these two transistor widths. but this voltage will be partially due to the IDRS drop across the parasitic series resistance. The saturation condition for T1 and T2 is VOA. The dc design of the two-level series-gated SCFL gate in Fig. requires that (16.4 into Eq. T4 to T7. If Vds.H – VSW – Vth – VS = VOA. For a given total power dissipation. 16.8) As with the voltage on node S.VOA . W11).5 V to prevent gate-source conduction. 16.H – VSW – Vth) ≥ Vds.9) Equation 16.11) Rewriting Eq.sat (16. W10).12) Equation 16.sat + Idss3 * R1 – Vth – VSW (16. more power needs to be allocated to the output buffers and.4 can be accomplished by applying Eqs.8 to 16.7) VOB.Idss 3 * R1 + R3 .Vth ≥ Vds.8 gives the minimum power supply range Vdd – Vss ≥ Idss3 * (R1+R3) + 3Vds.16-6 Analog Circuits and Devices VOB. The design parameters available in the level-shifters are the widths of the source followers (W8.10) (V dd .

A simpliﬁed schematic of a 2. of 2. for example. 16. The design strategies employed in the previous subsection can now be further applied to a high-speed 4:1 MUX. While this allocation will ensure faster switching at the output. Finally. The MSFF in the ﬁgure is simply a master-slave ﬂip-ﬂop containing two D-latches. as shown in Fig. DMUXs. 16. stage. The inherent propagation delay of the ﬂip-ﬂops ensures that the signals are passed through the selector only when they are stable.6.6 Advanced MESFET/HEMT Design Examples High-Speed TDM Applications The need for high bandwidth transmission systems continues to increase as the number of bandwidthintensive applications in the areas of video imaging.6. To accomplish this. GaAs MESFET technology has been employed extensively in the design of these high-speed circuits because of the excellent intrinsic speed performance of GaAs. and data communication (such as database sharing and database warehousing) continues to grow.5-Gb/s optical communication system. all transistors and diodes are made twice as wide while all resistors are reduced by half. If twice as much power is allocated to a gate. and switches capable of operating in the Gb/s range are crucial for the operation of these systems. The delay is usually implemented © 2003 by CRC Press LLC . multimedia. a delay is added between the CLK signal and the clock input to this ﬂip-ﬂop.6 2.5 Gb/s communication system is shown in Fig. it is useful to note that scaling devices to make a speed/power tradeoff is simple in SCFL. and care needs to be taken to obtain the best possible phase margin at the input of the last ﬂip-ﬂop. The 2:1 MUX at the second stage takes the two outputs of the ﬁrst stage and merges it into a single output at four times the primary input bit rate. the switching speed of the differential stage is reduced because of the reduced current available to charge and discharge the large input capacitance of the output buffers. The architecture is highly pipelined.5 Gb/s and 10 Gb/s. The 4:1 MUX is constructed using a tree-architecture in which two 2:1 MUXs merge two input lines each into one output operating at twice the input bit rate. ensuring good timing at all points in the circuit.6 The interface between the two stages of 2:1 MUXs is timing-critical. SCFL is especially well suited for these circuits where high speed is of utmost importance and power dissipation is not a critical factor. As seen in Fig. The PSFF is a phase-shifting ﬂip-ﬂop that contains three D-latches and has a phase shift of 180° compared with an MSFF.7. It was shown that the two-level series gated SCFL structure could be easily conﬁgured into a D-latch. 16. This has led to the development of optical communication systems with transmission bit rates.Logic Design Examples 16-7 FIGURE 16. MUXs.

Chips were fabricated that implemented multiplexers.0 Gb/s. data decision. frequency dividers. and a 2:4 demultiplexer circuit. A complete 40-Gb/s system has been implemented in the laboratory with 0. The high-speed static dividers used the super-dynamic FF approach.1-µm InAlAs/InGaAs/InP HEMT ICs as reported in Refs.10 The SCFL circuit approach was employed. Very-High-Speed Dynamic Circuits Conventional logic circuits using static DCFL or SCFL NOR gates such as those described above are limited in their maximum speed by loaded gate delays and serial propagation delays. VSC880.16-8 Analog Circuits and Devices FIGURE 16. The parallel inputs accept data at rates up to 625 Mb/s and the differential serial data output presents the data sequentially at 2. using logic gates because their delays are well characterized in a given process. Frequency divider applications that require clock frequencies above 40 GHz have occasionally employed alternative circuit approaches which are not limited in the same sense by gate delays and often use dynamic charge storage on gate nodes for temporarily holding a logic state. demultiplexers.2-µm AlGaAs/GaAs/AlGaAs HEMT quantum well device technology has also demonstrated 40-Gb/s TDM system components. but it is still limited to 1/2tD at best. The 40-Gb/s TDM application is the next step.7 High-speed 4:1 multiplexer (MUX). photodiode preampliﬁers. a retiming MSFF will be needed at the output of the 4:1 MUX. For example. parallel-to-serial data converter. These approaches have been limited to relatively simple circuit functions such as divide-by-2 or -4. a typical DCFL NOR-implemented edge-triggered DFF has a maximum clock frequency of approximately 1/5tD and the SCFL MSFF is faster.5 and 10 Gb/s data rates for optical ﬁber communication applications. A single chip has been reported that included clock recovery.9 A 0. The VS8004 4-bit MUX is a high-speed. 7 and 8. synchronous with the differential high-speed clock input. but it is challenging for all present semiconductor device IC technologies. higher speeds appear to require heterojunction technologies. wideband dc 47-GHz ampliﬁers. Vitesse Semiconductor has several standard products operating at the Gb/s range fabricated in GaAs using their own proprietary E/D MESFET process. has serial data rates of 2.2 While the MESFET technologies have proven capable at 2. © 2003 by CRC Press LLC . The 4:1 MUX is a good example of an application of GaAs MESFETs with very-high-speed operation and low levels of integration. decision circuits. Output jitter can be minimized if 50% duty-cycle clock signals are used. and limiting ampliﬁers. the 16 ¥ 16 crosspoint switch.5 Gb/s. Otherwise. For example.

The maximum and minimum clock frequencies of this circuit can be calculated from the gate delays of the n series inverters as shown in Eqs. and pass transistors to gate a short chain of inverters.9 and quasi-differential FF17 are examples of circuit designs emphasizing this objective.16 FETs J3 and J4 are operating in their ohmic regions and act as variable resistors.12 These have generally used DCFL or DCFL superbuffers for the inverters. The variation in VGS1 and VGS2 cause the oscillator to subharmonically injection-lock to the input source. The latter has achieved 16-GHz clock frequency with approximately 2 mW of power per FF. Here. 16. generally requiring high power per inverter in order to push the power-delay product to its extreme high-speed end. 11. ffmax = 1 t1 + nt D a t1 + nt D (16.14 and 16.) The dynamic frequency divider (DFD) technique is one of the well-known methods for increasing clock frequency closer to the limits of a device technology.8 shows a DFD circuit using a single-phase clock. ©1989 IEEE. For a 50% clock duty cycle. a divide-by-4 ratio was demonstrated with an input frequency of 75 GHz and a power dissipation of 160 mW using a 0. This divider also operated in the 59–64 GHz range with only –10 dBm RF input power. The cross-coupled inverter pair can be made small in width. utilizes an injection-locked push-pull oscillator (J1 and J2) whose free running frequency is a subharmonic of the desired input frequency. J1 and J2. since its serial delay is not in the datapath. 16. The parameter “a” is the duty cycle of the clock.Logic Design Examples 16-9 FIGURE 16. efforts have also been made to beat the speed limitations of a technology by dynamic design methods while still maintaining minimum power dissipation. a cross-coupled inverter pair as a latch to reduce the minimum clock frequency.12 The power dissipation was relatively high. (Ref. 16. But the series inverter chain must be designed to be very fast. with permission. Fig. Finally. Since fan-out is low. For an example.9.14) ffmin = (16. The frequency range is limited by the tuning range of the oscillator. An odd number n is required to force an inversion of the data so that the circuit will divide-by-2. 440 mW. the intrinsic delays of an inverter in a given technology can be approached.15) Clock frequencies as high as 51 GHz have been reported using this approach with a GaAs/AlGaAs P-HEMT technology.8 Dynamic frequency divider (DFD) divide-by-2 circuit. Here. Other DFD circuit approaches can also be found in the literature. and tD is the propagation delay of the DCFL inverters. about 2 octaves of frequency variation was demonstrated.13-15 A completely different approach. as shown in Fig. t1 is the propagation delay of the pass transistor switches.15. © 2003 by CRC Press LLC .1-µm InP-based HEMT technology with fT = 140 GHz and fmax = 240 GHz. The quasi-dynamic FF8. In this example. the range of minimum to maximum clock frequency is about 2 to 1.11.

sigma-delta ADCs with very high oversampling rates. During that time. as discussed below. During the same time.16-10 Analog Circuits and Devices FIGURE 16. III-V HBT for Circuit Designers III-V HBTs and Si BJTs are inherently bipolar in nature.) 16. I2L logic topologies as well as novel logic families with advanced quantum devices (such as resonant tunneling diodes17a) in the hopes of achieving any combination of high-speed. III-V HBTs have found success in telecom and datacom lightwave communication circuits for SONET/ATM-based links that operate from 2. with myriad similarities and a few essential differences. can be traced to three essential aspects: (1) heterojunction vs. III-V HBTs demonstrated their potential integration limits with an I2L 32-bit microprocessor18 and benchmarked its high-speed ability with an ECL 30-GHz static master/slave ﬂip-ﬂop based frequency divider.9 Injection-locked oscillator divide-by-4. (Ref. HBTs also dominate the high-speed data conversion area with Nyquist-rate ADCs capable of gigabit/gigahertz sampling rates/bandwidths. and high-integration level. In these applications. advances in Si based technology. the primary requirement is ultra-high-speed performance with LSI (10 K transistors) levels of integration. microwave integrated circuits. low-power. First. Consequently. 16. The traditional logic families developed for the Si BJTs serve as the starting point for high-speed logic with III-V HBTs. As HBT technology evolved into a mature production technology in the mid-1990s. With permission. Thus. from a circuit point of view. the dominant logic type used in HBT designs is based on non-saturating emitter coupled pairs such as ECL and current-mode logic (CML). both share many striking similarities and some important differences.2 HBT Logic Design Examples From a circuit topology perspective. which is the focus of this chapter. ©1996 IEEE. and direct digital synthesizers with gigahertz clock frequencies and ultra-low spurious outputs. and power ampliﬁer markets. and. If the base composition is also © 2003 by CRC Press LLC . both III-V HBTs and silicon BJTs are interchangeable. the primary advantage of a base–emitter heterojunction is that the wide bandgap emitter allows the base to be doped higher than the emitter (typically 10 to 50X in GaAs/AlGaAs HBTs) without a reduction in current gain. it was clear that III-V HBT technology had a clear advantage in high-speed digital circuits. Alternatively. CML. DTL. This translates to lower base resistance for improved fmax and reduces base width modulation with Vce for low output conductance. the base can be made thinner for lower base-transit time (tb) and higher ft without having Rb too high. homojunction. (2) III-V material properties. and (3) substrate properties. have demonstrated that parallel circuit algorithms implemented in a technology with slower low-power devices capable of massive integration will dominate most applications. HBTs have implemented ECL. in the high-speed digital arena. The key differences between III-V HBT technology and Si BJT technology.5 to 40 Gb/s. Today. During the period of intense HBT development in the 1980s and early 1990s. especially CMOS. III-V-based technologies such as HBTs and MESFET/HEMT have been relegated to smaller but lucrative niche markets. Today.

and the heavy use of implants and diffusion for doping silicon devices. lowloss transmission lines. so III-V HBTs typically have a high Johnson ﬁgure of merit (ft * breakdown voltage) compared with Si. With short collectors. This allows for the formation of high-Q inductors. unlike the resistive silicon substrate. The difference in potential between Vin and Vin¢ © 2003 by CRC Press LLC . For a GaAs/AlGaAs HBT. This results in a common-emitter I–V curve offset from the off to saturation transition. a larger bandgap material in the collector can increase the breakdown voltage of the device and reduce the I–V offset. The differential inputs (Vin and Vin¢) are applied to the bases of Q1 and Q2. which minimizes parasitic capacitance to ground through the substrate. however. Since GaAs/AlGaAs and GaAs/InGaP have wider bandgaps than Si. The thermal time constant for GaAs/AlGaAs HBTs is on the order of microseconds.7 V. the SiO2 layer is typically thin resulting in reduced but still signiﬁcant capacitive coupling across this thin layer. so PNP transistors are not typically included in an HBT process. and the loss is not limited by the resistive substrate. and interconnect step height coverage issues limit the practical structure to one device type. Second. resulting in observed self-heating effects. the RF performance of small III-V HBT devices can be measured directly on-wafer without signiﬁcant de-embedding of the probe pads below 26 GHz. the substrate contact as in Si BJTs is unnecessary with III-V HBTs. With a highly doped base. the output conductance of HBTs at RF (> 10 MHz) is low but positive. the turn-on voltage of the B–E (Vbe. and longer interconnects that can be operated in the 10’s of GHz. Although BESOI and SIMOX Si wafers are insulating. InP-based HBTs can have Vbe. The higher mobility in the collector can also lead to HBTs with lower turn on resistance in the common emitter I–V curves. signiﬁcant reductions in tcscl can result.10.19 Most III-V substrates have a lower thermal conductivity than bulk Si. The base–collector turn-on voltage is typically on the order of 1 V in GaAs-based HBTs. Third. but signiﬁcantly reduced Cbc for high fmax.Logic Design Examples 16-11 graded from high bandgap to low.4 V vs. When HBTs are designed to exploit this effect. however. The wide bandgap material typically results in higher breakdown voltages. III-V semiconductors typically offer higher electron mobility than Si for overall lower tb and collector space charge layer transit times (tcscl). Furthermore. this results in observed negative output conductance in the commonemitter I–V curve measured with constant Ib. The other key material differences between III-V vs. Since thermal effects cannot track above this frequency. III-V HBTs typically use epitaxial growth techniques. The CML buffer is a differential ampliﬁer that is operated with its outputs clipped or in saturation.on on the order of 0.on) junction is typically on the order of 1.and SiGe-based bipolar transistors. These key factors contribute to the differences between HBTs and BJTs in terms of fabrication. the GaAs substrate used in III-V HBTs is semi-insulating. many III-V materials exhibit velocity overshoot in the carrier drift velocity. With a heterojunction B-E and a homojunction B-C. this can also be used to form longer collectors with still acceptable tcscl . an electric ﬁeld can be established to sweep electrons across the base for reduced tb and higher ft. silicon materials are the lack of a native stable oxide in III-V. the line capacitance is typically dominated by parallel wire-to-wire capacitance. Therefore. 0. the higher electron mobility can result in ultra-high ft . Current-Mode Logic The basic current-mode logic (CML) buffer/inverter cell is shown in Fig. In fact.9 V for advanced high-speed Si BJT. the junction turn-on voltage is higher in the B-E than it is in the B-C. if a heterojunction is placed in the base–collector junction. Furthermore. This effect does result in a small complication for HBT models based on the standard Gummel Poon BJT model. This allows Vce to be about 600 mV lower than Vbe without placing the device in saturation. most mature production technologies capable of LSI integration levels are based on AlGaAs/GaAs or InGaP/GaAs. 16. For interconnects. This offset is approximately 200 mV in GaAs/AlGaAs HBTs. the extensive use of poly-Si in silicon-based processes. base punch-through is not typically observed in HBTs and does not limit the ft-breakdown voltage product as in high-performance Si BJTs and SiGe HBT with thin bases.

determines which transistor Ibias is steered through. A current mirror (Qcs and Rcs) sets the bias (Ibias) of the differential pair. Vout ﬂoats to ground for a logic high. causing Vout¢ to drop for a logic low. the logic low is pulled up by a RC time constant. it is possible that the risetime is slower than the falltime. As this limit approaches. Rc is the collector resistance. this CML stage would be an inverter instead of a buffer. Cbed is the B–E diffusion capacitance. As a result. and that may result in some complications with high-speed data. the transit time is dominated by the device gm and device capacitance.Low). With a large capacitive loading.10 Standard differential CML buffer with a simple reference generator. Cbej is the base–emitter junction capacitance. qIc/nkT is the transconductance (gm). With Q2 off. Q1 is on and Q2 is off. The logic high VOH of a CML gate is 0 V. tec is eventually limited by tb and tcscl . the logic high is actively pulled to a logic low. At low currents. With a GaAs basecollector turn-on voltage near 1V.16) where tec is the total emitter-to-collector transit time. This is an essential parameter in determining the performance of CML logic. 500 to 600 mV forward-bias is typically tolerated without any saturation effects. the ft dependence on Ic is as follows: 1 2pft = tec = nkT qIc C bej + C bc + C bed + R c C bej + C bc + t b + tcsc l ( ( )) ( ) (16. the outputs of one stage directly feed the inputs of another CML gate.High > Vin. this bias shortens the base-collector depletion region. The logic low output is determined by VOL = –RL1Ibias . For highspeed operation. In fact. Ibias completely ﬂows through RL1. the base-collector of the “on” transistor is slightly forward-biased (by 400 mV in this example). In HBTs. If the terminal assignment of Vout and Vout¢ were reversed. As a result. As the transistor is turned on. Vce (fmax suffers due to increase in Cbc). maximum logic swing of a CML gate is constrained by the need to keep the transistors out of saturation. and tcscl is the collector space charge layer transit time. the traditional logic low of a CML gate is –400 mV. With RL1/RL2 = 200 Ws. however. As the bias increases. resulting in a voltage drop across either load resistance RL1 or RL2. resulting in the highest ft vs.16-12 Analog Circuits and Devices FIGURE 16. and Ibias = 2 mA. As CML gates are cascaded together. it is necessary to keep the switching transistors out of saturation. Consequently. Kirk effect typically © 2003 by CRC Press LLC . If Vin = VOH and Vin¢ = VOL (Vin. Cbc is the base-collector capacitance. tb is the base transit time. as the transistor is turned off.

a second level is created through a © 2003 by CRC Press LLC . With the outputs at VoutA/VoutA¢ and 400 mV swing from the differential pair. the differential logic level should not be allowed to drop below 225 mV. one can assume that ft is the gain bandwidth product. With such low levels and limited gain. only 3 to 4 kT/q is needed to switch the transistors and overcome the noise ﬂoor. With a 225-mV swing vs. Nevertheless.18) where Cs is collector-substrate and interconnect capacitances. In some HBT technologies. In most applications. the reference generators used today typically result in a 2% variation in bias current from –40 to 100 C with a 10% variation in power supply.ext = gm. This implies that changes in the power supply are absorbed by the base–collector junction of Qcs . With constant bias. the average value of Vcm (around –1. With a 200-ohm load resistor. and it is important that this transistor is not deeply saturated. In the above example. gm. Furthermore. divided by the logic swing. the emitter followers (Qef1 and Qef2 ) shift the CML logic level down by Vbe .5 V). Vref is typically near –3. as Vee moves by ±10%. the maximum speed is ft/(gmRL). Both equations show that the load resistor and bias (which affects gm and device capacitors) have a strong effect on performance. Much effort has been invested in the design of the reference generator to maintain constant bias with power supply and temperature variation. the small-signal model. With Vee set at –5. Assuming the internal parasitic emitter resistance RE is 10 ohms and using the fact that gm. the ﬁrst level ECL logic high is –1. Thus.4 V) remains constant.cml = 1 + g m R L R bC bc + R b C be + C d + 2C bc + 1 2 C be + 1 2 C d ( ) ( ) ( ) gm (16. at 1 mA average bias.int). then the voltage drop across Rcs remains constant. which decreases ft . where the simplest generator is shown in Fig. Emitter-Coupled Logic By adding emitter followers to the basic HBT CML buffer.4 V and the ECL logic low is –1.4 V.17) where Cd is the diffusion capacitance of gm(tb + tcscl). large-signal models are typically used to numerically compute the delay in order to optimize the performance of a CML gate.Logic Design Examples 16-13 starts to increase tb/tcscl . it does show that high-speed CML logic desires high device bias and low logic swing. With the voltage gain set at gmRL. by considering the difference in charge storage at logic high and logic low. In some HBTs. resulting in decreasing noise margin.3 (Elmore) leads to the following approximation of a CML delay gate with unity fan-out:19a td . Although this estimate is quite rough. Since the device goes from the cutoff mode to the forward active mode as it switches. frequency-domain approach described in Chapter 16.8 V. 16. For a rough estimate of the CML maximum speed without loading. the output may not saturate to the logic extremes. 400 mV.int /(1 + REgm. This makes the design of bandgap reference circuits quite difﬁcult in most HBT technologies. In practice. the voltage gain is approximately 5. The bias of CML and ECL logic is typically set with a bias reference generator. As a rule of thumb. In HBT. In most differential circuits. the effective extrinsic gm is 1/36 mhos. the gate delay is difﬁcult to predict analytically with small-signal analysis.11. the maximum bias may be constrained by thermal or reliability concerns.5.int = 1/26 S at room temperature. the HBT ECL buffer is formed in Fig. 16. optimal performance is typically achieved when Ibias is near Ic. the effective CML gate capacitance can be expressed19b as C cml = C be 2 + 2C bc + C s + t b + tcsc l ( ) RL (16.maxft or Ic. With this in mind. the peak fmax occurs a bit after the peak ft. so Vref moves by the change in power supply (about ±0. Since the logic levels are referenced to ground.2 V. the voltage drop across Rcs is set to around 400 mV. which complicates the design of the reference generator.10. the maximum current density of HBTs is typically on the order of 5 ¥ 104 A/cm2. From a dc perspective. With a 70-GHz ft HBT process. the maximum gate bandwidth improves to 23 GHz from 13 GHz.maxfmax . Nevertheless. secondary effects of heterojunction design typically result in slightly varying ideality factor with bias. the maximum switching rate is about 13 GHz. For some ECL logic gates.

the output impedance of the EF becomes increasingly inductive. which makes it an ideal buffer. if the Ibias1/Ibias2 is lowered to 1 mA from 2 mA. in a 50 GHz HBT process. tf = 9 ps. at some point with high bias. RL1/RL2 = 150 W). © 2003 by CRC Press LLC . For example.16-14 Analog Circuits and Devices FIGURE 16. From an ac point of view. the impedance transformation of the EF stage results in slightly reduced gate delays and signiﬁcant improvements in the rise/falltimes. it is possible to obtain high-speed operation with the EF biased lower than would be necessary to obtain the maximum device ft. With the above ECL buffer modiﬁed for level 2 (level shifted) outputs. increases the RC time constant. In comparison. In comparison with CML gates. Ibias1/Ibias2 = 2 mA. 1/gm). The typical Schottky diode turn-on voltage for GaAs is 0.11 Standard differential ECL buffer with outputs taken at two different voltage levels. emitter followers have high input impedance (approximately b times larger than an unbuffered input) and low output impedance (approx. current mirrors (Qcs1/Qcs2 and Rcs1/Rcs2 ) are typically used. This change. tf = 13 ps. and tr = 16 ps. Schottky diode voltage shift (Def1/Def2). the effect of loading is reduced. with td = 15 ps. The addition of a series resistor between the EF output and the next stage can help to dampen the ringing by increasing the real part of the load. Ibias = 2 mA. the performance is only slightly lower with tD = 14. With a threefold increase in Pdiss. however. which usually results in a signiﬁcant reduction in performance.7 V. When combined with large load capacitance (as in the case of high fan-out or long interconnect). however. As the EF bias is increased. a CML buffer (fan-out = 1. Consequently.5 V for a logic low. and tr = 18 ps. an ECL buffer with level 1 outputs (fan-out = 1. RL1/RL2 = 150 W) has td = 14 ps. the performance is still quite high. Although tD approaches the CML case. Ibias = 2mA. and higher fan-out. it may result in severe ringing in the output that can result in excessive jitter on data edges. so the output at VoutB/VoutB¢ is –2. its driving ability is also increased.1 V for a logic high and –2. Current mirrors offer stable bias with logic level at the expense of higher capacitance. faster edge rates. yielding increased bandwidth. the propagation delay (tD) is 14. since the differential pair now drives a higher load impedance. tf = 11 ps. while resistors offer lower capacitance but the bias varies more and may be physically quite large.2 ps. The cost of this improvement is the increase in power due to the bias current of the emitter followers. In general. With the ECL level 1 buffer. which is signiﬁcantly higher than the differential pair. emitter followers tend to have bandwidths approaching the ft of the device. the HBT ECL levels differ quite a bit from the standard Si ECL levels. In general.8 ps with a risetime [20 to 80%] (tr) of 31 ps and a falltime [20 to 80%] (tf ) of 21 ps. the tf and tr are still signiﬁcantly better. Although resistors can be used to bias Qef1/Qef2 . and tr = 22 ps.

typically two levels of transistors are used to steer the bias current. changing the impedance of the EF bias source (high impedance current source or resistor bias) does not have a signiﬁcant effect on the ringing. The choice of logic input levels is typically dictated by the design tradeoff between bandwidth.Logic Design Examples 16-15 In practice. Figure 16. In general. ECL and CML logic is mixed throughout high-speed GaAs/AlGaAs HBT designs. it is very difﬁcult to cascade two HBT emitter followers without causing the current source to enter deep saturation. All other combinations will make Vout = VOL. the top can be driven with either the CML or the ECL1 inputs. only when VinA and VinB are high will Ibias current be steered into the load resistor that makes Vout = VOH. as required by the AND function. it is only necessary to add the emitter followers. To form more complex logic functions. although the power dissipation is higher. For the ECL counterpart. several source followers are cascaded together to increase the input impedance and lower the output resistance between two differential pairs for high-bandwidth drive.5 V). if the output terminal labels were reversed. In some FET DCFL designs.12 Two-level differential CML AND gate. and ECL2 (–2. The top input is VinA/VinA¢. ECL/CML Logic Examples Typically. 16.1/–2. The levels are CML (0/–400 mV). The bottom input is VinB/VinB¢. which places a very real constraint on bandwidth. fan-out. there are three available logic levels that can be used to interconnect various gates. ECL gates are typically used for the high-speed sections due to signiﬁcant improvement in rise/falltimes (bandwidth) and drive ability. the primary method to control the ringing is through the EF bias. and the bottom level can be driven by ECL1 and ECL2 levels. As seen in Fig.4/–1/8 V).12 shows an example of an CML AND/NAND gate. As a result. and fan-out.12. Due to the differential nature. and jitter that needs to be considered in the topology of real designs. Due to voltage headroom limits. As a result. this would be a NAND gate. power dissipation. © 2003 by CRC Press LLC . In general. FIGURE 16. ECL1 (–1.

however. a 1:2 DEMUX is formed as shown in Fig. 16. With the 2:1 MUX in mind. This also implies that Vcm2 is around –3. then a basic 2:1 MUX cell is formed.14. the MSB (ECL1) and LSB (ECL2) determine which of the four inputs are selected.7 V. the current source holds Ie in Qcs constant. As Vee becomes less negative. 16. which places Qcs closer into saturation. if each top differential pair had separate output resistors with a common input. forming the XOR/XNOR block.1 V). the lower stage (Q3/Q4) has a B-C forward-bias of 0. which may result in a slight saturation.2 to possibly –6 V. the worst-case Qcs saturation occurs at low temperature.8 V. In saturation. 16. which results in an acceptable nominal 100 mV forward-bias on the current source transistor (Qcs).15.13 Two-level differential CML OR/NOR gate. This concept can be further extended to a 4:1 MUX if the top signals are CML and the control signals are ECL1 and ECL2. If the current source reference can support the increase in Ib . 16.16. then Ic decreases. Fig. 16. For the worst-case voltage headroom.16-16 Analog Circuits and Devices FIGURE 16. If the top differential pairs are thought of as selectable buffers with a common output as shown in Fig. Here.17. © 2003 by CRC Press LLC . For HBTs. so if Ib increases (due to saturation). and the worst-case saturation for Q3 /Q4 occurs at high temperature since Vbe changes by –1. It is possible to decrease the forward-bias of the lower stage by using the base-emitter diode as the level shift to generate the second ECL levels. In Fig. VinB /VinB¢ determines which input (VinA1/VinA1¢ or VinA2/VinA2¢) is selected to the output. the power supply voltage needs to increase from –5. Here. then the bias of only the local saturated differential pair starts to decrease leading to the potential of lower speed and lower logic swing. resulting in Vcm1 of –2. By using the bottom differential pair to select one of the two top differential pairs. Otherwise. With the two-level issues in mind.4 mV/C and Vdiode = –1. the change in Vee is absorbed across Qcs. For some current source reference designs that cannot source the increased Ib. Vout = VOH. many other prime logic functions can be implemented. the increased loading due to saturated Ib may lower Vref . This design is similar to an AND gate except that Vout = VOL if both VinA and VinB are low. as shown in Fig. VinA/VinA¢ is driven with ECL1 levels.1 mV/C (for constant-current bias).5 V. With an ECL2 high on VinB (–2. which would have a global effect on the circuit bias.13 illustrates the topology for a two-level OR/NOR gate. the top pairs are wired such that Vout = VOL if VinA = VinB.

which results in asymmetric behavior and reduced bandwidth. However.18. The second pair is conﬁgured as a buffer with positive feedback. the delay of the top input is shorter than the lower input. 16. forming a latch. it must ﬁrst turn on either Q1/Q2 . Likewise. the top transistor forms a cascode stage with the lower differential ampliﬁer. © 2003 by CRC Press LLC . which. in large-signal logic. This added delay results in a larger propagation delay for the bottom pair vs. 16. This can lead to higher bandwidths and reduced rise/falltimes. the bottom transistor must ﬁrst turn on the top cascode stage before the output can change. it forms the basic master-slave ﬂip-ﬂop. As VinB = VOL.Logic Design Examples 16-17 FIGURE 16. The positive feedback causes any voltage difference between the input transistors to be ampliﬁed to full logic swing and that state is held as long as the bias is applied. the last value stored in the buffer is held.13.14 Two-level differential CML XOR gate. the propagation delay is short. is triggered on the falling edge of the ECL2 level. the top switching pair. as the ﬁrst buffer is selected (VinB = VOH). leading to the longest propagation delay. In this case. as in Fig. With the top-level transistor on. the ﬁrst differential pair is conﬁgured as a buffer. if Q1 or Q2 switches with Q3 on or if Q4 switches. This is shown in Fig. this can result in as much as a 10-ps delay from the rising edge of the clock to the sample point of the data. the cascode conﬁguration (common base on top of a common emitter stage) typically reduces the Miller capacitance for higher bandwidth. If Q3 switches. Advanced ECL/CML Logic Examples With small signal ampliﬁers. the output is transparent to the input. When two of these blocks are connected together in series. This issue must be taken into account in determining the optimal input data phase for lowest bit errors when dealing with digital data. The last primary cell of importance is the latch. in this case. the longest delay limits the usable bandwidth of the AND gate. in the XOR case. In the case of the OR/NOR. Here. For a 10-GHz ﬂip-ﬂop. With this in mind.

15 Two-level 2:1 differential CML MUX gate. FIGURE 16.16 Three-level 4:1 differential CML MUX gate.16-18 Analog Circuits and Devices FIGURE 16. © 2003 by CRC Press LLC .

© 2003 by CRC Press LLC .18 CML latch.17 Two-level 1:2 differential CML DEMUX gate.Logic Design Examples 16-19 FIGURE 16. FIGURE 16.

but some of the noise margin may be sacriﬁced. Figure 16. Ibias1 = Ibias2 = Ibias3 .12. 16. then Vout = VOH.16-20 Analog Circuits and Devices FIGURE 16. In this case.20 shows an example of a single-level XOR gate with a similar input level reference. Ignoring Ibias3 .20 Single-level CML quasi-differential XOR gate. © 2003 by CRC Press LLC .19 Single-level CML quasi-differential OR gate. One solution to the delay issue is to use a quasi-differential signal. a reference generator of (VH + VL)/2 is applied to VinA¢. The additional Ibias3 is used to make the output symmetric.19. Here. when VinA is not equal to VinB. In Fig. 16. a single-ended singlelevel OR/NOR gate is shown. If either of the VinA1 or VinA2 is high. Ibias1 and Ibias2 are used to force Vout¢ = VOL. This design has more bandwidth than the two-level topology shown in Fig. When VinA = VinB. Vout = Vout¢ since FIGURE 16.

In poorly designed cascode stages.5. The interconnect capacitance is on the order of 5 to 25 fF for adjacent to nearby gates. This can result in some “memory” FIGURE 16. Assuming that the voltage gain is 5. The cascode requires that the input level be either ECL1 or ECL2 to account for the Vbe drop of the cascode. the corner point between the fast-rising edge to the slowerrising edge may occur near the 20/80% point. the noise margin is somewhat reduced due to the quasi-differential approach and the outputs have a common-mode voltage offset of RLIbias . The reduction of the Miller effect through cascoding reduces the effect of both the internal transistor Cbc and load capacitance due to Cbc of the other stages. the cascode bases are connected to ground. This design results in higher speed due to the single-level design. a cascode stage may result in higher bandwidth and sharper rise/falltimes with a slight increase in propagation delay. Due to the 400-mV logic swing. its actual voltage varies with time (large RC discharge compared to the switching time).d capacitance when the transistor is on is of the order of 50 to 200 fF. however. The basecollector capacitance of the driving pair. when the transistor is off. is typically less than 6 fF. the collector swings only about 60 mV per decade change in Ic . the effective Cbc or Miller capacitance is about 140 fF. the interconnect capacitance. Since the base of the cascode is held at ac ground. Figure 16. For higher swings. Cbe. which results in the reduced rise/falltimes. In a standard differential pair. The Cbe. To remedy this. the increased charge stored in both transistors that has to discharge through an RC time constant may result in a slower edge rate near the logic high of a rising edge. and the input capacitance of the next stage. the Miller effect is greatly reduced. In these situations. resulting in an indeterminate state. Ibias3 is added to Vout to make the outputs symmetric. The base-collector depletion capacitance is on the order of 25 fF. © 2003 by CRC Press LLC . As both of the transistors in a cascode turn off.j . These rough numbers show that the Miller effect has a signiﬁcant effect on the effective load capacitance. canceling out some of the desired gains.21 shows a CML gate with an added cascode stage. the Miller effect increases both the effective internal Cbc as well as the external load. the Miller effect is not seen at the input of the common-base stage as the output voltage swings. especially at the logic transition region. From the common-emitter point of view. the output load capacitance can be broken into three parts. thus. the cascode bases can be biased to a more negative voltage to avoid saturation. with the emitter node of the off common-base stage ﬂoating in a high-impedance state.Logic Design Examples 16-21 both are lowered by Ibias .21 CML buffer with a cascode output stage. Furthermore. For the switching transistor.

the switch transistors for optimal performance. the current sources formed with Qpreb1 and Qpreb2 (Iprebias Ibias ) ensures that the cascode is always slightly on by bleeding a small bias current. Once the tradeoff is understood. CML/ECL HBT-based circuits have formed some of the faster circuits to date. This circuit does. introduce a common-mode offset in the output that may reduce the headroom in a two-level ECL gate that it must drive. This basic building block is employed in a variety of high-speed circuits.and falltimes. When properly designed. In this case. With these effects in mind. This design requires careful consideration to the design tradeoffs involving the ratio of Ibias/Iprebias as well as the potential size of the cascode transistor vs.22 CML buffer with a cascode output stage and bleed current to keep the cascode “on. however. and fan-out. allowable power dissipation. the bleed cascode can lead to signiﬁcant performance advantages. In general. demultiplexers. which include frequency synthesizers.22. high-speed HBT circuits require careful consideration and design of each high-speed node with respect to the required level of performance. device size. and ADCs. The basic static frequency divider consists of a master/slave ﬂip-ﬂop where the output data of the slave ﬂip-ﬂop is fed © 2003 by CRC Press LLC . as the transistor turns on. The performance and capability of HBT technology in circuit applications are summarized below.” effects where the actual node voltage depends on the previous bit patterns. The primary tools the designer has to work with are device bias. One way to remedy the off cascode issues is to use prebias circuits as shown in Fig.16-22 Analog Circuits and Devices FIGURE 16. the initial voltage may vary. Here. HBT Circuit Design Examples A traditional method to benchmark the high-speed capability of a technology is to determine the maximum switching rate of a static frequency divider. since the cascode does not completely turn off. Furthermore. which can result in increased jitter with digital data. ECL/CML gate topology. This results in improvements in the overall rise. 16. a series resistor can be introduced between the bleed point and the current source to decouple the current source capacitance into the high-speed node. and logic level to optimize the design. the cascoded CML design can be employed with performance advantages in carefully considered situations.

to date. reports the fastest results for any semiconductor technology. an advanced AlInAs/GaInAs HBT technology (ft of 164 GHz and fmax of 800 GHz) demonstrated a static frequency divider operating at 60 GHz. the high linearity characteristics of HBTs enable the design of wide dynamic range and high linearity sample-and-hold circuits.Logic Design Examples 16-23 back to the input data of the master ﬂip-ﬂop.23 2:1 Frequency divider based on two CML latches (master/slave ﬂip-ﬂop). As HBT started to achieve SSI capability in 1984. there are very few ICs having the performance margin over the SONET speciﬁcation for use in real systems. Due to the low transistor count and importance in many larger high-speed circuits. some of the ﬁrst OC-48 (2. there is signiﬁcantly less threshold variation when compared to FET-based technologies.23. with a spur-free dynamic range of about 48 dB. Today.5 Gb/s) and OC-192 (10 Gb/s) chip sets (e.5 GHz19c was demonstrated. there are many ICs that claim to be SONET-compliant at OC-48 (2.21 This HBT ECL-based design. in truth. The clock of the master and the clock of the slave ﬂip-ﬂop are connected together. Furthermore. preampliﬁers. In general. This enables the design of high-speed and accurate comparators. Since the SONET speciﬁcations apply on a system level. 16.. limiting ampliﬁers. a frequency divider with a toggle rate of 8.5 GHz. Due to the integration level. During the transition from research to pilot production in 1992. The essential circuit blocks (such as a 40-Gb/s 4:1 multiplexers23 and 26-GHz variable gain-limiting ampliﬁers24) have been demonstrated with HBTs in the research lab. thus.22 Another lucrative area for digital HBTs is in the area of high-speed circuits that are employed in ﬁberoptic based telecommunications systems. the frequency divider has emerged as the primary circuit used to demonstrate the high-speed potential of new technologies. a research-based AlInAs/GaInAs HBT (ft of 130 GHz and fmax of 90 GHz) was able to demonstrate a 39.5 Gb/s) and some at OC-192 (10 Gb/s) bit rates.5 GHz divide-by 4. which illustrates the potential of HBTs and ECL/CML circuit topology for high-speed circuits. The input bandwidth is from dc to 1. and reliability of HBTs. Besides high-speed operation. An 8-bit 2 gigasamples/s ADC has been fabricated with 2500 transistors. These paramount characteristics result in the dominance of GaAs HBTs in the super-high performance/high-speed ADCs.20 Recently. © 2003 by CRC Press LLC . For ADCs and DACs. the turn-on voltage of the transistor (Vbe) is determined by material constants. high-speed performance. the system-level speciﬁcations (SONET) for telecommunication systems are typically very stringent compared with data communication applications at the same bit rate.g. production GaAs HBTs have also achieved a high degree of integration for LSI circuits. The tighter speciﬁcations in telecom applications are due to the long-haul nature and the need to regenerate the data several times before the destination is reached. as shown in Fig. FIGURE 16.

clock and data recovery circuits. 164. In summary. R. presented at IEEE GaAs IC Symp. Solid-State Ciruits.. 1983. III-V HBT technology is a viable high-speed circuit technology with mature levels of integration and reliability for real-world applications. In the future. 2. 3. AZ. Lee. digital circuits. research labs have demonstrated the world’s fastest benchmark circuits with HBTs with ECL/CML-based circuit topology. J. 210. and laser/modulator drivers) deployed are based on GaAs HBTs.25 The LSI capability of HBT technology is showcased with this 9000 transistor switch on a 6730 ¥ 6130 µm2 chip. Gallium Arsenide Digital Integrated Circuit Design. the commercial success of HBTs can be exempliﬁed by that fact that HBT production lines ship several million HBT ICs every month and that several new HBT production lines are in the works. Subthreshold Design Considerations for Insulated Gate Field-Effect Transistors. New York. 1998. Repeatedly. R. © 2003 by CRC Press LLC . Ultra-low Power. With less than 3. With a throughput of 160. 4.26 and both were achieved with HBTs. S. et al. Today. 55. At this time. only two 16 ¥ 16 OC-192 switches have been demonstrated25. The production line has shown that current HBTs can achieve both the integration and performance level required for high-performance analog. 1990.000 Mb/s. 1974. IEEE J. S. High-Speed GaAs 256 bit Static RAM. it is also expected that III-V technology will move on to address ever higher speed and performance issues to satisfy our insatiable demand for bandwidth.24. References 1. and hybrid circuits that operate in the high gigahertz range.. 16. multiplexers. 1998 Product Selection Guide. and Butner..1 ps of RMS jitter (with four channels running). SC-9. 74. The high-speed performance is illustrated with a 10 Gb/s eye diagram shown in Fig.. McGraw-Hill. demultiplexers. these HBT parts have the largest amount of aggregate data running through it of any IC technology. Long.16-24 Analog Circuits and Devices FIGURE 16. Vitesse Semiconductor. A 16 ¥ 16 OC-192 crosspoint switch has been fabricated with a production 50 GHz ft and fmax process. this is the lowest jitter 10-Gb/s switch to date. it is expected that advances in Si based technology will start to compete in the markets currently held by III-V technology. however. S.24 Typical 10 Gbps eye diagram for OC-192 crosspoint switch. Phoenix. Troutman.

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