NEC – V850 Risc Microcontroller

CS433 Processor Presentation Series Prof. Luddy Harrison

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

1

Note on this presentation series
These slide presentations were prepared by students of CS433 at the University of Illinois at Urbana-Champaign All the drawings and figures in these slides were drawn by the students. Some drawings are based on figures in the manufacturer’s documentation for the processor, but none are electronic copies of such drawings You are free to use these slides provided that you leave the credits and copyright notices intact
CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 2

Table of Content
Product Overview Specifications Core Architecture Memory MAP Memory Organization Pipeline Register Set Instruction Set Applications Packaging PinOut Description Development Environment
CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 3

Product Overview Range of Performance
20-100 MHz and beyond 3-4 times the performance of the same frequency when compared to 16-bit Microprocessors Up to 168K high-speed instruction RAM, as well as 8 KB instruction cache memory and 8 KB of data cache memory. Built-in peripheral devices such as USB, Timer, Serial I/F, A/D Converter
CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 4
Competitors 32 bit microprocessors

Products

Data Processing V850E2
(under dev.)

compatible with popular machine class

>= 100MHZ

V850E1

50MHZ

compatible with high end machine class

V850

33MHZ

Competitors 16 bit microprocessors

V850ES V850

20MHZ

Applications
Range of Applications:
Digital consumer applications Inverters Industrial equipment Printers fax machines Etc…
More powerful, high performance memory interface V850E/xxx V850E1 Core V850ES/xxx V850ES Core V850 Core Specialized internal hardware V850/xxx ASSP Lineup Industry

V850E/Mxx High End Lineup

Car

QA

Communic ation

Lowe power, low noise internal memory extensions

V850ES/xxx V850/xxx Low end lineup

Informatio n application Quality of life

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

5

Product Overview
V850 Product Varieties
V850ES/FE2 V850ES/FF2 V850ES/FG2 V850ES/SG2 V850E/RS1 V850ES/FJ2 V850ES/SJ2 V850E/CA2 V850E/CG2

CAN

CAN & Motor Control Motor Control
V850ES/lk1 V850ES/IA3

V850ES/DG2

V850ES/DJ2 V850E/IA1

V850E/IA2 V850E/IA4

V850E/MA3

General Purpose

V850ES/KE1 V850ES/KE1+

V850ES/KF1 V850ES/KF1+

V850ES/KG1 V850ES/KG1+ V850E/MA2

V850ES/KJ1 V850ES/KJ1+ V850E/MA1 V850E/ME2 V850E2/ME3

Low Power
V850/SA1 V850ES/SA2

64

80

100

144

176 pins

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

6

Product Overview
Example: V850/ME2
High Speed Single Power Supply Memory interface Instruction RAM 128KB, Data RAM 16KB, Instruction Cache 8KB USB1.1
Operating Conditions
Voltage Dhrys tone Mips Max. clock (MHz) Min. Ins tr. Tim e (ns ) Sub. Clock Tm in[c] Tm ax[c] 3-3.6V 129 150 6.6 No -40 85

Peripherals
I/O Ports LCD FIP ADC DMA Channels CAN UART CSI I2C 77 No No 8X10bit 4 NO 2 2 No 6 No 2X16bit

Memory
ROM[KBytes ] Type RAM[KBytes ] EEPROM[Bytes ] Ins tr. Cache [KBytes ] Data Cache [KBytes ] No Rom les s 144 No 8 No

Tim er Watchdog PWM

Core
CPU Instructions Internal Bus [bits] External Bus [bits] V850E1 83 32 16-A ug

Package
Package Code Type Pins Pin Pitch[m m ] Size GM-UEU LQFP 176 0.5 24x24

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

7

Specifications
Performance & Features
Real-time performance of 130 MIPS Number of instructions: 83 Operation at over 150 MHz Minimum instruction execution time: 10 ns/7.5 ns/6.7 ns (at internal 100 MHz/133 MHz/150 MHz operation) General-purpose registers: 32 bits × 32 Instruction set: V850E1 CPU 128-bit instruction fetch bus Signed multiplication (16 bits × 16 bits → 32 bits or 32 bits × 32 bits →64 bits): 1 to 2 clocks 32-bit shift instructions: 1 clock Bit manipulation instructions Programmable wait function Interrupts/exceptions: External interrupts: 40 (including NMI) Eight levels of priorities can be set. Internal interrupts: 59 sources Exceptions: 2 sources Endian control function

Peripherals
Memory access controller DRAM controller (compatible with SDRAM) DMA controller: 4 channels I/O ports: 77 Real-time pulse unit: 16-bit timer/event counter: 6 channels (no capture operation for 2 channels) 16-bit timers: 6 16-bit capture/compare registers: 12 16-bit interval timer: 4 channels 16-bit up/down counter/timer for 2-phase encoder input: 2 channels 16-bit capture/compare registers: 4 16-bit compare registers: 4 Serial interfaces (SIO): Asynchronous serial interface B (UARTB) Clocked serial interface 3 (CSI3) CSI3/UARTB: 1 channel UARTB: 1 channel CSI3: 1 channel USB function controller (USBF): 1 channel A/D converter: 10-bit resolution A/D converter: 8 channels PWM (Pulse Width Modulation): 16-bit resolution PWM: 2 channels Clock generator: ×8 function using SSCG Power-save function: HALT/IDLE/software STOP mode

Memory
Memory space: 256 MB linear address space (common program/data use) External bus interface: 32-bit data bus (address/data separated) 32-/16-/8-bit bus sizing function Internal memory Instruction RAM: 128 KB Instruction cache 8 KB 2-way set associative Data RAM: 16 KB

Packaging
Package: 176-pin plastic LQFP (fine pitch) (24 × 24) 240-pin plastic FBGA (16 × 16) CMOS technology: All static circuit Operating voltage: IVDD = 1.4-1.65 V (core), EVDD = 3.0-3.6 V (I/O)

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

8

Core Architecture
Harvard Architecture
Two independent internal buses – for the simultaneous transfer of instructions and data
CPU R O M PC
32 bit Barrel Shifter System Registers Instruction Prefetch Queue (2 words) Multiplier 16X16 -> 32 32X32 -> 64 Bus control Unit ASTB OSTB R/W UBEN LBEN WAIT Add. Bus MUX ACK data bus HLDRQ HLDAK A LU

R A M

General Registers (32bitsx32)

Internal Peripheral Bus

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

9

Microprocessor Architecture
Block Diagram

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

10

On Chip Units
(1) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing.

(5) Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTPn) from on-chip peripheral I/O and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests.

(2) Bus control unit (BCU)
The BCU starts the required external bus cycle based on the physical address obtained by the CPU. The BCU controls a DRAM controller (DRAMC), page ROM controller (ROMC), and DMA controller (DMAC) and performs external memory access and DMA transfer. (a) SDRAM controller
The SDRAM controller generates the SDRAS, SDCAS, UUDQM, ULDQM, LUDQM, and LLDQM signals and performs access control for SDRAM.

(6) Clock generator (CG)
This clock generator supplies frequencies which are 8 times the input clock (FX) (using an on-chip PLL) as the internal system clock (fCLK).

(7) Real-time pulse unit (RPU)
This unit incorporates a 6-channel 16-bit timer/event counter, 4-channel 16-bit interval timer, and 2-channel 16-bit up/down counter/timer for 2-phase encoder input and can measure pulse widths or frequency and output a programmable pulse.

(b) Page ROM controller (ROMC)
This controller supports accessing ROM that includes the page access function.

(8) Serial interfaces (SIO)
The serial interfaces consist of 3 channels divided between an asynchronous serial interface B (UARTB) and clocked serial interface 3 (CSI3). Of these 3 channels, one is alternative with UARTB and CSI3, one is fixed to CSI3, and one is fixed to UARTB. In addition, a USB function controller (USBF) is also provided.

(c) DMA controller (DMAC)
This controller controls data transfer between memory and I/O instead of the CPU. There are three bus modes: single transfer, single step transfer, and block transfer.

(3) RAM
Instruction RAM (128 KB) and data RAM (16 KB) are provided. The instruction RAM can be accessed in one clock from the CPU when an instruction is fetched.

(9) A/D converter (ADC)
This high-speed, high-resolution 10-bit A/D converter includes 8 analog input pins. Conversion is performed using the successive approximation method.

(4) Cache
A 2-way set associative instruction cache (8 KB) is provided.

(10) PWM
Two channels for PWM signal output of 16-bit resolution have been provided.

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

11

Memory MAP
Linear address up to 4 GB total Up to 16MB for instructions

FFFFFFFFH Pheripheral I/O FFFFEFFFH Internal RAM

4 GB Linear Internal ROM/PROM/ Flash Memory

00000000H

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

12

Memory Organization
Internal Memory:
Instruction and Data RAM Instruction RAM (128 KB) and data RAM (16 KB) are provided. The instruction RAM can be accessed in one clock from the CPU when an instruction is fetched. Instruction Cache A 2-way set associative instruction cache (8 KB) is provided.

External Memory:
The BCU controls a DRAM controller (DRAMC), page ROM controller (ROMC), and DMA controller (DMAC) and performs external memory access and DMA transfer. SDRAM controller SRAM Controller Page ROM controller (ROMC) This controller supports accessing ROM that includes the page access function (i.e. Flash) DMA controller (DMAC) This controller controls data transfer between memory and I/O instead of the CPU. There are three bus modes: single transfer, single step transfer, and block transfer.

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

13

Pipeline
IF : Instruction fetch

5-stage pipeline Uses Forwarding

ID : Instruction decode EX : Instruction execution MEM: Memory Access WB : Writing execution result to register

Time Flow (State) System Clock
Instr. 1 Instr. 2 Instr. 3 Instr. 4 Instr. 5 Instr. 6 Instr. 7 Instr. 8 IF ID IF EX ID IF
MEM

WB
MEM

EX ID IF

WB
MEM

EX ID IF

WB
MEM

EX ID IF

WB
MEM

EX ID IF

WB
MEM

EX ID IF

WB
MEM

EX ID

WB
MEM

EX

WB

Executing instruction every 1 cycle

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

14

Data Types & Representation
Data Types:
Byte (8bit) Half-Word (16bit) Word (32 bit) Bit (1 bit)

Data Representation:
Integer Unsigned Integer Bit

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

15

Address Space
Up to 4-GB linear address space Memory and I/O are mapped to this address space The maximum address is 232-1 Byte ordering is little endian

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

16

Addressing Modes
Instruction address
Relative address (PC relative, i.e. Bcond) Register addressing (register indirect, i.e. JMP)

Operand address
Register addressing (Register is accessed as operand) Immediate addressing (Contained directly in instruction) Based addressing Bit addressing (accessing 1 bit directly)

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

17

Instruction Set
Mnemonic Function
Load/Store instructions SLD.B SLD.H SLD.W LD.B LD.H LD.W SST.B SST.H SST.W ST.B ST.H ST.W Load Byte Load Half-Word Load Word Load Byte Load Half-Word Load Word Store Byte Store Half-Word Store Word Store Byte Store Half-Word Store Word Saturate instructions SATADD SATSUB SATSUBI SATSUBR Saturated Add Saturated Subtract Saturated Subtract Immediate Saturated Subtract Reverse SET1 CLR1 NOT1 TST1 JMP JR JARL Bcond TST OR ORI AND ANDI XOR XORI NOT SHL SHR SAR

Mnemonic

Function
Logical operation instructions Test Or Or Immediate And And Immediate Exclusive-Or Exclusive-Or Immediate Not Shift Logical Left Shift Logical Right Shift Arithmetic Right Branch instructions Jump Jump Relative Jump and Register Link Branch on Condition Code Bit manipulation instructions Set Bit Clear Bit Not Bit Test Bit

Mnemonic

Function
Arithmetic instructions

MOV MOVHI MOVEA ADD ADDI SUB SUBR MULH MULHI DIVH CMP SETF

Move Move High Half-Word Move Effective Address Add Add Immediate Subtract Subtract Reverse Multiply Half-Word Multiply Half-Word Immediate Divide Half-Word Compare Set Flag Condition Special instructions

LDSR STSR TRAP RETI HALT DI EI NOP

Load System Register Store System Register Trap Return from Trap or Interrupt Halt Disable Interrupt Enable Interrupt No Operation

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

18

Applications
Range of Applications:
Digital consumer applications Inverters Industrial equipment Printers fax machines Etc…
More powerful, high performance memory interface V850E/xxx V850E1 Core V850ES/xxx V850ES Core V850 Core Specialized internal hardware V850/xxx ASSP Lineup Industry

V850E/Mxx High End Lineup

Car

QA

Communic ation

Lowe power, low noise internal memory extensions

V850ES/xxx V850/xxx Low end lineup

Informatio n application Quality of life

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

19

Role in Applications
Graphics Usage
High performance, Interface to SDRAM, DMA controller

DSP Usage
Barrel shifter, Multiplier Unit, 5 stage pipeline, DMA controller

Consumer Products Usage
High Performance, Huge memory, USB, PWM, ADC, SDRAM

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

20

V850 & IAR O.S.
FOR DSP and fast processing: The operating system uses the barrel shifter on the V850 as following:
On array access, the BREL_BASE symbol is used. C-Code: int main( void ) { int *p = array_1; int *q = array_2; *(p+10)= *(q +0) + *(q +1) + *(q +2) + *(q +3) + *(q +4) + *(q +5) + *(q+6) + *(q +7) + *(p +0) + *(p +1) + *(p +2) + *(p +3) + *(p +4) + *(p +5) + *(p+6) + *(p +7); return *(p+11); } ASM-Code: ------------------------MOVHI hi1(array_2+0-?BREL_BASE-0x8000),gp,r1 MOVEA lw1(array_2+0-?BREL_BASE-0x8000),r1,r1 MOVHI hi1(array_1+0-?BREL_BASE-0x8000),gp,r5 MOVEA lw1(array_1+0-?BREL_BASE-0x8000),r5,r5 LD.W (+0)[r1],r6 LD.W (+4)[r1],r7
CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 21

V850 & IAR O.S.
Size optimized FIR Filter
- Loops n times through the mac-code. - Designed for V850, - Strategy imposes an instruction time penalty of - One clock for the compare with n instruction and two (V850) clocks for the discarded pipeline when the branch is taken (n-1 times). - Implementing a pointer to the sample and another one to the coefficients .macro firsz filter,sample,size,scale -- size optimized version mov filter,r7 -- get address of FILTER struct mov size-1,r11 -- get filter order - 1 ld.w filter_coeff[r7],r8 -- get address of coefficients to r8 ld.w filter_data[r7],r7 -- get address of data to r7 addi 2*(size-2),r8,r8 -- we start from the end st.h sample,0[r7] -- store new sample addi 2*(size-2),r7,r7 -- we start from the end ld.h 2[r8],r10 -- coefficient ld.h 2[r7],r9 -- data ld.h 0[r7],r6 -- data mulh r9,r10 -- multiply .align 4 1: ld.h 0[r8],r9 -- coefficient st.h r6,2[r7] -- upshift mulh r6,r9 -- multiply add -2,r7 -- next data (go down) add -2,r8 -- next coefficient (go down) add r9,r10 -- accumulate result add -1,r11 -- loop counter ld.h 0[r7],r6 -- data bne 1b -- branch back while not finished satsubi -(1<<(scale-1)),r10,r10-- for proper rounding sar scale,r10 -- scale the result .endm

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

22

Packaging
176-Pin PlasticLQFP 0.5 mm pitch 24x24 mm 1.4 mm thick

240-Pin FBGA 0.8 mm pitch 16x16 mm 1.48 mm thick

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

23

Pin Descriptions
Pin Name P10 P11 P12 P13 P20 P21 P22 P23 P24 P25 P50 P51 P52 P53 P54 P55 P65 P66 P67 P72 P73 P74 P75 P76 P77 PAH0 to PAH9 I/O Function Port 1 4-bit I/O port Input/output can be specified in 1-bit units. I/O Input Port 2 P20 is an input port dedicated to checking the NMI input status. If a valid edge is input, it operates as an NMI input. P21 to P25 are a 5-bit I/O port. Input/output can be specified in 1-bit units. Port 5 6-bit I/O port Input/output can be specified in 1-bit units. I/O Port 6 3-bit I/O port Input/output can be specified in 1-bit units. Port 7 6-bit I/O port Input/output can be specified in 1-bit units. I/O I/O Port AH 8-/10-bit I/O port Input/output can be specified in 1-bit units. Copyright 2005 University of Illinois A16 to A25 Alternate Function INTP10/UCLK INTP11/SCK0 SI0/RXD0 – Serial I/O SO0/TXD0 – serial I/O NMI -- Interrupts INTP21/RXD1 INTP22/TXD1 INTP23/SCK1 INTP24/SI1 INTP25/SO1 INTP50/DMARQ0 INTP51/DMAAK0 INTP52/TC0 INTPC00/TIC0/DMARQ1 INTPC01/DMAAK1 TOC0/TC1 INTPC20/TIC2/DMARQ2 INTPC21/DMAAK2 TOC2/TC2 -- timers INTPC31/DMAAK3 TOC3/TC3 -- timers

I/O

I/O

CS433 Prof. Luddy Harrison

24

Pin Descriptions
Pin Name I/O Function Alternate Function

PAL0 PAL1

I/O

Port AL 2-bit I/O port Input/output can be specified in 1-bit units.

INTPL0/A0 INTPL1/A1

PDH0 PDH1 PDH2 PDH3 PDH4 PDH5 PDH6 PDH7 PDH8 PDH9 PDH10 PDH11 PDH12 PDH13 PDH14 PDH15

I/O

Port DH 8-/16-bit I/O port Input/output can be specified in 1-bit units.

D16/INTPD0 D17/INTPD1 D18/INTPD2/TOC4 D19/INTPD3 D20/INTPD4 D21/INTPD5/TOC5 D22/INTPD6/INTP100/TCUD10 D23/INTPD7/INTP101/TCLR10 D24/INTPD8/TO10 D25/INTPD9/TIUD10 D26/INTPD10/INTP110/TCUD11 D27/INTPD11/INTP111/TCLR11 D28/INTPD12/TO11 D29/INTPD13/TIUD11 D30/INTPD14/PWM0 D31/INTPD15/PWM1

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

25

Pin Descriptions
Pin Name PCD0 PCD1 PCD2 PCD3 PCM0 PCM1 PCM2 PCM3 PCM4 PCM5 I/O Port CM 6-bit I/O port Input/output can be specified in 1-bit units. I/O I/O Function Port CD 4-bit I/O port Input/output can be specified in 1-bit units. Alternate Function SDCKE BUSCLK SDCAS SDRAS WAIT HLDAK HLDRQ REFRQ ADTRG/SELFREF CS0

PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 PCS6 PCS7 I/O

Port CS 8-bit I/O port Input/output can be specified in 1-bit units.

CS1 CS2/IOWR CS3 CS4 CS5/IORD CS6 CS7

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

26

Pin Descriptions

Pin Name PCT0 PCT1 PCT2 PCT3 PCT4 PCT5 PCT7

I/O

Function Port CT 7-bit I/O port Input/output can be specified in 1-bit units.

Alternate Function LLWR/LLBE/LLDQM LUWR/LUBE/LUDQM ULWR/ULBE/ULDQM UUWR/UUBE/UUDQM RD WE/WR BCYST

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

27

Pins By Function
Pin Name A0 A1 A2 to A9 A10 to A15 A16 to A25 ADTRG ANI0 to ANI7 AVDD AVREFM AVREFP AVSS BCYST BUSCLK CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 D0 to D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 I/O Output Function 26-bit address bus for external memory Alternate Function PAL0/INTPL0 PAL1/INTPL1 input input input Output Output Output A/D converter external trigger input Analog inputs to A/D converter 3.3 V positive power supply for A/D converter Reference voltage applied to A/D converter Ground potential for A/D converter Strobe signal output that shows the start of the bus cycle Clock output for SDRAM Chip select signal output PAH0 to PAH9 PCM5/SELFREF

PCT7 PCD1 PCS0 PCS1 PCS2/IOWR PCS3 PCS4 PCS5/IORD PCS6 PCS7 PDH0/INTPD0 PDH1/INTPD1 PDH2/INTPD2/TOC4 PDH3/INTPD3 PDH4/INTPD4 PDH5/INTPD5/TOC5 PDH6/INTPD6/INTP100/TCUD10 PDH7/INTPD7/INTP101/TCLR10 PDH8/INTPD8/TO10 PDH9/INTPD9/TIUD10 PDH10/INTPD10/INTP110/TCUD11 PDH11/INTPD11/INTP111/TCLR11 PDH12/INTPD12/TO11 PDH13/INTPD13/TIUD11 PDH14/INTPD14/PWM0 PDH15/INTPD15/PWM1

I/O

32-bit data bus for external memory

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

28

Pins by Function
Pin Name DCK DDI DDO DMAAK0 DMAAK1 DMAAK2 DMAAK3 DMARQ0 DMARQ1 DMARQ2 DMARQ3 DMS DRST EVDD EVSS HLDAK HLDRQ INTP10 INTP11 INTP21 INTP22 INTP23 INTP24 INTP25 INTP50 INTP51 INTP52 INTP65 INTP66 INTP67 INTPD0 INTPD1 INTPD2 INTPD3 INTPD4 INTPD5 INTPD6 INTPD7 INTPD8 INTPD9 INTPD10 Output P76/INTPC31 I/O I/O Input Input Output Function Debug clock input Debug data input Debug data output Alternate Function − − − P51/INTP51 P54/INTPC01 P73/INTPC21 P76/INTPC31 P50/INTP50 P53/INTPC00/TIC0 P72/INTPC20/TIC2 P75/INTPC30/TIC3 − − − − PCM2 PCM3 P10/UCLK P11/SCK0 P21/RXD1 P22/TXD1 P23/SCK1 P24/SI1 P25/SO1 P50/DMARQ0 P51/DMAAK0 P52/TC0 P65/TIC1/INTPC10 P66/INTPC11 P67/TOC1 PDH0/D16 PDH1/D17 PDH2/TOC4/D18 PDH3/D19 PDH4/D20 PDH5/TOC5/D21 PDH6/INTP100/TCUD10/D22 PDH7/INTP101/TCLR10/D23 PDH8/TO10/D24 PDH9/TIUD10/D25 PDH10/INTP110/TCUD11/D26

Input Input Input

Output Input

DMA request signal input Debug mode select Reset input for debug 3.3 V positive power supply for external pin Ground potential for external pin Bus hold acknowledge output Bus hold request input

Input

External maskable interrupt request input

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

29

Pins by Function
Pin Name INTPD11 INTPD12 INTPD13 INTPD14 INTPD15 INTPL0 INTPL1 INTP100 INTP101 INTP110 INTP111 INTPC00 INTPC01 INTPC10 INTPC11 INTPC20 INTPC21 INTPC30 INTPC31 IORD IOWR IVDD IVSS JIT0 JIT1 LLBE LLDQM LLWR LUBE LUDQM LUWR MODE0 MODE1 NMI OSCVDD OSCVSS PLLSEL I/O Input Function External maskable interrupt request input

Input Input Input

Timer ENC10 external capture trigger input Timer ENC11 external capture trigger input External maskable interrupt request input/timer C0 external capture trigger input External maskable interrupt request input/timer C1 external capture trigger input External maskable interrupt request input/timer C2 external capture trigger input External maskable interrupt request input/timer C3 external capture trigger input DMA read strobe signal output DMA write strobe signal output 1.5 V positive power supply for internal unit Ground potential for internal unit Specifying SSCG operating mode External data bus byte enable signal output (lowest byte((D0 to D7)) Output disable/write mask signal output for SDRAM (lowest byte (D0 to D7)) External data bus write strobe signal output (lowest byte(D0 to D7)) External data bus byte enable signal output (third byte (D8to D15)) Output disable/write mask signal output for SDRAM (thirdbyte (D8 to D15)) External data bus write strobe signal output (third byte (D8to D15)) Specifying V850E/ME2 operating mode Non-maskable interrupt request signal input 3.3 V positive power supply for oscillator Ground potential for oscillator Input specifying PLL operating mode

Output Output Input Output Output Output Output Output Output Input Input Input

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

30

Pins By Function
Pin Name PLLVDD PLLVSS PWM0 PWM1 RD REFRQ RESET RXD0 RXD1 SCK0 SCK1 SDCAS SDCKE SDRAS SELFREF SI0 SI1 SO0 SO1 SSEL0 SSEL1 TC0 TC1 TC2 TC3 TCLR10 TCLR11 TCUD10 TCUD11 TIC0 TIC1 TIC2 TIC3 TIUD10 TIUD11 TO10 TO11 I/O Output Output Output Input Input I/O Output Output Output Input Input Output Input Output Function 1.5 V positive power supply for PLL synthesizer Ground potential for PLL synthesizer PWM pulse signal output External data bus read strobe signal output Refresh request signal output for SDRAM System reset input UARTB0 and UARTB1 serial receive data input CSI30 and CSI31 serial clock I/O (3-wire) Column address strobe signal output for SDRAM SDRAM clock enable signal output Row address strobe signal output for SDRAM Self-refresh request input for SDRAM CSI30 and CSI31 serial receive data input (3-wire) CSI30 and CSI31 serial transmit data output (3-wire) Specifying the clock generator’s operating mode DMA transfer end (terminal count) signal output

Input Input Input

Clear signal input to timer ENC10 and ENC11 Count operation switching signal input to timer ENC10 and ENC11 External count clock input of timer C0 to C3

Input Output

External count clock input to timer ENC10 and ENC11 Pulse signal output of timer ENC10 and ENC11

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

31

Pins By Function
Pin TOC0 TOC1 TOC2 TOC3 TOC4 TOC5 TRCCLK TRCDATA0 TRCDATA1 TRCDATA2 TRCDATA3 TRCEND TXD0 TXD1 UCLK UDM UDP ULBE ULDQM ULWR UUBE UUDQM UUWR UVDD WAIT WE WR X1 X2 I/O Output Function Pulse signal output of timer C0 to C5

Output Output

Trace clock output Trace data output (D0 to D3)

Output Output Input I/O I/O Output Output Output Output Output Output Input Output Output Input

Trace end status output UARTB0 and UARTB1 serial transmit data output USB clock signal input USB data I/O (−) USB data I/O (+) External data bus byte enable signal output (second byte (D16 to D23)) Output disable/write mask signal output for SDRAM(second byte (D16 to D23)) External data bus write strobe signal output (second byte(D16 to D23)) External data bus byte enable signal output (highest byte(D24 to D31)) Output disable/write mask signal output for SDRAM(highest byte (D24 to D31)) External data bus write strobe signal output (highest byte(D24 to D31)) 3.3 V positive power supply for USB Control signal input that inserts a wait in the bus cycle Write enable signal output for SDRAM Write strobe signal output for SDRAM Connects the crystal resonator for system clock oscillation.

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

32

Development Environment
Evaluation Board (starter kit)
Enables RISC chip performance sampling with only a serial connection to a PC Low-cost GUN Compiler exeCC assessment-version package featuring assessment board and PARTNER monitor-debugger Includes connector for writing to CPU's internal flash memory

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

33

Development Environment
In-circuit emulator IE-V850E1-CD-NW
Compact PC card-type emulator Supports flash programmer functions

IE-V850ESK1-ET, IECUBE series
Integrate emulation board into emulator body USB I/F for PC (Hi-Speed USB I/F, USB1.1) Real-time RAM monitor, time measurement function, USB_IF

CS433 Prof. Luddy Harrison

Copyright 2005 University of Illinois

34

References
NEC User Manuals
User’s Manual V850 FAMILY 32-bit Single-Chip Microcontroller Architecture Document No. U10243EJ7V0UM00 (7th edition), Date Published March 2001 J CP(K) V850 Series Development Environment. Document No. U15763EJ3V0PF00_E2, Date Feb. 2004 V850E/ME2 User’s Manual 32-Bit Single-Chip Microcontroller , Hardware µPD703111A Document No. U16031EJ3V0UD00 (3rd edition), Date Published June 2004 N CP(K) Application Notes Digital Signal Processing with V850 and V850E Devices Document No. U17285EE1V0AN00 Date Published August 2004, NEC Corporation 2004, Printed in Germany

http://www.necel.com/micro/english/v850/product/cpucore.html
CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 35