com
D R(n) L P(n)
Bridge
rectifier 
diode V DC R sn C sn Vsn
+ Np N S(n)
+
CO(n) CP(n) VO(n)
CDC 
Dsn
FPS D R1 L P1
Drain 1
N S1
CO1 CP1 V O1
AC line GND 2
FB Vcc
4 3 Da
Ra
Rd Rbias
H11A817A
CB H11A817A
Ca Na R1
RF CF
KA431
R2
1. Introduction and output filter, selecting the components and closing the
feedback loop. The design procedure described herein is
Figure 1 shows the schematic of the basic offline flyback general enough to be applied to various applications. The
converter using FPS, which also serves as the reference design procedure presented in this paper is also imple
circuit for the design process described in this paper. mented in a software design tool (FPS design assistant) to
Because the MOSFET and PWM controller together with enable the engineer finish their SMPS design in a short time.
various additional circuits are integrated into a single In the appendix, a stepbystep design example using the
package, the design of SMPS is much easier than the discrete software tool is provided. An experimental flyback converter
MOSFET and PWM controller solution. This paper provides from the design example has been built and tested to show
a stepbystep design procedure for a FPS based offline the validity of the design procedure.
flyback converter, which includes designing the transformer
Rev. 1.2.0
©2003 Fairchild Semiconductor Corporation
AN4137 APPLICATION NOTE
2. Stepbystep Design Procedure In this section, a design procedure is presented using the
schematic of figure 1 as a reference. In general, most FPS
devices have the same pin configuration from pin 1 to pin 4,
as shown in figure 1. Figure 2 illustrates the design flow
1. Determine the system specifications chart. The detailed design procedures are as follows:
(Vlinemin, Vlinemax, fL, Po, Eff)
N
(2) STEP2 : Determine DC link capacitor (CDC) and the
Y DC link voltage range.
Is it possible to change the core ?
It is typical to select the DC link capacitor as 23uF per watt
of input power for universal input range (85265Vrms) and
N 1uF per watt of input power for European input range (195V
265Vrms). With the DC link capacitor chosen, the minimum
link voltage is obtained as
9. Choose the proper rectifier diode for each
output
min min 2 P in ⋅ ( 1 – D ch )
V DC = 2 ⋅ ( V line ) –  (3)
C DC ⋅ f L
10. Determine the output capacitor
MOSFET
Drain Rectifier 0V
Current Diode
Current Figure 5. The output voltage reflected to the primary
When the MOSFET in the FPS is turned off, the input volt
age (VDC) together with the output voltage reflected to the
primary (VRO) are imposed on the MOSFET as shown in fig
D ure 5. After determining Dmax, VRO and the maximum nomi
nal MOSFET voltage (Vdsnom) are obtained as
As input voltage increases or
load current decreases
D max min
V RO =  ⋅ V DC (5)
MOSFET Rectifier 1 – D max
Drain Diode nom max
Current Current V ds = V DC + VRO (6)
P in
where I EDC = 
 (10)
min
V DC ⋅ D max (6) STEP6 : Determine the proper core and the minimum
primary turns.
min
V D
and ∆ I = 
DC max
(11) Actually, the initial selection of the core is bound to be crude
Lm fs
since there are too many variables. One way to select the
where Pin, VDCmin and Lm are specified in equations (1), (3), proper core is to refer to the manufacture's core selection
and (7) respectively, Dmax is specified in step3 and fs is the guide. If there is no proper reference, use the table 1 as a
FPS switching frequency. starting point. The core recommended in table 1 is typical for
the universal input range, 67kHz switching frequency and
The flyback converter designed for CCM at the minimum single output application. When the input voltage range is
input voltage and full load condition may enter into DCM as 195265 Vac or the switching frequency is higher than
the input voltage increases. The maximum input voltage 67kHz, a smaller core can be used. For an application with
guaranteeing CCM in the full load condition is obtained as multiple outputs, usually a larger core should be used than
recommended in the table.
With the chosen core, the minimum number of turns for the
transformer primary side to avoid the core saturation is given Output EI core EE core EPC core EER core
by Power
min L m Iover 6 010W EI12.5 EE8 EPC10
NP =  × 10 (turns) (13) EI16 EE10 EPC13
B sat A e
EI19 EE13 EPC17
where Lm is specified in equation (7), Iover is the FPS pulse EE16
bypulse current limit level, Ae is the crosssectional area of 1020W EI22 EE19 EPC19
the core as shown in figure 7 and Bsat is the saturation flux 2030W EE22 EPC25 EER25.5
density in tesla. Figure 8 shows the typical characteristics of EI25
ferrite core from TDK (PC40). Since the saturation flux den 3050W EI28 EE25 EPC30 EER28
sity (Bsat) decreases as the temperature goes high, the high EI30
temperature characteristics should be considered. 5070W EI35 EE30 EER28L
If there is no reference data, use Bsat =0.3~0.35 T. Since the
70100W EI40 EE35 EER35
MOSFET drain current exceeds Idspeak and reaches Iover in a
transition or fault condition, Iover is used in equation (13) 100150W EI50 EE40 EER40
instead of Idspeak to prevent core saturation during transition. EER42
150200W EI60 EE50 EER49
EE60
Aw
(7) STEP7 : Determine the number of turns for each
output
Figure 9 shows the simplified diagram of the transformer.
First, determine the turns ratio (n) between the primary side
and the feedback controlled secondary side as a reference.
NP V R0
Ae n = 
Ns1
= 
V o1 + V F1
 (14)
where Np and Ns1 are the number of turns for primary side
Figure 7. Window Area and Cross Sectional Area and reference output, respectively, Vo1 is the output voltage
and VF1 is the diode (DR1) forward voltage drop of the refer
ence output.
M agnetization Curves (typical)
M aterial :PC40
Then, determine the proper integer for Ns1 so that the result
ing Np is larger than Npmin obtained from equation (13).
25 ℃
500
60 ℃ The number of turns for the other output (nth output) is
determined as
100 ℃
400 Vo (n ) + VF ( n)
120 ℃ N s ( n ) =  ⋅ Ns1 ( turns ) ( 15 )
V o1 + V F1
Flux density B (mT)
300
The number of turns for Vcc winding is determined as
200
V cc * + V Fa
 ⋅ N s1
N a =  ( turns ) ( 16 )
V o1 + VF1
100
where Vcc* is the nominal value of the supply voltage of the
0 FPS device, and VFa is the forward voltage drop of Da as
0 800 1600 defined in figure 9. Since Vcc increases as the output load
M agnetic field H (A/m )
increases, it is proper to set Vcc* as Vcc start voltage (refer to
Figure 8. Typical BH characteristics of ferrite core the data sheet) to avoid the over voltage protection condition
(TDK/PC40)
during normal operation.
V RO ⋅ K L ( n )
rms
rms rms 1 – D max IF > 1.5 ⋅ I D ( n ) (23)
I sec ( n ) = I ds  ⋅  ( 18 )
D max ( Vo (n ) + VF ( n) )
where VRRM is the maximum reverse voltage and IF is the
rms average forward current of the diode.
where VRO and Ids are specified in equations (5) and (9),
Vo(n) is the output voltage of the nth output, VF(n) is the
A quick selection guide for Fairchild Semiconductor rectifier
diode (DR(n)) forward voltage drop, Dmax is specified in step
diodes is given in table 2. In this table trr is the maximum
3 and KL(n) is the load occupying factor for nth output
reverse recovery time.
defined in equation (2).
The current density is typically 5A/mm2 when the wire is
long (>1m). When the wire is short with a small number of
turns, a current density of 610 A/mm2 is also acceptable.
Avoid using wire with a diameter larger than 1 mm to avoid
Products VRRM IF trr Package The ripple current of the nth output capacitor (Co(n)) is
obtained as
SB330 30 V 3A  TO210AD
SB530 30 V 5A  TO210AD
rms rms 2 2
MBR1035 35 V 10 A  TO220AC I cap ( n ) = ( ID ( n ) ) – Io ( n) (24)
MBR1635 35 V 16 A  TO220AC where Io(n) is the load current of the nth output and ID(n)rms
SB340 40 V 3A  TO210AD is specified in equation (21). The ripple current should be
SB540 40 V 5A  TO210AD smaller than the ripple current specification of the capacitor.
The voltage ripple on the nth output is given by
SB350 50 V 3A  TO210AD
SB550 50 V 5A  TO210AD peak
I
o ( n ) max D I V R K
RO C ( n ) L ( n )
SB360 60 V 3A  TO210AD ∆ V o ( n ) =  ds
 + 
 (25)
C o ( n ) fs ( V o ( n ) + VF ( n ) )
SB560 60 V 5A  TO210AD
MBR1060 60 V 10 A  TO220AC
where Co(n) is the capacitance, Rc(n) is the effective series
MBR1660 60 V 16 A  TO220AC
resistance (ESR) of the nth output capacitor, KL(n), VRO and
Ultra Fast Recovery diode Idspeak are specified in equations (2), (5) and (8) respectively,
Products VRRM IF trr Package Dmax is specified in step3, Io(n) and Vo(n) are the load current
EGP10B 100 V 1A 50 ns DO41 and output voltage of the nth output, respectively and VF(n)
is the diode (DR(n)) forward voltage.
UF4002 100 V 1A 50 ns DO41
EGP20B 100 V 2A 50 ns DO15 Sometimes it is impossible to meet the ripple specification
with a single output capacitor due to the high ESR of the
EGP30B 100 V 3A 50 ns DO210AD
electrolytic capacitor. Then, additional LC filter stages (post
FES16BT 100 V 16 A 35 ns TO220AC filter) can be used. When using the post filters, be careful not
EGP10C 150 V 1A 50 ns DO41 to place the corner frequency too low. Too low a corner fre
EGP20C 150 V 2A 50 ns DO15 quency may make the system unstable or limit the control
bandwidth. It is typical to set the corner frequency of the
EGP30C 150 V 3A 50 ns DO210AD
post filter at around 1/10~1/5 of the switching frequency.
FES16CT 150 V 16 A 35 ns TO220AC
EGP10D 200 V 1A 50 ns DO41
UF4003 200 V 1A 50 ns DO41 (11) STEP11 : Design the RCD snubber.
EGP20D 200 V 2A 50 ns DO15 When the power MOSFET is turned off, there is a high volt
EGP30D 200 V 3A 50 ns DO210AD age spike on the drain due to the transformer leakage induc
FES16DT 200 V 16 A 35 ns TO220AC
tance. This excessive voltage on the MOSFET may lead to
an avalanche breakdown and eventually failure of FPS.
EGP10F 300 V 1A 50 ns DO41 Therefore, it is necessary to use an additional network to
EGP20F 300 V 2A 50 ns DO15 clamp the voltage.
EGP30F 300 V 3A 50 ns DO210AD The RCD snubber circuit and MOSFET drain voltage wave
EGP10G 400 V 1A 50 ns DO41 form are shown in figure 10 and 11, respectively. The RCD
UF4004 400 V 1A 50 ns DO41 snubber network absorbs the current in the leakage induc
EGP20G 400 V 2A 50 ns DO15
tance by turning on the snubber diode (Dsn) once the MOS
FET drain voltage exceeds the voltage of node X as depicted
EGP30G 400 V 3A 50 ns DO210AD in figure 10. In the analysis of snubber network, it is
UF4005 600 V 1A 75 ns DO41 assumed that the snubber capacitor is large enough that its
EGP10J 600 V 1A 50 ns DO41 voltage does not change significantly during one switching
EGP20J 600 V 2A 50 ns DO15
cycle.
EGP30J 600 V 3A 50 ns DO210AD The first step in designing the snubber circuit is to determine
UF4006 800 V 1A 75 ns TO41
the snubber capacitor voltage at the minimum input voltage
and full load condition (Vsn). Once Vsn is determined, the
UF4007 1000 V 1A 75 ns TO41 power dissipated in the snubber network at the minimum
Table 2. Fairchild Diode quick selection table input voltage and full load condition is obtained as
 
V sn1 VDC Rsn
∆ V sn = 
 (27) Csn Vsn
Np
C sn R sn f s + + VRO
X
where fs is the FPS switching frequency. In general, 5~10%
CDC  VX
ripple is reasonable. +
Dsn
The snubber capacitor voltage (Vsn) of equation (26) is for
the minimum input voltage and full load condition. When the FPS
Llk
converter is designed to operate in CCM, the peak drain cur Drain +
rent together with the snubber capacitor voltage decrease as
the input voltage increases. The snubber capacitor voltage Vds
under maximum input voltage and full load condition is GND
obtained as 
2 2
V RO + ( VRO ) + 2R sn L lk fs ( I ds2 )
V sn2 = 
 (28)
2
Figure 10. Circuit diagram of the snubber network
where fs is the FPS switching frequency, Llk is the primary
side leakage inductance, VRO is the reflected output voltage,
Rsn is the snubber resistor and Ids2 is the peak drain current at
the maximum input voltage and full load condition. When
the converter operates in CCM at the maximum input voltage
and full load condition (refer to equation (12)), the Ids2 of Voltage Margin > 10% of BVdss
equation (28) is obtained as
P in ⋅ V DC + V RO
max
V DC
max
⋅ VRO BVdss
I ds2 =  +  (29) Effect of stray inductance (510V)
V
DC
max
⋅ VRO 2L m f s ⋅ V DCmax + V RO
Vsn2
When the converter operates in DCM at the maximum input VRO
voltage and full load condition (refer to equation (12)), the
Ids2 of equation (28) is obtained as
2 ⋅ P in
I ds2 =  (30) VDC max
fs ⋅ Lm
where Pin, VDCmax, VRO and Lm are specified in equations
0V
(1), (4), (5) and (7), respectively, and fs is the FPS switching
frequency.
Figure 11. MOSFET drain voltage and snubber capacitor
voltage
2
(12) STEP12 : Design the feed back loop. 1 RL ( 1 – D ) (1 + D)
w z =  , w rz = 
 and w p = 
Since most FPS devices employ current mode control as R c1 C o1 DL m ( N s1 ⁄ N p )
2 R L C o1
shown in figure 12, the feedback loop can be simply imple
mented with a onepole and onezero compensation circuit. where Lm is specified in equation (7), D is the duty cycle of
In the feedback circuit analysis, it is assumed that the current the FPS, Co1 is the reference output capacitor and RC1 is the
transfer ratio (CTR) of the opto coupler is 100%. ESR of Co1.
The current control factor of FPS, K is defined as When the converter has more than one output, the low fre
quency controltooutput transfer function is proportional to
I pk Iover the parallel combination of all load resistance, adjusted by
K = 
 =  (32)
V FB VFBsat the square of the turns ratio. Therefore, the effective load
resistance is used in equation (33) instead of the actual load
where Ipk is the peak drain current and VFB is the feedback
resistance of Vo1.
voltage, respectively for a given operating condition, Iover is
the current limit of the FPS and VFBsat is the feedback satura Notice that there is a right half plane (RHP) zero (wrz) in the
tion voltage, which is typically 2.5V. controltooutput transfer function of equation (33). Because
the RHP zero reduces the phase by 90 degrees, the crossover
In order to express the small signal AC transfer functions, frequency should be placed below the RHP zero.
the small signal variations of feedback voltage (vFB) and
controlled output voltage (vo1) are introduced as vˆFB and vˆo1. Figure 13 shows the variation of a CCM flyback converter
controltooutput transfer function for different input volt
ages. This figure shows the system poles and zeros together
with the DC gain change for different input voltages. The
FPS vo1' vo1
gain is highest at the high input voltage condition and the
vFB RD RHP zero is lowest at the low input voltage condition.
ibias
Figure 14 shows the variation of a CCM flyback converter
iD Rbias controltooutput transfer function for different loads. This
RB CB figure shows that the low frequency gain does not change for
1:1
R1 different loads and the RHP zero is lowest at the full load
CF RF
condition.
KA431
For DCM operation, the controltooutput transfer function
of the flyback converter using current mode control is given
R2
by
v̂ o1 Vo1 ( 1 + s ⁄ w z )
Ipk  =  ⋅ 
G vc =  (34)
v̂ FB VFB ( 1 + s ⁄ w p )
1
MOSFET where wz =  , w p = 2 ⁄ R L C o1
current R c1 C o1
Figure 12. Control Block Diagram
Vo1 is the reference output voltage, VFB is the feedback volt
age for a given condition, RL is the effective total resistance
For CCM operation, the controltooutput transfer function of the controlled output, Co1 is the controlled output capaci
of the flyback converter using current mode control is given tance and Rc1 is the ESR of Co1.
by
Figure 15 shows the variation of the controltooutput trans
v̂ o1 fer function of a flyback converter in DCM for different
G vc = 

v̂ FB loads. Contrary to the flyback converter in CCM, there is no
K ⋅ R L V DC ( N p ⁄ N s1 ) ( 1 + s ⁄ w z ) ( 1 – s ⁄ w rz ) RHP zero and the DC gain does not change as the input volt
=  ⋅  ( 33 ) age varies. As can be seen, the overall gain except for the DC
2V RO + v DC 1 + s ⁄ wp
gain is highest at the full load condition.
where VDC is the DC input voltage, RL is the effective total The feedback compensation network transfer function of fig
load resistance of the controlled output, defined as Vo12/Po, ure 12 is obtained as
Np and Ns1 are specified in step7, VRO is specified in equa
tion (5), Vo1 is the reference output voltage, Po is specified in
step1 and K is specified in equation (32). The pole and zeros
of equation (33) are defined as
When the input voltage and the load current vary over a wide
range, it is not easy to determine the worst case for the feed
v FBˆ w i 1 + s ⁄ w zc back loop design. The gain together with zeros and poles
 =   ⋅ 
 (35)
v o1ˆ s 1 + 1 ⁄ w pc vary according to the operating condition. Moreover, even
though the converter is designed to operate in CCM or at the
RB 1 1
where w i = 
 , w zc =  , w pc =  boundary of DCM and CCM in the minimum input voltage
R1 RD CF ( R F + R 1 )C F RB CB
and full load condition, the converter enters into DCM
changing the system transfer functions as the load current
and RB is the internal feedback bias resistor of FPS, which is decreases and/or input voltage increases.
typically 2.8kΩ and R1, RD, RF, CF and CB are shown in fig One simple and practical way to this problem is designing
ure 12. the feedback loop for low input voltage and full load condi
tion with enough phase and gain margin. When the converter
operates in CCM, the RHP zero is lowest in low input volt
40 dB age and full load condition. The gain increases only about
fp 6dB as the operating condition is changed from the lowest
20 dB
input voltage to the highest input voltage condition under
universal input condition. When the operating mode changes
fp from CCM to DCM, the RHP zero disappears making the
High input voltage
0 dB
system stable. Therefore, by designing the feedback loop
fz
Low input voltage with more than 45 degrees phase margin in low input voltage
20 dB
frz
and full load condition, the stability over all the operating
fz frz ranges can be guaranteed.
40 dB
The procedure to design the feedback loop is as follows
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
Figure 13. CCM flyback converter controlto output trans (a) Determine the crossover frequency (fc). For CCM mode
fer function variation for different input voltages flyback, set fc below 1/3 of right half plane (RHP) zero to
minimize the effect of the RHP zero. For DCM mode fc can
be placed at a higher frequency, since there is no RHP zero.
40 dB
fp Light load (b) When an additional LC filter is employed, the crossover
frequency should be placed below 1/3 of the corner fre
20 dB quency of the LC filter, since it introduces a 180 degrees
fp phase drop. Never place the crossover frequency beyond the
0 dB corner frequency of the LC filter. If the crossover frequency
Heavy load is too close to the corner frequency, the controller should be
20 dB
designed to have a phase margin greater than 90 degrees
when ignoring the effect of the post filter.
fz frz f rz
40 dB (c) Determine the DC gain of the compensator (wi/wzc) to
cancel the controltooutput gain at fc.
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
Figure 14. CCM flyback converter controlto output trans (d) Place a compensator zero (fzc) around fc/3.
fer function variation for different loads (e) Place a compensator pole (fpc) above 3fc.
40 dB
Loop gain T
40 dB
fp
20 dB fp
20 dB fzc
Heavy load
Compensator
0 dB fp fpc
0 dB
fc
20 dB fz Control to output
Light load
frz
20 dB
fz
40 dB
fz
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz 40 dB
Figure 15. DCM flyback converter controlto output trans 1Hz 10Hz 100Hz 1kHz 10kHz 100kHz
fer function variation for different loads
Figure 16. Compensator design
ing the startup. While, too large a capacitor may increase the
When determining the feedback circuit component, there are startup time.
some restrictions as follows. (b) Vcc resistor (Ra) : The typical value for Ra is 520Ω. In
the case of multiple outputs flyback converter, the voltage of
(a) The voltage divider network of R1 and R2 should be
the lightly loaded output such as Vcc varies as the load cur
designed to provide 2.5V to the reference pin of the KA431.
rents of other outputs change due to the imperfect coupling
The relationship between R1 and R2 is given as
of the transformer. Ra reduces the sensitivity of Vcc to other
outputs and improves the regulations of Vcc.
2.5 ⋅ R 1
R 2 = 
 (36)
Vo1 – 2.5
V o1 – V OP – 2.5
 > I FB (38)
RD
V OP

 > 1mA (39)
R bias
where Vo1 is the reference output voltage, VOP is optodiode
forward voltage drop, which is typically 1V and IFB is the
feedback current of FPS, which is typically 1mA. For exam
ple, Rbias< 1kΩ and RD < 1.5kΩ for Vo1=5V.
Miscellaneous
(a) Vcc capacitor (Ca) : The typical value for Ca is 1050uF,
which is enough for most application. A smaller capacitor
than this may result in an under voltage lockout of FPS dur
 Summary of symbols 
☞ Since the input power is 67 W, the DC link capacitor is set to be 150uF by 2uF/Watt.
☞ Dmax is set to be 0.48 so that Vdsnom would be about 70% of BVdss (650V×
×0.7=455V)
5. Choose the proper FPS considering the input power and current limit
Typical current limit of FPS (Iover) 2.50 A
Minimum Iover considering tolerance of 12% 2.20 A > 2.01 A
>O.K.
☞ Since the maximum peak drain current (Idspeak) is 2.0A, FSDM07652R is chosen, whose current limit
level (Iover) is 2.5A. The current limit tolerance (12%) is considered.
☞ In general, the optimum turn ratio between 5V and 3.3V is 3/2, considering the diode forward voltage
drop.
rms 2
Diameter Parallel ID(n)rms (A/mm2)
Primary winding 0.5 mm 1T 1.1 A 5.44
Vcc winding 0.3 mm 2T 0.1 A 0.71
1st output winding 0.4 mm 4T 3.5 A 6.97
2nd output winding 0.4 mm 4T 3.7 A 7.30
3rd output winding 0.4 mm 3T 2.8 A 7.30
4th output winding 0.4 mm 2T 0.9 A 3.76
5th output winding 0.4 mm 1T 0.2 A 1.55
6th output winding mm T ##### A #####
2
Copper area (Ac) = 19.70 mm
Fill factor (KF) 0.15
2
Required window area (Awr) 131.33 mm
☞ Since the windings for 3.3V and 5V are short with small number of turns, relatively large current
densities (> 5A/mm2) are allowed. The fill factor is set to be 0.15 due to multiple outputs.
VD(n) ID(n)rms
Vcc diode 70 V 0.10 A
1st output diode 20 V 3.50 A
2nd output diode 29 V 3.67 A
3rd output diode 70 V 2.75 A
4th output diode 103 V 0.95 A
5th output diode 184 V 0.19 A
6th output diode 0 V ##### A
Vcc winding UF4003 (200V /1A, VF=1V) Ultra Fast Recovery Diode
3rd output (12V) EGP30D (200V/3A, VF=0.95V) Ultra Fast Recovery Diode
4st output (18V) EGP20D (200V/2A, VF=0.95V) Ultra Fast Recovery Diode
5st output (30V) UF4004 (400V /1A, VF=1V) Ultra Fast Recovery Diode
☞ The snubber capacitor and snubber resistor are chosen as 10nF and 33kΩ
Ω, respectively. The maximum
voltage stress on the MOSFET is designed to be 84% of 650V BVdss voltage of the FSDM07652R. The
actual Vdsmax would be lower than this.
Controltooutput DC gain = 2
Controltooutput zero (wz) = 5000 rad/s => fz= 796 Hz
Controltooutput RHP zero (wrz)= 694765 rad/s => frz= 110,631 Hz
Controltooutput pole (wp)= 2153 rad/s => fp= 343 Hz
FPS vo1' vo1
Voltage divider resistor (R1) 5.6 ㏀ vFB RD
ibias
Voltage divider resistor (R2)= 18 ㏀
iD Rbias
Opto coupler diode resistor (RD) 1 ㏀ CB
1:1
B R1
KA431 Bias resistor (Rbias) 1.2 ㏀ CF RF
KA431
Feeback pin capacitor (CB) = 33 nF
Feedback Capacitor (CF) = 47 nF R2
60
16 3.64105 41 44.7 16 2 88.7 #
Controltooutput
40 25 3.63 37 40.9 25 2 88 #
40 3.60099 33 36.8 Compensator
40 4 86.8 #
63 3.53167 29 32.8 T (Closed 63loop
6 gain)85 #
Gain (dB)
20
100 3.36222 25 28.7 100 9 82.2 #
160 2.96516 21 24.4 160 ## 77.9 #
0 250 2.20575 18 20.3 250 ## 72.2 #
10 100 400 1000
0.89557 15 15.9
10000 400 ## 100000
65.2 #
630 0.6501 13 12.1 630 ## 59.7 #
20
1000 2.0185 11 8.75 1000 ## 58.3 #
1600 2.9016 9 5.74 1600 ## 62.1 #
40 2500 3.3275 6 2.74 2500 ## 68.5 #
4000 3.5257
frequency (Hz) 3 0.8 4000 8 75.2 #
6300 3.5983 1 4.5 6300 7 80.2 #
10000 3.6107 5 8.4 10000 8 83.7 #
0
16000 3.5697 9 12 16000 ## 86 #
10 100 1000 10000 100000
25000 3.4485 # 16 25000 ## 87.5 #
30
40000 3.1334 # 20 40000 ## 88.4 #
63000 2.448 # 23 63000 ## 89 #
Phase (degree)
60
100000 1.0745 # 26 1E+05 ## 89.4 #
90
120
150
180
frequency (Hz)
☞ The control bandwidth is 4kHz. Since the crossover frequency is too close to the corner frequency of the
post filter (fo=7.2 kHz), the controller is designed to have enough phase margin when ignoring the effect of
the post filter.
Design Summary
• For the FPS, FSDM07652R is chosen. This device has a fixed switching frequency of 66kHz. Startup and softstart circuits
are implemented inside the device.
• To limit the current, 10 ohms resistors (Ra and Rdamp) are used in series with Da and DR5. These damping resistors improve
the regulations of the very lightly loaded outputs.
Figure 17 shows the final schematic of the flyback converter designed by FPS Design Assistant.
VO5 33V
DR5 Rdamp 10
NS5 Co5
UF4004
47uF/ 50V
VO4 18V
EGP20D
DR4 Co4
NS4
470uF/25V
VO3 12V
Lp3 2.2 uH
DR3 EGP30D Cp3
Co3
NS3 330uF/25V
220uF/ 25V
Rsn
GBLA06 10nF
Csn 1kV VO2 5V
33k Np Lp2 2.2 uH
CDC 2W
DR2 SB560
NS2 Cp2
150uF/400V Co2
Dsn UF4007 1000uF× 2 /10V
220uF/ 10V
6
VO1 3.3V
Vstr Lp1 2.2 uH
1
1.5nF/275Vac Drain UF4003 DR1 SB540
Cp1
FPS R a 10 Da
CL2 CL2 NS1 Co1 220uF/ 10V
(DM07652R) Vcc 3
1000uF× 2 /10V
RL1 CB H11A817A
1.5M 47nF
1.2k
33nF
NTC Fuse RF
5D13 CF
KA431
18k
AC line
R2
Experimental Verification
In order to show the validity of the design procedure pre
sented in this paper, the converter of the design example has
been built and tested. All the circuit components are used as
designed in the design example and the measured trans
former characteristics are shown in table 3.
Figure 18 shows the FPS drain current and DC link voltage
waveforms at the minimum input voltage and full load con
dition. As can be seen, the maximum peak drain current
(Idspeak) is 2A and the minimum DC link voltage (VDCmin) is
about 90V. The designed values are 2.01A and 92V, respec
tively.
Figure 19 shows the FPS drain current and voltage wave
forms at the minimum input voltage and full load condition.
As designed, the maximum duty ratio (Dmax) is about 0.5
and the maximum peak drain current (Idspeak) is 2A.
Figure 20 shows the FPS drain current and voltage wave Figure 18. Waveforms of drain current and DC link
voltage at 85Vac and full load condition (time:2ms/div)
forms at the maximum input voltage and full load condition.
The maximum voltage stress on the MOSFET is about 520V,
which is lower than the designed value (547V). This is
because of the lossy discharge of the inductor or the stray
capacitance. Another reason is that the power conversion
efficiency at the maximum input voltage is higher than the
estimated efficiency used in step1.
As calculated in design step4, the converter operates at the
boundary between CCM and DCM under the maximum
input voltage and full load condition (The maximum DC link
voltage guaranteeing CCM at full load was obtained as 375V
in design step4).
Figure 21 shows the current and voltage waveforms of the
first output (3.3V) rectifier diode. The maximum reverse
voltage of this diode was calculated as 20V in step9 and the
measured value is 23V.
Table 4 shows the line regulation of each output. 3.3V and Figure 19. Waveforms of drain current and voltage
5V output shows ±3% and ±4% regulations, respectively. at 85Vac and full load condition (time : 5us/div)
Figure 22 shows the measured efficiency at the full load con
dition for different input voltages. The minimum efficiency
is about 73% at the minimum input voltage condition better
than the 70% target efficiency specified in step1.
Efficiency
0.81
0.80
0.79
0.78
0.77
0.76
0.75
0.74
0.73
0.72
85 115 145 175 205 235 265
Input voltage (Vac)
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