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AND BOOST CONVERTERS USING LINEAR AND NONLINEAR
CONTROL METHODS
Except where reference is made to the work of others, the work described in this thesis is
my own or was done in collaboration with my advisory committee. This thesis does not
include proprietary or classified information.
____________________________
Liping Guo
Certificate of Approval:
____________________________
Victor P. Nelson
Professor
Electrical and Computer
Engineering
____________________________
R. M. Nelms, Chair
Professor
Electrical and Computer
Engineering
____________________________
John Y. Hung
Associate Professor
Electrical and Computer
Engineering
____________________________
Stephen L. McFarland
Acting Dean
Graduate School
DESIGN AND IMPLEMENTATION OF DIGITAL CONTROLLERS FOR BUCK
AND BOOST CONVERTERS USING LINEAR AND NONLINEAR
CONTROL METHODS
Liping Guo
A Dissertation
Submitted to
the Graduate Faculty of
Auburn University
in Partial Fulfillment of the
Requirements for the
Degree of
Doctor of Philosophy
Auburn, Alabama
August 7, 2006
iii
DESIGN AND IMPLEMENTATION OF DIGITAL CONTROLLERS FOR BUCK
AND BOOST CONVERTERS USING LINEAR AND NONLINEAR
CONTROL METHODS
Liping Guo
Permission is granted to Auburn University to make copies of this dissertation at its
discretion, upon request of individuals or institutions and at their expense.
The author reserves all publication rights.
______________________________
Signature of Author
______________________________
Date of Graduation
iv
VITA
Liping Guo, daughter of Zongyang Guo and Shuxian Xu, was born on June 20,
1974, in Beijing, P. R. China. She attended Beijing Institute of Technology in Beijing,
and graduated with a Bachelor of Science degree in Automatic Control in July, 1997.
After working as an associate engineer in Beijing City Commercial Bank for one year,
and as a system engineer in Beijing HKD Computer Co. Ltd for another year, she entered
Graduate School, Auburn University, in September, 1999. She graduated Phi Kappa Phi
with a Master of Science degree in Electrical and Computer Engineering in August, 2001.
She married Kezhou Wang, son of Shixue Wang and Yulan Ma in Beijing, on August 8,
2000.
v
DISSERTATION ABSTRACT
DESIGN AND IMPLEMENTATION OF DIGITAL CONTROLLERS FOR BUCK
AND BOOST CONVERTERS USING LINEAR AND NONLINEAR
CONTROL METHODS
Liping Guo
Doctor of Philosophy, August 7, 2006
(M.S., Auburn University, 2001)
(B.S., Beijing Institute of Technology, 1997)
128 Typed Pages
Directed by R. M. Nelms
Issues in the design and implementation of digital controllers for a buck converter
and a boost converter using linear and nonlinear control methods were investigated in this
dissertation. The small signal models of the buck and boost converters, obtained using
standard state space averaging techniques, were utilized in the dissertation. Analog PID
and PI controllers were designed for generic buck and boost converters using standard
frequency response techniques. The controllers were then transformed into digital
controllers.
The small signal models of the converters change with the variations of the
operating point. Since the linear controllers were designed based on the small signal
vi
models, they were not able to respond effectively to changes in operating point. To
achieve a stable and fast response, nonlinear control methods were applied to the buck
and boost converters. Since fuzzy controllers don’t require a precise mathematical model,
they are well suited to nonlinear, timevariant systems. Fuzzy controllers were designed
for the buck and boost converters. Two structures of fuzzy controllers are investigated in
this dissertation. Only one structure was applied to the buck converter, and both
structures were applied to the boost converter to obtain satisfactory response. The second
nonlinear control method investigated in this dissertation was sliding mode fuzzy
controller. The sliding mode fuzzy controller combined the advantages of both fuzzy
controllers and sliding mode controllers. Sliding mode fuzzy controllers are designed for
the boost converter.
The digital controllers designed using linear and nonlinear control methods were
implemented on a TI DSP. Experimental results for the buck and boost converters were
presented and compared. Experimental results verify that nonlinear controllers have
superior performance over linear controllers under the change of operating points.
vii
ACKNOWLEDGEMENTS
This research was supported by the Center for Space Power and Advanced
Electronics with funds from NASA grant NCC3511, Auburn University, and the
Center’s industrial partners.
The author wishes to thank her major professor Dr. R. M. Nelms most deeply for
his guidance through her graduate studies. The author would like to thank Dr. John Y.
Hung and Dr. Victor P. Nelson for many insightful suggestions which they have offered.
Finally, the author would like to extend her heartfelt gratitude to her parents and
her husband for their love, support and encouragement while pursuing her course of
study.
viii
Style Manual or Journal Used:
Bibliography conforms to those in the Institute of Electrical and Electronics
Engineers Transactions on Power Electronics
Computer Software Used:
Microsoft
®
Windows XP Operating Systems
Microsoft
®
Word 2002
Microsoft
®
Excel 2002
MATLAB
®
Version 6.5
Simulink Version 5.0
Visio
®
2000 for Microsoft Windows
TI C2000 Code Composer Studio IDE
Acrobat Distiller 4.0
ix
TABLE OF CONTENTS
LIST OF FIGURES ........................................................................................................... xi
LIST OF TABLES............................................................................................................ xv
1 INTRODUCTION.......................................................................................................... 1
1.1 SwitchMode DCDC Converters............................................................................. 2
1.1.1 Buck Converter .................................................................................................. 2
1.1.2 Boost Converter ................................................................................................. 4
1.2 Control of DCDC Converters.................................................................................. 5
1.3 Literature Review...................................................................................................... 6
2 EXPERIMENTAL TESTBED..................................................................................... 14
2.1 Hardware................................................................................................................. 14
2.2 TMS320F2812 DSP Evaluation Module................................................................ 18
2.2.1 TMS320F2812 Overview................................................................................ 18
2.2.2 Memory Map ................................................................................................... 19
2.2.3 AnalogtoDigital Converter Module .............................................................. 19
2.2.4 Event Manager Module.................................................................................... 21
2.2.5 Interrupts.......................................................................................................... 23
2.2.6 Code Development Tool .................................................................................. 25
3 LINEAR CONTROL DESIGN FOR DCDC CONVERTERS................................... 29
3.1 StateSpace Averaged Model for DCDC Converters............................................ 30
3.1.1 Buck Converters............................................................................................... 31
3.1.2 Boost Converters.............................................................................................. 34
3.2 Digital Controller Design for DCDC Converters Using Frequency Response
Techniques .................................................................................................................... 37
3.2.1 Buck Converters............................................................................................... 40
3.2.1.1 PID Controller Design for Buck Converters............................................. 41
3.2.1.2 PI Controller Design for Buck Converters................................................ 42
3.2.2 Boost Converters.............................................................................................. 43
3.2.2.1 PID Controller Design for Boost Converters............................................ 43
3.2.2.2 PI Controller Design for Boost Converters............................................... 44
3.2.3 Transformation from an Analog Controller to a Digital Controller ................ 44
3.3 Implementation of Digital Controllers.................................................................... 45
3.3.1 Program Structure ............................................................................................ 46
x
3.3.2 Implementation of Digital PID and PI Controllers.......................................... 48
4 FUZZY CONTROLLER DESIGN FOR DCDC CONVERTERS............................. 52
4.1 Introduction to Fuzzy Control................................................................................. 53
4.2 Fuzzy Control Design for DCDC Converters........................................................ 54
4.2.1 Fuzzification .................................................................................................... 57
4.2.2 Rule Base ......................................................................................................... 59
4.2.3 Inference Mechanism....................................................................................... 59
4.2.4 Defuzzification................................................................................................. 60
4.3 Implementation of Fuzzy Controllers ..................................................................... 60
5 SLIDING MODE FUZZY CONTROLLER DESIGN FOR DCDC CONVERTERS66
5.1 Design of Sliding Mode Fuzzy Controller for DCDC Converters ........................ 68
5.1.1 Switching Functions ........................................................................................ 69
5.1.2 Inputs and Their Scaling Factors ..................................................................... 72
5.1.3 Rule Base ......................................................................................................... 74
5.1.4 Inference Mechanism and Defuzzification Method......................................... 76
5.2 Implementation of Sliding Mode Fuzzy Controller................................................ 77
6 EXPERIMENTAL RESULTS...................................................................................... 79
6.1 Experimental Results for PID and PI Controllers................................................... 79
6.1.1 Buck Converter ................................................................................................ 79
6.1.2 Boost Converter ............................................................................................... 81
6.2 Experimental Results for Fuzzy Controllers........................................................... 82
6.2.1 Buck Converter ................................................................................................ 82
6.2.2 Boost Converter ............................................................................................... 86
6.3 Experimental Results for Sliding Mode Fuzzy Controllers.................................... 90
6.3.1 Boost Converter ............................................................................................... 90
6.3.2 Buck Converter ................................................................................................ 92
6.4 Comparison of Experimental Results of Linear and Nonlinear Control Methods.. 95
6.4.1 Buck Converter ................................................................................................ 95
6.4.2 Boost Converter ............................................................................................. 102
7 CONCLUSION AND FUTURE WORK................................................................... 104
BIBLIOGRAPHY........................................................................................................... 109
xi
LIST OF FIGURES
1.1 Buck Converter ............................................................................................................ 3
1.2 PWM signal to control the switches in the DCDC converters ................................... 3
1.3 Equivalent circuit of the buck converter when the switch is closed............................ 4
1.4 Equivalent circuit of the buck converter when the switch is open .............................. 4
1.5 Boost converter ............................................................................................................ 5
1.6 Equivalent circuit of the boost converter when the switch is closed ........................... 5
1.7 Equivalent circuit of the boost converter when the switch is open.............................. 5
2.1 Circuit schematic of digital control system of the buck converter ............................ 15
2.2 Circuit schematic of digital control system of the boost converter ........................... 15
2.3 Functional diagram of HCPL3180 high speed gate drive optocoupler .................... 17
2.4 F2812 memory map................................................................................................... 20
2.5 Flowchart of the operation for CPU maskable interrupts .......................................... 26
2.6 Flow chart for code development in CCStudio IDE.................................................. 27
3.1 Bode plot of the statespace averaged model of the buck converter.......................... 33
3.2 Frequency response of the buck converter obtained by the analog analyzer............. 33
3.3 Bode plot of the statespace averaged model of the boost converter......................... 36
3.4 Comparison of the actual and theoretical frequency response of the boost converter36
3.5 Comparison of the frequency response obtained using the analog analyzer and from
the generated transfer function.......................................................................................... 37
xii
3.6 Bode plot of PID controller compensated buck converter......................................... 41
3.7 Bode plot of PI controller compensated buck converter............................................ 42
3.8 Bode plot of PID controller compensated boost converter........................................ 43
3.9 Bode plot of PI controller compensated boost converter........................................... 44
3.10 Overview of the program structure for digital controllers ....................................... 47
3.11 Block diagram of digital PID controller .................................................................. 49
3.12 Flowchart of digital PID and PI controller .............................................................. 51
4.1 Block diagram of fuzzy control system..................................................................... 54
4.2 Simulink model of the fuzzy controller for the DCDC converters Method 1: (d[k] =
d[k1]+h*δd[k].)................................................................................................................ 56
4.3 Simulink model of the fuzzy controller with a linear integrator for the DCDC
converters Method 2:(d[k] = K
I
*I[k]+h*δd[k])................................................................. 57
4.4 Membership functions of the inputs e[k] and ce[k] for the buck converter ............... 58
4.5 Membership functions of the inputs e[k] and ce[k] for the boost converter .............. 58
4.6 Flowchart of fuzzy controller using method 1........................................................... 61
4.7 Flowchart of fuzzy controller with a linear integrator ............................................... 62
5.1 Switching function of the sliding mode fuzzy controller for boost converter ........... 71
5.2 Step response of the switching function for boost converter..................................... 71
5.3 Step response of switching function for buck converter............................................ 72
5.4 Membership functions of the inputs e[k] and ce[k] for the boost converter .............. 73
5.5 Function between ci and s(x) ..................................................................................... 75
5.6 Simulink model of the system using sliding mode fuzzy controller for the DCDC
converters.......................................................................................................................... 78
6.1 Start up transient response of the buck converter using the linear PID and PI control
method............................................................................................................................... 80
xiii
6.2 Transient response for the buck converter using the linear PID and PI control method
when the load changed from 1.364 A to 0.16 A............................................................... 80
6.3 Start up transient response of the boost converter using the linear PID and PI control
method............................................................................................................................... 81
6.4 Transient response for the boost converter using the linear PID and PI control
method when the load changed from 0.24 A to 0.48 A.................................................... 82
6.5 Start up transient response of the buck converter using the second fuzzy control
method with 17*17 rule base ............................................................................................ 84
6.6 Transient response for the buck converter using the second fuzzy control method
with 17*17 rule base when the load changed from 1.364 A to 0.16 A............................. 85
6.7 Start up transient response of the buck converter using the second fuzzy control
method with 7*7 rule base ................................................................................................ 85
6.8 Transient response for the buck converter using the second fuzzy control method
with 7*7 rule base when the load changed from 1.364 A to 0.16 A................................. 86
6.9 Start up transient response of the boost converter using the second fuzzy control
method............................................................................................................................... 87
6.10 Transient response for the boost converter using the first fuzzy control method
when the load changed from 0.24 A to 0.48 A................................................................. 89
6.11 Start up transient response of the boost converter using sliding mode fuzzy control
with different input voltage............................................................................................... 91
6.12 Transient response of the boost converter using sliding mode fuzzy control when
the load current changed from 0.24 A to 0.48 A .............................................................. 91
6.13 Start up transient response of the buck converter using sliding mode fuzzy
controller with different input voltage .............................................................................. 93
6.14 Steadystate response of the buck converter with the PWM signal......................... 94
6.15 Load transient response of the buck converter using sliding mode fuzzy controller
when the load changed from 0.96 A to 0.48 A with different input voltage .................... 94
6.16 Load transient response of the buck converter using sliding mode fuzzy controller
when the load changed from 0.48 A to 0.96 A with different input voltage .................... 95
xiv
6.17 Start up transient response of the buck converter using ordinary fuzzy controller
with different input voltage............................................................................................... 96
6.18 Load transient response using ordinary fuzzy controller when the load changed
from 0.96A to 0.48A with different input voltage............................................................ 97
6.19 Load transient response using ordinary fuzzy controller when the load changed
from 0.48 A to 0.96 A with different input voltage.......................................................... 97
6.20 Start up transient response of the buck converter using PID/PI controller with
different input voltage....................................................................................................... 99
6.21 Load transient response using PID/PI controller when the load changed from 0.96 A
to 0.48 A with different input voltage............................................................................... 99
6.22 Load transient response using PID/PI controller when the load changed from 0.48 A
to 0.96 A with different input voltage............................................................................. 100
xv
LIST OF TABLES
2.1 Configuration of eventmanager modules EVA and EVB ........................................ 22
5.1 7×7 Rule base of the sliding mode fuzzy controller .................................................. 76
6.1 Comparison of Performance of Sliding Mode Fuzzy Control vs. Ordinary Fuzzy
Control vs. PID/PI Control for Buck Converter ............................................................. 101
6.2 Comparison of Performance of PID Control, Fuzzy Control, and Sliding Mode Fuzzy
Control for the Boost Converter ..................................................................................... 103
1
CHAPTER 1
INTRODUCTION
Switch mode DCDC converters efficiently convert an unregulated DC input
voltage into a regulated DC output voltage. Compared to linear power supplies, switching
power supplies provide much more efficiency and power density. Switching power
supplies employ solidstate devices such as transistors and diodes to operate as a switch:
either completely on or completely off. Energy storage elements, including capacitors
and inductors, are used for energy transfer and work as a lowpass filter. The buck
converter and the boost converter are the two fundamental topologies of switch mode
DCDC converters. Most of the other topologies are either buckderived or boostderived
converters, because their topologies are equivalent to the buck or the boost converters.
Traditionally, the control methodology for DCDC converters has been analog
control. In the recent years, technology advances in verylargescale integration (VLSI)
have made digital control of DCDC converters with microcontrollers and digital signal
processors (DSP) possible. The major advantages of digital control over analog control
are higher immunity to environmental changes such as temperature and aging of
components, increased flexibility by changing the software, more advanced control
techniques and shorter design cycles. Generally, DSPs have more computational power
than microcontrollers. Therefore, more advanced control algorithms can be implemented
on a DSP.
2
1.1 SwitchMode DCDC Converters
Switchmode DCDC converters are used to convert the unregulated DC input to
a controlled DC output at a desired voltage level. Switchmode DCDC converters
include buck converters, boost converters, buckboost converters, Cuk converters and
fullbridge converters, etc. Among these converters, the buck converter and the boost
converter are the basic topologies. Both the buckboost and Cuk converters are
combinations of the two basic topologies. The fullbridge converter is derived from the
buck converter.
There are usually two modes of operation for DCDC converters: continuous and
discontinuous. The current flowing through the inductor never falls to zero in the
continuous mode. In the discontinuous mode, the inductor current falls to zero during the
time the switch is turned off. Only operation in the continuous mode is considered in this
dissertation.
1.1.1 Buck Converter
The buck converter, shown in Figure 1.1, converts the unregulated source voltage
Vin into a lower output voltage Vout. The NPN transistor shown in Figure 1.1 works as a
switch. The ratio of the ON time ( ON t ) when the switch is closed to the entire switching
period (T) is defined as the duty cycle D =
ON
T
t
. The corresponding PWM signal is
shown in Figure 1.2 [1].
3
+

Vin
iin
Diode
Inductor
Capacitor Load Vout
+
_
Gate Drive
Figure 1.1 Buck Converter
Switching Period (T)
tON
Figure 1.2 PWM signal to control the switches in the DCDC converters
The equivalent circuit in Figure 1.3 is valid when the switch is closed. The diode
is reverse biased, and the input voltage supplies energy to the inductor, capacitor and the
load. When the switch is open as shown in Figure 1.4, the diode conducts, the capacitor
supplies energy to the load, and the inductor current flows through the capacitor and the
diode [2]. The output voltage is controlled by varying the duty cycle. During steady state,
the ratio of output voltage over input voltage is D, which is given by (1.1).
Vout
D
Vin
= (1.1)
4
+

Vin
iin Inductor
Capacitor Load Vout
+

Figure 1.3 Equivalent circuit of the buck converter when the switch is closed
Inductor
Capacitor Load Vout
+
_
Figure 1.4 Equivalent circuit of the buck converter when the switch is open
1.1.2 Boost Converter
The boost converter, shown in Figure 1.5, converts an unregulated source voltage
Vin into a higher regulated load voltage Vout. When the switch is closed as shown in
Figure 1.6, the diode is reverse biased and the input voltage supplies energy to the
inductor while the capacitor discharges into the load. When the switch is opened as
shown in Figure 1.7, the diode conducts and both energy from the input voltage and
energy stored in the inductor are supplied to the capacitor and the load; thus the output
voltage is higher than the input voltage [3]. During steady state operation, the ratio
between the output and input voltage is
1
1 D −
, which is given in (1.2). The output
voltage is controlled by varying the duty cycle.
5
+

Vin
Diode
Inductor
Capacitor Load Vout
+
_
Gate
Drive
Figure 1.5 Boost converter
+

Vin
Inductor
Capacitor Load Vout
+
_
Figure 1.6 Equivalent circuit of the boost converter when the switch is closed
+

Vin
Inductor
Capacitor Load Vout
+
_
Figure 1.7 Equivalent circuit of the boost converter when the switch is open
1
1
Vout
Vin D
=
−
(1.2)
1.2 Control of DCDC Converters
The output voltage of the switchmode DCDC converters are regulated to be
within a specified range in response to changes in the input voltage and the load current.
6
There are two control methods for DCDC converters: voltage mode control and current
mode control [2].
In voltage mode control, the converter’s output voltage is compared with a
reference to generate the voltage error signal. The duty cycle is adjusted based on the
error signal to make the output voltage follow the reference value. Frequency response
methods are usually used in the design of voltage mode controllers for DCDC
converters. Small signal models of the converters are first obtained by linearizing the
power stage of the converters around an operating point, then a compensator is designed
based on the small signal model. Typical compensators include phaselead compensator,
phaselag compensator and leadlag compensator. In analog control, the compensators are
implemented using operational amplifiers and appropriate values of resistors and
capacitors to obtain the desired transfer function. In digital control, the control algorithm
is implemented on a microcontroller or DSP.
Current mode control for a DCDC converter is a twoloop system. An additional
inner current loop is added to the voltage loop. The current loop monitors the inductor
current and compares it with its reference value. The reference value for the inductor
current is generated by the voltage loop.
1.3 Literature Review
The research problem addressed in this dissertation is the design and
implementation of digital controllers for buck and boost converters on a DSP using linear
and nonlinear control methods. Digital controllers were implemented on a TI DSP.
Experimental results for the controllers have been evaluated and compared for prototype
buck and boost converters.
7
Digital control for DCDC converters is theoretically interesting because it is a
multidisciplinary research. Theory in the areas of power electronics, systems and control,
and computer systems are all needed to conduct research in digital control of DCDC
converters. The increasing interest in digital control of switch mode power supplies is
shown in international conference proceedings and journal publications in the past few
years. Duan and Jin from University of British Columbia made a thorough evaluation of
different digital control design methods for DCDC converters [4]. The methods include
direct and indirect design approaches. In the direct design approach, small signal models
of the converters are first converted into discretetime models, and digital controllers are
directly designed based on the discretetime models. In the indirect design approach,
analog controllers are first designed based on the small signal models of the converters,
and then converted into digital controllers. The best approach is determined based on a
comparison of experimental results. It was concluded that the direct design approach is
better than an indirect design approach. Backward integration methods were suggested to
be a better discretization method for the indirect design approach. Bibian and Jin from the
University of British Columbia studied two prediction techniques for the compensation of
digital control time delay in DCDC converters. Modified predictor and simplified
predictor were developed to increase the bandwidth of the control loop [5]. Vallittu,
Suntio and Ovaska studied the opportunities and constraints of digital control of power
supplies. The advantages and disadvantages of analog and digital control of power
supplies were compared in [6].
Linear controller design methods mainly include frequency response and root
locus techniques [7]. The small signal models of buck and boost converters are obtained
8
using standard state space averaging techniques [2, 3]. Linear controllers are designed
using frequency response techniques and root locus techniques. In this dissertation,
analog PID and PI controllers were first designed using standard frequency response
techniques based on the small signal model of the converters. The analog controllers were
then transformed into digital controllers.
When using the root locus techniques, the small signal models are first
transformed into discretetime models. Digital controllers are then designed based on the
discretetime models using the root locus method. A digital controller was designed for a
buck converter based on root locus techniques in [8]. The analog plant consists of the
buck converter’s model, the pulse width modulator, and the A/D converter. The analog
plant was transformed into a discretetime transfer function, and then a digital controller
was directly designed.
The small signal models for the converters change due to variations in operating
point. The boost converter’s small signal model is a nonlinear function of the operating
point, while only the magnitude of the buck converter’s small signal model shifts with the
change of operating point [3]. The linear controllers were designed only for the nominal
operating point.
To achieve a stable and fast response under varying operating points, there are
two possible solutions. One is to develop a more accurate model for the converter.
However, the model may be too complex to use in controller development. A second
solution is to use a nonlinear controller [9]. After designing and implementing linear
controllers for the buck and boost converters, nonlinear controllers were designed and
implemented for the converters.
9
Among the various techniques of artificial intelligence, the most popular and
widely used technique in control systems is fuzzy control [9]. Fuzzy controllers are
designed based on the general knowledge of the converters. The controller is then tuned
using a trial and error method to obtain satisfactory response. Since a fuzzy controller is a
nonlinear controller, it can adapt to a varying operating point.
Many researchers have investigated fuzzy controllers for DCDC converters.
Viswanathan, Srinivasan and Oruganti studied the development of a universal fuzzy
controller for a boost converter [9]. Simulation results were compared with the results of
a PI controller under varying operating points. The performance of the fuzzy controller
was superior to the performance of the PI controller. Mattevelli and Spiazzi investigated a
generalpurpose fuzzy controller for DCDC converters [10]. The fuzzy controller
improved performance in terms of overshoot limitations and sensitivity to parameter
variations compared to standard controllers. Simulation results for buckboost and Sepic
converters were presented. Perry and Sen proposed a design procedure that integrated
linear control techniques with fuzzy logic [11]. The small signal model for the converters
and linear design techniques were used in the initial stages of fuzzy controller design.
Simulation and experimental results were presented and compared with results of a
digital PI controller. Butkiewicz investigated steadystate error of a system with fuzzy
controllers [12]. Wang and Lee designed a fuzzy controller for basic DCDC converters
and then compared the computer simulation results with those for currentmode control in
buck, boost and buckboost converters [13]. It was concluded from the comparison of
startup responses and load regulation tests that the currentmode controlled buck
converter had a faster transient response and better load regulation, while the fuzzy
10
controller for both boost and buckboost converters had less steadystate error and better
transient response. J. Arias, A. Arias, et al. proposed a design procedure for a fuzzy logic
controller for a buck converter [14]. The control rules were derived from analysis of the
system dynamics in the state plane. This design procedure can be applied to other
converter topologies. Gomariz, Guinjoan, et al. applied the describing function
techniques to a tworule fuzzy controller for boost converters [15]. Scaling factors
boundaries were established to avoid oscillatory behavior in the system. This technique
facilitated theoretical design and analysis of fuzzy controllers. Simulation results for the
boost converter were presented in order to validate the considerations. Campo and Tarela
investigated the consequences of the finite word length on the performance of a digital
fuzzy logic controller [16]. There were three types of error as a result of the finite word
length: AD conversion errors, membership function errors and arithmetic errors.
Simulation results showed that bias and limit cycles were generated due to the
quantization. The bias and limit cycles were difficult to predict because of the nonlinear
nature of the both quantization and fuzzy controllers.
Many studies of fuzzy controllers for DCDC converters have only been
supported by simulation results, and have not been verified by experimental results. In
this dissertation, experimental results of the fuzzy controllers for buck and boost
converters have been obtained and compared with the results for linear controllers. Two
structures of fuzzy controllers have been studied. The first structure is more prevalently
used than the second structure [17,18,19]. In this dissertation, only the second method
was applied to the buck converter to obtain satisfactory response, while for the boost
converter, a combination of both methods was applied to obtain the desired response.
11
Sliding mode control of DCDC converters has been widely investigated by
researchers [2033]. A sliding mode is achieved by forcing the system trajectory on a
properly designed switching function using high speed switch control. Sliding mode
control is a powerful method that can yield a very robust closedloop system under plant
uncertainties and external disturbances. The sliding mode can be entirely independent of
the effects of modeling uncertainties, parameter fluctuations and disturbances. Hung, Gao
and Hung had a very thorough tutorial about variable structure control with sliding mode
[20]. Fundamental theory, main results and practical applications of sliding mode control
were introduced. Mahdavi, Emadi and Toliyat designed sliding mode controllers for
buck, boost, buckboost and Cuk converters based on the statespaceaveraging method
[21]. The controllers were simulated, and satisfactory simulation results were obtained.
Cortes and Alvarez investigated several sliding surface designs for boost converters [22].
They proposed sliding surfaces that do not depend on the load to eliminate the necessity
for current measurement. VidalIdiarte, MartinezSalamero, et al. presented a twoloop
control for a boost converter [23]. An inner loop controlled the inductor current using
sliding mode control. The outer loop used a fuzzy controller to implement the voltage
loop. The controller implementation used analog components for the inner loop and an 8
bit microcontroller for the outer loop. Orosco and Vazquez analyzed discrete sliding
mode control for DCDC converters [24]. The analysis included the reaching condition,
proof of the existence condition of the sliding mode and stability conditions. Simulation
results were presented. Shi and Sen conducted a study of different types of PIDlike
fuzzy logic controllers for application to DCDC converters [25]. Raviraj and Sen
performed a comparative evaluation of the PI, sliding mode and fuzzy logic controllers
12
for application to DCDC converters. Ahmed, Kuisma et al. presented implementation of
a sliding mode controller for a buck converter [26].
Most research on sliding mode controllers for DCDC converters has been limited
to continuous time, and only simulation results have been presented. Furthermore, several
disadvantages exist for sliding mode control. Because infinitely fast switching of the
control action is impossible in practice, chattering always occurs in steady state. A
constant switching frequency can’t be guaranteed. This issue has prevented sliding mode
control from being extensively applied to DCDC converters.
In this dissertation, a sliding mode fuzzy controller was proposed to control a DC
DC boost converter. The sliding mode fuzzy controller combines the advantages of both
fuzzy controllers and sliding mode controllers [34]. It is more robust than an ordinary
sliding mode controller. The sliding surface in a sliding mode fuzzy controller is rendered
by rule bases and scaling factors, rather than a function. The sliding mode fuzzy control
has advantages of its own that cope with the problems in the sliding mode control and
fuzzy control design and implementation.
All the digital controllers discussed here were implemented on a TI
TMS320F2812 DSP. The F2812 DSP is a 32bit, fixed point DSP. The clock frequency is
150 MHz. It supports peripherals used for embedded control applications, such as event
manager modules for PWM output and a dual 12bit, 16 channel ADC.
Described in Chapter 2 of this dissertation is the experimental testbed including
hardware configuration and main features of the DSP controller from Texas Instruments.
In Chapter 3, digital controllers are designed for DCDC converters using linear control
methods. Frequency response techniques are applied to design digital controllers for the
13
buck and boost converters. The transformation from analog controller to digital controller
and implementation of digital controllers are also discussed in Chapter 3. The design and
implementation of fuzzy controllers for DCDC converters is discussed in Chapter 4.
Design and implementation of sliding mode fuzzy controllers is presented in Chapter 5.
Laboratory results for the buck and the boost converters are presented and compared in
Chapter 6. In Chapter 7, the research is summarized and suggestions for future work are
made.
14
CHAPTER 2
EXPERIMENTAL TESTBED
Implementation of digital controllers for the buck and the boost converters
required both hardware and software. Described in this chapter are the hardware
components, including the DCDC converters, the gate drive and the digital signal
processor (DSP). In the first section of this chapter, the hardware configuration of the
experimental testbed is described. In the second section of this chapter, detailed
information about the Texas Instrument DSP is presented. The control algorithms of
linear and nonlinear controllers were all implemented on the TI DSP.
2.1 Hardware
The complete circuit schematics of the digital control system of the buck and
boost converters are shown in Figure 2.1 and Figure 2.2, respectively. The schematics
can be divided into four functional blocks: the DCDC converter, the input to the ADC,
the digital signal processor (DSP) and the gate drive.
The buck converter block is the common topology of the buck converter. It
consists of the source voltage, two input filter capacitors (470 µF and 0.47 µF), a fast
recovery diode (MBR3045PT), a MOSFET (IRFZ34N) as the switching device, output
capacitors and a load resistor of 10 Ω. The output capacitors are made of four capacitors
in parallel to reduce the equivalent series resistance (ESR). The total value of the output
capacitor C is 1000 µF. The ESR is estimated to be 30 mΩ [18,19].
15
Vin=20V
470uF 0.47uF
L=150uH
470uF 330uF 100uF 100uF
Load=
10 Ohm
TMS320F2812
T2PWM
GNDA
VCC
HCPL3180
1
2
3
4
8
7
6
5
NC
ANODE
CATHODE
NC
Vcc
Vo
Vo
GND
Buck Converter
Digital Signal
Processor
Gate Drive
DC
15V MM74HC04
3.3V
150 Ohm
0.5uF
1.3 KOhm
IRFZ34N
51 Ohm
MBR3045PT
56 KOhm 3V
OP184F
Input to ADC
10KOhm
GND
ADCINA3
8.2 KOhm
Figure 2.1 Circuit schematic of digital control system of the buck converter
Load=
25 Ohm
TMS320F2812
T2PWM
GNDA
VCC
HCPL3180
1
2
3
4
8
7
6
5
NC
ANODE
CATHODE
NC
Vcc
Vo
Vo
GND
Boost Converter
Digital Signal
Processor
Gate Drive
DC
15V MM74HC04
3.3V
150 Ohm
0.5uF
1.3 KOhm
51 Ohm
47KOhm 3V
OP184F
Input to ADC
10KOhm
GND
ADCINA3
8.2 KOhm
220uF 0.1uF 330uF 330uF 330uF 33uF 33uF
IRFZ14N
Vin=5V
MBR1545CT L=260uH
Figure 2.2 Circuit schematic of digital control system of the boost converter
16
The input to the analog to digital converter is connected to a voltage divider and a
unity gain buffer. The ADC of the DSP is able to receive an input voltage as high as 3 V,
but the output voltage of the buck converter is targeted at 12 V. The output voltage of the
buck converter is divided by the ratio of
6 . 6
1
, and thus limited to be under 3 V before it is
applied to the ADC. The function of the unity gain buffer is protection for the ADC. The
operational amplifier OP184F features railtorail input and output. Since the voltage
supply for the operational amplifier is 3 V, the output of the op amp will be less than or
equal to 3 V.
The third block is the gate drive. The MOSFET requires proper external gate
signals for turnon and turnoff. The switch will be on when gatetosource voltage VGS
is greater than the threshold voltage Vth, and off when VGS is less than Vth. The gate is
voltage controlled. Generally, Vth is about 2 to 4 V. In a practical gate drive design, a
higher V
GS
is more applicable in the converter design. In the buck converter, the ground
of the gate drive should be floating to avoid a short circuit. To achieve this, an
optocoupler was used to isolate the gate drive’s ground from the circuit’s common
ground. As is shown in the gate drive block in Figure 2.1, an HCPL3180 high speed gate
drive optocoupler from Agilent Technologies was used. The HCPL3180 is an
optocoupler integrated with a high speed gate drive. It features 2.0 A maximum peak
output current, 250 kHz maximum switching speed, 200 ns maximum propagation delay,
wide operating temperature range of 40
o
Cto 100
o
C, wide Vcc operating range of 10 V
to 20 V and 20 ns typical pulse width distortion. It is well suited to supply high frequency
gate signals for the MOSFETs and IGBTs used in high performance DCDC converters
17
and switching power supply applications. The functional diagram of the HCPL3180 is
shown in Figure 2.3 [35]. The LED across pins 2 and 3 is optically coupled to an
integrated circuit with a power stage.
Figure 2.3 Functional diagram of HCPL3180 high speed gate drive optocoupler
In Figure 2.1, at the input of the HCPL3180, a CMOS inverter MM74HC04
serves as an interface between the DSP and the optocoupler. The MM74HC04 has a
typical propagation delay of only 8 ns. It is very small compared to the switching period
of 6.67 µs.
In the digital control system of the boost converter shown in Figure 2.2, the block
for the boost converter is a generic boost converter. The block includes the source
voltage, two input filter capacitors (220 µF and 0.1 µF), a fast recovery diode
(MBR1545CT), a MOSFET (IRFZ14N) as the switching device, an output capacitor and
a load resistor of 25 Ω. The output capacitor C is made of five capacitors in parallel to
reduce the ESR. The total value of the capacitors is 1056 µF. Details about the
TMS320F2812 DSP controller will be presented in the next section.
18
2.2 TMS320F2812 DSP Evaluation Module
The TMS320 family of digital signal processors (DSP), produced by Texas
Instruments, is composed of fixed point, floating point and multiprocessor DSPs. The
TMS320 family has three DSP platforms: the TMS320C6000
TM
DSP, the
TMS320C5000
TM
DSP, and the TMS320C2000
TM
DSP. The TMS320C2000
TM
DSP
platform is optimized for control applications. The TMS320F2812 DSP belongs to the
TMS320C28x generation, which is the newest member of the TMS320C2000
TM
DSP
platform. By integrating the DSP core and onchip peripherals, the TMS320C28x DSP
generation offers a highperformance solution to digital control. It targets a wide variety
of digital control applications including industrial control, motor control and automobile
control applications.
2.2.1 TMS320F2812 Overview
The TMS320F2812 is a 32bit fixed point DSP controller with onboard flash
memory [36]. The CPU operates at 150 MHz. The C28x DSP generation is efficient in
executing C and C++ programs, hence enabling control algorithms to be developed in
high level languages. The F2812 supports the peripherals used for embedded control and
communication, such as an event manager module for pulsewidthmodulation (PWM)
and a dual 12bit, 16channel analogtodigital converter (ADC).
. The TMS320F2812 DSP controller comes in a 176 pin package. The pins can be
categorized according to function: address and data bus, interface control signals, ADC
inputs, bit I/O and shared functions bits, serial communication interface, compare signals,
interrupts signals, clock signals and test signals.
19
2.2.2 Memory Map
The C28x uses 32bit data addresses and 22bit program addresses. This allows
for a total address reach of 4G words in data space and 4M words in program space.
Memory blocks on all C28x designs are uniformly mapped to both program and data
space. Therefore, memory blocks can be used to execute code or for data variables. The
memory map for the TMS320F2812 is shown in Figure 2.4. The memory map is divided
into three segments: onchip program/data memory, CPU interrupt vectors and reserved
memory.
The memory blocks M0 and M1 are single access onchip RAM (SARAM). Each
of these blocks is 1K words in size. M0 is mapped at address 00 0000
16
– 00 03FF
16
and
M1 is mapped at addresses 00 0400
16
– 00 07FF
16
. L0 and L1 are two blocks of 4K words
SARAM. H0 is a block of 8K words SARAM. In total, there are five blocks of SARAM
with 18K words in size. There is a block of 128K words FLASH mapped at addresses 3D
8000
16
– 3F 7FF8
16
.
2.2.3 AnalogtoDigital Converter Module
The AnalogtoDigital Converter (ADC) module is a dual 12bit, 16channel
ADC [37]. The 12bit ADC has a builtin sampleandhold circuit. The 16 channels
provide multiplexed inputs to the ADC, as there is only one converter in the ADC
module. The channels can be configured as two independent 8channel modules or
cascaded to form a 16channel module. Autosequencing capability provides up to 16
autoconversions in a single session. Each conversion can be programmed to select any 1
of 16 input channels. Autosequencing allows the system to convert the same channel
multiple times, allowing the user to perform oversampling algorithms. This gives
20
increased resolution over traditional singlesampled conversion results. The conversion
time is 200 ns for a single conversion and 60 ns for pipelined conversions.
Data Space Program Space
M0 Vector – RAM (32x32)
(Enabled if VMAP = 0)
M0 SARAM (1Kx16)
M1 SARAM (1Kx16)
Peripheral Frame 0 (2Kx16)
PIE Vector – RAM (256x16)
(Enabled if VMAP=1, ENPIE=1)
Reserved
Reserved
Reserved
Peripheral Frame1 (4Kx16)
Peripheral Frame2 (4Kx16)
Reserved
L0 SARAM (4Kx16, secure block)
L1 SARAM (4Kx16, secure block)
Reserved
OTP (1Kx16, secure block)
Reserved (1K)
FLASH (128Kx16, secure block)
128bit password
H0 SARAM (8Kx16)
Reserved
Boot ROM (4Kx16)
BROM Vector – ROM (32x32)
Figure 2.4 F2812 memory map
The analog input is limited from 0 to 3 V. The digital value of the ADC can be
represented by (2.1), where ADCLO is the ground reference value for ADC.
Digital value =4095 ×
3
log ADCLO Voltage Ana Input −
(2.1)
0x00 0000
0x00 0040
0x00 0400
0x00 0800
0x00 0D00
0x00 0E00
0x00 2000
0x00 6000
0x00 7000
0x00 8000
0x00 9000
0x00 A000
0x3D 7800
0x3D 7C00
0x3D 8000
0x3F 7FF8
0x3F 8000
0x3F A000
0x3F F000
0x3F FFC0
21
Multiple triggers serve as sources for the start of an A/D conversion sequence.
The triggers are: (1) software immediate start, (2) event manager A (multiple event
sources within EVA), (3) event manager B (multiple event sources within EVB), and (4)
external pins.
2.2.4 Event Manager Module
The eventmanager (EV) modules provide a broad range of functions that are
particularly useful in motor control and power converter control applications [38]. The
EV modules include generalpurpose (GP) timers, fullcompare/PWM units, capture
units, and quadratureencoder pulse (QEP) circuits. The two EV modules, EVA and
EVB, are identical peripherals, intended for multiaxis/motioncontrol applications. Up to
eight PWM waveforms (outputs) can be generated simultaneously by each EV module:
three independent pairs (six outputs) by the three full compare units with programmable
deadbands and two independent PWMs. The complete configuration of the event
manager modules EVA and EVB is shown in Table 2.1.
There are two GP timers in each EV module. The GP timer x (x=1 or 2 for EVA;
x=3 or 4 for EVB) includes: a 16bit timer, up/down counter, TxCNT, for reads or writes,
a 16bit timercompare register, TxCMPR, for reads or writes, a 16bit timerperiod
register TxPR, for reads or writes, a 16bit timercontrol register, TxCON, for reads or
writes, selectable internal or external input clocks, a programmable prescaler for internal
or external clock inputs, control and interrupt logic, for four maskable interrupts
underflow, overflow, timer compare, and period interrupts, and GP timer output pin
TxCMP (x=1,2,3,4). The two GP timers can be used in applications such as: the
generation of sampling period for digital control system, providing a time base for the
22
operation of compare units and PWM outputs, and providing a time base for the capture
units and the QEP units.
Table 2.1: Configuration of eventmanager modules EVA and EVB
EVA EVB Event
Manager Modules Module Signal Module Signal
GP Timer 1 T1PWM/T1CMP GP Timer 3 T3PWM/T3CMP GP Timers
GP Timer 2 T2PWM/T2CMP GP Timer 4 T4PWM/T4CMP
Compare 1 PWM1/2 Compare 4 PWM7/8
Compare 2 PWM3/4 Compare 5 PWM9/10
Compare Units
Compare 3 PWM5/6 Compare 6 PWM11/12
Capture 1 CAP1 Capture 4 CAP4
Capture 2 CAP2 Capture 5 CAP5
Capture Units
Capture 3 CAP3 Capture 6 CAP6
QEP1 QEP1 QEP3 QEP3
QEP2 QEP2 QEP4 QEP4
QEP channels
QEPI1 CAP3 QEPI2 CAP6
Direction TDIRA Direction TDIRB External Clock
Inputs External Clock TCLKINA External Clock TCLKINB
Each GP timer has four modes of operation: (1) stop/hold mode, (2) continuous
upcounting mode, (3) directional up/down counting mode, and (4) continuous up/down
counting mode. The mode of operation is determined by the bit pattern in the timer
control register TxCON. In the stop/hold mode, the GP timer stops and holds at its
current value. In the continuous upcounting mode, the GP timer counts up according to
23
the scaled input clock until the value of the timer counter reaches the period register’s
value. On the next rising edge of the clock, the GP timer resets to zero and starts to count
again. The continuous up counting mode is very useful for the generation of edge
triggered or asymmetric PWM signals or a sampling period in a digital control system. In
the directional up/down counting mode, the GP timer counts up or down according to the
TDIRA/B input pin. When the TDIRA/B is held high, the GP timer counts up from zero
to the period register’s value, then resets to zero and continues to count up. On the other
hand, when the TDIRA/B input is low, the GP timer counts down from the period
register’s value to zero, then it reloads the period’s register value and continues to count
down. The continuous up/down counting mode is the same as the directional up/down
counting mode, but the TDIRA/B pin has no effect on the counting direction. The
counting direction only changes from up to down when the timer reaches the period
value, and only changes from down to up when the timer reaches zero. To generate an
asymmetric PWM signal, the GP timer needs to operate in continuous upcounting
modes. And, to generate a symmetric PWM signal, the GP timer should be in the
continuous up/down counting modes.
When the value of the GP timer matches that of the compare register, the output
of the GP timer toggles. For the continuous upcounting mode, the length of the active
phase (the output pulse width) is represented by [(TxPR)  (TxCMPR) + 1] cycles of the
scaled input clock.
2.2.5 Interrupts
The C28x CPU supports 32 CPU interrupt vectors [38, 39]. Each vector is a 22bit
address that is the starting address for the associated interrupt service routine (ISR).
24
Maskable interrupts include INT1INT14, DLOGINT and ROTSINT. INT1INT14 are
14 generalpurpose interrupts. Nonmaskable interrupts include software interrupts (INTR
and TRAP instructions), hardware interrupt NMI , illegalinstruction trap and hardware
reset interrupt RS .
The maskable interrupts are supported by three dedicated registers: the interrupt
flag register (IFR), the interrupt enable register (IER), and the debug interrupt enable
register (DBGIER). The 16bit IFR contains flag bits that indicate which of the
corresponding interrupts are pending. The IER and DBGIER registers each contain bits to
individually enable or disable a maskable interrupt. An interrupt can be enabled by
setting the corresponding bit to 1. All maskable interrupts can be globally enabled by
clearing the INTM bit, or globally disabled by setting it.
Since the CPU does not have enough capability to respond to all peripheral
requests at the CPU level, a centralized peripheral interrupt expansion (PIE) controller is
used to arbitrate the interrupt requests from different resources such as peripherals and
other external pins. Eight PIE interrupts are grouped into one CPU interrupt. The PIE
block can support 96 individual interrupts that are grouped into blocks of eight. Each
group is fed into one of 12 interrupt lines (INT1 to INT12). For multiplexed interrupt
sources, each interrupt group in the PIE block has an associated flag bit (PIEIFRx.y) and
enable bit (PIEIERx.y). In addition, there is an acknowledge bit (PIEACK) for every PIE
interrupt group INT1INT12.
The flowchart for the CPU to process maskable interrupts is shown in Figure 2.5.
When an interrupt request is sent to the CPU, the CPU level interrupt flag register IFR bit
corresponding to INTx is set. The CPU then checks if the interrupt is enabled in the CPU
25
interrupt enable register IER and the global interrupt mask INTM bit. The CPU then
prepares to service the interrupt. In preparation, the corresponding CPU IFR and IER bits
are cleared, EALLOW and LOOP are cleared, INTM and DBGM are set, the pipeline is
flushed, the return address is stored, and the automatic context save is performed. The
CPU is then loaded with the fetched interrupt vector, and the interrupt service routine is
executed.
2.2.6 Code Development Tool
The TMS320C2000 Code Composer Studio (CCS) is a Windowsbased integrated
development environment (IDE). The CCStudio IDE includes software tools for project
managing and editing, code generation, debugging, code optimization, real time kernel
and analysis. The flowchart to develop code on the CCStudion IDE is shown in Figure
2.6.
A new project needs to be created first. The project type can be selected to be
Executable (.out) or Library (.lib). Executable indicates that the project generates an
executable file, while library means that an object library will be built. After creating a
new project, the files of the source code, object libraries and linker command files are
added to the project list. Header files do not need to be added independently. They will be
automatically added when the source code is scanned for dependencies. The source files
can be edited, built and run on the CCStudio IDE.
The code generation tools include an optimizing C/C++ compiler, an assembler, a
linker and utilities. The optimizing C/C++ compiler translates C/C++ program into
TMS320 assembly source code [41]. The compiler tool includes an optimization tool that
reduces the size of the C/C++ program and reduces the execution speed.
26
Interrupt request sent to CPU
Set corresponding IFR flag bit
Interrupt Enabled in
IER?
Interrupt Enabled by
INTM bit ?
Clear corresponding IFR bit
Empty pipeline
Increment and temporarily
store PC
Fetch interrupt vector
Increment SP by 1
Perform automatic context
save
Clear corresponding IER bit
Set INTM and DBGM . Clear
LOOP, EALLOW, and
IDLESTAT
Load PC with fetched vector
Execute interrupt service
routine
Program continues
No
No
Yes
Yes
Figure 2.5 Flowchart of the operation for CPU maskable interrupts
27
Design conceptual
planning
Code & build
Create project,
Write source code,
Configuration file
Debug
Syntax Checking
Probe points,
logging, etc.
Analyze
Realtime debugging
Statistics, tracing
Figure 2.6 Flow chart for code development in CCStudio IDE
The optimization tool performs such tasks as simplifying loops, reagrranging
statements and expressions and allocating variables into registers. The operation of
optimization includes costbased register allocation, alias disambiguation, data flow
optimization, expression simplification, inline expansion of runtime support library,
induction variable optimizations and strength reduction, loopinvariant code motion, loop
rotation and register tracking and targeting. The optimization can be chosen to perform
on the file level or the program level. Optimization on the file level only optimizes a
single file. With program level optimization, all the source files are compiled into a
28
module file. The compiler uses the module file to optimize the entire program. Several
optimizations are only applied in the program level; for example, if a return value of a
function is never used, the compiler removes the return code in the function. And, if a
function is not called directly or indirectly, the compiler deletes the function.
29
CHAPTER 3
LINEAR CONTROL DESIGN FOR DCDC CONVERTERS
Presented in this chapter is the control design for DCDC converters using linear
control methods. An accurate model is essential to design linear controllers. Small signal
models for buck and boost converters were obtained using the standard statespace
averaging techniques. The actual frequency response was also measured to compare with
the small signal model. For the buck converter, the actual frequency response matches the
small signal model, while for the boost converter, there was a clear discrepancy between
them. Therefore, for the buck converter, the control design was based on the small signal
model, and for the boost converter, the measured frequency response was used for
controller design.
Frequency response and root locus methods [44] may be utilized to design linear
controllers. In the frequency response method, analog PID and PI controllers were
designed based on the converters’ small signal models [43]. The system was
compensated to achieve high loop gain, wide bandwidth and sufficient phase margin. The
PID and PI controllers were then transformed into digital controllers using the backward
integration method.
Statespace averaged models for DCDC converters are described in the first
section of this chapter. Control design using frequency response techniques is presented
30
in the second section. In the third section of this chapter, implementation of digital PID
and PI controllers is presented.
3.1 StateSpace Averaged Model for DCDC Converters
Linear controllers for DCDC converters are often designed based on
mathematical models. To obtain a certain performance objective, an accurate model is
essential. A number of AC equivalent circuit modeling techniques have appeared in the
literature, including circuit averaging, averaged switch modeling, the current injected
approach, and the statespace averaging method. Among these methods, the statespace
averaged modeling is most widely used to model DCDC converters.
The statespace averaged model of DCDC converters uses inductor current and
capacitor voltage as two independent state variables. It is a canonical form of writing the
differential equations to describe DCDC converters. This method combines the
advantage of both statespace and averaging methods. It provides an accurate small signal
model at relatively lower frequencies. It is assumed that the output filter’s cutoff
frequency is much lower than the switching frequency.
The procedure to obtain a statespace averaged model is described as follows.
First, the linear equivalent circuit for each state or switch position of the converter is
drawn. In the continuous conduction mode, there are two states; while in discontinuous
conduction mode, there are three states. Second, the circuit equations for each equivalent
circuit are derived. Third, each set of equations is averaged by using the duty cycle of the
switch as a weighting factor. The sets of equations are combined into a single set by
summation. Fourth, the average equation is perturbed to produce DC and small signal
terms. Nonlinear cross product terms are eliminated. Fifth, the small signal terms from
31
step 4 are transformed into the complex frequency domain. Thus, the statespace
averaged model of DCDC converters is obtained.
3.1.1 Buck Converters
The buck converter’s small signal controltooutput transfer function, derived by
the standard statespace averaging technique, is given by (3.1).
 
2
( ) 1
ˆ
( )
1 //
ˆo o C
C
C L
L L
s V sR C
L R R D
d s
s R C R R C s LC
R R R R
v
+
 
=

+
    \ .
+ + + +
 
+ +
\ . \ .
(3.1)
The small signal inputtooutput transfer function is given by (3.2):
 
2
( ) 1
( )
1 //
ˆ
ˆ
o C
C in L
C L
L L
s DR sR C
L R R s R R
s R C R R C s LC
R R R R
v
v
+
=
+ +    
+ + + +
 
+ +
\ . \ .
(3.2)
In the transfer functions, Vin and Vo are the input and output voltages
respectively.
ˆ ˆ ( ), ( )
o in
v s v s
and ) (
ˆ
s d are the small variations of the output voltage, input
voltage and duty cycle, respectively. D is the duty cycle, C is the output capacitance, L is
the inductance, and R is the load resistance. R
C
and R
L
are the ESR of C and L, where
these components can be found in Figures 2.1 and 2.2.
The controltooutput transfer function is utilized to design the controller. It is a
common twopole low pass filter, with a left half plane zero introduced by the ESR of the
filter capacitance [3]. The cutoff frequency of the low pass filter is ω
c
=
LC
1
. The
magnitude falls with a slope of –40 dB/decade at the cutoff frequency. The phase
32
associated with it is a –180 degree phase delay. The zero is at
C R
C
1
− . There is a
20 dB/decade magnitude rise at that frequency and the phase shift is 90 degrees. The
magnitude of the transfer function depends on the duty cycle D. When D increases, the
magnitude decreases; when D decreases, the magnitude increases. However, variations of
D don’t change the shape of the magnitude plot of the transfer function. It only shifts the
magnitude upward or downward.
The buck converter’s nominal operating point is as follows: Vin = 20 V, Vo = 12
V, and D = 0.6. The capacitance C is 1000 µF, L is 150 µH, and R is 10 Ω. The parasitic
elements RC and RL are estimated to be 30 mΩ and 10 mΩ, respectively [18, 19]. This
buck converter was used as a prototype buck converter in this dissertation. The control
tooutput transfer function at the nominal operating point is given by (3.3):
4
7 2 5
( ) 6*10 s+20
ˆ
1.503*10 s +5.4975*10 s+1
( )
ˆo s
d s
v
= (3.3)
The Bode plot of the transfer function is shown in Figure 3.1. The model has complex
conjugate poles at –615.9 ± j2481.5, which causes a 180 degrees phase delay at the
approximate frequency of 2500 radians/s. The model also has a zero at 33,333 radians/s.
Frequency response data for the prototype buck converter was measured using a Model
102B analog network analyzer by AP Instruments. Figure 3.2 shows the frequency
response of the buck converter near the nominal operating point. It compares favorably
with the theoretical model; thus linear controllers can be designed based on the
theoretical model.
33
10
2
10
3
10
4
10
5
10
6
50
30
10
10
30
50
Frequency (rad/sec)
G
a
i
n
d
B
10
2
10
3
10
4
10
5
10
6
200
150
100
50
0
Frequency (rad/sec)
P
h
a
s
e
d
e
g
D decreases
D increases
Two conjugate poles of the low pass filter
40dB/dec
20dB/dec
zero introduced by ESR
Figure 3.1 Bode plot of the statespace averaged model of the buck converter
10
2
10
3
10
4
10
5
60
40
20
0
20
Frequency (rad/sec)
G
a
i
n
d
B
10
2
10
3
10
4
10
5
200
150
100
50
0
Frequency(rad/sec)
P
h
a
s
e
d
e
g
Figure 3.2 Frequency response of the buck converter obtained by the analog analyzer
34
3.1.2 Boost Converters
The outputtocontrol small signal transfer function of the boost converter is given
by (3.4):
C L CR L
D R D R
CR L
D R D R
s s
R R C sR
R
sL
C L D
V
s d
s v
e e
O C O L
e
O C O L
C C
e
e O
O o
1 ) / ( ) / ( 1 ) / ( ) / (
) 1 / )( 1 (
) (
ˆ
) ( ˆ
2 2
2
+
+
+
+
+
+
+ + −
=
(3.4)
where
2
/(1 ) Le L D = − , and D
o
= 1D. For the experiment, the input voltage Vin is 5 V,
the output voltage Vo is 12 V, and the duty cycle D is 63%. Capacitance C is 1056 µF,
inductance L is 250 µH, and load resistance R is 25 Ω. The parasitic elements RC and RL
are estimated from data sheets to be 30 mΩ and 10 mΩ, respectively.
The Bode plot of the boost converter’s transfer function is shown in Figure 3.3.
The transfer function is a common twopole low pass filter with two zeros. The low pass
filter’s cut off frequency is at ω
c
=
1D
LC
. The zero in the left half plane is
ω
zl
=
C R
R R
C
C
/ 1+
− , and the zero in the right half plane is ω
zr
=
2
(1 ) D R
L
−
. Variables ω
c
and
ω
zr
are functions of nominal duty cycle D. In a closedloopvoltagecontrol system, the
filter element will change as the duty cycle changes, which means the model will change
accordingly. This makes the transfer function a nonlinear function of the duty cycle [3]. It
makes the control design for the boost converter more challenging from the point of view
of stability and bandwidth. The zero in the right half plane is caused by switching action,
and it introduces a 90 degree phase delay in the plant [3]. The physical phenomenon of
the RHP zero is that when there is a step increase in duty cycle, the initial slope of the
output voltage (dvo/dt) is negative, which means that the output voltage will drop
35
instantaneously. The RHP zero seriously complicates the problem of stabilizing the
control loop [3]. Special attention is required when designing the compensator for the
system to have adequate gain and phase margins.
Similar to the buck converter, the frequency response of the boost converter
prototype when operating in steady state is also obtained using the analog network
analyzer. Figure 3.4 shows the frequency response obtained compared to the Bode plot of
the theoretical transfer function. There are clear discrepancies between them. The zeros
of the theoretical model are 3.6801×10
4
radians/s and 3.1604×10
4
radians/s, and the
poles are (0.1324± j1.1769)×10
2
radians/s. Part of the discrepancy is because there is
more damping in the actual plant than in the theoretical model. A transfer function for the
boost converter is generated by fitting the experimental frequency response data using
Matlab. The experimental frequency response and this transfer function are plotted in
Figure 3.5. Note that there is good agreement between the two curves. The generated
transfer function is given in (3.5):
3 2 2 6
2 2 5
( ) 5.6956*10 s  2.5589*10 s + 4.9831*10
ˆ
s + 8.2525*10 s + 5.4241*10
( )
ˆo s
d s
v
= (3.5)
The transfer function in (3.5) has two zeros at 5.961×10
4
radians/s and 1.468×10
4
radians/s, and two complex conjugate poles are (4.126 ± j6.1)×10
2
radians/s. The control
design will be based on the actual frequency response determined by the analog network
analyzer.
36
10
1
10
2
10
3
10
4
10
5
10
6
10
7
40
20
0
20
40
Frequency (rad/sec)
G
a
i
n
d
B
10
1
10
2
10
3
10
4
10
5
10
6
10
7
200
150
100
50
0
Frequency (rad/sec)
P
h
a
s
e
d
e
g
Two conjugate poles of the low pass filter
Zero in LHP Zero in RHP
180 degrees phase shift caused by the conjugate poles
D increases
D decreases
40dB/dec
D increases D decreases
D decreases D increases
90 degree phase shift by LHP zero
90 degree phase delay by RHP zero
20dB/dec
Figure 3.3 Bode plot of the statespace averaged model of the boost converter
10
2
10
3
10
4
10
5
50
30
10
10
30
50
Frequency (rad/sec)
G
a
i
n
d
B
Actual frequency response
Theoretical frequency response
10
2
10
3
10
4
10
5
250
200
150
100
50
0
Frequency (rad/sec)
P
h
a
s
e
d
e
g
Figure 3.4 Comparison of the actual and theoretical frequency response of the boost
converter
37
10
1
10
2
10
3
10
4
10
5
60
40
20
0
20
40
Frequency (rad/sec)
G
a
i
n
d
B
Frequency Response
of the Actual Model
Bode Plot of the Transfer
Function Generated
10
1
10
2
10
3
10
4
10
5
400
300
200
100
0
Frequency (rad/sec)
P
h
a
s
e
d
e
g
Figure 3.5 Comparison of the frequency response obtained using the analog analyzer and
from the generated transfer function
3.2 Digital Controller Design for DCDC Converters Using Frequency Response
Techniques
In DCDC converters, the output voltage is a function of the input line voltage,
the duty cycle and the load current. It is desirable to have a constant output voltage in the
event of disturbances such as a sudden change of input voltage or load current. Negative
feedback control is applied to DCDC converters to automatically adjust the duty cycle to
obtain the desired output voltage with high accuracy in spite of disturbance [9].
In this section, frequency response techniques are used to design digital
controllers for DCDC converters. The compensated system is expected to have the
following characteristics [45]. Firstly, the loop gain should be high at lower frequencies
to minimize steadystate error and increase rejection to disturbances of input voltage and
load current variations. Secondly, the crossover frequency should be as high as possible,
38
but about an order of magnitude below the switching frequency to allow the DCDC
converter to respond quickly to the transients. Thirdly, the phase margin should be
sufficient to ensure the system’s stability. When the phase margin of the loop gain is
positive, the system is stable. A phase margin of 45
o
to 60
o
is desirable.
Phase margin determines the transient response of the DCDC converter. An
increase of the phase margin makes the system more stable with less ringing and
oscillation. There is a qualitative relationship between the phase margin and the closed
loop damping factor Q. To obtain Q = 1, a phase margin of 52
o
is required, and to obtain
Q = 0.5, a phase margin of at least 76
o
is needed. The damping factor Q determines the
shape of the transient response. When Q is equal to 0.5, the closedloop system has two
real poles at the same frequency, and the system is critically damped. The transient
response will be fast without overshoot. When Q is larger than 0.5, there are two complex
conjugate poles, and the system is underdamped. The transient response will have an
oscillatorytype waveform with decaying magnitude. The higher Q, the higher overshoot
the transient response will have. When Q is less than 0.5, the closedloop system has two
real poles at two different frequencies, and the system is overdamped. The transient
response is a decaying exponential function of time with the time constant determined by
the pole at the lower frequency. When Q is very low, the lowfrequency pole results in a
slow transient response.
To design a controller using the frequency response method, phaselead, phase
lag or leadlag compensation is usually used. A proportionalderivative (PD) controller is
phaselead compensation. PD controllers are used to increase the phase margin and
improve the crossover frequency. A zero is placed at frequency ω
Z
far below the cross
39
over frequency to improve the phase margin. The transfer function of a PD controller is
shown in (3.6).
) 1 (
) 1 (
) (
P
z
C C
s
s
K s G
ω
ω
+
+
= (3.6)
The pole at ω
P
is placed well below the switching frequency to avoid amplification of the
switching noise. The maximum phase shift occurs at the geometric mean of the pole ω
P
and the zero ω
Z.
To obtain maximum phase margin improvement, the maximum phase
shift should be placed at the crossover frequency.
A proportionalintegral (PI) controller is a phaselag controller. A PI controller is
used to increase the low frequency loop gain, thus reducing steadystate error. The
transfer function of a PI controller is shown in (3.7).
s
K s K
s
K
K s G
I P I
P C
+
= + = ) ( (3.7)
The PI controller has a pole at the origin. Both PD and PI controllers are firstorder
controllers.
By using a leadlag compensator, the advantages of lead compensation and lag
compensation can be combined to obtain sufficient phase margin, high loop gain and
wide control bandwidth. A proportionalintegralderivative (PID) controller is a leadlag
compensator. It is the most widely used compensator in feedback control systems. The
PID controller is defined by (3.8), where e(t) is the compensator input and m(t) is the
compensator output.
0
( )
( ) ( ) ( )
t
P I D
de t
m t K e t K e d K
dt
τ τ = + +
∫
(3.8)
40
The Laplace transform of (3.8) yields the transfer function in (3.9).
s K
s
K
K
s E
s M
s G
D
I
P C
+ + = =
) (
) (
) ( (3.9)
The integral term is phaselag and the derivative term is phaselead. The low frequency
gain is improved by the integral term, and the lowfrequency components of the output
voltage are accurately regulated. At high frequency, the phase margin and crossover
frequency are improved by the derivative term, which improves the system’s stability and
the speed of the transient response. An increase in the proportional term will increase the
speed of system response; however, too much proportional gain will make the system
unstable.
A PID controller and a PI controller were designed for both the buck converter
and the boost converter in the following sections.
3.2.1 Buck Converters
A PID and a PI controller were designed for the buck converter for operation
during a startup transient and steady state, respectively. The derivative term in a PID
controller is susceptible to noise and measurement error of the system, which could result
in oscillation of the duty cycle during steady state. However, during a transient, the
derivative term is needed to reduce the settling time by predicting the changes in error.
Therefore, the system switches between PID and PI controllers during transient and
steady state to obtain the desired response. The PID controller is applied during start up
to obtain a fast transient response. The PI controller is applied during steady state to
reduce oscillation of the duty cycle and improve the system’s stability.
41
3.2.1.1 PID Controller Design for Buck Converters
A PID controller was designed for the buck converter to improve the loop gain,
crossover frequency and phase margin. One zero was placed an octave below the cutoff
frequency (approximately 260 radians/s) and the other one at 4600 radians/s. The transfer
function of the PID controller is given by (3.10):
s
s
s G
c
000119 . 0
4 . 142
5786 . 0 ) ( + + = (3.10)
The Bode plot for the compensated system is shown in Figure 3.6. As can be seen in this
plot, the gain at low frequency is high, the phase margin is 107 degrees and the bandwidth
is 19100 radians/s.
Figure 3.6 Bode plot of PID controller compensated buck converter
42
3.2.1.2 PI Controller Design for Buck Converters
A PI controller was also designed for the control of the buck converter at steady
state to reduce steadystate oscillation. One pole was placed at the origin, and one zero
was placed at 800 radians/s. The DC gain of the controller was adjusted to obtain
sufficient phase margin and high crossover frequency. The transfer function of the PI
controller is given by (3.11):
s
s G
c
600
75 . 0 ) ( + = (3.11)
The Bode plot for the PI compensated system is shown in Figure 3.7. The Bode
plot shows that the phase margin is 15.4 degrees and the bandwidth is 10600 radians/s.
Figure 3.7 Bode plot of PI controller compensated buck converter
43
3.2.2 Boost Converters
A PID and a PI controller were designed for the boost converter for operation
during a startup transient and steady state, respectively. The controllers were designed
based on the measured small signal model of the boost converter using frequency
response techniques.
3.2.2.1 PID Controller Design for Boost Converters
For the PID controller, one zero was placed at 260 radians/s, and the other zero is
placed at 2600 radians/s. The transfer function of the PID controller is shown in (3.12).
s
s
s G
c
000198 . 0
13 . 134
567 . 0 ) ( + + = (3.12)
The bode plot of the PID compensated boost converter is shown in Figure. 3.8.
Figure 3.8 Bode plot of PID controller compensated boost converter
44
The bandwidth of the PIDcompensated system is 1.83×10
3
radians/s, and the phase
margin is 50 degrees.
3.2.2.2 PI Controller Design for Boost Converters
A PI controller was designed for the steady state to reduce oscillations of the duty
cycle. A pole was placed at the origin and a zero was placed at 600 radians/s. The Bode
plot of the PIcontrollercompensated system is shown in Figure. 3.9. The bandwidth of
the PI compensated system is 1010 radians/s, and the phase margin is 26.3 degrees.
Figure 3.9 Bode plot of PI controller compensated boost converter
3.2.3 Transformation from an Analog Controller to a Digital Controller
The design in the continuoustime domain was transformed into the discretetime
domain using the backward integration method (Euler Method) [45, 46]. Using the Euler
method, the transfer function of a numerical integrator is shown in (3.13).
45
) (
1
) ( z E
z
Tz
z M
−
= (3.13)
The transfer function of a numerical differentiator is the reciprocal of the transfer
function of the numerical integrator shown in (3.13). Therefore, by substituting (3.13)
and its reciprocal into the PID controller’s sdomain transfer function in (3.9), the digital
PID controller’s transfer function is shown in (3.14).
Tz
z K
z
Tz K
K z G
D I
P C
) 1 (
1
) (
−
+
−
+ = (3.14)
Similarly, by substituting (3.13) and its reciprocal into the PI controller’s sdomain
transfer function in (3.7), the digital PI controller’s transfer function is shown in (3.15).
1
) (
−
+ =
z
Tz K
K z G
I
P C
(3.15)
3.3 Implementation of Digital Controllers
Digital controllers were implemented on the eZdsp F2812 from Texas
Instruments. The eZdsp F2812 was introduced in Chapter 2. The eZdsp F2812 is a stand
alone evaluation module. This module features a TMS320F2812 Digital Signal Processor
(DSP) with 150 MIPS operating speed. The DSP has a fixed point 32bit CPU, 128K on
chip flash memory and a dual 12bit, 16 channel ADC. The conversion rate of the ADC is
80 ns. The sampling and the switching frequency of the controllers implemented on the
TMS320F2812 DSP was 150 kHz. The faster clock frequency and ADC conversion time
of the F2812 DSP allow a faster sampling and switching frequency. The one switching
period delay between sampling the converter’s output voltage and updating the duty cycle
is modeled by the function e
Ts
, where T is the switching period of the DCDC converter.
When the switching frequency is 150 kHz, T = 6.67 µs.
46
3.3.1 Program Structure
The overall program structure is shown in Figure 3.10. Once the program starts to
run, the first task was to initialize the DSP. Macros such as clearing bit, setting bit and
setting a certain amount of delay time were defined. The interrupt vector address mapped
the subroutines corresponding to each level of interrupts. The global variables were
declared and given initial values. The event manager module was initialized to define the
sampling and switching frequency, which was determined by the period of the general
purpose timers. Then certain bits were set to start the PWM. The analog to digital
conversion was set to be in the continuous conversion mode.
After the configuration of the DSP was complete, an interrupt was enabled to
allow the main algorithm to run. Each time when the value of the general purpose timer
equaled the timer’s period value, an interrupt was requested and directed to the
corresponding interrupt subroutine. The sampling period was equal to the period of the
general purpose timer.
The interrupt subroutine was executed every sampling period. The subroutine
acquired a sample once every sampling period, utilized a digital controller algorithm to
calculate a new duty cycle, and updated the new duty cycle at the start of the next
switching period. Different digital control algorithms, including PID and PI controllers
and fuzzy and sliding mode fuzzy controllers, were all implemented as interrupt
subroutines.
47
Power On
Run
Program Initialization
Macro Definition
Interrupt Vector Address Declarations
Initialize Local Variables
Configure CPU and System Clock
Clear Module Error Flags
Initialize RAM
Set Up Digital I / O Port
Set Up Event Manager Module
Set Up Interrupt Registers
Start PWM
Set ADC Into Continuous Conversion Mode
Enable Masked Interrupts
Interrupt Subroutine
Wait Until ADC Complete
Obtain ADC Value
Digital Control Algorithm
Update PWM
Return to Main Program
Interrupt Condition
Met?
Yes
No
Figure 3.10 Overview of the program structure for digital controllers
48
3.3.2 Implementation of Digital PID and PI Controllers
In Section 3.2, PID and PI controllers were first designed using the frequency
response techniques based on the small signal models of the DCDC converters, then
transformed into digital controllers using the backward integration method. The zdomain
transfer function of a digital PID controller is shown in (3.14), and the zdomain transfer
function of a digital PI controller is shown in (3.15).
The difference equation to calculate a new duty cycle for the digital PID
controller is written in (3.16).
∑
=
− − + + =
k
i
D
I P
k e k e
T
K
i e T K k e K k u
0
]} 1 [ ] [ { ] [ ] [ ] [ (3.16)
And the difference equation to calculate a new duty cycle for the digital PI controller is
given in (3.17).
∑
=
+ =
k
i
I P
i e T K k e K k u
0
] [ ] [ ] [ (3.17)
In the difference equation, u[k] is the controller output for the kth
sample, and e[k]
is the error of the kth
sample. The error e[k] is calculated as e[k] = RefADC[k], where
ADC[k] is the converted digital value of the kth
sample of the output voltage, and Ref is
the digital value corresponding to the desired output voltage.
∑
=
k
i
i e
0
] [ is the sum of the
errors and {e[k]e[k1]} is the difference between the error of the kth
sample and the error
of the (k1)th
sample. The block diagram for the difference equation (3.16) is shown in
Figure 3.11. It is noted that when K
D
is equal to zero, the PID algorithm changes into a PI
algorithm.
49
Proportional Gain
Integral Gain
Derivative Gain
Control l er Output
e(k1)
e(k)
ADC(k)
Ref
Kp
kiT
kd/T
1/z
1/z
u
Figure 3.11 Block diagram of digital PID controller
The flowchart for the digital PID and PI controller is shown in Figure 3.12. At the
start of each sampling period, there was a 2 µs delay before taking the analog to digital
conversion. Because the sampling and PWM switching frequency were the same and
their periods were synchronous, the start of the sampling and switching periods happened
at the same time. The switching action of the MOSFET in the DCDC converter produces
a glitch in the converter output voltage which can be measured by the A/D converter.
Measurement of this glitch will produce oscillation in the duty cycle calculated by the
digital PID controller. The sample was taken after the start of the switching period
instead to avoid sampling the switching glitches.
When both the absolute value of the error of the kth sample e[k] was less than ε,
and the absolute value of the difference between the error of the kth sample and the error
of the (k1)th sample de[k] was less than φ, the converter was considered to be operating
in steady state. The values ε and φ can be determined based on experimental results of the
converters. The PI controller was applied in steady state to reduce oscillation of the duty
50
cycle. The gain of the integrator K
D
was assigned to be zero, and the proportional and
integral gains K
P
and K
I
were assigned according to the design of the PI controller. The
result of the PID controller was a sum of the proportional, derivative and integral
controllers.
The duty cycle of the PWM signal in the digital control system for the buck
converter was limited between 10% and 90%. This prevents the MOSFET from being
turned on or off for a full switching period. In the digital control system for the boost
converter, the duty cycle was further limited to be between 20% and 80%, since the
digital controller for the boost converter tends to oscillate more than the digital controller
for the buck converter. After updating the new duty cycle, and the error of the (k1)th
sample, the interrupt subroutine returned to the main program and waited for a request for
the next interrupt.
The difference equations in (3.16) and (3.17) are linear combinations of feedback
and control signals. A series of scalar multiplification and addition instructions can be
used to implement the linear PID and PI controllers on the TMS320F2812. In order to
compare the experimental results using different control methods, experimental results of
the buck and boost converters using digital PID and PI controllers will be presented in
Chapter 6.
51
e[k]=RefADC[k]
Yes
PID=K+I+P
PID>90%?
PID<10%?
PID=90%
PID=10%
Duty Cycle = PID
e[k1]=e[k]
Yes
No
No
Update Duty Cycle of PWM
Wait On Until Next Interrupt
Interrupt
Subroutine Ends
ADC Conversion
Complete
Delay 2 us
Interrupt
Subroutine Starts
Yes
de[k]=e[k]e[k1]
Assign values for PI controller gains Kp,
Ki. KD=0
Yes
Assign values for PID
controller gains KP, KI and KD
P=KP*e[k]
D=KD/T*de[k]
1
0 0
( ) ( ) ( )
k k
i i
e i e i e k
−
= =
= +
∑ ∑
? ] [ ε ≤ k e
? ] [ φ ≤ k de
∑
=
=
k
i
I
i e T K I
0
) (
No
No
Figure 3.12 Flowchart of digital PID and PI controller
52
CHAPTER 4
FUZZY CONTROLLER DESIGN FOR DCDC CONVERTERS
Linear controllers for DCDC converters are usually designed based on
mathematical models. To obtain a certain performance objective, an accurate model is
essential. In the previous chapter, linear controllers were designed for buck and boost
converters based on each converter’s small signal model using frequency response and
root locus design methods. The small signal model changes due to variations in operating
point. Changes in the duty cycle only affect the magnitude of the buck converter’s small
signal model. While for the boost converter’s small signal model, the poles and a right
half plane zero, as well as the magnitude of the frequency response, are all dependent on
the duty cycle D. This makes the transfer function of the boost converter’s small signal
model a nonlinear function of the duty cycle. The righthalf plane zero and the nonlinear
nature of the boost converter’s small signal model makes the control design for this
converter more challenging from the point of view of stability and bandwidth [3].
To achieve a stable and fast response, two solutions are possible. One is to develop
a more accurate model for the converter. However, the model may become too complex to
use in controller development. A second solution is to use a nonlinear controller [9]. Since
fuzzy controllers don’t require a precise mathematical model, they are well suited to
nonlinear, timevariant systems. The design of fuzzy controllers is presented in this
chapter. The first section introduces the concept of fuzzy control. The second section is
53
mainly focused on the design of a fuzzy controller for the buck and boost converters.
Implementation of fuzzy controllers is presented in the third section of this chapter.
4.1 Introduction to Fuzzy Control
Fuzzy control is an artificial intelligence technique that is widely used in control
systems. It provides a convenient method for constructing nonlinear controllers from
heuristic information.
Conventional controllers are designed based on a mathematical model. Closed
loop control specifications include disturbance rejection properties, insenstivity to plant
parameter variations, stability, rise time, overshoot and settling time and steadystate
error. Based on these specifications, conventional controllers are designed. Major
conventional control methods include classical control methods (frequency response and
root locus techniques), statespace methods, optimal control, robust control, adaptive
control, sliding mode control and other nonlinear control methods such as feedback
linearization and backstepping. These conventional control methods provide a variety of
ways to utilize information from mathematical models on how to obtain good control.
Different from conventional control, fuzzy control is based on the expert
knowledge of the system. Fuzzy control provides a formal methodology to represent and
implement a human’s heuristic knowledge about how to control the system. A block
diagram of a fuzzy control system is shown in Figure. 4.1. A fuzzy controller contains
four main components: (1) the fuzzification interface that converts its inputs into
information that the inference mechanism can use to activate and apply rules, (2) the rule
base which contains the expert’s linguistic description of how to achieve good control,
(3) the inference mechanism that evaluates which control rules are relevant in the current
54
situation, and (4) the defuzzification interface which converts the conclusion from the
inference mechanism into the control input to the plant [48].
Inference
Mechanism
Fuzzification Defuzzification
Rule Base
Fuzzy Controller
Reference
Input r(t)
Plant
Input u(t) Output y(t)
Figure 4.1 Block diagram of fuzzy control system
The performance objectives and design constraints are the same as those for
conventional control. Design of fuzzy controllers involves the following procedures: (1)
choose the fuzzy controller’s inputs and outputs, (2) choose the preprocessing for the
controller inputs and postprocessing for the controller outputs, and (3) design each of the
four components of the fuzzy controller shown in Figure 4.1.
4.2 Fuzzy Control Design for DCDC Converters
A fuzzy controller for a DCDC converter has two inputs. The first input is the
error in the output voltage e[k]=RefADC[k], where ADC[k] is the converted digital value
of the k
th
sample, and Ref is the digital value corresponding to the desired output voltage.
The second input, ce[k]=e[k]e[k1], is the difference between the error of the k
th
sample
and the error of the (k1)
th
sample. The two inputs are multiplied by the scaling factors g0
55
and g1, respectively, and then fed into the fuzzy controller. The output of the fuzzy
controller is the change in duty cycle δd[k]. It is scaled by a linear gain h. The scaling
factors g0, g1 and h can be tuned to obtain a satisfactory response.
There are two methods to calculate the new duty cycle from the fuzzy controller’s
output δd[k]. In the first method, the output of the fuzzy controller, scaled by the output
gain h, is added to the previous sampling period’s duty cycle d[k1], which is written in
(4.1).
d[k] = d[k1]+h*δd[k] (4.1)
The integration of the fuzzy controller’s output increases the system type and improves
steadystate error. The Simulink model of the fuzzy controller using (4.1) to calculate the
duty cycle d[k] is shown in Figure 4.2. The disadvantage of this method is that the output
gain h has to be tuned to be very small to avoid oscillation in steady state. Since the
change in duty cycle is accumulated every sampling period, the duty cycle varies around
its nominal value during steady state, which could lead to oscillation. Quantization errors
in digital controllers increase the magnitude of the oscillation, because digital controllers
are restricted to a finite set of values. Oscillation between the maximum and minimum
values of the duty cycle may even occur if h is relatively large compared to the duty cycle
range. A very small output gain h tends to increase the transient response time because
more sampling periods are necessary to arrive at the desired duty cycle [49].
A second method to calculate the new duty cycle is to add the output of the fuzzy
controller scaled by h to the output of a linear integrator, which is shown by (4.2),
d[k] = Ki*I[k]+h*δd[k] (4.2)
56
where I[k] is the output of the linear integrator of the error e[k], and K
I
is the gain of the
integrator. The linear integrator is applied to eliminate steadystate error. The Simulink
model of the fuzzy controller using (4.2) to generate the duty cycle d[k] is shown in
Figure 4.3. In this method, the output gain h can be increased because the fuzzy
controller’s output is not accumulated every sampling period.
In order to prevent the MOSFET from being turned on or off for a full switching
period, the duty cycle d[k] is limited to be between 10% and 90% for the buck converter,
and further limited to be between 20% and 80% for the boost converter. From the
literature, the first method in Figure 4.2 is more prevalently used than the second method
in Figure 4.3 [9, 10]. In this dissertation, only the second method was applied to the buck
converter to obtain satisfactory response, while for the boost converter, a combination of
both methods was applied to get the desired response.
Figure 4.2 Simulink model of the fuzzy controller for the DCDC converters Method 1:
(d[k] = d[k1]+h*δd[k].)
57
Figure 4.3 Simulink model of the fuzzy controller with a linear integrator for the
DCDC converters Method 2:(d[k] = K
I
*I[k]+h*δd[k])
4.2.1 Fuzzification
First, the linguistic values are quantified using membership functions. Each
universe of discourse is divided into fuzzy subsets. There were 17 fuzzy subsets in the
fuzzy controller for the buck converter: N8, N7, N6, N5, N4, N3, N2, N1, Z, P1, P2, P3,
P4, P5, P6, P7 and P8, where N indicates negative, Z represents zero, and P indicates
positive. The membership functions for e[k] and ce[k] are shown in Figure 4.4. The
variables µ
e
(e[k]) and µ
ce
(ce[k]) are the membership degrees assigned to each fuzzy subset
to quantify the certainty that the input can be classified linguistically into the
corresponding fuzzy subsets. A triangleshaped membership function was used for this
controller design for the ease of implementation. Of the 17 subsets, there were 8 subsets
for the positive parts and 8 subsets for the negative parts of the universe of discourse,
respectively. For the purpose of implementation, the computation time and code size of
the fuzzy controller can be reduced when the number of subsets for the positive and
negative parts is a power of 2, because shift instructions can be used to calculate the
membership degrees instead of division functions.
58
For the boost converter, each universe of discourse was divided into 33 fuzzy
subsets: N16, N15, N14, …, N1, Z, P1, …, P14, P15, P16. The membership functions for
e[k] and ce[k] for the boost converter are shown in Figure 4.5. There were 16 fuzzy
subsets for the negative parts and 16 fuzzy subsets for the positive parts of the universe of
discourse in order to reduce the computation time. The number of fuzzy subsets was
determined based on the experimental results of buck and boost converters. 17 fuzzy
subsets for the buck converter and 33 fuzzy subsets for the boost converter were the
smallest number of fuzzy subsets in order to obtain satisfactory results.
Figure 4.4 Membership functions of the inputs e[k] and ce[k] for the buck converter
Figure 4.5 Membership functions of the inputs e[k] and ce[k] for the boost converter
59
4.2.2 Rule Base
The rule base is derived from general knowledge of DCDC converters, and
adjusted based on experimental results. There is a tradeoff between the size of the rule
base and the performance of the controller. A 7*7 rule base was also designed and
implemented for the buck converter. Experimental results indicate that the fuzzy controller
with a 17*17 rule base exhibited less oscillation during steady state, and faster transient
response was achieved by increasing the output gain h. For the same universe of
discourse, more membership functions resulted in finer control. The output of the
controller had less variation when either of the inputs had small changes, and a more
accurate control was achieved; chattering and oscillation were reduced [48].
The nonlinear property of the boost converter’s small signal model and its right
half plane zero makes the controller design for the boost converter more difficult than for
the buck converter. From laboratory experiments, oscillation occured in steady state when
a 17*17 rule base was used for the boost converter. Therefore, a larger rule base than the
buck converter was derived for the boost converter in order to obtain fast transient
response and reduce steadystate oscillations. There were 33*33 rules in the rule base for
the boost converter.
4.2.3 Inference Mechanism
The results of the inference mechanism include the weighing factor w
i
and the
change in duty cycle c
i
of the individual rule [4]. The weighing factor w
i
is obtained by
Mamdani’s min fuzzy implication of µ
e
(e[k]) and µ
ce
(ce[k]), where w
i
= min{µ
e
(e[k]),
µ
ce
(ce[k])} and µ
e
(e[k]), µ
ce
(ce[k]) are the membership degrees [10]. c
i
is taken from the
rule table. The change in duty cycle inferred by the i
th
rule, z
i
is written in (4.3).
60
i ce e i i i
c k ce k e c w z × = × = ])} [ ( ]), [ ( min{ u u
(4.3)
4.2.4 Defuzzification
The center of average method is used to obtain the fuzzy controller’s output δd[k],
which is given in (4.4). When using triangleshaped membership functions, there are at
most four rules that are effective at any one time; therefore, N=4.
 
∑
∑
=
=
×
=
N
i
i
N
i
i i
w
c w
k d
1
1
δ
(4.4)
4.3 Implementation of Fuzzy Controllers
Implementation of fuzzy controllers on the DSP had quite different issues from
implementation of linear controllers. The implementation of linear controllers usually
involves difference equations, which are linear combination of feedback and control
signals. A series of scalar multiplication and addition instructions can be used to
implement a linear digital controller. DSPs are usually optimized for such operations. The
TI TMS320F2812 DSP has several instructions to multiply a number by a constant and
add a previous product in a single instruction. Therefore, the implementation of the linear
controllers in real time was quite straightforward.
The flowcharts of the fuzzy controllers are shown in Figure 4.6 and Figure 4.7.
Figure 4.6 shows the flowchart of the fuzzy controller using the first method to calculate
the new duty cycle, which corresponds to the Simulink model in Figure 4.2. Figure 4.7
shows the flowchart of the fuzzy controller with a linear integrator, which corresponds to
the Simulink model in Figure 4.3.
61
e[k]=RefADC[k]
d[k]>90%?
d[k]<10%?
d[k]=90%
d[k]=10%
e[k1]=e[k]
Yes
No
No
Update Duty Cycle of PWM
Wait On Until Next Interrupt
Interrupt Subroutine Ends
ADC Conversion
Complete
Delay 2 us
Interrupt Subroutine Starts
Yes
ce[k]=e[k]e[k1]
e[k]=g0*e[k]
ce[k]=g1*de[k]
Calculate centers and membership
degrees µ
e
(e[k]) for e[k]
Calculate centers and membership
degrees µ
ce
(ce[k]) for ce[k]
d[k1]=d[k]
])} [ ( ]), [ ( min{ k ce k e w
ce e i
u u =
∑
∑
=
=
×
=
4
1
4
1
] [
i
i
i
i i
w
c w
k d δ
] [ ] 1 [ ] [ k d h k d k d δ × + − =
Figure 4.6 Flowchart of fuzzy controller using method 1
62
e[k]=RefADC[k]
d[k]>90%?
d[k]<10%?
d[k]=90%
d[k]=10%
e[k1]=e[k]
Yes
No
No
Update Duty Cycle of PWM
Wait On Until Next Interrupt
Interrupt Subroutine Ends
ADC Conversion
Complete
Delay 2 us
Interrupt Subroutine Starts
Yes
ce[k]=e[k]e[k1]
e[k]=g0*e[k]
ce[k]=g1*de[k]
Calculate centers and membership
degrees µ
e
(e[k]) for e[k]
Calculate centers and membership
degrees µ
ce
(ce[k]) for ce[k]
d[k1]=d[k]
∑ ∑
=
−
=
+ = =
k
i
k
i
k e i e i e k I
0
1
0
] [ ] [ ] [ ] [
])} [ ( ]), [ ( min{ k ce k e w
ce e i
u u =
∑
∑
=
=
×
=
4
1
4
1
] [
i
i
i
i i
w
c w
k d δ
] [ ] [ ] [ k d h k I K k d
I
δ × + × =
Figure 4.7 Flowchart of fuzzy controller with a linear integrator
63
A fuzzy controller is a nonlinear algorithm. It requires frequent use of
multiplication and division instructions with high accuracy. Most DSPs are not optimized
for nonlinear algorithms. There were unique challenges to implement a fuzzy controller
on a DSP.
When implementing a fuzzy controller in real time, two main issues are the
amount of time it takes to compute the output of fuzzy controllers, and the amount of
memory used. In each sampling period of the controller computations, centers in the
membership function and their corresponding membership degrees need to be calculated.
When there are many inputs to the fuzzy controller or each input has many membership
functions, the efficiency of the implementation of fuzzy controllers becomes even more
important. The reason is that the number of rules increases exponentially with the
increase of the number of inputs. For the fuzzy controller designed for the boost
converter, there were two inputs, and each input had 33 membership functions.
Therefore, there were totally 33
2
=1089 rules. In real time, it was prohibitive to calculate
the 1089 membership degrees and to sum up 1089 values in the numerator and
denominator in equation (4.4). The sampling frequency of the fuzzy controller would
have to be quite low because of the long computation time.
Triangleshaped membership functions were used to solve this problem. For
triangleshaped membership functions, there are at most four rules that are effective at
any time. Therefore, only four centers and four membership degrees need to be calculated
instead of going through all the rules in the rule base. The reduction of the computation
time is significant especially when the rule base is large. It is much more efficient to
calculate only four centers and corresponding membership degrees rather than 1089.
64
Of the 33 subsets, there were 16 subsets for the positive and negative parts of the
universe of discourse, respectively. The computation time and code size of the fuzzy
controller can be reduced when the number of subsets for the positive and negative parts
is a power of 2, because shift instructions can be used to calculate the membership
degrees instead of division functions.
There was a trade off between the size of the rule base and the performance of the
fuzzy controller. A 17×17 rule base was designed and implemented for the boost
converter. Experimental results indicated that the fuzzy controller with a 33×33 rule base
exhibited less oscillation during steady state and faster transient response was achieved
by increasing the output gain h. More membership functions resulted in finer control for
the same universe of discourse. The output of the controller had less variation when
either of the inputs changed slightly. Therefore, more accurate control was achieved and
chattering and oscillation were reduced. However, increasing the rule base resulted in a
larger amount of memory used. The size of the rule base was determined based on the
balance of the performance of the controller and the amount of memory used.
Generally, the implementation of a linear controller was less demanding than the
implementation of a fuzzy controller. Most DSPs are optimized for implementation of
digital filters. On the contrary, more computational power and memory are required to
implement a fuzzy controller than a linear controller. To reduce the computation time and
amount of memory used, several techniques have been utilized. A digital signal processor
(DSP) with fast computation speed and high computation power is more appropriate for
the implementation of fuzzy controllers in real time.
65
For comparison purposes, experimental results of the buck and boost converters
using fuzzy controllers will be presented in Chapter 6.
66
CHAPTER 5
SLIDING MODE FUZZY CONTROLLER DESIGN FOR DCDC CONVERTERS
Sliding mode control is a method for controlling systems with parametric
uncertainties and external disturbances. A sliding mode is achieved by forcing the system
trajectory on a properly designed switching function using high speed switch control.
Sliding mode control is able to provide a very robust closedloop system.
In sliding mode control, invariance can be achieved, which means that the system
can be entirely independent of plant uncertainties and disturbances. There are two steps to
design a sliding mode controller. First, a switching surface σ(x) = 0 in the state plane that
has x as coordinates is designed to specify desired closedloop system dynamics. Then a
variable structure switching control u is designed to drive the state trajectory to the
switching surface in finite time. The control u is shown in (5.1):
u = u
+
when σ(x) > 0
u = u

when σ(x) < 0 (5.1)
The period of time in which the state trajectory moves toward and reaches the switching
surface is called the reaching mode. The reaching condition is the sufficient condition for
a reaching mode. When the state trajectory stays on the switching surface, it is in a
sliding mode. In sliding mode control, the state trajectory follows the desired dynamics
that are described by the switching function.
67
Theoretically, sliding mode control is very suitable for the control of DCDC
converters. Because DCDC converters change from one state to another when the switch
is turned on or off, sliding mode control is able to move the state trajectory onto the
switching surface by controlling the switch. However, several disadvantages exist for
sliding mode control. First of all, a basic assumption for sliding mode control is that the
control can be switched infinitely fast from one state to another. In practice, this is
impossible due to the time delay for control computation and physical limitations of
switching devices. As a result, chattering always occurs in steady state and appears as an
oscillation in steady state. The oscillation may excite unmodeled highfrequency
dynamics of the system [20]. Therefore, chattering is very undesirable. The second
disadvantage is that the sliding mode controller will generate an ONOFF control for DC
DC converters, and the switching frequency is not regulated. Hysteresis can be used to
regulate the switching frequency, but a constant switching frequency can not be
guaranteed. With hysteresis, there is always some chattering in the sliding mode. The
third disadvantage is when the sliding mode control is implemented in discretetime, the
control action (in this case, ON or OFF of the switch) can only be activated at each
sampling instant and the control effort is constant over each sampling period. Thus, the
system is able to approach the sliding mode but not able to stay on it. The practical issues
above prevent the sliding mode control from being extensively applied to DCDC
converters.
Fuzzy controllers were applied to control DCDC converters in Section 4.2.
Design of fuzzy controllers does not require an exact mathematical model and is well
suited to nonlinear timevariant systems. However, fuzzy controllers are usually designed
68
based on expert knowledge of converters, and extensive tuning is required based on a
trial and error method. The tuning can be quite timeconsuming. In addition, the response
is not easy to predict.
In this chapter, a sliding mode fuzzy controller is used to control buck and boost
converters. The sliding mode fuzzy controller combines the advantages of both fuzzy
controllers and sliding mode controllers. It is like a modified sliding mode controller, and
it is more robust than an ordinary sliding mode controller. The sliding surface in a sliding
mode fuzzy controller is rendered by rule bases and scaling factors, rather than a
function. Sliding mode fuzzy control has advantages of its own that cope with the
problems in the sliding mode control and fuzzy control design and implementation.
Design of sliding mode fuzzy controllers for buck and boost converters is described in
detail in the next section. Implementation of sliding mode fuzzy controllers is presented
in the second section.
5.1 Design of Sliding Mode Fuzzy Controller for DCDC Converters
A sliding mode fuzzy controller has several advantages that make it applicable to
control of DCDC converters. First of all, the chattering problem is eliminated by
incorporating a boundary layer into the rule base. The second advantage is that the sliding
mode fuzzy controller can be implemented like a regular fuzzy controller. The output
from the sliding mode fuzzy controller is duty cycle directly; therefore, constant
switching frequency is achieved. Last but not the least, since sliding mode fuzzy
controllers can be designed systematically based on the principles of sliding mode
control, the amount of time needed for tuning is significantly reduced, and the system’s
response can be predicted. Like a regular fuzzy controller, a sliding mode fuzzy
69
controller includes four main components: (1) the fuzzification interface that converts the
inputs into information that the inference mechanism can use to activate and apply rules,
(2) the rule base which contains the expert’s linguistic description of how to achieve good
control, (3) the inference mechanism that evaluates which control rules are relevant in the
current situation, and (4) the defuzzification interface which converts the conclusion from
the inference mechanism into the control input to the plant.
There are four steps involved in the design of a sliding mode fuzzy controller: (1)
a switching function that represents a desired system dynamics is first designed, (2) from
the switching function, inputs to the sliding mode fuzzy controller and their scaling
factors can be determined, (3) a rule base is designed according to the switching function,
and (4) other parts of the sliding mode fuzzy controller such as the inference mechanism
and defuzzification method are designed. These four steps will be followed to design
sliding mode fuzzy controllers for buck and boost converters.
5.1.1 Switching Functions
A switching function defines the desired dynamics of the system. Switching
functions for the buck converter and boost converter are presented in this section.
A switching function is often of lower order than the plant. Since a boost
converter’s small signal model is second order, a firstorder switching function is
designed, which is shown in (5.2).
e e e s λ + = & ) ( (λ>0) (5.2)
When s(e) = 0, dynamics on the sliding surface are shown in (5.3).
0 = + e e λ & (5.3)
70
In the s domain, (5.3) becomes s+λ=0. A stable firstorder system with a pole at –λ is
represented by the dynamics in (5.3). The time constant τ is 1/ λ seconds, and the settling
time is 4/ λ seconds.
For the boost converter, to obtain a settling time of 10 ms, the time constant τ
should be 2.5 ms. Because λ =1/ τ, λ is 400. The switching function designed for the
sliding mode fuzzy controller is given by (5.4). s(e)=0 is called the switching line, and it
is plotted in Figure 5.1. The step response of (5.4) is simulated and shown in Figure 5.2.
The settling time of the step response is 10 ms, and there is no overshoot.
e e e s 400 ) ( + = & (5.4)
In a digital implementation, e& was approximated as shown in (5.5), where e[k] is
the error of the k
th
sample of the output voltage, and T is the sampling period. In this
experiment, the sampling frequency was chosen to be 150 kHz, and T was 6.67µs.
Substituting (5.5) into (5.4) yields (5.6), which is the switching function when the sliding
mode fuzzy controller is implemented in discretetime, where ce[k] is the difference
between e[k] and e[k1].
T
k e k e
e
] 1 [ ] [ − −
= & (5.5)
] [ 400
] [
] [ 400
] 1 [ ] [
) ( k e
T
k ce
k e
T
k e k e
e s + = +
− −
= (5.6)
71
s (e)=0
e&
e
Figure 5.1 Switching function of the sliding mode fuzzy controller for boost converter
Figure 5.2 Step response of the switching function for boost converter
For the buck converter, to obtain a settling time of 1 ms, the time constant τ
should be 0.25 ms, and λ =1/τ = 4000. The switching function designed for the sliding
mode fuzzy controller for the buck converter is given in (5.7). The step response of (5.7)
was simulated and is shown in Figure 5.3. The settling time of the step response is 1 ms,
and there is no overshoot.
e e e s 4000 ) ( + = & (5.7)
72
Figure 5.3 Step response of switching function for buck converter
Substituting (5.5) into (5.7) yields (5.8), which is the switching function for the
sliding mode fuzzy controller in discretetime. In this equation, ce[k] is the difference
between e[k] and e[k1].
] [ 4000
] [
] [ 4000
] 1 [ ] [
) ( k e
T
k ce
k e
T
k e k e
e s + = +
− −
= (5.8)
5.1.2 Inputs and Their Scaling Factors
From the switching function in (5.6), it can be determined that the sliding mode
fuzzy controller for the boost converter has two inputs. The first input is the error in the
output voltage e[k]=ADC[k]Ref, where ADC[k] is the converted digital value of the kth
sample, and Ref is the digital value corresponding to the desired output voltage. The
second input ce[k]=e[k]e[k1] is the difference between the error of the kth sample and
the error of the (k1)th sample. The two inputs are multiplied by the scaling factors g0 and
g1 respectively, and then fed into the fuzzy controller. The membership functions for e[k]
73
and ce[k] are shown in Figure 5.4. Each universe of discourse was divided into 33 fuzzy
subsets: N16,N15,N14,…,N1,Z,P1,…,P15,P16, where N indicates negative, Z represents
zero and P indicates positive. The variables µ
e
(e[k]) and µ
ce
(ce[k]) are the membership
degrees assigned to each fuzzy subset to quantify the certainty that the input can be
classified linguistically into the corresponding fuzzy subsets. A triangleshaped
membership function was used for this controller design for the ease of implementation.
Of the 33 subsets, there were 16 subsets for the positive and negative parts of the universe
of discourse, respectively. For the purpose of implementation, the computation time and
code size of the fuzzy controller can be reduced when the number of subsets for the
positive and negative parts is a power of 2, because shift instructions can be used to
calculate the membership degrees instead of division functions. From experimental
results, 33 fuzzy subsets was the smallest number of fuzzy sets in order to obtain
satisfactory response for the boost converter.
Figure 5.4 Membership functions of the inputs e[k] and ce[k] for the boost converter
The two input scaling factors g0 and g1 have a significant impact on the
controller’s performance, and usually require extensive tuning. In designing the fuzzy
sliding mode controller, g0 and g1 can be directly determined from the switching
74
function in (5.6). Laboratory observation of the boost converter indicated that if the
scaling factor g0 of e[k] is less than 1, the precision of the measured output voltage was
reduced, which can lead to steady state error. Therefore, g0 was chosen to be 1, and the
scaling factor g1 of ce[k] becomes 1/(400T), which equals 375 when the sampling
frequency is 150 kHz.
5.1.3 Rule Base
In a regular fuzzy controller, the rule base is often designed from an indepth
knowledge of the plant using a trial and error approach, which is very timeconsuming. In
the sliding mode fuzzy controller design, the rule base is derived from the switching
function. After scaling the inputs e[k] and ce[k] by g0 = 1 and g1 = 375, respectively, the
diagonal line from upper left corner to bottom right corner in the rule base represents the
switching line s(e) = 0. To avoid drastic changes in the controller output, a boundary
layer was introduced, which was designed in the rule base. The principles to design the
rule base are summarized as follows:
(1) ci should be negative above the switching line, and positive below it, where ci is
the center in the rule base that represents change in duty cycle.
(2) ci should increase as the distance between the actual state and the switching line
s(e) = 0 increases.
(3) ci should increase as the distance between the actual state and the line
perpendicular to the switching line increases, so that discontinuities close to the
switching line can be reduced.
75
(4) when e[k] and ce[k] fall out of the state plane, the maximum value of ci should
cover those states with their respective signs, which incorporates a boundary layer
into the rule base.
The relationship between ci and the switching function s(e) is shown in Figure
5.5. According to the principles above, the phase plane is divided into two semiplanes by
the switching line. Within each semiplane, positive and negative control outputs are
applied, respectively. The magnitude of the control output is associated with the distance
of the state vector to the switching line. A boundary layer was incorporated into the rule
base to eliminate chattering in steady state. Outside the boundary layer, the control had a
relay characteristic, and within the layer, the control was a highgain linear control.
A small 7×7 rule base for the sliding mode fuzzy controller is shown in Table 5.1
for illustration purposes. In the table, N stands for negative, P stands for positive, and Z
represents zero. B means big, M means medium and S stands for small. For example, NB
means negative big.
ci
s(e)
L
L
Figure 5.5 Function between ci and s(e)
76
Table 5.1: 7×7 Rule base of the sliding mode fuzzy controller
Change in error (CE)
NB NM NS Z PS PM PB
PB Z NS NM NM NB NB NB
PM PS Z NS NM NM NM NB
PS PM PS Z NS NS NM NB
Z PM PM PS Z NS NM NM
NS PB PM PS PS Z NS NM
NM PB PM PM PM PS Z NS
E
r
r
o
r
(
E
)
NB PB PB PB PM PM PS Z
A 33×33 rule table was derived for the sliding mode fuzzy controller for the boost
converter based on the principles above. There was a trade off between the size of the
rule base and the performance of the sliding mode fuzzy controller. More membership
functions resulted in finer control. The output of the controller had less variation when
either of the inputs had small changes, and a more accurate control was achieved.
5.1.4 Inference Mechanism and Defuzzification Method
The results of the inference mechanism include the weighing factor w
i
and the
change in duty cycle c
i
of the individual rule [4]. The weighing factor w
i
was obtained by
Mamdani’s min fuzzy implication of µ
e
(e[k]) and µ
ce
(ce[k]), where w
i
= min{µ
e
(e[k]),
µ
ce
(ce[k])} and µ
e
(e[k]), µ
ce
(ce[k]) are the membership degrees [10]. c
i
was taken from the
rule base. The change in duty cycle inferred by the i
th
rule z
i
is written in (5.9).
i ce e i i i
c k ce k e c w z × = × = ])} [ ( ]), [ ( min{ u u (5.9)
The center of average method was used to obtain the sliding mode fuzzy
controller’s output δd[k], which is given in (5.10). When using triangleshaped
77
membership functions, there are at most four rules that are effective at any one time;
therefore, N = 4. The output of the sliding mode fuzzy controller was added to the
previous sampling period’s duty cycle d[k1]. The integration of the controller’s output
increases the system type and improves the steadystate error.
 
∑
∑
=
=
×
=
N
i
i
N
i
i i
w
c w
k d
1
1
δ
(5.10)
5.2 Implementation of Sliding Mode Fuzzy Controller
A Simulink model for a sliding mode fuzzy controller for DCDC converters is
shown in Figure 5.6. Implementation of the sliding mode fuzzy controller had similar
issues as the implementation of an ordinary fuzzy controller. When implementing the
sliding mode fuzzy controller, a Gaussian lowpass filter was added to ce[k] in steady state
to filter out the undesired high frequency noise to smooth the controller’s output. The
noise was mainly introduced by the quantization errors and the switching action in the
converter circuit. The change in error was calculated using ce[k]=e[k]ev[k1], where
ev[k1] = e[k1]/4 + e[k2]/2 + e[k3]/4 and was obtained using the Gaussian lowpass
filter. The coefficients of the Gaussian filter were [1/4 1/2 1/4]. The Gaussian filter
reduced the high frequency noise, and it was characterized by narrow bandwidth, sharp
cutoff frequency and low overshoot. The filter was very simple to implement on the TI
DSP. Because the coefficients of the filter were 1/2 and 1/4, a shift instruction was used
instead of calling the function to divide two numbers, thus reducing the computation time.
78
The sliding mode fuzzy controllers for buck and boost converters were also
implemented on the TI TMS320F2812 DSP. Experimental results will be presented in the
next chapter.
Figure 5.6 Simulink model of the system using sliding mode fuzzy controller for the DC
DC converters
79
CHAPTER 6
EXPERIMENTAL RESULTS
Experimental results for the DSPcontrolled buck and boost converters are
presented in this chapter.
6.1 Experimental Results for PID and PI Controllers
Design and implementation of the PID and PI controllers for the buck and the
boost converters were presented in Sections 3.2 and 3.3, respectively. Experimental
results for the buck and the boost converters are presented in this chapter. PID and PI
controllers were switched between transient and steady state to obtain desired responses.
The PID controller was applied during start up to obtain a fast transient response. The PI
controller was applied during steady state to reduce oscillation of the duty cycle and
improve the system’s stability. The sampling and switching frequencies of both PID and
PI controllers were 150 kHz.
6.1.1 Buck Converter
The start up transient response is shown in Figure 6.1. The settling time is about 1
ms without any overshoot. The load transient response is shown in Figure 6.2 when the
load current changed from 1.364 A to 0.16 A. The settling time was about 2 ms, and the
maximum transient error was 120 mV.
80
Figure 6.1 Start up transient response of the buck converter using the linear PID and PI
control method (5 V/div, 500 µs/div)
Figure 6.2 Transient response for the buck converter using the linear PID and PI control
method when the load changed from 1.364 A to 0.16 A (100 mV/div, 500 µs/div)
81
6.1.2 Boost Converter
The start up transient response is shown in Figure 6.3. The rise time is 15 ms, with
about 10% overshoot. The transient response when the load changed from 0.24 A to 0.48
A using the PID and PI control method is shown in Figure 6.4. The settling time was about
10 ms. There was a 100 mV steadystate error.
Figure 6.3 Start up transient response of the boost converter using the linear PID and PI
control method (2 V/div, 5 ms/div)
82
Figure 6.4 Transient response for the boost converter using the linear PID and PI control
method when the load changed from 0.24 A to 0.48 A (200 mV/div, 2 ms/div)
6.2 Experimental Results for Fuzzy Controllers
Design and implementation of fuzzy controllers for the buck and the boost
converters were presented in Sections 4.2 and 4.3, respectively. Experimental results of
the fuzzy controllers for the buck and the boost converters are presented in this section.
6.2.1 Buck Converter
For the buck converter, the fuzzy controller shown in Figure 4.3 was implemented.
It produced the duty cycle d[k] by adding a linear integrator to the output of the fuzzy
controller shown in (4.2). The input scaling factors g0, g1 and the output scaling factor h
of the fuzzy controller for the buck converter were tuned to be 1, 1, and 1, respectively,
based on experimental results and simulation by Simulink. Experiments from the buck
converter indicated that if the scaling factor g0 of e[k] was less than 1, the precision of the
measured output voltage was reduced. Therefore, g0 was chosen to be 1. g1 was tuned to
83
be 1 based on simulation and experimental result. The output scaling factor h was tuned to
1 to achieve a fast transient response without overshoot. The gain of the linear integrator
K
I
was chosen to be 0.000381. Because the error of the output voltage was accumulated
every sampling period and the sampling period was only 6.67 µs, a small value of K
I
was
chosen.
The start up transient response is shown in Figure 6.5. The settling time was about
1 ms with a little overshoot. The load transient response is shown in Figure 6.6 when the
load current changed from 1.364 A to 0.16 A. The settling time was about 2 ms. The
maximum transient error was 140 mV.
A fuzzy controller with a 7*7 rule base was also designed and implemented for
the buck converter. The start up transient response is shown in Figure 6.7. The settling
time is about 1 ms with a little overshoot, which is very similar to the start up transient
response in Figure 6.5. The load transient response is shown in Figure 6.8 when the load
current changed from 1.364 A to 0.16 A. The settling time was about 7 ms, and the
maximum transient error was 300 mV. A comparison between Figure 6.6 and Figure 6.8
indicates that a much shorter settling time and smaller maximum transient error was
obtained by using the 17*17 rule base. Experimental results verified that the addition of
more membership functions and rules can provide a more accurate control, which can
reduce chattering and oscillation.
Experimental results of linear PID and PI controllers for the buck converter were
presented in the first section of this chapter. They are compared with the experimental
results of the fuzzy controllers for the buck converter. Comparisons between Figure 6.1
and Figure 6.5 and between Figure 6.2 and Figure 6.6 show that the linear PID and PI
84
controller obtained similar results as the fuzzy controller using the 17*17 rule base. The
poles and zero of the buck converter’s small signal model don’t change when the
operating point varies. The change in the operating point only has impact on the
magnitude of the buck converter’s small signal model. Therefore, the linear PID and PI
controller was able to achieve similar response as the fuzzy controller.
Figure 6.5 Start up transient response of the buck converter using the second
fuzzy control method with 17*17 rule base (5 V/div, 500 µs/div)
85
Figure 6.6 Transient response for the buck converter using the second fuzzy control
method with 17*17 rule base when the load changed from 1.364 A to 0.16 A
(100 mV/div, 500 µs/div)
Figure 6.7 Start up transient response of the buck converter using the second fuzzy
control method with 7*7 rule base (5 V/div, 500 µs/div)
86
Figure 6.8 Transient response for the buck converter using the second fuzzy control
method with 7*7 rule base when the load changed from 1.364 A to 0.16 A
(100 mV/div, 1 ms/div)
6.2.2 Boost Converter
For the boost converter, the fuzzy controller shown in Figure 4.3 was also
implemented. It produced the duty cycle d[k] by (4.2). Based on simulation by Simulink
and experimental results, the scaling factors g0, g1 and h of the fuzzy controller for the
boost converter were tuned to be 1.5, 1, and 1, respectively, and the gain of the integrator
K
I
was chosen to be 0.000122.
The start up transient response is shown in Figure 6.9. The settling time was about
6ms with no overshoot. However, when the load current changed, there was 200 mV
steadystate error. To eliminate the steadystate error, the first method to get the duty
cycle d[k] was used, which is shown in Figure 4.2. The new duty cycle was calculated by
(4.1). In this method, the output of the fuzzy controller was added to the previous
87
sampling period’s duty cycle d[k1]. The integration of the fuzzy controller’s output
increased the system type and improved the steadystate error.
In addition, a Gaussian lowpass filter was added to decrease the noise in the
difference of error ce[k] at steady state. The noise was mainly introduced by the
quantization errors and the switching action in the converter circuit. The change in error
was calculated using ce[k]=e[k]ev[k1], where ev[k1] = e[k1]/4 + e[k2]/2 + e[k3]/4.
ev[k1] was obtained by the Gaussian lowpass filter. The coefficients of the Gaussian
filter were [1/4 1/2 1/4]. The Gaussian filter reduced the high frequency noise, and it was
characterized by narrow bandwidth, sharp cutoff frequency and low overshoot. The filter
was very simple to implement on the TI DSP. Because the coefficients of the filter were
1/2 and 1/4, a shift instruction was used instead of calling the function to divide two
numbers, therefore reducing the computation time.
Figure 6.9 Start up transient response of the boost converter using the second
fuzzy control method (2 V/div, 5 ms/div)
88
When using the fuzzy controller configuration in Figure 4.2, the output gain h had
to be tuned to be very small to avoid oscillation during steady state. Scaling factors g0, g1
and h were tuned to be 3, 2 and 0.0001373, respectively. The transient response of the
boost converter when the load changed from 0.24 A to 0.48 A is shown in Figure 6.10.
The settling time was about 10 ms. The maximum transient error was about 400 mV.
Both structures in Figure 4.2 and Figure 4.3 should result in zero steadystate
error, because both have integrators to eliminate the steadystate error. However,
experimental results from the boost converter indicated that steadystate error was
observed during load transients by using the structure in Figure 4.3. In the first structure
in Figure 4.2, the integration was realized by accumulating the fuzzy controller’s output.
The controller is a pure nonlinear controller. While for the topology shown in Figure 4.3,
the linear integrator and the fuzzy controller were in parallel. It was a combination of
linear and nonlinear controller. The reason why the second topology resulted in steady
state error during load transients requires further investigation.
A comparison of the boost converter’s experimental results obtained using the
fuzzy control method shown in Figure 6.9 and Figure 6.10 and those obtained using the
linear PID and PI control method shown in Figure 6.3 and Figure 6.4 indicates that fuzzy
control was able to achieve faster transient response without overshoot, better rejection to
load variation, more stable steadystate response and less dependence on the operating
point. The advantage of the fuzzy control method applied to the boost converter was much
more obvious than application to the buck converter.
An examination of the buck converter and the boost converter’s small signal
models suggests that the boost converter’s small signal model is a nonlinear function of
89
the operating point, while only the magnitude of the buck converter’s small signal model
shifts with the change of operating point [3]. The linear PID and PI controller was
designed only for the nominal operating point. When the operating point varies, both the
shape and the position of the bode plot of the boost converter’s small signal model
changes. Therefore, the linear controller was not able to respond well for the boost
converter. On the other hand, since the fuzzy controller doesn’t require an exact
mathematical model, it was not designed based on a specific operating point. It responded
to the line and load variations more effectively than the linear controller. However, one
disadvantage of the fuzzy control method was that it required extensive tuning by the trial
and error method. Simulation by Simulink can provide some guidance and help to reduce
the amount of time needed for tuning.
Figure 6.10 Transient response for the boost converter using the first fuzzy control
method when the load changed from 0.24 A to 0.48 A
(200 mV/div, 2 ms/div)
90
6.3 Experimental Results for Sliding Mode Fuzzy Controllers
Experimental results of the sliding mode fuzzy controllers for both the buck
converter and the boost converter are presented and evaluated in this section.
6.3.1 Boost Converter
The start up transient response of the boost converter using sliding mode fuzzy
control when the input voltage varied from 4 V to 7 V is shown in Figure 6.11. The
settling time was about 8 ms with very little overshoot at the nominal input voltage of 5
V. As the input voltage increased from 4 V to 7 V, the settling time decreased. When the
input voltage was 7 V, the settling time was only 5 ms.
The transient response of the boost converter using sliding mode fuzzy control
when the load changed from 0.24 A to 0.48 A at different input voltages is shown in
Figure 6.12. The settling time was about 10ms at nominal input voltage. The maximum
transient error is about 400 mV. When the input voltage increased from 4 V to 7 V, the
settling time decreased and the maximum transient error decreased.
Transient responses in Figure 6.11 and Figure 6.12 indicate that the experimental
result’s settling time and overshoot at nominal input voltage matched the desired
dynamics represented by the switching function in (5.4). A settling time of less than or
equal to 10 ms was achieved. When the input voltage increased, the settling time for both
the start up and load transient response decreased. The output voltage was stable in steady
state.
91
Figure 6.11 Start up transient response of the boost converter using sliding mode
fuzzy control with different input voltage (2 V/div, 5 ms/div)
Figure 6.12 Transient response of the boost converter using sliding mode fuzzy
control when the load current changed from 0.24 A to 0.48 A (200 mV/div, 2 ms/div)
1—Vin=4V
2—Vin=5V
3—Vin=6V
4—Vin=7V
1
2
3
4
1
2
3
4
1—Vin=4V
2—Vin=5V
3—Vin=6V
4—Vin=7V
92
When using ordinary fuzzy controllers, two structures of fuzzy controllers were
applied to the prototype boost converter during start up and steady state to obtain both fast
transient and stable steadystate response without steadystate error. While for the sliding
mode fuzzy controller, only one structure was used for all operating points. This indicates
that the sliding mode fuzzy controller is able to perform well under operating point
variations.
6.3.2 Buck Converter
The start up transient response using the sliding mode fuzzy controller when the
input voltage varies from 17 V to 23 V is shown in Figure 6.13. The settling time is about
2 ms with very little overshoot at a nominal input voltage of 20 V, while the designed
settling time is only 1 ms. The reduction of the speed of the transient response was
mainly caused by the parallel linear integrator. As the input voltage increased from 17 V
to 23 V, the settling time remained the same. The overshoot at the nominal input voltage
was 3.3%, and increased a little when the input voltage increases. The steadystate
response of the buck converter and the PWM signal are shown in Figure 6.14 Note that
there is no oscillation of the duty cycle in steady state.
The load transient response of the buck converter when the load decreased from
0.96 A to 0.48 A is shown in Figure 6.15. When the input voltage varied from 17 V to 23
V, the settling time remained at about 4 ms. The maximum transient error was about 160
mV when the input voltage was 17 V, and was about 140 mV when the input voltage was
23 V.
When the load increased from 0.48 A to 0.96 A, the load transient response of the
buck converter is shown in Figure 6.16. The settling time remained at about 4 ms, which
93
is the same as the settling time when the load current decreases. The maximum transient
error was about 140 mV when the input voltage was 17 V, and was about 120 mV when
the input voltage was 23 V.
From the load transient responses in Figure 6.15 and Figure 6.16, it can be
observed that variations in settling time and the maximum transient error with changes in
the input voltage were small.
Figure 6.13 Start up transient response of the buck converter using sliding mode fuzzy
controller with different input voltage
(2 V/div, 1 ms/div)
1
2
1—Vin=17V
2—Vin=20V
3—Vin=23V
3
94
Figure 6.14 Steadystate response of the buck converter with the PWM signal
(5 V/div, 5 µs/div)
Figure 6.15 Load transient response of the buck converter using sliding mode fuzzy
controller when the load changed from 0.96 A to 0.48 A with different input voltage
(100 mV/div, 1 ms/div)
1
2
3
1—Vin=17V
2—Vin=20V
3—Vin=23V
95
Figure 6.16 Load transient response of the buck converter using sliding mode fuzzy
controller when the load changed from 0.48 A to 0.96 A with different input voltage
(100 mV/div, 1 ms/div)
6.4 Comparison of Experimental Results of Linear and Nonlinear Control Methods
Experimental results of linear and nonlinear control methods applied to buck and
boost converters are compared in this section.
6.4.1 Buck Converter
For comparison purposes, the experimental results of the buck converter using
the ordinary fuzzy controller when the input voltage changed were evaluated. The start up
transient response when the input voltage varied from 17 V to 23 V is shown in Figure
6.17. The settling time at the nominal input voltage of 20 V was about 8 ms with about
7% overshoot. When the input voltage increased from 17 V to 23 V, the settling time
remained the same. The overshoot increased when the input voltage increased from 17 V
to 23 V.
3
2 1
1—Vin=17V
2—Vin=20V
3—Vin=23V
96
The load transient response of the buck converter using the ordinary fuzzy
controller when the load current decreased from 0.96 A to 0.48 A is shown in Figure
6.18. When the input voltages changed from 17 V to 23 V, the settling time remained at
about 0.8 ms and maximum transient error remained at about 60 mV.
The load transient response of the buck converter when the load current increased
from 0.48 A to 0.96 A is shown in Figure 6.19 When the input voltage increased from 17
V to 23 V, the settling time remained at about 1 ms, and the maximum transient error
remained at about 60 mV.
Figure 6.17 Start up transient response of the buck converter using ordinary fuzzy
controller with different input voltage
(2 V/div, 1 ms/div)
1—Vin=17V
2—Vin=20V
3—Vin=23V
3
2 1
97
Figure 6.18 Load transient response using ordinary fuzzy controller when the load
changed from 0.96 A to 0.48 A with different input voltage
(100 mV/div, 1 ms/div)
Figure 6.19 Load transient response using ordinary fuzzy controller when the load
changed from 0.48 A to 0.96 A with different input voltage
(100 mV/div, 1 ms/div)
3
1
1—Vin=17V
2—Vin=20V
3—Vin=23V
2
1—Vin=17V
2—Vin=20V
3—Vin=23V
3
1
2
98
For comparison purposes, a PID/PI controller was also implemented for the buck
converter. The derivative term in a PID controller is susceptible to noise and
measurement error of the system, which could result in oscillation of the duty cycle
during steady state. However, during transient operation, the derivative term is needed to
reduce the settling time by predicting the changes in error. Therefore, PID and PI
controllers are switched between transient and steady state to obtain fast response without
oscillation in steady state.
The start up transient response using the PID/PI controller is shown in Figure 6.20
The settling time was about 4 ms when the input voltage was 20 V. Both the settling time
and overshoot increase when the input voltage increased from 17 V to 23 V.
The load transient response using the PID/PI controller is shown in Figures 6.21
and 6.22, respectively. When the load decreased from 0.96 A to 0.48 A as shown in
Figure 6.21, the settling time remained at about 1 ms, and the maximum transient error
remained at about 60 mV. When the load increased from 0.48 A to 0.96 A as shown in
Figure 6.22, the settling time remained at about 1 ms, and the maximum transient error
remained in the range of 40 to 60 mV.
99
Figure 6.20 Start up transient response of the buck converter using PID/PI controller
with different input voltage
(2 V/div, 1 ms/div)
Figure 6.21 Load transient response using PID/PI controller when the load changed
from 0.96 A to 0.48 A with different input voltage
(100 mV/div, 1 ms/div)
1
2
1—Vin=17V
2—Vin=20V
3—Vin=23V
3
1—Vin=17V
2—Vin=20V
3—Vin=23V
3
2
1
100
Figure 6.22 Load transient response using PID/PI controller when the load changed
from 0.48 A to 0.96 A with different input voltage
(100 mV/div, 1 ms/div)
A comparison of the performance between the sliding mode fuzzy control,
ordinary fuzzy control and PID/PI control for the buck converter is quantified in Table
6.1. An examination of the experimental results shows that the sliding mode fuzzy
control obtained the shortest settling time and smallest overshoot during a start up
transient. Furthermore, it can be observed that the start up transient response varied the
least using sliding mode fuzzy control when the input voltage changed from 17 V to 23V.
1—Vin=17V
2—Vin=20V
3—Vin=23V
1
3 2
101
Table 6.1: Comparison of Performance of Sliding Mode Fuzzy Control vs. Ordinary
Fuzzy Control vs. PID/PI Control for Buck Converter
Experimental results
Sliding
mode
fuzzy
control
Ordinary
fuzzy
control
PID/PI
control
Settling time (ms) 2 8 4 Start up
transient
response
Overshoot(%) 3.3 7 10
Settling
time (ms)
4 0.8 1
Load
decrease Maximum
error(mV)
150 60 60
Settling
time (ms)
4 1 1
Load
Transient
response
Load
increase Maximum
error(mV)
110 60 40
Experimental results for load transients using different control methods were also
evaluated and compared. Ordinary fuzzy control and PID/PI control obtained very similar
load transient response for both load increase and load decrease. When the input voltage
changed from 17 V to 23 V, the load transient response varied very little. On the other
hand, the settling time obtained using sliding mode fuzzy control was much longer than
the settling time obtained using the other two control methods. The maximum transient
error was also the largest for the sliding mode fuzzy control among all three control
methods.
The comparison indicates that sliding mode fuzzy control obtained a more
satisfactory start up transient response than ordinary fuzzy control and PID/PI control
methods, while the load transient response using sliding mode fuzzy control was less
satisfactory than the other two control methods. During a start up transient, the small
102
signal model of the converter changes dramatically. Because sliding mode fuzzy control
can yield a very robust closedloop system under plant uncertainties like ordinary sliding
mode control, it is able to respond to start up transient more effectively than ordinary
fuzzy control and PID control. On the other hand, during load transients, the small signal
model of a buck converter changes less dramatically than during a start up transient.
Therefore, linear controllers such as PID control are able to respond more effectively than
sliding mode fuzzy control. A possible reason that ordinary fuzzy control obtained faster
load transient response than sliding mode fuzzy control is that the ordinary fuzzy
controller had been tuned extensively using a trial and error method, while it takes much
less time to tune the sliding mode fuzzy controller.
6.4.2 Boost Converter
Experimental results obtained using linear and nonlinear control methods are
compared for the buck and boost converters. For the buck converter, linear and nonlinear
control methods obtained similar experimental results. While for the boost converter,
there was a clear difference between the results from the linear and nonlinear control
methods.
Table 6.2 compares the performance of PID control, fuzzy control and sliding
mode fuzzy control for the boost converter. Both start up transient response and load
transient response are compared. For the start up transient response, the fuzzy controller
obtained the shortest settling time, while the PID controller had the longest settling time.
There was a 10% overshoot with the PID control and no overshoot for the fuzzy and
sliding mode fuzzy control. For the load transient response, all three control methods
obtained the same settling time. The maximum transient error was actually smaller for the
103
PID control, but there was a 100 mV steadystate error for the PID control. The fuzzy
control and sliding mode fuzzy control obtained very similar experimental results for the
boost converter. However, the design of sliding mode fuzzy control was more systematic,
and system’s response was easier to predict.
An examination of the small signal models for the converters shows that only the
magnitude of the buck converter’s small signal model shifts with the change of operating
point. But for the boost converter, both the shape and the position of the frequency
response changes. Therefore, the linear PID controller was not able to respond well for
the boost converter. Since the fuzzy controller is nonlinear and adaptive in nature, it
responded to the line and load disturbances more effectively than linear controllers.
Table 6.2: Comparison of Performance of PID Control, Fuzzy Control, and Sliding Mode
Fuzzy Control for the Boost Converter
Experimental Results PID control Fuzzy control Sliding mode
fuzzy control
Settling time
(ms)
15 6 8 Start up
transient
response Overshoot
(%)
10 0 0
Settling time
(ms)
10 10 10
Maximum
transient error
(mV)
200 400 400
Load transient
response
Steadystate
error
(mV)
100 0 0
104
CHAPTER 7
CONCLUSION AND FUTURE WORK
Issues in the design and implementation of digital controllers for buck and boost
converters have been discussed in this dissertation. There are many control methods that
may be used to design digital controllers for DCDC converters. Generally, these methods
fall into two categories: linear and nonlinear control methods. Both linear and nonlinear
techniques have been reported in this dissertation.
Analog PID and PI controllers were designed using the frequency response method
based on the small signal models of buck and boost converters. The PID and PI controllers
were then converted into discrete time. Advantages of frequency response techniques are:
design and analysis are relatively easy and implementation is straightforward on a DSP.
The disadvantages are: performance of the controller is dependent on the operating point
and the controller needs to be modified to obtain both fast and stable response.
The performance of a linear controller is dependent on the load and working point.
Since small signal models obtained using state space averaging techniques are linear
approximations of the local behavior of the system, the small signal models change due
tochanges in operating points. Linear controllers are designed based on the small signal
models. Therefore, their performance is dependent on the working point, the parasitic
elements, and the load and line conditions.
105
To achieve a stable steadystate response and fast transient response under varying
operating points, nonlinear controllers were used to control buck and boost converters. In this
dissertation, nonlinear control techniques, including fuzzy controllers and sliding mode fuzzy
controllers, were applied to buck and boost converters.
Among the various techniques of artificial intelligence, the most popular and widely
used technique in control systems is fuzzy control. Fuzzy controllers were designed based on
the general knowledge of the converters. The controller was then tuned using a trial and error
method to obtain satisfactory response. Since a fuzzy controller is a nonlinear controller, it is
able to adapt to varying operating points.
The second nonlinear control method is sliding mode fuzzy control. Sliding mode
fuzzy control combines the advantage of sliding mode control and fuzzy control. It also has
advantages of its own that cope with the problems in the sliding mode control and fuzzy
control design and implementation.
The advantages of fuzzy controllers are: exact mathematical models are not
required for the design of fuzzy controllers, complexities associated with nonlinear
mathematical analysis are relatively low, and fuzzy controllers are able to adapt to
changes in operating points. The disadvantages of fuzzy controllers are: extensive tuning
may be required based on trial and error method and the system’s response is not easy to
predict. The advantages of sliding mode fuzzy controllers are: the design of sliding mode
fuzzy controller is more systematic and the system’s response is easier to predict. The
disadvantage is that some tuning may still be required.
All the digital controllers were implemented on a TI TMS320F2812 Digital Signal
Processor (DSP). The F2812 DSP is a 32bit, fixed point DSP. Experimental results
106
obtained using linear and nonlinear control methods were compared for the buck and
boost converters. For the buck converter, linear and nonlinear control methods obtained
similar experimental results. While for the boost converter, there was a clear difference
between the results from the linear and nonlinear control methods. Nonlinear control
methods obtained more satisfactory responses for the boost converter.
Several areas for future research are possible. Fuzzy control for DCDC
converters could continue to be investigated. It is interesting to see how the fuzzy
controller will respond to a large variation of input voltage, and if it can be modified for
large line disturbances. Adaptive fuzzy controllers could be investigated. In order to
obtain both fast transient response and stable steadystate response, the gains and rule
table of the fuzzy controller could be switched between transient and steady state.
Other nonlinear control methods such as neural network, genetic algorithm and
adaptive control can be applied to DCDC converters. Neural networks have learning and
selforganizing abilities to adapt to nonlinear systems. The network can be trained on
typical signals and then tested on an experimental testbed. Simulation results may be
compared with experimental results for DCDC converters.
Digital currentmode control could also be investigated. Currentmode control is
typically a two loop system: an inner current loop and outside voltage loop. The
dynamics of the voltage loop are much slower than that of the current loop. Therefore
voltage loop can be easily implemented using digital signal processors (DSP) or
microcontrollers. However, it is quite challenging to implement digital control for the
current loop due to delay of the sampling and computation process. To solve this
problem, the inductor current was estimated to achieve predictive digital currentmode
107
control [51]. With the advance of VLSI technology, DSPs with faster clock frequency
and analogtodigital converters are becoming available. Therefore, it would be
interesting to investigate digital currentmode control that uses directly measured
inductor current values. Sampling algorithms may be developed in order to obtain values
of inductor current in real time.
Another research issue is related to the efficiency of the converters. Since
intelligence can be conveniently included in DSPs, the converter can be controlled in such a
way that optimum efficiency is achieved under various operating points. The operating mode
can also be shifted between continuous mode and discontinuous mode by changing the
switching frequency. In addition, a digital controller could monitor the temperature of
different parts of the converter to perform thermal management. Functions of control
regulation, thermal management and supervision can all be integrated on a single DSP chip.
The advantage is tremendous over analog control.
It will also be interesting to investigate digital control of transformer isolated
converters, such as forward converters, flyback converters and pushpull converters.
Implementation issues of digital controllers may be investigated. Besides DSPs, FPGAs
and custom designed integrated circuits are also viable solutions for the implementation
of digital controllers. FPGAs tend to be more flexible than DSPs because the user is able
to specify their size, speed and price. Nowadays many FPGAs also have builtin DSP
function in order to improve their computation capability. Digital controllers may be
implemented on both FPGAs and DSPs in order to compare the advantage and
disadvantage of each implementation method.
108
To summarize, several issues in digital control may be investigated in the future.
In the past, research in digital control was mainly conducted in universities and research
institutes. In the recent years, there are rapidly increasing interests in digital control from
the industry in order to achieve small space and high efficiency in DCDC converters.
Therefore, collaboration between the academia and the industry could achieve
tremendous development and application of digital control in the future.
109
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DESIGN AND IMPLEMENTATION OF DIGITAL CONTROLLERS FOR BUCK AND BOOST CONVERTERS USING LINEAR AND NONLINEAR CONTROL METHODS Liping Guo
A Dissertation Submitted to the Graduate Faculty of Auburn University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy
Auburn, Alabama August 7, 2006
DESIGN AND IMPLEMENTATION OF DIGITAL CONTROLLERS FOR BUCK AND BOOST CONVERTERS USING LINEAR AND NONLINEAR CONTROL METHODS
Liping Guo
Permission is granted to Auburn University to make copies of this dissertation at its discretion, upon request of individuals or institutions and at their expense. The author reserves all publication rights.
______________________________ Signature of Author
______________________________ Date of Graduation
iii
on August 8. in Beijing. and graduated with a Bachelor of Science degree in Automatic Control in July. 1999. in September.VITA Liping Guo. 2001. After working as an associate engineer in Beijing City Commercial Bank for one year. 1974. she entered Graduate School. China. P. R. daughter of Zongyang Guo and Shuxian Xu. Auburn University. 2000. She attended Beijing Institute of Technology in Beijing. She graduated Phi Kappa Phi with a Master of Science degree in Electrical and Computer Engineering in August. 1997. She married Kezhou Wang. and as a system engineer in Beijing HKD Computer Co. was born on June 20. son of Shixue Wang and Yulan Ma in Beijing. Ltd for another year. iv .
Auburn University. Nelms Issues in the design and implementation of digital controllers for a buck converter and a boost converter using linear and nonlinear control methods were investigated in this dissertation. 2006 (M. Since the linear controllers were designed based on the small signal v .DISSERTATION ABSTRACT DESIGN AND IMPLEMENTATION OF DIGITAL CONTROLLERS FOR BUCK AND BOOST CONVERTERS USING LINEAR AND NONLINEAR CONTROL METHODS Liping Guo Doctor of Philosophy. M. The small signal models of the buck and boost converters. 2001) (B.. Analog PID and PI controllers were designed for generic buck and boost converters using standard frequency response techniques. were utilized in the dissertation. 1997) 128 Typed Pages Directed by R.S. August 7. The controllers were then transformed into digital controllers. The small signal models of the converters change with the variations of the operating point.S.. Beijing Institute of Technology. obtained using standard state space averaging techniques.
nonlinear control methods were applied to the buck and boost converters. Fuzzy controllers were designed for the buck and boost converters. The sliding mode fuzzy controller combined the advantages of both fuzzy controllers and sliding mode controllers. The digital controllers designed using linear and nonlinear control methods were implemented on a TI DSP. and both structures were applied to the boost converter to obtain satisfactory response. Since fuzzy controllers don’t require a precise mathematical model. Experimental results verify that nonlinear controllers have superior performance over linear controllers under the change of operating points.models. Experimental results for the buck and boost converters were presented and compared. they are well suited to nonlinear. timevariant systems. they were not able to respond effectively to changes in operating point. Sliding mode fuzzy controllers are designed for the boost converter. Two structures of fuzzy controllers are investigated in this dissertation. Only one structure was applied to the buck converter. The second nonlinear control method investigated in this dissertation was sliding mode fuzzy controller. vi . To achieve a stable and fast response.
R. Nelson for many insightful suggestions which they have offered. support and encouragement while pursuing her course of study. The author would like to thank Dr. Finally. and the Center’s industrial partners. Victor P. Auburn University.ACKNOWLEDGEMENTS This research was supported by the Center for Space Power and Advanced Electronics with funds from NASA grant NCC3511. vii . Nelms most deeply for his guidance through her graduate studies. Hung and Dr. the author would like to extend her heartfelt gratitude to her parents and her husband for their love. John Y. M. The author wishes to thank her major professor Dr.
0 Visio ® 2000 for Microsoft Windows TI C2000 Code Composer Studio IDE Acrobat Distiller 4.Style Manual or Journal Used: Bibliography conforms to those in the Institute of Electrical and Electronics Engineers Transactions on Power Electronics Computer Software Used: Microsoft ® Windows XP Operating Systems Microsoft ® Word 2002 Microsoft ® Excel 2002 MATLAB ® Version 6.5 Simulink Version 5.0 viii .
................................2 Boost Converter .........................................................................2......................................................................... 1 1....1......................... 4 1..........................................................2 TMS320F2812 DSP Evaluation Module .............1 Buck Converter .....2........... 6 2 EXPERIMENTAL TESTBED .....................3.........................................................................................................2 Memory Map ........................................ 19 2.1.............2.............................................. 23 2.............2 Boost Converters.............................2........................................1 PID Controller Design for Buck Converters.......................................... 14 2..............1..........1 Hardware................................ 2 1..................1 Buck Converters.......... 44 3...............2... 5 1........................3 Transformation from an Analog Controller to a Digital Controller ......................................1 TMS320F2812 Overview ...........................................1...........2 PI Controller Design for Buck Converters....................... 43 3....................... 25 3 LINEAR CONTROL DESIGN FOR DCDC CONVERTERS.....................1 Program Structure ........................................................................................2................................................................................ 43 3......................................3 Implementation of Digital Controllers.........2 Boost Converters...............2.............. 30 3.................................................................. 19 2...............................................3 Literature Review.................................................. 31 3......5 Interrupts ..................2.......................... xv 1 INTRODUCTION ...................................... 2 1.... xi LIST OF TABLES....2................................................................................ 18 2........................................................................ 46 ix ..........2............................................3 AnalogtoDigital Converter Module ...........................................................................................1 StateSpace Averaged Model for DCDC Converters ..........................................................................................2................6 Code Development Tool .......................... 45 3.........2...................................................................2 Control of DCDC Converters .....................................................................1 PID Controller Design for Boost Converters............................1 SwitchMode DCDC Converters......1...... 44 3................... 34 3.......... 42 3............. 37 3............................2 PI Controller Design for Boost Converters................................2 Digital Controller Design for DCDC Converters Using Frequency Response Techniques ..4 Event Manager Module............................ 40 3......................................... 41 3.................................2...1............................................ 18 2.......................2........... 14 2..............................................TABLE OF CONTENTS LIST OF FIGURES ..........................................................1 Buck Converters........2......................... 29 3......................................................... 21 2.......
...................................2 Rule Base ........................................................ 79 6..............................................................................4 Comparison of Experimental Results of Linear and Nonlinear Control Methods.................. 72 5.3 Rule Base ............................................1 Buck Converter .........1.................................. 69 5..............3.......... 81 6.................... 104 BIBLIOGRAPHY...........................1 Boost Converter .............................................. 57 4...................................................................................1 Switching Functions . 77 6 EXPERIMENTAL RESULTS..........3 Experimental Results for Sliding Mode Fuzzy Controllers.......................3.......... 82 6.............................2 Boost Converter . 48 4 FUZZY CONTROLLER DESIGN FOR DCDC CONVERTERS ..................... 102 7 CONCLUSION AND FUTURE WORK ...............1 Introduction to Fuzzy Control..............2 Inputs and Their Scaling Factors ......... 95 6.................................2 Implementation of Sliding Mode Fuzzy Controller...... 68 5............................................ 95 6.........2 Fuzzy Control Design for DCDC Converters.............................................................................................................................................................................................. 90 6..........1...................1 Buck Converter .................................................................................................................................................................................1..........4 Defuzzification........................................1 Buck Converter ............ 90 6................................................. 79 6....................................................................1 Design of Sliding Mode Fuzzy Controller for DCDC Converters ..........................4 Inference Mechanism and Defuzzification Method................................................. 54 4...1 Experimental Results for PID and PI Controllers...........1...................................................2 Implementation of Digital PID and PI Controllers ..................................................................................................... 86 6.................................................2... 79 6....................................................2 Boost Converter .......................................................................................1 Fuzzification ...4........................................................... 92 6.. 109 x ...........2 Buck Converter .2.................. 60 4............................................................. 74 5......... 59 4.............................3... 60 5 SLIDING MODE FUZZY CONTROLLER DESIGN FOR DCDC CONVERTERS 66 5........1.................2............................1......................................... 82 6...2..........4.......................3 Implementation of Fuzzy Controllers .........3 Inference Mechanism...........2. 52 4............................................. 53 4................2 Experimental Results for Fuzzy Controllers......2......................................2 Boost Converter .......... 59 4.............. 76 5....................................................................3....
................................................................................. 27 3....................................................5 Boost converter ...............4 Equivalent circuit of the buck converter when the switch is open ................1 Buck Converter .............1 Bode plot of the statespace averaged model of the buck converter........3 Functional diagram of HCPL3180 high speed gate drive optocoupler ........................................................... 4 1. 33 3.......................................... 3 1................. 4 1......................7 Equivalent circuit of the boost converter when the switch is open...........................6 Equivalent circuit of the boost converter when the switch is closed ......... 26 2.................. 5 1.................................................................................... 3 1....2 Circuit schematic of digital control system of the boost converter ...............LIST OF FIGURES 1............. 17 2....... 15 2........................... 36 3.................. 20 2..................................6 Flow chart for code development in CCStudio IDE..............................................3 Bode plot of the statespace averaged model of the boost converter.....4 Comparison of the actual and theoretical frequency response of the boost converter36 3....... 33 3..2 PWM signal to control the switches in the DCDC converters ............5 Comparison of the frequency response obtained using the analog analyzer and from the generated transfer function..... 37 xi .......3 Equivalent circuit of the buck converter when the switch is closed ................ 15 2.................................... 5 2..................4 F2812 memory map . 5 1.................................5 Flowchart of the operation for CPU maskable interrupts ........1 Circuit schematic of digital control system of the buck converter .......2 Frequency response of the buck converter obtained by the analog analyzer....................
....................7 Bode plot of PI controller compensated buck converter...............................1 Start up transient response of the buck converter using the linear PID and PI control method........ 58 4..6 Bode plot of PID controller compensated buck converter........................................... 80 xii .......................................... 51 4............................... 49 3................)............ 56 4.........................3 Simulink model of the fuzzy controller with a linear integrator for the DCDC converters Method 2:(d[k] = KI*I[k]+h*δd[k])..... 54 4.............................. 71 5..............................................6 Flowchart of fuzzy controller using method 1................................ 73 5................... 44 3................3....................................7 Flowchart of fuzzy controller with a linear integrator ...........1 Block diagram of fuzzy control system ...................4 Membership functions of the inputs e[k] and ce[k] for the buck converter ............ 47 3......................... 58 4......... 42 3............................................................................... 75 5....................6 Simulink model of the system using sliding mode fuzzy controller for the DCDC converters............. 71 5......11 Block diagram of digital PID controller .......................................2 Simulink model of the fuzzy controller for the DCDC converters Method 1: (d[k] = d[k1]+h*δd[k]........................8 Bode plot of PID controller compensated boost converter..............5 Membership functions of the inputs e[k] and ce[k] for the boost converter ............................................................... 43 3............................................................................................................. 57 4..........................................2 Step response of the switching function for boost converter..........3 Step response of switching function for buck converter.12 Flowchart of digital PID and PI controller .5 Function between ci and s(x) ...............................9 Bode plot of PI controller compensated boost converter..........................................10 Overview of the program structure for digital controllers .... 78 6........ 72 5.............................1 Switching function of the sliding mode fuzzy controller for boost converter ....................................... 62 5... 41 3................................................................................ 61 4.......4 Membership functions of the inputs e[k] and ce[k] for the boost converter .........................
..................... 85 6................................ 95 xiii ......364 A to 0... 91 6.............16 Load transient response of the buck converter using sliding mode fuzzy controller when the load changed from 0.......6 Transient response for the buck converter using the second fuzzy control method with 17*17 rule base when the load changed from 1............ 91 6....24 A to 0..............................................15 Load transient response of the buck converter using sliding mode fuzzy controller when the load changed from 0.13 Start up transient response of the buck converter using sliding mode fuzzy controller with different input voltage ...9 Start up transient response of the boost converter using the second fuzzy control method.......16 A...................................................................24 A to 0...4 Transient response for the boost converter using the linear PID and PI control method when the load changed from 0........96 A to 0......48 A .................7 Start up transient response of the buck converter using the second fuzzy control method with 7*7 rule base ............................................. 81 6........ 94 6..................... 94 6.................................................24 A to 0..... 80 6.........................16 A..8 Transient response for the buck converter using the second fuzzy control method with 7*7 rule base when the load changed from 1..................................................11 Start up transient response of the boost converter using sliding mode fuzzy control with different input voltage........... 85 6...............48 A to 0..............364 A to 0.................................16 A ..................5 Start up transient response of the buck converter using the second fuzzy control method with 17*17 rule base ..........96 A with different input voltage ...14 Steadystate response of the buck converter with the PWM signal................. 87 6........364 A to 0...........48 A ........... 82 6...... 86 6............2 Transient response for the buck converter using the linear PID and PI control method when the load changed from 1.................... 93 6..........48 A ................................................................. 89 6...................................................................................6...................................................................................................... 84 6....12 Transient response of the boost converter using sliding mode fuzzy control when the load current changed from 0..10 Transient response for the boost converter using the first fuzzy control method when the load changed from 0....48 A with different input voltage .....3 Start up transient response of the boost converter using the linear PID and PI control method...........................................................................................
.......................96 A to 0...................18 Load transient response using ordinary fuzzy controller when the load changed from 0............96A to 0.................48 A with different input voltage.....................96 A with different input voltage.........................................................................17 Start up transient response of the buck converter using ordinary fuzzy controller with different input voltage......... 99 6..................22 Load transient response using PID/PI controller when the load changed from 0...............21 Load transient response using PID/PI controller when the load changed from 0...................48A with different input voltage . 97 6.....................................96 A with different input voltage ...................... 99 6....................... 96 6......................19 Load transient response using ordinary fuzzy controller when the load changed from 0...............20 Start up transient response of the buck converter using PID/PI controller with different input voltage............ 97 6.............................................................48 A to 0..............48 A to 0......................6.......... 100 xiv ......................
.......LIST OF TABLES 2............... 101 6.................................................. 22 5...2 Comparison of Performance of PID Control.........1 Comparison of Performance of Sliding Mode Fuzzy Control vs.......... Ordinary Fuzzy Control vs......... and Sliding Mode Fuzzy Control for the Boost Converter ............ 76 6..... PID/PI Control for Buck Converter ............ Fuzzy Control. 103 xv ..1 7×7 Rule base of the sliding mode fuzzy controller ..................................1 Configuration of eventmanager modules EVA and EVB ............................................................................
Most of the other topologies are either buckderived or boostderived converters. DSPs have more computational power than microcontrollers. switching power supplies provide much more efficiency and power density. are used for energy transfer and work as a lowpass filter. 1 . Traditionally. In the recent years. because their topologies are equivalent to the buck or the boost converters. technology advances in verylargescale integration (VLSI) have made digital control of DCDC converters with microcontrollers and digital signal processors (DSP) possible. Generally. increased flexibility by changing the software. including capacitors and inductors. Switching power supplies employ solidstate devices such as transistors and diodes to operate as a switch: either completely on or completely off. the control methodology for DCDC converters has been analog control. more advanced control techniques and shorter design cycles.CHAPTER 1 INTRODUCTION Switch mode DCDC converters efficiently convert an unregulated DC input voltage into a regulated DC output voltage. more advanced control algorithms can be implemented on a DSP. Compared to linear power supplies. Energy storage elements. Therefore. The buck converter and the boost converter are the two fundamental topologies of switch mode DCDC converters. The major advantages of digital control over analog control are higher immunity to environmental changes such as temperature and aging of components.
the inductor current falls to zero during the time the switch is turned off. The current flowing through the inductor never falls to zero in the continuous mode. 1. T The corresponding PWM signal is shown in Figure 1. buckboost converters.1. The ratio of the ON time ( tON ) when the switch is closed to the entire switching period (T) is defined as the duty cycle D = tON . Switchmode DCDC converters include buck converters.1 Buck Converter The buck converter. In the discontinuous mode.2 [1]. Only operation in the continuous mode is considered in this dissertation. Both the buckboost and Cuk converters are combinations of the two basic topologies.1.1. the buck converter and the boost converter are the basic topologies. There are usually two modes of operation for DCDC converters: continuous and discontinuous. converts the unregulated source voltage Vin into a lower output voltage Vout. Cuk converters and fullbridge converters. 2 . boost converters. etc. The fullbridge converter is derived from the buck converter. The NPN transistor shown in Figure 1. shown in Figure 1.1 SwitchMode DCDC Converters Switchmode DCDC converters are used to convert the unregulated DC input to a controlled DC output at a desired voltage level. Among these converters.1 works as a switch.
the ratio of output voltage over input voltage is D.3 is valid when the switch is closed. During steady state.1) 3 . When the switch is open as shown in Figure 1. Vout =D Vin (1. the capacitor supplies energy to the load. capacitor and the load.2 PWM signal to control the switches in the DCDC converters The equivalent circuit in Figure 1. the diode conducts. The diode is reverse biased. and the inductor current flows through the capacitor and the diode [2].1).4.1 Buck Converter Switching Period (T) tON Figure 1. and the input voltage supplies energy to the inductor. The output voltage is controlled by varying the duty cycle. which is given by (1.iin + Vin Gate Drive Diode Inductor + Capacitor Load Vout _ Figure 1.
4 Equivalent circuit of the buck converter when the switch is open 1. converts an unregulated source voltage Vin into a higher regulated load voltage Vout. the diode conducts and both energy from the input voltage and energy stored in the inductor are supplied to the capacitor and the load.7.2). shown in Figure 1.iin + Vin  Inductor + Capacitor Load Vout  Figure 1.6. When the switch is opened as shown in Figure 1. During steady state operation.1. thus the output voltage is higher than the input voltage [3]. the ratio between the output and input voltage is 1 . The output 1− D voltage is controlled by varying the duty cycle.2 Boost Converter The boost converter.5. the diode is reverse biased and the input voltage supplies energy to the inductor while the capacitor discharges into the load. When the switch is closed as shown in Figure 1.3 Equivalent circuit of the buck converter when the switch is closed Inductor + Capacitor Load Vout _ Figure 1. which is given in (1. 4 .
2) The output voltage of the switchmode DCDC converters are regulated to be within a specified range in response to changes in the input voltage and the load current.5 Boost converter Inductor + Vin Capacitor Load + Vout _ Figure 1.6 Equivalent circuit of the boost converter when the switch is closed Inductor + Vin Capacitor Load + Vout _ Figure 1.Inductor Diode + Vin  Gate Drive + Capacitor Load Vout _ Figure 1.2 Control of DCDC Converters (1.7 Equivalent circuit of the boost converter when the switch is open Vout 1 = Vin 1 − D 1. 5 .
the control algorithm is implemented on a microcontroller or DSP. Current mode control for a DCDC converter is a twoloop system. then a compensator is designed based on the small signal model. An additional inner current loop is added to the voltage loop. Experimental results for the controllers have been evaluated and compared for prototype buck and boost converters. The duty cycle is adjusted based on the error signal to make the output voltage follow the reference value.3 Literature Review The research problem addressed in this dissertation is the design and implementation of digital controllers for buck and boost converters on a DSP using linear and nonlinear control methods. Frequency response methods are usually used in the design of voltage mode controllers for DCDC converters. Digital controllers were implemented on a TI DSP. phaselag compensator and leadlag compensator.There are two control methods for DCDC converters: voltage mode control and current mode control [2]. Small signal models of the converters are first obtained by linearizing the power stage of the converters around an operating point. In voltage mode control. The reference value for the inductor current is generated by the voltage loop. The current loop monitors the inductor current and compares it with its reference value. In analog control. In digital control. 6 . the compensators are implemented using operational amplifiers and appropriate values of resistors and capacitors to obtain the desired transfer function. Typical compensators include phaselead compensator. 1. the converter’s output voltage is compared with a reference to generate the voltage error signal.
Vallittu. In the direct design approach. and computer systems are all needed to conduct research in digital control of DCDC converters. Backward integration methods were suggested to be a better discretization method for the indirect design approach. Suntio and Ovaska studied the opportunities and constraints of digital control of power supplies. Bibian and Jin from the University of British Columbia studied two prediction techniques for the compensation of digital control time delay in DCDC converters. The methods include direct and indirect design approaches. and then converted into digital controllers. The small signal models of buck and boost converters are obtained 7 . Theory in the areas of power electronics. Duan and Jin from University of British Columbia made a thorough evaluation of different digital control design methods for DCDC converters [4]. The best approach is determined based on a comparison of experimental results. Modified predictor and simplified predictor were developed to increase the bandwidth of the control loop [5]. Linear controller design methods mainly include frequency response and root locus techniques [7]. The advantages and disadvantages of analog and digital control of power supplies were compared in [6]. systems and control. small signal models of the converters are first converted into discretetime models.Digital control for DCDC converters is theoretically interesting because it is a multidisciplinary research. It was concluded that the direct design approach is better than an indirect design approach. The increasing interest in digital control of switch mode power supplies is shown in international conference proceedings and journal publications in the past few years. analog controllers are first designed based on the small signal models of the converters. In the indirect design approach. and digital controllers are directly designed based on the discretetime models.
there are two possible solutions. 3]. One is to develop a more accurate model for the converter. the model may be too complex to use in controller development. In this dissertation. while only the magnitude of the buck converter’s small signal model shifts with the change of operating point [3]. The analog plant consists of the buck converter’s model. analog PID and PI controllers were first designed using standard frequency response techniques based on the small signal model of the converters. Linear controllers are designed using frequency response techniques and root locus techniques.using standard state space averaging techniques [2. nonlinear controllers were designed and implemented for the converters. To achieve a stable and fast response under varying operating points. After designing and implementing linear controllers for the buck and boost converters. A second solution is to use a nonlinear controller [9]. the small signal models are first transformed into discretetime models. The linear controllers were designed only for the nominal operating point. When using the root locus techniques. The boost converter’s small signal model is a nonlinear function of the operating point. and then a digital controller was directly designed. The analog plant was transformed into a discretetime transfer function. The small signal models for the converters change due to variations in operating point. A digital controller was designed for a buck converter based on root locus techniques in [8]. However. and the A/D converter. Digital controllers are then designed based on the discretetime models using the root locus method. 8 . The analog controllers were then transformed into digital controllers. the pulse width modulator.
Butkiewicz investigated steadystate error of a system with fuzzy controllers [12]. The fuzzy controller improved performance in terms of overshoot limitations and sensitivity to parameter variations compared to standard controllers. The small signal model for the converters and linear design techniques were used in the initial stages of fuzzy controller design. Since a fuzzy controller is a nonlinear controller. while the fuzzy 9 . The controller is then tuned using a trial and error method to obtain satisfactory response. Srinivasan and Oruganti studied the development of a universal fuzzy controller for a boost converter [9]. Fuzzy controllers are designed based on the general knowledge of the converters. Perry and Sen proposed a design procedure that integrated linear control techniques with fuzzy logic [11]. the most popular and widely used technique in control systems is fuzzy control [9]. boost and buckboost converters [13]. The performance of the fuzzy controller was superior to the performance of the PI controller. Many researchers have investigated fuzzy controllers for DCDC converters. Viswanathan.Among the various techniques of artificial intelligence. It was concluded from the comparison of startup responses and load regulation tests that the currentmode controlled buck converter had a faster transient response and better load regulation. Simulation results were compared with the results of a PI controller under varying operating points. it can adapt to a varying operating point. Simulation and experimental results were presented and compared with results of a digital PI controller. Mattevelli and Spiazzi investigated a generalpurpose fuzzy controller for DCDC converters [10]. Simulation results for buckboost and Sepic converters were presented. Wang and Lee designed a fuzzy controller for basic DCDC converters and then compared the computer simulation results with those for currentmode control in buck.
This design procedure can be applied to other converter topologies.19].18. The bias and limit cycles were difficult to predict because of the nonlinear nature of the both quantization and fuzzy controllers. The control rules were derived from analysis of the system dynamics in the state plane. and have not been verified by experimental results. A. This technique facilitated theoretical design and analysis of fuzzy controllers. Simulation results for the boost converter were presented in order to validate the considerations. membership function errors and arithmetic errors. Campo and Tarela investigated the consequences of the finite word length on the performance of a digital fuzzy logic controller [16]. Simulation results showed that bias and limit cycles were generated due to the quantization. J. In this dissertation. while for the boost converter. et al. Arias. et al. only the second method was applied to the buck converter to obtain satisfactory response. a combination of both methods was applied to obtain the desired response. Scaling factors boundaries were established to avoid oscillatory behavior in the system. In this dissertation. Two structures of fuzzy controllers have been studied. applied the describing function techniques to a tworule fuzzy controller for boost converters [15]. 10 . experimental results of the fuzzy controllers for buck and boost converters have been obtained and compared with the results for linear controllers.controller for both boost and buckboost converters had less steadystate error and better transient response. The first structure is more prevalently used than the second structure [17. Many studies of fuzzy controllers for DCDC converters have only been supported by simulation results. proposed a design procedure for a fuzzy logic controller for a buck converter [14]. Gomariz. Arias. There were three types of error as a result of the finite word length: AD conversion errors. Guinjoan.
VidalIdiarte. The controllers were simulated. Fundamental theory. MartinezSalamero. The sliding mode can be entirely independent of the effects of modeling uncertainties. boost. buckboost and Cuk converters based on the statespaceaveraging method [21]. proof of the existence condition of the sliding mode and stability conditions. and satisfactory simulation results were obtained. Cortes and Alvarez investigated several sliding surface designs for boost converters [22]. presented a twoloop control for a boost converter [23]. Shi and Sen conducted a study of different types of PIDlike fuzzy logic controllers for application to DCDC converters [25]. parameter fluctuations and disturbances. Raviraj and Sen performed a comparative evaluation of the PI. Mahdavi. The outer loop used a fuzzy controller to implement the voltage loop. An inner loop controlled the inductor current using sliding mode control. Hung. Simulation results were presented. et al. Gao and Hung had a very thorough tutorial about variable structure control with sliding mode [20]. sliding mode and fuzzy logic controllers 11 .Sliding mode control of DCDC converters has been widely investigated by researchers [2033]. The analysis included the reaching condition. main results and practical applications of sliding mode control were introduced. The controller implementation used analog components for the inner loop and an 8bit microcontroller for the outer loop. They proposed sliding surfaces that do not depend on the load to eliminate the necessity for current measurement. Sliding mode control is a powerful method that can yield a very robust closedloop system under plant uncertainties and external disturbances. Orosco and Vazquez analyzed discrete sliding mode control for DCDC converters [24]. A sliding mode is achieved by forcing the system trajectory on a properly designed switching function using high speed switch control. Emadi and Toliyat designed sliding mode controllers for buck.
In this dissertation. and only simulation results have been presented. Kuisma et al. presented implementation of a sliding mode controller for a buck converter [26]. Because infinitely fast switching of the control action is impossible in practice. a sliding mode fuzzy controller was proposed to control a DCDC boost converter. It is more robust than an ordinary sliding mode controller. The sliding mode fuzzy control has advantages of its own that cope with the problems in the sliding mode control and fuzzy control design and implementation. In Chapter 3. 16 channel ADC. All the digital controllers discussed here were implemented on a TI TMS320F2812 DSP. The sliding surface in a sliding mode fuzzy controller is rendered by rule bases and scaling factors. The clock frequency is 150 MHz. rather than a function. A constant switching frequency can’t be guaranteed. chattering always occurs in steady state. Furthermore. The F2812 DSP is a 32bit. digital controllers are designed for DCDC converters using linear control methods. Described in Chapter 2 of this dissertation is the experimental testbed including hardware configuration and main features of the DSP controller from Texas Instruments. It supports peripherals used for embedded control applications. Ahmed. The sliding mode fuzzy controller combines the advantages of both fuzzy controllers and sliding mode controllers [34].for application to DCDC converters. fixed point DSP. such as event manager modules for PWM output and a dual 12bit. This issue has prevented sliding mode control from being extensively applied to DCDC converters. several disadvantages exist for sliding mode control. Most research on sliding mode controllers for DCDC converters has been limited to continuous time. Frequency response techniques are applied to design digital controllers for the 12 .
The transformation from analog controller to digital controller and implementation of digital controllers are also discussed in Chapter 3. In Chapter 7. Design and implementation of sliding mode fuzzy controllers is presented in Chapter 5. The design and implementation of fuzzy controllers for DCDC converters is discussed in Chapter 4. the research is summarized and suggestions for future work are made.buck and boost converters. Laboratory results for the buck and the boost converters are presented and compared in Chapter 6. 13 .
1 and Figure 2. The buck converter block is the common topology of the buck converter. the input to the ADC. In the first section of this chapter. It consists of the source voltage. The ESR is estimated to be 30 mΩ [18. two input filter capacitors (470 µF and 0. The total value of the output capacitor C is 1000 µF. a MOSFET (IRFZ34N) as the switching device. Described in this chapter are the hardware components. 14 . The output capacitors are made of four capacitors in parallel to reduce the equivalent series resistance (ESR).2. the hardware configuration of the experimental testbed is described. including the DCDC converters.19].47 µF).CHAPTER 2 EXPERIMENTAL TESTBED Implementation of digital controllers for the buck and the boost converters required both hardware and software. output capacitors and a load resistor of 10 Ω. The control algorithms of linear and nonlinear controllers were all implemented on the TI DSP. the digital signal processor (DSP) and the gate drive. the gate drive and the digital signal processor (DSP). In the second section of this chapter. detailed information about the Texas Instrument DSP is presented.1 Hardware The complete circuit schematics of the digital control system of the buck and boost converters are shown in Figure 2. The schematics can be divided into four functional blocks: the DCDC converter. 2. a fast recovery diode (MBR3045PT). respectively.
5uF 51 Ohm 4 NC Figure 2.3V 150 Ohm HCPL3180 Vcc 8 Vo 7 TMS320F2812 T2PWM GND ADCINA3 GNDA VCC 1 NC 2 ANODE 1.2 Circuit schematic of digital control system of the boost converter 15 .3 KOhm 8.2 KOhm MM74HC04 3 CATHODE Vo 6 GND 5 DC 15V 0.5uF 51 Ohm GNDA VCC 4 NC Figure 2.2 KOhm MM74HC04 3 CATHODE Vo 6 GND 5 DC 15V 0.3 KOhm 8.Buck Converter IRFZ34N L=150uH Input to ADC 56 KOhm Vin=20V 470uF 0.47uF MBR3045PT 470uF 330uF 100uF Load= 100uF 10 Ohm 10KOhm 3V OP184F Gate Drive Digital Signal Processor 3.1 Circuit schematic of digital control system of the buck converter Boost Converter L=260uH MBR1545CT Input to ADC 47KOhm 220uF Vin=5V IRFZ14N 0.1uF 330uF 330uF 330uF 33uF 33uF Load= 25 Ohm 10KOhm 3V OP184F Gate Drive Digital Signal Processor 3.3V 150 Ohm HCPL3180 Vcc 8 Vo 7 TMS320F2812 T2PWM GND ADCINA3 1 NC 2 ANODE 1.
0 A maximum peak output current. but the output voltage of the buck converter is targeted at 12 V. and thus limited to be under 3 V before it is 6.6 applied to the ADC. The gate is voltage controlled. The switch will be on when gatetosource voltage VGS is greater than the threshold voltage Vth. a higher VGS is more applicable in the converter design. and off when VGS is less than Vth. an optocoupler was used to isolate the gate drive’s ground from the circuit’s common ground. Generally. It features 2. In a practical gate drive design.The input to the analog to digital converter is connected to a voltage divider and a unity gain buffer. the output of the op amp will be less than or equal to 3 V. Vth is about 2 to 4 V. the ground of the gate drive should be floating to avoid a short circuit. wide operating temperature range of 40 oCto 100 oC. The operational amplifier OP184F features railtorail input and output. wide Vcc operating range of 10 V to 20 V and 20 ns typical pulse width distortion. The ADC of the DSP is able to receive an input voltage as high as 3 V. The third block is the gate drive. The HCPL3180 is an optocoupler integrated with a high speed gate drive. The MOSFET requires proper external gate signals for turnon and turnoff. The function of the unity gain buffer is protection for the ADC. To achieve this. an HCPL3180 high speed gate drive optocoupler from Agilent Technologies was used. 200 ns maximum propagation delay. It is well suited to supply high frequency gate signals for the MOSFETs and IGBTs used in high performance DCDC converters 16 . Since the voltage supply for the operational amplifier is 3 V.1. 250 kHz maximum switching speed. As is shown in the gate drive block in Figure 2. In the buck converter. The output voltage of the buck converter is divided by the ratio of 1 .
17 . Figure 2.3 Functional diagram of HCPL3180 high speed gate drive optocoupler In Figure 2. The block includes the source voltage. an output capacitor and a load resistor of 25 Ω. It is very small compared to the switching period of 6.2.67 µs. a MOSFET (IRFZ14N) as the switching device. a CMOS inverter MM74HC04 serves as an interface between the DSP and the optocoupler. the block for the boost converter is a generic boost converter. two input filter capacitors (220 µF and 0.3 [35]. The LED across pins 2 and 3 is optically coupled to an integrated circuit with a power stage. The total value of the capacitors is 1056 µF. The MM74HC04 has a typical propagation delay of only 8 ns.1 µF).1. The output capacitor C is made of five capacitors in parallel to reduce the ESR. In the digital control system of the boost converter shown in Figure 2. The functional diagram of the HCPL3180 is shown in Figure 2. Details about the TMS320F2812 DSP controller will be presented in the next section. a fast recovery diode (MBR1545CT). at the input of the HCPL3180.and switching power supply applications.
The TMS320F2812 DSP controller comes in a 176 pin package. which is the newest member of the TMS320C2000TM DSP platform. The F2812 supports the peripherals used for embedded control and communication. By integrating the DSP core and onchip peripherals. The TMS320C2000TM DSP platform is optimized for control applications.2. ADC inputs. compare signals. It targets a wide variety of digital control applications including industrial control. serial communication interface. . the TMS320C5000TM DSP. 16channel analogtodigital converter (ADC). motor control and automobile control applications. bit I/O and shared functions bits. The pins can be categorized according to function: address and data bus. interrupts signals. clock signals and test signals. is composed of fixed point. and the TMS320C2000TM DSP.2. produced by Texas Instruments. 18 . interface control signals. floating point and multiprocessor DSPs.2 TMS320F2812 DSP Evaluation Module The TMS320 family of digital signal processors (DSP). such as an event manager module for pulsewidthmodulation (PWM) and a dual 12bit. The CPU operates at 150 MHz. The TMS320F2812 DSP belongs to the TMS320C28x generation. hence enabling control algorithms to be developed in high level languages. The TMS320 family has three DSP platforms: the TMS320C6000TM DSP. The C28x DSP generation is efficient in executing C and C++ programs. the TMS320C28x DSP generation offers a highperformance solution to digital control. 2.1 TMS320F2812 Overview The TMS320F2812 is a 32bit fixed point DSP controller with onboard flash memory [36].
Each of these blocks is 1K words in size.2 Memory Map The C28x uses 32bit data addresses and 22bit program addresses. Memory blocks on all C28x designs are uniformly mapped to both program and data space. H0 is a block of 8K words SARAM. Therefore. 2. The memory blocks M0 and M1 are single access onchip RAM (SARAM). The 16 channels provide multiplexed inputs to the ADC. M0 is mapped at address 00 000016 – 00 03FF16 and M1 is mapped at addresses 00 040016 – 00 07FF16. There is a block of 128K words FLASH mapped at addresses 3D 800016 – 3F 7FF816. allowing the user to perform oversampling algorithms. memory blocks can be used to execute code or for data variables. This allows for a total address reach of 4G words in data space and 4M words in program space. Autosequencing allows the system to convert the same channel multiple times. as there is only one converter in the ADC module. The channels can be configured as two independent 8channel modules or cascaded to form a 16channel module. The 12bit ADC has a builtin sampleandhold circuit. The memory map is divided into three segments: onchip program/data memory.3 AnalogtoDigital Converter Module The AnalogtoDigital Converter (ADC) module is a dual 12bit.4.2. there are five blocks of SARAM with 18K words in size. Autosequencing capability provides up to 16 autoconversions in a single session. Each conversion can be programmed to select any 1 of 16 input channels.2. In total. 16channel ADC [37]. This gives 19 . The memory map for the TMS320F2812 is shown in Figure 2.2. CPU interrupt vectors and reserved memory. L0 and L1 are two blocks of 4K words SARAM.
The conversion time is 200 ns for a single conversion and 60 ns for pipelined conversions.1) 20 .increased resolution over traditional singlesampled conversion results.4 F2812 memory map The analog input is limited from 0 to 3 V. The digital value of the ADC can be represented by (2.1). 0x00 0000 0x00 0040 0x00 0400 0x00 0800 0x00 0D00 0x00 0E00 0x00 2000 0x00 6000 0x00 7000 0x00 8000 0x00 9000 0x00 A000 Data Space Program Space M0 Vector – RAM (32x32) (Enabled if VMAP = 0) M0 SARAM (1Kx16) M1 SARAM (1Kx16) Peripheral Frame 0 (2Kx16) Reserved PIE Vector – RAM (256x16) (Enabled if VMAP=1. secure block) 128bit password H0 SARAM (8Kx16) Reserved Boot ROM (4Kx16) BROM Vector – ROM (32x32) Figure 2. secure block) Reserved 0x3D 7800 0x3D 7C00 0x3D 8000 0x3F 7FF8 0x3F 8000 0x3F A000 0x3F F000 0x3F FFC0 OTP (1Kx16. Digital value =4095 × Input Ana log Voltage − ADCLO 3 (2. ENPIE=1) Reserved Reserved Peripheral Frame1 (4Kx16) Reserved Peripheral Frame2 (4Kx16) L0 SARAM (4Kx16. secure block) Reserved (1K) FLASH (128Kx16. secure block) L1 SARAM (4Kx16. where ADCLO is the ground reference value for ADC.
The two GP timers can be used in applications such as: the generation of sampling period for digital control system. selectable internal or external input clocks.3. for reads or writes. and quadratureencoder pulse (QEP) circuits. a programmable prescaler for internal or external clock inputs. The complete configuration of the eventmanager modules EVA and EVB is shown in Table 2. a 16bit timercontrol register. TxCNT. The triggers are: (1) software immediate start. control and interrupt logic. x=3 or 4 for EVB) includes: a 16bit timer. are identical peripherals. and period interrupts. There are two GP timers in each EV module.Multiple triggers serve as sources for the start of an A/D conversion sequence. for reads or writes. providing a time base for the 21 . for reads or writes. The two EV modules. EVA and EVB. intended for multiaxis/motioncontrol applications.4 Event Manager Module The eventmanager (EV) modules provide a broad range of functions that are particularly useful in motor control and power converter control applications [38]. TxCON. timer compare. 2. a 16bit timerperiod register TxPR. (2) event manager A (multiple event sources within EVA).2. and (4) external pins. for four maskable interruptsunderflow. (3) event manager B (multiple event sources within EVB). fullcompare/PWM units. Up to eight PWM waveforms (outputs) can be generated simultaneously by each EV module: three independent pairs (six outputs) by the three full compare units with programmable deadbands and two independent PWMs.4).1. a 16bit timercompare register. for reads or writes. The EV modules include generalpurpose (GP) timers. and GP timer output pin TxCMP (x=1.2. capture units. TxCMPR. up/down counter. overflow. The GP timer x (x=1 or 2 for EVA.
Table 2. In the continuous upcounting mode. The mode of operation is determined by the bit pattern in the timer control register TxCON. and providing a time base for the capture units and the QEP units. In the stop/hold mode.1: Configuration of eventmanager modules EVA and EVB Event Manager Modules GP Timers Module GP Timer 1 GP Timer 2 Compare 1 Compare Units Compare 2 Compare 3 Capture 1 Capture Units Capture 2 Capture 3 QEP1 QEP channels QEP2 QEPI1 External Clock Inputs Direction External Clock EVA Signal T1PWM/T1CMP T2PWM/T2CMP PWM1/2 PWM3/4 PWM5/6 CAP1 CAP2 CAP3 QEP1 QEP2 CAP3 TDIRA TCLKINA Module GP Timer 3 GP Timer 4 Compare 4 Compare 5 Compare 6 Capture 4 Capture 5 Capture 6 QEP3 QEP4 QEPI2 Direction External Clock EVB Signal T3PWM/T3CMP T4PWM/T4CMP PWM7/8 PWM9/10 PWM11/12 CAP4 CAP5 CAP6 QEP3 QEP4 CAP6 TDIRB TCLKINB Each GP timer has four modes of operation: (1) stop/hold mode. (3) directional up/down counting mode.operation of compare units and PWM outputs. and (4) continuous up/down counting mode. (2) continuous upcounting mode. the GP timer stops and holds at its current value. the GP timer counts up according to 22 .
the GP timer should be in the continuous up/down counting modes. The continuous up/down counting mode is the same as the directional up/down counting mode. Each vector is a 22bit address that is the starting address for the associated interrupt service routine (ISR). The counting direction only changes from up to down when the timer reaches the period value. when the TDIRA/B input is low. the GP timer needs to operate in continuous upcounting modes. then resets to zero and continues to count up. When the value of the GP timer matches that of the compare register. and only changes from down to up when the timer reaches zero. the GP timer counts down from the period register’s value to zero. to generate a symmetric PWM signal.2. For the continuous upcounting mode. but the TDIRA/B pin has no effect on the counting direction. the length of the active phase (the output pulse width) is represented by [(TxPR) . the GP timer counts up from zero to the period register’s value. the GP timer counts up or down according to the TDIRA/B input pin. On the other hand. And. On the next rising edge of the clock. the output of the GP timer toggles.(TxCMPR) + 1] cycles of the scaled input clock. then it reloads the period’s register value and continues to count down. In the directional up/down counting mode. To generate an asymmetric PWM signal. the GP timer resets to zero and starts to count again. 39].5 Interrupts The C28x CPU supports 32 CPU interrupt vectors [38. When the TDIRA/B is held high. 23 . 2. The continuous up counting mode is very useful for the generation of edgetriggered or asymmetric PWM signals or a sampling period in a digital control system.the scaled input clock until the value of the timer counter reaches the period register’s value.
y).Maskable interrupts include INT1INT14. An interrupt can be enabled by setting the corresponding bit to 1. the interrupt enable register (IER). The maskable interrupts are supported by three dedicated registers: the interrupt flag register (IFR). The PIE block can support 96 individual interrupts that are grouped into blocks of eight.y) and enable bit (PIEIERx. The IER and DBGIER registers each contain bits to individually enable or disable a maskable interrupt. Each group is fed into one of 12 interrupt lines (INT1 to INT12).5. For multiplexed interrupt sources. The CPU then checks if the interrupt is enabled in the CPU 24 . All maskable interrupts can be globally enabled by clearing the INTM bit. Eight PIE interrupts are grouped into one CPU interrupt. or globally disabled by setting it. hardware interrupt NMI . illegalinstruction trap and hardware reset interrupt RS . there is an acknowledge bit (PIEACK) for every PIE interrupt group INT1INT12. In addition. DLOGINT and ROTSINT. The 16bit IFR contains flag bits that indicate which of the corresponding interrupts are pending. a centralized peripheral interrupt expansion (PIE) controller is used to arbitrate the interrupt requests from different resources such as peripherals and other external pins. the CPU level interrupt flag register IFR bit corresponding to INTx is set. Nonmaskable interrupts include software interrupts (INTR and TRAP instructions). The flowchart for the CPU to process maskable interrupts is shown in Figure 2. INT1INT14 are 14 generalpurpose interrupts. and the debug interrupt enable register (DBGIER). each interrupt group in the PIE block has an associated flag bit (PIEIFRx. Since the CPU does not have enough capability to respond to all peripheral requests at the CPU level. When an interrupt request is sent to the CPU.
The flowchart to develop code on the CCStudion IDE is shown in Figure 2. and the automatic context save is performed. The compiler tool includes an optimization tool that reduces the size of the C/C++ program and reduces the execution speed. The project type can be selected to be Executable (. In preparation. 25 . The optimizing C/C++ compiler translates C/C++ program into TMS320 assembly source code [41]. The CPU is then loaded with the fetched interrupt vector. INTM and DBGM are set. EALLOW and LOOP are cleared. the files of the source code. while library means that an object library will be built. The source files can be edited. debugging.lib). The code generation tools include an optimizing C/C++ compiler. Header files do not need to be added independently. Executable indicates that the project generates an executable file. an assembler. object libraries and linker command files are added to the project list. They will be automatically added when the source code is scanned for dependencies. the return address is stored.2. The CCStudio IDE includes software tools for project managing and editing. code optimization.6. built and run on the CCStudio IDE. After creating a new project.interrupt enable register IER and the global interrupt mask INTM bit. real time kernel and analysis.6 Code Development Tool The TMS320C2000 Code Composer Studio (CCS) is a Windowsbased integrated development environment (IDE). code generation. The CPU then prepares to service the interrupt.out) or Library (. a linker and utilities. 2. the corresponding CPU IFR and IER bits are cleared. A new project needs to be created first. the pipeline is flushed. and the interrupt service routine is executed.
EALLOW .5 Flowchart of the operation for CPU maskable interrupts 26 . and IDLESTAT Load PC with fetched vector Execute interrupt service routine Program continues Figure 2.Interrupt request sent to CPU Set corresponding IFR flag bit No Interrupt Enabled in IER? Yes No Interrupt Enabled by INTM bit ? Yes Clear corresponding IFR bit Empty pipeline Increment and temporarily store PC Fetch interrupt vector Increment SP by 1 Perform automatic context save Clear corresponding IER bit Set INTM and DBGM . Clear LOOP .
all the source files are compiled into a 27 . induction variable optimizations and strength reduction. reagrranging statements and expressions and allocating variables into registers. The optimization can be chosen to perform on the file level or the program level. Analyze Realtime debugging Statistics. expression simplification. The operation of optimization includes costbased register allocation. Write source code. inline expansion of runtime support library. etc. alias disambiguation.6 Flow chart for code development in CCStudio IDE The optimization tool performs such tasks as simplifying loops. Optimization on the file level only optimizes a single file. logging.Design conceptual planning Code & build Create project. Configuration file Debug Syntax Checking Probe points. data flow optimization. loop rotation and register tracking and targeting. With program level optimization. loopinvariant code motion. tracing Figure 2.
the compiler deletes the function. the compiler removes the return code in the function. if a function is not called directly or indirectly. Several optimizations are only applied in the program level. The compiler uses the module file to optimize the entire program. if a return value of a function is never used. 28 . for example. And.module file.
there was a clear discrepancy between them. The PID and PI controllers were then transformed into digital controllers using the backward integration method. In the frequency response method. An accurate model is essential to design linear controllers. Control design using frequency response techniques is presented 29 . Therefore. and for the boost converter. while for the boost converter. the measured frequency response was used for controller design. Statespace averaged models for DCDC converters are described in the first section of this chapter.CHAPTER 3 LINEAR CONTROL DESIGN FOR DCDC CONVERTERS Presented in this chapter is the control design for DCDC converters using linear control methods. The actual frequency response was also measured to compare with the small signal model. Small signal models for buck and boost converters were obtained using the standard statespace averaging techniques. analog PID and PI controllers were designed based on the converters’ small signal models [43]. the actual frequency response matches the small signal model. for the buck converter. The system was compensated to achieve high loop gain. the control design was based on the small signal model. Frequency response and root locus methods [44] may be utilized to design linear controllers. wide bandwidth and sufficient phase margin. For the buck converter.
the average equation is perturbed to produce DC and small signal terms. Fourth. and the statespace averaging method. The sets of equations are combined into a single set by summation. implementation of digital PID and PI controllers is presented. the current injected approach. The procedure to obtain a statespace averaged model is described as follows. 3. This method combines the advantage of both statespace and averaging methods. the circuit equations for each equivalent circuit are derived. In the third section of this chapter. To obtain a certain performance objective. the linear equivalent circuit for each state or switch position of the converter is drawn. the statespace averaged modeling is most widely used to model DCDC converters. First. there are three states. Nonlinear cross product terms are eliminated. It is assumed that the output filter’s cutoff frequency is much lower than the switching frequency. the small signal terms from 30 . A number of AC equivalent circuit modeling techniques have appeared in the literature. an accurate model is essential. In the continuous conduction mode. Fifth. The statespace averaged model of DCDC converters uses inductor current and capacitor voltage as two independent state variables.in the second section. Third. there are two states. Second. each set of equations is averaged by using the duty cycle of the switch as a weighting factor. It provides an accurate small signal model at relatively lower frequencies. averaged switch modeling. including circuit averaging. while in discontinuous conduction mode. It is a canonical form of writing the differential equations to describe DCDC converters.1 StateSpace Averaged Model for DCDC Converters Linear controllers for DCDC converters are often designed based on mathematical models. Among these methods.
C is the output capacitance.2): ˆ vo( s ) DR 1 + sRCC = ˆ vin( s ) R + RL 1 + s RCC + R // RL C + L + s 2 LC R + RC [ ] R + RL R + RL (3.2. ˆ vo ( s ) Vo 1 + sRCC = ˆ d ( s ) D 1 + s RCC + R // RL C + L + s 2 LC R + RC [ ] R + RL R + RL (3. Vin and Vo are the input and output voltages ˆ ˆ ˆ respectively. where these components can be found in Figures 2.1 Buck Converters The buck converter’s small signal controltooutput transfer function. RC and RL are the ESR of C and L.1. the statespace averaged model of DCDC converters is obtained. The LC magnitude falls with a slope of –40 dB/decade at the cutoff frequency. with a left half plane zero introduced by the ESR of the filter capacitance [3].1 and 2. is given by (3. Thus. L is the inductance. vin ( s ) and d ( s ) are the small variations of the output voltage. vo ( s ).1) The small signal inputtooutput transfer function is given by (3. The controltooutput transfer function is utilized to design the controller. It is a common twopole low pass filter.1). The phase 31 . The cutoff frequency of the low pass filter is ωc= 1 . derived by the standard statespace averaging technique. respectively. 3. D is the duty cycle. and R is the load resistance.step 4 are transformed into the complex frequency domain.2) In the transfer functions. input voltage and duty cycle.
respectively [18.associated with it is a –180 degree phase delay. The capacitance C is 1000 µF. Vo = 12 V. variations of D don’t change the shape of the magnitude plot of the transfer function. The model has complex conjugate poles at –615.5. and R is 10 Ω.3) The Bode plot of the transfer function is shown in Figure 3. and D = 0. When D increases. the magnitude increases. However.333 radians/s. The controltooutput transfer function at the nominal operating point is given by (3. It compares favorably with the theoretical model. L is 150 µH.2 shows the frequency response of the buck converter near the nominal operating point. 19]. This buck converter was used as a prototype buck converter in this dissertation.3): ˆ vo ( s ) 6*104s+20 = 7 2 5 ˆ d ( s ) 1.6. thus linear controllers can be designed based on the theoretical model. Figure 3. There is a RC C 20 dB/decade magnitude rise at that frequency and the phase shift is 90 degrees.1. The parasitic elements RC and RL are estimated to be 30 mΩ and 10 mΩ. It only shifts the magnitude upward or downward.9 ± j2481. Frequency response data for the prototype buck converter was measured using a Model 102B analog network analyzer by AP Instruments. the magnitude decreases. 32 . The buck converter’s nominal operating point is as follows: Vin = 20 V.4975*10 s+1 (3. The model also has a zero at 33. which causes a 180 degrees phase delay at the approximate frequency of 2500 radians/s. The zero is at − 1 . when D decreases. The magnitude of the transfer function depends on the duty cycle D.503*10 s +5.
1 Bode plot of the statespace averaged model of the buck converter 20 0 Gain dB 20 40 60 10 2 10 3 10 Frequency (rad/sec) 4 10 5 0 50 P hase deg 100 150 200 10 2 10 3 10 Frequency(rad/sec) 4 10 5 Figure 3.2 Frequency response of the buck converter obtained by the analog analyzer 33 .50 30 D decreases Two conjugate poles of the low pass filter zero introduced by E SR 40dB/dec Gain dB 10 D increases 10 20dB /dec 30 50 10 2 10 3 10 Frequency (rad/sec) 4 10 5 10 6 0 50 P hase deg 100 150 200 10 2 10 3 10 Frequency (rad/sec) 4 10 5 10 6 Figure 3.
1. which means that the output voltage will drop 34 .4): ˆ vo ( s ) VO = ˆ d ( s ) DO Le C sLe )( sRC C + RC / R + 1) R 2 ( R / DO 2 ) + ( RC / DO ) 1 ( RL / DO ) + ( RC / DO ) 1 s2 + s L + + + Le CR Le CR Le C (1 − (3.2 Boost Converters The outputtocontrol small signal transfer function of the boost converter is given by (3. and the zero in the right half plane is ωzr = . and load resistance R is 25 Ω. The zero in the right half plane is caused by switching action. and Do = 1D. and it introduces a 90 degree phase delay in the plant [3]. The Bode plot of the boost converter’s transfer function is shown in Figure 3.3. For the experiment. which means the model will change accordingly. the output voltage Vo is 12 V. The parasitic elements RC and RL are estimated from data sheets to be 30 mΩ and 10 mΩ. the filter element will change as the duty cycle changes. the initial slope of the output voltage (dvo/dt) is negative. The transfer function is a common twopole low pass filter with two zeros. the input voltage Vin is 5 V. inductance L is 250 µH. and the duty cycle D is 63%. Capacitance C is 1056 µF. It makes the control design for the boost converter more challenging from the point of view of stability and bandwidth. In a closedloopvoltagecontrol system. The zero in the left half plane is ωzl= − 1 + RC / R (1 − D )2 R . The physical phenomenon of the RHP zero is that when there is a step increase in duty cycle. The low pass filter’s cut off frequency is at ωc= 1D LC . Variables ωc and RC C L ωzr are functions of nominal duty cycle D.3. This makes the transfer function a nonlinear function of the duty cycle [3]. respectively.4) where Le = L /(1 − D ) 2 .
instantaneously.1604×104 radians/s.961×104 radians/s and 1.4 shows the frequency response obtained compared to the Bode plot of the theoretical transfer function.2525*102 s + 5. A transfer function for the boost converter is generated by fitting the experimental frequency response data using Matlab. and the poles are (0. The zeros of the theoretical model are 3.5) has two zeros at 5. Special attention is required when designing the compensator for the system to have adequate gain and phase margins.2. The control design will be based on the actual frequency response determined by the analog network analyzer.1324 ± j1.1769)×102 radians/s. Note that there is good agreement between the two curves. Similar to the buck converter. Figure 3. the frequency response of the boost converter prototype when operating in steady state is also obtained using the analog network analyzer. Part of the discrepancy is because there is more damping in the actual plant than in the theoretical model.468×104 radians/s. There are clear discrepancies between them.6956*103s2 . The experimental frequency response and this transfer function are plotted in Figure 3.5.1)×102 radians/s.126 ± j6. and two complex conjugate poles are (4. The RHP zero seriously complicates the problem of stabilizing the control loop [3].6801×104 radians/s and 3.5589*102s + 4. 35 .5): ˆ vo( s ) 5.4241*105 (3.5) The transfer function in (3.9831*106 ˆ d ( s) = s2 + 8. The generated transfer function is given in (3.
3 Bode plot of the statespace averaged model of the boost converter 50 30 Gain dB 10 10 30 50 10 Actual frequency response Theoretical frequency response 2 10 3 10 Frequency (rad/sec) 4 10 5 0 50 Phase deg 100 150 200 250 10 2 10 3 10 Frequency (rad/sec) 4 10 5 Figure 3.4 Comparison of the actual and theoretical frequency response of the boost converter 36 .D increases 40 Two conjugate poles of the low pass filter Zero in LHP Zero in RHP 20 D increases Gain dB 0 D decreases D decreases 40dB/dec 20dB/dec 20 D increases 40 10 1 D decreases 10 5 10 2 10 3 10 Frequency (rad/sec) 4 10 6 10 7 0 180 degrees phase shift caused by the conjugate poles 50 Phase deg 90 degree phase shift by LHP zero 90 degree phase delay by RHP zero 150 100 200 10 1 10 2 10 3 10 Frequency (rad/sec) 4 10 5 10 6 10 7 Figure 3.
the output voltage is a function of the input line voltage. Firstly. Negative feedback control is applied to DCDC converters to automatically adjust the duty cycle to obtain the desired output voltage with high accuracy in spite of disturbance [9]. the crossover frequency should be as high as possible. In this section. 37 . the loop gain should be high at lower frequencies to minimize steadystate error and increase rejection to disturbances of input voltage and load current variations. The compensated system is expected to have the following characteristics [45].2 Digital Controller Design for DCDC Converters Using Frequency Response Techniques In DCDC converters. It is desirable to have a constant output voltage in the event of disturbances such as a sudden change of input voltage or load current. Secondly. frequency response techniques are used to design digital controllers for DCDC converters.5 Comparison of the frequency response obtained using the analog analyzer and from the generated transfer function 3. the duty cycle and the load current.40 20 Gain dB 0 20 40 60 10 Frequency Response of the Actual Model Bode Plot of the Transfer Function Generated 1 10 2 10 Frequency (rad/sec) 3 10 4 10 5 0 100 Phase deg 200 300 400 10 1 10 2 10 Frequency (rad/sec) 3 10 4 10 5 Figure 3.
The transient response is a decaying exponential function of time with the time constant determined by the pole at the lower frequency.but about an order of magnitude below the switching frequency to allow the DCDC converter to respond quickly to the transients. the lowfrequency pole results in a slow transient response. the closedloop system has two real poles at the same frequency. the system is stable. To obtain Q = 1. To design a controller using the frequency response method. A zero is placed at frequency ωZ far below the cross38 . and the system is critically damped. the closedloop system has two real poles at two different frequencies. A proportionalderivative (PD) controller is phaselead compensation. When the phase margin of the loop gain is positive.5. When Q is equal to 0. phaselag or leadlag compensation is usually used. A phase margin of 45o to 60o is desirable. When Q is larger than 0. the phase margin should be sufficient to ensure the system’s stability. and the system is overdamped. phaselead. When Q is less than 0. and to obtain Q = 0.5. An increase of the phase margin makes the system more stable with less ringing and oscillation. Phase margin determines the transient response of the DCDC converter. a phase margin of at least 76o is needed. and the system is underdamped. When Q is very low. Thirdly. there are two complex conjugate poles. The transient response will be fast without overshoot. There is a qualitative relationship between the phase margin and the closedloop damping factor Q.5. the higher overshoot the transient response will have. The transient response will have an oscillatorytype waveform with decaying magnitude. PD controllers are used to increase the phase margin and improve the crossover frequency. a phase margin of 52o is required. The higher Q. The damping factor Q determines the shape of the transient response.5.
6) ) ωP The pole at ωP is placed well below the switching frequency to avoid amplification of the switching noise. where e(t) is the compensator input and m(t) is the compensator output. The PID controller is defined by (3.7).8). the advantages of lead compensation and lag compensation can be combined to obtain sufficient phase margin. To obtain maximum phase margin improvement.over frequency to improve the phase margin. By using a leadlag compensator. the maximum phase shift should be placed at the crossover frequency. The maximum phase shift occurs at the geometric mean of the pole ωP and the zero ωZ.6). Both PD and PI controllers are firstorder controllers. (1 + GC ( s ) = K C (1 + s ωz s ) (3. The transfer function of a PD controller is shown in (3. A PI controller is used to increase the low frequency loop gain. high loop gain and wide control bandwidth. The transfer function of a PI controller is shown in (3. m(t ) = K P e(t ) + K I ∫ e(τ )dτ + K D 0 t de(t ) dt (3.8) 39 .7) The PI controller has a pole at the origin. A proportionalintegralderivative (PID) controller is a leadlag compensator. thus reducing steadystate error. GC ( s ) = K P + KI KPs + KI = s s (3. It is the most widely used compensator in feedback control systems. A proportionalintegral (PI) controller is a phaselag controller.
An increase in the proportional term will increase the speed of system response. Therefore. The low frequency gain is improved by the integral term. which could result in oscillation of the duty cycle during steady state.1 Buck Converters A PID and a PI controller were designed for the buck converter for operation during a startup transient and steady state. The PI controller is applied during steady state to reduce oscillation of the duty cycle and improve the system’s stability. however.The Laplace transform of (3. and the lowfrequency components of the output voltage are accurately regulated. the derivative term is needed to reduce the settling time by predicting the changes in error. the phase margin and crossover frequency are improved by the derivative term. The PID controller is applied during start up to obtain a fast transient response. At high frequency.9) The integral term is phaselag and the derivative term is phaselead. 40 . GC ( s ) = M ( s) K = KP + I + KDs E (s) s (3. respectively.2.8) yields the transfer function in (3. A PID controller and a PI controller were designed for both the buck converter and the boost converter in the following sections. The derivative term in a PID controller is susceptible to noise and measurement error of the system. during a transient. the system switches between PID and PI controllers during transient and steady state to obtain the desired response. 3.9). too much proportional gain will make the system unstable. However. which improves the system’s stability and the speed of the transient response.
1. the gain at low frequency is high. The transfer function of the PID controller is given by (3. As can be seen in this plot.6 Bode plot of PID controller compensated buck converter 41 . Figure 3.6.10): Gc ( s ) = 0. One zero was placed an octave below the cutoff frequency (approximately 260 radians/s) and the other one at 4600 radians/s. crossover frequency and phase margin.5786 + 142.4 + 0.3.1 PID Controller Design for Buck Converters A PID controller was designed for the buck converter to improve the loop gain. the phase margin is 107 degrees and the bandwidth is 19100 radians/s.000119s s (3.2.10) The Bode plot for the compensated system is shown in Figure 3.
4 degrees and the bandwidth is 10600 radians/s.2 PI Controller Design for Buck Converters A PI controller was also designed for the control of the buck converter at steady state to reduce steadystate oscillation.7. and one zero was placed at 800 radians/s.11) The Bode plot for the PI compensated system is shown in Figure 3. One pole was placed at the origin. The DC gain of the controller was adjusted to obtain sufficient phase margin and high crossover frequency. The transfer function of the PI controller is given by (3.1.3. Figure 3.11): Gc ( s) = 0.2.75 + 600 s (3. The Bode plot shows that the phase margin is 15.7 Bode plot of PI controller compensated buck converter 42 .
13 + 0.12) The bode plot of the PID compensated boost converter is shown in Figure. Figure 3. one zero was placed at 260 radians/s.2.2 Boost Converters A PID and a PI controller were designed for the boost converter for operation during a startup transient and steady state. respectively. The controllers were designed based on the measured small signal model of the boost converter using frequency response techniques.8.000198s s (3. The transfer function of the PID controller is shown in (3.2.3. 3.2. Gc ( s) = 0. and the other zero is placed at 2600 radians/s.1 PID Controller Design for Boost Converters For the PID controller.567 + 134.12). 3.8 Bode plot of PID controller compensated boost converter 43 .
The bandwidth of the PI compensated system is 1010 radians/s.9.3 degrees. Figure 3. 46].2. The Bode plot of the PIcontrollercompensated system is shown in Figure.13). 44 . and the phase margin is 26.83×103 radians/s. Using the Euler method.2 PI Controller Design for Boost Converters A PI controller was designed for the steady state to reduce oscillations of the duty cycle.2. the transfer function of a numerical integrator is shown in (3.9 Bode plot of PI controller compensated boost converter 3. 3.2.The bandwidth of the PIDcompensated system is 1. 3. and the phase margin is 50 degrees.3 Transformation from an Analog Controller to a Digital Controller The design in the continuoustime domain was transformed into the discretetime domain using the backward integration method (Euler Method) [45. A pole was placed at the origin and a zero was placed at 600 radians/s.
14). GC ( z ) = K P + 3.13) and its reciprocal into the PID controller’s sdomain transfer function in (3.13) and its reciprocal into the PI controller’s sdomain transfer function in (3. The eZdsp F2812 is a standalone evaluation module.15) Digital controllers were implemented on the eZdsp F2812 from Texas Instruments. where T is the switching period of the DCDC converter. GC ( z ) = K P + K I Tz K D ( z − 1) + z −1 Tz (3. The conversion rate of the ADC is 80 ns. by substituting (3. The eZdsp F2812 was introduced in Chapter 2. Therefore.15). The faster clock frequency and ADC conversion time of the F2812 DSP allow a faster sampling and switching frequency. 16 channel ADC. The sampling and the switching frequency of the controllers implemented on the TMS320F2812 DSP was 150 kHz. the digital PI controller’s transfer function is shown in (3. by substituting (3.M ( z) = Tz E( z) z −1 (3. T = 6. The DSP has a fixed point 32bit CPU.9). This module features a TMS320F2812 Digital Signal Processor (DSP) with 150 MIPS operating speed. When the switching frequency is 150 kHz.14) Similarly.13) The transfer function of a numerical differentiator is the reciprocal of the transfer function of the numerical integrator shown in (3.7). 45 . 128K onchip flash memory and a dual 12bit. The one switching period delay between sampling the converter’s output voltage and updating the duty cycle is modeled by the function eTs. the digital PID controller’s transfer function is shown in (3.13).3 Implementation of Digital Controllers K I Tz z −1 (3.67 µs.
The interrupt subroutine was executed every sampling period. The interrupt vector address mapped the subroutines corresponding to each level of interrupts. The subroutine acquired a sample once every sampling period.1 Program Structure The overall program structure is shown in Figure 3. an interrupt was enabled to allow the main algorithm to run. the first task was to initialize the DSP. 46 .3. utilized a digital controller algorithm to calculate a new duty cycle. Once the program starts to run. Then certain bits were set to start the PWM. Each time when the value of the general purpose timer equaled the timer’s period value. which was determined by the period of the general purpose timers. The event manager module was initialized to define the sampling and switching frequency. The analog to digital conversion was set to be in the continuous conversion mode. After the configuration of the DSP was complete. The global variables were declared and given initial values. including PID and PI controllers and fuzzy and sliding mode fuzzy controllers. Macros such as clearing bit. setting bit and setting a certain amount of delay time were defined.10. The sampling period was equal to the period of the general purpose timer.3. and updated the new duty cycle at the start of the next switching period. Different digital control algorithms. were all implemented as interrupt subroutines. an interrupt was requested and directed to the corresponding interrupt subroutine.
10 Overview of the program structure for digital controllers 47 .Power On Run Program Initialization Macro Definition Interrupt Vector Address Declarations Initialize Local Variables Configure CPU and System Clock Clear Module Error Flags Initialize RAM Set Up Digital /IO Port Set Up Event Manager Module Set Up Interrupt Registers Start PWM Set ADC Into Continuous Conversion Mode Enable Masked Interrupts No Interrupt Condition Met? Yes Interrupt Subroutine Wait Until ADC Complete Obtain ADC Value Digital Control Algorithm Update PWM Return to Main Program Figure 3.
16) And the difference equation to calculate a new duty cycle for the digital PI controller is given in (3. then transformed into digital controllers using the backward integration method. where ADC[k] is the converted digital value of the kth sample of the output voltage.2. u[k ] = K P e[k ] + K I T ∑ e[i ] i =0 k (3. The zdomain transfer function of a digital PID controller is shown in (3.14).3. the PID algorithm changes into a PI algorithm. It is noted that when KD is equal to zero.16) is shown in Figure 3. and Ref is the digital value corresponding to the desired output voltage. 48 .15). The difference equation to calculate a new duty cycle for the digital PID controller is written in (3.17). PID and PI controllers were first designed using the frequency response techniques based on the small signal models of the DCDC converters. and e[k] is the error of the kth sample.16). The error e[k] is calculated as e[k] = RefADC[k].11. The block diagram for the difference equation (3. and the zdomain transfer function of a digital PI controller is shown in (3. u[k] is the controller output for the kth sample. u[k ] = K P e[k ] + K I T ∑ e[i ] + i =0 k KD {e[k ] − e[k − 1]} T (3.3.2 Implementation of Digital PID and PI Controllers In Section 3. ∑ e[i] i =0 k is the sum of the errors and {e[k]e[k1]} is the difference between the error of the kth sample and the error of the (k1)th sample.17) In the difference equation.
Measurement of this glitch will produce oscillation in the duty cycle calculated by the digital PID controller. The switching action of the MOSFET in the DCDC converter produces a glitch in the converter output voltage which can be measured by the A/D converter.12.Kp Proportional Gain e(k) Ref kiT u Controller Output ADC(k) 1/z Integral Gain kd/T 1/z e(k1) Derivative Gain Figure 3. The sample was taken after the start of the switching period instead to avoid sampling the switching glitches. At the start of each sampling period. Because the sampling and PWM switching frequency were the same and their periods were synchronous. and the absolute value of the difference between the error of the kth sample and the error of the (k1)th sample de[k] was less than φ. the start of the sampling and switching periods happened at the same time. The PI controller was applied in steady state to reduce oscillation of the duty 49 . When both the absolute value of the error of the kth sample e[k] was less than ε.11 Block diagram of digital PID controller The flowchart for the digital PID and PI controller is shown in Figure 3. there was a 2 µs delay before taking the analog to digital conversion. the converter was considered to be operating in steady state. The values ε and φ can be determined based on experimental results of the converters.
The duty cycle of the PWM signal in the digital control system for the buck converter was limited between 10% and 90%. A series of scalar multiplification and addition instructions can be used to implement the linear PID and PI controllers on the TMS320F2812.cycle. derivative and integral controllers. In the digital control system for the boost converter. The gain of the integrator KD was assigned to be zero. The difference equations in (3.16) and (3. After updating the new duty cycle. This prevents the MOSFET from being turned on or off for a full switching period. and the error of the (k1)th sample. The result of the PID controller was a sum of the proportional. experimental results of the buck and boost converters using digital PID and PI controllers will be presented in Chapter 6. the duty cycle was further limited to be between 20% and 80%. since the digital controller for the boost converter tends to oscillate more than the digital controller for the buck converter.17) are linear combinations of feedback and control signals. and the proportional and integral gains KP and KI were assigned according to the design of the PI controller. In order to compare the experimental results using different control methods. 50 . the interrupt subroutine returned to the main program and waited for a request for the next interrupt.
KI and KD Assign values for PI controller gains Kp.12 Flowchart of digital PID and PI controller 51 .Interrupt Subroutine Starts Delay 2 us ADC Conversion Complete e[k]=RefADC[k] de[k]=e[k]e[k1] No e[k ] ≤ ε ? Yes No de[k ] ≤ φ ? Yes Assign values for PID controller gains KP. KD=0 P=KP*e[k] ∑ e (i ) = ∑ e (i ) + e ( k ) i=0 i=0 k k −1 I = K I T ∑ e (i ) i =0 k D=KD/T*de[k] PID=K+I+P Yes PID>90%? No PID=90% PID<10%? No Duty Cycle = PID Update Duty Cycle of PWM e[k1]=e[k] Wait On Until Next Interrupt Interrupt Subroutine Ends Yes PID=10% Figure 3. Ki.
are all dependent on the duty cycle D. A second solution is to use a nonlinear controller [9]. The second section is 52 . This makes the transfer function of the boost converter’s small signal model a nonlinear function of the duty cycle. as well as the magnitude of the frequency response. However.CHAPTER 4 FUZZY CONTROLLER DESIGN FOR DCDC CONVERTERS Linear controllers for DCDC converters are usually designed based on mathematical models. In the previous chapter. The design of fuzzy controllers is presented in this chapter. To obtain a certain performance objective. The small signal model changes due to variations in operating point. Changes in the duty cycle only affect the magnitude of the buck converter’s small signal model. two solutions are possible. While for the boost converter’s small signal model. The righthalf plane zero and the nonlinear nature of the boost converter’s small signal model makes the control design for this converter more challenging from the point of view of stability and bandwidth [3]. an accurate model is essential. linear controllers were designed for buck and boost converters based on each converter’s small signal model using frequency response and root locus design methods. The first section introduces the concept of fuzzy control. To achieve a stable and fast response. One is to develop a more accurate model for the converter. the model may become too complex to use in controller development. timevariant systems. the poles and a righthalf plane zero. Since fuzzy controllers don’t require a precise mathematical model. they are well suited to nonlinear.
adaptive control. Implementation of fuzzy controllers is presented in the third section of this chapter. A fuzzy controller contains four main components: (1) the fuzzification interface that converts its inputs into information that the inference mechanism can use to activate and apply rules. (2) the rule base which contains the expert’s linguistic description of how to achieve good control. rise time. robust control. Based on these specifications. optimal control. statespace methods. Major conventional control methods include classical control methods (frequency response and root locus techniques). 4. These conventional control methods provide a variety of ways to utilize information from mathematical models on how to obtain good control. Different from conventional control. Conventional controllers are designed based on a mathematical model. sliding mode control and other nonlinear control methods such as feedback linearization and backstepping. conventional controllers are designed.mainly focused on the design of a fuzzy controller for the buck and boost converters. insenstivity to plant parameter variations. 4.1 Introduction to Fuzzy Control Fuzzy control is an artificial intelligence technique that is widely used in control systems. A block diagram of a fuzzy control system is shown in Figure.1. overshoot and settling time and steadystate error. It provides a convenient method for constructing nonlinear controllers from heuristic information. fuzzy control is based on the expert knowledge of the system. (3) the inference mechanism that evaluates which control rules are relevant in the current 53 . Closedloop control specifications include disturbance rejection properties. stability. Fuzzy control provides a formal methodology to represent and implement a human’s heuristic knowledge about how to control the system.
Fuzzy Controller Inference Mechanism Reference Input r(t) Input u(t) Output y(t) Fuzzification Defuzzification Plant Rule Base Figure 4. The two inputs are multiplied by the scaling factors g0 54 . 4. Design of fuzzy controllers involves the following procedures: (1) choose the fuzzy controller’s inputs and outputs. and (3) design each of the four components of the fuzzy controller shown in Figure 4. where ADC[k] is the converted digital value of the kth sample. and (4) the defuzzification interface which converts the conclusion from the inference mechanism into the control input to the plant [48]. is the difference between the error of the kth sample and the error of the (k1)th sample.situation.1 Block diagram of fuzzy control system The performance objectives and design constraints are the same as those for conventional control.1. ce[k]=e[k]e[k1]. The second input. The first input is the error in the output voltage e[k]=RefADC[k]. and Ref is the digital value corresponding to the desired output voltage.2 Fuzzy Control Design for DCDC Converters A fuzzy controller for a DCDC converter has two inputs. (2) choose the preprocessing for the controller inputs and postprocessing for the controller outputs.
Oscillation between the maximum and minimum values of the duty cycle may even occur if h is relatively large compared to the duty cycle range.2).1) to calculate the duty cycle d[k] is shown in Figure 4. Quantization errors in digital controllers increase the magnitude of the oscillation. respectively. which is shown by (4. A very small output gain h tends to increase the transient response time because more sampling periods are necessary to arrive at the desired duty cycle [49]. and then fed into the fuzzy controller. because digital controllers are restricted to a finite set of values. A second method to calculate the new duty cycle is to add the output of the fuzzy controller scaled by h to the output of a linear integrator. which could lead to oscillation.and g1. The disadvantage of this method is that the output gain h has to be tuned to be very small to avoid oscillation in steady state. the output of the fuzzy controller. It is scaled by a linear gain h. In the first method. d[k] = Ki*I[k]+h*δd[k] (4. The output of the fuzzy controller is the change in duty cycle δd[k]. The Simulink model of the fuzzy controller using (4.1) The integration of the fuzzy controller’s output increases the system type and improves steadystate error. which is written in (4. The scaling factors g0. the duty cycle varies around its nominal value during steady state. Since the change in duty cycle is accumulated every sampling period. is added to the previous sampling period’s duty cycle d[k1]. scaled by the output gain h.2. There are two methods to calculate the new duty cycle from the fuzzy controller’s output δd[k].2) 55 .1). d[k] = d[k1]+h*δd[k] (4. g1 and h can be tuned to obtain a satisfactory response.
the duty cycle d[k] is limited to be between 10% and 90% for the buck converter.3 [9.2 Simulink model of the fuzzy controller for the DCDC converters Method 1: (d[k] = d[k1]+h*δd[k]. Figure 4. a combination of both methods was applied to get the desired response.) 56 .2) to generate the duty cycle d[k] is shown in Figure 4.2 is more prevalently used than the second method in Figure 4. From the literature. In this method. the first method in Figure 4. 10]. In this dissertation. and further limited to be between 20% and 80% for the boost converter. The linear integrator is applied to eliminate steadystate error. the output gain h can be increased because the fuzzy controller’s output is not accumulated every sampling period. In order to prevent the MOSFET from being turned on or off for a full switching period. The Simulink model of the fuzzy controller using (4. only the second method was applied to the buck converter to obtain satisfactory response.where I[k] is the output of the linear integrator of the error e[k]. and KI is the gain of the integrator.3. while for the boost converter.
P2. P7 and P8. P1.1 Fuzzification First.2. respectively. N1. where N indicates negative. N6. the computation time and code size of the fuzzy controller can be reduced when the number of subsets for the positive and negative parts is a power of 2. P6. P4. A triangleshaped membership function was used for this controller design for the ease of implementation. P3. P5. For the purpose of implementation. and P indicates positive.Figure 4. Of the 17 subsets. Z represents zero. 57 . N5. Each universe of discourse is divided into fuzzy subsets. Z. N3. because shift instructions can be used to calculate the membership degrees instead of division functions. there were 8 subsets for the positive parts and 8 subsets for the negative parts of the universe of discourse. The variables µe(e[k]) and µce(ce[k]) are the membership degrees assigned to each fuzzy subset to quantify the certainty that the input can be classified linguistically into the corresponding fuzzy subsets. the linguistic values are quantified using membership functions.3 Simulink model of the fuzzy controller with a linear integrator for the DCDC converters Method 2:(d[k] = KI*I[k]+h*δd[k]) 4. N2.4. The membership functions for e[k] and ce[k] are shown in Figure 4. N7. N4. There were 17 fuzzy subsets in the fuzzy controller for the buck converter: N8.
P1. Z. The number of fuzzy subsets was determined based on the experimental results of buck and boost converters.5 Membership functions of the inputs e[k] and ce[k] for the boost converter 58 . Figure 4. …. P16. There were 16 fuzzy subsets for the negative parts and 16 fuzzy subsets for the positive parts of the universe of discourse in order to reduce the computation time.5. 17 fuzzy subsets for the buck converter and 33 fuzzy subsets for the boost converter were the smallest number of fuzzy subsets in order to obtain satisfactory results.4 Membership functions of the inputs e[k] and ce[k] for the buck converter Figure 4. N1. N15. P15. …. P14.For the boost converter. N14. each universe of discourse was divided into 33 fuzzy subsets: N16. The membership functions for e[k] and ce[k] for the boost converter are shown in Figure 4.
a larger rule base than the buck converter was derived for the boost converter in order to obtain fast transient response and reduce steadystate oscillations. ci is taken from the rule table. There is a tradeoff between the size of the rule base and the performance of the controller. chattering and oscillation were reduced [48]. Experimental results indicate that the fuzzy controller with a 17*17 rule base exhibited less oscillation during steady state. Therefore.2. For the same universe of discourse.3 Inference Mechanism The results of the inference mechanism include the weighing factor wi and the change in duty cycle ci of the individual rule [4].3). The weighing factor wi is obtained by Mamdani’s min fuzzy implication of µe(e[k]) and µce(ce[k]). oscillation occured in steady state when a 17*17 rule base was used for the boost converter. and faster transient response was achieved by increasing the output gain h. µce(ce[k]) are the membership degrees [10]. The change in duty cycle inferred by the ith rule. 59 .2 Rule Base The rule base is derived from general knowledge of DCDC converters. A 7*7 rule base was also designed and implemented for the buck converter. and a more accurate control was achieved. and adjusted based on experimental results. The output of the controller had less variation when either of the inputs had small changes.4. There were 33*33 rules in the rule base for the boost converter. µce(ce[k])} and µe(e[k]).2. From laboratory experiments. zi is written in (4. 4. more membership functions resulted in finer control. The nonlinear property of the boost converter’s small signal model and its righthalf plane zero makes the controller design for the boost converter more difficult than for the buck converter. where wi = min{µe(e[k]).
Figure 4. DSPs are usually optimized for such operations. The flowcharts of the fuzzy controllers are shown in Figure 4. there are at most four rules that are effective at any one time. which corresponds to the Simulink model in Figure 4.2. the implementation of the linear controllers in real time was quite straightforward.4).3) The center of average method is used to obtain the fuzzy controller’s output δd[k].6 and Figure 4.3 Implementation of Fuzzy Controllers Implementation of fuzzy controllers on the DSP had quite different issues from implementation of linear controllers. which is given in (4.3. N=4. which corresponds to the Simulink model in Figure 4. µ ce ( ce [ k ])} × c i 4. When using triangleshaped membership functions. which are linear combination of feedback and control signals. Figure 4.4) 4. therefore. A series of scalar multiplication and addition instructions can be used to implement a linear digital controller. The TI TMS320F2812 DSP has several instructions to multiply a number by a constant and add a previous product in a single instruction.7.6 shows the flowchart of the fuzzy controller using the first method to calculate the new duty cycle.7 shows the flowchart of the fuzzy controller with a linear integrator.4 Defuzzification (4.2.z i = w i × c i = min{ µ e ( e[ k ]). 60 . δd [k ] = ∑w ×c i =1 i N i ∑ wi i =1 N (4. Therefore. The implementation of linear controllers usually involves difference equations.
Interrupt Subroutine Starts Delay 2 us ADC Conversion Complete e[k]=RefADC[k] ce[k]=e[k]e[k1] e[k]=g0*e[k] ce[k]=g1*de[k] Calculate centers and membership degrees µe(e[k]) for e[k] Calculate centers and membership degrees µce(ce[k]) for ce[k] wi = min{µe (e[k ]). µ ce (ce[k ])} δd [k ] = ∑w ×c i =1 i 4 i ∑w i =1 4 i d [ k ] = d [ k − 1] + h × δd [ k ] Yes d[k]>90%? No d[k]<10%? Yes d[k]=10% d[k]=90% No Update Duty Cycle of PWM e[k1]=e[k] d[k1]=d[k] Wait On Until Next Interrupt Interrupt Subroutine Ends Figure 4.6 Flowchart of fuzzy controller using method 1 61 .
µ ce (ce[ k ])} δd [ k ] = ∑ w ×c i =1 i 4 i ∑w i =1 4 i d[k] = KI × I[k] + h×δd[k] Yes d[k]>90%? No d[k]=90% d[k]<10%? No Update Duty Cycle of PWM e[k1]=e[k] d[k1]=d[k] Wait On Until Next Interrupt Interrupt Subroutine Ends Yes d[k]=10% Figure 4.7 Flowchart of fuzzy controller with a linear integrator 62 .Interrupt Subroutine Starts Delay 2 us ADC Conversion Complete e[k]=RefADC[k] ce[k]=e[k]e[k1] I [k ] = ∑ e[i ] = ∑ e[i ] + e[ k ] i =0 i =0 k k −1 e[k]=g0*e[k] ce[k]=g1*de[k] Calculate centers and membership degrees µe (e[k]) for e[k] Calculate centers and membership degrees µce(ce[k]) for ce[k] wi = min{µ e (e[k ]).
A fuzzy controller is a nonlinear algorithm. there are at most four rules that are effective at any time. The sampling frequency of the fuzzy controller would have to be quite low because of the long computation time. It is much more efficient to calculate only four centers and corresponding membership degrees rather than 1089. there were two inputs. Most DSPs are not optimized for nonlinear algorithms. the efficiency of the implementation of fuzzy controllers becomes even more important. For triangleshaped membership functions. When there are many inputs to the fuzzy controller or each input has many membership functions. In each sampling period of the controller computations.4). Triangleshaped membership functions were used to solve this problem. Therefore. there were totally 332=1089 rules. 63 . The reason is that the number of rules increases exponentially with the increase of the number of inputs. The reduction of the computation time is significant especially when the rule base is large. For the fuzzy controller designed for the boost converter. Therefore. When implementing a fuzzy controller in real time. and the amount of memory used. It requires frequent use of multiplication and division instructions with high accuracy. only four centers and four membership degrees need to be calculated instead of going through all the rules in the rule base. centers in the membership function and their corresponding membership degrees need to be calculated. and each input had 33 membership functions. In real time. it was prohibitive to calculate the 1089 membership degrees and to sum up 1089 values in the numerator and denominator in equation (4. There were unique challenges to implement a fuzzy controller on a DSP. two main issues are the amount of time it takes to compute the output of fuzzy controllers.
Therefore. more accurate control was achieved and chattering and oscillation were reduced. The computation time and code size of the fuzzy controller can be reduced when the number of subsets for the positive and negative parts is a power of 2. respectively. A 17×17 rule base was designed and implemented for the boost converter. because shift instructions can be used to calculate the membership degrees instead of division functions. more computational power and memory are required to implement a fuzzy controller than a linear controller. several techniques have been utilized. However. The output of the controller had less variation when either of the inputs changed slightly. Experimental results indicated that the fuzzy controller with a 33×33 rule base exhibited less oscillation during steady state and faster transient response was achieved by increasing the output gain h. the implementation of a linear controller was less demanding than the implementation of a fuzzy controller. Generally.Of the 33 subsets. There was a trade off between the size of the rule base and the performance of the fuzzy controller. On the contrary. increasing the rule base resulted in a larger amount of memory used. Most DSPs are optimized for implementation of digital filters. A digital signal processor (DSP) with fast computation speed and high computation power is more appropriate for the implementation of fuzzy controllers in real time. To reduce the computation time and amount of memory used. More membership functions resulted in finer control for the same universe of discourse. 64 . The size of the rule base was determined based on the balance of the performance of the controller and the amount of memory used. there were 16 subsets for the positive and negative parts of the universe of discourse.
For comparison purposes. experimental results of the buck and boost converters using fuzzy controllers will be presented in Chapter 6. 65 .
In sliding mode control. a switching surface σ(x) = 0 in the state plane that has x as coordinates is designed to specify desired closedloop system dynamics. The control u is shown in (5. In sliding mode control. When the state trajectory stays on the switching surface. it is in a sliding mode. the state trajectory follows the desired dynamics that are described by the switching function.CHAPTER 5 SLIDING MODE FUZZY CONTROLLER DESIGN FOR DCDC CONVERTERS Sliding mode control is a method for controlling systems with parametric uncertainties and external disturbances. Sliding mode control is able to provide a very robust closedloop system. Then a variable structure switching control u is designed to drive the state trajectory to the switching surface in finite time. The reaching condition is the sufficient condition for a reaching mode.1) The period of time in which the state trajectory moves toward and reaches the switching surface is called the reaching mode. invariance can be achieved. 66 .1): u = u+ u = uwhen σ(x) > 0 when σ(x) < 0 (5. There are two steps to design a sliding mode controller. which means that the system can be entirely independent of plant uncertainties and disturbances. A sliding mode is achieved by forcing the system trajectory on a properly designed switching function using high speed switch control. First.
sliding mode control is able to move the state trajectory onto the switching surface by controlling the switch.2. However. the control action (in this case. the system is able to approach the sliding mode but not able to stay on it. a basic assumption for sliding mode control is that the control can be switched infinitely fast from one state to another. The second disadvantage is that the sliding mode controller will generate an ONOFF control for DCDC converters. there is always some chattering in the sliding mode.Theoretically. As a result. Fuzzy controllers were applied to control DCDC converters in Section 4. Therefore. The practical issues above prevent the sliding mode control from being extensively applied to DCDC converters. several disadvantages exist for sliding mode control. and the switching frequency is not regulated. The third disadvantage is when the sliding mode control is implemented in discretetime. sliding mode control is very suitable for the control of DCDC converters. fuzzy controllers are usually designed 67 . chattering is very undesirable. The oscillation may excite unmodeled highfrequency dynamics of the system [20]. However. Hysteresis can be used to regulate the switching frequency. chattering always occurs in steady state and appears as an oscillation in steady state. but a constant switching frequency can not be guaranteed. In practice. Design of fuzzy controllers does not require an exact mathematical model and is well suited to nonlinear timevariant systems. With hysteresis. Thus. ON or OFF of the switch) can only be activated at each sampling instant and the control effort is constant over each sampling period. this is impossible due to the time delay for control computation and physical limitations of switching devices. First of all. Because DCDC converters change from one state to another when the switch is turned on or off.
In this chapter. since sliding mode fuzzy controllers can be designed systematically based on the principles of sliding mode control. the chattering problem is eliminated by incorporating a boundary layer into the rule base. Last but not the least.based on expert knowledge of converters. and it is more robust than an ordinary sliding mode controller. rather than a function. a sliding mode fuzzy 68 . therefore. It is like a modified sliding mode controller. Sliding mode fuzzy control has advantages of its own that cope with the problems in the sliding mode control and fuzzy control design and implementation. The sliding mode fuzzy controller combines the advantages of both fuzzy controllers and sliding mode controllers. and extensive tuning is required based on a trial and error method. Like a regular fuzzy controller. The tuning can be quite timeconsuming. In addition. and the system’s response can be predicted. the response is not easy to predict. a sliding mode fuzzy controller is used to control buck and boost converters. the amount of time needed for tuning is significantly reduced. Implementation of sliding mode fuzzy controllers is presented in the second section. Design of sliding mode fuzzy controllers for buck and boost converters is described in detail in the next section. The output from the sliding mode fuzzy controller is duty cycle directly. 5. The sliding surface in a sliding mode fuzzy controller is rendered by rule bases and scaling factors. The second advantage is that the sliding mode fuzzy controller can be implemented like a regular fuzzy controller. First of all. constant switching frequency is achieved.1 Design of Sliding Mode Fuzzy Controller for DCDC Converters A sliding mode fuzzy controller has several advantages that make it applicable to control of DCDC converters.
These four steps will be followed to design sliding mode fuzzy controllers for buck and boost converters.2) When s(e) = 0. (3) the inference mechanism that evaluates which control rules are relevant in the current situation. inputs to the sliding mode fuzzy controller and their scaling factors can be determined. (3) a rule base is designed according to the switching function. which is shown in (5. A switching function is often of lower order than the plant.1 Switching Functions A switching function defines the desired dynamics of the system. dynamics on the sliding surface are shown in (5. There are four steps involved in the design of a sliding mode fuzzy controller: (1) a switching function that represents a desired system dynamics is first designed.1.3) 69 . and (4) other parts of the sliding mode fuzzy controller such as the inference mechanism and defuzzification method are designed. and (4) the defuzzification interface which converts the conclusion from the inference mechanism into the control input to the plant.3).controller includes four main components: (1) the fuzzification interface that converts the inputs into information that the inference mechanism can use to activate and apply rules. a firstorder switching function is designed. (2) from the switching function. Switching functions for the buck converter and boost converter are presented in this section. 5. & e + λe = 0 (5. (2) the rule base which contains the expert’s linguistic description of how to achieve good control.2). & s (e) = e + λ e (λ>0) (5. Since a boost converter’s small signal model is second order.
and the settling time is 4/ λ seconds. In this experiment.2.3).6) e[k ] − e[k − 1] ce[k ] + 400e[k ] = + 400e[k ] T T 70 .3) becomes s+λ=0. & e= s (e ) = e[k ] − e[k − 1] T (5.5) into (5. & s (e) = e + 400e (5. and there is no overshoot. and T is the sampling period.67µs. The time constant τ is 1/ λ seconds.1.5 ms.4) & In a digital implementation. For the boost converter. (5.6).5). Substituting (5. A stable firstorder system with a pole at –λ is represented by the dynamics in (5. where ce[k] is the difference between e[k] and e[k1].In the s domain. λ is 400. The step response of (5. e was approximated as shown in (5. The settling time of the step response is 10 ms. which is the switching function when the sliding mode fuzzy controller is implemented in discretetime. The switching function designed for the sliding mode fuzzy controller is given by (5. where e[k] is the error of the kth sample of the output voltage. to obtain a settling time of 10 ms. and it is plotted in Figure 5. and T was 6. Because λ =1/ τ.4) yields (5.5) (5. s(e)=0 is called the switching line. the time constant τ should be 2. the sampling frequency was chosen to be 150 kHz.4) is simulated and shown in Figure 5.4).
& e
s (e)=0
e
Figure 5.1 Switching function of the sliding mode fuzzy controller for boost converter
Figure 5.2 Step response of the switching function for boost converter For the buck converter, to obtain a settling time of 1 ms, the time constant τ should be 0.25 ms, and λ =1/τ = 4000. The switching function designed for the sliding mode fuzzy controller for the buck converter is given in (5.7). The step response of (5.7) was simulated and is shown in Figure 5.3. The settling time of the step response is 1 ms, and there is no overshoot.
& s (e) = e + 4000e
(5.7)
71
Figure 5.3 Step response of switching function for buck converter Substituting (5.5) into (5.7) yields (5.8), which is the switching function for the sliding mode fuzzy controller in discretetime. In this equation, ce[k] is the difference between e[k] and e[k1].
s (e) =
e[ k ] − e[ k − 1] ce[k ] + 4000e[ k ] = + 4000e[k ] T T
(5.8)
5.1.2 Inputs and Their Scaling Factors
From the switching function in (5.6), it can be determined that the sliding mode fuzzy controller for the boost converter has two inputs. The first input is the error in the output voltage e[k]=ADC[k]Ref, where ADC[k] is the converted digital value of the kth sample, and Ref is the digital value corresponding to the desired output voltage. The second input ce[k]=e[k]e[k1] is the difference between the error of the kth sample and the error of the (k1)th sample. The two inputs are multiplied by the scaling factors g0 and g1 respectively, and then fed into the fuzzy controller. The membership functions for e[k] 72
and ce[k] are shown in Figure 5.4. Each universe of discourse was divided into 33 fuzzy subsets: N16,N15,N14,…,N1,Z,P1,…,P15,P16, where N indicates negative, Z represents zero and P indicates positive. The variables µe(e[k]) and µce(ce[k]) are the membership degrees assigned to each fuzzy subset to quantify the certainty that the input can be classified linguistically into the corresponding fuzzy subsets. A triangleshaped membership function was used for this controller design for the ease of implementation. Of the 33 subsets, there were 16 subsets for the positive and negative parts of the universe of discourse, respectively. For the purpose of implementation, the computation time and code size of the fuzzy controller can be reduced when the number of subsets for the positive and negative parts is a power of 2, because shift instructions can be used to calculate the membership degrees instead of division functions. From experimental results, 33 fuzzy subsets was the smallest number of fuzzy sets in order to obtain satisfactory response for the boost converter.
Figure 5.4 Membership functions of the inputs e[k] and ce[k] for the boost converter The two input scaling factors g0 and g1 have a significant impact on the controller’s performance, and usually require extensive tuning. In designing the fuzzy sliding mode controller, g0 and g1 can be directly determined from the switching 73
function in (5.6). Laboratory observation of the boost converter indicated that if the scaling factor g0 of e[k] is less than 1, the precision of the measured output voltage was reduced, which can lead to steady state error. Therefore, g0 was chosen to be 1, and the scaling factor g1 of ce[k] becomes 1/(400T), which equals 375 when the sampling frequency is 150 kHz.
5.1.3 Rule Base
In a regular fuzzy controller, the rule base is often designed from an indepth knowledge of the plant using a trial and error approach, which is very timeconsuming. In the sliding mode fuzzy controller design, the rule base is derived from the switching function. After scaling the inputs e[k] and ce[k] by g0 = 1 and g1 = 375, respectively, the diagonal line from upper left corner to bottom right corner in the rule base represents the switching line s(e) = 0. To avoid drastic changes in the controller output, a boundary layer was introduced, which was designed in the rule base. The principles to design the rule base are summarized as follows: (1) ci should be negative above the switching line, and positive below it, where ci is the center in the rule base that represents change in duty cycle. (2) ci should increase as the distance between the actual state and the switching line s(e) = 0 increases. (3) ci should increase as the distance between the actual state and the line perpendicular to the switching line increases, so that discontinuities close to the switching line can be reduced.
74
A small 7×7 rule base for the sliding mode fuzzy controller is shown in Table 5. and Z represents zero. positive and negative control outputs are applied. which incorporates a boundary layer into the rule base.(4) when e[k] and ce[k] fall out of the state plane. N stands for negative. According to the principles above. and within the layer. the phase plane is divided into two semiplanes by the switching line. M means medium and S stands for small. In the table. B means big.5. The magnitude of the control output is associated with the distance of the state vector to the switching line. For example. the maximum value of ci should cover those states with their respective signs.5 Function between ci and s(e) 75 .1 for illustration purposes. Outside the boundary layer. respectively. The relationship between ci and the switching function s(e) is shown in Figure 5. the control was a highgain linear control. the control had a relay characteristic. NB means negative big. P stands for positive. Within each semiplane. A boundary layer was incorporated into the rule base to eliminate chattering in steady state. ci L L s(e) Figure 5.
More membership functions resulted in finer control.1: 7×7 Rule base of the sliding mode fuzzy controller Change in error (CE) NB PB PM Error (E) NM NS Z PS PM PM PM PB NS NM NS Z PS PS PM PB Z NM NM NS Z PS PM PM PS NB NM NS NS Z PS PM PM NB NM NM NM NS Z PS PB NB NB NB NM NM NS Z Z PS PM PM PB PB PB PS Z NS NM NB A 33×33 rule table was derived for the sliding mode fuzzy controller for the boost converter based on the principles above. There was a trade off between the size of the rule base and the performance of the sliding mode fuzzy controller. µce(ce[k])} and µe(e[k]). where wi = min{µe(e[k]).9) The center of average method was used to obtain the sliding mode fuzzy controller’s output δd[k]. ci was taken from the rule base.1. When using triangleshaped 76 . The weighing factor wi was obtained by Mamdani’s min fuzzy implication of µe(e[k]) and µce(ce[k]).9). which is given in (5. The change in duty cycle inferred by the ith rule zi is written in (5. µ ce ( ce [ k ])} × c i (5. and a more accurate control was achieved. The output of the controller had less variation when either of the inputs had small changes.Table 5. z i = w i × c i = min{ µ e ( e[ k ]). µce(ce[k]) are the membership degrees [10].10).4 Inference Mechanism and Defuzzification Method The results of the inference mechanism include the weighing factor wi and the change in duty cycle ci of the individual rule [4]. 5.
The Gaussian filter reduced the high frequency noise. When implementing the sliding mode fuzzy controller.6. Implementation of the sliding mode fuzzy controller had similar issues as the implementation of an ordinary fuzzy controller. The coefficients of the Gaussian filter were [1/4 1/2 1/4]. 77 . thus reducing the computation time. The filter was very simple to implement on the TI DSP. and it was characterized by narrow bandwidth. a shift instruction was used instead of calling the function to divide two numbers. The output of the sliding mode fuzzy controller was added to the previous sampling period’s duty cycle d[k1]. The noise was mainly introduced by the quantization errors and the switching action in the converter circuit. Because the coefficients of the filter were 1/2 and 1/4. δd [k ] = ∑w ×c i =1 i N i ∑w i =1 N (5. there are at most four rules that are effective at any one time.10) i 5. where ev[k1] = e[k1]/4 + e[k2]/2 + e[k3]/4 and was obtained using the Gaussian lowpass filter. The change in error was calculated using ce[k]=e[k]ev[k1]. The integration of the controller’s output increases the system type and improves the steadystate error.2 Implementation of Sliding Mode Fuzzy Controller A Simulink model for a sliding mode fuzzy controller for DCDC converters is shown in Figure 5. N = 4.membership functions. a Gaussian lowpass filter was added to ce[k] in steady state to filter out the undesired high frequency noise to smooth the controller’s output. therefore. sharp cutoff frequency and low overshoot.
The sliding mode fuzzy controllers for buck and boost converters were also implemented on the TI TMS320F2812 DSP. Figure 5. Experimental results will be presented in the next chapter.6 Simulink model of the system using sliding mode fuzzy controller for the DCDC converters 78 .
The PI controller was applied during steady state to reduce oscillation of the duty cycle and improve the system’s stability. The load transient response is shown in Figure 6. and the maximum transient error was 120 mV. The sampling and switching frequencies of both PID and PI controllers were 150 kHz.CHAPTER 6 EXPERIMENTAL RESULTS Experimental results for the DSPcontrolled buck and boost converters are presented in this chapter.3. The settling time is about 1 ms without any overshoot. respectively. 79 . 6.2 and 3.1 Buck Converter The start up transient response is shown in Figure 6.1. The PID controller was applied during start up to obtain a fast transient response.2 when the load current changed from 1. 6. PID and PI controllers were switched between transient and steady state to obtain desired responses. Experimental results for the buck and the boost converters are presented in this chapter.364 A to 0.16 A. The settling time was about 2 ms.1.1 Experimental Results for PID and PI Controllers Design and implementation of the PID and PI controllers for the buck and the boost converters were presented in Sections 3.
364 A to 0. 500 µs/div) 80 . 500 µs/div) Figure 6.2 Transient response for the buck converter using the linear PID and PI control method when the load changed from 1.Figure 6.1 Start up transient response of the buck converter using the linear PID and PI control method (5 V/div.16 A (100 mV/div.
6. 5 ms/div) 81 . There was a 100 mV steadystate error.2 Boost Converter The start up transient response is shown in Figure 6.48 A using the PID and PI control method is shown in Figure 6.3. The transient response when the load changed from 0.24 A to 0. The rise time is 15 ms. Figure 6.3 Start up transient response of the boost converter using the linear PID and PI control method (2 V/div. The settling time was about 10 ms.1.4. with about 10% overshoot.
24 A to 0.2).4 Transient response for the boost converter using the linear PID and PI control method when the load changed from 0.2 and 4.3 was implemented. g1 and the output scaling factor h of the fuzzy controller for the buck converter were tuned to be 1. the precision of the measured output voltage was reduced.2. Experiments from the buck converter indicated that if the scaling factor g0 of e[k] was less than 1. Experimental results of the fuzzy controllers for the buck and the boost converters are presented in this section. 2 ms/div) 6.3. It produced the duty cycle d[k] by adding a linear integrator to the output of the fuzzy controller shown in (4. and 1. g1 was tuned to 82 .Figure 6. the fuzzy controller shown in Figure 4. Therefore. respectively. respectively.48 A (200 mV/div. g0 was chosen to be 1.2 Experimental Results for Fuzzy Controllers Design and implementation of fuzzy controllers for the buck and the boost converters were presented in Sections 4. based on experimental results and simulation by Simulink.1 Buck Converter For the buck converter. 1. 6. The input scaling factors g0.
Experimental results verified that the addition of more membership functions and rules can provide a more accurate control.67 µs.000381. A fuzzy controller with a 7*7 rule base was also designed and implemented for the buck converter. The maximum transient error was 140 mV. Because the error of the output voltage was accumulated every sampling period and the sampling period was only 6. and the maximum transient error was 300 mV.16 A.5 and between Figure 6. The settling time was about 7 ms. which is very similar to the start up transient response in Figure 6. The load transient response is shown in Figure 6.8 indicates that a much shorter settling time and smaller maximum transient error was obtained by using the 17*17 rule base. Experimental results of linear PID and PI controllers for the buck converter were presented in the first section of this chapter. The settling time was about 1 ms with a little overshoot. The output scaling factor h was tuned to 1 to achieve a fast transient response without overshoot.6 when the load current changed from 1. which can reduce chattering and oscillation. The settling time is about 1 ms with a little overshoot.7. A comparison between Figure 6. The start up transient response is shown in Figure 6.be 1 based on simulation and experimental result. They are compared with the experimental results of the fuzzy controllers for the buck converter.5.2 and Figure 6.6 and Figure 6.16 A.8 when the load current changed from 1.6 show that the linear PID and PI 83 . Comparisons between Figure 6. The gain of the linear integrator KI was chosen to be 0.364 A to 0. a small value of KI was chosen. The load transient response is shown in Figure 6. The settling time was about 2 ms.1 and Figure 6. The start up transient response is shown in Figure 6.364 A to 0.5.
The change in the operating point only has impact on the magnitude of the buck converter’s small signal model. the linear PID and PI controller was able to achieve similar response as the fuzzy controller. Figure 6. Therefore.controller obtained similar results as the fuzzy controller using the 17*17 rule base.5 Start up transient response of the buck converter using the second fuzzy control method with 17*17 rule base (5 V/div. The poles and zero of the buck converter’s small signal model don’t change when the operating point varies. 500 µs/div) 84 .
500 µs/div) 85 . 500 µs/div) Figure 6.Figure 6.364 A to 0.7 Start up transient response of the buck converter using the second fuzzy control method with 7*7 rule base (5 V/div.6 Transient response for the buck converter using the second fuzzy control method with 17*17 rule base when the load changed from 1.16 A (100 mV/div.
and 1. the first method to get the duty cycle d[k] was used. It produced the duty cycle d[k] by (4.16 A (100 mV/div.2 Boost Converter For the boost converter.364 A to 0. the scaling factors g0. 1.1).8 Transient response for the buck converter using the second fuzzy control method with 7*7 rule base when the load changed from 1. 1 ms/div) 6. The start up transient response is shown in Figure 6. g1 and h of the fuzzy controller for the boost converter were tuned to be 1. To eliminate the steadystate error. Based on simulation by Simulink and experimental results. when the load current changed. which is shown in Figure 4. the output of the fuzzy controller was added to the previous 86 .2). In this method.5. respectively. However.000122.Figure 6.2.9. The new duty cycle was calculated by (4. there was 200 mV steadystate error. and the gain of the integrator KI was chosen to be 0.2.3 was also implemented. the fuzzy controller shown in Figure 4. The settling time was about 6ms with no overshoot.
ev[k1] was obtained by the Gaussian lowpass filter. The change in error was calculated using ce[k]=e[k]ev[k1]. where ev[k1] = e[k1]/4 + e[k2]/2 + e[k3]/4. 5 ms/div) 87 . The integration of the fuzzy controller’s output increased the system type and improved the steadystate error.9 Start up transient response of the boost converter using the second fuzzy control method (2 V/div. The noise was mainly introduced by the quantization errors and the switching action in the converter circuit. a Gaussian lowpass filter was added to decrease the noise in the difference of error ce[k] at steady state. The Gaussian filter reduced the high frequency noise. a shift instruction was used instead of calling the function to divide two numbers. The coefficients of the Gaussian filter were [1/4 1/2 1/4]. The filter was very simple to implement on the TI DSP. therefore reducing the computation time. and it was characterized by narrow bandwidth. sharp cutoff frequency and low overshoot. In addition. Because the coefficients of the filter were 1/2 and 1/4.sampling period’s duty cycle d[k1]. Figure 6.
The maximum transient error was about 400 mV. g1 and h were tuned to be 3. respectively. the output gain h had to be tuned to be very small to avoid oscillation during steady state.3 should result in zero steadystate error. The reason why the second topology resulted in steadystate error during load transients requires further investigation.When using the fuzzy controller configuration in Figure 4.2 and Figure 4. It was a combination of linear and nonlinear controller. An examination of the buck converter and the boost converter’s small signal models suggests that the boost converter’s small signal model is a nonlinear function of 88 . 2 and 0. The controller is a pure nonlinear controller. The advantage of the fuzzy control method applied to the boost converter was much more obvious than application to the buck converter.4 indicates that fuzzy control was able to achieve faster transient response without overshoot.24 A to 0. better rejection to load variation. The settling time was about 10 ms.3 and Figure 6. the linear integrator and the fuzzy controller were in parallel.3. However. Both structures in Figure 4.10.48 A is shown in Figure 6. While for the topology shown in Figure 4. Scaling factors g0.3. A comparison of the boost converter’s experimental results obtained using the fuzzy control method shown in Figure 6.2. In the first structure in Figure 4.0001373. experimental results from the boost converter indicated that steadystate error was observed during load transients by using the structure in Figure 4. because both have integrators to eliminate the steadystate error.9 and Figure 6. the integration was realized by accumulating the fuzzy controller’s output.10 and those obtained using the linear PID and PI control method shown in Figure 6. more stable steadystate response and less dependence on the operating point.2. The transient response of the boost converter when the load changed from 0.
Simulation by Simulink can provide some guidance and help to reduce the amount of time needed for tuning. both the shape and the position of the bode plot of the boost converter’s small signal model changes. the linear controller was not able to respond well for the boost converter. The linear PID and PI controller was designed only for the nominal operating point. since the fuzzy controller doesn’t require an exact mathematical model. it was not designed based on a specific operating point. one disadvantage of the fuzzy control method was that it required extensive tuning by the trial and error method. Figure 6. Therefore.24 A to 0. On the other hand.48 A (200 mV/div.the operating point. When the operating point varies. 2 ms/div) 89 .10 Transient response for the boost converter using the first fuzzy control method when the load changed from 0. It responded to the line and load variations more effectively than the linear controller. However. while only the magnitude of the buck converter’s small signal model shifts with the change of operating point [3].
6.3 Experimental Results for Sliding Mode Fuzzy Controllers
Experimental results of the sliding mode fuzzy controllers for both the buck converter and the boost converter are presented and evaluated in this section.
6.3.1 Boost Converter
The start up transient response of the boost converter using sliding mode fuzzy control when the input voltage varied from 4 V to 7 V is shown in Figure 6.11. The settling time was about 8 ms with very little overshoot at the nominal input voltage of 5 V. As the input voltage increased from 4 V to 7 V, the settling time decreased. When the input voltage was 7 V, the settling time was only 5 ms. The transient response of the boost converter using sliding mode fuzzy control when the load changed from 0.24 A to 0.48 A at different input voltages is shown in Figure 6.12. The settling time was about 10ms at nominal input voltage. The maximum transient error is about 400 mV. When the input voltage increased from 4 V to 7 V, the settling time decreased and the maximum transient error decreased. Transient responses in Figure 6.11 and Figure 6.12 indicate that the experimental result’s settling time and overshoot at nominal input voltage matched the desired dynamics represented by the switching function in (5.4). A settling time of less than or equal to 10 ms was achieved. When the input voltage increased, the settling time for both the start up and load transient response decreased. The output voltage was stable in steady state.
90
4
3 2 1
1—Vin=4V 2—Vin=5V 3—Vin=6V 4—Vin=7V
Figure 6.11 Start up transient response of the boost converter using sliding mode fuzzy control with different input voltage (2 V/div, 5 ms/div)
4
3
1
2
1—Vin=4V 2—Vin=5V 3—Vin=6V 4—Vin=7V
Figure 6.12 Transient response of the boost converter using sliding mode fuzzy control when the load current changed from 0.24 A to 0.48 A (200 mV/div, 2 ms/div) 91
When using ordinary fuzzy controllers, two structures of fuzzy controllers were applied to the prototype boost converter during start up and steady state to obtain both fast transient and stable steadystate response without steadystate error. While for the sliding mode fuzzy controller, only one structure was used for all operating points. This indicates that the sliding mode fuzzy controller is able to perform well under operating point variations.
6.3.2 Buck Converter
The start up transient response using the sliding mode fuzzy controller when the input voltage varies from 17 V to 23 V is shown in Figure 6.13. The settling time is about 2 ms with very little overshoot at a nominal input voltage of 20 V, while the designed settling time is only 1 ms. The reduction of the speed of the transient response was mainly caused by the parallel linear integrator. As the input voltage increased from 17 V to 23 V, the settling time remained the same. The overshoot at the nominal input voltage was 3.3%, and increased a little when the input voltage increases. The steadystate response of the buck converter and the PWM signal are shown in Figure 6.14 Note that there is no oscillation of the duty cycle in steady state. The load transient response of the buck converter when the load decreased from 0.96 A to 0.48 A is shown in Figure 6.15. When the input voltage varied from 17 V to 23 V, the settling time remained at about 4 ms. The maximum transient error was about 160 mV when the input voltage was 17 V, and was about 140 mV when the input voltage was 23 V. When the load increased from 0.48 A to 0.96 A, the load transient response of the buck converter is shown in Figure 6.16. The settling time remained at about 4 ms, which 92
13 Start up transient response of the buck converter using sliding mode fuzzy controller with different input voltage (2 V/div. 3 2 1 1—Vin=17V 2—Vin=20V 3—Vin=23V Figure 6.16. From the load transient responses in Figure 6. and was about 120 mV when the input voltage was 23 V. it can be observed that variations in settling time and the maximum transient error with changes in the input voltage were small.15 and Figure 6.is the same as the settling time when the load current decreases. The maximum transient error was about 140 mV when the input voltage was 17 V. 1 ms/div) 93 .
96 A to 0.48 A with different input voltage (100 mV/div. 1 ms/div) 94 .14 Steadystate response of the buck converter with the PWM signal (5 V/div.15 Load transient response of the buck converter using sliding mode fuzzy controller when the load changed from 0. 5 µs/div) 1 3 2 1—Vin=17V 2—Vin=20V 3—Vin=23V Figure 6.Figure 6.
95 .4.48 A to 0.3 1 2 1—Vin=17V 2—Vin=20V 3—Vin=23V Figure 6.16 Load transient response of the buck converter using sliding mode fuzzy controller when the load changed from 0. 1 ms/div) 6. 6. the experimental results of the buck converter using the ordinary fuzzy controller when the input voltage changed were evaluated. The overshoot increased when the input voltage increased from 17 V to 23 V. the settling time remained the same. When the input voltage increased from 17 V to 23 V.96 A with different input voltage (100 mV/div.17.4 Comparison of Experimental Results of Linear and Nonlinear Control Methods Experimental results of linear and nonlinear control methods applied to buck and boost converters are compared in this section.1 Buck Converter For comparison purposes. The settling time at the nominal input voltage of 20 V was about 8 ms with about 7% overshoot. The start up transient response when the input voltage varied from 17 V to 23 V is shown in Figure 6.
96 A is shown in Figure 6.18.The load transient response of the buck converter using the ordinary fuzzy controller when the load current decreased from 0. and the maximum transient error remained at about 60 mV.96 A to 0. the settling time remained at about 1 ms.48 A to 0.8 ms and maximum transient error remained at about 60 mV. When the input voltages changed from 17 V to 23 V. 1 ms/div) 96 .17 Start up transient response of the buck converter using ordinary fuzzy controller with different input voltage (2 V/div. The load transient response of the buck converter when the load current increased from 0.48 A is shown in Figure 6. 3 1 2 1—Vin=17V 2—Vin=20V 3—Vin=23V Figure 6. the settling time remained at about 0.19 When the input voltage increased from 17 V to 23 V.
48 A with different input voltage (100 mV/div.1 3 2 1—Vin=17V 2—Vin=20V 3—Vin=23V Figure 6. 1 ms/div) 3 2 1 1—Vin=17V 2—Vin=20V 3—Vin=23V Figure 6.18 Load transient response using ordinary fuzzy controller when the load changed from 0.19 Load transient response using ordinary fuzzy controller when the load changed from 0. 1 ms/div) 97 .96 A with different input voltage (100 mV/div.96 A to 0.48 A to 0.
The derivative term in a PID controller is susceptible to noise and measurement error of the system. the settling time remained at about 1 ms.48 A as shown in Figure 6. and the maximum transient error remained in the range of 40 to 60 mV.22. Both the settling time and overshoot increase when the input voltage increased from 17 V to 23 V. PID and PI controllers are switched between transient and steady state to obtain fast response without oscillation in steady state.For comparison purposes.22. which could result in oscillation of the duty cycle during steady state. The load transient response using the PID/PI controller is shown in Figures 6. the settling time remained at about 1 ms. during transient operation. respectively. the derivative term is needed to reduce the settling time by predicting the changes in error. The start up transient response using the PID/PI controller is shown in Figure 6. a PID/PI controller was also implemented for the buck converter. When the load increased from 0.48 A to 0.20 The settling time was about 4 ms when the input voltage was 20 V.96 A as shown in Figure 6.96 A to 0. and the maximum transient error remained at about 60 mV.21. 98 . When the load decreased from 0.21 and 6. Therefore. However.
48 A with different input voltage (100 mV/div.3 1 2 1—Vin=17V 2—Vin=20V 3—Vin=23V Figure 6.21 Load transient response using PID/PI controller when the load changed from 0. 1 ms/div) 2 1 3 1—Vin=17V 2—Vin=20V 3—Vin=23V Figure 6.20 Start up transient response of the buck converter using PID/PI controller with different input voltage (2 V/div. 1 ms/div) 99 .96 A to 0.
48 A to 0.96 A with different input voltage (100 mV/div.3 2 1 1—Vin=17V 2—Vin=20V 3—Vin=23V Figure 6. ordinary fuzzy control and PID/PI control for the buck converter is quantified in Table 6.1. Furthermore.22 Load transient response using PID/PI controller when the load changed from 0. it can be observed that the start up transient response varied the least using sliding mode fuzzy control when the input voltage changed from 17 V to 23V. An examination of the experimental results shows that the sliding mode fuzzy control obtained the shortest settling time and smallest overshoot during a start up transient. 1 ms/div) A comparison of the performance between the sliding mode fuzzy control. 100 .
Ordinary fuzzy control and PID/PI control obtained very similar load transient response for both load increase and load decrease. the load transient response varied very little.3 4 150 4 110 Ordinary fuzzy control 8 7 0. During a start up transient.8 60 1 60 PID/PI control 4 10 1 60 1 40 Settling Load time (ms) Load decrease Maximum Transient error(mV) response Settling Load time (ms) increase Maximum error(mV) Experimental results for load transients using different control methods were also evaluated and compared. Ordinary Fuzzy Control vs.Table 6. The comparison indicates that sliding mode fuzzy control obtained a more satisfactory start up transient response than ordinary fuzzy control and PID/PI control methods. the settling time obtained using sliding mode fuzzy control was much longer than the settling time obtained using the other two control methods. while the load transient response using sliding mode fuzzy control was less satisfactory than the other two control methods. On the other hand. PID/PI Control for Buck Converter Experimental results Start up transient response Settling time (ms) Overshoot(%) Sliding mode fuzzy control 2 3.1: Comparison of Performance of Sliding Mode Fuzzy Control vs. When the input voltage changed from 17 V to 23 V. The maximum transient error was also the largest for the sliding mode fuzzy control among all three control methods. the small 101 .
during load transients. Because sliding mode fuzzy control can yield a very robust closedloop system under plant uncertainties like ordinary sliding mode control.2 Boost Converter Experimental results obtained using linear and nonlinear control methods are compared for the buck and boost converters. all three control methods obtained the same settling time. Both start up transient response and load transient response are compared. For the buck converter. while the PID controller had the longest settling time. For the load transient response. fuzzy control and sliding mode fuzzy control for the boost converter. For the start up transient response. while it takes much less time to tune the sliding mode fuzzy controller. Therefore.2 compares the performance of PID control. While for the boost converter. 6.signal model of the converter changes dramatically. the small signal model of a buck converter changes less dramatically than during a start up transient. The maximum transient error was actually smaller for the 102 . Table 6. On the other hand. linear controllers such as PID control are able to respond more effectively than sliding mode fuzzy control.4. linear and nonlinear control methods obtained similar experimental results. it is able to respond to start up transient more effectively than ordinary fuzzy control and PID control. there was a clear difference between the results from the linear and nonlinear control methods. A possible reason that ordinary fuzzy control obtained faster load transient response than sliding mode fuzzy control is that the ordinary fuzzy controller had been tuned extensively using a trial and error method. There was a 10% overshoot with the PID control and no overshoot for the fuzzy and sliding mode fuzzy control. the fuzzy controller obtained the shortest settling time.
2: Comparison of Performance of PID Control. but there was a 100 mV steadystate error for the PID control. The fuzzy control and sliding mode fuzzy control obtained very similar experimental results for the boost converter. it responded to the line and load disturbances more effectively than linear controllers. and Sliding Mode Fuzzy Control for the Boost Converter Experimental Results Start up transient response Settling time (ms) Overshoot (%) Settling time (ms) Maximum transient error (mV) Steadystate error (mV) PID control 15 10 10 200 100 Fuzzy control 6 0 10 400 0 Sliding mode fuzzy control 8 0 10 400 0 Load transient response 103 . the design of sliding mode fuzzy control was more systematic. Therefore. An examination of the small signal models for the converters shows that only the magnitude of the buck converter’s small signal model shifts with the change of operating point. the linear PID controller was not able to respond well for the boost converter. However. Table 6. Fuzzy Control. both the shape and the position of the frequency response changes.PID control. and system’s response was easier to predict. Since the fuzzy controller is nonlinear and adaptive in nature. But for the boost converter.
The PID and PI controllers were then converted into discrete time.CHAPTER 7 CONCLUSION AND FUTURE WORK Issues in the design and implementation of digital controllers for buck and boost converters have been discussed in this dissertation. Linear controllers are designed based on the small signal models. the small signal models change due tochanges in operating points. The disadvantages are: performance of the controller is dependent on the operating point and the controller needs to be modified to obtain both fast and stable response. Therefore. Generally. their performance is dependent on the working point. Since small signal models obtained using state space averaging techniques are linear approximations of the local behavior of the system. Advantages of frequency response techniques are: design and analysis are relatively easy and implementation is straightforward on a DSP. The performance of a linear controller is dependent on the load and working point. Both linear and nonlinear techniques have been reported in this dissertation. these methods fall into two categories: linear and nonlinear control methods. the parasitic elements. Analog PID and PI controllers were designed using the frequency response method based on the small signal models of buck and boost converters. and the load and line conditions. There are many control methods that may be used to design digital controllers for DCDC converters. 104 .
The second nonlinear control method is sliding mode fuzzy control. and fuzzy controllers are able to adapt to changes in operating points. It also has advantages of its own that cope with the problems in the sliding mode control and fuzzy control design and implementation. fixed point DSP. the most popular and widely used technique in control systems is fuzzy control. Sliding mode fuzzy control combines the advantage of sliding mode control and fuzzy control. nonlinear control techniques. The controller was then tuned using a trial and error method to obtain satisfactory response. complexities associated with nonlinear mathematical analysis are relatively low. The disadvantages of fuzzy controllers are: extensive tuning may be required based on trial and error method and the system’s response is not easy to predict. The advantages of fuzzy controllers are: exact mathematical models are not required for the design of fuzzy controllers.To achieve a stable steadystate response and fast transient response under varying operating points. The F2812 DSP is a 32bit. Experimental results 105 . it is able to adapt to varying operating points. In this dissertation. were applied to buck and boost converters. The disadvantage is that some tuning may still be required. including fuzzy controllers and sliding mode fuzzy controllers. nonlinear controllers were used to control buck and boost converters. Fuzzy controllers were designed based on the general knowledge of the converters. Since a fuzzy controller is a nonlinear controller. Among the various techniques of artificial intelligence. All the digital controllers were implemented on a TI TMS320F2812 Digital Signal Processor (DSP). The advantages of sliding mode fuzzy controllers are: the design of sliding mode fuzzy controller is more systematic and the system’s response is easier to predict.
For the buck converter. The network can be trained on typical signals and then tested on an experimental testbed. the inductor current was estimated to achieve predictive digital currentmode 106 . and if it can be modified for large line disturbances. it is quite challenging to implement digital control for the current loop due to delay of the sampling and computation process. To solve this problem. Several areas for future research are possible. genetic algorithm and adaptive control can be applied to DCDC converters. there was a clear difference between the results from the linear and nonlinear control methods. It is interesting to see how the fuzzy controller will respond to a large variation of input voltage. However. the gains and rule table of the fuzzy controller could be switched between transient and steady state. Nonlinear control methods obtained more satisfactory responses for the boost converter. Simulation results may be compared with experimental results for DCDC converters. Currentmode control is typically a two loop system: an inner current loop and outside voltage loop. In order to obtain both fast transient response and stable steadystate response. The dynamics of the voltage loop are much slower than that of the current loop. Digital currentmode control could also be investigated. Neural networks have learning and selforganizing abilities to adapt to nonlinear systems. Other nonlinear control methods such as neural network. linear and nonlinear control methods obtained similar experimental results. Therefore voltage loop can be easily implemented using digital signal processors (DSP) or microcontrollers.obtained using linear and nonlinear control methods were compared for the buck and boost converters. Fuzzy control for DCDC converters could continue to be investigated. While for the boost converter. Adaptive fuzzy controllers could be investigated.
Nowadays many FPGAs also have builtin DSP function in order to improve their computation capability. 107 . FPGAs tend to be more flexible than DSPs because the user is able to specify their size. Implementation issues of digital controllers may be investigated. Digital controllers may be implemented on both FPGAs and DSPs in order to compare the advantage and disadvantage of each implementation method.control [51]. Sampling algorithms may be developed in order to obtain values of inductor current in real time. The advantage is tremendous over analog control. a digital controller could monitor the temperature of different parts of the converter to perform thermal management. Another research issue is related to the efficiency of the converters. In addition. The operating mode can also be shifted between continuous mode and discontinuous mode by changing the switching frequency. such as forward converters. flyback converters and pushpull converters. thermal management and supervision can all be integrated on a single DSP chip. DSPs with faster clock frequency and analogtodigital converters are becoming available. Besides DSPs. With the advance of VLSI technology. Therefore. Functions of control regulation. It will also be interesting to investigate digital control of transformer isolated converters. the converter can be controlled in such a way that optimum efficiency is achieved under various operating points. FPGAs and custom designed integrated circuits are also viable solutions for the implementation of digital controllers. it would be interesting to investigate digital currentmode control that uses directly measured inductor current values. Since intelligence can be conveniently included in DSPs. speed and price.
Therefore. 108 . research in digital control was mainly conducted in universities and research institutes. In the past. several issues in digital control may be investigated in the future.To summarize. there are rapidly increasing interests in digital control from the industry in order to achieve small space and high efficiency in DCDC converters. collaboration between the academia and the industry could achieve tremendous development and application of digital control in the future. In the recent years.
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