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P
haselocked dielectric resonator oscilla
tors (DRO) are essential components in
high frequency microwave links where
phase noise is a crucial parameter. The main
advantage of a phaselocked DRO (PLDRO)
source over an ordinary synt hesizer is it s
phase noise characteristic. This is due to the
voltagetuned DRO’s (VtDRO) high quality
factor tank circuit (a dielectric resonator) on
one hand, and direct locking to a high fre
quency reference harmonic by means of a mi
crowave sampling phase detector (SPD) on
the other. In this way, the noise floor contribu
tion of prescalers and frequency dividers used
in an ordinary synthesized frequency genera
tor is avoided within the loop band. In addi
tion, the freerunning phase noise characteris
tic of the VtDRO gives the advantage of low
phase noise performance outside the loop
bandwidth at high offset frequencies. This
characteristic is most evident with GaAsFET
DROs, where the freerunning phase noise
spectrum rolls off at a –30 dB per decade rate.
Furt hermore, t he possibilit y of wideband
phase locking of the VtDRO provides good
shortterm stability (for instance, low micro
phonicity) for this frequency source. However,
unlike a standard synthesizer, a PLDRO re
quires a special frequency acquisition and
locking technique for correct and reliable op
eration. In this article, phase noise considera
tions, a loop optimization procedure and a
specific acquisition technique for PLDROs
are explained.
ACQ U I SI TI O N CI RCU I T REQ U I REM EN TS
Sweepi ng Range Consi derat i ons
Fr equency acquisit ion can be accom
plished by sweeping the VtDRO, as shown in
the block diagram in Figure 1. The SPD dri
ven by the reference signal generates a comb
like spectrum. At the instant the VtDRO fre
quency coincides with the reference signal’s
desired harmonic, the loop will acquire a sta
ble lock and will remained locked as long as
the search signal is not too fast or large. The
UNDERSTANDING
PHASELOCKED DRO
DESIGN ASPECTS
AVI BRILLANT
Optomic Microwaves Ltd.
Migdal Ha’Emek, Israel
M
IC
R
O
W
AVE JO
U
R
N
A
L
E
D
IT
O
RIAL B
O
A
R
D
REVIEWED
Vt  DRO
V
t une
TU N I N G SCREW
I
SW
C
R
1
R
2
LO CK
DETECT
CI RCU I T
LO CK
DETECT
ALARM
CU RREN T I N JECTI O N
FO R SWEEP/ SEARCH
SI GN AL
f
PLO
· N
x
f
REF
f
REF
LO O P FI LTER
AN D AI DED
SEARCH /
ACQ U I SI TI O N
CI RCU I T
PLDRO
O U TPU T
H I GH STABI LI TY AN D
LO W PH ASE N O I SE
REFEREN CE SO U RCE
( TCXO )
M I CRO WAVE
SAM PLI N G
PH ASE
DETECTO R
Fig. 1 The PLDRO block
diagram concept.
w
fr equency spacing bet ween each
comb harmonic is equal to the tem
peraturecompensated crystal oscilla
tor’s (TCXO) frequency as defined in
f(n) = f(TCXO)• n • δ(n – N) (1)
f(TCXO) = f(TCXO)
• {n • δ(n – N) – [(n – 1)
• δ([n – 1] – [N – 1])} (2)
Hence, to prevent false lock on an
undesired comb harmonic, the tuning
range ∆f of the VtDRO should satis
fy the condition
∆f < 2 • f(TCXO) (3)
For a symmetrical search, the opti
mum V
tune
value of the VtDRO (that
is, t he value at which t he desired
phaselocked oscillator frequency is
reached) should be half of the control
voltage swing range (for instance, 1/2
V
cc
, where V
cc
is the supply voltage to
the active loop filter). This value can
be easily obtained by mechanically
tuning the VtDRO tuning screw. In
the same way, the search signal volt
age should be pr oper ly offset
(through a suitable bias voltage at the
acquisition and lock circuitry) by a
value equal t o t he same opt imum
V
tune
. It is also important to use a suf
ficiently high frequency reference
signal so that the sweep can be made
wide enough to cover the tempera
ture drifts of the VtDRO.
Frequency Acqui si t i on
The sweep can be applied as an
updown ramp voltage directly to the
VtDRO tuning input. For a perfect
secondorder loop with active inte
grator, a constant current I
sw
is insert
ed to create a triangle sweep voltage
with switching polarities. Such a tri
angle sweep signal is due to tracking
considerations.
The steadystate phase error θ
e
= θ
i
–
θ
o
after all transient effects have ter
minated (t→∞) is given by
where
K
V
= VtDRO modulation
sensitivity (in radians/second
per volt)
K
d
= sampling phase detector
output sensitivity (in volts per
radian)
H(s) = loop filter transfer function
θ
θ
e
i
V d
s
s s
s K K H s
( )
·
( )
+
( )
( ) 4
In the case of a secondorder PLL
with an active loop filter, H(s) is given
by
where
τ
1
= R
1
C (6)
τ
2
= R
2
C (7)
Substituting these expressions into
Equation 4 and using the LaPlace fi
nal value theorem produces
where the natural loop frequency ω
n
and the loop damping factor ξ are
given by
Now suppose that the input frequen
cy is linearly changing with time at
the rate of ∆ω
⋅
rad/sec
2
such that
Hence, θ(s) is given by the relevant
LaPlace transform
Substituting Equation 12 into Equa
tion 8 using the final value theorem
yields the steadystate phase error ac
cumulated during a linear frequency
sweep
(also called dynamic tracking error).
Such input behavior might arise from
accelerated motion between a trans
lim lim
˙
˙
( )
t
e
s
n n
e
n
t s
s
s
s s
t
rad
→∞ →
( )
·
+ +
⇒
( )
·
θ
ω
ξω ω
θ
ω
ω
0
2
3
2 2
2
2
13
∆
∆
θ
ω
i
s
s
( )
·
∆
˙
( )
3
12
θ ω
θ
ω
i
i
dt
t
t
· ∫ ∫
⇒
( )
·
1
2
11
2
∆
˙
( )
ξ
ω τ
·
n 2
2
10 ( )
ω
τ
n
V d
K K
·
1
9 ( )
θ
θ
ξω ω
e
i
n n
s
s s
s s
( )
·
( )
+ +
2
2 2
2
8 ( )
H s
V s
V s
s
s
o
i
( )
·
( )
( )
·
+
– ( )
1
5
1
2
τ
τ
TECHNI CAL FEATURE
mit t er and receiver, Doppler fre
quency shift or fr equency sweep
modulation, which is the case here.
For a sinusoidal char act er ist ic
phase detector, this expression is
Note that the sinus function cannot
exceed ±1. Thus, the maximum per
mitted sweep rate limit is given by
However, this condition is not satis
factory; Viterbi discovered that acqui
sition is not certain even if the loop is
noise free, and there is a possibility
for acquisition only if
Otherwise, it will not be locked.
Frazier and Page provided empiri
cal data that indicate the sweep rate
should satisfy a particular condition
for acquisit ion in t he presence of
noise. Gardner’s experience added
some changes, resulting in
In this case, 0.707 ≤ ξ ≤ 1 and the
loop signaltonoise ratio (SNR
L
) is
less than 6 dB.
Two other experimental formulas
were suggested by Frazier and Page.
for 90 percent acquisition probability,
while ρ represents SNR
L
. In most
cases, a probability of 0.9 is too low.
For a better design where E(B
L
T
S
) =
10
4
cycle slips, the normalized sweep
rate is given by
∆
˙
– . ( )
%
ω
ω
ρ
ξ
N
2
90
1
2
0 707 17 ≈ ∀ >
∆
˙
–
( ) ω ω <
]
]
]
]
1
2
1 2
16
2
n
L
SNR
∆
˙
ω
ω
<
n
2
2
∆ ∆
˙ ˙
( ) ω ω ω ω · ⇒ <
n n
2 2
15
sin
˙
( ) θ
ω
ω
e
n
·
∆
2
14
0 . 5 9
0 . 4 9
0 . 3 9
0 . 3 0
0 . 2 0
0 .1 0
0
1 2 1 1 1 0 9 8 7
SI GN AL TO  N O I SE RATI O ρ
i
, ρ
j
EQ U ATI O N 1 7 EQ U ATI O N 1 8
6 5 4 3 2
N
O
R
M
A
L
I
Z
E
D
S
W
E
E
P
R
A
T
E
S
R
i
,
S
R
j
v Fig. 2 Normalized sweep rate
as a function of SNR
L
.
Figure 2 shows the normalized sweeping rate as a func
tion of loop SNR
L
.
Sweepi ng and Locki ng
The PLDRO search and locking circuit, shown in Fig
ure 3, consists of two feedback paths: a negative feedback
path, which is the locking circuit (OPA2loop filter OPA3
high input impedance buffer), and a sweeping circuit for
aided acquisition as the positive feedback (OPA1Schmitt
trigger comparator, OPA2integrator). A better under
standing of this circuit is possible by referring to it as a tri
angle wave generator circuit. Hence, the secondorder
loop design formulas together with the triangle generator
design formulas are applicable.
Suppose that in the moment t
0
= 0 the output of OPA1
is V
cc
while OPA1 is in its positive saturation (OPA1 is a
comparator). Hence, the current to the invert input of
OPA2 is
(This offset voltage has several names and meanings, for
example, V
offset
= V
tunelocking
= V
bias
.)
The constant positive current in Equation 19 will cause
a negativegoing liner voltage ramp at the output of OPA2
due to the charge of C
1
. At that time (using superposition)
the voltage at the noninverting input of the comparator
OPA1 is given by
V t
V R
R R
V t R
R R
OPA
CC
O
OPA
( )
·
+
+
( )
+
+ 1
4
6 4
2
6
6 4
20 ( )
I
V V
R
SW
CC offset
·
–
( )
5
19
∆
˙
–
–
. . . ( )
/
ω
ω
ρ
ρ ρ
n
2
1 2
1
2
4
6 9 5 0 4 9 5 18 ·

.
`
,
< < >
¹
'
¹
¹
¹
¹
'
¹
¹
¹
where
V
o
(t)
OPA2
= the output voltage from OPA2
at a given time t
When, during the negativegoing ramp of OPA2, the volt
age V(t)
OPA1+
at the comparator noninverting input be
comes smaller than V
ref
at the comparator OPA1 inverting
input, its output switches to 0 V. At that moment the cur
rent to the inverting input of the integrator OPA2 be
comes
Since V
offset
was chosen to be 1/2 V
cc
, the current changes
its sign and the capacitor C is discharged. When the volt
age V(t)
OPA1+
reaches a higher value than V
ref
, the charge
of C
1
will begin and vice versa. Figure 4 shows the trian
gle sweep signal generated by this circuit. The sweep rate
∆
⋅
ω is defined by the triangle signal slope. Thus, the trian
gle frequency is onehalf the sweep rate.
The next objective is to calculate the sweep frequency
from the circuit parameters. The current I
SW
through R
5
is equal to the charging current of C
1
and is related to the
voltage V
c
(t) across the capacitor C
1
by
On the other hand,
Since V
CC
and V
offset
are constants, the charge is linear as
already observed. Substituting Equation 22 into Equation
23 and deriving it by t yields, as expected,
Hence, the charging equation (after substituting Equation
24 into Equation 22 and integrating the result) is
V t
V V
R C
dt
O
OPA
CC offset
t
t
( )
·
∫ 2
5 1
0
1
25
–
( )
dV t
dt
dV
dt
O
OPA C
( )
·
2 1
24 – ( )
V
dV t
dt
C R V t V t
offset
C
C O
OPA
– – ( )
1
1 2 1
2
23
( )
( )
·
( )
V V
R
dV t
dt
C
CC offset
C –
– ( )
5
1
1
22 ·
( )
I
V
R
SW
offset
·
–
( )
5
21
TECHNI CAL FEATURE
BEAT
N O TE
R6
R5
0 V
0 V
R9
R3
−
+
−
+
−
+
R4
R2
R1
I
SW
C1
O PA2
O PA3
O PA1
SAM PLER
O FFSET FO R
V
t
O PTI M U M
V
CC
V
CC
V
CC
N U LL
ADJU ST
V
t une
Vt  DRO
v Fig. 3 The aided search/acquisition circuit.
•
·
4 π
f
Vt  DRO max
− F
Vt  DRO min
T
∆ω
f
Vt  DRO max
TI M E ( t )
V
t

D
R
O
F
R
E
Q
U
E
N
C
Y
T/ 2
V
CC
/ 2
V
CC
T
f
Vt  DRO min
f
Vt  DRO l ocke d
•
∆ω
v Fig. 4 The triangle sweep signal.
The result is a linear ramp that cre
ates the triangle wave described by
To calculate T/2, which is half of
the triangle duration, there is a need
to calculate the charging time until
the voltage at the noninverting input
of the comparator OPA1 reaches the
reference voltage value applied at the
inverting input of the same opera
tional amplifier. This equation is ex
pressed as
Thus,
V t
R R
R
V
V R
R R
O
OPA
ref
CC
( )
·
+
+

.
`
,
2
6 4
6
4
6 4
28 – ( )
V t V
V R
R R
V t R
R R
OPA
ref
CC
O
OPA
( )
· ·
+
+
( )
+
1
4
6 4
2
6
6 4
27
–
( )
V t
R C
V V t t V
O
OPA
CC offset
( )
·
( )( )
+
( )
2
5 1
1 0 0
1
0
26
– –
( )
Combining Equation 26 with Equa
tion 28 and writing the expression (t
1
– t
0
) as ∆T and assuming V
O
(0) = 0
results in
Therefore, the triangle frequency is
given by
Bearing in mind that optimum V
tune
for locking is V
CC
/2 and that V
ref
=
V
CC
/2 since a symmetrical sweep is re
quired, Equation 29 can be simplified
so the triangle frequency is given by
In some cases the sweep circuit
may not operate due to improper de
sign of the comparator’s OPA1 hys
teresys. The hysteresis plot, generat
ed using superposition calculation, is
shown in Figure 5.
When the loop is locked the signal
voltage coming from the sampling
phase detector is at its maximum value.
The current through R
4
is higher than
the current through R
5
and, hence, the
negative feedback becomes dominant.
However, when the loop is out of lock,
the sampler output voltage drops. The
current through R
5
generated by the
Schmitt trigger OPA1 becomes domi
nant and a new search triangle signal
begins until the loop acquires lock.
When the loop is locked the negative
feedback becomes dominant, the posi
tive feedback path is
suppressed and the
triangle sweep wave
is stopped. This de
script ion dem
onstrates how a con
trol system automati
cally operat es it s
positive feedback to
bring the system to a
stable point where
t he negat ive feed
back suppresses the
posit ive feedback,
stabilizing the sys
tem.
f
R
R R R C
·
( )
6
6 4 5 1
2
31
–
( )
f
T
·
1
2
30
∆
( )
∆T V
V R
R R
R R
R
R C
V V
ref
CC
CC ref
·
+

.
`
,
•
+ 
.
`
,
–
–
( )
4
6 4
6 4
6
5 1
29
PH ASE N O I SE
Phase noise at the output of a phase
locked loop (PLL) can be calculated as
a root mean square summation of all
the noise generators’ variances. The
noise generators considered here are
the phase detector, VCO prescalers and
dividers (if any), loop filter (operational
amplifier), reference dividers or step
recovery diode (SRD) that drive the
microwave sampler in the case of PL
DROs, VCOs and TCXOs.
The noise contributions injected
into a PLL are shown in Figure 6.
For convenience, these noise term
variances (rms values) in V/√Hz
__
have
been indicated as
φ
nR
= reference TCXO phase noise
φ
nM
= reference divider or SRD
phase noise
φ
nO
= total output phase noise
φ
nN
= emittercoupled logic (ECL)
divider phase noise
φ
Nvco
= VCO phase noise
variance
V
nD
= phase detector phase
noise
V
nLPF
= loop amplifier phase
noise
The objective now is to determine
the phase noise transmission function
for each noise generator. Using con
trol theory notation, the applicable
noise equations are
where
K
VCO
= VtDRO modulation
sensitivity (in radians/second
per volt)
K
PD
= phase detector or sampling
phase detector output
sensitivity (in volts per
radian)
H(s) = loop filter transfer function
N = prescaler (and VCO
frequency divider) ratio
M = reference divider ratio
After some manipulations, the ex
pression becomes
φ
φ
φ ' ( )
nO
nO
nN
N
· + 35
φ
φ φ
neq PD nLPF
VCO
nVCO nO
V V H s
K
s
+ +
( ) ( )
[ ]
+ · ( ) 34
φ φ φ
neq ni nO PD
K ·
( )
– ' ( ) 33
φ
φ
φ
ni
nR
nM
M
· + ( ) 32
TECHNI CAL FEATURE
V
O
(
t
)
O
P
A
1
(
V
)
V
CC
V
O
( t ) O PA2 ( V)
V
Tr rmar
< V
O  O PA2
0 < V
Tr min
< V
O  O PA2
R
6
− R
4
Vre f
0
SWEEP
RAN GE
R
6
2 R
4
Vre f
R
6
R
6
+ R
4
Vre f
R
6
vFig. 5 The OPA1 comparator’s hysteresis.
TCXO
φ
nR
Σ Σ Σ Σ
φ
nN
φ
ne q,
θ
e
φ
nVCO
φ
nO
φ
nM
V
nPD
V
nLPF
H ( s)
K
VCO
/ S K
PD
θ
i
θ'
i
θ'
o
φ
θ'
nO
θ
o
1 / N
1 / M
Σ Σ
v Fig. 6 Noise generators within a synthesizer.
Rearranging the variables in a way that φ
nO
is the subject
of the formula, the PLL phase noise at its output becomes
This result is interesting because it gives the transfer
function for each noise generator within the loop referred
to the output. Furthermore, it can be easily investigated
for phase noise optimization.
Since each noise term is uncorrelated, the phase noise
power spectral density may be obtained from Equation 37 by
mean square addition of the individual sources. The first ex
pression of this formula should be changed in sign from φ
nM
– φ
nN
to φ
nM
+ φ
nN
since these variances are not correlated.
Reference Source Noise Contribution
The TCXO output phase noise contribution to the out
put phase noise is given by
Assuming that H(s) describes an active filter, using Equa
tions 5, 6, 7, 9 and 10 transforms Equation 38 into
Equation 39 shows that the reference source (TCXO) phase
noise within the loop is multiplied by the closedloop lowpass
transmission function with a –20 dB per decade slope, and
will be attenuated outside the loop. Hence, the closedloop
sharpness defines the amount of the TCXO phase noise that
is enhanced outside the loop bandwidth. For this reason, the
damping factor ξ of the loop has a significant impact on the
phase noise characteristic outside the loop bandwidth. This
σ
φ ξω ω
ξω ω
nTCXO
nR n n
n n
M
S
s s
· •
+
+ +
2
2
39
2
2 2
( )
σ
φ
nTCXO
nR
PD VCO
PD VCO
M
K K H s
s
K K H s
Ns
· •
( )
]
]
]
]
+
( )
]
]
]
]
1
38 ( )
φ
φ
φ φ
φ
nO
nR
nM nN
PD VCO
PD VCO
nPD nLPF
VCO
PD VCO
nVCO
PD VCO
M
K K H s
s
K K H s
Ns
V V
H s K
s
K K H s
Ns
K K H s
Ns
· +
]
]
]
•
( )
]
]
]
]
+
( )
]
]
]
]
+ +
[ ]
•
( )
]
]
]
]
+
( )
]
]
]
]
+
+
( )
–
1
1
1
1
]
]
]
]
( ) 37
φ
φ
φ
φ
φ
φ
nO
nR
nM
nO
nN
PD nPD nLPF
VCO
nVCO
M N
K V V H s
K
s
· +

.
`
,
+

.
`
,
]
]
]
]
¹
'
¹
¹
¹
¹
'
¹
¹
¹
• + +
¦ ( )¦
• +
–
( ) 36
same conclusion also holds for the reference dividers or
SRD, prescalers, loop amplifier and phase detector.
Well inside the loop bandwidth (where the loop gain is
high — K
PD
K
VCO
H(s) → ∞), the output phase noise stan
dard due to the TCXO can be approximated as
where
N = divider and prescaler ratio
M = reference divider ratio
In the actual case of a PLDRO, N = 1 and M = 1/M
SRD
,
where M
SRD
is the order of the reference frequency har
monic at which the VtDRO is locked. Thus, for a PLDRO it
holds that
σ
nTCXO
= M
SRD
φ
nR
(41)
Frequency Di vi der
Noi se Cont ri but i on
The 1/N and 1/M frequency dividers’ contribution to
the output phase noise is given by a similar expression
that is almost identical (lowpass filtering action), such that
Like before, when the loop gain is high, the frequency di
viders’ noise contributions at the loop output are given by
σ
nN
= Nφ
nN
σ
nM
= Nφ
nM
(44)
As already discussed, in the PLDRO, N = 1 and φNr =
0 (no VCO dividers are used). Thus, the noise term that
remains is the SRD contribution σ
nM
= φ
nM
. As a result,
the PLDRO has the benefit of a lower noise floor within
the loop compared to the usual PLLs.
Phase Det ect or Noi se Cont ri but i on
By changing the notation of the phase detector expres
sion in Equation 37, the phase detector noise contribution
can be written as
σ
nPD
nPD
PD
PD VCO
PD VCO
V
K
K K H s
s
K K H s
Ns
· •
( )
]
]
]
]
+
( )
]
]
]
]
1
45 ( )
σ φ
nM nM
PD VCO
PD VCO
K K H s
s
K K H s
Ns
· •
( )
]
]
]
]
+
( )
]
]
]
]
1
43 ( )
σ φ
nN nN
PD VCO
PD VCO
K K H s
s
K K H s
Ns
· •
( )
]
]
]
]
+
( )
]
]
]
]
1
42 ( )
σ φ
nTCXO nR
N
M
· ( ) 40
TECHNI CAL FEATURE
Again, this expression is a lowpass function as seen previ
ously. In the same way, inside the loop band (where the
loop gain is high) the phase detector rms noise contribu
tion at the PLL output is expressed as
In the case of a PLDRO, N = 1 (no VCO divider is used)
— another reason why the noise floor within the loop is
much lower compared to a classical synthesizer. Additional
ly (both in a PLDRO and synthesizer), a higher phase de
tector gain will reduce the noise floor within the loop band
width. In the case of a PLDRO, a higher phase detector
gain means that a higher beat note output is required from
the microwave sampler. The disadvantage is that the sam
pler must be driven with a higher power signal at mi
crowave frequencies. In an ordinary chargepump synthe
sizer, this increase of phase detector gain will usually affect
the level of spurious signals around the output carrier.
Loop Ampl i f i er Noi se Cont ri but i on
In the same manner, the loop amplifier noise contribu
tion is expressed as
As explained previously, inside the loop band (where the
loop gain is high), the loop active filter rms noise contri
bution at the PLL output is given by
Again, a high phase detector gain will improve the phase
noise characteristic within the loop bandwidth.
VCO Phase Noi se Cont ri but i on
The VCO phase noise transfer function is given by
Replacing H(s) as in Equation 5 produces
This expression describes a highpass filter (HPF) charac
teristic with a 40 dB per decade slope, which means that
the phase noise generated by the VCO (or VtDRO) is
strongly attenuated within the loop limits. At higher offset
frequencies (far from the carrier) where there is no more
feedback action, the output phase noise becomes equal to
the freerunning phase noise of the VCO or VtDRO
alone. Hence, the best phase noise limit of a synthesizer
or PLDRO is defined by the freerunning VCO or Vt
DRO phase noise characteristic.
σ φ
ξω ω
nVCO nVCO
n n
s
s s
·
+ +
2
2 2
2
50 ( )
σ φ
nVCO nVCO
PD VCO
K K H s
Ns
· •
+
( )
1
1
49 ( )
σ
nLPF nLPF
PD
V
N
K
· ( ) 48
σ
nLPF
nLPF
PD
PD VCO
PD VCO
V
K
K K H s
s
K K H s
Ns
· •
( )
]
]
]
]
+
( )
]
]
]
]
1
47 ( )
σ
nPD nPD
PD
V
N
K
· ( ) 46
General Consi derat i ons
It can be demonstrated that the optimum choice for
the loop bandwidth (that is, the one that minimizes the
output phase noise variance) is the frequency at which the
phase noise of the freerunning VCO coincides with the
total noise floor coming from the reference and phase de
tector side. In the transition region close to the loop cor
ner frequency, the output phase noise can become higher
than the freerunning VCO noise. In fact, since the HPF
function is given by HPF(s) = 1 – LPF(s) where LPF(s) is
the closedloop transfer function, the optimization of in
band phase noise will affect the outofband phase noise
and vice versa. For example, a sharp lowpass filter (LPF)
function means a sharp HPF function and better suppres
sion of the VCO or VtDRO noise inside the loop fre
quency limits. Of course, this condition will require a high
damping factor ξ and higher overshoot of the transfer
function with subsequent increase of the phase noise in
that offset frequency range.
With the previously described method, each phase
noise contribution can be calculated separately by using
an appropriate CAD method. The total output phase
noise then can be obtained using the root mean square
notation:
This frequencydependent function gives the overall
phase noise spectrum log.
Since the noise generators’ contributions are expressed in
rms terms, each contribution X can be expressed in logarith
mic units by calculating 20logX. For example, considering
the phase detector noise expressed by Equation 46 yields
In this manner, socalled singlesideband phase noise can
be obtained in dBc/Hz just as it would be displayed by a
spectrum analyzer. (Note that the parameter 20logV
nPD
should be given by the manufacturer of the device or can
be evaluated.) The overall phase noise (PN) within the
loop bandwidth or outside the loop bandwidth in dBc/Hz
notation is given by
PN(dBc/Hz) = 20logσ (53)
LO O P FI LTER
AN D ACQ U I SI TI O N CI RCU I T O PTI M I ZATI O N
Desi gn Procedure
The loop filter is a secondorder integrator with opti
mized ω
3dB
to obtain good phase noise matching between
the loop noise floor and freerunning VtDRO phase noise.
Following the PLDRO design steps, the ω
3dB
of the loop
(and the damping factor ξ) is defined considering phase
noise requirements. Next, the SPD beat note peaktopeak
output voltage V
BN
is measured (or determined from the
data sheet) and K
PD
of the SPD is calculated using
K
V
PD
BN
·
2
σ
nPD nP
PD
V
N
K
· + 20 20 52 log log ( )
σ σ σ σ σ σ σ · + + + + +
nPD nTCXO nN nM nVCO nLPF
2 2 2 2 2 2
51 ( )
TECHNI CAL FEATURE
Bear in mind that a high beat note
voltage is required for good phase
noise. The loop natural frequency ω
then is calculated using
Next, the VtDRO sweep range (SR)
in Hertz is defined. The locking V
t
must be optimized to be located at
ω
ω
ξ ξ
n
dB
·
+ + +
( )
+
3
2 2
2
2 1 2 1 1
t he middle of t he sweep volt age
swing r ange by using t he t uning
screw. This point is defined by the
hysteresis of the OPA1 comparator.
C
1
is selected and the remaining loop
parameters are calculated using
The maximum allowable sweep rate
is defined using Viterbi’s condition
More margin is added if needed. (For
example,
may be used.) The required triangle
halfperiod T/2, expressed in seconds,
is calculated using
where
SR = sweep range of the VtDRO
(Hz)
Next, the OPA2 comparator feedback
values are calculated and optimized
for the required sweep time. Arbi
trary initial values are selected for R
4
or R
6
and final values are calculated
from the relation of the SR voltage
swing V
SR
defined by the comparator
hysteresis limitations
Remembering that V
ref
= V
CC
/2, R
5
is
calculated using
Finally, t he current t hrough R
5
is
compared with the current through
R
1
(beat note
max
is the peak voltage at
the SPD output) to verify that the
negative feedback can prevail over
∆T
R R
R
R C ·
6 4
6
5 1
–
V
R
R
V at V
V
SR ref ref
CC
· ·
2
2
4
6
T SR
2
2
·
• π
ω ∆
˙
∆
˙
. ω
ω
· 0 1
2
2
n
∆
˙
ω
ω
<
n
2
2
τ
ω
τ
ξ
ω
τ
τ
1
2
2
1
1
1
2
2
1
2
·
·
·
·
K K
R
C
R
C
d V
n
n
the positive feedback such that
If necessary, R
5
is increased in value
to slow down the sweep rate.
Lock I ndi cat i on Ci rcui t
The lock indication circuit samples
the output of the comparator amplifi
er or the tuning voltage V
tune
. When
ever the loop is out of lock the square
wave voltage will generate a 0 (low
level). When the loop is locked the
square wave stops and the output lev
el is 1. However, the level indicating a
correct lock can be 0 and then a 1 will
indicate the unlocked state, depend
ing on t he syst em r equir ement s.
There are several ways to implement
such a circuit. For example, a sample
andhold circuit or an absolute value
circuit, where the fluctuating voltage
is detected, may be used.
M EASU RED RESU LTS
Thr ee ver y low cost PLDROs
were designed, built and tested at
9.5, 11.3 and 15.5 GHz. The refer
ence frequency was 50 MHz. CAE
optimization techniques were used to
opt imize t he loop st abilit y, phase
noise and acquisition performance,
showing good agreement with the
measured results. The performance
of a 11.3 GHz low cost PLDRO ex
ample for a local multipoint distribu
tion system application is shown in
Figures 7, 8, 9 and 10.
CO N CLU SI O N
When designing an aided search/
acquisition PLDRO, the rise and fall
times of the sweep signal are crucial
parameters. A low frequency sweep
signal with fast rise and fall times such
as a square wave or exponential wave
is not adequate because the sweep
rate is much too fast and will be inter
preted as a chirp modulation. The
phase error θ
e
transmission function
of a PLL is an HPF so the fast tran
sient interrupt will pass directly to the
VCO output and the feedback path
will not be able to track it. Dualfeed
back circuits such as a classical Wien
bridge are not recommended due to
their temperature sensitivity. Finally,
special consideration should be taken
V V
R
beat note
R
V
V R
R R
CC ref
ref
CC
–
max
5 1
9
3 9
<
·
+
TECHNI CAL FEATURE
1 2 0
6 0
0
−6 0
−1 2 0
1 2 0
6 0
0
−6 0
−1 2 0
1 0 M 1 K
FREQ U EN CY ( H z)
8 0 ° PH ASE
M ARGI N
LO O P DELAY
1
G
A
I
N
(
d
B
)
P
H
A
S
E
(
°
)
v Fig. 7 Phase and gain margin.
−2 5
−1 0 0
−1 7 0
1 M 4 0 0 K 1 K
FREQ U EN CY ( H z)
1
P
H
A
S
E
N
O
I
S
E
(
d
B
c
/
H
z
)
−1 0 2 . 5
−8 5
w
Fig. 8 Phase noise simulation.
1 0
−2 0
−5 0
1 0 M
4 8 K
3 dB
1 0 K 1 K
FREQ U EN CY ( H z)
1
T
R
A
N
S
M
I
S
S
I
O
N
(
d
B
)
v Fig. 9 The closedloop
transmission function.
0
−2 0
−4 0
−6 0
−8 0
1 1 0 0
−1 0 1 dB/ H z
O FFSET FREQ U EN CY ( kH z)
−1 1 0
R
E
T
U
R
N
P
H
A
S
E
N
O
I
S
E
(
d
B
c
/
3
k
H
z
)
Fig. 10 Phase noise at 11.3 GHz measured
in a 3 kHz bandwidth.
w
when selecting the SPD to optimize
phase noise performance.
ACKN O WLEDGM EN T
The author would like to thank
Boris Vainer, the project develop
ment technician, for his aid on tests
and help in carrying out the project’s
tasks from its conception to success
ful completion. Thanks also go to Mr.
Kondoh, Mr. Onoda and Mr. Rolhoff
for the samples, and A. Villa for re
viewing this article. s
TECHNI CAL FEATURE
Ref erences
1. Gardner Phaselock Techniques, Second
Edition, John Wiley and Sons, New York.
2. Heinrich Meyr and Gerd Ascheid, Syn
chronization in Digital Communications,
Vol. 1, John Wiley and Sons, New York.
3. Alex Hodisan, Ziv Hellman and Avi Bril
lant, “Method Optimizes Performance of
PLLs,” Microwaves & RF, Sept ember
1994, pp. 87–96.
4. Alex Hodisan, Ziv Hellman and Avi Bril
lant, “CAE Software Predicts PLL Phase
Noise,” Microwaves & RF, November
1994, pp. 95–102.
5. V.F. Kroupa, “Noise Properties of PLL Sys
tems,” IEEE Transactions on Communica
tions, October 1982, pp. 2244–2251.
6. Millman Halkias, Integrated Electronics,
McGrawHill.
Avi Bril l ant received
his BSc degree in
electrical engineering
from the Technion
Israel Institute of
Technology, Haifa in
1986. From September
1986 to July 1993, he
was employed at
MicroKim Ltd. in
Haifa as a design
engineer in the
amplifiers and sources group. In 1993, Brillant
joined MTI Technology and Engineering Ltd.
in TelAviv as a system engineer. He was also a
consulting engineer for BreezCom. In July
1995, he joined Optomic Microwaves Ltd. in
Migdal Ha’Emek as a senior engineer in charge
of communications products for VSAT, LMDS,
microwave, mmwave link and cellular
applications. Brillant is a member of the Israeli
MMIC Consortium.
H(s) is given by EQUATION 17 0. and there is a possibility for acquisition only if ω2 ∆˙ω < n 2 Otherwise. For a better design where E(BLTS) = 104 cycle slips.707 (17) ρ rad (13) (also called dynamic tracking error). Substituting these expressions into Equation 4 and using the LaPlace final value theorem produces θe s = () s 2θi s 2 () mitter and receiver. This value can be easily obtained by mechanically tuning the VtDRO tuning screw. Doppler frequency shift or frequency sweep modulation. the normalized sweep rate is given by .TECHNICAL FEATURE NORMALIZED SWEEP RATE SRi. 2 Normalized sweep rate as a function of SNRL. 0.59 0. the tuning range ∆f of the VtDRO should satisfy the condition ∆f < 2 • f(TCXO) (3) For a symmetrical search.30 0. Frequency Acquisition The sweep can be applied as an updown ramp voltage directly to the VtDRO tuning input. the search signal voltage should be properly offset (through a suitable bias voltage at the acquisition and lock circuitry) by a value equal to the same optimum Vtune.10 EQUATION 18 () H(s ) = Vi (s ) Vo s = – where τ1 = R1C τ2 = R2C (6) (7) 1 + sτ1 sτ 2 (5) (2) Hence. the optimum Vtune value of the VtDRO (that is. For a perfect secondorder loop with active integrator. the value at which the desired phaselocked oscillator frequency is reached) should be half of the control voltage swing range (for instance. Frazier and Page provided empirical data that indicate the sweep rate should satisfy a particular condition for acquisition in the presence of noise. Such input behavior might arise from accelerated motion between a trans for 90 percent acquisition probability. a probability of 0. In most cases.49 0. The steadystate phase error θe = θi – θo after all transient effects have terminated (t→∞) is given by θe s = where KV = VtDRO modulation sensitivity (in radians/second per volt) Kd = sampling phase detector output sensitivity (in volts per radian) H(s) = loop filter transfer function 0 2 3 4 5 6 7 8 9 10 11 12 SIGNALTONOISE RATIO ρi. ρj v Fig. resulting in 1–2 1 ∆˙ω < ω 2 (16) n 2 SNRL In this case.39 0. In the same way. while ρ represents SNR L. the maximum permitted sweep rate limit is given by ∆˙ω = ω 2 ⇒ ∆˙ω < ω 2 n n (15) ω nτ2 (10) 2 Now suppose that the input frequency is linearly changing with time at ⋅ the rate of ∆ω rad/sec2 such that θ i = ∫ ∫ ωdt ⇒ θi t = However.9 is too low. Such a triangle sweep signal is due to tracking considerations. this expression is sin θe = ∆˙ω ω2 n (14) s + 2ξω ns + ω 2 n (8) where the natural loop frequency ωn and the loop damping factor ξ are given by ωn = ξ= K VKd τ1 (9) Note that the sinus function cannot exceed ±1. Gardner’s experience added some changes. it will not be locked. to prevent false lock on an undesired comb harmonic. a constant current Isw is inserted to create a triangle sweep voltage with switching polarities. 1/2 Vcc. this condition is not satisfactory.707 ≤ ξ ≤ 1 and the loop signaltonoise ratio (SNR L) is less than 6 dB. which is the case here. where Vcc is the supply voltage to the active loop filter). For a sinusoidal characteristic phase detector. Viterbi discovered that acquisition is not certain even if the loop is noise free. Two other experimental formulas were suggested by Frazier and Page. θ(s) is given by the relevant LaPlace transform (12) s3 Substituting Equation 12 into Equation 8 using the final value theorem yields the steadystate phase error accumulated during a linear frequency sweep θi s = () ∆˙ω () sθ i s () s + K V K dH s () (4) t →∞ lim θe t = lim s s →0 () ⇒ θe t = ∆˙ω 2 ωn () s3 2 s 2 + 2ξω ns + ω n s2 ∆˙ω ≈1– 2 ∀ ξ > 0.20 0. It is also important to use a sufficiently high frequency reference signal so that the sweep can be made wide enough to cover the temperature drifts of the VtDRO. Thus. ∆˙ω 2 ω N 90% () 1 ˙ 2 ∆ωt (11) 2 Hence. SRj frequency spacing between each comb harmonic is equal to the temperaturecompensated crystal oscillator’s (TCXO) frequency as defined in f(n) = f(TCXO)• n • δ(n – N) (1) f(TCXO) = f(TCXO) • {n • δ(n – N) – [(n – 1) • δ([n – 1] – [N – 1])} In the case of a secondorder PLL with an active loop filter.
Hence. When the voltage V(t)OPA1+ reaches a higher value than Vref. Thus. Vo(t)OPA2 = the output voltage from OPA2 at a given time t When. A better understanding of this circuit is possible by referring to it as a triangle wave generator circuit. during the negativegoing ramp of OPA2. the charging equation (after substituting Equation 24 into Equation 22 and integrating the result) is VO t ( )OPA1+ VO t R V R OPA 2 6 = CC 4 + R6 + R 4 R6 + R 4 () (20) ( )OPA 2 = VCC – Voffset R 5C1 t1 t0 ∫ dt (25) . Hence. The next objective is to calculate the sweep frequency from the circuit parameters. which is the locking circuit (OPA2loop filter OPA3 high input impedance buffer). the current to the invert input of OPA2 is ISW = VCC – Voffset R5 (19) Since Voffset was chosen to be 1/2 Vcc. and a sweeping circuit for aided acquisition as the positive feedback (OPA1Schmitt trigger comparator. the current changes its sign and the capacitor C is discharged. Voffset – dVC1 t dt () (22) ( )C R 1 2 – VC1 t = VO t () ( )OPA 2 (23) (This offset voltage has several names and meanings. Sweeping and Locking The PLDRO search and locking circuit. dVO t ( )OPA 2 = – dVC1 dt dt (24) Hence.5 Figure 2 shows the normalized sweeping rate as a function of loop SNRL. Substituting Equation 22 into Equation 23 and deriving it by t yields. for example. OPA2integrator). 1/2 2 = 1 – 6 < ρ < 9. The sweep rate ∆⋅ω is defined by the triangle signal slope.) The constant positive current in Equation 19 will cause a negativegoing liner voltage ramp at the output of OPA2 due to the charge of C1.4 ρ > 9. shown in Figure 3. Figure 4 shows the triangle sweep signal generated by this circuit.5 ω2 ρ – 4 n 0. 4 where VCC The triangle sweep signal. the voltage V(t)OPA1+ at the comparator noninverting input becomes smaller than Vref at the comparator OPA1 inverting input. the charge of C1 will begin and vice versa. 3 ∆˙ω The aided search/acquisition circuit. The current ISW through R5 is equal to the charging current of C1 and is related to the voltage Vc(t) across the capacitor C1 by dVC1 t VCC – Voffset C1 =– R5 dt On the other hand. the charge is linear as already observed. At that moment the current to the inverting input of the integrator OPA2 becomes ISW = (18) – Voffset R5 (21) Vtune VtDRO v Fig. its output switches to 0 V. Suppose that in the moment t0 = 0 the output of OPA1 is Vcc while OPA1 is in its positive saturation (OPA1 is a comparator). Voffset = Vtunelocking = Vbias.TECHNICAL FEATURE R6 + − OPA1 − NULL ADJUST BEAT NOTE + OPA3 0V R5 ISW R1 R2 C1 VCC 0V OPA2 VtDRO FREQUENCY VCC R4 f − FVtDROmin • ∆ω = 4π VtDROmax T fVtDRO max fVtDRO locked VCC/2 • ∆ω fVtDRO min T/2 TIME (t) T VCC − + SAMPLER R9 OFFSET FOR Vt OPTIMUM R3 v Fig. the secondorder loop design formulas together with the triangle generator design formulas are applicable. consists of two feedback paths: a negative feedback path. as expected. the triangle frequency is onehalf the sweep rate. At that time (using superposition) the voltage at the noninverting input of the comparator OPA1 is given by V t Since VCC and Voffset are constants.
6 Noise generators within a synthesizer. when the loop is out of lock. VCOs and TCXOs. For convenience. hence. the negative feedback becomes dominant. Equation 29 can be simplified so the triangle frequency is given by f= R6 2 R6 – R 4 R 5C1 PHASE NOISE Phase noise at the output of a phaselocked loop (PLL) can be calculated as a root mean square summation of all the noise generators’ variances. is shown in Figure 5. VO(t)OPA1 (V) ( )OPA 2 = φ neq = φ ni – φ'nO K PD ( ) [(φ neq + VPD + VnLPF H s + φ nVCO = φ nO φ'nO = ) ( )] K s (34) (35) φ nO + φ nN N where KVCO = VtDRO modulation sensitivity (in radians/second per volt) KPD = phase detector or sampling phase detector output sensitivity (in volts per radian) H(s) = loop filter transfer function N = prescaler (and VCO frequency divider) ratio M = reference divider ratio After some manipulations. When the loop is locked the signal VCC voltage coming from the sampling 2R4 phase detector is at its maximum value. the triangle frequency is given by f= 1 2∆T (30) ( )OPA1– = Vref = VO t R VCCR 4 OPA 2 6 + R6 + R 4 R6 + R 4 Thus. the expression becomes . reference dividers or step recovery diode (SRD) that drive the microwave sampler in the case of PLDROs. VO t () (27) Bearing in mind that optimum Vtune for locking is VCC/2 and that Vref = VCC/2 since a symmetrical sweep is required. The noise contributions injected into a PLL are shown in Figure 6.TECHNICAL FEATURE The result is a linear ramp that creates the triangle wave described by VO t ( )OPA 2 = 1 (VCC – Voffset )(t1 – t0 ) + V0 (0) R C 5 1 Combining Equation 26 with Equation 28 and writing the expression (t1 – t0) as ∆T and assuming VO(0) = 0 results in V R ∆T = Vref – CC 4 R6 + R 4 R + R 4 R 5C1 • 6 R6 VCC – Vref (29) (26) To calculate T/2. SWEEP Vref RANGE R6 The current through R4 is higher than the current through R5 and. θo stabilizing the sysv Fig. The hysteresis plot. Using control theory notation. The 0 < VTrmin < VOOPA2 VTrrmar < VOOPA2 current through R5 generated by the Schmitt trigger OPA1 becomes domiR6 − R4 R6 + R 4 nant and a new search triangle signal R6 Vref R6 Vref begins until the loop acquires lock. This equation is expressed as V t Therefore. generatR6 R6 + R 4 ed using superposition calculation. the positive feedback path is θ'i suppressed and the VnLPF triangle sweep wave φnR θi VnPD φnM is stopped. 5 The OPA1 comparator’s hysteresis. the applicable noise equations are φ ni = φ nR + φ nM M (32) (33) VCO ( ) (31) In some cases the sweep circuit may not operate due to improper design of the comparator’s OPA1 hysR6 + R 4 VCCR 4 (28) Vref – teresys. there is a need to calculate the charging time until the voltage at the noninverting input of the comparator OPA1 reaches the reference voltage value applied at the inverting input of the same operational amplifier. θe cally operates its positive feedback to φnVCO θ'oφ bring the system to a φnN stable point where the negative feed1/N Σ Σ back suppresses the φnO positive feedback. these noise term __ variances (rms values) in V/√Hz have been indicated as φnR φnM = reference TCXO phase noise = reference divider or SRD phase noise φnO = total output phase noise φnN = emittercoupled logic (ECL) divider phase noise φNvco = VCO phase noise variance VnD = phase detector phase noise VnLPF = loop amplifier phase noise The objective now is to determine the phase noise transmission function for each noise generator. The noise generators considered here are the phase detector. VO (t)OPA2 (V) When the loop is locked the negative v Fig. loop filter (operational amplifier). This deH(s) KPD KVCO/S scription demonstrates how a con1/M Σ Σ Σ Σ trol system automatiTCXO θ'nO φneq. VCO prescalers and dividers (if any). which is half of the triangle duration. However. 0 the sampler output voltage drops. feedback becomes dominant. tem.
the phase noise power spectral density may be obtained from Equation 37 by mean square addition of the individual sources. using Equations 5. 9 and 10 transforms Equation 38 into σ nTCXO = 2ξω nS + ω 2 φ nR n • 2 2 M s + 2ξω ns + ω n (39) As already discussed. Thus. the PLL phase noise at its output becomes K PDK VCOH s s φ nR + φ nM – φ nN • φ nO = M K PDK VCOH s 1 + Ns H s K VCO s + VnPD + VnLPF • K PDK VCOH s 1 + Ns 1 + φ nVCO (37) K PDK VCOH s 1 + Ns This result is interesting because it gives the transfer function for each noise generator within the loop referred to the output. prescalers. for a PLDRO it holds that σnTCXO = MSRDφnR (41) Frequency Divider Noise Contribution The 1/N and 1/M frequency dividers’ contribution to the output phase noise is given by a similar expression that is almost identical (lowpass filtering action). 7. As a result. the frequency dividers’ noise contributions at the loop output are given by σnN = NφnN σnM = NφnM (44) σ nTCXO ( ) (38) Assuming that H(s) describes an active filter. Hence. The first expression of this formula should be changed in sign from φnM – φnN to φnM + φnN since these variances are not correlated. Well inside the loop bandwidth (where the loop gain is high — KPDKVCOH(s) → ∞). the damping factor ξ of the loop has a significant impact on the phase noise characteristic outside the loop bandwidth. in the PLDRO. Since each noise term is uncorrelated. () () () [ ] () () () () σ nM Reference Source Noise Contribution The TCXO output phase noise contribution to the output phase noise is given by K PDK VCOH s s φ nR = • M K PDK VCOH s 1 + Ns K PDK VCOH s s = φ nM • K PDK VCOH s 1 + Ns () ( ) (43) () Like before. 6. For this reason. Thus. the closedloop sharpness defines the amount of the TCXO phase noise that is enhanced outside the loop bandwidth.TECHNICAL FEATURE φ nO φ φ = nR + φ nM – nO + φ nN N M K •K PD + VnPD + VnLPF H s • VCO + φ nVCO s } ( )} (36) same conclusion also holds for the reference dividers or SRD. N = 1 and M = 1/MSRD. where MSRD is the order of the reference frequency harmonic at which the VtDRO is locked. Furthermore. Phase Detector Noise Contribution By changing the notation of the phase detector expression in Equation 37. N = 1 and φNr = 0 (no VCO dividers are used). the phase detector noise contribution can be written as K PDK VCOH s s • K PDK VCOH s 1 + Ns Equation 39 shows that the reference source (TCXO) phase noise within the loop is multiplied by the closedloop lowpass transmission function with a –20 dB per decade slope. loop amplifier and phase detector. it can be easily investigated for phase noise optimization. the output phase noise standard due to the TCXO can be approximated as σ nTCXO = where N = divider and prescaler ratio M = reference divider ratio In the actual case of a PLDRO. when the loop gain is high. such that K PDK VCOH s s (42) σ nN = φ nN • K PDK VCOH s 1 + Ns N φ nR M (40) Rearranging the variables in a way that φnO is the subject of the formula. the PLDRO has the benefit of a lower noise floor within the loop compared to the usual PLLs. This () σ nPD = VnPD K PD ( ) (45) . the noise term that remains is the SRD contribution σnM = φnM. and will be attenuated outside the loop.
In an ordinary chargepump synthesizer. For example. each phase noise contribution can be calculated separately by using an appropriate CAD method. For example. the one that minimizes the output phase noise variance) is the frequency at which the phase noise of the freerunning VCO coincides with the total noise floor coming from the reference and phase detector side. considering the phase detector noise expressed by Equation 46 yields σ nPD = 20 log VnP + 20 log N K PD (52) Again. this increase of phase detector gain will usually affect the level of spurious signals around the output carrier. socalled singlesideband phase noise can be obtained in dBc/Hz just as it would be displayed by a spectrum analyzer. the output phase noise can become higher than the freerunning VCO noise.TECHNICAL FEATURE Again. Next. Additionally (both in a PLDRO and synthesizer). In fact. a higher phase detector gain means that a higher beat note output is required from the microwave sampler. The total output phase noise then can be obtained using the root mean square notation: 2 2 2 2 σ = σ2 + σ2 nPD nTCXO + σ nN + σ nM + σ nVCO + σ nLPF (51) () σ nLPF = VnLPF K PD ( ) (47) As explained previously. Loop Amplifier Noise Contribution In the same manner. the SPD beat note peaktopeak output voltage VBN is measured (or determined from the data sheet) and KPD of the SPD is calculated using K PD = VBN 2 . the loop amplifier noise contribution is expressed as K PDK VCOH s s • K PDK VCOH s 1 + Ns General Considerations It can be demonstrated that the optimum choice for the loop bandwidth (that is. Since the noise generators’ contributions are expressed in rms terms. In the transition region close to the loop corner frequency. the output phase noise becomes equal to the freerunning phase noise of the VCO or VtDRO alone. LOOP FILTER AND ACQUISITION CIRCUIT OPTIMIZATION Design Procedure The loop filter is a secondorder integrator with optimized ω3dB to obtain good phase noise matching between the loop noise floor and freerunning VtDRO phase noise.) The overall phase noise (PN) within the loop bandwidth or outside the loop bandwidth in dBc/Hz notation is given by PN(dBc/Hz) = 20logσ (53) σ nVCO = φ nVCO s2 s 2 + 2ξω ns + ω 2 n (50) This expression describes a highpass filter (HPF) characteristic with a 40 dB per decade slope. N = 1 (no VCO divider is used) — another reason why the noise floor within the loop is much lower compared to a classical synthesizer. which means that the phase noise generated by the VCO (or VtDRO) is strongly attenuated within the loop limits. VCO Phase Noise Contribution The VCO phase noise transfer function is given by 1 (49) σ nVCO = φ nVCO • K PDK VCOH s 1+ Ns Replacing H(s) as in Equation 5 produces () In this manner. the ω3dB of the loop (and the damping factor ξ) is defined considering phase noise requirements. since the HPF function is given by HPF(s) = 1 – LPF(s) where LPF(s) is the closedloop transfer function. a higher phase detector gain will reduce the noise floor within the loop bandwidth. At higher offset frequencies (far from the carrier) where there is no more feedback action. inside the loop band (where the loop gain is high). this expression is a lowpass function as seen previously. In the case of a PLDRO. Of course. inside the loop band (where the loop gain is high) the phase detector rms noise contribution at the PLL output is expressed as N σ nPD = VnPD (46) K PD In the case of a PLDRO. With the previously described method. In the same way. The disadvantage is that the sampler must be driven with a higher power signal at microwave frequencies. the loop active filter rms noise contribution at the PLL output is given by σ nLPF = VnLPF N K PD (48) This frequencydependent function gives the overall phase noise spectrum log. this condition will require a high damping factor ξ and higher overshoot of the transfer function with subsequent increase of the phase noise in that offset frequency range. a high phase detector gain will improve the phase noise characteristic within the loop bandwidth. the optimization of inband phase noise will affect the outofband phase noise and vice versa. each contribution X can be expressed in logarithmic units by calculating 20logX. (Note that the parameter 20logVnPD should be given by the manufacturer of the device or can be evaluated. Following the PLDRO design steps. the best phase noise limit of a synthesizer or PLDRO is defined by the freerunning VCO or VtDRO phase noise characteristic. a sharp lowpass filter (LPF) function means a sharp HPF function and better suppression of the VCO or VtDRO noise inside the loop frequency limits. Hence.
Fig. Finally. When the loop is locked the square wave stops and the output level is 1. the level indicating a correct lock can be 0 and then a 1 will indicate the unlocked state. a sampleandhold circuit or an absolute value circuit. The performance of a 11. special consideration should be taken 1K FREQUENCY (Hz) v Fig. C1 is selected and the remaining loop parameters are calculated using τ1 = τ2 = R1 = R2 = K dK V ω2 n 2ξ ωn τ1 C1 τ2 C1 the positive feedback such that VCC – Vref beat notemax < R5 R1 VCCR 9 R3 + R9 If necessary. expressed in seconds. w RETURN PHASE NOISE (dBc/3 kHz) 0 −20 −40 −60 −80 −110 −101 dB/Hz 0 110 OFFSET FREQUENCY (kHz) Bear in mind that a high beat note voltage is required for good phase noise. the OPA2 comparator feedback values are calculated and optimized for the required sweep time. The loop natural frequency ω then is calculated using ωn = 2ξ 2 + 1 + ω 3dB Remembering that Vref = VCC/2. 8.) The required triangle halfperiod T/2. may be used.1 n 2 may be used. 11. is calculated using 2 10 TRANSMISSION (dB) 3 dB −20 −50 1 48K 1K 10K FREQUENCY (Hz) 10M T 2π • SR = 2 ∆˙ω where SR = sweep range of the VtDRO (Hz) Next. A low frequency sweep signal with fast rise and fall times such as a square wave or exponential wave is not adequate because the sweep rate is much too fast and will be interpreted as a chirp modulation.5 The maximum allowable sweep rate is defined using Viterbi’s condition 1K 400K 1M FREQUENCY (Hz) −170 1 ω2 ∆˙ω < n 2 More margin is added if needed.3 GHz measured in a 3 kHz bandwidth. The phase error θe transmission function of a PLL is an HPF so the fast transient interrupt will pass directly to the VCO output and the feedback path will not be able to track it. For example. the VtDRO sweep range (SR) in Hertz is defined.TECHNICAL FEATURE 120 GAIN (dB) 60 0 −60 −120 1 80° PHASE MARGIN 60 0 −60 −120 10M PHASE (°) LOOP DELAY 120 the middle of the sweep voltage swing range by using the tuning screw. CONCLUSION When designing an aided search/ acquisition PLDRO. 8 −25 PHASE NOISE (dBc/Hz) Phase and gain margin. R5 is calculated using ∆T = R6 – R 4 R 5C1 R6 ( 2 ξ + 1) 2 2 +1 Next. 7 w Fig. 9 The closedloop transmission function. 9 and 10.5. phase noise and acquisition performance. Phase noise simulation. ω ∆˙ω = 0. The reference frequency was 50 MHz. showing good agreement with the measured results.5 GHz. the rise and fall times of the sweep signal are crucial parameters. The locking Vt must be optimized to be located at Finally.3 and 15. Vref = Lock Indication Circuit The lock indication circuit samples the output of the comparator amplifier or the tuning voltage Vtune. CAE optimization techniques were used to optimize the loop stability. There are several ways to implement such a circuit. 10 Phase noise at 11.3 GHz low cost PLDRO example for a local multipoint distribution system application is shown in Figures 7. where the fluctuating voltage is detected. R5 is increased in value to slow down the sweep rate. Whenever the loop is out of lock the square wave voltage will generate a 0 (low level). the current through R 5 is compared with the current through R1 (beat notemax is the peak voltage at the SPD output) to verify that the negative feedback can prevail over . built and tested at 9. However. −85 −100 −102. Dualfeedback circuits such as a classical Wien bridge are not recommended due to their temperature sensitivity. This point is defined by the hysteresis of the OPA1 comparator. (For example. MEASURED RESULTS Three very low cost PLDROs were designed. depending on the system requirements. Arbitrary initial values are selected for R4 or R6 and final values are calculated from the relation of the SR voltage swing VSR defined by the comparator hysteresis limitations VSR = 2R 4 V Vref at Vref = CC R6 2 v Fig.
pp. John Wiley and Sons. Alex Hodisan. September 1994. Heinrich Meyr and Gerd Ascheid. the project development technician. November 1994.TECHNICAL FEATURE when selecting the SPD to optimize phase noise performance. 6. Second Edition. microwave.” Microwaves & RF. pp. John Wiley and Sons. “Method Optimizes Performance of PLLs. October 1982. New York. 95–102. Villa for reviewing this article. “Noise Properties of PLL Systems. Avi Brillant received his BSc degree in electrical engineering from the Technion Israel Institute of Technology. he joined Optomic Microwaves Ltd. pp. 4. 87–96. mmwave link and cellular applications. Haifa in 1986. In July 1995. and A. “CAE Software Predicts PLL Phase Noise. . Onoda and Mr. In 1993. Ziv Hellman and Avi Brillant. Mr. V. for his aid on tests and help in carrying out the project’s tasks from its conception to successful completion. 2. 1. Synchronization in Digital Communications. 3. ACKNOWLEDGMENT The author would like to thank Boris Vainer. Kroupa. Integrated Electronics. Millman Halkias. New York. s References 1.” IEEE Transactions on Communications. Thanks also go to Mr. in Haifa as a design engineer in the amplifiers and sources group. Alex Hodisan. he was employed at MicroKim Ltd. Kondoh. Ziv Hellman and Avi Brillant. McGrawHill. LMDS. 5. in TelAviv as a system engineer. He was also a consulting engineer for BreezCom. 2244–2251.F. Brillant is a member of the Israeli MMIC Consortium. Rolhoff for the samples. Vol. in Migdal Ha’Emek as a senior engineer in charge of communications products for VSAT. Gardner Phaselock Techniques.” Microwaves & RF. From September 1986 to July 1993. Brillant joined MTI Technology and Engineering Ltd.