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CD74HC40103ĆQ1

HIGHĆSPEED CMOS LOGIC
8ĆSTAGE SYNCHRONOUS DOWN COUNTER
SCLS547A − OCTOBER 2003 − REVISED APRIL 2008
1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Qualified for Automotive Applications
D Synchronous or Asynchronous Preset
D Cascadable in Synchronous or Ripple
Mode
D Fanout (Over Temperature Range)
− Standard Outputs . . . 10 LSTTL Loads
− Bus Driver Outputs . . . 15 LSTTL Loads
D Balanced Propagation Delay and Transition
Times
D Significant Power Reduction Compared to
LSTTL Logic ICs
D V
CC
Voltage = 2 V to 6 V
D High Noise Immunity N
IL
or N
IH
= 30% of
V
CC
, V
CC
= 5 V
description/ordering information
The CD74HC40103 is manufactured with high-speed silicon-gate technology and consists of an 8-stage
synchronous down counter with a single output, which is active when the internal count is zero. The device
contains a single 8-bit binary counter. Each device has control inputs for enabling or disabling the clock, for
clearing the counter to its maximum count, and for presetting the counter either synchronously or
asynchronously. All control inputs and the terminal count (TC) output are active-low logic.
In normal operation, the counter is decremented by one count on each positive transition of the clock (CP)
output. Counting is inhibited when the terminal enable (TE) input is high. TC goes low when the count reaches
zero, if TE is low, and remains low for one full clock period.
When the synchronous preset enable (PE) input is low, data at the P0−P7 inputs are clocked into the counter on
the next positive clock transition, regardless of the state of TE. When the asynchronous preset enable (PL) input
is low, data at the P0−P7 inputs asynchronously are forced into the counter, regardless of the state of the PE, TE,
or CP inputs. Inputs P0−P7 represent a single 8-bit binary word for the CD74HC40103. When the master reset
(MR) input is low, the counter asynchronously is cleared to its maximum count of 255
10
, regardless of the state of
any other input. The precedence relationship between control inputs is indicated in the truth table.
If all control inputs except TE are high at the time of zero count, the counters jump to the maximum count, giving a
counting sequence of 100
16
or 256
10
clock pulses long.
ORDERING INFORMATION
{
T
A
PACKAGE

ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 125°C SOIC − M Tape and reel CD74HC40103QM96Q1 HC40103Q

For the most current package and ordering information, see the Package Option Addendum at the
end of this document, or see the TI web site at http://www.ti.com.

Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
Copyright  2008, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
M PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CP
MR
TE
P0
P1
P2
P3
GND
V
CC
PE (SYNC)
TC
P7
P6
P5
P4
PL (ASYNC)
CD74HC40103ĆQ1
HIGHĆSPEED CMOS LOGIC
8ĆSTAGE SYNCHRONOUS DOWN COUNTER
SCLS547A − OCTOBER 2003 − REVISED APRIL 2008
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
The CD74HC40103 may be cascaded using the TE input and the TC output, in either synchronous or ripple
mode. These circuits have the low power consumption usually associated with CMOS circuitry, yet have speeds
comparable to low-power Schottky TTL circuits and can drive up to ten LSTTL loads.
FUNCTION TABLE
CONTROL INPUTS
PRESET MODE ACTION
MR PL PE TE
PRESET MODE ACTION
H H H H Inhibit counter
H H H L Synchronous Count down
H H L X
Synchronous
Preset on next positive clock transition
H L X X
Asynchronous
Preset asynchronously
L X X X
Asynchronous
Clear to maximum count
NOTE: H = high voltage level, L = low voltage level, X = don’t care
Clock connected to clock input
Synchronous operation: changes occur on negative-to-positive clock transitions.
Load inputs: MSB = P7, LSB = P0
logic diagram (positive logic)
7
10
11
12
13
G
N
D
4
5
6
P3
P4
P5
P6
P7
P0
P1
P2
C
P
15 9 3 1 2 16 8
14
T
C
CD74HC40103ĆQ1
HIGHĆSPEED CMOS LOGIC
8ĆSTAGE SYNCHRONOUS DOWN COUNTER
SCLS547A − OCTOBER 2003 − REVISED APRIL 2008
3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
CC
(see Note 1) −0.5 V to 7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< −0.5 V or V
I
> V
CC
+ 0.5 V) ±20 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< −0.5 V or V
O
> V
CC
+ 0.5 V) ±20 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Source or sink current per output pin, I
O
(V
O
> −0.5 V or V
O
< V
CC
+ 0.5 V) ±25 mA . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND ±50 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2) 73°C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum junction temperature, T
J
150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature (during soldering):
At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max 300°C . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
−65°C to 150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages referenced to GND unless otherwise specified.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
CC
Supply voltage 2 6 V
V
CC
= 2 V 1.5
V
IH
High-level input voltage V
CC
= 4.5 V 3.15 V V
IH
High-level input voltage
V
CC
= 6 V 4.2
V
V
CC
= 2 V 0.5
V
IL
Low-level input voltage V
CC
= 4.5 V 1.35 V V
IL
Low-level input voltage
V
CC
= 6 V 1.8
V
V
I
Input voltage 0 V
CC
V
V
O
Output voltage 0 V
CC
V
V
CC
= 2 V 0 1000
t
t
Input transition (rise and fall) time V
CC
= 4.5 V 0 500 ns t
t
Input transition (rise and fall) time
V
CC
= 6 V 0 400
ns
T
A
Operating free-air temperature −40 125 °C
NOTES: 3. All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CD74HC40103ĆQ1
HIGHĆSPEED CMOS LOGIC
8ĆSTAGE SYNCHRONOUS DOWN COUNTER
SCLS547A − OCTOBER 2003 − REVISED APRIL 2008
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
I
O
V
CC
T
A
= 25°C
MIN MAX UNIT PARAMETER TEST CONDITIONS
I
O
(mA)
V
CC
MIN MAX
MIN MAX UNIT
−0.02 2 V 1.9 1.9
CMOS loads −0.02 4.5 V 4.4 4.4
V
OH
V
I
= V
IH
or V
IL
CMOS loads
−0.02 6 V 5.9 5.9 V V
OH
V
I
= V
IH
or V
IL
TTL loads
−4 4.5 V 3.98 3.7
V
TTL loads
−5.2 6 V 5.48 5.2
0.02 2 V 0.1 0.1
CMOS loads 0.02 4.5 V 0.1 0.1
V
OL
V
I
= V
IH
or V
IL
CMOS loads
0.02 6 V 0.1 0.1 V V
OL
V
I
= V
IH
or V
IL
TTL loads
4 4.5 V 0.26 0.4
V
TTL loads
5.2 6 V 0.26 0.4
I
I
V
I
= V
CC
or GND 6 V ±0.1 ±1 µA
I
CC
V
I
= V
CC
or GND 0 6 V 8 160 µA
C
IN
C
L
= 50 pF 10 10 pF
CD74HC40103ĆQ1
HIGHĆSPEED CMOS LOGIC
8ĆSTAGE SYNCHRONOUS DOWN COUNTER
SCLS547A − OCTOBER 2003 − REVISED APRIL 2008
5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
PARAMETER V
CC
T
A
= 25°C
MIN MAX UNIT PARAMETER V
CC
MIN MAX
MIN MAX UNIT
2 V 165 250
CP 4.5 V 33 50 CP
6 V 28 43
2 V 125 190
t
w
Pulse duration PL 4.5 V 25 38 ns t
w
Pulse duration PL
6 V 21 32
ns
2 V 125 190
MR 4.5 V 25 38 MR
6 V 21 32
2 V 3 2
f
max
CP frequency (see Note 4) 4.5 V 15 10 MHz f
max
CP frequency (see Note 4)
6 V 18 12
MHz
2 V 100 150
P to CP 4.5 V 20 30 P to CP
6 V 17 26
2 V 75 110
PE to CP 4.5 V 15 22
t
su
Setup time
PE to CP
6 V 13 19
ns t
su
Setup time
2 V 150 225
ns
TE to CP 4.5 V 30 45 TE to CP
6 V 26 38
2 V 50 75
To CP, MR inactive 4.5 V 10 15 To CP, MR inactive
6 V 9 13
2 V 5 5
P to CP 4.5 V 5 5 P to CP
6 V 5 5
2 V 0 0
t
h
Hold time TE to CP 4.5 V 0 0 ns t
h
Hold time TE to CP
6 V 0 0
ns
2 V 2 2
PE to CP 4.5 V 2 2 PE to CP
6 V 2 2
NOTE 4: Noncascaded operation only. With cascaded counters, clock-to-terminal count propagation delays, count enables (PE or TE) to clock
setup times, and count enables (PE or TE) to clock hold times determine maximum clock frequency. For example, with these HC
devices:
CP f
max
+
1
CP to TC prop delay )TE to CP setup time )TE to CP hold time
+
1
60 )30 )0
[ 11 MHz
CD74HC40103ĆQ1
HIGHĆSPEED CMOS LOGIC
8ĆSTAGE SYNCHRONOUS DOWN COUNTER
SCLS547A − OCTOBER 2003 − REVISED APRIL 2008
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM TO LOAD
V
CC
T
A
= 25°C
MIN MAX UNIT PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
V
CC
MIN TYP MAX
MIN MAX UNIT
TC
2 V 300 450
TC
(asynchronous
C
L
= 50 pF 4.5 V 60 90
(asynchronous
preset)
C
L
= 50 pF
6 V 51 77
CP
preset)
C
L
= 15 pF 5 V 25
CP
TC
2 V 300 450
TC
(synchronous
C
L
= 50 pF 4.5 V 60 90
(synchronous
preset)
C
L
= 50 pF
6 V 51 77
preset)
C
L
= 15 pF 5 V 25
2 V 200 300
t
pd
TE TC
C
L
= 50 pF 4.5 V 40 60
ns t
pd
TE TC
C
L
= 50 pF
6 V 34 51
ns
C
L
= 15 pF 5 V 17
2 V 275 415
PL TC
C
L
= 50 pF 4.5 V 55 83
PL TC
C
L
= 50 pF
6 V 47 71
C
L
= 15 pF 5 V 23
2 V 275 415
MR TC
C
L
= 50 pF 4.5 V 55 83
MR TC
C
L
= 50 pF
6 V 47 71
C
L
= 15 pF 5 V 23
2 V 75 110
t
t
C
L
= 50 pF 4.5 V 15 22 ns t
t
C
L
= 50 pF
6 V 13 19
ns
f
max
CP C
L
= 15 pF 5 V 25 MHz
operating characteristics, V
CC
= 5 V, T
A
= 25°C, input t
r
, t
f
= 6 ns
PARAMETER TYP UNIT
C
pd
Power dissipation capacitance (see Note 5) 25 pF
NOTE 5: C
pd
is used to determine the dynamic power consumption per package.
P
D
= (C
pd
× V
CC
2
× f
i
) + (C
L
× V
CC
2
× f
O
)
f
I
= input frequency
f
O
= output frequency
C
L
= output load capacitance
V
CC
= supply voltage
CD74HC40103ĆQ1
HIGHĆSPEED CMOS LOGIC
8ĆSTAGE SYNCHRONOUS DOWN COUNTER
SCLS547A − OCTOBER 2003 − REVISED APRIL 2008
7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
t
h
t
su
50%
50% 50%
10% 10%
90% 90%
V
CC
V
CC
0 V
0 V
t
r
t
f
Reference
Input
Data
Input
50%
High-Level
Pulse
50%
V
CC
0 V
50% 50%
V
CC
0 V
t
w
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50% 50%
10% 10%
90% 90%
V
CC
V
OH
V
OL
0 V
t
r
t
f
Input
In-Phase
Output
50%
t
PLH
t
PHL
50% 50%
10% 10%
90% 90%
V
OH
V
OL
t
r
t
f
t
PHL
t
PLH
Out-of-Phase
Output
NOTES: A. C
L
includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z
O
= 50 Ω, t
r
= 6 ns, t
f
= 6 ns.
C. For clock inputs, f
max
is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
PLH
and t
PHL
are the same as t
pd
.
Test
Point
From Output
Under Test
C
L
= 50 pF
(see Note A)
LOAD CIRCUIT
Figure 1. Load Circuit and Voltage Waveforms
CD74HC40103ĆQ1
HIGHĆSPEED CMOS LOGIC
8ĆSTAGE SYNCHRONOUS DOWN COUNTER
SCLS547A − OCTOBER 2003 − REVISED APRIL 2008
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CP
MR
TE
PE
PL
P0
P1
P2
P3
P4
P5
P6
TC
P7
Count 255 254 3 2 1 0 255 254 254 253 8 7 6 5 4 255 254 253 252
Figure 2. Timing Diagram
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
CD74HC40103QM96Q1 ACTIVE SOIC D 16 2500 Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Apr-2008
Addendum-Page 1



















































X = don’t care Clock connected to clock input Synchronous operation: changes occur on negative-to-positive clock transitions. L = low voltage level.SCLS547A − OCTOBER 2003 − REVISED APRIL 2008 CD74HC40103 Q1 HIGH SPEED CMOS LOGIC 8 STAGE SYNCHRONOUS DOWN COUNTER description/ordering information (continued) The CD74HC40103 may be cascaded using the TE input and the TC output. LSB = P0 logic diagram (positive logic) 14 TC 13 12 11 10 7 6 5 4 GND 2 16 8 CP 15 9 3 1 P7 P6 P5 P4 P3 P2 P1 P0 2 POST OFFICE BOX 655303 • DALLAS. in either synchronous or ripple mode. Load inputs: MSB = P7. These circuits have the low power consumption usually associated with CMOS circuitry. yet have speeds comparable to low-power Schottky TTL circuits and can drive up to ten LSTTL loads. TEXAS 75265 . FUNCTION TABLE CONTROL INPUTS MR H H H H L PL H H H L X PE H H L X X TE H L X X X Asynchronous Synchronous PRESET MODE Inhibit counter Count down Preset on next positive clock transition Preset asynchronously Clear to maximum count ACTION NOTE: H = high voltage level.

. . . NOTES: 1. . . . .CD74HC40103 Q1 HIGH SPEED CMOS LOGIC 8 STAGE SYNCHRONOUS DOWN COUNTER SCLS547A − OCTOBER 2003 − REVISED APRIL 2008 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range. .59 ± 0. . . . These are stress ratings only. . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . .5 V) . . . . . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. . . . . . . . . . . . Tstg . . . . . . . . . . All unused inputs of the device must be held at VCC or GND to ensure proper device operation. . . . . . . . . . . . ±50 mA Package thermal impedance. . . . . . Implications of Slow or Floating CMOS Inputs. . . . . . . . . TEXAS 75265 3 . . . . . . . . . . . . . 300°C Storage temperature range. ±20 mA Output clamp current. . . . . . . . . 73°C/W Maximum junction temperature. −0. . . . . . . . . The package thermal impedance is calculated in accordance with JESD 51-7. . . . . . . . . . . . . . . . . . . . . . . . . . . IIK (VI < −0. . . . . . . . . .8 VCC VCC 1000 500 400 ns V V V V MAX 6 UNIT V High-level input voltage Input transition (rise and fall) time TA Operating free-air temperature −40 125 °C NOTES: 3. . . . . . . . . . . . . All voltages referenced to GND unless otherwise specified. . . . . . . . . . . . Refer to the TI application report. . . . .79 mm) from case for 10 s max . . . . . 150°C Lead temperature (during soldering): At distance 1/16 ± 1/32 inch (1.35 1. . θJA (see Note 2) . . . . . . . . .5 V or VI > VCC + 0. . . . . . . . . . . TJ . . . . . . VCC (see Note 1) . . . . . .5 V or VO < VCC + 0. . . . . . . . . . . . . . . . . . .5 V) . . . . . . . . . . . .5 3.5 V VCC = 6 V 0 0 0 0 0 2 1. . . . . . . . . recommended operating conditions (see Note 3) MIN VCC VIH Supply voltage VCC = 2 V VCC = 4. . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. .15 4. . . . . . . and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. . . literature number SCBA004. . . . . . . . . . . . . .5 V VCC = 6 V VCC = 4. . . . . . . . . . . . . . .5 V to 7 V Input clamp current. . . . . . . . . . . . . . . . . . . . . . POST OFFICE BOX 655303 • DALLAS. . . . . . . . . . .5 V) . . . .5 1. . . . . .2 0. IOK (VO < −0. . . . . . .5 V or VO > VCC + 0. . . . . . 2. . . . . . . . . . . . . . . . . . . ±20 mA Source or sink current per output pin. . IO (VO > −0. . . . . .5 V VCC = 6 V VCC = 2 V VIL VI VO tt Low-level input voltage Input voltage Output voltage VCC = 2 V VCC = 4. . . . . . .

02 4 5.1 8 10 MIN 1.1 0.1 0.26 0.SCLS547A − OCTOBER 2003 − REVISED APRIL 2008 CD74HC40103 Q1 HIGH SPEED CMOS LOGIC 8 STAGE SYNCHRONOUS DOWN COUNTER electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IO (mA) −0.02 −4 −5.9 4.02 0.5 V 6V 4.1 0.1 0.4 5.7 5. TEXAS 75265 .9 3.5 V 6V 4.48 0.02 CMOS loads VOH VI = VIH or VIL TTL loads −0.02 −0.9 3.02 CMOS loads VOL VI = VIH or VIL TTL loads II ICC CIN VI = VCC or GND VI = VCC or GND CL = 50 pF 0.2 0.5 V 6V 2V 4.5 V 6V 6V 6V TA = 25°C MIN MAX 1.4 0.2 0 VCC 2V 4.2 0.4 ±1 160 10 µA µA pF V V MAX UNIT 4 POST OFFICE BOX 655303 • DALLAS.4 5.1 0.98 5.26 ±0.9 4.1 0.

5 V 6V 2V 4.5 V 6V 2V MR 4.5 V 6V 2V P to CP 4.CD74HC40103 Q1 HIGH SPEED CMOS LOGIC 8 STAGE SYNCHRONOUS DOWN COUNTER SCLS547A − OCTOBER 2003 − REVISED APRIL 2008 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER VCC 2V CP 4.5 V 6V 2V th Hold time TE to CP 4.5 V 6V 2V tw Pulse duration PL 4.5 V 6V 2V PE to CP tsu Setup time TE to CP 4.5 V 6V 2V fmax CP frequency (see Note 4) 4.5 V 6V TA = 25°C MIN MAX 165 33 28 125 25 21 125 25 21 3 15 18 100 20 17 75 15 13 150 30 26 50 10 9 5 5 5 0 0 0 2 2 2 MIN 250 50 43 190 38 32 190 38 32 2 10 12 150 30 26 110 22 19 225 45 38 75 15 13 5 5 5 0 0 0 2 2 2 ns ns MHz ns MAX UNIT NOTE 4: Noncascaded operation only.5 V 6V 2V P to CP 4.5 V 6V 2V PE to CP 4.5 V 6V 2V To CP. with these HC devices: 1 1 + [ 11 MHz CP f max + 60 ) 30 ) 0 CP to TC prop delay ) TE to CP setup time ) TE to CP hold time POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 5 . count enables (PE or TE) to clock setup times. clock-to-terminal count propagation delays. With cascaded counters. For example. MR inactive 4. and count enables (PE or TE) to clock hold times determine maximum clock frequency.

5 V 6V 5V 2V 4. VCC = 5 V.SCLS547A − OCTOBER 2003 − REVISED APRIL 2008 CD74HC40103 Q1 HIGH SPEED CMOS LOGIC 8 STAGE SYNCHRONOUS DOWN COUNTER switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TC (asynchronous preset) CP TC (synchronous preset) LOAD CAPACITANCE VCC 2V CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF tt fmax CP CL = 50 pF CL = 15 pF 4.5 V 6V 5V 2V 4. PD = (Cpd × VCC2 × fi) + (CL × VCC2 × fO) fI = input frequency fO = output frequency CL = output load capacitance VCC = supply voltage TYP 25 UNIT pF 6 POST OFFICE BOX 655303 • DALLAS.5 V 6V 5V 2V 4. TEXAS 75265 . TA = 25°C.5 V 6V 5V 2V 4.5 V 6V 5V 2V 4. tf = 6 ns PARAMETER Cpd Power dissipation capacitance (see Note 5) NOTE 5: Cpd is used to determine the dynamic power consumption per package. input tr.5 V 6V 5V 25 23 75 15 13 110 22 19 MHz ns MR TC 23 275 55 47 415 83 71 PL TC 17 275 55 47 415 83 71 tpd TE TC 25 200 40 34 300 60 51 ns 25 300 60 51 450 90 77 MIN TA = 25°C TYP MAX 300 60 51 MIN MAX 450 90 77 UNIT operating characteristics.

Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS. Figure 1.CD74HC40103 Q1 HIGH SPEED CMOS LOGIC 8 STAGE SYNCHRONOUS DOWN COUNTER SCLS547A − OCTOBER 2003 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION High-Level Pulse VCC 50% tw Low-Level Pulse VCC 50% 50% 0V VOLTAGE WAVEFORMS PULSE DURATIONS VCC 50% tPLH Reference Input tsu Data Input 50% 10% 90% 50% th 90% VCC 50% 10% 0 V tf Out-of-Phase Output VCC 0V In-Phase Output 50% 10% tPHL 90% 50% 10% tf 90% tr tPLH 50% 10% 90% tr 50% 0V tPHL 90% VOH 50% 10% VOL tf VOH VOL 50% 0V From Output Under Test Test Point CL = 50 pF (see Note A) LOAD CIRCUIT Input tr VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. tPLH and tPHL are the same as tpd. TEXAS 75265 7 . D. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz. fmax is measured when the input duty cycle is 50%. CL includes probe and test-fixture capacitance. The outputs are measured one at a time with one input transition per measurement. Phase relationships between waveforms were chosen arbitrarily. C. ZO = 50 Ω. tr = 6 ns. E. B. For clock inputs. tf = 6 ns.

SCLS547A − OCTOBER 2003 − REVISED APRIL 2008 CD74HC40103 Q1 HIGH SPEED CMOS LOGIC 8 STAGE SYNCHRONOUS DOWN COUNTER CP MR TE PE PL P0 P1 P2 P3 P4 P5 P6 P7 TC Count 255 254 3 2 1 0 255 254 254 253 8 7 6 5 4 255 254 253 252 Figure 2. Timing Diagram 8 POST OFFICE BOX 655303 • DALLAS. TEXAS 75265 .

LIFEBUY: TI has announced that the device will be discontinued.1% by weight in homogeneous material) (3) MSL. and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0. TI Pb-Free products are suitable for use in specified lead-free processes. or 2) lead-based die adhesive used between the die and leadframe.PACKAGE OPTION ADDENDUM www. Samples may or may not be available. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. and a lifetime-buy period is in effect. Efforts are underway to better integrate information from third parties. OBSOLETE: TI has discontinued the production of the device.com/productcontent for the latest availability information and additional product content details.The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible). TI and TI suppliers consider certain information to be proprietary. Addendum-Page 1 . or Green (RoHS & no Sb/Br) .com 15-Apr-2008 PACKAGING INFORMATION Orderable Device CD74HC40103QM96Q1 (1) Status (1) ACTIVE Package Type SOIC Package Drawing D Pins Package Eco Plan (2) Qty 16 2500 Pb-Free (RoHS) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-2-250C-1 YEAR/ Level-1-235C-UNLIM The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. TBD: The Pb-Free/Green conversion plan has not been defined. TI bases its knowledge and belief on information provided by third parties.ti. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances. including the requirement that lead not exceed 0. (2) Eco Plan . TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. NRND: Not recommended for new designs. and thus CAS numbers and other limited information may not be available for release. Pb-Free (RoHS Exempt). PREVIEW: Device has been announced but is not in production. -. Where designed to be soldered at high temperatures. Device is in production to support existing customers. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. and makes no representation or warranty as to the accuracy of such information.1% by weight in homogeneous materials.The planned eco-friendly classification: Pb-Free (RoHS).ti. and peak solder temperature. Peak Temp. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package. but TI does not recommend using this part in a new design.please check http://www. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.

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