1. Explain Non-Recursive algorithms with suitable examples Explain the algorithms i Max element i General Plan i Unique Elements i Matrix Multiplication i Binary Representation

2. Explain Recursive algorithms with suitable examples Explain the algorithms ‡ Factorial ‡ General Plan ‡ Towers of Hanoi ‡ Binary Representation

3. Discuss about the empirical analysis of algorithms Explain ‡ General Plan ‡ Pseudo random numbers

4. Discuss briefly about Algorithmic visualization Explain ‡ Static algorithm visualization ‡ Dynamic algorithm visualization

5. Discuss about the Fibonacci numbers Explain about i Explicit formula i Computation i Iterative algorithm

2 Marks
1.What is cache memory? The small and fast RAM units are called as caches. When the execution of an instruction calls for data located in the main memory, the data are fetched and a copy is placed in the cache. Later if the same data is required it is read directly from the cache.

2. What is the function of ALU? Most of the computer operations (arithmetic and logic) are performed in ALU.The data required for the operation is brought by the processor and the operation is performed by the ALU.

3. What is the function of CU? The control unit acts as the nerve center, that coordinates all the computer operations. It issues timing signals that governs the data transfer.

4. What are basic operations of a computer? The basic operations are READ and WRITE.

5. What are the registers generally contained in the processor? MAR-Memory Address Register MDR-Memory Data Register IR-Instruction Register R0-Rn-General purpose Registers PC-Program Counter

11.Execute 4. Define interrupt and ISR? An interrupt is a request from an I/O device for service by the processor.Store 7.6. 9. What is System Software? Give an example? It is a collection of programs that are executed as needed to perform functions such as ‡ Receiving and interpreting user commands ‡ Entering and editing application programs and storing them as files in secondary storage devices. Define Bus? A group of lines that serves as a connecting path for several devices is called a bus. 10. What is the use of buffer register? The buffer register is used to avoid speed mismatch between the I/O device and the processor.e only one transfer at a time) is called as a single bus structure. Compiler etc . The processor provides the requested service by executing the interrupt service routine. Compare single bus structure and multiple bus structure? A system that contains only one bus(i.Fetch 2. 8. A system is called as multiple bus structure if it contains multiple buses. What are the steps in executing a program? 1. Linker. 12. Ex: Assembler. What is a compiler? A system software program called a compiler translates the high-level language program into a suitable machine language program containing instructions such as the Add and Load instructions.Decode 3.

in which the programmer specifies mathematical or text-processing operations. JAVA 14. 18.or actually a collection of routines. 17.this pattern of concurrent execution is called multiprogrraming or multitasking.The OS routines perform the tasks required to assign computer resources to individual application programs.where P is the length of one clock cycle.What is Application Software? Give an example? Application programs are usually written in a high-level programming language. . Ex: C. C++. R=1/P. What is processor time of a program? The periods during which the processor is active is called processor time of a programIt depends on the hardware involved in the execution of individual machine instructions. These operations are described in a format that is independent of the particular computer used to execute the program.that is used to control the sharing of and interaction among various computer units as they execute application programs. What is multiprogrraming or multitasking? The operating system manages the concurrent execution of several application programs to make the best possible uses of computer resources.the disk and the printer. Discuss about OS as system software? OS is a large is affected by the speed of the processor. 15. 16. Define clock rate? The clock rate is given by. What is text editor? It is used for entering and editing application programs.What is elapsed time of computer system? The total time to execute the total program is called elapsed time. 19. The user of this program interactively executes command that allow statements of a source program entered at a keyboard to be accumulated in a file.13.

What is branch target? As a result of branch instructions . 23. 25. What is a branch instruction? Branch instruction is a type of instruction which loads a new value into the program counter. instead of the instruction at the location that follows the branch instruction in sequential address order. 24. .What is pipelining? The overlapping of execution of successive instructions is called pipelining. What is byte addressable memory? The assignment of successive addresses to successive byte locations in the memory is called byte addressable memory. the processor fetches and executes the instruction at a new address called branch target. 26. The name little endian is used for the less significiant bytes of the word. often called condition code flags. What is big endian and little endian format? The name big endian is used when lower byte addresses are used for the more significiant of the word.What are condition code flags? The processor keep track of information about the results of various operations for use by subsequent conditional branch instructions.20. Write down the basic performance equation? T=N*S/R T=processor time N=no of instructions S=no of steps R=clock rate 21. 22. This is accomplished by recording the required information in individual bits.

Response time is the time between the start and the completion of the event.memory.Autodecrement addressing mode 29.Autoincrement addressing mode 8. What are the basic functional units of a computer? Input .Absolute addressing mode 2. How will you compute the SPEC rating? SPEC stands for system performance Evaluation Corporation Running time on the reference computer SPEC rating= _________________________________ Running time on the computer under test .Relative addressing mode 7. Define Response time and Throughput.Define addressing mode.Index addressing mode 5.Define various addressing modes.Indirect addressing mode 4.arithmetic and logic unit.output and control units are the basic functional units of a computer 30.27. The different ways in which the location of an operand is specified in an instruction are referred to as addressing modes. The various addressing modes are 1. 28.Immediate addressing mode 6.Register addressing mode 3. Also referred to as execution time or latency.Throughput is the total amount of work done in a given amount of time 31.

Overflow occurs when the carry bits Cn and Cn-1 are different.Give the representation for n bit ripple carry adder 34.Give the symbol of a full adder circuit for a single stage addition 33.32. Write down the Booth·s algorithm Multiplier Version of Multiplicand selected by bit i Bit i Bit i-1 000xM 0 1 +1 x M 1 0 -1 x M 110xM 35.What is the delay encountered for Cn-1.What are the 2 ways to detect overflow in an n-bit adder? Overflow can occur when the signs of two operands are the same. 36. Sn-1 and Cn in the FA for a single stage Cn-1 ² 2(n-1) Sn-1 ² 2(n-1)+1 Cn ² 2n 37.What is the delay encountered for all the sum bits in n-bit binary addition/subtraction logic unit? The gate delays with and without overflow logic are 2n+2 and 2n respectively 38. Pi=Xi xor with Yi .Write down the basic generate and propagate functions for stage i Gi = XiYi.

45.What is the delay encountered in the path in an n x n array multiplier The delay encountered in the path in an n x n array multiplier is 6(n-1)-1 42.What is skipping over of one·s in Booth decoding? The Transformation 011« 110= +100«0 ² 10 is called skipping over one·s.39. Give an example for the worst case of Booth algorithm The worst case is shown as below 010101010 +1-1+1-1+1-1+1-1+1 In the worst case each bit of the multiplier selects the summands. This results in more number of summands.What are the two attractive features of Booth algorithm ‡ It handles both positive and negative multipliers uniformly ‡ It achieves some efficiency in the number of additions required when the multiplier has a few large blocks of ones 44.What are the two approaches to reduce delay in adders ‡ Fastest electronic technology in implementing the ripple carry logic design ‡ Augmented logic gate network 41. 43.Write down the general expression for Ci+1 using first level generate and propagate function Ci+1 = Gi+PiGi-1+PiPi-1Gi-2+«+PiPi-1«P1G0+PiPi-1«P0G0 40. What are the two techniques for speeding up the multiplication operation? ‡ Bit Pair recoding ‡ CSA .In his case multiplier has its ones grouped into a few contiguous blocks.

Due to this the magnitude of the numbers can be compared. 2. 50. set Q0 to 1. add M back to A otherwise set Q0 to 1 51. Instead of letting the carries ripple along the rows. add M to A Restoring: ‡ Shift A and Q left one binary position ‡ Subtract M from A ‡ If the sign of A is one .46. set Q0 to 0.If the sign of A is 0.What is the need for adding binary 8 value to the true exponential in floating point numbers? This solves the problem of negative exponent. 47. at the correct waited position.7 49. otherwise set Q0 to 0 Step 2: If the sign of A is 1. Write down the steps for restoring division and non-restoring division Non-Restoring: Step1: Do the following n times 1. shift A and Q left one bit position and subtract M from A otherwise shift A and Q left and add M to A. Write down the levels of CSA steps needed to reduce k summands to two vectors in CSA The number of levels can be shown by 1.What is the advantage of non restoring over restoring division? Non restoring division avoids the need for restoring the contents of register after an successful subtraction. How CSA speeds up multiplication? It reduces the time needed to add the summands.The excess-x representation for exponents enables efficient comparison of the relative sizes of the two floating point numbers. How bit pair recoding of multiplier speeds up the multiplication process? It guarantees that the maximum number of summands that must be added is n/2 for nbit operands. 48.7log2k-1.Now if the sign of A is 0. . they can be saved and introduced into the next row.

52.significiant bits 3.In SP it means that the normalized representation requires an exponent greater than +127./0.Briefly explain the floating point representation with an example? The floating point representation has 3 fields 1. underflow case in single precision(sp)? Underflow-In SP it means that the normalized representation requires an exponent less than -126.single 2. Overflow.inexact and invalid values.exponent For example consider 1.11101100110 x 10^5. 55.underflow.What are the exceptions encounted for FP operation? The exceptions encounted for FP operation are overflow.What are the 2 IEEE standards for floating point numbers? 1. Mantissa=11101100110 Sign=0 Exponent=5 53.double 54.sign bit 2. .What is guard bits? Guard bits are extra bits which are produced during the intermediate steps to yield maximum accuracy in the final results. 56.What is overflow.

Chopping 2. ‡ Structural hazard ‡ Duplicating resources ‡ Stalling ‡ Data hazards o Stalling o Duplicating ‡ Control hazard.Explain the various types of hazards in pipelining? ‡ Instruction hazard ‡ Data hazard ‡ Structural hazard ‡ Control hazard 2. Explain the techniques used to overcome the various hazards.Rounding procedure 16 Marks 1. Write notes on super scalar operation? ‡ Explanation ‡ Diagram 3. Explain the multiple bus organization? ‡ Explanation ‡ Diagram 4.Von Neumann rounding 3.What are the ways to truncate guard bits? 1.57. ‡ Predicted taken branch scheme .

Or it is the time that elapses between the initiation of an operation and the completion of that operation.Read After Write (also known as True Data Dependency) ‡ WAW . Eg. 2. 3. 5. What is the maximum size of the memory that can be used in a 16-bit computer and 32 bit computer? The maximum size of the memory that can be used in a 16-bit computer is 216=64K memory locations. . 5. Define memory access time? The time required to access one word is called the memory access time.Write After Write (also known as Output Dependency) ‡ WAR . When is a memory unit called as RAM? A memory unit is called as RAM if any location can be accessed for a read or write operation in some fixed amount of time that is independent of the location·s address. What is MMU? MMU is the Memory Management Unit. The maximum size of the memory that can be used in a 32-bit computer is 232 =4G memory locations. 4.Explain the classification of data hazards in pipelining? ‡ RAW . Define memory cycle time? It is the minimum time delay required between the initiation of two successive memory operations.Write After Read (also known as Anti Data Dependency) 2 MARKS 1. It is a special memory control circuit used for implementing the mapping of the virtual address space onto the physical memory.‡ Predicted untaken branch scheme ‡ Flush or freeze technique ‡ Delayed branch scheme. The time between two successive read operations.

all the cells of a row are connected to a common line called as word line.What are the Characteristics of semiconductor RAM memories? They are available in a wide range of speeds. 12. 11. Define static memories? Memories that consists of circuits capable of retaining their state as long as power is applied is called Static memories.‡ Their cycle time range from 100ns to less than 10ns.‡ 10. 9.‡ They are used for implementing memories. What is a word line? In a memory cell.‡ They replaced the expensive magnetic core memories. ‡ They are of high cost. It is usually organized in the form of an array. Define memory cell? A memory cell is capable of storing one bit of information. . So SRAMs are said to be volatile.What are the Characteristics of SRAMs? ‡ SRAMs are fast.6. 7.What are the Characteristics of DRAMs? ‡ Low cost. ‡ Less density. 8.Why SRAMs are said to be volatile? Because their contents are lost when power is interrupted. ‡ They are volatile. ‡ High density.

Define Bandwidth? When transferring blocks of data. This measure is often referred to as the memory bandwidth.Define Refresh Circuit? It is a circuit which ensures that the contents of a DRAM are maintained when each row of cells are accessed periodically.‡ Refresh circuitry is needed. . 19. 17.Define Memory Latency? It is used to refer to the amount of time it takes to transfer a word of data to or from the memory. the timing of the memory device is controlled asynchronously.The processor must take into account the delay in the response of the memory.what are synchronous DRAMs? Synchronous DRAMs are those whose operation is directly synchronized with a clock signal. 13.what are asynchronous DRAMs? In asynchronous DRAMs. 14. A specialised memory controller circuit provides the necessary control signals RAS and CAS that govern the timing. since blocks can be variable in size it is useful to define a performance measure in terms of number of bits or bytes that can be transferred in one second. 15. it is of interest to know how much time is needed to transfer an entire block.What is motherboard? Mother Board is a main system printed circuit board which contains the processor. It will occupy an unacceptably large amount of space on the board. 16. such memories are asynchronous DRAMs . 18. What is double data rate SDRAMs? Double data rates SDRAMs are those which can transfer data on both edges of the clock and their bandwidth is essentially doubled for long burst transfers.

21. These chips use cell arrays based on the standard DRAM technology. It is used for performing multiplexing of address bits. . Differentiate static RAM and dynamic RAM? Static RAM Dynamic RAM They are fast They are slow They are very expensive They are less expensive They retain their state indefinitely They do not retain their state indefinitely They require several transistors They require less no transistors. Small voltage swings make it possible to have short transition times. the memory controller has to provide all the information needed to control the refreshing process. the signals consist of much smaller voltage swings around a reference voltage. Multiple banks of cell arrays are used to access more than one word at atime. Such chips are known as RDRAMs. What is Ram Bus technology? The key feature of Ram bus technology is a fast signaling method used to transfer information between chips.What is memory Controller? A memory controller is a circuit which is interposed between the processor and the dynamic memory. Circuitry needed to interface to the Rambus channel is included on the chip.20. vref. It can hold upto 16 RDRAMs.What are SIMMs and DIMMs? SIMMs are Single In-line Memory Modules. which do not have self refreshing capability . What are RDRAMs? RDRAMs are Rambus DRAMs. DIMMs are Dual In-line Memory Modules. When used with DRAM chips . Instead of using signals that have voltage levels of either 0 or V supply to represent the logic values. 24. which allows for a high speed of transmission.What are RIMMs? RDRAM chips can be assembled in to larger modules called RIMMs. Rambus requires specially designed memory chips. It also sends R/W and CS signals to the memory. 25.It provides RAS-CAS timing. Such modules are an assembly of several memory chips on a separate small board that plugs vertically into a single socket on the motherboard. Low density High density 23. 22.

‡ 29. . 32.What is cache memory? It is a small.What are the disadvantages of EPROM? The chip must be physically removed from the circuit for reprogramming and its entire contents are erased by the ultraviolet light.Why EPROM chips are mounted in packages that have transparent window? Since the erasure requires dissipating the charges trapped in the transistors of memory cells.‡ It has 18 data lines intended to transfer two bytes of data at a time.26. It reduces the memory access time. The only disadvantage is that different voltages are needed for erasing. This can be done by exposing the chip to UV light .‡ 27.What are the features of PROM? They are programmed directly by the user.. 28.What are the special features of Direct RDRAMs? It is a two channel Rambus. 31. fast memory that is inserted between the larger.‡ There are no separate address lines.What are the advantages and disadvantages of using EEPROM? The advantages are that EEPROMs do not have to be removed for erasure. It involves only reading of stored data. slower main memory and the processor. writing and reading the stored data.Also it is possible to erase the cell contents selectively. 30.‡ Faster‡ Less expensive‡ More flexible. Define ROM? It is a non-volatile memory.

Relatively lower density Lower cost per bit. Two aspects of locality of reference are temporal aspect and spatial aspect. and the remainder of the program is accessed relatively infrequently. Relatively more cost.. 35. 36. This property leads to the effectiveness of cache mechanism.What are the two ways in which the system using cache can proceed for a write operation? Write through protocol technique.33. It is possible to read and write the contents of a single cell. A flash cell is based on a single transistor controlled by trapped charge just like an EEPROM cell. Greater density which leads to higher capacity. 34. Differentiate flash devices and EEPROM devices. Temporal aspect is that a recently executed instruction is likely to be executed again very soon.Define flash memory? It is an approach similar to EEPROM technology. but it is only possible to write an entire block of cells. What are the two aspects of locality of reference?. Cache block is also referred to as cache line. Define them. Consumes more power. 37. Flash devices EEPROM devices It is possible to read the contents of a single cell. 38. This is referred to as locality of reference.š . What is locality of reference? Analysis of programs shows that many instructions in localized areas of the program are executed repeatedly during some time period. Cache block is used to refer to a set of contiguous address locations of some size. Consumes less power in their operation and makes it more attractive for use in portable equipments that is battery driven. The spatial aspect is that instructions in close proximity to a recently executed instruction are also to be executed soon. Define cache line.

42. when the block containing this marked word is to be removed from the cache to make room for a new block. and then the desired word in the cache is overwritten with the new information. What is write through protocol? For a write operation using write through protocol during write hit: the cache location and the main memory location are updated simultaneously. the information is written directly to the main memory. a read miss occur.What are the mapping technique? ‡ Direct mapping ‡ Associative mapping ‡ Set Associative mapping 44.Define hit rate? The number of hits stated as a fraction of all attempted access . The main memory location of the word is updated later.What is a hit? A successful access to data in cache memory is called hit.What is load-through or early restart? When a read miss occurs for a system with cache the required word may be sent to the processor as soon as it is read from the main memory instead of loading in to the cache.š 39. For a write miss: For a write miss. 43. This approach is called load through or early restart and it reduces the processor·s waiting period. .When does a readmiss occur? When the addressed word in a read operation is not in the cache.Write-back or copy back protocol technique. For a write miss: the block containing the addressed word is first brought into the cache. 45. often called the dirty or modified bit. 40. What is write-back or copy back protocol? For a write operation using this protocol during write hit: the technique is to update only the cache location and to mark it as updated with an associated flag bit. 41.

What is the formula for calculating the average access time experienced by the processor? tave=hc +(1-h)M Where h =Hit rate M=miss penalty C=Time to access information in the cache. It s disadvantage is poor bit-storage density. 49. 52.Define miss penalty? The extra time needed to bring the desired information into the cache.46.Describe the memory hierarchy? 48. .What is phase encoding or Manchestor encoding? It is one encoding technique for combining clocking information with data. 50.Define miss rate? It is the number of misses stated as a fraction of attempted accesses. It is a scheme in which changes in magnetization occur for each data bit. 47.Define access time for magnetic disks? The sum of seek time and rotational delay is called as access time for disks. Seek time is the time required to move the read/write head to the proper track. 51. Rotational delay or latency is the amount of time that elapses after the head is positioned over the correct track until the starting position of the addressed sector passes under the read/write head.What are the two ways of constructing a larger module to mount flash chips on a small card? ‡ Flash cards ‡ Flash drivers.

The collection of rules for making this decision constitutes the replacement algorithm.It is convenient to assemble the OS routines into a virtual address space.What are prefetch instructions? Prefetch Instructions are those instructions which can be inserted into a program either by the programmer or by the compiler. 58. .What is dirty or modified bit? The cache location is updated with an associated flag bit called dirty bit. 54. C2=Time to access information in the L2 cache.Define system space? Management routines are part of the operating system of the computer. 57.53. 55. the cache control hardware must decide which block should be removed to create space for the new block that contains the reference word . 56.What are pages? All programs and data are composed of fixed length units called pages. 59.Define user space? The system space is separated from virtual address space in which the user application programs reside. The letter space is called user space.each consists of blocks of words that occupies contiguous locations in main memory. What is the formula for calculating the average access time experienced by the processor in a system with two levels of caches? tave =h1c1(1-h1)h2c2+(1-h1)(1-h2)M where h1=hit rate in L1 cache h2=hit rate in L2 cache C1=Time to access information in the L1 cache.What is replacement algorithm? When the cache is full and a memory word that is not in the cache is referenced.

64. 67. 66. 65.What is virtual memory? Techniques that automatically move program and datablocks into the physical main memory when they are required for execution are called as virtual memory. 61. .60.What is virtual page number? Each virtual address generated by the processor whether it is for an instruction fetchis interpreted as a virtual page. 62.What is Winchester technology? The disk and the read/write heads are placed in a sealed air-filtered enclosure called Winchester technology.What is write miss? During the write operation if the addressed word is not in cache then said to be write miss.What is associative research? The cost of an associative cache is higher than the cost of a direct mapped cache because of the need to search all 128 tag patterns to determine whether a given block is in the cache. 63. A search of this kind is called an associative search.What is page frame? An area in the main memory that can hold one page is called as page frame.What is virtual address? The binary address that the processor used for either instruction or data called as virtual address.What is a disk drive? The electromechanical mechanism that spins the disk and moves the read/write heads called disk drive.

Explain the various types of computer systems.What is word count? The number of words in the block to be transferred.What is booting? When the power is turned on the OS has to be loaded into the main memory which takes place as part of a process called booting.‡ 74. 71. 69. Explain how protection is provided for the hardware resources by the operating system. 75. 73.What is disk controller? The electronic circuitry that controls the operation of the system called as disk controller.What is lockup-free? A cache that can support multiple outstanding misses is called lockup-free. 72. 2.What is main memory address? The address of the first main memory location of the block of words involved in the transfer is called as main memory address. 70.What is Error checking? It computes the error correcting code (ECC)value for the data read from a given sector and compares it with the corresponding ECC value read from the disk. .What are the two states of processor? Supervisor state‡ User state.To initiate booting a tiny part of main memory is implemented as a nonvolatile ROM.Draw the static RAM cell? 16 Marks 1.68.

Distinguish between multiprogramming (multi-tasking) and multiprocessing. Explain about interprocess communication. 16 Marks 1. Explain Co-operating process with example. What is a process? Explain the process control block and the various process states. Explain what semaphores are. Explain process creation and process termination 11. Discuss the design issues of distributed operating system. i) Multiprogrammed Systems ii) Time-sharing Systems 8. 2. Explain the following: i) Real-time Systems ii) Distributed Systems 9. Explain the classic problems of synchronization. 10. their usage. 14. What are the important issue involved in the Design and Implementation of operating systems? 12. a) Write about the various CPU scheduling algorithms. 4. Explain in detail about the threading issues. . What is critical section problem and explain two process solutions and multiple process solutions? 6. Write notes about multiple-processor scheduling and real-time scheduling. 3. What are the various process scheduling concepts 6. Write about the various system calls.3. 15. 5. 5. Give an overview about threads. What are operating system services? Explain each one of them. 13. Explain the essential properties of the following types of Operating System. 7. implementation given to avoid busy waiting and binary semaphores. What are the system components of an operating system and explain them? 4. b) Explain the various scheduling criteria used for comparing CPU scheduling algorithms. Define system calls. 7.

What are files and explain the access methods for files? 6. algorithm.Dinning philosopher Problem. 16 Marks 1. a) Explain process scheduler. 11. a process priority change at rate EA system uses the following preemptive priority-scheduling algorithm (processes with larger priority numbers have high priority). What is demand paging and what is its use? 2. . 2) for FCFS. What is thrashing and explain the methods to avoid thrashing? 4. Explain about Access Methods.SJF. 13. What is the algorithm that results from <F<0? Justify your statement. Explain the various CPU scheduling techniques with Gantt charts clearly as indicated by (process name. Write about critical regions and monitors. b) What is context switching? Explain briefly. What is the advantage of having different time-quantum size at different levels in Multi-level Feedback Queue (MFQ) based scheduling. 2) and (D. 7). 14.F. What is the job of a scheduling algorithm? State the objective of a good scheduling algorithm.8. priority and shortest job first scheduling algorithms. Explain the various page replacement strategies. a process priority changes at rate F(1). 0. Explain round robin. Processes enter the system with a priority of 0. 16.RR with quantum 1 and 2. While waiting on the ready queue. 3. 3. What is the algorithm that results from >E>0? E(2). 3. Explain the schemes for defining the logical structure of a directory.Producer Consumer Problem. 5. algorithm 10. 4). (C. 17. b) Describe in detail the Multi-level feedback queue scheduling. 15. What are p-threads? Explain with the code. 9. Explain about Dining Philosopher·s problem of Synchronization Explain. 12. 2.SRT. a) Explain the criteria for scheduling. arrival time. (B. Explain about Producer Consumer Problem Explain. While running. process time) for the following (A. .

3. Explain the following Page Replacement Algorithms: i.9. Explain in thrashing in detail. 14.1. or seven frames? Remember all frames are initially empty. three. Optimal replacement? (7 Faults) 15. 2.2. FIFO replacement (c). two. 7. How many page faults will occur if the program has three page frames available to it and uses: (a). six. 1.7. Write notes about the protection strategies provided for files.8. LRU replacement (b). 1. LRU approximation Algorithm iii. so your first unique pages will all cost one fault each. five. 8. 1. 1. Explain I/O Interlock. 8.0.7. four. 2. assuming one.2. How many page faults would occur for the following replacement algorithms. 9. 0.8. Optimal replacement . FIFO replacement? (8 Faults) (b). Explain Allocation of frames.8. 2. 3. What is page fault? Explain the procedure for handling the page fault using Demand paging? 10. Consider the following page reference string: 1. 3. 4.8. 2. 6. 1. Counting Algorithm 12. 13. 6. 3.8. 11.3. LRU replacement? (9 Faults) (c). 5. Explain in detail the WS clock page replacement algorithm. 6.2. Page Buffering Algorithm iv.7.3. 2. (a). Give references to the following pages by a program. Optimal Algorithm ii.7. 2.

we search for the page frame with the smallest counter. (b). 5. Define a page-replacement algorithm using this basic idea. (2) when counters are increased. 9. 4. Counters are increased³whenever a new page is associated with that frame. Define a page-replacement algorithm addressing the problems of: i. We can associate with each page frame a counter of the number of pages that are associated with that frame. for four page frames? 1. How many page faults occur for your algorithm for the following reference string. Then. rather than having them compete for a small number of page frames.Answer: Number of frames LRU FIFO Optimal 1 20 20 20 2 18 18 15 3 15 16 11 4 10 14 8 5 8 10 7 6 7 10 7 7777 16. A page-replacement algorithm should minimize the number of page faults. 7. ii. 8.(3) when counters are decreased. 9. What is the minimum number of page faults for an optimal page-replacement strategy for the reference string in part b with four page frames? Answer: (a). and (4) how the page to be replaced is selected. 8. 3. 5. to replace a page. 2. 2. (c). 4. 3. Initial value of the counters³0. 6. (a). 4. 7. 4. Specifically address the problems of (1) what the initial value of the counters is. 7. 5. . We can do this minimization by distributing heavily used pages evenly over all of memory. 8. 1.

(b). Counters are decreased³whenever one of the pages associated with that frame is no longer required. Reduction of block diagram Determination of Transfer function . Explain How components are secured in an information system? Explain in detail the various phases of System Development Life Cycle(SDLC)? Explain in detail the Security System Development Life Cycle(SecSDLC) Explain the history of information security Explain the approaches used for implementing information security Explain the critical characrteristics of information Explain NSTISSC Security model 10) Describe the information security roles to be played by various professionals in a typical organization 11) Write a note on balancing Security and Access 12) Explain with examples various threats to Information Security. iv. How the page to be replaced is selected³find a frame with the smallest counter. Use FIFO for breaking ties. 14 page faults (c). 16 Marks 1.Determination of the overall transfer function using Block diagram Reduction technique. 2. For a given mechanical or electrical or electromechanical system Derive the transfer Function. 11 page faults 16 Marks 1) 2) 3) 4) 5) 6) 7) 8) 9) Explain in detail the critical characteristics of information Explain the components of an Information System.iii.

Rise time . Settling time 2. Reduction of signal flow graph Apply masons gain formula 4.. . Write the differential equation Draw the equivalent electrical network 16 Marks 1.Write the procedure for constructing the block diagram of a given Mechanical or electrical or electromechanical system. Find the time response of a first order system for various standard inputs. .Find the electrical analogical variables of a mechanical rotational System. Explain the working of Synchro transmitter and receiver. Derive the expressions of the time domain specifications for a second order system with unit step input. Apply the input . Time response of second order system . Determination of the overall transfer function from the given signal flow Graph using Mason·s gain formula.3. Peak overshoot . Working principle 5. .Explain ac and dc servomotors 6. Write the differential equation Develop block diagram 7. Peak time . Diagram .

Solve using partial differential equation .For a second order system whose open loop transfer function is given to the system.2 and the peak time is 1 sec. time constant and the settling time for an error of 7%.Problems using static error coefficients or generalized error coefficients..For the system shown in the figure determine the values of K and Kh so that the maximum overshoot in the unit step response is 0. Find the time response of a second order system for unit step input.rG(s) =4 /s(s+2). .35) 6. With these values of K and Kh. .Obtain the unit step response of an unity feed back system whose open loop transfer function is G(s) =5(s+20)/s(s+4. Find the rise time. Apply inverse Laplace transform 3. Apply the input . Determine the maximum overshoot. Solve using partial differential equation . and then time to reach the maximum overshoot when a step displacement of 18 7. Apply inverse Laplace transform 4.14s+16.. Find the error coefficient . obtain rise time and settling time .5)(s2+3. Apply in formula 5.