The F-LDPC Family: High-Performance Flexible Modern Codes for Flexible Radio

Thomas R. Halford, Metin Bayram, Cenk Kose
TrellisWare Technologies, Inc. San Diego, CA, USA {thalford,mbayram,ckose}

Keith M. Chugg
Univ. of Southern California Los Angeles, CA, USA

Andreas Polydoros
Univ. of Athens Athens, Greece

Abstract—Flexibility is an increasingly important aspect of radio modem design. In this paper, flexibility within the physical (PHY) layer in general, and the forward error correction (FEC) component in particular, is examined in detail. Following a discussion of the need for flexible modern code designs that exhibit universally good performance across a wide range of operational scenarios (i.e., input block size, code rate, modulation), TrellisWare Technologies, Inc.’s Flexible Low-Density ParityCheck (F-LDPC) codes are offered as an example of a highperformance modern coding solution for flexible radio designs. Specifically, the F-LDPC family offers performance within 0.8 dB of theoretical bounds across a wide range of operational scenarios with a design that is especially amenable to low-complexity, highthoughput reconfigurable hardware implementation.

I. I NTRODUCTION Flexibility, adaptability, and reconfigurability are three aspects of radio design receiving ever more attention from industry, government, and the academe (cf., [1], and the references therein). This focus comprises such technological frameworks as software radio (SR) (cf., [2]), software defined radio (SDR) (cf., [3]), reconfigurable radio (cf., [4]), and cognitive/intelligent/smart radio (cf., [5]). European research efforts in this field were reviewed in [6]. At a high level, a flexible radio receiver is capable of processing signals defined by a plurality of modes. These different modes may be defined by distinct communication standards (e.g., the co-existence of UMTS and WLAN receiver processing chains in a single handset [7]), or within a single standard (e.g., the different modulations and code rates used to define different modes in the HiperLAN/2 standard). A flexible receiver may adaptively choose a specific operating mode in order to, e.g., achieve some quality of service (QoS) target (cf., [8]). Furthermore, a receiver may be reconfigured in order to process some new mode defined by, e.g., an over-the-air download (cf., [9]). In this paper, a particular aspect of the flexible radio concept is considered: flexibility in the FEC component of the PHY-layer. Modern flexible receivers must support modes corresponding a wide range of FEC operational scenarios. For example, the efficient transmission of control packets typically requires short block lengths, while the robust transmission of data packets typically requires long block lengths and code rates that adapt to changing channel conditions. A conceptually simple solution to offering such flexibility is to design a specific code for each mode, and to then implement

separate, mode-specific decoders (in software or softwarereconfigurable hardware). Such an approach is clearly inefficient - and possibly intractable - from an implementation complexity perspective. Furthermore, this approach is brittle with respect to reconfigurability in that any future modes to be supported by such a radio must employ one these pre-defined codes. A more pragmatic approach is to choose a family of codes that can be decoded by a single flexible architecture. While some loss in performance with respect to specific point designs is inevitably incurred by such a scheme, the gains in implementation complexity, flexibility, adaptability, and reconfigurability can vastly outstrip this performance penalty, provided the code family is properly designed. TrellisWare Technologies, Inc. (TWT) recently proposed a family of codes that offer the flexibility, high-performance, and high-throughput implementation architectures demanded by modern flexible radio receivers [10]. The F-LDPC family offers performance within 0.8 dB of theoretical bounds (cf., [11]) across a wide range of operational scenarios with a design that is especially amenable to low-complexity, high-throughput reconfigurable-hardware implementation. For example, TWT has implemented F-LDPC decoders in field-programmable gate arrays (FPGAs) - a core enabling technology for SDR [12] - which achieve throughput at and beyond 1 Gbps with full decoder convergence. Xilinx, Inc. featured such a decoder in its booth at MILCOM’06 in Washington, DC. A high-speed F-LDPC FPGA-based decoder was also featured at Altera Corp.’s MILCOM’07 in Orlando, FL. Finally, TWT recently announced the F-LDPC Chameleon ASIC encoder/decoder which achieves 1 Gbps throughput. This paper discusses the F-LDPC in the context of flexible radio design and is organized as follows. Section II briefly reviews modern codes and discusses existing popular designs in the context of flexible radios. The design and performance of the F-LDPC are discussed in Sections III and IV, respectively. Concluding remarks are given in Section V. II. F LEXIBLE M ODERN C ODES FOR F LEXIBLE R ADIOS A. Review of Modern Codes The introduction of turbo codes in 1993 [13] and the subsequent rediscovery of Gallager’s low-density parity-check (LDPC) codes [14], [15], revolutionalized coding theory and practice. In the ensuing years, there has been an explosion

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Many unstructured LDPCs are prone to early flooring due to non minimum-distance error events. respectively. This is particularly difficult as it is often observed that floor and threshold performance can be improved at each others expense. the amount of puncturing required results in degraded performance. the low implementation complexity of LDPCs. III. 1. arbitrary rates and block sizes cannot be supported. the code that results from a puncturing a good low-rate design does not generally a good high-rate code. Since the overall rate and block size of a TPC is determined by its constituent codes. and structured LDPCs (e... Performance is a function of the code’s minimum distance and distance spectrum in the floor and waterfall regions. the key challenge of modern coding is the construction of codes which excel in both the waterfall and floor regions for a given operational scenario. and floor performance that is a compromise between PCCCs and SCCCs. Classical Modern Eb/No (dB) Fig. T HE F-LDPC FAMILY In light of the above discussion.the waterfall region . however. However. Observe that the performance curve for the modern code is characterized by an initial steep reduction in error probability as Eb /N0 is increased . Observe that the performance curve for the classical code is characterized by a shallow reduction in error probability throughout. 1) PCCCs: While offering good threshold performance. Specifically. For similar reasons to PCCCs. Figure 1 illustrates typical error probability performance curves for modern and classical codes. Before beginning a discussion of a modern code family that does just this TWT’s F-LDPC . unstructured LDPCs exhibit poor flexibility. Existing Code Designs: A Flexible Radio Perspective While initially demonstrated for relatively low rates and large input block sizes [13]. which are designed in a manner more akin to PCCCs and SCCCs. practically implementable LDPC codes have thresholds that are typically comparable to PCCCs. turbo product codes (TPCs) [18].g.. 3) TPCs: TPCs have the worst threshold performance among all modern code designs (except for very high code rates and very large block sizes).3 dB). serially concatenated convolutional codes (SCCCs) [17]. From a performance perspective.followed by a region of shallower reduction in the floor region. combined with a decoding strategy that operates by passing messages between decoders for the simple constituent codes. 2) SCCCs: The threshold performance of SCCCs are worse than PCCCs (typically by ∼ 0. This situation is mirrored when implementation is considered: while lowcomplexity codes have been successfully design for specific operational scenarios. and a rate flexibility exceeding all existing popular designs. SCCCs exhibit good block size but poor code rate flexibility. . Most importantly. Classical codes thus operate in the floor (i. Block size flexibility can only be achieved by changing the matrix that defines the code. the key challenge of modern coding is the construction of codes which afford low-complexity decoding algorithms that are particularly amenable to high-throughput hardware implementation.. In terms of performance. which are defined by optimizing the sparse paritycheck matrix that defines the code. Practical modern code point designs must consider both performance and implementation complexity. [20]). modern codes have been shown to be capable of near-optimal performance for nearly all practical operational scenarios. Modern codes are characterized by the concatenation of two or more relatively simple codes separated by an interleaver. code rate flexibility is achieved by puncturing the output of the constituent codes. it is the presence of the waterfall region that distinguishes modern and classical codes. However. From an implementation complexity perspective. of interest in the design of such modern codes (in contrast to classical codes such as Reed-Solomon (RS) and convolutional codes [16]). but they exhibit among the best floors of all modern code designs. For very high code rates. What has been lacking in modern coding theory and practice is a single design that can simultaneously offer excellent performance and low decoding complexities across a wide range of operational scenarios. Typical error performance for modern and classical codes.g.the prevelant existing modern code designs are briefly viewed through the lens of flexible radio systems. block size and code rate flexibility are coupled in SCCCs which can complicate reconfigurability. PCCCs exhibit only modest code rate flexibility. Gallager’s codes [14]). no single design todate has offered the necessary flexibility and performance required for practical flexible radio design. the most popular modern code designs include parallel concatenated convolutional codes (PCCCs) [13].e. The block size of PCCCs can trivially be changed by modifying the interleaver size. 4) Unstructured LDPCs: Although LDPCs have been reported with threshold performance within a tiny fraction of a dB of theoretical limits (e. minimum distance dominated) region for all Eb /N0 values. The initial steep reduction at some Eb /N0 threshold allows systems employing modern codes to function reliably at lower signal-to-noise ratios (SNRs). repeat-accumulate codes [19]). floor performance similar to that of SCCCs. While some rate flexibility can be achieved via puncturing. To date.g. no single design to-date has offered lowcomplexity implementations across all operational scenarios of practical interest.Waterfall Region Block / Bit Error Rate Error Floor Region B. practically realizable PCCCs tend to suffer from poor floor performance. and the large family of LDPC codes that includes both unstructured LDPCs (e. a modern code design should be sought that exhibits the threshold performance and block size flexibility of PCCCs.

A. . the J refined code rate is Rp = J+2p . a number of authors have studied structured LDPCs. When a fraction p of the parity bits are transmitted. Encoder Structure Example 2-state Ir-S-SCP b i P/S 1+D dj I Q(i) 1/(1+D) J:1 Puncture IPG = Punctured Accumulator = P = kQ/J p parity bits m k systematic bits bi Fig. IV. e. which generates a parity bit stream. The performance of this F-LDPC code is strictly better than that of the CCSDS turbo code with identical 2 Note that similar block length flexibility can be achieved for PCCC and SCCC designs by using DRP interleavers. B. many modern code designs perform poorly at short block lengths and there remains a considerable gap between the performance of these codes and theoretical limits. 1 Indeed. and 256QAM. [24]) for processing the constituent inner and outer code trellises thus enabling parallel architectures that achieve very high throughputs. QPSK. In this section. 8/9.. As expected. Rate refinement can be achieved by further periodic puncturing of the parity bits.. If Q(i) is constant over all i. [26]).rather than storing the entire permuation . and modulations on the additive white Gaussian noise channel (AWGNC). Input block sizes from 3-1024 bytes in single byte increments are considered. therefore. Observe that the ith output of this convolutional code is repeated Q(i) times. a GRA code with the same performance as a regular Q = 2 F-LDPC typically requires 33%-50% more memory and suffers a 25% penalty in decoder throughput.g. The RS code is decoded using classical hard-in algebraic techniques (cf.. Figure 3 illustrates packet error rate (PER) versus receiver SNR curves for a range of code rates and modulation orders using min-sum decoding. A deeper discussion of hardware architectures for the F-LDPC family can be found in [23]. 2. The input and output block ¯ sizes of the F-LDPC are K and K(1 + Q(i)/J). and 16/17 are considered along with 8 fine rates using p = 16/16. The standard regular F-LDPC uses Q = 2 and thus has a (coarse) J code rate that depends only on J: Rc = J+2 . protograph (cf. To this end. F-LDPC Performance for Short Block Sizes It is now well-known that modern codes offer excellent performance with respect to classical codes when input block sizes are long.interleavers corresponding to an enormous range of block sizes (e.To this end. [10]. A block of K input bits feeds an outer code. For example. Note that the design of rate compatible Q(i) distributions for efficient irregular F-LDPC decoder architectures was discussed in [22]. . Flexibility Across Rate and Block Length In this section. Irregular variants of the F-LDPC are formed by varying Q(i) over i. This inner block is denoted an IPG rather than an inner code to highlight the fact that the IPG produces 1 output bit for every J inputs and thus has rate greater than unity. the performance degrades with decreasing input block size. Since rate flexibility for regular designs is achieved via puncturing. The interleaver length of a Q = 2 regular F-LDPC code is simply 2K and. the main advantage of F-LDPC codes over GRA codes lies in implementation complexity. Figure 4 illustrates PER vs. memory design and routing become the primal challenge. the design of the F-LDPC is closely related to that of GRA codes. the decoding complexity of the F-LDPC is highlighted in the context of input block size and code rate flexibility. Flexibility Without Sacrificing Throughput That the F-LDPC code family does not sacrifice performance for flexibility will be detailed in Section IV. 16QAM. 32 bits . As the degree of parallelism employed becomes large. The specific F-LDPC modes studied in this section were initially proposed as a potential coding solution for 802. respectively ¯ (where Q(i) is the average value of Q(i)). 4/5. The IPG comprises an accumulator (1/(1 + D)) followed by a J : 1 puncture. as will be seen in Section IV. TWT utilizes segment-based techniques (cf. 9/16. The F-LDPC constitutes an especially flexible structured LDPC design that is particularly amenable to high-throuput hardware implementation. Figure 5 compares the performance of the binary image of a rate 1/3 RS code with input block size 126 ¯ bits to that of a similar irregular F-LDPC with Q(i) = 4.g. .16K) can be implemented efficiently on a single chip. Observe that a 1% PER can be achieved from −2 dB to 27 dB SNR in increments of approximately 0. . [22]. The parity bit stream is then transmitted along with the systematic bit stream so that the resulting code is systematic. Since DRP interleavers are compactly described by a small parameter set .11n MIMO systems [23]. 5 Graymapped modulations are supported: BPSK. F-LDPC encoder structure. for a total of 40 overall codes rates from Rp = 1/2 to 32/33. 15/16. In order to demonstrate the efficacy of the F-LDPC for short block lengths. the uniformly good performance of the regular (Q = 2) F-LDPC family is demonstrated across a wide range of rates. [21]) and generalized repeataccumulate1 (GRA) codes [19]. A. the output of which is interleaved and then fed to an inner parity generator (IPG). the F-LDPC offers unparalleled code rate flexibility.. 2/3. The outer code is formed by the serial concatenation of a 2-state convolutional code (1 + D) and a repetition code (=). F-LDPC P ERFORMANCE E XAMPLES Figure 2 illustrates an encoder for a typical member of the F-LDPC family. block lengths. However. Finally. SNR curves for a range of input block block sizes (8 to 1000 bytes) with fixed rate (4/5) and modulation (16QAM). then the resulting F-LDPC code is regular. depends only on the input block size. Five coarse rates of Rc = 1/2.. 64QAM. B. overall hardware throughput is minimally affected.2 Finally. dithered relative-prime (DRP) interleavers [25] are used to ensure low-overhead addressing and contention-free memory access. .25 dB by varying the rate and modulation. As discussed in detail in [10] and [22].

R = 1/2 regular F-LDPC.5 11 11.5 1.3 outperforms those of the best known unstructured irregular LDPC codes [21]. Some of this difference can be accounted for by the fact that the RS decoder employing a hard-in algorithm that discards available soft information from the channel. [28]) decoding algorithms can improve performance by 1-2 dB. Twelve F-LDPC decoding iterations were performed. regular rate 1/2 F-LDPC on the AWGNC with BPSK modulation.5 3.g.5 13 13.001 0 5 10 15 SNR (dB) 20 25 30 0.5 5.5 6.0 1. While the F-LDPC family is no exception to this trend. This gap can be closed with a modest reduction in flexibility via irregular design. [27]) and novel iterative (e. Furthermore. These curves were produced via hardware simulation in order to simulate such low error rates with statistical confidence. however.1 10-1 F-LDPC Reed-Solomon 10-2 0.5 2.0 2. the use of such high-degree repetition constraints can impede the design of high-speed decoder architectures (e. As detailed in [22].8 1.001 10.3 dB of the best point designs over a wide range of operational scenarios.01 10-4 0. Fig.5 12 SNR (dB) Frame Size 8 bytes Block/Bit Error Rate 10-4 PER 10-5 10-6 10-7 10-8 10-9 10-10 Block Error Rate Bit Error Rate 0. All curves correspond to rate R=4/5. Observe that no error flooring was observed to occur at a bit error rate (BER) of 10−10 .5 dB.1 10-3 0.5 14 Eb/No (dB) Fig. Fifteen F-LDPC decoding iterations were performed. For high rates and small block sizes.g. the irregular profile used to define 3 Note that this 0. 3. For example. Comparisons to Optimized Point Designs A flexible code design generally incurs some performance penalty with repsect to a highly optimized point solution.7 1.. Gbps and higher throughput) for such codes. The protograph used to construct this code. C.8 0..01 1000 bytes 0. the F-LDPC outperforms the RS code by approximately 4.5 7.0 0. The rates and modulations range from R=1/2 BPSK (left) to R=32/33 256QAM (right). 4.1 0.5 1. the complexity of these algorithms vastly outstrip that of decoding the F-LDPC.9 12. it is remarkable in that this loss is minimal and can be tradedoff favorably with flexibility.4 1. Flexibility in rate and modulation of the F-LDPC.0 3.5 4. maximally flexible regular F-LDPC codes typically perform within 0.0 4.6 1.0 7.8 dB from the sphere packing bound (as extrapolated from curves in [11]).2 1. 5.0 1. Observe that at this low rate and short block length. In particular. parameters and approximately 0.0 5. 1 Fig. R = 1/3 F-LDPC and Reed-Solomon codes. When complexity is considered.. the performance of this particular F-LDPC code compares favorably to highly optimized point designs that have been reported in the literature. Figure 6 illustrates the performance of an input block size 4096. 100 10-1 10-2 0.3 1. Divsalar and Jones reported performance results of a protograph-based code with the same parameters that also does not floor by 10−10 BER and noted that the threshold of their code.1 1. which is approximately 0.25 dB threshold gap can be readily closed by careful construction of an irregular F-LDPC. Hardware performance of a K = 4096 bit. Soft algebraic (e.0 6.5 Bit Error Rate PER 10-3 10-5 Eb/No (dB) Fig. the F-LDPC provides the best performance known to the authors. contains degree-6 repetition constraints in contrast to the degree-3 constraints used to define the regualr F-LDPC.9 1.g. .25 dB better that this regular F-LDPC code. 6. 16QAM-modulated codes. Flexibility in block length of the F-LDPC. however. Performance comparison of K = 126 bit.

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