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Diagram of a generic dual-core processor, with CPU-local level 1 caches, and a shared, on-die level 2 cache.
An Intel Core 2 Duo E6750 dual-core processor.
An AMD Athlon X2 6400+ dual-core processor. In computing, a processor is the unit that reads and executes program instructions, which are fixed-length (typically 32 or 64 bit) or variable-length chunks of data. The data in the instruction tells the processor what to do. The instructions are very basic things like reading data from memory or sending data to the user display, but they are processed so rapidly that we experience the results as the smooth operation of a program. Processors were originally developed with only one core. The core is the part of the processor that actually performs the reading and executing of instructions. Single-core processors can process only one instruction at a time. (To improve efficiency, processors commonly utilize pipelines internally, which allow several instructions to be processed together; however, they are still consumed into the pipeline one at a time.)
A multi-core processor implements multiprocessing in a single physical package. In particular.1 Commercial incentives o 2. Contents [hide] y y y 1 Terminology 2 Development o 2. One can describe it as an integrated circuit which has two or more individual processors (called cores in this sense). however. unlike heterogeneous multi-core systems. SIMD.1 Trends o 3.2 Technical factors o 2.4 Disadvantages 3 Hardware o 3. In the best case. and graphics. The amount of performance gained by the use of a multi-core processor depends very much on the software algorithms and implementation. cores in multi-core systems may implement architectures like superscalar. Multi-core processors are widely used across many application domains including generalpurpose. so-called embarrassingly parallel problems may realize speedup factors near the number of cores. The parallelization of software is a significant on-going topic of research. Homogeneous multi-core systems include only identical cores. 2-dimensional mesh. vector processing. Many typical applications.A multi-core processor is composed of two or more independent cores. or beyond even that if the problem is split up enough to fit within each processor's or core's cache(s) due to the fact that the much slower main memory system is avoided. the possible gains are limited by the fraction of the software that can be parallelized to run on multiple cores simultaneously. and crossbar. network. a quad-core processor contains four cores (Such as the AMD Phenom II X4 and Intel 2010 core line.3 Advantages o 2. this effect is described by Amdahl's law. and a hexa-core processor contains six cores (Such as the AMD Phenom II X6 or Intel Core i7 Extreme Edition 980X). ring. Manufacturers typically integrate the cores onto a single integrated circuit die (known as a chip multiprocessor or CMP). Common network topologies to interconnect cores include bus. VLIW. embedded. digital signal processing (DSP). or onto multiple dies in a single chip package. For example. A dual-core processor contains two cores (Such as AMD Phenom II X2 or Intel Core Duo).2 Architecture . Just as with single-processor systems. or multithreading. cores may or may not share caches. A many-core processor is one in which the number of cores is large enough that traditional multi-processor techniques are no longer efficient ² largely due to issues with congestion supplying sufficient instructions and data to the many processors. and they may implement message passing or shared memory inter-core communication methods. Designers may couple cores in a multi-core device tightly or loosely. This threshold is roughly in the range of several tens of cores and probably requires a network on chip. which includes 3 levels of quad core processors). do not realize such large speedup factors.
the term multi-CPU refers to multiple physically separate processing-units (which often contain special circuitry to facilitate communication between each other). such as multi-chip module. These people generally refer to separate microprocessor dies in the same package by another name. Some systems use many soft microprocessor cores placed on a single FPGA. Some instruction-level parallelism (ILP) methods like superscalar pipelining are suitable for many applications. but are inefficient for others that tend to contain difficult-to-predict code. but are sometimes also applied to digital signal processors (DSP) and system-on-a-chip (SoC). some[who?] use these terms to refer only to multi-core microprocessors that are manufactured on the same integrated circuit die.1 Commercial o 6.3 Academic 7 Notes 8 See also 9 References 10 External links  Terminology The terms multi-core and dual-core most commonly refer to some sort of central processing unit (CPU). Many applications are better suited to thread level parallelism (TLP) methods.  Development While manufacturing technology improves. Some effects of these physical limitations can cause significant heat dissipation and data synchronization problems.y y y y y y y 4 Software impact o 4.1 Licensing 5 Embedded applications 6 Hardware examples o 6. reducing the size of single gates. The terms many-core and massively multi-core sometimes occur to describe multi-core architectures with an especially high number of cores (tens or hundreds). A combination of increased available space (due to refined . physical limits of semiconductor-based microelectronics have become a major design concern. The demand for more-capable microprocessors encourages CPU designers to use various methods with a view to increasing performance. In contrast to multi-core systems. Additionally. This article uses both the terms "multi-core" and "dual-core" to reference microelectronic CPUs manufactured on the same integrated circuit. Each "core" can be considered a "semiconductor intellectual property core" as well as a CPU core. unless otherwise noted.2 Free o 6. and multiple independent CPUs is one common method used to increase a system's overall TLP.
Additionally: y y Utilizing a proven processing-core design without architectural changes reduces design risk significantly.  Commercial incentives Several business motives drive the development of dual-core architectures. The power wall poses manufacturing. This helps only to the extent that memory bandwidth is not the bottleneck in performance. This is due to three primary factors: 1. the trend of consuming exponentially increasing power with each factorial increase of operating frequency. For decades. Alternatively. especially for CISC architectures. . For general-purpose processors. the increasing gap between processor and memory speeds. Multiple processors had to be employed to gain speed in computation. The ILP wall. 2.  Technical factors Since computer manufacturers have long implemented symmetric multiprocessing (SMP) designs using discrete CPUs. to the point where microwavefrequency circuit layout techniques had to be employed. and more (multi-core). This led to the use of multiple cores on the same chip to improve performance. The CPUs could also be driven at faster clock rates. for the same circuit area. which could then lead to better sales of CPU chips which had dual cores.manufacturing processes) and the demand for increased TLP led to the development of multicore CPUs. much of the motivation for multi-core processors comes from greatly diminished gains in processor performance from increasing the operating frequency. The terminology "dual-core" (and other multiples) lends itself to marketing differentiation from single-CPU processors. system design and deployment problems that have not been justified in the face of the diminished gains in performance due to the memory wall and ILP wall. The power wall. the increasing difficulty of finding enough parallelism in a single instructions stream to keep a high-performance single-core processor busy. it was possible to improve performance of a CPU by shrinking the area of the integrated circuit which drove down the cost of the silicon used per device. more transistors could be utilized in the design. the issues regarding implementing multi-core processor architecture and supporting it in software are well known. The memory wall. This increase can be mitigated by "shrinking" the processor by using smaller traces for the same logic. This effect pushes cache sizes larger in order to mask the latency of memory. 3. Eventually these techniques failed to improve the CPU performance. which increased functionality. One manufacturer has produced a 48-core for research in processors used for cloud computing.
like the L2 cache and the interface to the front side bus (FSB). adding more cache suffers from diminishing returns. multi-core design can make use of proven CPU core library designs and produce a product with lower risk of design error than devising a new wider core-design. manufacturers such as Intel and AMD have turned to multi-core designs.In order to continue delivering regular performance improvements for general-purpose processors. a dual-core processor uses slightly less power than two coupled single-core processors. the ability of multi-core processors to increase application performance depends on the use of multiple threads within applications. . The largest boost in performance will likely be noticed in improved response-time while running CPU-intensive processes. the multi-core CPU designs require much less printed circuit board (PCB) space than do multi-chip SMP designs. this means that signals between different CPUs travel shorter distances. since individual signals can be shorter and do not need to be repeated as often. Assuming that the die can fit into the package. but so are the alternatives. The situation is improving: for example the Valve Corporation's Source engine offers multi-core support. Apple Inc. physically. and Crytek has developed similar technologies for CryEngine 2. which powers their game. Also. Mac OS X Snow Leopard has built-in multi-core facility called Grand Central Dispatch for Intel CPUs.'s latest OS. These higherquality signals allow more data to be sent in a given time period. and therefore those signals degrade less. or searching for folders.  Advantages The proximity of multiple CPU cores on the same die allows the cache coherency circuitry to operate at a much higher clock-rate than is possible if the signals have to travel off-chip. An especially strong contender for established markets is the further integration of peripheral functions into the chip. sacrificing lower manufacturing-costs for higher performance in some applications and systems. ripping/burning media (requiring file conversion). if the automatic virus-scan runs while a movie is being watched. the cores share some circuitry. Emergent Game Technologies' Gamebryo engine includes their Floodgate technology which simplifies multicore development across game platforms. In addition. Combining equivalent CPUs on a single die significantly improves the performance of cache snoop (alternative: Bus snooping) operations. Furthermore. Put simply. For example. Crysis. like antivirus scans. Multi-core architectures are being developed. Also. the application running the movie is far less likely to be starved of processor power. principally because of the decreased power required to drive signals external to the chip.  Disadvantages Maximizing the utilization of the computing resources provided by multi-core processors requires adjustments both to the operating system (OS) support and to existing application software. as the antivirus program will be assigned to a different processor core than the one running the movie playback. In terms of competing technologies for the available silicon die area. Also.
while others use a mixture of different cores. single CPU designs may make better use of the silicon surface area than multiprocessing cores. especially in processing multimedia. Two processing cores sharing the same system bus and memory bandwidth limits the real-world performance advantage. In addition. From an architectural point of view. Some architectures use one core design repeated consistently ("homogeneous"). hence any two working dual-core dies can be used. [. If a single core is close to being memory-bandwidth limited.. He suggested the cellphone's use of many specialty cores working in concert is a good model for future multi-core designs. took the opposing view. "heterogeneous". The article CPU designers debate multi-core future  by Rick Merritt.. recognition and networking applications. each optimized for a different. He said multi-core chips need to be homogeneous collections of general-purpose cores to keep the software model simple.] Anant Agarwal. going to dual-core might only give 30% to 70% improvement. laptop computers and portable media players). octo-core chips to ones with tens or even hundreds of cores. hexa-. EE Times 2008.  Hardware  Trends The general trend in processor development has moved from dual-.  Architecture The composition and balance of the cores in multi-core architecture show great variety.] suggested computers should be more like cellphones.. and special-purpose "heterogeneous" cores promise further performance and efficiency gains. as opposed to producing four cores on a single die and requiring all four to work to produce a quad-core. Finally. Intel has partially countered this first problem by creating its quad-core designs by combining two dual-core on a single die with a unified cache. memory-on-chip. There is also a trend of improving energy-efficiency by focusing on performance-per-watt with advanced fine-grain or ultra fine-grain power management and dynamic voltage and frequency scaling (i. [. role . founder and chief executive of startup Tilera. generally agreed.e. which would count as more than 100% improvement. multi-core chips mixed with simultaneous multithreading. quad-. a senior chief engineer at Renesas." . tri-.] Atsushi Hasegawa. so a development commitment to this architecture may carry the risk of obsolescence.. If memory bandwidth is not a problem. raw processing power is not the only constraint on system performance. It would be possible for an application that used two CPUs to end up running faster on one dual-core if communication between the CPUs was the limiting factor..Integration of a multi-core chip drives chip production yields down and they are more difficult to manage thermally than lower-density single-chip designs. a 90% improvement can be expected.. using a variety of specialty cores to run modular software scheduled by a high-level applications programming interface. ultimately. includes comments: "Chuck Moore [.
Intel's MKL and AMD's ACML are written in these native languages and take advantage of multi-core processing. OpenMP. Software impact An outdated version of an anti-virus application may create a new thread for a scan process.g. Programming truly multithreaded code often requires complex co-ordination of threads and can easily introduce subtle and difficult-to-find bugs due to the interleaving of processing on data shared between threads (thread-safety). the extra overhead of development has been difficult to justify due to the preponderance of single-processor machines. Cray's Chapel. a multicore architecture is of little benefit for the application itself due to the single thread doing all heavy lifting and the inability to balance the work evenly across multiple cores. Multi-core processing has also affected the ability of modern computational software development. Other research efforts include the Codeplay Sieve System. FastFlow. Sun's Fortress. Also. the extent to which software can be multithreaded to take advantage of these new chips is likely to be the single greatest constraint on computer performance in the future. serial tasks like decoding the entropy encoding algorithms used in video codecs are impossible to parallelize because each result generated is used to help create the next result of the entropy decoding algorithm. This then requires the use of numerical libraries to access code written in languages like C and Fortran. Managing concurrency acquires a central role in developing parallel applications. and IBM's X10. These MPUs are going to replace the traditional Network Processors that were based on proprietary micro. which perform math computations faster than newer languages like C#. Skandium. Some existing parallel programming models such as Cilk++. In such cases. Consequently. cancel the scan). while its GUI thread waits for commands from the user (e. Although threaded applications incur little additional performance penalty on single-processor machines. such code is much more difficult to debug than single-threaded code when it breaks. If developers are unable to design software to fully exploit the resources provided by multiple cores. then they will ultimately reach an insurmountable performance ceiling. and MPI can be used on multi-core platforms. Intel introduced a new abstraction for C++ parallelism called TBB. The telecommunications market had been one of the first that needed a new design of parallel datapath packet processing because there was a very quick adoption of these multiple-core processors for the datapath and the control plane.or pico-code. Developers programming in newer languages might find that their modern languages do not support multi-core functionality. Given the increasing emphasis on multicore chip design. The basic steps in designing parallel applications are: Partitioning . stemming from the grave thermal and power consumption problems posed by any further significant increase in processor clock speeds. Parallel programming techniques can benefit from multiple cores directly. There has been a perceived lack of motivation for writing consumer-level threaded applications because of the relative rarity of consumer-level multiprocessor hardware.
This allows for Web servers and application servers that have much better throughput. In the past a CPU was a processor and most computers had only one CPU.  Embedded applications . the trend seems to be counting dual-core chips as a single processor: Microsoft. tasks identified by the partitioning phase. in general. proprietary enterprise-server software is licensed "per processor". Microsoft have said they would treat a socket as a single processor. execute independently. Mapping In the fourth and final stage of the design of parallel algorithms. They also determine whether it is worthwhile to replicate data and/or computation. the developers specify where each task is to execute. each of greater size. If multi-chip modules count as one processor. On the other hand. on the server side. CPU makers have an incentive to make large expensive multi-chip modules so their customers save on software licensing. no matter how many cores each die has. In particular. Oracle counts an AMD X2 or Intel dual-core CPU as a single processor but has other numbers for other types.  Licensing Typically. The computation to be performed in one task will typically require data associated with another task. However. and AMD support this view. It seems that the industry is slowly heading towards counting each die (see Integrated circuit) as a processor. or agglomerate. Developers revisit decisions made in the partitioning and communication phases with a view to obtaining an algorithm that will execute efficiently on some class of parallel computer. multicore processors are ideal because they allow many users to connect to a site simultaneously and have independent threads of execution. Hence. This mapping problem does not arise on uniprocessors or on shared-memory computers that provide automatic task scheduling. IBM and HP count a multichip module as multiple processors. the focus is on defining a large number of small tasks in order to yield what is termed a fine-grained decomposition of a problem. development moves from the abstract toward the concrete. so there was no ambiguity. Now there is the possibility of counting cores as processors and charging a customer for multiple licenses for a multi-core CPU. Data must then be transferred between tasks so as to allow computation to proceed. so as to provide a smaller number of tasks. Communication The tasks generated by a partition are intended to execute concurrently but cannot.The partitioning stage of a design is intended to expose opportunities for parallel execution. This information flow is specified in the communication phase of a design. Agglomeration In the third stage. especially for processors with more than two cores. Intel. developers consider whether it is useful to combine.
released in 2005. In addition. . wireless applications. dual-core desktop processors. quad-. with companies such as Freescale Semiconductor. dual-. o Athlon II. dual-. 8-. up to 128 cores. Indeed. and 12-core server/workstation processors. a 48-core processor. and hex-core desktop processors. a 24-core processor. Athlon 64 FX and Athlon 64 X2 family. released in 2006. it is easier for developers to adopt new technologies and as a result there is a greater variety of multicore processing architectures and suppliers. triple-. a 336-core Massively Parallel Processor Array (MPPA) AMD o Athlon 64. Freescale the four-core MSC8144 and six-core MSC8156 (and both have stated they are working on eight-core successors).  Hardware examples  Commercial y y y y y y y y Aeroflex Gaisler LEON3. and quad-core desktop processors. o Vega 2. Inc with 40 and 80 general purpose ALUs per chip. in many cases the application is a "natural" fit for multicore technologies. In digital signal processing the same trend applies: Texas Instruments has the three-core TMS320C6488 and four-core TMS320C5441. dual-core laptop processors. o Opteron. focused on communication applications. o Turion 64 X2. a multi-core SPARC that also exists in a fault-tolerant version. Ambric Am2045. multi-core network processing devices have become mainstream. making issues of software portability. Ageia PhysX. if the task can easily be partitioned between the different processors. all programmable in C as a SIMD engine and Picochip with three-hundred processors on a single die. o Radeon and FireStream multi-core GPU/GPGPU (10 cores. Newer entries include the Storm-1 family from Stream Processors. dual-core entry level processors. hex-. o Sempron X2. intended for high-performance embedded and entertainment applications. a multi-core physics processing unit. As a result. Azul Systems o Vega 1. triple-. legacy code or supporting independent developers less critical than is the case for PC or enterprise computing. Wintegra and Broadcom all manufacturing products with eight processors. quad-. o Phenom.Embedded computing operates in an area of processor technology distinct from that of "mainstream" PCs. 16 5-issue wide superscalar stream processors per core) Analog Devices Blackfin BF561. dual-. As of 2010. The same technological drivers towards multicore apply here too. ASOCS ModemX. Cavium Networks. embedded software is typically developed for a specific hardware release. a symmetrical dual-core processor ARM MPCore is a fully synthesizable multicore container for ARM11 MPCore and ARM Cortex-A9 MPCore processor cores.
IBM o POWER4. Hewlett-Packard PA-8800 and PA-8900. Core i5 and Core i7. the world's first non-embedded dual-core processor. a 4. dual core PA-RISC processors. o POWER6. a 16-core MIPS MPU. both multi-core DSPs. released in 2008 (32/64-bit floating point. a dual-core processor. which the company says will be released within the next five years. released in 2008. Power Architecture MPU. a dual-core. quad-threaded MIPS64 processor Nvidia o GeForce 9 multi-core GPU (8 cores. quad-threaded MIPS64 processor o XLS. an eight-core. PowerPC microprocessor used in the Microsoft Xbox 360 game console. IntellaSys  o SEAforth 40C18. a dual-core processor. o Core Duo. a dual-core processor. o Xenon. the successor of the Core 2 Duo and the Core 2 Quad. released in 2010. a dual-core processor. IBM. 192-core processor. a family of multi-core processors. a 32-core. SMT-capable. quad-. up to 8 cores. o POWER5. o Pentium Dual-Core. o Core 2 Quad. used in the Apple Power Mac G5. home gateway processor. o PowerPC 970MP. Freescale Semiconductor QorIQ series processors. 16 scalar stream processors per core) o . Intel o Celeron Dual-Core. 2 single-core dies packaged in a multi-chip module. o Itanium 2. the first dual-core processor for the budget/entry-level market. a triple-core. a dual-core processor. and Toshiba Cell processor. o POWER7.6. Sony. and octo-core processors. a 3. a dual-core processor. MIPS-based. SB1255 and SB1455. o Core 2 Duo. Broadcom SiByte SB1250. quad-threaded MIPS64 processor o XLR. a 40-core processor o SEAforth24. 80-core processor prototype. hexa-. released in 2001.y y y y y y y y y y y y y Vega 3.8-core processor. Integer ALU) Cradle Technologies CT3400 and CT3600. an eight-core. a 54-core processor. 2 dual-core dies packaged in a multi-chip module. Cavium Networks Octeon. o Core i3.16 GHz. Moore NetLogic Microsystems o XLP. a dual-core processor. o Pentium D. ClearSpeed o CSX700. a 24-core processor designed by Charles H. released in 2004. o Pentium Extreme Edition. o Teraflops Research Chip (Polaris). 2 single-core dies packaged in a multi-chip module. o Xeon dual-. a nine-core processor with one general purpose PowerPC core and eight specialized SPUs (Synergystic Processing Unit) optimized for vector operations used in the Sony PlayStation 3 Infineon Danube. released in 2007.
^ Digital signal processors (DSPs) have utilized multi-core architectures for much longer than high-end general purpose processors. Davis. This allows for the design of products that require a general purpose processor for user interfaces and a DSP for real-time data processing. executing threads within the OS independently. Is now out of business. two-core VLIW processor o UltraSPARC IV and UltraSPARC IV+. a growing number of companies have developed multi-core DSPs with very large numbers of processors.2 GHz AsAP2  Notes 1. a five-core multimedia video processor. processors work in a shared space. SiCortex "SiCortex node" has six MIPS64 cores on a single chip. in an SMP OS. o UltraSPARC T1. In other applications. o UltraSPARC T3. . 24 scalar stream processors per core) Parallax Propeller P8X32. 32-thread processor. Tilera o TILE64. picoChip PC200 series 200±300 cores per device for DSP & wireless Plurality HAL series tightly coupled 16-256 cores. L1 shared memory. Sun Microsystems o MAJC 5200. a 64-core 32-bit processor o TILE-Gx. 128-concurrent-thread processor. an sixteen-core. a 257-core microcontroller with a PowerPC core and 256 8-bit "processing elements". ^ Two types of operating systems are able to utilize a dual-CPU multiprocessor: partitioned multiprocessing and symmetric multiprocessing (SMP). A typical example of a DSP-specific implementation would be a combination of a RISC CPU and a DSP MPU. 16-core RAW processor University of California.y y y y y y y y y GeForce 200 multi-core GPU (10 cores. hardware synchronized processor. 24 scalar stream processors per core) Tesla multi-core GPGPU (10 cores. each CPU boots into separate segments of physical memory and operate independently. a 100-core 64-bit processor XMOS Software Defined Silicon quad-core XS1-G4 o o  Free y OpenSPARC  Academic y y MIT. In a partitioned architecture. an eight-core. Asynchronous array of simple processors (AsAP) o 36-core 610 MHz AsAP o 167-core 1. Rapport Kilocore KC256. this type of design is common in mobile phones. 64-concurrent-thread processor. an eight-core microcontroller. an eight-core. o UltraSPARC T2. Texas Instruments TMS320C80 MVP. 2. dual-core processors.
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