IN NANOSCALE MOSFET
3 TIDAK TERHAD
Disahkan oleh
Alamat Tetap:
Tarikh: Tarikh:
Signature : .……………………………………….…
Name of Supervisor : Professor Madya Dr. Razali Bin Ismail .
Date : .
BAHAGIAN A – Pengesahan Kerjasama*
Adalah disahkan bahawa projek penyelidikan tesis ini telah dilaksanakan melalui
kerjasama antara_______________ dengan _________________
Disahkan oleh:
Tandatangan : ………………………………………… Tarikh: ……………..
Nama : ………………………………………………
Jawatan : ………………………………………………
(Cop rasmi)
DECEMBER 2006
ii
I declare that this thesis entitled “Modeling the Effect of Velocity Saturation in
Nanoscale MOSFET” is the result of my own research except as cited in references.
The thesis has not been accepted for any degree and is not concurrently submitted in
candidature of any other degree.
To my wonderful parents and family, for their guidance, support, love and
enthusiasm. I am so thankful for that blessing and for the example you both are to me
over the years. I would not have made it this far without your motivation and
dedication to my success. Thank you, mom and dad, I love you both.
iv
ACKNOWLEDGEMENTS
I thank the many good friends I met here, Kaw Kiam Leong, Ng Choon Peng,
Lee Zhi Feng and many others for the encouragement and unforgettable memories.
They have always given me the chance to discuss my academic issues as well as my
personal issues. Without them, I could not have been completed my study. Very
valuable advice was also given by fellow friend, Dr Kelvin Kwa for his sharing of
experience, sachets of tea and coffee, books and advices. Also, thank to my friends
Sim Tze Yee, Liu Chin Foon, Liew Eng Yew, Gan Hock Lai and Alvin Goh Shing
Cyhe. I cherish the ideas they have given me, their support and warmhearted
friendship.
ABSTRACT
ABSTRAK
TABLE OF CONTENTS
DECLARATION ii
DEDICATION iii
ACKNOWLEDGEMENTS iv
ABSTRACT v
ABSTRAK vi
TABLE OF CONTENTS vii
LIST OF TABLES xi
LIST OF FIGURES xii
LIST OF ABBREVIATIONS xvi
LIST OF SYMBOLS xviii
1 INTRODUCTION 1
1.1 Background 1
1.2 Problem Statements 4
1.3 Objectives 5
1.4 Research Scope 5
1.5 Contributions 6
1.6 Thesis Organization 7
2 LITERATURE REVIEW 9
2.1 Non Ideal Effects in MOSFET 9
2.2 Velocity Saturation 10
viii
3 RESEARCH METHODOLOGY 29
3.1 Velocity Saturation Electrical Modeling 29
3.2 Intel Proprietary Softwares 31
3.3 Parameters Extraction for Proposed 32
Model
3.4 MOSFET Modeling for Circuit 33
Simulation
3.5 NMOS Transistor 34
9 CONCLUSIONS AND 83
RECOMMENDATIONS
9.1 Summary and Conclusion 83
9.2 Recommendations 84
REFERENCES 86
LIST OF TABLES
LIST OF FIGURES
LIST OF ABBREVIATIONS
IC  Integrated Circuit
k  Boltzmann’s constant
L  Channel length
S  Spacer thickness
Si  Silicon
LIST OF SYMBOLS
E  Electric Field
k  Boltzmann’s constant
L  Channel length
μm  micrometer
μc  Coulombic scattering
φf  Fermi potential
nm  nanometer
ρ  Effective resistivity
Qn  Inversion Charge
Rd  Source resistance
S  Spacer thickness
vd  Drift velocity
Vc  Critical Voltage
Vt  Threshold Voltage
W  Channel width
xj  Junction depth
LIST OF APPENDICES
A Publication 93
INTRODUCTION
1.1 Background
In silicon chip manufacturing, feature size and wafer size is the two most
important parameter as they determined the cost of a plant and production line
equipments. Presently, 300 mm wafers is the largest silicon wafers which produce
more than double as many chips as the older 200 mm wafers. Since the end of 2005,
Intel is the first manufacturer offering single and core 2 duo processors based on 65
nm production technologies. 65 nm generation transistors come with gates that are
able to turn a transistor on and off measuring only 35 nm which is roughly 30 percent
smaller than 90 nm technology gate lengths. Intel claims that 65 nm transistors cut
current leakage by four times compared to previous process technology. According
to Figure 1.2, new technology generation is introduced every 24 months and this
2
Feature Size
Gate Length
vd = μeff E (1.1)
where µeff is the effective mobility. When the electric field applied is increase,
nonlinearities appear in the mobility and carriers in the channel will have an
increased velocity. In high field, charge carriers gain and lose their energy rapidly
particularly through phonon emission until the drift velocity reaches a maximum
value called velocity saturation. Velocity saturation in MOSFET will yield a smaller
lower drain current and voltage. A cross section of a MOSFET is illustrated in
Figure 1.3. This research focuses on the role of velocity saturation has on the
characteristic of MOSFET in term of the carrier velocity field, carrier doping
concentration, drain current versus drain voltage curve. Intel proprietary software is
used to generate the experimental drain current versus drain voltage characteristic for
90nm generation of MOSFET. After parameter extraction is carried out, several
compact models are employed to study the effect of velocity saturation and the
impact of high electric field. The modified device models will be able the predict
behavior of electrical devices based on fundamental physics. Characteristics and
gives us the mobility and the drift velocity of the electrons versus transverse and
longitudinal electric field respectively.
4
Gate Oxide
N+
N+ N+ Drain Regions
Poly Si Gate
Isolation
P
Substrate/ Well
1.3 Objectives
The research is divided into three major phases. In the beginning, literature
review and previous researches in this field is carried out. Strengths and weaknesses
of available model and equations are compared. The second phase begins with the
modeling based on the literature review. A semiempirical model for velocity
saturation due to high field mobility degradation is presented. Best fit model
parameters are extracted from the experimental results. The results compared with a
6
set of published experimental data points and validated. The final phase is preceded
with analysis incorporating all the derived and modified models.
Future improvements and suggestion for the model are presented at the end of
the thesis. Nchannel MOSFET with polysilicon gate is used in this research. The
Ids compact model is derived by studying and analyzing Berkeley ShortChannel
IGFET Model 3 Version 3 (BSIM3v3) standard (Berkeley, 2005). The one region
equation from linear to saturation is based on the modification of the conventional
long channel model with the addition of second order effects, each parameter with its
physical meanings. Other semi empirical models include threshold voltage, mobility
and source drain series resistance.
1.5 Contributions
The modified short channel models are able to overcome the limitations of
previously long channel analytical and semi empirical models without velocity
saturation. It is also the interest of this study to find out the critical voltage and
electric field when velocity saturation appears. Based on this evaluation, it can
provide a guideline for designers in term of graphical representation on figures and
as well as parameter dependency relationship on the mobility behaviour, including
threshold voltage, doping concentration and temperature. Designer can examine the
behavior of the device when it is saturated at high electric field under specific
7
temperature and doping concentration. They can improve their design after a
thorough testing to prevent device breakdown.
Chapter 3 deals with the work flow of this research. It also introduce the
modeling process as well as the Intel Proprietary Schematic Editor and Circuit
Simulator. Chapter 4 marks the beginning of the proposed models formulation with
the introduction of threshold voltage modeling. Chapter 5 discusses about the
electron mobility model in MOS inversion layer. A comprehensive semi empirical
8
drain current and voltage model is explained in Chapter 6 by studying the long
channel characteristics and short channel effects. In addition, this chapter also
includes the derivation of source and drain resistance equation which normally
omitted in long channel devices. In Chapter 7, we study the velocity field model
which describes the effects of high vertical and lateral field in inversion layer pinch
off and velocity saturation.
LITERATURE REVIEW
second order effects (SOE) and occurs in short channel device is where the effective
channel length is approximately equal to the source and drain junction depth.
Among the SOE which need to be examined carefully in short channel device
design are mobility degradation, velocity saturation, hot carrier effects, short channel
effects and narrow width effects (Taur et al., 1997). Without doubt, one of the most
widely discussed effects is velocity saturation that has a significant implication upon
the current voltage characteristics of the short channel MOSFET.
vd (cm/s)
E (V/cm)
Figure 2.1 Drift velocity versus electric field in Silicon
3x107
InP
Drift Velocity, Vd (cm/s)
2x107
Si
1x107
GaAs
0 5 10 15 20
4
Electric Field E (10 V/cm)
Figure 2.2 Drift velocity versus electric field in for three different semiconductor
12
n (xl)
n (x)
n (x+l)
l
EC
EF
l
E EV
Metal
K+
Na+ Mobile ionic charge (Qm)
SiO2
Oxide trapped charge (Qot)
Fixed oxide charge (Qf)
SiOX
generation, by hot electron injection or high current passing into the SiO2. This has
become a more prominent problem as oxide thickness is scaled down.
Further down into the oxide layer at close range to the SiO2/Si interface, there
exist fixed oxide charges, Qf due to the abruptly incomplete oxidized silicon. The
presence of these charges affects the flat band voltage. As a charged scattering
center, it is responsible for the mobility degradation. Interface trapped charge, Qit is
represented by X at the SiO2/Si interface in Figure 2.16 and is caused by excess Si,
oxygen and impurities. Here, Qit have energy states in the forbidden energy gap of
the Si which is called the surface states. This arises from the dangling/incomplete
bonds as a result of a disruption of the crystal lattice as pictured in Figure 2.5.
Surface states act like a localized generation and recombination centers. They
captured electron from the conduction band or a hole from the valence band. The
electrons or holes trapped in this state are called interface trap charge.
O O
O Si O Si O
SiO2
O O Interfacial
trap
Si Si Si Si Si
Si
Si Si Si Si Si
Figure 2.5 Post oxidation dangling bonds that will become interfacial traps
15
There are varieties of definition models that can be used to measure and
predict the threshold voltage of a MOSFET. Old long channel threshold voltage
model need to be modified to give a more accurate value for nanoscale devices as
new physic is being discovered and new materials being used (Wang et al., 1971).
Presently, analytical models can adequately describe the threshold behaviour very
well both in definition and extraction method (Zhou et al., 1999). In this work, a
shortchannel threshold voltage model for short channel MOSFET is derived for n
channel MOSFET with n+ polysilicon gate and ptype silicon. For precision
formulation, short channel effect and narrow width effect is taken into consideration
(Yu et al., 1997).
(
VT = 2φ f + VFB + 2ε Si qN A 2φ f ) Cox (2.1)
The electron effective mobility due to the transverse field is modeled semiempirically
and calculated using Matthiessen's rule by incorporating the individual scatterings as
shown below.
−1
⎡ 1 1 1⎤
μeff =⎢ + + ⎥ (2.2)
⎢⎣ μ ph μ sr μc ⎥⎦
where μc is Coulombic scattering due to doping concentration, μph is phonon scattering and
μsr is surface roughness scattering.
This velocity saturation has a very significant implication upon the current
voltage characteristics of the short channel MOSFET. It reduces the saturation mode
current below the current value predicted by the conventional long channel equation
Simpler approximations for long channel MOS transistor are no longer valid as the
accuracy of a drain current model is directly affected by occurrence of velocity
saturation effect. The long channel numerator will be divided by velocity saturation
to get newly improved short channel drain current equation. Below are equation for
short and long channel current in the linear region for NMOS. The current in the
saturation region is a linear function of Vgt instead of Vgt2 as in the long channel.
μeff Cox W
I ds ( long channel ) = ⋅ ⋅ ⎡⎣ 2Vgt Vds − Vds 2 ⎤⎦ (2.3)
2 L
The saturation drain current in for long and short channel can be expressed as
μeff Cox W
⋅ (Vgs − VT )
2
I ds ( long channel ) = ⋅ (2.5)
2 L
μeff Cox W
I ds ( short channel ) = ⋅ ⋅ (Vgs − VT ) Vc (2.6)
2 L
where Vc is the critical voltage defined in Eq. (6.12), Vds is the drain voltage, Vgs is
gate voltage, W is the width and L is the length of the channel. In this research, a
newly developed unified oneregion currentvoltage (IV) compact model for linear
and saturation region is adopted (Zhou and Lim, 1997). The model is formulated on
the analysis of second order effects on the long channel model.
The accuracy of a drain current model is directly affected by how the velocity
saturation effect is implemented. The most commonly used carrier velocity model is
in Eq. (2.7) and Eq. (2.8) as shown below (Jeng, Ko and Hu, 1998).
μ eff E
, (E < Ec )
1 + ( E Ec ) (2.7)
v=
v sat , ( E ≥ Ec ) (2.8)
where νsat is the carrier saturation velocity and Ec is critical electric field for velocity
saturation defined by
vsat
Ec = (2.9)
μeff
20
The channel of the MOS transistor can be generally divided into two regions, a
gradual channel region and a velocity saturated region, as shown in Figure 2.6. In the
gradual channel region ν<νsat and E < Ec, while in the velocity saturation region, ν
=νsat and E ≥Ec (Takeuchi and Fukuma, 1994).
Source Drain
0 LC LEFF
Velocity saturation will yield an Idsat value smaller than that predicted by the
ideal relation, and it will yield a smaller Vdsat value than predicted. Figure 2.7 shows
a comparison of drain current versus drain to source voltage characteristic for
constant mobility and for field dependent mobility.
Constant
Mobility
Velocity
Saturation
Ids (mA)
Vds (V)
Figure 2.7 Comparison of IV characteristic for a constant mobility and for field
dependent mobility and velocity saturation effects
21
When current flow into the channel through the terminal contact, there is a
tiny voltage drop in the source and drain region. This is associated with the resistance
that appears in the device. This resistance has several components:
2ρ S υ
Rs / d = Rext + Rint = + (2.10)
x jW VGS − VT
where Rext is the extrinsic resistance, Rint is intrinsic resistance, xj is the junction
depth, S is the spacer thickness and ρ is taken as effective resistivity of the S/D
regions (including contacts). The component of the drain source resistance
expression will be discussed in Section 6.4.
22
The parasitic source and drain resistance of a NMOS is shown in Figure 2.8.
Inversion Layer
N+ RS RD N+
It was shown that the peak electric field, Emax in Figure 8.12 can attain high
value at low drain voltage for short channel device. When the carrier in velocity
saturation region gain adequate kinetic energy to generate electronhole pairs,
avalanche process occurs. Electrons from the conduction band gains energy as they
move down the channel. They possess high kinetic energy and travel at saturation
velocity. On impact with the lattice, they generate a secondary electron and holes by
breaking the bond, ionizing the valence electron from the valence band into the
conduction band. As of this moment, there are now three carriers; the original
electron and the electronhole pair. Subsequently, the newly generated pair that gains
enough energy will collide with the lattice to generate more electron hole pairs. This
phenomenon is referred to as impact ionization. The effect is more pronounced at
drain end where fields are highest. The generated electrons which are attracted to the
drain will cause a rise in drain current while the generated holes which flow through
23
the substrate to the body terminal will form substrate hole current. The potential
difference between substrate and source will create a forward bias near the source
terminal. All these effects are shown in Figure 2.9 below.
Vg
Vs = 0 V Vds


 
 
Avalanche
2
   Depletion region
Forward injection 
Substrate
3
Current
ptype Si substrate
Vb
Under this circumstances, electrons from the source inject themselves into the
substrate and a fraction of them will diffuse into the drain space charge region. This
triggers a positive feedback and increases the avalanche process. Another issue with
hot carrier effect that concern designer is when electron that has enough energy to
overcome the SiSiO2 interface barrier enter the oxide layer. The trapped electrons in
the oxide produce a net negative charge and contribute to the total oxide charge in
Eq. (4.13). The trapped oxide charge results in a positive shift in threshold voltage,
which in turn increases surface scattering, reduces mobility as well as drain current
and transconductance. Eventually, this will lead to the reduction of speed and cause
the circuit to fail the speed test specification. Since these processes are continuous,
device will degrade over a period of time and stability is at stake. Ultimately, the
lifespan of the device will decrease and breakdown may occur sooner than expected.
24
Narrow self aligned n region are placed between the channel and n+ source
drain diffusion as shown in Figure 2.10. Optimized n doses in LDD spreads the high
field at pinchoff along the n region and reduces the peak value of the longitudinal
electric field along the channel length. It also increases the breakdown voltage and
limit the impact ionization.
n n
n+ n+ n+  
n+
n n
p p
A close up view is shown in Figure 2.11. The gate is now extend from the
LDD which makes it the effective channel shorter than conventional MOSFET where
Loverlap is the length of the LDDgate overlap region. Leff is the length of silicon
surface region in which its conductivity is effectively controlled by the gate bias and
Lmet is the physical separation between the source channel junction and the drain
channel junction near silicon surface.
Lgate /2
Loverlap Lmet /2
gate electrode
spacer
n+ source x
y
LDD
p substrate
There are several different approaches for introducing strain into the Si
channel of nanoscale MOSFETs. Of these, two of the well known strained silicon
options are processinduced (uniaxial) strain and bulk wafer (biaxial) strain.
Recently, biaxial strainedSi has received substantial attention. In biaxial strained
silicon, the electronic band structure is modified by pulling the individual silicon
atoms moderately apart. As a result, higher currents in the transistor can be achieved
as electrons and holes can move faster in the layer. This can be in Appendix E where
mobility is higher for strained device compared to unstrained silicon and the
universal mobility curve by Takagi et al. (1994).
More attention has been paid to uniaxial strainedSi as it enables the amount
of strain for the ntype and ptype MOSFET can be controlled independently on the
same wafer. Furthermore, uniaxial stressed Si for PMOS demonstrates tremendous
hole mobility improvement at a given strained and mobility enhancement is present
at large vertical fields. The process flow consists of selective epitaxial SiGe in the
source/drain regions to create longitudinal uniaxial compressive strain in the PMOS
as illustrated in Figure 2.14. On the other hand, specially engineered high tensile Si
nitridecapping layer is used to introduce tensile uniaxial strain as shown in Figure
2.15 (Thompson et al., 2004). The technology is proven to be remarkable and has
increases saturated ntype and ptype MOSFET drive currents by 10 and 25%,
respectively. Since then, it has been implemented and ramped into high volume
27
Figure 2.13 TEM micrographs of 45nm ptype MOSFET (Thompson et al., 2004)
Figure 2.14 TEM micrographs of 45nm ntype MOSFET (Thompson et al., 2004)
short channel effect such as threshold voltage rolloff characteristics, DIBL and
punchthrough voltage and also electric field peak at drain end as illustrated in Figure
2.17.
Figure 2.15 DILDD device cross section (Codella and Ogura, 1985)
Figure 2.16 Surface electric field at drain edge for conventional and DILDD
devices from 2D device simulation, VSUB = 1V and L=0.6 µm (Ogura et al., 1982)
CHAPTER III
RESEARCH METHODOLOGY
Physical parameters or elements are extracted from the IV curve in order to
analyze the velocity saturation response. In this stage, schematic design of the
NMOS is carried out by using Intel Proprietary Schematic Editor. Circuit netlist is
then generated and the IV curve is displayed by running Intel Proprietary Circuit
Simulator. The numerical values of the extracted parameters are feed into the semi
empirical models.
Check Schematics
Netlist Schematics
Invoke Circuit
Simulator Circuit Simulator
Parameters Extraction
Proposed Models
Measure Results
Export to CSV
Parameters Extraction
a) Physical model
This model is based on device physics formulation and each parameter in the
model has a physical significance such as flat band voltage, doping
concentration and Fermi potential. The threshold voltage model discussed
here is a physical model.
In developing the models, several effects that occur in a given region of operation is
combined into one physical model. Several phenomena which simpler model ignore
is taken into account to derive a good model in term of accurate parameter extraction.
The NMOS transistors consist of three terminals: gate, drain, and source. The
source is biased at a lower potential (often 0V) than the drain. In this case, the source
and body are both grounded. The drain current is induced based on voltages applied
at the gate and drain of the transistor. Every NMOS transistor contains a threshold
voltage. The voltage applied to the gate terminal determines whether current can
flow between the source and drain terminals. In order for the transistor to operate, Vgs
must be greater than Vt. Once this condition has been met, the resulting drain current
34
can be controlled by the voltages supplied at the gate and the drain. The relationship
between Vgs, Vds, and Ids is described by three regions of operation; the cut off region,
the triode region and the saturation region. Figure 3.4 illustrates a schematic of an
NMOS transistor.
4.1 Introduction
2ε si qN A ( 2φ f )
VT = 2φ f + VFB + (4.1)
Cox
Eg
φms = χ ' − ( χ ' + + φ fp )
2e
E
= χ ' − χ ' − g − φ fp )
2e
⎛ Eg ⎞
= −⎜ + φ fp ⎟ (4.2)
⎝ 2e ⎠
where χ is the oxide electron affinity. φfp and φfn is the Fermi surface potential for p
type and ntype semiconductor substrate respectively. They are written as
kT ⎛ N A ⎞
φ fp (T ) = ln ⎜ ⎟ (4.3)
q ⎝ ni ⎠
kT ⎛ N D ⎞
φ fn (T ) = ln ⎜ ⎟ (4.4)
q ⎝ ni ⎠
1 ⎛ Eg ⎞
ni = ( N c N v ) 2 exp ⎜ − ⎟ (4.5)
⎝ 2kT ⎠
compared to the substrate, which make it negative. The magnitude of φms for
n+ polysilicon with p+ substrate decreases with doping as the Fermi level for the
substrate proceed to travel down further from the midgap.
αT 2
Eg (T ) = Eg (0) − (4.6)
(T + β )
where Eg (0) is the initial value of the band gap at 0 K while α and β are constant.
(Zeghbroeck, 2004). The band gap of a semiconductor is the energy difference
between the top of its valence band and the bottom of its conduction. The bandgap is
a forbidden energy range between the valence and conduction bands. In order to be
in the conduction band and taking part in conduction, electron in the valence band
must absorb sufficient energy to leap across the band gap. The fitting parameters for
germanium, silicon and gallium arsenide in listed in Table 4.1.
4.73 x 104T 2
E g (T ) = 1.17 − (eV) (4.7)
(T + 636)
39
The effective hole and electron masses used in the calculations are given by
mn =1.08 m0 (4.8)
and
m p = 0.81 m0 (4.9)
The parameter Nc in Eq. (4.5) is the effective density of states function in the
conduction band and can be defined as
( cm )
3
−3
N c ≅ 5.42 x1015 T 2
(4.10)
( cm )
3
−3
N v ≅ 3.52 x1015 T 2
(4.11)
Qtot
VFB = φms − (4.13)
Cox
where Qtot is effective net charges per unit area at the SiSiO2 (C/cm2) and is a sum
of fixed oxide charge, Qf and interface trap charge, Qit which is discussed is Section
2.4. Using Eq. (4.2) and Eq. (4.13), Eq. (4.1) can be written as
2ε si qN A ( 2φ f ) ⎛ Eg Qtot ⎞
VT = φ fp + −⎜ + ⎟ (4.14)
Cox ⎝ 2e Cox ⎠
40
Additional effects on VT occur as the device shrink in size. The short channel
threshold voltage shift reduce VT predicted by the long channel. The source and
drain distance becomes comparable to the MOS depletion width. The net charge in
the depletion region has to be considered since a portion of the charge is shared
among the gate, source and drain charge. The fraction of the charged induced by the
source and drain becomes significant as the channel length reduces. Therefore, the
chargesharing model (Yau, 1974) is utilized. This model assumes the charge
induced by gate voltage is contained in a region that can be best described by a
trapezoid, as shown in the Figure 4.2. The total charge contributing to the threshold
under the gate contact is represented by the rectangle with a width of xdT and a length
of L.
VG
VS VD
L
rj xdm
n+ n+
L’
p substrate
VB
Figure 4.2 Charge sharing in the short channel threshold voltage model
The bulk charge inside the trapezoid is controlled by the gate is given by
⎛ L+ L'⎞
Q 'B = qN A xdT ⎜ ⎟ (4.15)
⎝ 2 ⎠
41
1/ 2
⎛ 4ε siφ fp ⎞
xdT =⎜ ⎟ (4.16)
⎝ qN A ⎠
The threshold voltage shift due to short channel effects (Neaman, 2003) can be
expressed as
qN A xdT ⎡ rj 2x ⎤
ΔVT = − ⎢ 1 + dT − 1⎥ (4.17)
Cox ⎢⎣ L rj ⎥⎦
By taking Eq. (4.17) into account, the threshold voltage now can be approximated by
qN A xdT ⎧⎪ ⎡ r ⎛ 2 xdT ⎞ ⎤ ⎫⎪
VT = 2φ fp + VFB + ⎢ ⎟⎥ ⎬
j
⎨1 − ⎜ 1 + − 1 (4.18)
Cox ⎢ L ⎜ r ⎟⎥
⎩⎪ ⎣ ⎝ j ⎠ ⎦ ⎭⎪
where
VT ( Short Channel ) = VT ( Long Channel ) + ΔVT (4.19)
For wide widths, the size of this augmented charge at each end of the channel
width relative to the bulk charge is small and can be neglected. However, as the
width is reduced, this ratio increases and becomes significant. This additional charge
increases the bulk charge and causes VT to increase. As the width becomes smaller,
the shift in threshold voltage becomes larger.
42
The additional space charge due to narrow width effect is given by Neamen (2003)
and it is shown to be
qNxdT ⎡ ξ xdT ⎤
ΔVT = (4.20)
Cox ⎢⎣ W ⎥⎦
where W is the channel width while ξ is a fitting parameter for lateral space charge
width and normally given to be π/2 for a semicircle width. By adding this extra
charge into Eq. (4.18), the final threshold voltage expression can be approximated as
qN A xdT ⎧⎪ ⎡ r ⎛ 2 xdT ⎞⎤ ξ x ⎫⎪
VT = 2φ fp + VFB + ⎨1 − ⎢ ⎜⎜ 1 + − 1⎟ ⎥ + dT
j
⎬ (4.21)
Cox L rj ⎟⎥ W
⎩⎪ ⎢⎣ ⎝ ⎠⎦ ⎭⎪
SiO2 TTH
Tox
Si WTH WD
Actual Depletion
Boundary
Ideal Depletion
Boundary
Figure 4.3 Cross section of an NMOS showing the depletion region along the
width of the device
43
VT
VT
5.1 Introduction
2qZ Z
μs = = (5.3)
pm υth 3.2 x10−9 pTn1 2
*
⎛ NI ⎞ −1
p = 0.09Tn1.5 + 1.5 x10−8 ⎜ ⎟ Tn N f (5.4)
⎝ Z ⎠
Z = Z cl + Z QM (5.5)
3 2kT
Z cl = = 0.0388 Tn Eeff−1 (5.6)
qEeff
1
⎡ 9 ( h 2π )2 ⎤ 3
−1
Z QM =⎢ * ⎥ = 1.24 x10−5 Eeff 3 (5.7)
⎢⎣ 4m qEeff ⎥⎦
where p is the Fuchs factoring scattering which describe the probability of diffuse
scattering, Z is the averaged inversion layer width, Nf is the interface charge density,
Zcl is the classical channel width and ZQM is the quantum mechanically broadened
width due to the two dimensional quantization of the energy levels in the inversion
layer, h is the Planck's constant, m* is the electron effective mass and υth is thermal
velocity and q is electronic charge.
Figure 5.2 includes both scattering and show an excellent agreement with measured
data.
Figure 5.1 Comparison of calculated and measured μeff versus Eeff for several
channel doping levels without Coulomb scattering and surface roughness scattering
(Shin et al., 1991).
Figure 5.2 Comparison of calculated and measured μeff versus Eeff for several
channel doping levels with Coulomb scattering and surface roughness scattering
(Shin et al., 1991).
47
Coulomb Surface
MOBILITY (cm2/Vs)
Scattering Roughness
Low
Scattering
Phonon High
Scattering
Total Mobility
The universal curve can be divided into rising curve influenced by phonon
scattering term, the mid section governed by columbic scattering term and the roll off
contributed by the surface roughness term. The equations to calculate effective
mobility of electron in MOS (Shin et al., 1991) based on the three dominant
scattering are given below.
−1
⎛ 1 1 1 ⎞
μeff =⎜ + + ⎟
⎜ μ ph μ sr μc ⎟
(5.8)
⎝ ⎠
−1
⎡ ⎛ 2qZ ⎞ ⎤
−1
( )
−1
μ ph = ⎢ K BTnKT +⎜ ⎟ ⎥
⎝ pm υth ⎠ ⎥⎦
*
⎢⎣
−1 −1
⎡ ⎛ Z cl + Z QM ⎞ ⎤
( )
−1
= ⎢ 1400Tn −2.5 +⎜ −9 12 ⎟
⎥ (5.9)
⎢⎣ ⎝ 3.2 x10 pTn ⎠ ⎥⎦
48
−0.25
⎛N ⎞
p = 0.09T n
1.75
+ 4.53 x10 ⎜ I ⎟−8
Tn −1 N f (5.10)
⎝ Z ⎠
3 2kT
Z cl = = 0.0388 Tn Eeff−1 (5.11)
qEeff
−1 −1
Z QM = K QM Eeff 3 =1.73 x10−5 Eeff 3 (5.12)
K cTn1.5 1
μc =
γ 2
NA
ln (1 + γ 2 BH ) − BH
γ 2 BH + 1
1.1x10−21Tn1.5 1
=
γ 2
NA (5.14)
ln (1 + γ 2 BH ) − BH
γ 2 BH + 1
Kγ 2x1019 2
γ 2
BH = Tn = 2
Tn (5.15)
NI z NI z
T (K )
Tn = (5.16)
300
γ2BH is the Brooks Herring constant while KB, KQM, Ksr, Kc and Kγ are numerical
coefficients that provide best agreements with the experimental data. The total
number of electrons per unit area in the inversion layer, NI in Eq. (5.10) can be
calculated by using
2ε si
NI =
q
( Eeff − E0 ) (5.17)
49
1
Eeff = (η Qinv + QB ) (5.18)
ε si
where η is a fitting parameter. The best values are η = 1/2 for (100) electrons
(Sabnis and Clemens, 1979) and η = 1/3 for holes and (111) or (110) electrons
(Takagi et al., 1994). A set of three vector integers in parentheses describe the
crystal planes in a lattice while the vector component in brackets are used to
designate direction. The lattice point of the diamond structure is represented by a dot.
The three types of lattice planes along the a , b and c axis is shown in Figure 5.4,
Figure 5.5 and Figure 5.6.
[100]
a
Figure 5.4 A diamond structure with (100) lattice plane at [100] direction
50
[110]
a
Figure 5.5 A diamond structure with (110) lattice plane at [110] direction
[111]
Figure 5.6 A diamond structure with (111) lattice plane at [111] direction
Es + E0
Eeff = (5.19)
2
where Es is the transverse electric field at the gate dielectric silicon interface.
51
The transverse electric field at the edge of the inversion layer, E0 is given as
qN B QB qN A xdT
E0 = = =
ε si ε si ε si
1/ 2
qN A ⎛ 4ε siφ fp ⎞
= ⎜ ⎟
ε si ⎝ qN A ⎠
1/ 2
⎛ 4qN Aφ fp ⎞
=⎜ ⎟ (5.20)
⎝ ε si ⎠
Carrier transport primarily occurs in the surface on the inversion layer. The
induced transverse and longitudinal electric field influence the velocity of the carrier
toward and parallel to the siliconsilicon oxide interface respectively. The carrier
near the surface suffers collision with the silicon interface which resemble a zig zag
motion which is shown in Figure 5.7.
Gate
S D
Silicon Oxide
n+ n+
Depletion region
Mobility that is due to the various modes of lattice vibration including surface
acoustic phonons and optical phonons is called phonon scattering. Phonon scattering
is dominant in strong inversion where interaction between electrons and vibrating
lattice atom is frequent. It is dominant at high temperature and weak at low
temperature. Phonon scattering is also known as lattice scattering. KB and KT in
Eq. (5.9) is fitting parameter for bulk phonon scattering. KB=1400 and KT=2.5 and
found to have good agreement with measured data as described by Shin (1991).
6.1 Introduction
∂E y ∂Ex
(6.1)
∂y ∂x
Baccarani and Brews (1978) has make calculation simpler by avoiding numerical
analysis needed in PaoSah model and became one of the most widely adopted
model. Charged sheet approximation assumes that all the inversion charges are
located at the silicon surface like a sheet of charge and there is no potential drop and
no band bending across the inversion layer.
In this section, the charge sheet model is employed to derive the expression
for drain current in linear and saturation region. To gain insight into short channel
effects, velocity saturation coefficient is incorporated. The current flow in silicon is
driven by two mechanism; the drift of carriers and the diffusion of carrier. In this
section, the carrier concentration within the silicon is assumed to be uniform.
Therefore, diffusion current which is caused by an electron or hole concentration
gradient in silicon is omitted from the calculation.
− qE yτ
vd = (6.2)
m*
Drift velocity returns to zero after a collision event where velocity is randomized and
the whole process repeats all over again.
56
The IV derivation is shown below while a more detailed explanation can be seen
Appendix G. The mobility of the electron can be defined as
qτ ql
μ= *
= * (6.3)
m m vth
where the mean free path, l is
l = vthτ (6.4)
For ntype silicon with a free electron density n, drift current density Jn, under an
electric is given by
J n = qnvd (6.5)
μeff E y
vd = (6.6)
1 + E y Ec
where E is the longitudinal electric field while Ec is the critical electric field before
velocity saturation occurs. The total charge per unit area at a point y along the
inversion layer can be given as
Qs ( y ) = Cox ⎡⎣VGS − VT − V ( y ) ⎤⎦
= Cox [VGT − V ( y ) ] (6.7)
ε ox
Cox = (6.8)
tox
εox is dielectric constant of the oxide and tox is oxide thickness as shown in
Figure 6.1.
57
GATE
++++++++++++
xi Z

L
The total current at a point y along the inversion layer can be represented as
⎛ μeff E y ⎞ (6.9)
I ds = nv qvd A = nv q ⋅ ⎜
⎜ 1 + E y Ec ⎟⎟ ( zxi )
⎝ ⎠
where A is the area of the inversion width, xi as shown in Figure 6.1. Ids can also be
written as
By integrating from 0 to L the drain current for short channel device is given by
I ds =
(
Cox μeff z VGT .Vds − Vds2 2 ) (6.11)
L [ L + Vds LEc ]
vsat
VC = LEc = L (6.12)
μeff
Therefore, the equation given for short channel current in the linear region is
I ds = eff ox ⋅ ⋅ ⎣ (6.13)
2 L V
1 + ds
VC
58
A better approximation of the drain current in second order term in the power series
expansion would include a bodyeffect coefficient, m (Tsividis, 1999 and Zhou et al.,
1999) as shown below.
I ds = eff ox ⋅ ⋅ ⎣ (6.14)
2 L V
1 + ds
VC
Next is the derivation of short channel saturation voltage and current. Note that the
short channel current without bodyeffect coefficient in the linear region is used here
for an easier calculation. Idsat can written as
I dsat = ns qvsat W
= Cox (VGT − Vdsat ) vsat W (6.15)
Drain saturation current can also be approximated by letting V= Vdsat in Eq. (6.14)
Substituting Ids from Eq (6.15) into Eq. (6.16), one can obtain Vdsat in quadratic form
2
Vdsat − 2VGT VC + 2 VdsatVC = 0 (6.17)
From Eq. (6.15), when VGT >> Vc and Vc is small, Vdsat can be approximated by
2
Vdsat = 2VC (VGT − Vdsat ) (6.20)
Therefore, if one uses the Eq (6.18) for Vdsat and Eq (6.20) for V2dsat, the integration
in Eq. (6.15) for short channel saturation drain current can be carried out to yield
When drain source resistance, Rds is considered, Vgs and Vd in Eq (6.22) are replaced
as shown below
{ }
I dsat = Cox vsat W (VG − I dsat Rs ) − VT − m ⎡⎣Vdsat − I dsat ( RS + RD ) ⎤⎦ (6.23)
60
I dsat 0
I dsat = (6.24)
1 − Cox vsat W ⎡⎣( m − 1) RS + mRD ⎤⎦
2
aVdsat + bVdsat + c = 0 (6.25)
−b − b 2 − 4ac
Vdsat = (6.26)
2a
where
In order to have one drain current equation which cover both linear and saturation
region, a smoothing transition function is utilized.
1
Vdeff = Vdsat − ⎡Vdsat − Vds − δ s + (Vdsat − Vds − δ s ) + 4δ sVdsat ⎤
2
(6.30)
2 ⎢⎣ ⎥⎦
By incorporating Eq. (6.30), into Eq. (6.16), the unified one region equation is given
as
I ds 0 = ⋅ ⋅ (6.31)
2 L Vdeff
1+
VC
Ids0 denoted the condition for Rsd = 0, therefore when Rsd is calculated, the expression
becomes
I ds 0
I ds 0 = (6.32)
1 + I ds 0 Rsd Vdeff
where Rch is the resistance along the channel. Channel length modulation (CLM) is a
non ideal characteristic that present in short channel MOSFET. Therefore, the
effective early voltage, VAeff is included into the formulation. It is considered to be
positive and defined as
where ξ is a fitting parameter. With CLM effect, Eq. (6.31) can be rewritten as
⎛ V −V ⎞
I deff = ⎜1 + ds deff ⎟⎟ I ds 0 (6.34)
⎜ VAeff
⎝ ⎠
I deff
I ds = (6.35)
1 + ( Rsd I deff ) Vdeff
62
In reality, there are parasitic resistances associated with the source and drain
regions other than the channel resistance (Rch) as illustrated in Figure 6.2. These
source drain resistance should be taken into consideration in short channel modeling
as it causes a substantial drain current degradation besides contributing to the RC
delay.
Rs Rd
Rch
Vds
The model is based on the concept introduced by Zhou and Lim (2000). Rsd is the
sum of Rs and Rd when both resistance are equal in magnitude. It is also compose of
extrinsic (Rext) and intrinsic resistance (Rint)
where Rac and Rsp is accumulation and spreading resistance respectively. On the other
hand, the bias independent or extrinsic resistance (Rext) is given as
The extrinsic resistance Rext and intrinsic resistance Rint can be rewritten as
2ρ S
Rext = (6.39)
x jW
υ
Rint = (6.40)
VGS − VT
where ρ is average resistivity in the spacer region, S is the spacer thickness, xj is the
junction depth and υ is treated as a fixed fitting parameter in Ω  V unit. All of these
resistance component is illustrated in Figure 6.3.
Lwin S
GATE
Xj
Metallurgical
Junction
Rac/2
Rsh/2 Rsp/2
Rco/2
Figure 6.3 Current patterns in the source/drain region and its resistance
(Ng and Lynch, 1986)
CHAPTER VII
7.1 Introduction
Vg
Vs Vd
Gate
Source SiO2 LΔL L Drain
n+ n+
Depletion layer
ΔL
L′
ptype Si substrate
The two commonly used empirical velocity longitudinal field relationship models in
the inversion layer described by Trofinen (1965) and Caughey and Thomas (1967)
respectively as
μeff E y
vd = (7.1)
1 + ( E y Ec )
and
μeff E y
vd = 12
(7.2)
(
⎡1 + E E
) ⎤
2
⎢⎣ y c ⎥⎦
Ec is the critical electric field before the occurrence of velocity saturation defined by
vsat
Ec = (7.3)
μeff
Vd − IRsd
Ey = (7.4)
L
66
The accuracy of Eq. (2.7), Eq. (2.8), Eq. (7.1) and Eq (7.2) is depicted in
Figure 7.2. Electric field should be large enough than Ec in order for Eq. (7.1) to
approach νsat. Eq. (2.7) is able to fit the experimental data nicely in the linear region
than the complicated Eq. (7.1) while Eq. (7.2) fits the data quite accurately. The
simpler Eq (7.2) reaches saturation at a much later point than Eq (7.1).
1.0E+08
1x108
μ 0 = 710 cm 2 /Vsec E c = 2 .8x10 4 V/cm for Eq.( 2 .7 ) and Eq.( 2 .8 )
ν sat = 1x10 7 cm/sec E c = 1 .1x10 4 V/cm for Eq.( 7 .1) and Eq.( 7 .2 )
Velocity (cm/sec)
1x107
1.0E+07 Eq. (2.7) & Eq. (2.8) Eq. (7.1)
Eq. (7.2)
6
1x10
1.0E+06
Eq (2.7) & Eq (2.8)
1.0E+05
1x105
4
1x10
1.0E+04
1x102
1.0E+02 1x10 3
1.0E+03 1x10 4
1.0E+04 1x10
1.0E+05
5
1x10 6
1.0E+06
Electric Field (V/cm)
GATE
tox Ex (0,y)
(0,0) A D y
B C
x
ΔL
Pseudo 2 dimensional model includes the effect of gate field into the analysis and
comprises both depletion charge density, qNa and mobile charge density qNm. The
Poisson’s equation with field gradient in the x direction is now given by
∂ 2V ( x , y ) ∂ 2V ( x , y ) qN a ( x , y ) qN m ( x , y )
+ = +
∂x 2 ∂y 2 ε si ε si
∂Ex ( x ) ∂Ey ( y ) qN a qN m
+ = + (7.5)
∂x ∂y ε si ε si
It is assumed that the value of ∂Ex ∂x at each point can be represented by the
average value ∂Ex ∂x from x=0 to x=xj. The value Ex (xj,y) is assumed to be close to
zero while Ex at the SiSiO2 interface is denoted by Ex (0,y). The average value
∂Ex ∂x can be approximated by
Ex (0,y) can be rewritten as Esi (0,y). The field at the surface of the silicon is related
to the field in the oxide by the equation
ε ox
Esi ( 0 , y ) = E ( 0, y ) (7.7)
ε si ox
VGS − VFB − 2φ f − V ( y )
Eox ( 0 , y ) = (7.8)
tox
and
Qc
Eox ( y = 0 ) =
ε ox
⎛ qN + qN m ⎞
= xj ⎜ a ⎟ (7.11)
⎝ ε ox ⎠
Hence
Substituting the right hand side of Eq. (7.9) with Eq (7.12) yields
∂Ey ( y ) ⎛ ε ⎞⎛ 1 ⎞ ⎛ 1 ⎞
= ⎜ ox ⎟⎜ ⎟ ⎜
⎜ ⎟⎟ ⎡⎣V ( y ) − Vdsat ⎤⎦
∂y ⎝ ε si ⎠⎝ tox ⎠ ⎝ x j ⎠
⎡V ( y ) − Vdsat ⎤⎦
=⎣ (7.13)
l2
where l is the characteristic effective length of the VSR. Eq. (7.13) is a linear first
order differential equation which can be solved with boundary condition V(0) = Vdsat
and E(0) = Esat, The general solution of Eq. (7.13) is
⎡⎣V ( y ) − Vdsat ⎤⎦ y −y
2
= Ae l + Be l (7.14)
l
The coefficients in Eq. (7.14) are found to be A= lEsat/2 and B=lEsat/2. Thus, the
expression for V (y) and Ey (y) in the VSR is
⎡ ⎛ ⎞
2 ⎤
V − V V − V
ΔL = l ln ⎢ d dsat
+ ⎜ d dsat
⎟ + 1 ⎥ (7.17)
⎢ lEsat ⎝ lEsat ⎠ ⎥
⎣ ⎦
2
⎛ V − Vdsat ⎞
Emax = E y ( y = ΔL ) = ⎜ d ⎟ + Esat
2
(7.18)
⎝ lE sat ⎠
CHAPTER VIII
8.1 Introduction
The measured IV curve generated by Intel Proprietary Schematic Editor and
Intel Proprietary Circuit Simulator is shown as solid lines in Figure 8.1, Figure 8.2
and Figure 8.3 for gate voltage 0.7 V, 0.8 V, 0.9 V, 1.0 V, 1.1 V and 1.2 V. In order
71
to validate the short channel MOSFET developed for this work, the IV model
calculated in Section 6.2 is compared to those calculated by a compact IV model in
Section 6.3. Initially, the analytical short channel model from Eq. (6.10) and Eq.
(6.15) are used to calculate the drain current. However, the model is not able to
predict the drain voltage precisely beyond saturation drain current due to channel
length modulation. Furthermore, drain series resistance is not included in this model
which affects the degree of accuracy. Therefore, a unified MOSFET compact IV
model from cutoff to saturation has been utilized to fit the graph. In addition to that,
a physically based semi empirical series resistance model is also incorporated with
parasitic resistance, ρ of 3.5x105 Ω/cm, 4.5x105 Ω/cm and 5.5x105 Ω/cm. The
calculated curve shows an excellent agreement with the IV experimental data across
a wide range of gate voltage in Figure 8.1. The calculated results show that the
lower ρ in Figure 8.1 gives a fairly accurate prediction than Figure 8.2 and 8.3. The
reason for this is that drain current is inversely proportional to the source drain series
resistance. Lower Rsd will give a higher drain current and vice versa. Further analysis
show that there is a slight Ids inconsistency for Vg above 1.0 V from Figure 8.2 and
Figure 8.3 with Vds ranging from 0.8 V1.5 V.
1.2
Measured Data Calculated
Data
1.0 VGS = 1.2V
Normalized Drain Current
VGS = 1.1V
0.8
VGS = 1.0V
VGS = 0.8V
0.4
VGS = 0.7V
0.2
0.0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Drain Voltage (V)
Figure 8.1 Comparison of calculated (pattern) versus measured (solid lines) IV
characteristics for a wide range of gate voltage at resistivity 3.5x105 Ω/cm
72
1.2
3.5e5 Ω/cm 4.5e5 Ω/cm
1.0
VGS = 1.2V
Normalized Drain Current
VGS = 1.1V
0.8
VGS = 1.0V
VGS = 0.8V
0.4
VGS = 0.7V
0.2
0.0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Drain Voltage (V)
Figure 8.2 Comparison of calculated IV characteristics for a wide range of gate
voltage at resistivity 3.5x105 Ω/cm (solid lines) and 4.5x105 Ω/cm (pattern)
1.2
4.5e5 Ω/cm 5.5e5 Ω/cm
1.0
Normalized Drain Current
VGS = 1.2V
VGS = 1.0V
0.6
VGS = 0.9V
VGS = 0.7V
0.2
0.0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Drain Voltage (V)
Figure 8.3 Comparison of calculated IV characteristics for a wide range of gate
voltage at resistivity 4.5x105 Ω/cm (solid lines) and 5.5x105 Ω/cm (pattern)
73
The author also analyze the effect of Channel Length Modulation (CLM) has on the
IV curve. Notable differences can be found in Figure 8.4 where the saturation drain
current is predicted higher in the saturation region compared to the shaded lines
(without CLM). Since the channel length is modulated by the drain current when it is
in saturation, Idsat increases with increasing Vds. In other word, the deviation of the
drain current from its ideal IV curve is due to increased average electric field at
decreasing effective channel length. The velocity saturation extracted from these
figure is found to be satisfactory with the default velocity suggested by the process
technology file.
1.2
Without CLM With CLM
1.0
Normalized Drain Current
VGS = 1.2V
VGS = 1.0V
0.6
VGS = 0.9V
VGS = 0.8V
0.4
VGS = 0.7V
0.2
0.0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Drain Voltage (V)
Figure 8.4 Comparison of calculated IV characteristics for a wide range of gate
voltage at resistivity 3.5e5 Ω/cm with (pattern marking) and without channel length
modulation (solid lines)
74
Short channel effect also alter the threshold voltage characteristic of long
channel MOSFET. The combined effects of reduced gate length and gate width
produce a change in VT. Figure 8.5 show the long channel like threshold voltage
behaviour generated using Eq. (4.14). In the beginning, threshold voltage is negative
as device is lightly doped in which the positive oxide charge and work function
difference is overwhelming.
0.9
Threshold Voltage
(V) (Vth)
0.6
Voltage
Voltage
0.3
Threshold
0.0
0.3
16 17 18 19
1x10
1.E+16 1x10
1.E+17 1x10
1.E+18 1x10
1.E+19
3
Doping Concentration (cm )
Figure 8.5 Threshold Voltage without Short Channel Effect (SCE) and Narrow
Width Effect (NWE)
To get a good calculation, two short channel effects on the threshold voltage
of MOSFET namely the short channel voltage shift and narrow gate width effect.
Short channel effect decreases the threshold voltage due to the charge sharing under
gate oxide and can be plotted using Eq. (4.17). The threshold voltage shift decreases
dramatically at higher channel doping. When the channel length approaches the
junction depletion region width of source and drain, a greater portion of the channel
75
depletion region begins to overlap the space charge in the junction depletion regions.
As a result, less gate charge is needed to cause inversion in short channel MOSFET.
Hence, a smaller threshold voltage is needed to turn on a short channel device and
changes the ideal threshold voltage as shown in Figure 8.6. An additional effect that
also modifies the expected VT is the narrow width effect and is represented using
Eq. (4.20). Although, this effect is less critical than short channel effect as illustrated
in Figure 8.6, it causes a positive shift for threshold voltage. In Figure 8.7, the effect
of short channel and narrow width effects from becomes more pronounced as the
doping concentration goes beyond 1x1016 cm3. The final VT in Figure 8.7 is given
by Eq. (4.21).
3.0
Short Channel Effect
2.0 Narrow Width Effect
1.0
Voltage (V)
0.0
1.0
2.0
3.0
4.0
1x1014
1.E+14 1x10 15
1.E+15 1x1016
1.E+16 1x1017
1.E+17 1x10 18
1.E+18 1x10 19
1.E+19
3
Doping Concentration (cm )
0.6
0.0
Voltage
Voltage
Threshold
0.3
0.6
Threshold Voltage
0.9
1x1013
1.E+13 1x10 14
1.E+14 1x10 15
1.E+15 1x10
16
1.E+16 1x10
17
1.E+17 1x10 18
1.E+18 1x10 19
1.E+19
Doping Concentration (cm3)
1.2
15 3 3 TT
== 300K
300 K
NA Na
= 1x10 cm cm
= 1.0 E+15
1.0
Normalized Effective Mobility
NA = 1x1016 cm3
Na = 1.0 E+16 cm3
0.8
NA = 1x1017 cm3
0.6 Na = 1.0 E+17 cm3
NA = 1x1018 cm3
0.4 Na = 1.0 E+18cm3
0.2
0.0
1x104
1.00E+04 5
1.00E+05
1x10 1x106
1.00E+06 1x107
1.00E+07
Effective Transverse Electric Field (V/cm)
Although each of the individual mobility curves for the four doping
concentration in Figure 8.8 has different initial mobility, they formed a unique
universal mobility curve versus transverse electric field. Coulomb scattering
considerably degrades the mobility on higher impurity concentration as the deviation
from the universal curve becomes larger. It is caused by the Coulomb interaction
between the carrier in the inversion layer and the interface charges localized in SiO2.
When the doping concentration is low, the mobility is higher as Coulomb scattering
is lower. The mobility of the carriers begins to decrease gradually when
concentration of the dopants increases. Consequently, there are more carriers to
bump into and scattering becomes more frequent. Therefore, the Coulomb scattering
equation described in the mobility model includes both scattering caused by fixed
interface charge and doping impurities for better modeling. As the channel inversion
78
increases, the number of impurities and charge which are able to interact with the
carriers decreases. This can be ascribed to the carrier screening effect which is less
effective for a heavily inverted surface. The velocity saturation dependence on
doping concentration is depicted in Figure 8.9 and determined by using Eq. (7.2).
1.0
TT=300K
= 300 K
0.8
Normalized Drift Velocity
1.01x10
E+1515 cm3
3
1.0e15cm3
0.6
1.01x10
E+1616 cm3
3
1.0e16cm3
3
0.4
1.01x 1017cm
1.0e17cm3
E+17 cm3
1.01x10
E+1818 cm3
3
1.0e18cm3
0.2
0.0
1x103
1.0E+03 1x10
1.0E+04
4
1x10 5
1.0E+05 1x10 6
1.0E+06
Effective Longitudinal Electric Field (V/cm)
Figure 8.9 Normalized drift velocity versus longitudinal electric field at different
doping concentration
The drift velocity as a function of the longitudinal field for different doping
concentrations are essentially similar due to the domination of surface roughness
scattering at higher field. Surfaceroughness scattering within the inversion layer is a
function of the effective field independent of the doping concentration. When drift
velocity is plotted as a function of the longitudinal field for different doping
concentrations of 1015 cm3, 1016 cm3, 1017 cm3 and 1018 cm3 as shown in Figure
8.9, they are essentially similar due to the limitation of surface roughness scattering.
At first glance, doping concentration does not have a significant influence on drift
velocity at high field as they overlap each other. This is due to the fact that the
mobility for different doping concentrations is taken from the mobility curve in
79
Figure 8.8 at a fixed transverse field. In reality, the transverse field at a given gate
bias for different doping concentrations will be different due to the different VT at
different substrate doping concentration. For the same gate bias, the higher doped
substrate will experience a higher transverse field, and lower mobility at the high
fields experienced when the device is on. However, this also means that the critical
field will be higher for higher doped substrates and higher doped substrate will reach
saturated velocity later. The saturation field, Esat is chosen to be twice of the critical
field, 2Ec as it has been the range of vertical field in MOSFET device reported in the
literature.
1.2
70 K 70K
T = 70 K
Normalized Effective Mobility 1.0
300K
T = 300 K
0.8
400K
T = 400 K
0.6
450K
T = 450 K
0.4
0.2 300 K
400 K
450 K
0.0
1x104
1.0E+04 1x105
1.0E+05 1x10 6
1.0E+06 1x10 7
1.0E+07
Effective Transverse Electric Field (V/cm)
1.2
1.2 V
Gate Voltage = 1.1V
1.0
Normalized Drift Velocity
0.8 T77K
= 70 K
0.6 T = 300 K
300K
0.4
T = 400 K
400K
T = 450 K
430K
0.2
0.0
1x103
1.00E+03 1x104
1.00E+04 1x105
1.00E+05 1x10 6
1.00E+06 1x107
1.00E+07 1x108
1.00E+08
Effective Longitudinal Electric Field (V/cm)
Figure 8.11 Normalized drift velocity versus longitudinal electric field at different
temperature
81
Figure 8.12 illustrates the normalized longitudinal electric field along the channel
position for drain voltage of 1.2 V. The strength of the longitudinal electric field is
determined by the device VT, source and drain series resistance and L as expressed in
Eq. (7.4). Shorter channel length yield larger Ey and correspondingly higher velocity.
By using Eq. (7.16), the longitudinal electric field versus L is plotted. It has a linear
relationship with the channel up to Esat where Vdsat occurred. From this point
onward, the electric field grows exponentially to Emax near the drain end in the
velocity saturation region. Emax is calculated using Eq. (7.18). Under the influence of
saturation velocity, electron drift velocity becomes constant and independent of the
effective longitudinal field, Ey. In short channel devices, the saturation of drain
currents occur at a much lower voltage due to velocity saturation. The Idsat is
approximately linear with gate overdrive, instead of having a square law dependence
predicted in long channel device in Figure 8.13. The saturation drain current is
equally spaced voltage against drain voltage at different gate voltages as shown in
Figure 8.14. The value of Idsat is determined by using Eq. (6.26) and Eq. (6.33).
1.2
Vds = 1.2V
1.2 V Emax
Normalized Longitudinal Electric Field
1.0 Emax
0.8
0.6
0.4
Esat
0.2
0.0
0x100
0.0E+00 2x106
2.0E06 4x106
4.0E06 6x10 6
6.0E06 8x106
8.0E06 5
1.0E05
1x10
Channel Position y (m)
1.0
Normalized Saturation Drain Current
0.8
0.6
0.4
0.2
16
Doping Concentration: 11x10
E+16 cm3
0.0
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Gate Overdrive VGVT (V)
1.2
16 3
Doping Concentration: 11x10
E+16 cm3
cm
Vgs = 1.2 V
Normalized Saturation Drain Current
1.0
Vgs = 1.1 V
0.8
Vgs = 1.0 V
Vgs = 0.8 V
0.4
Vgs = 0.7 V
Vgs = 0.6 V
0.2
Vgs = 0.5 V
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6
Drain Voltage Vd (V)
Several newly developed models are modified and employed to analyze the
characteristics and behaviors of transistor in sub100 nm. They are the threshold
voltage model, physically based model for effective mobility and compact IV,
velocity field model and source drain resistance model. It is vital to investigate the
physical insight into the device’s operating principles at high field to diminish hot
carrier effect and avoid catastrophic breakdown of the device via punchthrough. The
abovementioned models are improvement upon existing long channel models and
include various effects discussed in previous chapters.
Intel Proprietary Schematic Editor and Circuit Simulator are used to generate
experimental data. The relevant parameters are then extracted from the IV curve.
Finally, the modified models are utilized to characterize the effects of velocity
saturation and effective mobility on drain voltage, gate voltage, temperature and
doping concentration. Simulated results show that the temperature effect on velocity
saturation depends on the predominant scattering mode. It is shown that at high fields
where surface roughness is predominant, the mobility has a negative temperature
coefficient and the velocity saturates at lower temperatures. Substrate doping
concentration changes the transverse field and scattering modes for a given gate bias,
and hence the saturation velocity is achieved at different longitudinal fields
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APPENDICES
93
APPENDIX A
PUBLICATION
Abstract – This paper reports the drift and submicron transistor designs such as velocity
velocity saturation dependence on saturation, short channel effect (SCE), channel
temperature, substrate doping concentration length modulation (CLM) and narrow width
and longitudinal electric field for nMOSFET. effect (NWE) is increasingly becoming a great
This study observes the velocity in response to concern for designers [2]. Velocity saturation
the variation of above input parameters. An deteriorates the drive strength in the saturation
existing currentvoltage (IV) compact model velocity region. SOE could be ignored in
is utilized and modified by appending a previous long channel CMOS generation as the
simplified threshold voltage derivation and a effects are not that significant. Nevertheless,
more precise carrier mobility model. The these undesirable effects are inevitable when
threshold voltage derivation provides similar devices are gradually scaled down to gain higher
accuracy when compared to actual devices speed, performance and chip density [3].
and comprises major short channel effect as Many research have been carried out [45] for
well as narrow width effect. The compact the development of semi empirical model for
model also includes a semi empirical source nanoscale MOSFET under the influence of
drain series resistance modeling. The models velocity saturation. More investigation has to be
show good agreement with the experimental done to examine the velocity saturation
data over a wide range of gate and drain bias. dependence on transverse electric field, substrate
doping concentration and temperature. This
I. INTRODUCTION analysis is crucial when taking into account
MOSFET scaling on device performance. In this
VELOCITY saturation occurs in high electric paper, the impact of velocity saturation, on the
fields when the drift velocity of electron in the parameters mentioned above is presented. The
inversion channel reaches a limiting value, at paper is organized as follows. We began with a
107 cm/s due to mobility degradation. Linear survey of studies on limitation of scaling of
velocity field relationship is applicable as long as MOSFET and effect of the velocity saturation
the electric field is low. Here, Ohm Law’s is still [6]. Section II provides further description of the
valid. Electrons in nanoelectronic devices are employed models. Firstly, a simple semi
being driven by a tremendously high electric empirical threshold voltage is derived for
field [1] and can go up to 106 V/cm. At high nanoscale MOSFET [7]. It is then incorporated
critical electric field, the average carrier energy with a modified semi empirical IV model by
and scattering rate of highly energetic electrons considering a more accurate description of
increases. Under these circumstances, the carrier mobility model [8]. Finally, a velocity field
loses their energy by opticalphonon emission model is used to analyze the carrier drift velocity
nearly as fast as they acquire from the field. This in the channel. Result are presented and
resulted in mobility degradation. Second order discussed in Section III. Section IV concludes
effects (SOE) in 50100nm generation of ultra the study.
95
A. The Threshold Voltage Model The outcome of this model will depend
primarily on the original mobility model
The threshold voltage, VT is one of the key developed by Schwarz and Russek described by
parameters in MOSFET design and modeling to [10] with some improvement on the scattering
predict the device performance. There are mechanism. The electron effective mobility due
various kinds of definitions and extraction to the vertical field [11] is modeled semi
methods proposed [9], each with a focus on empirically incorporating three basic scatterings
different aspects. This model formulation starts mechanisms in the inversion layer is namely,
with the modeling of threshold voltage for n Coulombic scattering due to doping
channel MOSFET with n+ polysilicon gate and concentration, phonon scattering and surface
ptype silicon substrate. The model assumes that roughness scattering as shown below
there is no substrate bias effect. The analytical
definition of the threshold voltage is ⎡ 1
−1
1 1⎤
μeff =⎢ + + ⎥ (5)
(
VT = 2φ f + VFB + 2ε Si qN A 2φ f ) Cox (1) ⎣⎢ μ ph μ sr μc ⎥⎦
where p is the Fuchs factor, z is the average and Ey is the longitudinal electric field. Ey is
inversion layer width including quantum channel given by
broadening effects. In the above Tn is the V − IRs / d
normalized temperature at 300K. The mobile Ey = d (16)
L
inversion layer charge density is given as
When E >> 2Ec, vd becomes μeffEc. Quasi two
Qinv = qN I = 2ε si ( E⊥eff + E0 ) (10) dimensional approach by Ko [18] is applied here
to model the velocity saturation region (VSR).
and depletion region charge density is
III. RESULTS AND DISCUSSION
QB = q ⋅ N A ⋅ xd = 2q ⋅ N A ⋅ε si ⋅ 2φF (11)
1.2
Gate Voltage = 1.1V
C. The IV model 1.0
I deff 0.0
I ds = (12)
1 + ( Rs / d I deff )V
1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08
Effective Longitudinal Electric Field (V/cm)
deff
Fig. 1 Normalized υd versus Ey for different
temperature as indicated.
where Vdeff is the smoothing function to replace
Vds for a smooth transition from linear to The saturation electron velocity, effective
saturation region while Ideff is the smoothing mobility, effective electric field corresponding to
function for Ids0iwith effective early voltage. A the gate voltage and drain voltage are
physicallybased source/drain (S/D) series summarized here. Under the influence of
resistance, Rs/d model for deep submicron saturation velocity, electron drift velocity
MOSFET is included comprising a bias becomes constant and independent of the
dependent (intrinsic) component and a bias effective longitudinal field, Ey. The saturation
independent (extrinsic) to give a precise reading field, Esat is chosen to be twice of the critical
[15]. The final S/D series resistance is given by field, 2Ec as it has been the range of vertical field
in MOSFET device reported in literature [17]. In
2ρ S υ short channel devices, the saturation of drain
Rs / d = Rext + Rint = + (13) currents occur at a much lower voltage due to
x jW VGS − VT
velocity saturation. It can be concluded that for a
higher vertical field, the effective mobility is
D. The VelocityField Model lower but the critical field becomes higher as
shown in (15).
The electron velocitylongitudinal field At low temperature at 77K, saturation velocity
relationship in the inversion layer given in [16] is substantially influence by surface roughness
is described as scattering. Devices at low temperature have a
higher drift velocity as a result of a high
μeff E y effective mobility as illustrated in Figure 2.
vd = 1n
(14)
⎡1 + ( E E )n ⎤ However, as temperature is increase to 300K and
⎢⎣ y c ⎥⎦ above, the extracted mobility show that
scattering mechanism transit to phonon
with n=2 for electrons, Ec is the critical electric scattering for moderately doped devices biased
field for velocity saturation defined by at moderate vertical field. The drift velocity
vsat curve for 300K, 400K and 430K appear lower
Ec = (15) compared to 77K as depicted in Figure 1 but
μeff
97
velocity saturation is achieved for all four channel, thus, making the velocity saturation
temperature at 1 x106 V/cm onwards. effects less pronounced. Nevertheless, the drive
1.2 current of the transistor still suffers from the
Na = 1.0 E+15 cm3 reduced transconductance.
1.0
Normalized Effective Mobility
0.8
Na = 1.0 E+16 cm3 1.2
0.8
0.4 Na = 1.0 E+18cm3
0.2 0.6
0.0 0.4
1.00E+04 1.00E+05 1.00E+06 1.00E+07
Esat
Effective Transverse Electric Field (V/cm) 0.2
APPENDIX B
ROADMAP OF SEMICONDUCTOR SINCE 1977
APPENDIX C
ROADMAP OF SEMICONDUCTOR INTO 32NM PROCESS
TECHNOLOGY
APPENDIX D
Schematic cross section of a planar PMOS and NMOS (Zeitzoff and Chung, 2005)
102
APPENDIX E
APPENDIX F
3
⎡ ⎤ 2 3
2π x 1.08 x 9.11 x 10 31
kg x1.38 x 10 23
J / K
≅ 2⎢ ⎥ T 2
⎢ ⎡⎣6.625 x 10 J ⋅ S ⎤⎦
34 2
⎥
⎣ ⎦
( cm )
3
−3
≅ 5.42 x1015 T 2
3
⎡ ⎤ 2 3
2π x 0.81 x 9.11 x 10 31
kg x1.38 x 10 23
J / K
≅2⎢ ⎥ T 2
⎢ ⎡⎣ 6.625 x 1034 J ⋅ S ⎤⎦
2
⎥
⎣ ⎦
( cm )
3
−3
≅ 3.52 x1015 T 2
104
Eq. (4.1) can expanded by using Eq. (4.2) and Eq. (4.13). It yield
2ε si qN A ( 2φ f )
VT = 2φ fp + VFB +
Cox
⎛ Q ⎞ 2ε si qN A ( 2φ f )
= 2φ fp + ⎜ φms − tot ⎟ +
⎝ Cox ⎠ Cox
⎛ Eg ⎞ Q 2ε si qN A ( 2φ f )
= 2φ fp − ⎜ + φ fp ⎟ − tot +
⎝ 2e ⎠ Cox Cox
2ε si qN A ( 2φ f ) ⎛E Q ⎞
= φ fp + − ⎜ g + tot ⎟
Cox ⎝ 2e Cox ⎠
2ε si qN A ( 2φ fp ) qN A xdT ⎡ rj ⎛ 2x ⎞ ⎤ qN x ⎛ ξ x ⎞
= 2φ fp + VFB + − ⎢ ⎜ 1 + dT − 1⎟ ⎥ + A dT dT
Cox Cox ⎜
⎢⎣ L ⎝ rj ⎟
⎠ ⎥⎦ Cox ⎝ W ⎟⎠
⎜
2ε si qN A ( 2φ fp ) qN A qNxdT ⎡ rj ⎛ 2x ⎞⎤
= 2φ fp + VFB + ⋅ ⋅ xdT − ⎢ ⎜ 1 + dT − 1⎟ ⎥
Cox 4ε siφ fp Cox ⎢⎣ L ⎜⎝ rj ⎟⎥
⎠⎦
qN A xdT ⎛ ξ xdT ⎞
+
Cox ⎜⎝ W ⎟⎠
qN A xdT qN A xdT ⎡ rj ⎛ 2x ⎞ ⎤ qN x ⎛ ξ x ⎞
= 2φ fp + VFB + − ⎢ ⎜ 1 + dT − 1⎟ ⎥ + A dT dT
⎜ W ⎟
Cox Cox L
⎢⎣ ⎝ ⎜ r ⎟ C ⎝ ⎠
j ⎠ ⎥⎦ ox
qN A xdT ⎧⎪ ⎡ r ⎛ 2 xdT ⎞ ⎛ ξ x ⎞ ⎤ ⎫⎪
= 2φ fp + VFB + ⎨1 − ⎢ ⎜⎜ − 1⎟ + ⎜ dT ⎟ ⎥ ⎬
j
1+
Cox ⎢L rj ⎟
⎩⎪ ⎣ ⎝ ⎠ ⎝ W ⎠ ⎦⎥ ⎭⎪
105
APPENDIX G
IV MODEL
The total current at a point y along the inversion layer can be represented as
⎛ μeff E y ⎞
I ds = nv qvd A = nv q ⋅ ⎜
⎜ 1 + E y Ec ⎟⎟ ( zxi )
⎝ ⎠
⎛ ∂V ∂y ⎞
= ( nv xi ) ⋅ qμeff z ⋅ ⎜
⎜ 1 + ( ∂V ∂y )(1 E ) ⎟⎟
⎝ c ⎠
⎛ ∂V ∂y ⎞
= ns q ⋅ μeff z ⋅ ⎜
⎜ 1 + ( ∂V ∂y )(1 E ) ⎟⎟
⎝ c ⎠
⎛ ∂V ∂y ⎞
= Cox ⎡⎣VGT − V ( y ) ⎤⎦ ⋅ μeff z ⋅ ⎜
⎜ 1 + ( ∂V ∂y )(1 E ) ⎟⎟
⎝ c ⎠
I ds L [ L + Vds LEc ] (
= Cox μeff z VGT .Vds − Vds2 2 )
Cox μeff z (V
GT .Vds − Vds2 2)
I ds =
L [ L + Vds LEc ]
106
Vdsat in quadratic form is obtained by substituting Ids from Eq (6.15) into Eq. (6.16).
μeff Cox W
⋅ ⋅ ( 2VGT Vdsat − Vdsat
2
) = Cox (VGT − Vdsat ) vsatW
2 L
vsat L ⎛ Vdsat ⎞
2 (VGT − Vdsat ) ⎜1 + ⎟ = 2VGT − Vdsat
2
μeff ⎝ Vc ⎠
2VGT VC − 2 VdsatVC + 2 VGT VC − 2 Vdsat
2
=0
2
Vdsat − 2 VGT VC + 2 VdsatVC = 0
Vdsat in Eq. (6.18) can be approximated when VGT >> Vc and Vc is small to be
⎛ V ⎞
Vdsat = VC ⎜ 1 + 2 GT − 1⎟
⎜ VC ⎟
⎝ ⎠
⎛ V ⎞
≈ VC ⎜ 2 GT ⎟
⎜ VC ⎟⎠
⎝
≈ 2VGT VC
2
Vdsat is obtained by rearranging Eq (6.17)
2
Vdsat − 2 VGT VC + 2 VdsatVC = 0
2
Vdsat = 2 VGT VC − 2 VdsatVC
2
Vdsat = 2VC (VGT − Vdsat )
I dsat = ns qvsat W
μeff
= Cox W (VGT − Vdsat ) Vc
L
μeff ⎛1 2 ⎞
= Cox W ⎜ Vdsat ⎟
L ⎝2 ⎠
μeff
= Cox W ( 2VGT VC )
2L
= Cox vsat W VGT
107
Vdeff
I ds 0 =
Rch + Rsd
Vdeff Rch
=
1 + Rsd Rch
I ds 0
=
1 + Rsd (Vdeff I ds 0 )
I ds 0
=
1 + I ds 0 Rsd Vdeff