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Copyright 2006 © Wayne Burleson

VLSI Design
ECE 558/658 (Fall 2006):
Lecture #1

Wayne Burleson
UMASS Amherst - ECE Department
Email: burleson@ecs.umass.edu

Copyright 2006 © Wayne Burleson


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Welcome

 Who am I?
 Who are you?

 Where are we?

 Why are we here?

 What's next?

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Copyright 2006 © Wayne Burleson
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Logistics

 Refer to print-out of Web-page.

http://www.ecs.umass.edu/ece/vspgroup/burleson/co
urses/558/

Copyright 2006 © Wayne Burleson


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Lecture
Outline
 Refer to Lecture 1 notes.

http://www.ecs.umass.edu/ece/vspgroup/burleson/co
urses/558/lecture1.html

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Copyright 2006 © Wayne Burleson
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Some Final Advice

 This is a demanding course


? lots of material
? lots of time needed for homeworks
? lots of time needed to learn and use CAD tools
 This is a broad course drawing on many previous courses
for both theory and design ideas.
 This is a true engineering design course.

 Advice: focus on learning and doing your best, and not on


the grades
? Hard/smart work always pays off!

Copyright 2006 © Wayne Burleson


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Questions?

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VLSI Design: Let's go!

VLSI = Very Large Scale Integration

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Design Abstraction Levels


SYSTEM

MODULE
+

GATE

CIRCUIT

Vin Vout

DEVICE
G
SD
n+ n+

Adapted from Irwin & Nayaranan's Slides from PSU. Copyright 2002 J. Rabaey et al."

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Transistor Twiddling & Rectangle


Pushing

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Issues & Trends in VLSI Design

 Exponential growth in integration complexity


? lots of transistors!
 Advances in semiconductor technology
? not just digital & analog - RF, optical, MEMS
 Relentless digitization of things around us
? computers getting embedded everywhere
 New user requirements
? portable, wireless, low-power

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Copyright 2006 © Wayne Burleson
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Moore's
Law
 By Gordon Moore, Intel's co-founder
# of transistors on a die
doubles every 1 to 2 years
 From 1958 to 1994
? F (feature size) : 1/50
? D2 (die area): x170
? PE (packing efficiency - # of transistors per minimum feature area): x100
? N = D2xPE/F2 = 50E6!
 No sign of slowing down!
? 2300 transistors, 1 MHz clock (Intel 4004) - 1971
? 16 Million transistors (Ultra Sparc III)
? 42 Million, 2 GHz clock (Intel P4) - 2001
? 140 Million transistor (HP PA-8500)
? "SoC" or System-on-chip

Copyright 2006 © Wayne Burleson


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Moore's Law Plot

109

108
107 integrated
# transistors

106 circuit
invented
105 memory
104 CPU
103
102
101
100
1960 1970 1980 1990 2000 2010 year

Modern VLSI Design 3e: Chapter 1 Copyright ♥ 1998, 2002 Prentice Hall PTR

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Copyright 2006 © Wayne Burleson
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Recent
Chips
 Intel Pentium 4  Sony Playstation II
? 42M transistors ? 128-bit CPU "Emotion Engine"
? 217 mm^2 die ? 0.18 micron process
? 0.18-micron process ? 300MHz, 6.2 GFLOPS, 3.2
2GHz clock Gbytes/second
?
• 10 floating point multiply-
 Intel/HP Itanium 646 accumulators and 4 floating point
dividers
? 220M transistors
• 3x floating point performance of
? 465 mm^2 die 500 MHz PIII
? 0.18-micron process ? Graphic synthesizer cgip
? 1.2GHz clock ? 0.25 micron chip
 Sparc III ? 42.7M transistors
? 90M transistors ? 16.8x16.8 mm^2 die
? 0.13-micron, 7-level metal copper ? 2560-bit datapath
process ? 48 Gbytes/sec memory bandwidth
? 64b, 1MB L2$ ? 75M polygons/sec, 2.4
Gpixels/sec
? 53W @ 1.3V, 1.1GHz

Copyright 2006 © Wayne Burleson


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The Old and the New

Intel 4004 Microprocessor Intel Pentium Microprocessor

[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

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Pentium 3 & Pentium 4

 28.1M transistors  42M transistors


 106 mm^2 die size  217 mm^2 die
 0.18 micron, 6-layer metal CMOS  0.18-micron process
 2GHz clock

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State-of-the Art: Lead


Microprocessors

Adapted from Irwin & Nayaranan's Slides from PSU. Copyright 2002 J. Rabaey et al."

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Moore's Law in Microprocessors


Transistors
Transistors on
on lead
lead microprocessors
microprocessors double
double every
every 22 years
years
1000

100
2X growth in 1.96 years!
Transistors (MT)

10
P6
Pentium® proc
1 486
386
0.1 286
8085 8086 Courtesy, Intel
0.01 8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year
Adapted from Irwin & Nayaranan's Slides from PSU. Copyright 2002 J. Rabaey et al."

Copyright 2006 © Wayne Burleson


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Evolution in DRAM Chip Capacity


human memory
human DNA
100000000
64,000,000

4X growth every 3 years! 16,000,000 0.07 ∝m


10000000
4,000,000
0.1 ∝m
1000000 1,000,000
0.13 ∝m
book 256,000 0.18-0.25 ∝m
Kbit capacity/chip

100000
64,000
0.35-0.4 ∝m
16,000
10000 0.5-0.6 ∝m
4,000 encyclopedia
0.7-0.8 ∝m
1000 1,000
2 hrs CD audio
1.0-1.2 ∝m 30 sec HDTV
256
1.6-2.4 ∝m
100
64
page
10
1980 1983 1986 1989 1992 1995 1998 2001 2004 2007 2010

Year
Adapted from Irwin & Nayaranan's Slides from PSU. Copyright 2002 J. Rabaey et al."

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Copyright 2006 © Wayne Burleson
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Die Size Growth


Die
Die size
size grows
grows by
by 14%
14% to
to satisfy
satisfy Moore's
Moore's Law
Law

100
Courtesy, Intel
Die size (mm)

P6
486 Pentium ® proc
10 386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years

1
1970 1980 1990 2000 2010
Year
Adapted from Irwin & Nayaranan's Slides from PSU. Copyright 2002 J. Rabaey et al."

Copyright 2006 © Wayne Burleson


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Clock Frequency
Lead
Lead microprocessors
microprocessors frequency
frequency doubles
doubles every
every 22 years
years
10000

1000 2X every 2 years


Frequency (Mhz)

P6
100
Pentium ® proc
486
10 8085 386
8086 286

1 8080
8008 Courtesy, Intel
4004
0.1
1970 1980 1990 2000 2010
Year

Adapted from Irwin & Nayaranan's Slides from PSU. Copyright 2002 J. Rabaey et al."

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Copyright 2006 © Wayne Burleson
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Power Dissipation
Lead
Lead Microprocessors
Microprocessors power
power continues
continues to
to increase
increase
100

P6
Pentium ® proc
Power (Watts)

10
486
8086 286
386
8085
1 8080
8008
4004
Courtesy, Intel
0.1
1971 1974 1978 1985 1992 2000
Year

Power
Power delivery
delivery and
and dissipation
dissipation will
will be
be prohibitive
prohibitive

Adapted from Irwin & Nayaranan's Slides from PSU. Copyright 2002 J. Rabaey et al."

Copyright 2006 © Wayne Burleson


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Power: A Major Problem


100000
18KW
5K
10000
W
1.5KW
Power (Watts)

1000 500W
Pentium® proc
100
286 486
10 8086 386
8085
8080
8008
1 4004

0.1 Courtesy, Intel


1971 1974 1978 1985 1992 2000 2004 2008
Year

Power
Power delivery
delivery and
and dissipation
dissipation will
will be
be prohibitive
prohibitive

Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

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Power Density
10000
Rocket
Nozzle
Power Density (W/cm2)

1000

Nuclear
100 Reactor

8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
286 486
8080 Courtesy, Intel
1
1970 1980 1990 2000 2010
Year

Power
Power density
density too
too high
high to
to keep
keep junctions
junctions at
at low
low temp
temp

Adapted from Irwin & Nayaranan's Slides from PSU. Copyright 2002 J. Rabaey et al."

Copyright 2006 © Wayne Burleson


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Sematech's International Technology


Roadmap for Semiconductors (ITRS)
(http://public.itrs.net)
 2001  2016
? 0.13 micron ? 0.022 micron
? 1.7GHz on chip clock ? 28.8 GHz on chip clock
? 7 wiring levels ? 10 wiring levels
? 480-1700 pins ? 1320-7100 pins
? Vdd=1.1-1.2V ? Vdd=0.4-0.9V
? 2.4W / 61W / 130W ? 3.0W / 158W / 288W
? DRAM: ? DRAM:
0.54 Gb/chip, 127 mm^2, 0.42 Gb/cm^2 68.72 Gb/chip, 238 mm^2, 28.85 Gb/cm^2
? MPU ? MPU
97 Mtrans/chip, 140 mm^2, 69 3092 Mtrans/chip, 140 mm^2, 2209
Mtrans/cm^2 Mtrans/cm^2
 2007
? 0.065 micron
? 6.7 GHz on chip clock
? 9 wiring levels
? 600-3000 pins
? Vdd=0.7-1.1V
? 3.5W / 104W / 190W
? DRAM:
4.29 Gb/chip, 183 mm^2, 2.35 Gb/cm^2
? MPU
386 Mtrans/chip, 140 mm^2, 276.1
Mtrans/cm^2

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Copyright 2006 © Wayne Burleson
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Why Scaling?
 Technology shrinks by ~0.7 per generation
 With every generation can integrate 2x more functions
on a chip; chip cost does not increase significantly
 Cost of a function decreases by 2x
 But ?
? How to design chips with more and more functions?
? Design engineering population does not double every two
years?
 Hence, a need for more efficient design methods
? Exploit different levels of abstraction

Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

Copyright 2006 © Wayne Burleson


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The Design Problem : Complexity
Outpaces Design Productivity

10,000 100,000
Logic Transistor per Chip(M)

10,000,000 100,000,000
1,000 Logic Tr./Chip 10,000
1,000,000 10,000,000
Tr./Staff Month.
(K) Trans./Staff -Mo.

100
100,000 1,000
1,000,000
Complexity

Productivity

10 58%/Yr. compounded 100


10,000 Complexity growth rate 100,000

1,0001 10
10,000
x x
0.1
100 1
1,000
xx
x
21%/Yr. compound
xx Productivity growth rate
x
0.01
10 0.1
100

0.001
1 0.01
10
1989
1991
1993

1997
1999
2001
2003
2005
1981
1983
1985
1987

1995

2007
2009

Source: Sematech

A growing gap between design complexity and design productivity

Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

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Throwing More Designers Not the Answer:


The Mythical Man-Month
 In theory, adding designers to team reduces project completion time
 In reality, productivity per designer decreases due to complexities of team
management and communication
 In the software community, known as "the mythical man-month" (Brooks 1975)
 At some point, can actually lengthen project completion time! ("Too many cooks")

 1M transistors, 1
designer=5000 Team
60000 16 15 16
trans/month 18
50000 19
 Each additional designer 40000 24 23
reduces for 100 30000
trans/month Months until completion
20000 43
 So 2 designers produce 10000 Individual
4900 trans/month each
0 10 20 30 40
Number of designers

[Adapted from Embedded Systems Design: A Unified Hardware/Software Introduction. Copyright 2000 Vahid & Givargis]

Copyright 2006 © Wayne Burleson


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Major Design Challenges


 Microscopic issues  Macroscopic issues
? ultra-high speeds ? time-to-market
? power dissipation and supply ? design complexity
rail drop (millions of gates)
? growing importance of ? high levels of
interconnect abstractions
? noise, crosstalk ? reuse and IP, portability
? reliability, manufacturability ? systems on a chip (SoC)
? clock distribution ? tool interoperability

Year Tech. Complexity Frequency 3 Yr. Design Staff Costs


Staff Size
1997 0.35 13 M Tr. 400 MHz 210 $90 M
1998 0.25 20 M Tr. 500 MHz 270 $120 M
1999 0.18 32 M Tr. 600 MHz 360 $160 M
2002 0.13 130 M Tr. 800 MHz 800 $360 M
Adapted from Irwin & Nayaranan's Slides from PSU. Copyright 2002 J. Rabaey et al."

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Copyright 2006 © Wayne Burleson
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Profound Impact on the way VLSI is


Designed

 The old way: manual transistor twiddling


? expert "layout designers"
? entire chip hand-crafted
? okay for small chips? but cannot design billion
transistor chips in this fashion
 The new way: using CAD tools at high level
? tools do the grunge work?
? high levels of abstractions
? synthesis from a description of the behavior
? libraries of reusable cores, modules, and cells
Chip design increasingly like object-oriented software design!

Copyright 2006 © Wayne Burleson


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Design with CAD Tools

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