Todays topics

Single BUS organization of processor Instruction execution –General idea… Register transfer… AL operations… Fetching a word from memory (to processor) Storing a word in memory (from processor)
1/16/11 BINOSHI SAMUVEL. lect. 11

A A+4

INSTRUCTION 1 A INSTRUCTION 2

Memory unit

MAR
PC

MDR

CONTRO L UNIT
READ WRITE

REG
IR

ALU
22

processor
1/16/11 BINOSHI SAMUVEL. lect.

CONTAINS MEM0RY ADDRESS OF THE NEXT CONTAINS ADDRESS INSTUCTION TO BE OF THE to the Transperent LOCATION TO EXECUTED BE ACCESSED programmer.. Use to hold value while doing some process CONTAINS DATA TO BE WRITTEN INTO OR READ OUT OF THE MEMORY LOCATION ARE general purpose reg. Programmer can consider..
1/16/11 BINOSHI SAMUVEL. lect.

Has 2 pins ..select 4and select
33

lect. .A A+4 INSTR 1 INSTR 1 A INSTR 2 MAR A PC A MDR CONTRO L UNIT READ WRITE REG IR ALU 44 1/16/11 BINOSHI SAMUVEL.

. lect.A A+4 INSTR 1 A INSTR 2 MAR A PC A MDR INSTR 1 CONTRO L UNIT READ WRITE REG IR ALU 55 1/16/11 BINOSHI SAMUVEL.

66 .A A+4 INSTR 1 A INSTR 2 MAR PC A+4 A MDR CONTRO L UNIT READ WRITE REG INSTR 1 IR result ALU 1/16/11 BINOSHI SAMUVEL. lect.

A A+4 INSTR 1 A INSTR 2 result MAR PC A+4 A MDR CONTRO L UNIT READ WRITE REG INSTR 1 IR ALU 77 1/16/11 BINOSHI SAMUVEL. . lect.

lect.Common steps… Transfer a word of data from one processor register to another or to the ALU Perform an arithmetic or a logic operation and store the result in a processor register Fetch the contents of a given memory location and load them into a processor register Store a word of data from a processor register into a given memory location 1/16/11 BINOSHI SAMUVEL. 88 .

lect. 1/16/11 BINOSHI SAMUVEL.REGISTER TRANSFERS two control signals are used to place the contents of that register on the bus or to load the data on the bus into the register. Ri and Ro All operations and data transfers within the processor take place within time periods defined by the processor clock. 99 .

reg2 R2 in 0 Reg .R1 in 0 65 Reg. lect.2 o R1 out o R2 out BINOSHI SAMUVEL. 1010 1/16/11 .1 Move reg1.

1 1 Reg .R1 in 0 R2 in R 1 out .2 1 R1 out o R2 out BINOSHI SAMUVEL. lect. R2 in 65 Reg. 1111 1/16/11 .

2 1/16/11 BINOSHI SAMUVEL. 1212 .1 0 65 1 R2 out 0 R1 out Reg . lect.R1 in 1 R2 in Reg.

Instruction execution cycles. REGISTER TRANSFER ----------. 1313 .DONE Perform an arithmetic or a logic operation and store the result in a processor register 1/16/11 BINOSHI SAMUVEL.. lect.

Yin R2 out . lect.select Y .PERFORMING AN ARITHMETIC 2 numbers.R3 in 1/16/11 BINOSHI SAMUVEL. 1414 .Zin Step3… Z out .Add . Step2… R1 out .. OR LOGIC Control signals for adding OPERATION Aim add [R1]+[R2]----->R3 Step1….

2 Y in R3 in 0 Reg .1 0 8 Y R1 in R1 out R2 in 0 0 0 MUX R2 out 2 0 Reg . 0 0 O 1515 .Reg. lect.3 R3 out Z in Z out 1/16/11 0 Z BINOSHI SAMUVEL.

2 1 Y in MUX R3 in 0 Reg . Yin 1616 . 0 0 O out R1 .3 R3 out Z in Z out 1/16/11 0 Z BINOSHI SAMUVEL.1 0 8 1 Y R1 in R1 out R2 in 0 R2 out 2 0 Reg . lect.Reg.

0 0 O 1717 .3 R3 out Z in Z out 1/16/11 0 Z BINOSHI SAMUVEL. lect.1 0 8 1 Y R1 in R1 out R2 in 0 R2 out 2 0 Reg .2 1 Y in MUX R3 in 0 Reg .Reg.

lect.select Y . 1818 . Yin R2 out .R3 in 1/16/11 BINOSHI SAMUVEL.Zin Step3… Z out .Add . Step2… R1 out .next Step1….

Zin R1 in R1 out R2 in 0 0 0 8 R2 out 2 1 Reg .2 0 Y in MUX R3 in 0 Reg .Add . 0 0 O 1919 . lect.R2 out .1 .3 R3 out Z in Z out Z 1/16/11 BINOSHI SAMUVEL.select Y Reg.

2 0 0 MUX R2 out Y in R3 in 0 Reg .R2 out . 0 0 O 2020 .1 .select Y Reg. lect.Add .3 1/16/11 0 1 1 R3 out Z out Z in Z BINOSHI SAMUVEL.Zin R1 in R1 out R2 in 0 0 0 Reg .

Add .Zin Z out .next Step1…. Step2… Step3… R1 out . 2121 .select Y .R3 in 1/16/11 BINOSHI SAMUVEL. lect. Yin R2 out .

lect.3 Z in 1/16/11 0 10 Z out BINOSHI SAMUVEL.1 Z out .R3 in R1 in R1 out R2 in 0 0 0 Reg .2 0 0 MUX R2 out Y in 1 R3 in Pr0cess completed R3 out Reg . 1 0 O 2222 .Reg.

Instruction execution cycles. lect. REGISTER TRANSFER ----------.DONE AL OPERATION__________DONE Fetching a word from memory 1/16/11 BINOSHI SAMUVEL. 2323 ..

2424 . 4. 5. lect. consider …Move The actions needed to execute this instruction are: 1.FETCHING A WORD FROM As an exa of a read operation.R2 1/16/11 BINOSHI SAMUVEL. MAR [RI] Start a Read operation on the memory bus Wait for the MFC response from the memory Load MDR from the memory bus R2 [MDR] MEMORY (RI ). 3. 2.

lect. MAR in . 0 R1 in 2525 BINOSHI SAMUVEL. Read External bus Internal b 1 MDR OUT E MAR. R1ou .R1 out. 0 1 0 MDR MDR OUT MDR in 0 MDR in E 0 1 1/16/11 REG.

0 1 0 MDR MDR OUT REA D MDR in 0 MDR in E 0 1 1/16/11 A 0 R1 in 2626 BINOSHI SAMUVEL. lect. R1ou . Read External bus Internal b 1 MDR OUT E MAR. MAR in .R1 out.

WMFC External bus Internal b 1 MDR OUT E A. 0 o MDR OUT 0 MDR REA D MDR in conten t WMF C 1/16/11 1 MDR in E 0 o A 0 R1 in 2727 BINOSHI SAMUVEL. lect.MDRin E. R1ou .

lect.MDR out. R2 in External bus Internal b 1 MDR OUT E A. 1 o MDR OUT 0 content MDR 0 MDR in E Pr0cess MDR in completed 0 1 Reg 2 o 1/16/11 A 0 R1 in 2828 BINOSHI SAMUVEL. R1ou .

Timing diagram 1/16/11 BINOSHI SAMUVEL. 2929 . lect.

3030 ..Instruction execution cycles.DONE AL OPERATION__________DONE Fetching a word from memory----done Storing a word in memory 1/16/11 BINOSHI SAMUVEL. lect. REGISTER TRANSFER ----------.

R2 out.. MAR in 2. 3131 . WMFC 1/16/11 BINOSHI SAMUVEL. lect. 1. MDR in. WRITE 3…MDR out E.Storing a word in memory Move R2.R1 out..(R1) C signals…….

MAR in External bus Internal b 1 MDR OUT E MAR. 0 1 0 MDR MDR OUT REA D MDR in 0 MDR in E 0 0 5 1 1/16/11 B A 0 R1 in 3232 BINOSHI SAMUVEL.R1 out. R1ou . lect.

lect.R2 out. MDR in. WRITE External bus Internal b 1 MDR OUT E MAR 0 o 0 5 MDR MDR OUT writ e MDR in 0 MDR in E 1 1 5 o 1/16/11 B 0 R1 in 3333 BINOSHI SAMUVEL. R1ou .

lect. R1ou . WMFC External bus Internal b 1 MDR OUT E MAR.MDR out E. 1 o 1 B MDR OUT 5 MDR WM FC 1/16/11 0 MDR in E Pr0cess complete in MDR d 0 o B 1 Reg 2 0 R1 in 3434 BINOSHI SAMUVEL.

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