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Code No: 3220403 Set No.

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II B.Tech II Semester Regular Examinations, April/May 2009
SWITCHING THEORY AND LOGIC DESIGN
(Electronics & Communication Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. (a) List the first 20 numbers in base17. Use the letters A, B, C, D, E, F and G
to represent the last seven digits. [4]
(b) Convert the following numbers with the given radix to decimal. [4 × 3 = 12]
i. 12345
ii. 12347
iii. 123411
iv. 3334

2. (a) Simplify the following Boolean expressions. [8]


i. A’C’+ABC+AC’ to three literals
ii. (x’y’+z)’+z+xy+wz to three literals
iii. A’B(D’+C’D)+B(A+A’CD) to one literal
iv. (A’+C)(A’+C’)(A+B+C’D) to four literals
(b) Obtain the complement of the following Boolean expressions. [8]
i. B’C’D+(B+C+D)’+B’C’D’E
ii. AB+(AC)’+(AB+C)
iii. A’B’C’+ABC’+AB’C’+ABC’
iv. AB+(AC)’+AB’C

3. (a) Reduce the following function


Q using K- map and implement it in AOI logic as
well as NOR logic F= M (0, 1, 2, 3, 4, 7) [10]
(b) What do you mean by K-map? Name its advantages and disadvantages [6]

4. Implement the BCD to Seven segment Display Decoder, Showing the truth table,
K-map simplification and Realization using Logic Gates. [16]

5. (a) List the PLA programming table for the BCD to excess-3 code converter.
(b) A ROM chip of 4,096 × 8 bits has two clip select inputs and operates from
a 5-volt power supply. How many pins are needed for the integrated circuit
package? Draw the block diagram of this ROM. [8+8]

6. (a) Compare synchronous & Asynchronous circuits


(b) Design a Mod-6 synchronous counter using J-K flip flops. [6+10]

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Code No: 3220403 Set No. 1
7. A clocked sequential circuit is provided with a single input x and single output Z.
Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the
sequence it produce an output Z = 1 and overlapping is also allowed.

(a) Obtain State - Diagram.


(b) Also obtain state - Table.
(c) Find equivalence classes using partition method & design the circuit using D
- flip-flops. [4+4+8]

8. (a) Draw the ASM chart for the following state transistion, start from the initial
state T1 , then if xy=00 go to T2 , if xy=01 go to T3 , if xy=10 go to T1 , other
wise go to T3 .
(b) Show the exit paths in an ASM block for all binary combinations of control
variables x, y and z, starting from an initial state. [8+8]

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Code No: 3220403 Set No. 2
II B.Tech II Semester Regular Examinations, April/May 2009
SWITCHING THEORY AND LOGIC DESIGN
(Electronics & Communication Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. A 12-bit Hamming code word containing 8-bits of data and 4 parity bits is read from
memory. What was the original 8-bit data word that was written in to memory if
12-bit words read out is as follows? [4 × 4 = 16]

(a) 001111101010
(b) 101110010110
(c) 101110110100
(d) 110011010111

2. (a) Simplify the following Boolean expressions to minimum no. of literals. [8]
i. x’y’+xy+x’y
ii. xy’+y’z’+x’z’
iii. x’+xy+xz’+xy’z’
iv. (x + y)(x + y’)
(b) Obtain the complement of the following Boolean expressions. [8]
i. AB+A(B+C)+B’(B+D)
ii. A+B+A’B’C
iii. A’B+A’BC’+A’BCD+A’BC’D’E
iv. ABEF+ABE’F’+A’B’EF

3. (a) For the truth table given below , find the minimal expression for the out put
(Y) using K-map [8+8]

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Code No: 3220403 Set No. 2
Inputs Output(Y)
A B C D
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0
(b) Expand A + B C̄ + AB D̄ + ABCD to minterms and maxterms.
4. (a) A combinational circuit is defined by the following three functions F1 = x̄ȳ +
xyz̄ F2 =x̄ + y F3 =xy + x̄ȳ Design the circuit with a decoder and external
gates.
(b) List the applications of Multiplexer and Demultiplexer. [12+4]
5. Write a brief note on:
(a) Architecture of PLDs
(b) Capabilation and the limitations of threshold gates. [8+8]
6. Design a 4 bit universal shift register which can be used as a parallel in- parallel
out register, serial in serial out register, serial in - parallel out and parallel in serial
out register with a shift option to wards left or right. Explain each of the behavior
with timing waveform. [16]
7. A clocked sequential circuit is provided with a single input x and single output Z.
Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the
sequence it produce an output Z = 1 and overlapping is also allowed.
(a) Obtain State - Diagram.
(b) Also obtain state - Table.
(c) Find equivalence classes using partition method & design the circuit using D
- flip-flops. [4+4+8]
8. (a) Draw the ASM chart for the following state transistion, start from the initial
state T1 , then if xy=00 go to T2 , if xy=01 go to T3 , if xy=10 go to T1 , other
wise go to T3 .

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Code No: 3220403 Set No. 2
(b) Show the exit paths in an ASM block for all binary combinations of control
variables x, y and z, starting from an initial state. [8+8]

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Code No: 3220403 Set No. 3
II B.Tech II Semester Regular Examinations, April/May 2009
SWITCHING THEORY AND LOGIC DESIGN
(Electronics & Communication Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) List the first 20 numbers in base17. Use the letters A, B, C, D, E, F and G
to represent the last seven digits. [4]
(b) Convert the following numbers with the given radix to decimal. [4 × 3 = 12]
i. 12345
ii. 12347
iii. 123411
iv. 3334

2. (a) Reduce the following Boolean expressions. [8]


i. (AB’+AC’)(BC+BC’)(ABC)
ii. AB’C+A’BC+ABC
iii. (ABC)’(A+B+C)’
iv. A+B’C(A+(B’C)’)
(b) Obtain the Dual of the following Boolean expressions. [8]
i. ABC+A’B+ABC’
ii. (BC’+A’D)(AB’+CD’)
iii. x’yz+xz
iv. xy+x(wz+wz’)

3. (a) Plot the K map for the Boolean expression. Y = (A + B + C + D̄)(A + B̄ +


C̄ + D)(A + B + C̄ + D̄)
(Ā + B̄ + C + D̄)(Ā + B̄ + C̄ + D) [6]
(b) Reduce the following function
P using K- map and implement it in AOI logic as
well as NAND logic. F= m(0, 1, 2, 3, 5, 7, 8, 9, 10, 12, 13) [10]

4. Implement
P the following Boolean function by a Hazard free OR-AND Network.
f = m(0, 2, 6, 7) and explain in detail what are the Hazards encountered in
implementing the above function. [16]

5. Write a brief note on:

(a) Architecture of PLDs


(b) Capabilation and the limitations of threshold gates. [8+8]

6. (a) Explain the operation of 5 - stage twisted ring counter with circuit diagram
State transition diagram & state table

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Code No: 3220403 Set No. 3
(b) Find a ring code for a module - 5 shift counter using D-flip flops. Explain
with the waveforms. [8+8]

7. A clocked sequential circuit is defined by the following state - table:

(a) Using implication table Obtain equivalence classes.


(b) Design the circuit using D - Flip-Flops. [8+8]

P.S N.S Z
x=0 x=1 x=0 x=1
0 0 4 1 0
1 0 4 0 0
2 1 5 0 0
3 1 5 0 0
4 2 6 0 1
5 2 6 0 1
6 3 7 0 1
7 3 7 0 1

8. (a) Draw the ASM chart for the following state transistion, start from the initial
state T1 , then if xy=00 go to T2 , if xy=01 go to T3 , if xy=10 go to T1 , other
wise go to T3 .
(b) Show the exit paths in an ASM block for all binary combinations of control
variables x, y and z, starting from an initial state. [8+8]

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Code No: 3220403 Set No. 4
II B.Tech II Semester Regular Examinations, April/May 2009
SWITCHING THEORY AND LOGIC DESIGN
(Electronics & Communication Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Generate Hamming code for the given 11 bit message 10001110101 and rewrite
the entire message with Hamming code. [8]
(b) The binary numbers listed have a sign bit in the left most position and, if neg-
ative numbers are in 2’s complement form. Perform the arithmetic operations
indicated and verify the answers. [4 × 2 = 8]
i. 101011 + 111000
ii. 001110 + 110010
iii. 111001 - 001010
iv. 101011 - 100110

2. (a) Simplify the following Boolean expressions. [8]


i. A’C’+ABC+AC’ to three literals
ii. (x’y’+z)’+z+xy+wz to three literals
iii. A’B(D’+C’D)+B(A+A’CD) to one literal
iv. (A’+C)(A’+C’)(A+B+C’D) to four literals
(b) Obtain the complement of the following Boolean expressions. [8]
i. B’C’D+(B+C+D)’+B’C’D’E
ii. AB+(AC)’+(AB+C)
iii. A’B’C’+ABC’+AB’C’+ABC’
iv. AB+(AC)’+AB’C

3. Reduce the following functions using K-map techniques


Q
(a) M (4, 5, 6, 7, 8, 12, 13).d(1, 15)
P
(b) m(1, 4, 8, 10, 11, 20, 22, 24, 25, 26) + d(0, 12, 16, 17). [8+8]

4. (a) Design a Excess-3 adder using 4-bit parallel binary adder and logic gates.
(b) Draw the logic diagram of a single bit comparator. [12+6]

5. (a) Specify the size of a ROM (number of words and numbers bits per word) that
will accommodate the truth table of a BCD to seven segment decoder with an
enable input.
(b) Write a brief note on programmable logic devices. [8+8]

6. (a) Compare synchronous & Asynchronous circuits

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Code No: 3220403 Set No. 4
(b) Design a Mod-6 synchronous counter using J-K flip flops. [6+10]

7. A clocked sequential circuit is provided with a single input x and single output Z.
Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the
sequence it produce an output Z = 1 and overlapping is also allowed.

(a) Obtain State - Diagram.


(b) Also obtain state - Table.
(c) Find equivalence classes using partition method & design the circuit using D
- flip-flops. [4+4+8]

8. (a) Draw the ASM chart for the following state transistion, start from the initial
state T1 , then if xy=00 go to T2 , if xy=01 go to T3 , if xy=10 go to T1 , other
wise go to T3 .
(b) Show the exit paths in an ASM block for all binary combinations of control
variables x, y and z, starting from an initial state. [8+8]

⋆⋆⋆⋆⋆

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