Service Manual U8110

Model : U8110

P/N : MMBD0032201

Date: May, 2004 / Issue 1.0

Table Of Contents
1. INTRODUCTION .............................. 6
1.1 Purpose................................................... 6 1.2 Regulatory Information............................ 6 1.3 Abbreviations .......................................... 8 3.2.3 Camera & Camera FPC Interface... 40 3.2.4 Camera Position Detection ............. 42 3.2.5 Camera Regulator .......................... 42 3.2.6 Display & LCD FPC Interface ......... 43 3.2.7 Main LCD Backlight Illumination ..... 46 3.2.8 Sub LCD Backlight Illumination ...... 47 3.2.9 Keypad Illumination ........................ 48 2.1 System Overview .................................. 10 2.2 Usable environment .............................. 11 2.3 Radio Performance ............................... 11 2.4 Current Consumption............................ 17 2.5 RSSI...................................................... 17 2.6 Battery Bar ............................................ 17 2.7 Sound Pressure Level........................... 18 2.8 Charging ............................................... 19 3.2.10 Camera Flash Illumination ............ 49 3.3 LCD Module .......................................... 50 3.4 Analog Baseband (ABB) Processor...... 51 3.4.1 Overview of Audio path................... 51 3.4.2 Audio Signal Processing & Interface .......................................... 52 3.4.3 Audio Mode..................................... 54 3.4.4 Voice Call........................................ 55 3.4.5 MIDI (Ring Tone Play) .................... 59

2. PERFORMANCE............................ 10

3. Technical Brief .............................. 20
3.1 Digital Baseband(DBB)& Multimedia Processor ........................... 20 3.1.1 General Description ........................ 20 3.1.2 Hardware Architecture .................... 21 3.1.3 External memory interface .............. 25 3.1.4 RF Interface .................................... 26 3.1.5 SIM Interface .................................. 28 3.1.6 UART Interface ............................... 28 3.1.7 GPIO (General Purpose Input/Output) map ................................................. 29 3.1.8 USB ................................................ 31 3.1.9 IrDA Interface.................................. 33 3.1.10 Folder ON/OFF Operation ............ 34 3.1.11 Power On Sequence..................... 35 3.1.12 Key Pad ........................................ 36 3.2 GAM Hardware Subsystem .................. 37 3.2.1 General Description ........................ 37 3.2.2 Block Description ............................ 38

3.4.6 MP3 (Audio Player)......................... 60 3.4.7 Video Telephony ............................. 61 3.4.8 Audio Main Component .................. 62 3.4.9 GPADC(General Purpose ADC) and AUTOADC2 .................................... 64 3.4.10 Charger control ............................. 65 3.4.11 Fuel Gauge ................................... 66 3.4.12 Battery Temperature Measurement ................................ 67 3.4.13 Charging Part................................ 68 3.5 Voltage Regulation ............................... 71 3.5.1 Internal Regulation.......................... 71 3.5.2 External Regulation ........................ 71 3.6 General Description .............................. 73 3.7 GSM Mode............................................ 75 3.7.1 Receiver.......................................... 75 3.7.2 Transmitter...................................... 80 3.8 WCDMA Mode ...................................... 82 3.8.1 Receiver.......................................... 82

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Table Of Contents

3.8.2 Transmitter...................................... 85 3.8.3 Frequency Generation .................... 89

4.20.1 Checking ..................................... 152 4.20.2 Checking Ant. SW module .......... 152 4.20.3 Checking Control Signal ............. 152

4. TROUBLE SHOOTING .................. 91
4.1 Power ON Trouble ................................ 91 4.2 USB Trouble ......................................... 93 4.3 SIM Detect Trouble ............................... 94 4.4 Keypad Trouble..................................... 95 4.5 Camera Trouble .................................... 96 4.6 Main LCD Trouble................................. 98 4.7 Sub LCD Trouble .................................. 99 4.8 Keypad Backlight Trouble ................... 100 4.9 Folder ON/OFF Trouble ...................... 102 4.10 Camera Detection Trouble................ 104 4.11 Camera Flash Trouble ...................... 106 4.12 Audio Trouble Shooting .................... 108 4.13 Charger Trouble Shooting................. 123 4.14 RF Component.................................. 126 4.15 Procedure to check ........................... 128 4.16 Checking Common Power Source Block.......................... 129 4.16.1 Step 1 ......................................... 130 4.16.2 Step 2 ......................................... 131 4.16.3 Step 3 ......................................... 132 4.16.4 Step 4 ......................................... 133 4.16.5 Checking Regular Part................ 136 4.17 Checking VCXO Block ...................... 137 4.18 Checking Ant. SW Module Block ...... 142 4.19 Checking Antenna Switch Block input logic.......................................... 143 4.19.1 Mode Logic by TP Command ..... 143 4.19.2 Checking Switch Block power source .............................. 145 4.20 Checking WCDMA Block .................. 151

4.20.4 Checking RF TX Level ................ 155 4.20.5 Checking PAM Block .................. 158 4.20.6 Checking RX I,Q ......................... 162 4.20.7 Checking RX Level ..................... 164 4.21 Checking GSM Block ........................ 166 4.21.1 Checking Regulator Circuit ........ 167 4.21.2 Checking VCXO Block ............... 167 4.21.3 Checking Ant. SW Module .......... 167 4.21.4 Checking Control Signal ............. 168 4.21.5 Checking RF Tx Path.................. 170 4.21.6 Checking RF Rx Path ................. 175

5. BLOCK DIAGRAM ....................... 180
5.1 GSM & WCDMA RF Block.................. 180 5.2 Interface Diagram ............................... 182 5.3 Detailed Interface Signal..................... 184

6. DISASSEMBLY INSTRUCTION... 186 7. DOWNLOAD ................................ 194 8. CALIBRATION ............................. 207
8.1 General Description ............................ 207 8.2 XCALMON Environment ..................... 207 8.2.1 H/W Environment.......................... 207 8.2.2 S/W Environment .......................... 207 8.2.3 Configuration Diagram of Calibration Environment................ 207 8.3 Calibration Explanation ....................... 208 8.3.1 Overview ....................................... 208 8.3.2 Calibration Items ........................... 208 8.3.3 EGSM 900 Calibration Items ........ 209

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Table Of Contents

8.3.4 DCS 1800 Calibration Items ......... 214 8.3.5 WCDMA Calibration Items ............ 217 8.3.6 Baseband Calibration Item ........... 225 8.4 Program Operation ............................. 226 8.4.1 XCALMON Program Overview ..... 226 8.4.2 XCALMON Icon Description ......... 227 8.4.3 Calibration Procedure ................... 230 8.4.4 Calibration Result Message .......... 232

9. CIRCUIT DIAGRAM ..................... 235 10. PCB LAYOUT ............................. 244 11. EXPLODED VIEW & REPLACEMENT PART LIST ..... 248
11.1 EXPLODED VIEW ............................ 248 11.2 Replacement Parts <Mechanic component>.................... 249 <Main component> ........................... 252 11.3 Accessory ......................................... 271

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1. INTRODUCTION

1. INTRODUCTION
1.1 Purpose
This manual provides the information necessary to repair, calibration, description and download the features of this model.

1.2 Regulatory Information
A. Security
Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example, persons other than your company’s employees, agents, subcontractors, or person working on your company’s behalf) can result in substantial additional charges for your telecommunications services. System users are responsible for the security of own system. There are may be risks of toll fraud associated with your telecommunications system. System users are responsible for programming and configuring the equipment to prevent unauthorized use. The manufacturer does not warrant that this product is immune from the above case but will prevent unauthorized use of common-carrier telecommunication service of facilities accessed through or connected to it. The manufacturer will not be responsible for any charges that result from such unauthorized use.

B. Incidence of Harm
If a telephone company determines that the equipment provided to customer is faulty and possibly causing harm or interruption in service to the telephone network, it should disconnect telephone service until repair can be done. A telephone company may temporarily disconnect service as long as repair is not done.

C. Changes in Service
A local telephone company may make changes in its communications facilities or procedure. If these changes could reasonably be expected to affect the use of the phones or compatibility with the network, the telephone company is required to give advanced written notice to the user, allowing the user to take appropriate steps to maintain telephone service.

D. Maintenance Limitations
Maintenance limitations on the phones must be performed only by the manufacturer or its authorized agent. The user may not make any changes and/or repairs expect as specifically noted in this manual. Therefore, note that unauthorized alternations or repair may affect the regulatory status of the system and may void any remaining warranty.

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Interference and Attenuation A phone may interfere with sensitive laboratory equipment. Electrostatic Sensitive Devices ATTENTION Boards. which contain Electrostatic Sensitive Device (ESD). use the protective package as described. your actual hardware may look slightly different. F. • Keep sensitive parts in these protective packages until these are used. Pictures The pictures in this manual are for illustrative purposes only. etc. medical equipment.1. • Service personnel should ground themselves by using a wrist strap when exchange system boards. G. In accordance with these agencies. are indicated by the Following information is ESD handling: sign. INTRODUCTION E. • When repairs are made to a system board. • Use a suitable. H. they should spread the floor with anti-static mat which is also grounded. -7- . you may be required to provide information such as the following to the end user. • When returning system boards or parts like EEPROM to the factory. Notice of Radiated Emissions This model complies with rules regarding radiation and radio frequency emission as defined by local regulatory agencies. grounded soldering iron. Interference from unsuppressed engines or electric motors may cause problems.

3 Abbreviations For the purposes of this manual. following abbreviations apply: APC BB BER CC-CV CLA DAC DCS dBm DSP DTC EEPROM EL ESD FPCB GMSK GPIB GPRS GSM IPUI IF LCD LDO LED OPLL PAM PCB PGA PLL Automatic Power Control Baseband Bit Error Ratio Constant Current – Constant Voltage Cigar Lighter Adapter Digital to Analog Converter Digital Communication System dB relative to 1 milliwatt Digital Signal Processing DeskTop Charger Electrical Erasable Programmable Read-Only Memory Electroluminescence Electrostatic Discharge Flexible Printed Circuit Board Gaussian Minimum Shift Keying General Purpose Interface Bus General Packet Radio Service Global System for Mobile Communications International Portable User Identity Intermediate Frequency Liquid Crystal Display Low Drop Output Light Emitting Diode Offset Phase Locked Loop Power Amplifier Module Printed Circuit Board Programmable Gain Amplifier Phase Locked Loop -8- .1. INTRODUCTION 1.

INTRODUCTION PSTN RF RLR RMS RTC SAW SIM SLR SRAM UMTS Public Switched Telephone Network Radio Frequency Receiving Loudness Rating Root Mean Square Real Time Clock Surface Acoustic Wave Subscriber Identity Module Sending Loudness Rating Static Random Access Memory Universal Mobile Telephony System -9- .1.

DRX=1.Dual Mode Handset 49.1 System Overview Item Shape Size Weight Power Talk Time Over 180 Min (GSM.0V > 1200mAh Li-Ion Over 140 Min (WCDMA.2.0V/1. Tx=Max. Paging period=9) Antenna LCD Main LCD BL Sub LCD BL Vibrator LED Indicator C-MIC Receiver Earphone Jack SIM Socket Volume Key Voice Key I/O Connect Fixed Type (Fixed Screw) 176 x 220 Pixel White LED Back Light 7-color LED Yes (Coin Type) 7-color(Sub LCD BL) Yes Yes Yes Yes (3. PERFORMANCE 2. Tx=12 dBm.-) Push Type (Memo) 24 Pin Specification GSM900/1 800 & WCDMA Folder. Voice) Over 120 hrs (WCDMA.7 x 22.8V) Push Type(+. PERFORMANCE 2.5 mm 120g (with Battery) 4. Voice) .5 x 95.10 - .28) Standby Time Over 1 50 hrs (GSM.

11 - .75GHz -50dBm -56dBm -50dBm 1G ~ 1.2.75GHz Conducted 1 Spurious Emission Idle Mode 1G ~ 1. Available power Min 100 Typ.785G ~ 12.3 Radio Performance 1) Transmitter -GSM Mode No Item GSM 9k ~ 1GHz 100k ~ 1GHz MS allocated Channel 1G ~ 12. PERFORMANCE 2.71G ~ 1. 4.75GHz -50dBm -56dBm -50dBm 100k ~ 880MHz 880M ~ 915MHz 915M ~ 1000Mz -60dBm -62dBm -60dBm -33dBm 1785M ~ 12. 3.71GHz 1.2) -20 ~ + 60 -30 ~ + 85 max.785GHz 1.71GHz 1. 85 Unit V °C °C % 2) Environment(Accessory) Item Power * CLA: 12~24V(DC) Spec. (Shut Down: 3.785G ~ 12.2 Usable environment 1) Environment Item Voltage Size Storage Humidity Spec.71G ~ 1.75GHz 100k ~ 880MHz 880M ~ 915MHz 915M ~ 1000MHz -33dBm -60dBm -62dBm -60dBm -39dBm 1G ~ 1710MHz 1710M ~ 1785MHz -33dBm -39dBm DCS -39dBm .4 (Min).785GHz 1. 220 Max 240 Unit Vac 2.0 (Typ).

2.5: ±200Hz 0 ~ 100kHz 200kHz 250kHz 400kHz 600 ~ 1800kHz +0.71G ~ 1. PERFORMANCE No Item 30M ~ 1GHz MS allocated Channel 1G ~ 4GHz Radiated GSM 30M ~ 1GHz -36dBm DCS -36dBm -30dBm -36dBm -30dBm -57dBm -59dBm -57dBm -47dBm -53dBm -47dBm 1G ~ 1710MHz 1710M ~ 1785MHz -30dBm 1785M ~ 4GHz 30M ~ 880MHz 880M ~ 915MHz 915M ~ 1000Mz -57dBm -59dBm -57dBm -47dBm -53dBm -47dBm 30M ~ 880MHz 880M ~ 915MHz 915M ~ 1000MHz 1G ~ 1.785GHz 1.71GHz 1.1ppm ±5(RMS) ±20(PEAK) 1 Spurious Emission Idle Mode 1G ~ 1.71GHz 1.12 - .785G ~ 4GHz 2 3 Frequency Error Phase Error ±20(PEAK) ±0.5dB -30dB -33dB -60dB -66dB RA250: ±250Hz HT100: ±250Hz TU50: ±150Hz TU1.71G ~ 1.1ppm ±5(RMS) 3dB below reference sensitivity 3dB below reference sensitivity Frequency Error Under 4 Multipath and Interference Condition RA250: ±200Hz HT100: ±100Hz TU50: ±100Hz TU3: ±150Hz 0 ~ 100kHz 200kHz 250kHz Due to modulation Output RF 5 Spectrum 3000 ~ 6000kHz ≥6000kHz 400kHz Due to 600kHz Switching 1200kHz transient 1800kHz -24dB 1800kHz -27dB -21dB 1200kHz -24dB -21dB 600kHz -24dB -71dB -77dB -19dB 400kHz -22dB ≥6000kHz -73dB 1800 ~ 3000kHz -69dB 1800 ~ 6000kHz -60dB 400kHz 600 ~ 1800kHz +0.785GHz 1.5dB -30dB -31dB -33dB -60dB .785G ~ 4GHz ±0.

2. PERFORMANCE No Item GSM DCS Frequency offset 800kHz Intermodulation product should 7 Intermodulation attenuation – be Less than 55dB below the level of Wanted signal Power control Power Tolerance Power control Power Tolerance Level 5 6 7 8 9 10 8 Transmitter Output Power 11 12 13 14 15 16 17 18 19 (dBm) 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 (dB) ±3 ±3 ±3 ±3 ±3 ±3 ±3 ±3 ±3 ±3 ±3 ±5 ±5 ±5 ±5 Level 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 9 Burst timing Mask IN (dBm) 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 Mask IN (dB) ±3 ±3 ±3 ±3 ±3 ±3 ±3 ±3 ±3 ±4 ±4 ±4 ±4 ±4 ±5 ±5 .13 - .

5 -0. 1M .5/4.84MHz) Qin/Qout:DPCCH quality levels 6 Out-of-synchronization handling of output power Toff@DPCCH/lor:-22->-28dB Ton@DPCCH/lor:-24->-18dB 7 8 Transmit OFF Power Transmit ON/OFF Time Mask -56dBm(3.5MHz. CPCH.5 -1/-3 -1.5 -0.5 2dB +1/3 3dB +1. 1M 12 Spectrum emission Mask -39-10*(∆f-7.5)dBc@∆f=3.5~3.5~8.5/1. PERFORMANCE 2) Transmitter-WCDMA Mode No 1 2 3 Item Maximum Output Power Class4: +21dBm(±2dB) Frequency Error Open Loop Power control in uplink ±0.5MHz.5 group(10equal command group) +1 5 Minimum Output Power +8/+12 +16/+24 -50dBm(3.5/-4.5MHz.5 Specification Class3: +24dBm(+1/-3dB) -0. ±12dB@extreme Adjust output(TPC command) cmd +1 4 Inner Loop Power control in uplink 0 -1 1dB +0.5/+0. 30k -35-1*(∆f-3.5 -0.5MHz.5/+0.5)dBc@∆f=2. uplink compressed mode ±25us power varies according to the data rate 9 Change of TFC DTX: DPCH off (minimize interference between UE) 10 11 Power setting in uplink compressed Occupied Bandwidth(OBW) ±3dB(after 14slots transmission gap) 5MHz(99%) -35-15*(∆f-2.2.84M) ±25us PRACH.5/+0.1ppm ±9dB@normal.5)dBc@∆f=7.5/-1. 1M -49 dBc@∆f=8.5~12.14 - .5~7.

TUhigh/FH) 3 Adjacent Channel Rejection 200kHz 400kHz C/Ia1=-12dB C/Ia2=-44dB Wanted Signal: -98dBm 4 Intermodulation Rejection 1’st interferer: -44dBm 2’st interferer: -45dBm Blocking Response 5 (TCH/FS Class II. 300k -67dBm*@925~935MHz. 1k BW -36dBm@f=150KHz~30MHz. 100k -31dBc@5MHz. 100k -79dBm*@935~960MHz. 100k -71dBm*@1805~1880MHz. 768kbps. Interferer -40dBc 15 Transmit Intermodulation -41dBc@10MHz.15 - . multi-code 17 Transmit OFF Power transmission 3)Receiver . ACP>-50dBm -36dBm@f=9~150KHz. ACP>-50dBm 43dB@10MHz. PERFORMANCE No 13 Item Adjacent Channel Leakage Ratio(ACLR) Specification 33dB@5MHz.5% (>-20dBm) 16 Error Vector Magnitude(EVM) (@12. RBER) Unwanted Signal: Depend on freq. RBER.6MHz.75GHz. Interferer -40dBc 17. Unwanted Signal: Depend on freq. 10k -36dBm@f=30~1000MHz.2. 100k Spurious Emissions 14 *: additional requirement -30dBm@f=1~12.GSM Mode No 1 2 (TCH/FS Class II.2k. 1M -41dBm*@1893.5~1919. Wanted Signal: -101dBm C/Ia1=-12dB C/Ia2=-44dB Wanted Signal: -96dBm 1’st interferer: -44dBm 2’st interferer: -44dBm Wanted Signal: -101dBm Item Sensitivity (TCH/FS Class II) Co-Channel Rejection C/Ic=7dB C/Ic=7dB GSM -105dBm DCS -105dBm . 1DPDCH+1DPCCH) -15dB@SF=4.

84MHz@10MHz 21 In-band Blocking UE@+20dBm output power(class3) -44dBm/3.7dBm(3. 1M -60dBm@f=1920~1980MHz.84M) -25dBm(3. PERFORMANCE 4) Receiver . 3.84MHz) 19 Maximum Input Level -44dBm/3.84MHz@f=1~2025 & 2255~12500MHz.84MHz . 100k BW 25 Spurious Emissions -47dBm@f=1~12. band a) UE@+20dBm output power(class3) -15dBm/3. 3.84MHz -60dBm@f=2110~2170MHz.16 - .84MHz(DPCH_Ec) UE@+20dBm output power(class3) 33dB 20 Adjacent Channel Selectivity(ACS) UE@+20dBm output power(class3) -56dBm/3.2. band a) UE@+20dBm output power(class3) -30dBm/3.84MHz@15MHz UE@+20dBm output power(class3) -44dBm/3.75GHz.84MHz@20MHz UE@+20dBm output power(class3) -57dBm@f=9KHz~1GHz.WCDMA Mode No 18 Item Reference Sensivitivity Level Specification -106.84MHz@f=2050~2095 & 2185~2230MHz.84MHz@f=2025~2050 & 22 Out-band Blocking 2230~2255MHz. band a) UE@+20dBm output power(class3) -44dBm CW 23 Spurious Response UE@+20dBm output power(class3) -46dBm CW@10MHz & 24 Intermodulation Characteristic -46dBm/3.

46 ±0.50 ±0.20 ±0. warning message 3.03V(Standby: 3min.28) GSM 150Hours=8mA (paging=9period) Voice Call 140Min=514mA (Tx=12dBm) 180Min=400mA (Tx=Max) VT 100Min=720mA (Tx=12dBm) 2.03V ↓ (else) Voltage 3.10 ±0.4 Current Consumption (VT test : Speaker off.03V 3. LCD backlight On) Stand by WCDMA 120Hours=10mA (DRX=1.17 - .50 ±0.5 RSSI TBD GSM BAR 4 → 3 BAR 3 → 2 BAR 2 → 1 BAR 1 → 0 -91 ±2dBm -96 ±2dBm -101 ±2dBm -106 ±2dBm WCDMA(TBD) 2.87 ±0. Inverval) -3% Power OFF 3.03V ↓ (WCDMA Talk) 3. PERFORMANCE 2.6 Battery Bar Indication BAR 4 → 3 (68%) BAR 3 → 2 (47%) BAR 2 → 1 (26%) BAR 1 → Icon Blinking (5%) Low voltage.72 ±0.2.03V 3. interval) -5% .03V 3.03V(Talk: 1min.03V 3.77 ±0.

2.Acoustic(Max Vol.18 - .GSM: Power Level: 5 MS DCS: Power Level: 0 (Cell Power: -90 ~ -105dBm) –.3 refer to TABLE 30. PERFORMANCE 2. HEAD SET MS NOM MAX NOM MAX NOM MAX NOM MAX Specification 8±3dB -1±3dB -13±1dB 17dB over 40dB over refer to TABLE 30.4 NOM -64dBm0p under MAX NOM -47dBPA under MAX -36dBPA under NOM 8±3dB MAX NOM -1±3dB MAX -12±3dB NOM 25dB over MAX NOM 40dB over MAX refer to TABLE 30.) MS/HEADSET SLR: 8±3dB Headset MS/HEADSET RLR: -13±1dB/-15dB (SLR/RLR: mid-Value Setting) GSM DCS GSM DCS SEND REV.7 Sound Pressure Level No 1 2 3 4 5 6 7 8 A C O U S T I C 9 10 11 12 13 14 15 16 Test Item Sending Loudness Rating (SLR) Receiving Loudness Rating (RLR) Side Tone Masking Rating (STMR) Echo Loss (EL) Sending Distortion (SD) Receiving Distortion (RD) Idle Noise-Sending (INS) Idle Noise-Receiving (INR) Sending Loudness Rating (SLR) Receiving Loudness Rating (RLR) Side Tone Masking Rating (STMR) Echo Loss (EL) Sending Distortion (SD) Receiving Distortion (RD) Idle Noise-Sending (INS) Idle Noise-Receiving (INR) TDMA NOISE –. SEND REV.3 refer to TABLE 30. SEND REV.4 NOM -55dBm0p under MAX NOM -45dBPA under MAX -40dBPA under 17 -62dBm under . SEND REV.

9V in all power level WCDMA: It will not be kept 3.8 Charging • Normal mode: Complete Voltage: 4.19 - .9V (GSM: It should be kept 3.2. PERFORMANCE 2.7V in all power level WCDMA: It will not be kept 3.2V Charging Current: 600mA • Await mode: In case of During a Call.7V in some power level) .9V in some power level) Extend await mode: At Charging prohibited temperature(-20C under or 60C over) (GSM: It should be kept 3. should be kept 3.

32 kB Instruction Cache.Dedicated API channel to DSP memory (not locked up to other DMA channels) • UMTS Access .Tone Generator Interface .1 Digital Baseband(DBB) & Multimedia Processor 3. 32 kWord SARAM . Technical Brief 3. 32 kWord DARAM.Multislot Class 8 .Camera Data and Programmable Display Interfaces .RTC . EDB (RS232)) .GSM AMR .External Memory Interface that supports FLASH.Support for WCDMA/GSM Dual Mode .IrDA ® (SIR) .Enhanced graphics support for QCIF display • Operation and Services .WCDMA Ciphering and Integrity . 16 kB Data Cache.3.4 kb/s • MMI .12 by 12 mm 289 pin FPBGA Production Package .Slave USB • Package .8 channel DMAC • DSP C55x (LEAD3) Megastar (MGS3_2.7 channel DMAC .SIM Interfaces .High Speed Serial Link (HSSL) to the WCDMA Modem (at Layer 1) .GSM/GPRS network signaling (from Layer 1 to 3) .General Purpose I/O (GPIO) Interface .HSCSD 14.I2C™ Interface . TECHNICAL BRIEF 3.0B) running at 170 MHz .JTAG . SRAM and PSRAM .UARTs (ACB.144 kWord ROM. Features • CPU ARM946 running at 104 MHz .20 - .ETM (in Prototype Package) • Data Communication .1 General Description A.1. 128 kB Instruction TCM and 128 kB Data TCM .Keypad Interface .

Figure. TECHNICAL BRIEF 3.21 - .2 Hardware Architecture The hardware structure is delivered as five separate hardware macros to the top-level design. Simplified Block Diagram . also depicted in Figure.3.1.

the CPU AHB and the DMA AHB. The reset lines are all asynchronously asserted low and synchronously negated high. The bus architecture is built on the ARM AMBA standard with multi-layer AHB (Advanced High-speed Bus) and APB (Advanced Peripheral Bus) for the peripheral buses.22 - . Block Diagram Figure. Simplified Block Diagram B. TECHNICAL BRIEF A.3. . AHB system. The CPU subsystem has separate clocking and reset for the ARM946. There are two AHB busses. Clocks to the CPU subsystem are distributed from the system control (SYSCON) backplane clocking. EMIF and DMAC. CPU Hardware Subsystem The CPU subsystem incorporates: • CPU Sub chip • Backplane • JTAG • DMA Controller • System Buffer RAM • Boot ROM • External Memory Interface (EMIF) for connection to external SRAM and Flash memories.

TECHNICAL BRIEF C. The visual data could be graphics. EQU. From an architecture-hierarchy perspective. E.programmable display interface for parallel/serial displays. • GRAPHCON . 4 x CHD. the SYSCON block is an APB slave on the slow APB bridge. DSP Hardware Subsystem The DSP subsystem provides support for processor intensive activity. F.23 - . Within the peripheral subsystem. CLKCON. GPRS CRYPTO. FCHDET. GAM Hardware Subsystem The Graphics Accelerator Module (GAM) subsystem provides hardware support in the creation of visual imagery and the transfer of this data to the display. With the exception of the USB. graphics controller. SERCON. . The GAM subsystem consists of five modules: • GRAM . CRYPTO. GAM also provides support for the camera module. • PDI/SSI . DIRMOD. D.graphics memory (160 kB). GPRS CRC24. • CDI . CHE. Peripheral Hardware Subsystem There are 29 peripherals within the peripheral hardware subsystem. The hardware peripheral blocks are RXIF. GSM Hardware Subsystem The GSM subsystem is a stand-alone sub-chip incorporating GSM modem and interface to GSM radio together with memory control (MEMSYS) and internal RAM (IRAM).camera data interface. MEMSYS and IRAM. The APB provides a simple interface to support low-performance peripherals. all hardware peripheral blocks are APB slave peripherals. The peripherals are accessible to the AHB (CPU-only) by an asynchronous I/O bridge. • GAMCON . GAM controller. still images or video. The dual port IRAM is accessible to the AHB (CPU and DMA) by a synchronous AHB slave interface. but resides at the top level of the ASIC. The DSP subsystem includes the standard C55xTM Core (LEAD3) from Texas Instruments with associated memory system and peripherals. TIMGEN. there are four separate APB busses with AHB to APB (AHB2APB) bridges to the multi-layer AHB. NODI. such as voice coding and multimedia application support.3.

SYSCON consists of analog and digital PLL clocks and a clock squarer. . System Control Subsystem The system controller subsystem (SYSCON) is primarily responsible for generating clock signals and distributing the clock and reset signals within the ASIC and certain external devices. Individual blocks can also be reset and their clocks held inactive by accessing the appropriate control registers.24 - . The programming of SYSCON controls the fundamental modes of operation within the ASIC.3. The block is a slave peripheral on the slow APB bus under control of the CPU. SYSCON also controls the requesting protocol through which different sub-blocks in Ericsson DB 20000 can request clocks derived from the system clock. GAM and DSP subsystems include their own system controllers that are sourced from SYSCON. TECHNICAL BRIEF G. The GSM core. The system controller also stores the chip-ID number in a read only register.

U8120 • 512Mb flash memory + 64Mb PSRAM • 3-CS(Chip Select) are used Interface Spec. Audio parameters and battery calibration data etc are stored in flash memory area. RF calibration data.25 - . Read Access Time Device Part Name Maker Async MCP FLASH PSRAM S71WS256HC0BAW00 Am29BDS128HD9VKI S71WS256HC0BAW00 AMD AMD AMD 56 ns 56 ns 70 ns Page – – 20 ns Burst 13.1.3. CS2. U8100 & U8110 • 384Mb flash memory + 64Mb PSRAM • 4-CS(Chip Select) are used Interface Spec. Read Access Time Device Part Name Maker Async MCP FLASH PSRAM RD38F4050L0YTQ0 NZ48F4000L0YBQ0 RD38F4050L0YTQ0 Intel Intel Intel 85 ns 85 ns 85 ns Page 25 ns 25 ns 25 ns Burst 14 ns at 54MHz 14 ns at 54MHz 10 ns at 66MHz Write Access Time 85 ns 85 ns 85 ns Table External memory interface for U8120 .5 ns at 54MHz 13. TECHNICAL BRIEF 3. CS1. A.3 External memory interface There are four independent chip selects (CS0.5 ns at 54MHz – Write Access Time 56 ns 70 ns 70 ns Table External memory interface for U8100 & U8110 B. CS3) provided for external memories and each has an address range of 256 Mb.

IDATA. WANDA Interface Wanda controls WCDMA RF part using these signals through W-CDMA RF chip-Wopy & Wivi.3. QDATA : GSM/DCS RX Data • DIRMOD[A:D] : GSM/DCS TX Data Figure. • RFCLK.4 RF Interface A. Figure. Schematic of WANDA RF Interface . RXON : Control signals for TX and RX part of Ingela • PCTL : Control signal for GSM TX PAM • BANDSEL0 : Band selection signal for GSM or DCS • ANTSW[0:3] : Control signals for antenna switch • DCLK. RFSTR : Control signals for Ingela • TXON. TECHNICAL BRIEF 3. MARITA Interface Marita controls GSM RF part using these signals through GSM RF chip-Ingela. Schematic of MARITA RF Interface B.26 - . RFDAT.1.

HSSLTX_CLK : Control signals for Wivi & Wopy : WCDMA RX Data : WCDMA TX Data : Marita & Wanda Communication Signal : Marita & Wanda Communication Signal . Schematic of WANDA RF Interface • RADIO_CLK. RXIB.27 - . RXQB • TXIA. RADIO_DAT. TXQA. TXQB • HSSLRX_D. HSSLRX_CLK • HSSLTX_D. TECHNICAL BRIEF Figure. RXQA. RADIO_STR • RXIA. TXIB.3.

1.6 UART Interface UART signals are connected to MARITA GPIO through IO connector UART0 Resource GPIO10 GPIO11 Name UARTRX0 UARTTX0 UART1 GPIO14 GPIO15 GPIO16 GPIO17 UARTRX1 UARTTX1 UARTRTS1 UARTCTS1 Transmit Data (UART1) Receive Data (UART1) Request To Send Clear To Send Table. TECHNICAL BRIEF 3.3. UART Interface Note Transmit Data Receive Data . SIMRST0 ports are used to communicate DBB(MARITA) with ABB(VINCENNE) and filter. SIM Interface MARITA VDIG 10K SIMVCC VINCENNE 15K VDD SDAT SCLK SR ST SIMDAT SIMCLK SIM RST DAT CLK RST CARD SIMDAT0 SIMCLK0 SIMRST0 Figure.28 - .1. SIM (Interface between DBB and ABB) SIMDAT0 SIMCLK0 SIMRST0 SIM card bidirectional data line SIM card reference clock SIM card async/sync reset Table. SIMCLK0.5 SIM Interface SIMDAT0. SIM Interface 3.

and enable level are shown in below table.7 GPIO (General Purpose Input/Output) map In total 40 allowable resources.3. describing application. GPIO Map. IO # GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO30 GPIO31 Application Not used BL_PWL 7C_LED_VDD_EN PULSESKIP (Not used) CAMERA_DET GPIO05 (Not used) AMPCTR TGBUZZ (Not used) UARTRX0 UARTTX0 Not used Not used UARTRX1 UARTTX1 UARTRTS1 UARTCTS1 CAM_REG_EN CAM_FLASH_ON TP2125 (Not used) CAM_FLASH_SHOT Not used Not used Not used Not used Not used Not used IO – O O I I O O O I O – – I O I O O O – O – – – – – – Resource – GPIO GPIO GPIO GPIO – GPIO GPIO UART0 UART0 – – UART1 UART1 UART1 UART1 GPIO GPIO – GPIO – – – – – – Inactive State – Low Low – High – Low Low High High – – High High High – Low Low – Low – – – – – – Active State – High High – Low – High High Low Low – – Low Low Low – High High – High – – – – – – . I/O state. This model is using 25 resources.1. TECHNICAL BRIEF 3.29 - .

MARITA GPIO Map Table . TECHNICAL BRIEF IO # GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 Application KEY_LED_ONOFF Not used Not used LCDVSYNCI (Not used) SPKMUTE Not used USBSENSE Not used BL_EN FOLDER_DET EN_LED_R EN_LED_G EN_LED_B IRDA_REG_CTRL IO O – – I O – I – O I O O O O Resource GPIO – – GPIO GPIO – GPIO – GPIO GPIO GPIO GPIO GPIO GPIO Inactive State Low – – Low Active State High – – High LOW (Ear piece) HIGH (Speaker) – Low – Low High Low Low Low Low – High – High Low High High High High Table.30 - .3.

31 - . Data for each endpoint is buffered in RAM within the USB block and is read/written from the endpoint FIFO using DMA transfers or FIFO register access. TECHNICAL BRIEF 3.3. three for IN endpoints and three for OUT endpoints. The USB block can request up to six DMA channels.0 standard. The USB specification allows up to 15 pairs of endpoints. Schematic of MARITA USB block . and handles USB transactions with minimal CPU intervention.1. It provides an interface between the CPU (embedded local host) and the USB wire. High-speed (high throughput) endpoints can use DMA while slower endpoints can use FIFO register access.8 USB The USB block supports the implementation of a "full-speed" device fully compliant to USB 2. USB Signal Interface of MARITA Figure. USB Function USBDP USBDM USBSENSE (GPIO40) USBPUEN VDDUSB Note USB differential (+) line USB differential (-) line USB detection (input) USB pull-up control Power supply for MARITA USB block Table.

TECHNICAL BRIEF USB regulator input voltage is 5V and uses external USB device power through IO Connector.32 - .3V and supply to MARITA USB block.3. Schematic of USB filter . Schematic of USB Regulator Figure. USB is detected by MARITA GPIO40(USBSENES). • VUSB / (10K + 51K) = VUSBSENSE / 51K Figure. Output voltage is 3.

3.600 bps. Figure. TECHNICAL BRIEF 3. MIR and SIR mode. the IrDA block supports SIR (Standard IrDA) mode.9 IrDA Interface MARITA supports FIR. In this model.1. IrDA supports a protocol defined by the IrDA Association.600/19.200/38. In this mode. SIR supports data rates up to 115.33 - . Schematic of MARITA IrDA Interface .200 bps. including 9.400/57. IrDA uses eight data bits per character and one stop bit.

34 - . Schematic of MARITA IrDA Interface . Otherwise. VCAM R3206 100K CAMERA_DET N3200 A3212ELH 1 VDD 3 GND OUT 2 C3204 0.3. opened or closed.1u C3205 10p Figure. 2. the voltage at pin2 of U1 goes to 0V. This folder signal is delivered to MARITA GPIO43. If a magnet is close to the hall-effect switch (U1 on keypad). TECHNICAL BRIEF 3.10 Folder ON/OFF Operation There is a magnet to detect the folder status.8V.1.

Power On Sequence . VINCENNE 2 1 Press END key 3 Power for MARITA MARITA 4 PWRRSTn PWRRST 1 ONSWAn ONSWA RESETB RESOUT0_N IRQ 4 IRQ0n RESPOW_N IRQ0_N Figure. 3 VINCENNE generate a power for MARITA. TECHNICAL BRIEF 3.3.35 - .1.11 Power On Sequence 1 User press END key and ONSWAn signal is changed to Low. 2 VINCENNE initiate the internal oscillator and power up the regulators. 4 VINCENNE release the power reset signal(PWRRSTn) and generate an interrupt(IRQ0n) to MARITA.

12 Key Pad There are 26 buttons and 3 side keys in Figure 3-xx.1. Power On Sequence .3.36 - . TECHNICAL BRIEF 3. KEYIN0 KEYOUT0 KEYOUT1 KEYOUT2 KEYOUT3 KEYOUT4 KEYOUT5 1 2 3 SEND MENU KEYIN1 SIDE1 4 5 6 CLEARER SEARCH KEYIN2 SIDE2 7 8 9 BACK MULTI KEYIN3 SIDE3 * 0 # GAME CAM UP DOWN RIGHT LEFT OK KEYIN4 Table Key Matrix Mapping Table Figure.Shows the Keypad circuit.‘END’ Key is connected ONSWAn from Vincenne.

37 - . GAM controller. graphics controller. The GAM subsystem consists of five modules: • GRAM . • PDI/SSI .graphics memory (160 kB). • GRAPHCON .3. TECHNICAL BRIEF 3. • GAMCON .programmable display interface for parallel/serial displays. • CDI .camera data interface.2. GAM Subsystem Functional Block Diagram 3.1 General Description The Graphics Accelerator Module (GAM) subsystem provides hardware support in the creation of visual imagery and the transfer of this data to the display. . still images or video.2 GAM Hardware Subsystem Figure. GAM also provides support for the camera module. The visual data could be graphics.

The three image areas can be combined into one frame buffer. Subsequent sequential read access take a single AHB clock cycle. video frames or camera frames. The programmable PDI block is configured at the software build stage. Images can be moved and merged with other images and text. Graphics Controller (GRAPHCON) Block GRAPHCON is controlled by the application CPU and can perform operations on pixels and image areas. 16 or 32-bit mode. The PDI block is built around a micro controller and executes 16-bit instruction words to individually control the I/O ports. GRAM. The CPU transfers all set-up and control data to the display. that is 12 MByte/s. The reset signals CIRES_N and PDIRES_N are distributed from GAMCON to the camera and display module respectively. It has a 128 byte program memory. programmable by the CPU. The CIPCLK is used to clock the received data into the camera data interface.3. Programmable Display Interface (PDI) Block The programmable display interface (PDI) is designed to interface both parallel and serial display modules. TECHNICAL BRIEF 3. GRAM. Non-sequential read and the first access of a sequential read access takes two AHB clock cycles. see Figure.38 - . GRAPHCON performs conversion from YUV to RGB and can scale (zoom) still or video images. which can store up to 64 instructions. GAMCON also distributes the GAM reset signal to GRAPHCON. The GRAPHCON block receives graphical objects from GRAM and performers the appropriate graphical manipulation. GAMCON receives the HCLK from SYSCON and distributes to GRAPHCON. The GRAM is used as a buffer. There are three image areas with one used for normal MMI graphics and the other two areas used for still images.2 Block Description GAM Controller(GAMCON) The GAM Controller (GAMCON) is responsible for clock gating and distribution within the GAM module. The GRAM contains both frame buffer and temporary data. which in turn writes 8-bit data to the display. but the average transfer bandwidth required is approximately 3 Mword/s (32-bit word).2. PDI and CDI. . Write access takes a single AHB clock cycle. The resulting data is transfers to the display interface (PDI). GRAM is required to transfer a VGA (640 by 480 pixels) image from the camera data interface (CDI) over DMA at 100 MBit/s. Graphics RAM (GRAM) Block GAM includes 160 kB of graphics memory (GRAM) in order to support display screen sizes of QCIF + alfa display size and three frame buffers when decoding QCIF video. The CIPCLK can be in the range of 100 kHz to 16 MHz. within a 50 ms timeframe. to support either parallel interface such as PPI or serial interface such as SSI or I2C. The GRAM can be accessed in 8. The display data is transferred from the 32 word FIFO on GAMCON to the display module via the PDI block. GRAPHCON can receive images from the camera data interface (CDI) and send them to the PDI automatically. Data is transferred to PDI as 32-bit words. PDI and CDI.

3. TECHNICAL BRIEF

Camera Data Interface (CDI) Block
The camera data interface (CDI) block is designed to support a range of still image camera modules. An 8-bit parallel bus supports data transfer from the camera module to the CDI. The pixel clock is an output clock from the camera module to the CDI and qualifies the data on the parallel bus. One byte of data is captured on each rising edge of the pixel clock. CDI allows the pixel clock to be in the range of 100 kHz to 16 MHz. The horizontal synchronization line is an input from the camera module and defines one scan-line of image data. The horizontal synchronization line can be programmed to be active high or low. The vertical synchronization line is an input from the camera module and defines one image frame (image height) of data. The vertical synchronization line can be programmed to be active high or low. The frame rate can be adjusted by skipping frames and various interrupts are used to inform the application CPU regarding the progress of incoming images and potential errors. The normal data format on the data bus is YUV 4:2:2 (raw binary image data) according to the CCIR-656 standard. A function within the CDI can be programmed to reorder the YUV parameters as they pass through the CDI. In addition, the CDI is able to detect the end of an image and perform some truncation as well as overflow conditions. There is nothing preventing the use of other data types such as JPEG or RGB (as long as the timing is followed), but only YUV data can be sent to the display. Camera images can also be sent to a DMA channel to store the image in external memory.The I2C interface and GPIO are part of the interface to the camera module, but they are not part of the CDI block. The I2C is used to set-up and control the camera module. The camera module I2C lines must go high impedance when the supply is removed from the camera. The I2C commands needed to control the camera, as well as the functional behavior of the module, are also different for each implementation. The ON-signal (GPIO) is used to power-on the camera from Standby or Off mode (implementation dependent). This signal must be held low when the mobile equipment is powered down and during the mobile equipment reset period. The GPIO pin can also be an input or high impedance during mobile equipment reset and start. In this case, it must have pull-down to ground. The camera module reset signal is an output to the camera module.

- 39 -

3. TECHNICAL BRIEF

3.2.3 Camera & Camera FPC Interface

PDID1 PDID2 PDID3 PDID4 PDID5 PDID6 PDID7 I2CSCL I2CSDA CIPCLK CIVSYNC CIHSYNC CIRES_N CID0 CID1 CID2 CID3 CID4 CID5 CID6 CID7

VSSMC VSSDM VSSUSB VSSRTC VSSA0 VSSA1 VSSA2

C18 B19 A20 H13 G14 B20 Y2 W3 H18 H15 G21 E19 E20 E21 H14 F19 F20 G18 G19 G20 VDIG

PDID1 PDID2 PDID3 PDID4 PDID5 PDID6 PDID7

VDIG

R2304

3.3K

I2CDAT CIPCLK CIVSYNC CIHSYNC CIRES_N CID0 CID1 CID2 CID3 CID4 CID5 CID6 CID7
VCORE VDIG

K18 E3 J18 R11 V12 W13 V14

CAMERA I/F

R2303

4.7K R3329

1

2

3

3.3K R3330

4.7K

I2CCLK

R3333 NA

Q3202 PMST3904

RTC_GND

I2CCLK_CAMERA

Figure. Camera Interface (in Marita)

Figure. Camera Board to Board Connector

- 40 -

3. TECHNICAL BRIEF

The Camera module is connected to main board with 20pin Board to Board connector (AXK7L80225). Its interface is dedicated camera interface port in Marita. The camera port supply 24MHz master clock to camera module and receive 12MHz pixel clock (30fps), vertical sync signal, horizontal sync signal, reset signal and 8bits YUV data from camera module. The camera module is controlled by I2C port. NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name DOUT4 DOUT5 VD DOUT1 DOUT2 DCLK DOUT0 DOUT3 EXTCLK GND FSSTB DVDD GND SCL RESET AVDD HD SDA DOUT6 DOUT7 DO DO DO DI DO Pin Type DO DO DO DO DO DO DO DO DI Description Image data output Image data output Vertical Synchronization Pulse Output Image data output Image data output Clock for Output Data Image data output Image data output External Clock Input Ground Strobe Pulse for Flash VDD for the Digital Circuit Ground Clock for IIC bus Command Reset Terminal VDD for the Sensor and PLL Horizontal Synchronization Pulse Output Clock for IIC bus Command Image data output Image data output

Table. Interface between Camera Module and Main Board (in camera module)

- 41 -

3. TECHNICAL BRIEF

3.2.4 Camera Position Detection
GPIO_04 detects the Camera Position (front or back)

Figure. Camera Position Detection

3.2.5 Camera Regulator
GPIO_20 enables Camera Regulator Operation

Figure. Camera Regulator

- 42 -

3. TECHNICAL BRIEF

3.2.6 Display & LCD FPC Interface
LCD module include device in table 3-2 Device Main LCD Sub LCD Main LCD Backlight Sub LCD Backlight Type 176 x RGB x 220 65K Color TFT LCD 96 x 64 Mono FSTN LCD White LED 7 color LED Table. Devices in LCD Module

LCD module is connected to key board with 40-pin BtoB connector (CONN_40_AXK840145J) and Speaker, Receiver, Vibrator, Camera Flash is connected by soldering the leads to 9 pads in LCD module. The Main LCD is controlled by 8-bit PDI(Parallel Data Interface) in Marita and Sub LCD is controlled by 8-bit PDI in Marita. PIN SYMBOL FUNCTION SPK TERMINAL 1 2 3 4 EARP EARM SPKP SPKM Ear Piece Plus Ear Piece Minus Loud Speaker Plus Loud Speaker Minus MOTOR TERMINAL 1 2 MOTOR_BATT MOTOR_GND MOTOR Power MOTOR Ground CAMERA FLASH TERMINAL 1 2 3 VOUT_F1 VSIG_F2 F3 FLASH Power FLASH Signal Dummy Ground O O O O O O O O O I/O REMARKS

Table. Interface between LCD module and Speaker, Receiver, Vibrator, Flash

- 43 -

3.8V LCDERESX LCDCSX_MAIN LCDWRX PDID7 PDID5 Ground FUNCTION I/O REMARKS Turn ON the Camera Flash Shot MOTOR Power Loud Speaker Plus Loud Speaker Minus Enable Signal for Sub LCD Backlight LED(Green) Power Supply for Sub LCD Backlight Enable Signal for Main LCD Backlight Parallel Data 0 bit for Main/Sub LCD Parallel Data 2 bit for Main/Sub LCD Parallel Data 4 bit for Main/Sub LCD Parallel Data 6 bit for Main/Sub LCD Read Signal for Main/Sub LCD status Register Select Pin Chip Select Signal for Sub LCD Main LCD Vertical Synch.44 - . TECHNICAL BRIEF PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 SYMBOL GND CAM_FLASH_SHOT MOTOR_BATT SPKP SPKM EN_LED_G 7C_LED_VDD BL_EN PDID0 PDID2 PDID4 PDID6 LCDRDX LCDRS LCDCSX_SUB LCDVSYNCI GND GND GND GND GND GND VDIG_2. Signal Ground Ground Ground Ground Ground Ground Power Supply for system and I/O Logic(2.8V) Reset Signal for Main/Sub LCD Chip Select Signal for Main LCD Write Signal for Main/Sub LCD Parallel Data 7 bit for Main/Sub LCD Parallel Data 5 bit for Main/Sub LCD .

3. Interface between LCD module and main board(in LCD Module) .45 - .2V EN_LED_B EN_LED_R EARP ERAM GND CAM_FLASH_ON GND FUNCTION Parallel Data 3 bit for Main/Sub LCD Parallel Data 1 bit for Main/Sub LCD Main LCD PWL signal Battery Power(4.2V) Enable Signal for Sub LCD Backlight LED(Blue) Enable Signal for Sub LCD Backlight LED(Red) Ear Piece Plus Ear Piece Minus Ground Turn ON the Camera Flash Continuous ON Ground I/O REMARKS Table. TECHNICAL BRIEF PIN 30 31 32 33 34 35 36 37 38 39 40 SYMBOL PDID3 PDID1 BL_PWL VBATI_4.

Charge Pump Circuit for Main LCD Backlight * LED : SSC-HWTS902(Seoul Semiconductor) .7 Main LCD Backlight Illumination There are 4 white LEDs in Main LCD Backlight circuit which are driven by 4.46 - . Figure. TECHNICAL BRIEF 3.3.2. GPIO_01(BL_PWL) is used for Backlightbrightness control.5V Regulated Output Charge Pump(SC604).

Red LED is turned-on. .8 Sub LCD Backlight Illumination GPIO_02(7C_LED_VDD_EN) in Marita enables 7 color LED. 7 color LED consists of Red LED. Sub LCD Backlight 4. GPIO_44(EN_LED_R). if TA is inserted.2.5V In case of power off mode. GPIO_45(EN_LED_G) and GPIO_46(EN_LED_B) in Marita does ON or OFF its own LEDs. Figure.47 - . Green LED and Blue LED.3. TECHNICAL BRIEF 3.

TECHNICAL BRIEF 3.48 - . which aredriven by GPIO_32 (KEY_LED_ONOFF) line form Marita.3.2. Keypad Backlight Circuit . Keypad Backlight Blue LED Interface Figure. Figure.9 Keypad Illumination There are 19 blue LEDs in key board backlight circuit.

Camera Flash FPCB & Circuit . Mode 2.2. combines Mode 1. Camera Flash Circuit Figure.3. and Mode 2. TECHNICAL BRIEF 3. Mode 1.49 - . Is Continuous ON mode using GPIO_21(CAM_FLASH_ON).10 Camera Flash Illumination Camera Flash illumination circuit make 3 modes using white LED. Figure. Is Flash Shot using GPIO_23(CAM_FLASH_SHOT) and Mode 3.

LCD Module Block Diagram Figure.50 - . LCD Module(Main & Sub LCD) .3 LCD Module Figure. TECHNICAL BRIEF 3.3.

Audio Path Block Diagram . TECHNICAL BRIEF 3.1 Overview of Audio path Figure.4.3.4 Analog Baseband (ABB) Processor 3.51 - .

This transmitted signal is reformed to fit in GSM & WCDMA Frame format and delivered to RF Chip. Figure.4. The decoder has a receive volume control.52 - . microphone amplifiers and earphone drivers. The audio interface consists of PCM encoding and decoding circuitry. The uplink path amplifies the audio signal from MIC and converts this analog signal to digital signal and then transmit it to DBB Chip (Marita).2 Audio Signal Processing & Interface Audio signal processing is divided Uplink path and downlink path. Audio Interface Detailed Diagram (VICENNE) . The PCM encoder and decoder blocks are two-channel. 16-bit circuits with programmable gain amplifiers (PGA).3. The audio inputs and outputs can be switched to normal or auxiliary ports. The downlink path amplifies the signal from DBB chip (Marita) and outputs it to Receiver (or Speaker). TECHNICAL BRIEF 3.

3. TECHNICAL BRIEF Figure.53 - . Audio Section scheme .

4.3 Audio Mode Audio Mode includes three states. Loud Speaker. Headset). TECHNICAL BRIEF 3. Video Telephony Mode Operate on state of the WCDMA CALL.MP3).3. (Voice call.54 - . Each states is sorted by the total 7 Modes according to external Devices (Receiver. VINCENNE In/Out Port Mode IN Receiver Mode Loud Speaker Mode Voice call Headset Mode Video Telephony Mode MIDI MP3 Only Loud Speaker Loud Speaker Mode Headset Mode Table Audio Mode AUXI1 MIC1P/MIC1N AUXO1/AUXO2 BEARP BEARP BEARP AUXO1/AUXO2 MIC1P/MIC1N MIC1P/MIC1N OUT BEARP/BEARN BEARP . Midi.

Speaker. Voice call Downlink Scheme .1 Voice call Downlink Mode(Receiver.4.4.4.3. Headset) This section provides a detailed description of the Voice Call RX functions. Figure.4 Voice Call 3.55 - . TECHNICAL BRIEF 3.

TECHNICAL BRIEF The voice decoder accepts a serial input stream of linear PCM coded speech. The earphone amplifier and the auxiliary audio outputs can be powered down (muted) via I2C. Mode Receiver Headset Loud Speaker Video Telephony SPKMUTE High High Low Low Table Speaker Phone Mode GPIO control state AMPCTRL Low Low High High * SPKMUTE.3. • Receiver Mode : Earphone amplifier → BEARP/N Port → Receiver(32Ω) • Loud Speaker Mode : Earphone amplifier → BEARP Port → Analog S/W(ADG702) → AUDIO AMP(LM4894IBP) → Speaker(8Ω) •Video Telephony Mode : Earphone amplifier → BEARP Port → Analog S/W(N2603) → AUDIO AMP (LM4894IBP) → Speaker(8Ω) • Headset Mode : Auxiliary audio amplifier → AUXO1/2 → TJATTE2 IN (AFMS_R_INT/AFMS_L_INT) → TJATTE2 OUT(AFMS_R/AFMS_L) → Head Phone Speaker Phone Mode has two GPIO switching control ports. SPKMUTE controls analog switch( ADG702) and AMPCTRL controls shutdown of AUDIOAMP(LM4894IBP). The auxiliary audio amplifier is intended to drive low impedance headphones. The final step in the receive path is the earphone amplifier and the auxiliary output. Both the earphone driver and one of the auxiliary drivers can simultaneously provide an output signal during voice decoding. The receive band-pass filter is the next step in the CODEC receive path.56 - . Following the filter is the DAC. MARITA GPIO36 * AMPCTRL. Video Telephony Mode has same paths with Loud Speaker Mode. MARITA GPIO06 . One is SPKMUTE and the other is AMPCTRL. followed by a PGA enabling to adjust or trim the circuit in the product for different sensitivity of the earphone and spread in the RX path.

The ADCs are followed by the transmit band pass filters.2 Voice Call Uplink Mode (Receiver. a source from an external microphone or as an analog loop connection. Speaker.4. a transmit gain control amplifier precedes the final encoding of the PCM output. and maintain a good signal-to-noise ratio. Figure. TECHNICAL BRIEF 3.4V.3.57 - . which accept the maximum output swing that the microphone preamplifiers can deliver without clipping. The high pass filter in the TX-paths can be disabled via I2C. For one of the two transmit paths. But the voltage source of our Model is to supply 2. Both microphone inputs are compatible with an electric microphone.4V. Headset) This section provides a detailed description of the Voice Call TX functions. still removing the DC offset from the signal. which enables to adjust the total gain in the product for different sensitivities of the microphones and spread in the transmit paths. The VINCENNE internal voltage source (CCO) provides the necessary drive current for the electric microphone. Voice call Uplink Scheme The Uplink supports two microphones and two auxiliary inputs to the speech encoder blocks. The auxiliary audio inputs can be used as an alternative source of speech. .4. The voltage source is via I2C programmable to supply 2. Figure shows that the audio inputs are fed to the transmit PGAs.2V or 2.

Receiver Mode : C-MIC(OBG-15S44) → TJATTE2 IN (MICP/N) → TJATTE2 OUT (MICP_INT/MICN_INT) → VICENNE Input(MIC1N/1P) Loud Speaker Mode : C-MIC(OBG-15S44) → TJATTE2 IN (MICP/N) → TJATTE2 OUT(MICP_INT/MICN_INT) → VICENNE Input(MIC1N/1P) Video Telephony Mode : C-MIC(OBG-15S44) → TJATTE2 IN (MICP/N) → TJATTE2 OUT (MICP_INT/MICN_INT) → VICENNE Input(MIC1N/1P) Headset Mode : Headset MIC → EARJACK S/W(X2602.58 - . So. GPA6(Circuit Diagram net Name) converted into low state. TECHNICAL BRIEF Each Voice Uplink Mode paths shown below.3. . the headset icon is displayed on Main LCD. Pin Num 2) → TJATTE2 IN(ATMS_CAP) TJATTE2 OUT (ATMS_INT) VICENNE Input(AUXI1) When the headset is inserted.

MIDI Scheme External MIDI path is the same as Voice Loudspeaker downlink Mode. TECHNICAL BRIEF 3. MIDI Mode control port shown below STATE(SPK ONLY) MIDI ON MIDI OFF SPKMUTE LOW High Tabel MIDI GPIO Control STATE * SPKMUTE. • MIDI : MARITA → PCM Decoder → Earphone amplifier → BEARP Port → Analog S/W(ADG702) → AUDIO AMP(LM4894IBP) → Speaker(8Ω) MIDI being played through external Device Speaker only. MARITA GPIO06 AMPCTRL High Low .59 - . except source in MARITA (DSP and Audio Mixer). MARITA GPIO36 * AMPCTRL. Figure.4.3.5 MIDI (Ring Tone Play) This section provides a detailed description of the MIDI and WAV-file functions.

. auxiliary outputs (AUXO1 and AUXO2) can be used to drive the headset.3.60 - . Figure.The PCM44/48 RX-path is intended to be used as a stereo music headphones.4. In stereo mode. In single channel mode (mono). MP3 Scheme MP3 function supports PCM 44/48KHz sampling rate. It is also possible to connect a differential load or to use the RX-path with only one channel running (mono).6 MP3 (Audio Player) This section provides a detailed description of the MP3 file functions. TECHNICAL BRIEF 3. BEARP can be used to drive a load (Speaker).

MARITA GPIO36 .4. Figure.61 - .3.7 Video Telephony This section provides a description of the Video Telephony functions. Video Telephony Scheme Video Telephony Mode has same paths with Loud Speaker Mode. STATE(SPK ONLY) Video Telephony ON Video Telephony OFF SPKMUTE LOW High AMPCTRL High Low Tabel Video Telephony GPIO Control STATE * SPKMUTE. TECHNICAL BRIEF 3. MARITA GPIO36 * AMPCTRL.

8 Audio Main Component There are 6 components in U8100 schematic Diagram.3.62 - . In addition. the TJATTE2 incorporates diodes to provide protection to downstream components from Electrostatic Discharge (ESD) voltages as high as 8 kV. N0 1 1 3 4 5 6 ITEM Dual Speaker C-MIC Audio AMP TJATTE2 Ear-JACK Analog Switch Part Name EMD1940A OBG-15S44 LM4894IBP IP4025CS20 HSJ1730 ADG702 X2603 N2601 N2602 X2602 N2603 Part Number Tabel Audio Component List TJATTE2 Description The TJATTE2 is a 6-channel RC low pass filter array that is designed to provide filtering of undesired RF signals in the 800-2700 MHz frequency band. Part Number marked on U8100 Schematic Diagram. PIN A1 A2 A3 A4 A5 DESCRIPTION MICN MICP ATMS ATMS-cap AFMS_L PIN B1 B2 B3 B4 B5 DESCRIPTION GND GND GND AFMS_R VDD PIN C1 C2 C3 C4 C5 DESCRIPTION CCO ATMS_AD GND GND GND PIN D1 D2 D3 D4 D5 DESCRIPTION MICN-int MICP-int ATMS-int AFMS_R-int AFMS_L-int Tabel TJATTE Pin Description . TECHNICAL BRIEF 3.4.

3. TJATTE2 Block Diagram . TECHNICAL BRIEF Figure.63 - .

GPADC and AUTOADC2 Block diagram ADC 6 channels Resource GPA0 GPA2 GPA3 GPA4 GPA6 GPA7 Name RTEMP VLOOP WPOWERSENSE WRFLOOP GPA6 VBACKUP Table.64 - . AUTOADC2. Schematic of GPADC and AUTOADC2 Figure. Figure.3. The analog input signal is selected with the MUX and converted in the ADC.9 GPADC(General Purpose ADC) and AUTOADC2 The GPADC consists of a 14 input MUX and an 8-bit ADC. which is able to operate in the background without software intervention. The GPADC channel spec is as following Table. TECHNICAL BRIEF 3.4. The GPADC has a built in controller. GPADC channel spec Description Radio temperature sense Loop voltage sense Reference voltage for PAM Lock inform Headset detect Backup battery . The AUTOADC2 periodically measures the battery voltage or current. Figure shows the schematic of GPADC part.

and the output current from DCIO via the sense resistor to CHSENSE-. It is possible to set limits for the output voltage at CHSENSE. Schematic of charging control part Figure. Figure shows the schematic of charging control part. The voltage at CHSENSE.65 - . the two measuring amplifiers translate these inputs to a voltage proportional to the input and within the range of the GPADC. TECHNICAL BRIEF 3.10 Charger control A programmable charger in AB2000 is used for battery charging.4. Battery charging block diagram . DCIN_3 C2280 NA 1608 Q2201 Si5441DC 1 8 D1 D6 2 7 D2 D5 3 6 D3 D4 4 5 G S R2214 0.3.cannot be measured directly by the GPADC.1 E2 D1 D3 D2 DCIO CHREG CHSENSE+ CHSENSE- DCIN_2 VBATI Figure. Instead.and the current feed to CHSENSE.

The Schematic of the fuel gauge block Name FGSENSE+ FGSENSE- Type Analog Analog Unused VBAT VBAT Description Fuel gauge current sensing input positive Fuel gauge current sensing input negative Table. A sense resistor R_FGSENSE is connected in series with the battery. By constantly integrating the current flowing into and out of the battery.3. Figure. Fuel Gauge channel spec . TECHNICAL BRIEF 3. The voltage across the resistor. The function of the fuel gauge block is schematically described in Figure. the fuel gauge block is used to determine the remaining battery capacity.11 Fuel Gauge AB2000 supports the measurement of the current consumption/charging current in the U8100 with a fuel gauge block. is integrated using an ADC block. The analog front-end of the fuel gauge block Figure. equivalent to the current entering/leaving the battery.66 - .4.

Figure shows the schematic of battery temperature measurement part.3.67 - . This battery data is converted to the battery temperature. Figure. the constant current source. feed the battery data output while monitoring the voltage at the battery data node with GPADC.12 Battery Temperature Measurement The BDATA node. Battery Temperature Measurement Name BDATA Type Digital Input/Output Unused Unconnected Description Current output Table BDATA channel spec . TECHNICAL BRIEF 3.4.

87 (V) 100 ~ 68 (%) 3.68 - . The DCIO signal is asserted when its voltage is above the voltage at VBAT.87 ~ 3.20 (V) 5 ~ 0 (%) Figure. As soon as generator is turned off and all parts of the charging block are functional and active. a current generator take care of initial charging of the CHSENSE+ node and internal trickle charge signal is active. 3.50 (V) 26 ~ 5 (%) 3.20 ~ 3.72 ~ 3. TECHNICAL BRIEF 3. This part of the charging block is powered on and active when DCIO is asserted. It is enabled or disabled by the assertion/negation of the external signal DCIO. Figure shows the schematic of charging part. Figure.4. Battery Block Indication . Battery block indication as shown in Fig 4.77 ~ 3.3.72 (V) 47 ~ 26 (%) 3. Part of the charging block are activated and deactivated depending on the level of VBAT.13 Charging Part The charging block in AB2000 processes the charging operation by using VBAT voltage.77 (V) 68 ~ 47 (%) 3. Charging Part When VBAT is below a certain value.50 ~ 3.2V.

3.2V. (a) Charging voltage (b) Charging current Figure. The charging current is set to 50mA. CCCV charging method . a current generator take care of internal trickle charge signal is active. the current source for trickle charging is turned off and all parts of the charging block are active. The CCCV method regulates the charge current and the VBAT voltage. This picture shows the charging voltage(a) and charging current change(b). Parameter Trickle current Min 30 Typ 50 Max 60 Unit mA Table BDATA channel spec Normal charging When the VBAT voltage is within limits or the internal regulators are turned on. This charging method prevents the battery voltage to go above the charge set in the CCCV algorithm. TECHNICAL BRIEF Trickle charging When the VBAT is below a certain value. The charging method is ‘CCCV’.69 - . (Constant Current Constant Voltage) This charging method is used for Lithium chemistry battery packs. 3.

46V.3.3. Dedicated .3.70 - .2V Charging of Extended Temperature When the battery temperature is outside the normal charging specification.3 min.5h • Full charge indication current (icon stop current) : 80mA • Low battery POP UP : Idle .7V. is maintained at 3. VBAT. •Under 0 °C : Extended temperature •From 0 °C to 55 °C : Normal charging temperature •Over 55 °C : Extended temperature . the battery voltage. Dedicated – 3.2V • Maximum Charging Current : 600mA • Nominal Battery Capacity : 1200 mAh • Charger Voltage : 4.50V • Low battery alarm interval : Idle .6V • Charging time : Max 3.1 min • Cut-off voltage : WCDMA call .1V. ELSE – 3. TECHNICAL BRIEF • Charging Method : CCCV (Constant Current Constant Voltage) • Maximum Charging Voltage : 4.

3.8V LDO .8V and 2. The output of these LDOs and BUCK converter are as following Table.3V for USB 4.8V for Camera 3. 3.supply 2. The output of these LDOs supply VDD-A.2 External Regulation 1.5 Voltage Regulation 3.71 - . Figure shows the power supply of each module in U8100.supply 2.5V for LCD back light .3V LDO . LDO regulators and BUCK converter generate the following voltages : 1.supply 1.8V LDO .5.5.8V for IrDA 2.supply 3.1 Internal Regulation There are LDO (Low Drop Output) regulators and BUCK converter in AB2000 (Vincenne) chip. VDD-B and VDIG with 2. and to 1.5V for VCORE and VRTC. BUCK converter steps down the VBAT to 1.5V LDO .5V DC-DC converter – supply 4. 1. TECHNICAL BRIEF 3.5V for wanda core 2.5V.75V.75V.8V for VMEM voltage.

75V 1.3.5V Unused: VBAT GND Description Supply output Supply output Supply output Supply output Low Power supply output Buck converter switch supply Buck converter switch ground Table BDATA channel spec . TECHNICAL BRIEF Figure. Power Supply Scheme Pin B12 A11 M11 L12 L2 A2 B1 Name VDD_A VDD_B VDD_D VDD_E VDDLP VDDBUCK VSSBUCK Type Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Output voltage 2.8V 1.72 - .75V 2.75V 2.

For the W-CDMA part. Block diagram of RF part Starting at the antenna end. WCDMA duplexer.6 General Description The RF part includes a dual-band GSM/DCS part (900 and 1800MHz) and W-CDMA part for IMT-2000 (UL 1900MHz. an antenna switch provides switching capability needed for three frequency bands (900. duplexer is included to facilitate the simultaneous transmission and reception required for the FDD mode. The whole structure of Radio part is shown in Figure 3-1. Ingela(GSM/GPRS transceiver) and two power amplifiers. UMTS RX SAW UMTS RX IF SAW Antenna Duplex er UM TS Wopy RF PLL /VCO XO Dio de XO (13 MHz) Test po int Isola to r UMTS PA Antenna Switch UMTS TX SAW Tank IF PLL/VCO DC/DC Ro sa lie DCS RX SAW UM TS Wivi ADC ÷ GSM RX SAW ADC ÷ GSM Dual PA DCS Ba lun GSM Ingela Loo p filter Clk GSM Herta PD GSM Balun Prescaler Figure 3-1.3. Wivi(W-CDMA transmitter ASIC). WCDMA Power Amplifier and GSM Power Amplifier. The main components in the radio are Wopy (W-CDMA receiver ASIC). Vincenne provides power supply for the main RF components.73 - . DL 2100MHz). The mixed-signal circuit ASIC. TECHNICAL BRIEF 3. It also contains Antenna Switch. 1800 and 2100MHz). .

this control is handled via direct interfaces to individual RF components. In the GSM/GPRS air interface mode.74 - . The Marita(the main processor) also handles the antenna switch mechanism for selection of mode. TECHNICAL BRIEF The control flow for the Radio is shown in Figure 3-2. RF control signal flow diagram The Marita(the main processor) controls the overall radio system.3. . the RF system is managed via the Wanda (WCDMA digital base-band coprocessor ASIC) and its DSP processor. Figure 3-2. In the W-CDMA mode.

8V ~ 3. The logic for antenna switch is given below Table 3-1. two RF SAWs(Z1100. DCS RX.0V 2. RF Front end consists of antenna. TECHNICAL BRIEF 3.75 - . the filtered I and Q signals are converted by a sigma-delta converter into two 13 Mbps digital bit streams by Herta(A/D converter). VC1 GSM TX GSM RX DCS TX DCS RX WCDMA 0V 0V 2.0V 0V VCG 2.8V ~ 3. Z1110) and dual band LNAs integrated in transceiver(N1100).7 GSM Mode 3. is filtered by GSM RF SAW filter to suppress any unwanted signal except GSM RX band. the received RF signal.1 Receiver The received RF signal on the antenna connector arrives via antenna switch at external band pass filters for band selectivity. The LNA output signal is mixed with the on-channel LO generated by the proper VCO and transformed into a Q and an I signal. A. The process for DCS RX is also the same as GSM RX case. Front end. The control signals VC1. then fed to the Marita baseband ASIC.3. The filtered RF signal is amplified by an LNA integrated in the transceiver IC(N1100) and is passed to a direct conversion demodulator.0V 0V 0V VC2 0V 0V 2. The corresponding LNA amplifies the signal for optimum noise suppression. The I and Q signals are low pass filtered with two parallel high dynamic range filters. Antenna Switch logic . An antenna matching circuit is between the antenna and the coaxial connector. GSM TX.8V ~ 3.8V ~ 3.7. VC2 and VCG of antenna switch (N1000) are connected to Marita baseband ASIC(D2000) to control the signal path. GSM RX. The Antenna Switch(N1000) is used to select the signal path. The Received RF signals(GSM 925MHz ~ 960MHz. and DCS TX.0V 0V 0V 0V 0V Table 3-1. which has passed through the antenna switch. Finally. For example. antenna switch(N1000). when the GSM RX path is turned on. DCS 1805MHz ~ 1880MHz) are fed into the antenna or coaxial connector. One filter is required per supported GSM band. which is one of WCDMA.

The circuit contains one frequency down-conversion section for each receive band and a common base band amplifier and filter section. Figure 3-3. The same baseband circuitry is used for all bands. Figure 3-3 shows a block diagram of the receiver block. The I and Q signals are then buffered and low pass filtered. There is no gain switch in DCS 1800. An impedance level at RF of 150 ohms for the GSM 900 input and 50 ohms for the DCS 1800 input is chosen to minimmize current consumption at best noise performance. TECHNICAL BRIEF B.76 - . The amplified RF signal is mixed with the quadrature local oscillator signal to create in-phase (I) and quadrature phase (Q) baseband signals. The DCS 1800 RF part also has low noise amplifier connected to the other mixers. The GSM900 RF part consists of a low noise amplifier followed by high dynamic range mixers. Receiver Block. . The low gain mode in GSM 900 is used in high input signal mode. Balanced signals are used for minimizing cross talk due to package parasitics.3. Block diagram of receiver part.

Figure 3-4. Figure 3-4 shows a block diagram of the LO block.3. Block diagram of the LO part. TECHNICAL BRIEF C. The LO signal is also supplied to the prescaler and transmit output buffer. . LO Block The LO signals from the receive VCO section drive the dividers for GSM 900 and DCS 1800 respectively to provide quadrature LO signals to the receive mixers.77 - .

A separate ground pin is also used as varactor ground reference to prevent DC voltage drop changes from affecting the VCO frequency. . VCO Block The VCOs are fully integrated balanced LC oscillators with on-chip resonators.3. The receive VCOs run on double frequency. Figure 3-5.78 - . Figure 3-5 shows a block diagram of the VCO block. The VCOs are supplied from a separated external voltage regulator to avoid frequency pushing and up conversion of low frequency noise. Block diagram of the VCO part. TECHNICAL BRIEF D. Different frequency ranges can be selected in the VCOs for GSM/DCS band operation.

3. TECHNICAL BRIEF

E. PLL Block
The PLL consists of a programmable prescaler with multiple division ratios and a phase and frequency detector with a charge pump with programmable output current. Channel frequency selection and transmitter modulation is controlled via the prescaler modulus inputs MODA ~ MODD and the prescaler offset value N offset. The MODA ~ MODD signals could be delayed 0, 5, 10 or 15 ns with MD bits to be synchronized with the XO signal. Figure 3-6 shows a block diagram of the PLL block.

Figure 3-6. Block diagram of the PLL part.

- 79 -

3. TECHNICAL BRIEF

3.7.2 Transmitter
A 4-bit sigma-delta bit stream comes from the Marita ASIC including both channel information and the GMSK phase information. Via the 3-wire control bus also driven from Marita, the selection of transmitter band is made. The 4bits from the bit stream provides the fine-tuning of the division ratio before going to the divider of the used VCO (low band, 900MHz or high band, 1800MHz). The modulated VCO signal is fed to the output buffer. One buffer is available for each of the low and high bands. Trimming capability is included for best match versus the PA used. The GSM/GPRS transceiver, Ingela, output is passed to the dual-band PA that after amplification feeds the signal via a low pass filter to the antenna switch and further to the antenna. The transmit block consists of two differential high power transmit output buffers with controllable output power. The modulated transmit signal from the VCO buffer is amplified to a level suitable to drive the external power amplifier. The buffer outputs are of open collector type and must be terminated into a suitable load. Figure 3-7 shows a block diagram of the transmitter block.

Figure 3-7. Block diagram for the transmitter.

- 80 -

3. TECHNICAL BRIEF

B. Power Amplifier
The Power Amplifier (N1300) is intended for use in EGSM and DCS/PCS mobile equipment. It is a module with two parallel amplifier chains, with one chain for the EGSM transmitter section and one for the DCS/PCS transmitter section. Each chain amplifies the RF signal from the respective transmitter to the antenna. The power amplifier supports class 10. Band selection and the output power level of the RF amplifier are controlled by discrete signals Vband and Vapc respectively from the digital baseband controller ASIC.

Figure 3-8. Block diagram of the Power Amplifier with Two Parallel chains.

- 81 -

3. TECHNICAL BRIEF

3.8 WCDMA Mode
3.8.1 Receiver
The received RF signal on the antenna connector arrives via the antenna switch to the duplexer. The duplexer directs the signal to the LNA, which resides in Wopy (W-CDMA Receive ASIC) as every other active part of the radio receiver. The LNA has two different gain settings. From the output of the LNA, the signal is fed to the input of a RF SAW filter, and then appears at the differential output of the filter. The differential output of the RF SAW filter is connected to the differential mixer input, and the received signal is down-converted to a 190MHz IF frequency (with the RFLO signal) by the mixer. At 190MHz, the signal is filtered in a differential (input and output) IF SAW filter, with the approximate bandwidth of 4MHz, and then again the signal is fed to Wopy (W-CDMA Receive ASIC), this time to the differential IF input, which also has a LNA. From the 190MHz, the signal is mixed down to base-band I and Q which represented signals (using the IFLO signal). Finally the signals are filtered in low pass filters and amplified in base-band VGAs. The I and Q represented signals appear at the output of Wopy (W-CDMA Receive ASIC) as differential voltages. The large signal gain provided by the processing steps from the antenna down to base-band gives a DC offset at the outputs of Wopy (W-CDMA Receive ASIC). To eliminate this, there are DC-offset compensation loops included, one in the VGA of each of the I and the Q signals.

A. IFLO Section
The balanced IFLO signal from an external IFVCO drives the divider to provide qaudrature LO signals to the RxIF mixers. The LO buffers amplifies the signal to a suitable amplitude and DC level to drive the RxIF mixers.

Figure 3-9. Block diagram of the IFLO section.

- 82 -

3. TECHNICAL BRIEF

B. RFLO Section
The VCO is a fully integrated balanced LC oscillator with on-chip resonator. An on-chip varactor is used to control the frequency over the desired tuning range. A separate external voltage regulator supplies the VCO with power to avoid frequency pushing and up conversion of low frequency noise. A separate ground pin is also used as varactor ground reference to prevent DC voltage drop changes from affecting the VCO frequency. Via the serial interface, the VTUNE voltage can be set to VCC/2 to check the center frequency of the VCO. The PLL consists of a programmable prescaler with multiple division ratios and a phase and frequency detector with a charge pump with programmable output current. Channel frequency selection is set via the serial interface.

Figure 3-10. Block diagram of the RFLO section

- 83 -

Reference Section The reference block consists of a balanced oscillator and a buffer amplifier.3. TECHNICAL BRIEF C. . Block diagram of the Reference section. The crystal unit and the feedback capacitors are external. Figure 3-11.84 - . The current consumption when only the reference oscillator and the output buffer are activated must be kept to an absolute minimum.

the mixed-signal circuit ASIC). which adapts itself by means of a control loop so that the linearity of the PA is kept constant. are sent to the radio ASCI Wivi (WCDMA Transmitter ASIC) from the D/A converter in Wanda (W-CDMA digital base-band coprocessor ASIC). the signal is mixed to its final frequency (using the RFLO) and amplified in a differential output RF buffer with two different gain settings (high gain or low gain). . The second amplifier provides a 54dB gain range in 1 dB steps (54steps = 55 levels). and is then amplified in a stand-alone RF buffer.85 - . and a low-pass filter for removing the unwanted high frequency components from the baseband input waveform. The variable supply voltage is provided from the battery through a DC/DC converter and a signal linearity detector sits at the PA output. Variable Gain Amplifier (VGA) Comprising two cascaded variable gain amplifiers. In the PA the signal is amplified for the last time before leaving the radio. the so-called QVGA.3. The signal is then amplified in a VGA and filtered in an external filter (an LC filter). TECHNICAL BRIEF 3. the signal is filtered again in a SAW filter before it is fed to the PA (Power Amplifier). C. IQ-modulator The IQ-modulator receives the incoming I and Q analog baseband signals at baseband frequency and converts them to an intermediate frequency of 380MHz. After the RF buffer.2 Transmitter Analogue differential signals (currents). Reconstruction Filters The reconstruction filters consist of input buffers that provide the correct DC biasing for the preceding DAC in the digital baseband controller. The signals are filtered in a reconstruction filter and then modulated up to 380MHz (using the IFLO signal). After the PA.5/0.8.75dB. A. The first of these two amplifiers. which directs the transmit signal to the antenna connector via the antenna switch. the signal is sent through an isolator and through the duplexer. The filter inputs are adapted for use with a current-source type of input signal.25/0.25dB steps. enables fine-tuning of the transmitter by varying the gain in 0. which provides the control signal to the DC/DC converter. the VGA-together with the RF mixer. representing I and Q. The differential RF signal is fed into a SAW filter with a single ended output. and the error signal is used in a loop filter.controls the power of the transmitter. After filtering. The detected signal at the PA output is compared with a reference (supplied by the Vincenne. B. The PA has variable supply voltage. that is 0/0.

Figure 3-12. IF Band Bass Filter (IFBP) The IF filter suppresses spurious signals and eliminates unwanted frequency components generated in the IQ modulator and subsequently amplified in the VGA.3. Principle Schematic of the IFBP. The filter is tuned using an external RLC load as shown in Figure 3-12. . TECHNICAL BRIEF D.86 - .

3. The mixer can be switched between three different gain levels: high gain (HG). It should achieve a reduction of bias current from the nominal value of 17mA to 3mA (signal ended) in 7 steps. The buffer is of an open-collector design.25 dB steps over no less than 80dB. The RF buffer is used to drive an external PA stage. The LO buffer provides the buffering for either an internal LO signal generated within the internal RFPLL. or an external LO signal applied to the RFLO/RFLOBAR pins. The gain switching together with the VGA amplifier at IF will enable an output power control in 0. . medium gain (MG). TECHNICAL BRIEF E. The programmable bias in the high and mid-gain settings is specified as a reduction of bias current from the maximum bias condition. and low gain (LG). RF Mixer and Buffer The RF mixer converts the signal output from the IF BP filter from an intermediate frequency (IF) to the final radio frequency (RF). External DC blocking is necessary for the external LO signal.87 - . Figure 3-13. Block Diagram of RF Mixer and Buffer.

The module is fully matched to 50( for easy system integration and utilizes advanced GaAs HBT process technology. Power Amplifier The N1630(RF9266) is a high-power. Additionally.88 - .3. Block Diagram of W-CDMA power amplifier. The PA features an integrated RF power output detection network and is compatible with DC-DC converter operation in DC power management applications. a variable bias-current allows the idle current to be adjusted for optimum performance at a given RF output power. high-efficiency linear amplifier module targeting W-CDMA transmitter ASIC. Figure 3-14. TECHNICAL BRIEF F. .

The 13MHz is used as the reference. which is designed to be the reference frequency of the UE. They generate the Intermediate Frequency Local Oscillator (IFLO) and Radio Frequency Local Oscillator (RFLO) signals. The programmable divider makes the RF synthesizer cover the 2300~2360MHz band. The 13MHz clock is used as the reference. The IF synthesizer is in the Wivi (W-CDMA Transmitter ASIC). which is external. and the phase detector frequency is 200kHz. The synthesizers are controlled by Wanda (W-CDMA digital base-band coprocessor ASIC) via the serial bus to Wivi (W-CDMA Transmitter ASIC) and Wopy (W-CDMA Receive ASIC). which gives the radio a fixed duplex distance of 190MHz. an intermediate frequency (IF) synthesizer and a radio frequency (RF) synthesizer. TECHNICAL BRIEF 3. . The RF synthesizer is in the Wopy (W-CDMA Receive ASIC).8.3 Frequency Generation The Wopy (W-CDMA Receive ASIC) contains the active elements for a 13MHz VCXO. and the phase detector frequency is 1MHz.3. There are two synthesizers in the W-CDMA part of the radio. except for the loop filter. Both synthesizers are used in both the transmitter and the receiver. The IF VCO runs at 1520MHz given that the (programmable) reference divider is set to 13. except for the loop filter.89 - .

. Figure 3-15.90 - .Input buffer: A 13MHz input buffer with DC-biasing provided at source. TECHNICAL BRIEF A. .VCO: Operating on 1. On-chip varactor are used to tune the VCO frequency. the tuning voltage is set to Vcc/2. this is a fully integrated balanced LC oscillator with on-chip resonator.Prescaler . Block Diagram of Frequency Synthesizer Part(IF PLL). External DC blocking capacitors must be used on the IFLO/IFLOBAR signals. . IF PLL The IF LO frequency synthesis comprises the four following parts: .Phase-detector with charge pump For maintaining check on the VCO center frequency.3.52GHz which is 4times the TX-IF frequency (380MHz) and 8 times the RX-IF (190MHz).

91 - . Yes No Follow the keypad Trouble shooting guide Check the voltage.5 V VEXT1. VCORE (R2210) 1.8 V VDD_B (R1811) 2. TROUBLE SHOOTING 4.5 (N22 03 Pin#3) 1. Longer than 3 Seconds Keypad LED ON? No No Charge or change main battery Yes Follow the LCD Trouble shooting guide END key oper ates wel l? ONSWAn(C2621) level is low when END key press ed.5V VDIG (R2200) 2.4. TROUBLE SHOOTING 4.8V VMEM (R2201) 1.1 Power ON Trouble START The vol tage of main battery is higher than 3.2V ? Yes Press END key.8V VRTC (R2202) 1.8 V Yes The phone should work ONSWAn No Change main board N2000 C2621 .5V VDD_A (R1810) 2.

Top side > R1810 R1811 R2210 R2201 R2200 < Main Board .92 - .Bottom side > . TROUBLE SHOOTING Pin #3 R2202 N2203 < Main Board .4.

pin5) is 3.3V? Yes USBSENSE level is 2. TROUBLE SHOOTING 4.8V? Yes VUSB(R3103) is 3. pin1) is 5V? Yes Output power(N2204.3V? Yes Change main board No Resolder or change N2204 No Resolder R2232 or R2233 No Resolder R3103 USBSENSE N2204 R2232 R2233 R3103 .93 - .4.2 USB Trouble START (Measure during the state of USB module running) No Check host USB port or USB cable Input power(N2204.

.75V level) to VINCENNE. START Reconnect SIM card SIM work well? No Resolder X2300 on main PCB and check the contact between X2300 and SIM card Yes Finish SIM work well? No Change SIM card Yes Finish X2300 SIM work well? No Change main board Yes Finish . TROUBLE SHOOTING 4.8V/3V.MARITA generates SIM interface signals(2.3 SIM Detect Trouble • SIM control path .Vincenne converts SIM interface signals to 1.94 - .4.

START Press the keypad Keypad operates well? No Resolder X3200 on main board and CN962 on keypad Yes Finish Keypad operates well? No Change Keypad Yes Finish Keypad operates well? No Change main board Yes Finish Pin #54~#59 Pin # 2~#7 ONSWAn KEYIN0 KEYIN1 KEYIN2 KEYIN3 KEYIN4 1 60 Pin #45~#50 KEYOUT5 KEYOUT4 KEYOUT3 KEYOUT2 KEYOUT1 KEYOUT0 Pin #12~#17 KEYOUT5 KEYOUT4 KEYOUT3 KEYOUT2 KEYOUT1 KEYOUT0 30 1 60 ONSWAn KEYIN0 KEYIN1 KEYIN2 KEYIN3 KEYIN4 X3200 CN962 30 31 31 .4 Keypad Trouble • Keypad signals go to MARITA and VINCENNE through board-to-board connector.95 - . TROUBLE SHOOTING 4.4.

96 - .4.5 Camera Trouble Camera control signals are generated by Marita . TROUBLE SHOOTING 4.

4. TROUBLE SHOOTING Camera control signals are generated by Marita .97 - .

TROUBLE SHOOTING 4. .98 - .4.6 Main LCD Trouble LCD control signals are generated by Marita.

99 - . TROUBLE SHOOTING 4.4.7 Sub LCD Trouble .

TROUBLE SHOOTING 4.4.8 Keypad Backlight Trouble .100 - .

4. TROUBLE SHOOTING .101 - .

TROUBLE SHOOTING 4.9 Folder ON/OFF Trouble .4.102 - .

TROUBLE SHOOTING VCAM R3206 100K CAMERA_DET N3200 A3212ELH 1 VDD 3 GND OUT 2 C3204 0.4.1u C3205 10p Be sure that magnet is here .103 - .

4. TROUBLE SHOOTING 4.10 Camera Detection Trouble .104 - .

4.105 - . TROUBLE SHOOTING .

106 - .4.11 Camera Flash Trouble . TROUBLE SHOOTING 4.

TROUBLE SHOOTING .107 - .4.

4. L. TROUBLE SHOOTING 4. LCD Module -> • 6. X3200 on main board -> • 3.108 - . CN963 on key PCB -> • 5. .12 Audio Trouble Shooting A. C along the corresponding path before every step. Receiver • Signals to the receiver – Receiver signals are generated at Vincenne • BEARP. Receiver • Note : It is recommanded that engineer should check the soldering of R. BEARM – Receiver path : • 1. CN962 on key PCB -> • 4. Vincenne (BEARP. BEARM) -> • 2.

109 - . TROUBLE SHOOTING START Connect the phone to network Equipment and setup call Setup 1KHz tone out NO 1 Does the sine wave appear at R2619 ? Change the m ain board YES 2 Does the sine wave appear at Num ber 36.4. 37 pin in the key B' d CN963? NO Change the Key boar d YES 3 Does the sine wave appear at EAR(+) PAD in LCD Module? NO Change the LCD module YES 3 Is the soldering o t the receiv er OK? NO Resolder R eceiver YES Can you hear sine wave out of the receiv er ? NO Change the Receiver YES END .

TROUBLE SHOOTING 1 R2619 2 Pin 36.110 - . 37 40 1 3 21 CN963 20 .4.

111 - .4. TROUBLE SHOOTING 1 2 Measured 1khz Sine Wave Signal 3 Measured 1khz Sine Wave Signal .

112 - . TROUBLE SHOOTING B. MP3. C along the corresponding path before every step. CN963 on key PCB -> • 6. Speaker • Note : It is recommanded that engineer should check the soldering of R.4. Midi. N2601(Audio Amp) on main board -> • 5. N2603(ADG) on main board -> • 4. Speaker (Voice Loud Speaker. Vincenne (BEARP) -> • 2. L. C2604 on main board -> • 3. LCD Module -> • 7. . Key Tone) • Signals to the speaker – Speaker signals are generated at Vincenne • BEARP – Speaker path : • 1.

TROUBLE SHOOTING START Connect the phone to network Equipment and setup call Setup 1KHz tone out NO 1 Does the sine wave appear at C2604 ? Change the main board YES 2 Does the sine wave appear at R2607 ? NO Resolder or change N2603 YES 3 Does the sine wave appear at R2621 ? NO Change the main board YES NO 4 Does the sine wave appear at number 4 pin in key B' d CN963 ? Change the key B'd YES NO 5 Does the sine wave appear at spk(+) pad in LCD module ? Change t he LCD Module YES NO Can you hear sine wave out of the receiv er ? Change the Speaker YES END .113 - .4.

114 - .4. TROUBLE SHOOTING 1 C2604 3 R2621 2 R2607 N2603 4 Pin 4 40 1 5 21 CN963 20 .

115 - .4. TROUBLE SHOOTING 5 Measured 1khz Sine Wave Signal .

MICIN signals to ABB ( Vincenne ) • Check Points – Microphone bias – Audio signal level of the microphone – Soldering of components • Signal from the mic – MIC -> – N2602(TJATTE2) on main board -> – C2615 on main board -> – Vincenne . Microphone (Voice call. MICIP.116 - . Voice Recorder. TROUBLE SHOOTING C. Video Recorder) • Microphone Signal Flow – MIC is enable by MIC Bias – MICBAS.4.

C2617.4V ? No Check the signal level at C2615 at the putti ng Audio signal in MIC Yes Yes A few hundred of m V of the signal measured ? Change t he MIC Yes Change the main B'd No 3 Resolder C2615.4. chage the main B' d Yes No Does it work p roperly ? YES END . If fail again.117 - . C2616 and try again. TROUBLE SHOOTING START Check the MIC b ias level at the pad of MIC+(X2603) 2 1 Is the level o f M IC+ AND MIC2.

4.118 - . TROUBLE SHOOTING 1 C2616 C2617 2 C2615 3 .

119 - . TROUBLE SHOOTING 2 Measured Some Noise Signal .4.

5Volt ? NO YES YES YES 2 Does the level of R2613 over 2. Does the Headset ico n display on the main LCD? NO Does the level of R3381 under 0. Video Telephony.R3303.4. And try ag ain fr om the start 5 Does the sine wave appear at C3268.C2619 ? Change the main B'd N0 4 YES Resolde r R2613. Headset Receiver (Voice call. TROUBLE SHOOTING D.0Vo lt ? NO 3 Does the sine wave appear at C2611.120 - .C3269 ? NO Change the main B'd YES 6 Resolder X2602 Pins or change the Head set Can you hear sine wave out of the re ceiv er ? NO Change the main Bíd YES END . MP3) START Connect the phone to network Equipment and setup call Setup 1KHz tone out 1 Insert Head set.R3397 R3381.

R3397 and try again.0Vo lt ? 5 Check the signal level at R3397 at the putting Audio signal in MIC Change the main B'd N0 4 Resolde r R2613. Change t he m ain B' d YES Change the main B'd NO Does it work p roperly ?? Try again from the start YES END . If fail again.121 - .5Volt ? YES YES 2 YES Does the level of R2613 over 2. TROUBLE SHOOTING E. Video Telephony) START 1 Insert Head set.4. Headset MIC(Voice call.R3397 And try again from the start 8 A few hundred of m V NO 7 of the signal measured at C2612 ? Resolder C2613. Does t he Headset ico n display on the main LCD? NO NO Does the level of R3397 under 0.

TROUBLE SHOOTING 1 R3381 6 X2602 8 C2610 4 C2612 7 2 3 R2613 5 C2619 C2611 R3397 C2613 8 .122 - .4.

Check the battery .Charging current path .Control the charging current by AB2000(Vincenne) .13 Charger Trouble Shooting Figure.Battery • Trouble shooting setup . 13. Main Battery Charging Path • Charging Procedure .123 - . TROUBLE SHOOTING 4.Connect TA and battery to the phone • Trouble Shooting Procedure .Charging current flows into the battery • Check Point .Check the charger connecter .Connection of TA .4.Connecting TA and Charger Detection .Check the Charging current Path .

4.Charging .124 - . TROUBLE SHOOTING start ① Check the pin and battery connect terminals of I/O connector Connection OK? NO Change I / O connector YES ② NO I s the TA voltage 5.2V? Change TA YES ③ I s it charging properly after changing Q2201? YES END NO Change t he board Figure. 14. Trouble Shooting .

125 - . Main Board .4.I/O connector and FET . 15. TROUBLE SHOOTING ③ ② ① Figure.

TROUBLE SHOOTING 4.14 RF Component N1331 N1330 Z1100 Z1110 Z1420 Z1400 N1620 B1501 Z1500 N1700 N1400 N1101 B1770 Figure 4-1.4. RF component (Top) Reference B1501 B1770 N1101 N1330 N1331 N1400 N1620 Description Temperature Sensor Crystal GSM ADC GSM TX Balun DCS TX Balun WCDMA RX IC DC/DC Convertor Reference N1700 Z1100 Z1110 Z1400 Z1420 Z1500 Description WCDMA TX IC DCS RX SAW GSM RX SAW WCDMA RX RF SAW WCDMA RX IF SAW WCDMA TX RF SAW .126 - .

SW Module Duplexer GSM PAM WCDMA PAM Reference N1650 N1850 V1001 W1001 Description Isolator Regulator Transistor Test Connector .4. TROUBLE SHOOTING W1001 N1002 N1650 N1000 N1630 V1001 N1850 N1300 Figure 4-2.127 - . RF component (Bottom) Reference N1000 N1002 N1300 N1630 Description Ant.

62. 9750 (Uplink) Ch. P. Check VCXO Block 3. Check GSM Block Redownload SW.4.L. -60dBm setting 5. Check WCDMA Block Agillent 8960 : Test mode(GSM) Ch. 10700 (Downlink) 4. 62.15 Procedure to check start Oscilloscope setting 1.128 - . TROUBLE SHOOTING 4. 7 level setting Ch. Check Ant. Cal . Check Power Source Block 2. SW Module Agillent 8960 : Test mode(WCDMA) Ch.

Common Source Block(Bottom) .16 Checking Common Power Source Block Figure 4-3. TROUBLE SHOOTING 4.4.129 - .

Power Source Block 5 No 3.7V OK ? Yes Short? Yes Change the Board Check (C3215 & R2215) See The Step 2 Check Soldering (R2215 & R2216) I n Power Source Block in Block to check inner line connection From R1805 to R2215 .130 - .16.8 Figure 4-4.2.4.1 Step 1 Check VBATI (R1850) LP39 81 I LD. Regulator Block 1 R2216 R2215 Check Point ( C3215 ) Step 1 Check Point (C3215) in Power Source Block 5 To Check Power source to Check if main power source input or not Check Point (R2215) in Power Source Block 5 To Check Power source Figure 4-5.7V OK ? Yes Check Soldering (C3215) Yes No Resoldering Change the Board No No 3. TROUBLE SHOOTING 4.

7V OK ? Yes See The Step 3 Check (R2215 & R1805) in Block 1.16.2 Step 2 Step 2 Check VBATI (R1850) in Regulator Block 1 to Check if main power source input or not No 3. TROUBLE SHOOTING 4. 5 to check inner line connection From R1850 to R2215 No Short? Yes Change the Board Check Soldering (R2215 & R2216) In Power Source Block .131 - .4.

3 Step 3 VBATI ( R1326) GSM PAM L1 300 Figure 4-6. TROUBLE SHOOTING 4. 5 to check inner line connection From L1300 to R2215 Change L1300 Change the Board .16.4.132 - .7V OK ? Short? Yes Yes Check Soldering (R2215 & R2216) In Power Source Block No Check L1300 & R1326 inner Line connection Short? Change the Board Yes Check (L1300 & R2215) in Block 2. GSM PAM Block 2 Step 3 Check VBATI (R1326) in GSM PAM Block 2 to Check if main power source input or not Yes 3.7V OK ? See The Step 4 No No No Check L1300 to check if power source input or not 3.

16. PAM-Power Source .4.4 Step 4 VBATI (R163 1) WCDMA PAM Figure 4-7. WCDMA PAM Block 3 R22 16 Check Po int ( C32 15 ) R22 15 Figure 4-7-1.133 - . TROUBLE SHOOTING 4.

4. TROUBLE SHOOTING Step 4 Check R1631 in WCDMA PAM block No 3.134 - .7V OK ? Yes See the Next Page No Shor t? Yes Change the Board Check Soldering (R2215 & R2216) In Power Source Block .

75V OK ? Chec k Point VCCB (R181 1) Yes Change the Board Before Change.75V OK ? Check Poin t VCCA(R1810) Yes No 2.135 - .7u C1802 10u 2012 Vincenne (N2000) VDD_B VCCB Wopy (N1400) No 2.4. Check soldering Common Input Power is OK See The Next Part . TROUBLE SHOOTING VCCB (R 181 1) VCCA (R 181 0) Figure 4-8. Power for Radio ASIC Ingela (N1100) R1810 VDD_A VCCA 0 R1811 0 C1810 10u 2012 C1811 4.

8V OK ? Yes No Point High ? Yes No Change the Board Check EX TLOD Point . Regular Circuit Diagram or Check Poin t . 2. Regulator Block Figure 4-10. TROUBLE SHOOTING 4. or (R1825) (R1826) To Check Reg ulator Out put Vol tage .136 - .5 Checking Regular Part LP3981ILD-2.4.16. To Check regulator e nable signal Regulator Circuit is OK.8 Reg ulat or V_ wi vi_B (N1700) V_ wi vi_A (N1700) EXTLDO ( R1851) Figure 4-9. See the next Page Change The Regulator .

17 Checking VCXO Block The reference frequency (13MHz) from B1770 (Crystal) is used WCDMA TX part. TROUBLE SHOOTING 4. Check 3 Check 4 Check 1 Chec k 2 Figure 4-12. GSM part and BB part. Connection for Checking VCXO Block .4.137 - . Top Place Figure 4-13. Therefore you have to check below 4 point.

Schematic of the Crystal Part Figure 4-16.4.138 - . you can skip check 1. Figure 4-14.3 . TROUBLE SHOOTING Check 1. 13MHz at B1770. Test Point (Crystal Part) Figure 4-15. Crystal part If you already check this crystal part.

TROUBLE SHOOTING Check 2.3 13MHz at WCDMA TX part and GSM part N1770. Test point (13MHz at TX Part) Figure 4-18.K9 Figure 4-17.K9 .4.C1 N1100.139 - .B1 N1770.B1 and N1100. 13MHz at N1770.

4.C1 . Test Point (13MHz at BB Part) Figure 4-20.C1 Figure 4-19. TROUBLE SHOOTING Check 4. Schematic (13MHz at BB Part) Figure 4-21. 13MHz at N1400.140 - . 13MHz at BB part N1400.

4. TROUBLE SHOOTING

- 141 -

4. TROUBLE SHOOTING

4.18 Checking Ant. SW Module Block

ANTSW2 ANT SW 1 ANTSW0 ANTSW3

LMSP -00 64 (N1 000 )

V10 01

VCCB (C101 0)

Figure 4-20. Antenna Switch Block(Bottom)

- 142 -

4. TROUBLE SHOOTING

4.19 Checking Antenna Switch Block input logic
4.19.1 Mode Logic by TP Command

EGSM Rx
MODE=0 SWRX=64 ,10 24 ,2

EGSM Tx
MODE=0 SWTX=1, 64, 7,1 024 ,1

Low ANTSW1 W1 Low ANTSW2 W2 Low ANTSW3 W3

Low Low High Hi

DCS Rx
MODE=2 SWRX=699,1024,2

DCS Tx
MODE=2 SWTX=1,699,0,1024, 1

High Hi ANTSW1 W1 High Hi ANTSW2 W2 Low ANTSW3 W3

Low High Hi Low

- 143 -

4. TROUBLE SHOOTING

WCDMA Mode
MODE=4 WTXC=9750,0,1, 0 SYCT=1 07 00 TXGN=1,43

Low ANTSW1 Low ANTSW2 Low ANTSW3

Band EGSM Tx EGSM Rx DCS Tx DCS Rx WCDMA

ANTSW0 H H H H H

ANTSW1 L L H L L

ANTSW2 L L H H L

ANTSW3 H L L L L

Table 4-1. Antenna Switch Module Logic

- 144 -

4. TROUBLE SHOOTING

4.19.2 Checking Switch Block power source
❈ Before Checking this part, must check common power source (through Vincenne) part

TP Command
MODE=0 SWRX= 64,1024,2
No

C heck Soldering . It is necessary to c heck shor t co nditi on. Using Tester, Che ck 4 resistor ANTSW0(R1 003),ANTSW1( R10 04), ANTSW2(R1 005),ANTSW3( R10 06)

Open?
Yes

Check soldering (R1003)
No No

High?
Check A NTSW0(R1003) To check Switch i np ut power source.
Yes

OK?
Yes

Resoldering

Check each mode by TP command

Change the Board

- 145 -

4. 1 part Check OK? Yes No Try 4.146 - . 10 24 . TROUBLE SHOOTING A. EGSM Rx Mode EGSM Rx MODE=0 SWRX= 64.1 part See the Next mode (EGSM Tx Mode) Change the Board . EGSM Rx Mode EGSM Rx Logic OK? Yes No 4.4.4.2 Low ANTSW1 Low ANTSW2 Low ANTSW3 Figure 4-21.

1 Low ANTSW1 Low ANTSW2 High ANTSW3 Figure 4-22.4.1 part Check OK? No Try 4.147 - . 102 4.4.6 4.1 part Yes See the Next mode (DCS Tx Mode) ANTSW1 : Low ANTSW2 : Low ANTSW3 : Low Yes No Change the Board Change V1001 . TROUBLE SHOOTING B. 7. EGSM Tx Mode EGSM Tx Logic OK? Yes No 4.4. EGSM Tx Mode EGSM Tx MODE=0 SWTX= 1.

2 High ANTSW1 High ANTSW2 Low ANTSW3 Figure 4-23.4. DCS Rx Mode DCS Rx MODE= 2 SWRX=6 99 .4.1 part See the Next mode ( DCS Tx Mode) Change the Board . DCS Rx Mode DCS Rx Logic OK? Yes No 4. 1 p ar t Check OK? Yes No Try 4.4. TROUBLE SHOOTING C.148 - .1 02 4.

6 99 . TROUBLE SHOOTING D.0 .4. 1 p ar t Check OK? Yes No Try 4.4. DCS Tx Mode DCS Tx Logic OK? Yes No 4.149 - .4. DCS Tx Mode DCS Tx MODE=2 SWTX= 1.1 Low ANTSW1 ANTSW2 ANTSW3 High Low Figure 4-24.1 part WCDMA Mode Change the Board .1 02 4.

4. WCDMA Mode WCDMA Mode MODE=4 WTXC=9 75 0.4.1.1 part Input Signal and Power to Antenna Switch Block is OK. 1 p ar t Check OK? Yes No Try 4. See the Next P age Change the Board .4 3 Low ANTSW1 Low ANTSW2 Low ANTSW3 Figure 4-25. WCDMA Mode WCDMA Logic OK? Yes No 4.4. 0. 0 SYCT= 107 00 TXGN=1. TROUBLE SHOOTING E.150 - .

SW Module ⑤ ③ ① ⑥ 3. Check RF Tx Level 5. Check Ant. Check PAM Block 6.20 Checking WCDMA Block start ⑦ 1. C heck Rx IQ ② ④ 7. Chec k Contr ol Signal 4.4. TROUBLE SHOOTING 4. C heck RF Rx Level Redo wnload SW. Check VCXO Block 2.151 - . Cal .

2 Checking Ant.20.4.20.1 Checking Refer to 4.4 4. clk. TROUBLE SHOOTING 4.3 Checking Control Signal First of all.152 - .5 4. you have to check control signal. Test Point (Control Signal) Figure 4-29.20. strobe) TP 1402(CLK) TP 1402(DATA) TP 140 2(STROBE) Figure 4-28. SW module Refer to 4. Schematic (Control Signal) . (data.

TROUBLE SHOOTING Figure 4-30.153 - .4. Connection for Checking Control Signal .

154 - . Control signal . TROUBLE SHOOTING TP1403( STRO BE) TP1401(DATA) TP1402( CLK) TP1403( STRO BE) TP1401(DATA) TP1402( CLK) Figure 4-30.4.

155 - .2 Figure 4-31. TROUBLE SHOOTING 4.20.4 Checking RF TX Level Check 3 N1002.4.Ant Check 1 W1001 Check 2 N1000.Out Check 6 N1630. Test Point (RF TX Level) .In Check 4 N1650.21 Check 7 Z1500.8 Check 5 N1650.

TROUBLE SHOOTING Figure 4-32.4.156 - . Connection for Checking RF TX Level .

157 - . TROUBLE SHOOTING To verify that the phone fulfils requirements on maximum output power.4. .

5 Checking PAM Block Rosalie VBATI (R162 9) WD CDCREF (R1621) WPAREF (R 1617) WCDMA PAM(N1630) Wivi in put (R1605 ) WPA( R1630) fro m Rosalie Step1: Check PAM(N1630) control signal from N2000 Step2: Check PAM(N1630) control signal from N1620 ❈ Before Checking this part .20.2 Common power source(Battery Direct) part . must check 4. TROUBLE SHOOTING 4.4.158 - .

1.159 - .0.0 -Syct=10700 -Txgn=1.43 -TFTI=10700 Step1: Check PAM control signal from N2000 Mean Value Check R16 17 To Check PAM control signal from Vi nce nne (WP A REF) No 2. Check soldering(R1617) See the Step 2 . TROUBLE SHOOTING TP Command -mode =4 -Wtxc=9750.4.4V ? Yes Change the Board Before Change board.

1. TROUBLE SHOOTING TP Command -mode =4 -Wtxc=9750.0 -Syct=10700 -Txgn=1.0. check soldering VBATI(R1631) . Check soldering(R1621) Mean Value Change the DC/DC Converter Before Change board.160 - .4.43 -TFTI=10700 Step2: Check PAM control signal from DC/DC converter(N1620) Check R1603 To Check PAM VCC BIAS fr om DC/ DC conver tor (V CC WPA ) Mean Value No 2.5V ? Yes No Change the Board Before Change board.4V ? Yes Check The DC/ DC convertor(N1620) Part Change the PAM Mean Value Check R1621 To Check DC /DC conver tor control si gnal From Vincen ne(N2000) (WDCDCREF) 2.

TROUBLE SHOOTING TP Command -mode =4 .1.4.5V ? Check the Vincenne to WCDMA PAM Signal line Check R1617 To Check PAM control signal from Vincenne(N2000) (WPAREF) Check R1603 To Check PAM VCC BIAS from DC/DC convertor(N1620) (VCCWPA) Yes No 3.0.Wtxc=9750.Txgn=1.5V ? No Change the Rosaili Yes Change The PAM (N1630) .Syct=10700 .43 -TFTI=10700 No 23dBm ? Level < -10 dBm? No Check Duplex output (C1012) Yes To Check PAM output WCDMA PAM i s OK See t he Next page Download the SW & Calibrate Yes Level >2 dBm No Check the WCDMA RF Tx Chip(Wivi) Check R1605 To Check PAM Input level Yes No 2.4V ? 2.161 - .0 .

4. TROUBLE SHOOTING

4.20.6 Checking RX I,Q
To verify the RX path you have to check the pk-pk level and the shape of the RX I,Q.

N1400.A7 (RXQA) N1400.A8 (RXQB) N1400.A9 (RXIA) N1400.A10 (RXIB)

Figure 4-33. WCDMA RF RX IC (Top)

Figure 4-34. RX I,Q signal (CW:2142MHz)

Figure 4-35. RX I,Q signal (CW:2141MHz)

- 162 -

4. TROUBLE SHOOTING

Figure 4-36. RX I, Q signal

- 163 -

4. TROUBLE SHOOTING

4.20.7 Checking RX Level

Check 2 N1400.H1

Check 3 N1400.B1

Checkt 1 N1002.Ant

Figure 4-37. Peak level at N1400.B1

Figure 4-38. Connection for Checking RX Level

- 164 -

4. TROUBLE SHOOTING

- 165 -

4. TROUBLE SHOOTING

4.21 Checking GSM Block

start


1. Check Regulator Circuit

2. Check VCXO Block

② ④
3. Check Ant. SW Modu le

4. Check Control Signal


5. Check RF Tx Path


6. Check RF Rx Path

Redow nload SW, Cal

- 166 -

You can skip this test.21. 4. . IF you already check this point while Checking Antenna Switch Block input logic. IF you already check this point while Checking Common Power Source Block.167 - .3 Checking Ant.2 Checking VCXO Block Refer to chapter 4. You can skip this test.3 Checking Common Power Source Block.4. TROUBLE SHOOTING 4. 4.21.1 Checking Regulator Circuit Refer to chapter 4. SW Module Refer to chapter 4.6 Checking Antenna Switch Block input logic. You can skip this test. IF you already check this point while Checking VCXO Block.21.4 Checking VCXO Block.

TROUBLE SHOOTING 4.168 - .4.1 VCCA (C1330) VC CA (L1200) LPFblock Vtune (C1223) VCCA (L1120) VCCA (L1202) TXON (R1333) RADSTR (TP1203) RADDAT (TP1202) RADCLK (TP1201) RADSTR RADCLK RADDAT TXON Vtune Figure 4-39. GSM RF Control signal .1024.64.7.21.4 Checking Control Signal Test Program Script MODE=0 SWTX=1.

169 - .L1200. Check voltage of L1120. TROUBLE SHOOTING Check TP1201.R1335) Yes Control signal is OK. Yes Resoldering LPF block .TP1202. Refer to left side of Figure 4-39 No Simiar? Short? Check the short status between TP1201~TP1203 No Redownload SW Yes Yes Change the board Check R1333.4.L1200.7V? No Resoldering VCCA block (L1120. Check if there is any major difference.L1202.R1335 Refer to right side of Figure 4-39 No Similar? VCCA= 2. See next page to check.L1202.TP1203 Check if there is any major difference.C1223.

5 Checking RF Tx Path A. TROUBLE SHOOTING 4.4.170 - . GSM/DCS Tx Path Level .21. GSM Tx path Level Figure 4-40.

171 - . Test Point of GSM/DCS Tx path .4. TROUBLE SHOOTING Figure 4-41.

172 - . See chapter 4. TROUBLE SHOOTING B.0. Refer to Figure 4-42.1024.5.1 v.4.6 to check Rx path . Oscilloscope setting Check GSM/DCS output power at ①. Check if there is any Major difference.699.8.64. GSM Tx MODE=0 SWTX=1. GSM Tx Output Level Check Figure 4-42.1 2.1024. GSM Tx Level at 1 Test Program Script 1. GSM > 32dBm DCS > 29dBm Yes No Similar? See next page to check Tx path GSM/DCSTx Path OK. DCS Tx MODE=2 SWTX=1. Agilent 8960 setting : GSM BCH+TCH m ode v.

GSM RF Transceiver IN/OUT Signal Check ④ DCS Tx (R1341) N1331 N1330 MODA (R1213) MODB (R1212) MODC (R1211) MODD (R1210) MODA GSM Tx (L1330) DCS Tx (L1331) GSM T x (R1338) ② ③ MODB Figure 4-43. Yes Resoldering MODE block (R1210. GSM/DCS >.R1211.7dBm No Resoldering Tx Balun GSM : N1330 DCS : N1331 Yes See next page to check Tx path .173 - . TROUBLE SHOOTING C. GSM/ DCS >.4.5dBm No Redownload SW Yes Check GSM/DCS Tx Balun output power at ④ . Refer to right side of Figure 4-43.R1213) Check GSM RF Transceiver Output power at ③ . GSM Tx MODE signal Check Mode(A/B/C/D)signal at ②. Simiar? No Check if there is any Major difference.R1212.

5 V ? Resoldering APC block Ye s Check GSM/DCS PAM output power at ⑤ .4. Refer to Figure 4-44. V apc > 1 . See Next p age t o check . GSM/DCS Tx control signal Check Vapc level. G SM: > 23dBm D C S: > 20dBm No Changing GSM PAM ( N1 3 00 ) Ye s GSM Tx Pat h OK.174 - . GSM PAM Check GSM Tx (C1341) DCS Tx (C1352) APC block Vapc (C1327) TXON TXON Vapc (GS M) Vapc (DCS) Figure 4-44. TROUBLE SHOOTING D. Check if there is any Major No difference.

6 Checking RF Rx Path Antenna GSM : -50d Bm DCS : . GSM Rx path Level GSM Rx : Ch64.:2 0 0m Vpp / QQ + GSM/ DCS I / Q e l Lev I / Q 5 Vpp :2. -50dBm.A. GSM/DCS Rx Path Level GSM RX SAW B7 705 . TROUBLE SHOOTING Pre s c al er .5 dBm B7 714 ADC Mobile Switch KMS. -50dBm. 4.50 dBm DCS RX SAW DCS : . CW GSM/ DCS I / Q e l Lev I+ I-/ / .5 dBm ∏ Lo o p fi lt e r Clk GSM Herta PD Antenna SW module LMSP. CW DCS Rx : Ch699.175 - GSM : .50 7 ∏ ADC GSM Ingela Figure 4-45.51 .21.51 .006 4 4.

DCS Rx MODE=2 SWRX=699.8MHz) v Oscilloscope Setting .4.1024.1024.2 v Agilent 8960 Setting CW Mode GSM : -50dBm@Ch65(948MHz) DCS : -50dBm@Ch700(1842. GSM Rx MODE=0 SWRX=64.176 - .2 2. TROUBLE SHOOTING Z1110 Z1100 ③ ③ N1100 ② N1101 ① Test Program Script 1.

177 - .4. Herta IQ data and DCLK QRB QRA IRB IRA Figure 4-47. GSM I/Q Signal Check Qdata DCLK Idata (TP1142) (TP1141) (TP1143) QRB (R1103) QRA (R1104) IRB (R1105) IRA (R1106) VDIG_HERTA R1150 I Data Q Data DCLK Figure 4-46. Ingela IQ signal . TROUBLE SHOOTING B.

TROUBLE SHOOTING QRB QRA Figure 4-48.4. .L1200.7V? A= Yes Redownload SW No Reso ldering R1150 Check GSM/DCS Rx IQ signal 2. Refer to Figure 4-46.R1335) Check GSM/DCS Rx IQ signal level at 2. Check if there is any Major difference. Refer to Figure 4-48. Ingela IQ signal Check GSM/DCS Rx IQ data at 1.178 - .L1202. Refer to Figure 4-47. Similar? Yes No Resoldering VCCA block (L1120. No Similar? Yes VDIG_HERT 2. IQ signal : 200mV ? Yes See next page to check Rx path GSMRx path OK.

GSM RF Level Check Z1100 ③ ③ Z1110 Figure 4-49.4.5dBm DCS:-51.179 - . .5dBm Yes No Change Ant. TROUBLE SHOOTING C. GSM:-51. GSM/DCS Rx Path v Agilent 8960 Setting CW Mode GSM : -50dBm@Ch65(948MHz) DCS : -50dBm@Ch700(1842. SW module (N1000) GSM Rx path OK.8MHz) Check GSM/DCS Rx signal level at ③ .

BLOCK DIAGRAM 5. W1001 Is olator N1650 V CO UMT S Receiver N1400( Wopy ) V CO T ank UMT S T ransm itter DC DC N1620 Switc h N1000 N1700( Wivi) XO D2006 Wan da UMT S IF Filter Z1420 UMTS PAM N1630 UMTS TX Filter Z1500 V arac tor V 1770 Crys tal .1 GSM & WCDMA RF Block UMTS UMT S RF Filter Z1400 Du plex er N1002 An tenna C2.180 - . RF Block Diagram .5.13M B 1770 GSM DCS Rx Filter Z 1100 GSM RX Filter Z 1110 GSM PAM N1300 DCS Balun N1331 GSM Balun N1330 ÷ ÷ ADC ADC GSM ADC N1101 M arita D2000 PD ÷ GSM T rans ceiver N 1100( Ingela) Loop fi l ter Clk Pre sc aler Figure 5-1. BLOCK DIAGRAM 5.6122 T es t Conn.

Name N1000 W1001 Part Name LMSP-0064 KMS-507 TSX-8A DFYK61G95LBNCB LZT-108- Function Switch Test Connector Crystal Duplexer Receiver RX RF Filter RX IF Filter DC/DC PAM Isolator Transmitter Comment Band select Calibration. RF Block Component (INGELA) CX77304 LDB21897M15C LDB211G8020C POP-101-3035 Modem PAM GSM Balun DCS Balun GSM/DCS Dual TX TX B7714 B7705 LZT-108-5325 Transceiver TRX Baseband DCS RX Filter GSM RX Filter Direct Conversion Direct Conversion SX-S205B ROP-101-3033 TX RF Filter Analog 5323(WOPY) LK20A TMX-M453 MAX1820ZEBC RF9266 CEO0401G95DCB LZT-108- .5. BLOCK DIAGRAM Block Ref.181 - . etc Reference –13M TRX RX RX RX TX TX TX TX TX TRX Common B1770 N1002 N1400 Z1400 Z1420 WCDMA N1620 N1630 N1650 N1700 5322(WIVI) Z1500 D2006 (WANDA) Z1100 Z1110 N1100 GSM N1300 N1330 N1331 D2000 (MARITA) Table 5-1.

RF RX I/ Q_WR WR IFLO 13M 13 _R Duplex er N1002 W.PAM N1630 W ivi Z1700 I/ Q_WT HSSL SSL (2 bit) Switch N1000 G .5. Re W opy N1400 Bus Bu _W 32k RTC W.2 Interface Diagram 13M _M CLK M _M C Crystal B1770 13 13M Ref. Interface Diagram 1 .RF RX I/ Q_GA I/ Q_GD Marita D2000 RXON RX G/ D. BLOCK DIAGRAM 5.PA C trl V CXO Ctrl C Pctl Pc Vincenne N2000 Bus Bu .PA Ctrl G .RF T X G.Band SEL SW C trl DCLK DC Herta N1101 G/ D.PAM N1300 TXON TX Ingela N1100 DIRM OD( 4bi t) DI Bus Bu _G W.G/ W PA Figure 5-2.182 - .RF TX W anda D2006 RFLO RF W .

5.183 - . BLOCK DIAGRAM Function Block Name 13M_MCLK Schematic_Signal Name MCLK XOOA/XOOB RFLO/RFLOBAR IFLO/IFLOBAR RTCCLK WCDMA_RX WCDMA_TX GSM_RX/DCS_RX GSM_TXDCS_TX RXIA/RXIB/RXQA/RXQB TXIA/TXIB/TXQA/TXQB IRA/IRB/QRA/QRB IDATA/QDATA ANTSW0/1/2/3 BSEL0 WPAREF PAREG PCTL VCXOCONT RXON TXON WDAT/WCLK/WSTR RADDAT/RADCLK/RADSTR DACDAT/DACCLK/DACSTR Function Main clock to BB Ref for PLL RF LO Generation IF LO Generation Real Time RX RF signal TX RF signal RX RF signal RX RF signal WCDMA RXIQ WCDMA TXIQ GSM RX analog GSM RX digital Band/System switch GSM/DCS switch PAM Ref. Interface Signal Block . Bias Power control TX power control AFC RX block ON TX block ON PLL program PLL program TX Gain program 13M 13M_R RFLO LO IFLO 32K 32K W-RF RX W-RF TX G/D-RF RX G/D-RF TX Signal I/Q_WR I/Q_WT I/Q_GA I/Q_GD SW Ctrl G-Band SEL W-PA Ctrl Control G-PA Ctrl Pctl VCXO Ctrl RXON TXON Bus_W Bus Bus_G Bus-G/WPA Table 5-2.

. O n/Off for S wi tch/ GS M I2C D A T I2C C LK MCLK R ES ETB QDATA IDATA DCLK RXON GSM / GPRS STROB E Ingela / Herta DATA CLK BSEL MO D [D.184 - .A] P ULS ES KIP (GP IO03) PCTL TXON (Combine to Vincenne ) CLKREQ VLOOP (GPA2) PAS ENS E+ PAS ENS EPAREG / IO UT Commo n M arita GSM / GPRS PAM UM TS Commo n BSEL PAS ENS E+ PAS ENS EPAREG DATA CLK STROB E ADCS TR RTEMP IRA / B QRA /B REFO N/XO OO N WRFLO OP MCLK VCXO CO NT IIN / IINB AR QIN / Q INBAR WIFLOOP WDCD C R EF WPA R EF WPOW ERS ENS E Vincenne Radi o_D A T Radi o_CLK Radi o_STR Wa nda AD_STR (Combine to Vincen ne / Marita) IRA / B QRA /B IIN / IINB AR QIN / Q INBAR WRFLO OP (GP A4) VCXO CO NT (DAC03) WDCD C R EF (DAC01) WPA R EF (D A C02) WPOW ERS ENS E (GP A3) WIFLOOP (GPA6) EXTLDO RTEMP (GP A0) UM TS Wopy Vincenne UM TS Wiv i UM TS PAM CLK (to Vincenne / W anda) MCLK (to Vince nne / Wan da / Mari ta) Figure 5-3. BLOCK DIAGRAM 5.3 Detailed Interface Signal RF ANTSW [3.5.A] P ULS ES KIP PCTL TXON VLOOP Baseband ANTS W [3. Interface Diagram 2 ..0] Reg...0] I2CSDA (Combi ne to Vince nne) I2CSCL (Combine to Vince nne ) SYSCLK2 RES ETon (RESO UT3) QDATA IDATA DCLK RXON RFSTR R FDAT R FCLK BS EL0 D IR MO D [D.

1.8V ) V DD_E (1. BLOCK DIAGRAM VBAT Vincenne V DD_LP (1.5V V MEM V DDA 0.1.75V / 200mA ) V DDPA V EXT15 1.75V V CCB W opy Herta V FLASH 2.2 V DDE1 V DDDM 5.5V ) V DDE0.5.75V Ingela V CCA W anda 2.5V ) 2.8V ) V DD_H V DD_L GSM PAM LCD V CC V DD_D (2.8V ) V DD V DDI V DDL UMTS PAM DCDC N1620 V CCBIAS V CC LCD White LED V DDI V DD VRAM V CC V CC CS 2 RF RAM V BATI LM4894 Figure 5-4.8V / 100mA ) DCIO V DD_B V DD_A V DD_D V DD V DDA_TX V DDA_RX V DDA_BG V DDA_CS _APLL V DD_DPLL V EXT15 V DD_CLK32 VRTC V DIG V BUCK V DD_IO V BAT_C V DDBUCK SWBUCK VSSBUCK R 0. Power Diagram . 1ohm V BATI V DIG L Marita P BUCK NBUCK V CORE(1.2 V CORE (1.75V FLASH V CC V CCQ VBATI W IVI REG N1850 2.5V ) V DDMC V DDE2 V DDCODEC V DDBEAR VRTC V DDRTC PASEN E+ S V DDBUF V BAT_A V DD_D (2.4V V DD_E (1.8V V _wiv i_A V _wiv i_B Camera V DD_D (2.185 - .

6.186 - . DISASSEMBLY INSTRUCTION 6. DISASSEMBLY INSTRUCTION .

187 - . DISASSEMBLY INSTRUCTION .6.

6.188 - . DISASSEMBLY INSTRUCTION .

189 - .6. DISASSEMBLY INSTRUCTION .

190 - . DISASSEMBLY INSTRUCTION .6.

6. DISASSEMBLY INSTRUCTION .191 - .

6.192 - . DISASSEMBLY INSTRUCTION .

DISASSEMBLY INSTRUCTION .6.193 - .

7.194 - . – The older version software of the phone can be replaced to the newer version. DOWNLOAD The Purpose of Downloading Software • To make a phone operate at the first manufacturing – A phone = Hardware + Software – A phone cannot operate with hardware alone. DOWNLOAD 7. – The hardware with the suitable software can operate properly. • To upgrade the software of the phone – The software of the phone may be changed to enhance the performance of the phone. • Download Tools FlashRW : Download tool for U81X0 software Download Environment Setup U81X0 UART data cable USB cable U81X0 Download can be done via UART & USB .

exe.195 - . Execute FLASHRW. 2. Press the “Global Settings” on the top menu to configure FlashRW environment . DOWNLOAD U81X0 Download (1) – FlashRW configuaration 1.7.

Select Port configurations for both RS232 Port and USB Port. 4. You have to do FlashRW configuration only at the first time of installation . DOWNLOAD U8110 Download (2) – FlashRW configuaration 3.pldr for U8120.196 - .7. You can use browse button to select Loader File. Select Loader File for Product. Loader File is provided with FlashRW. You may select any loader of 3 loaders in loader folder for U8110. You must select only U8120_CXC1325712_R2H(R5E_Signed by cust_brown). Baudrate should be 115200bps.

DOWNLOAD U81X0 Download (3) – Phone Model Selection 1. 2. Select Model to download images . Press Button for Model.7.197 - .

2.198 - . Click to select file <Before Select> U81X0 download file is selected <After Select> . DOWNLOAD U81X0 Download (4) – Download file selection 1.7. Press “Add1” button to select LGE GDFS file to download. Press “Add” button to select LGE SSW files to download.

7. Phone should be turned off. DOWNLOAD U81X0 Download (5) – Connect & Download 1.199 - . 3. Connect the phone to PC via Cable for Downloading. Turn the phone on to connect to PC. Click on connector icon ( ) to connect to the phone Check the Dialog Box that say “Please.switch on the target”. 2. 1 .

7. Error will happen because of USB Driver uninstalled. If you use FlashRW Tool firstly.200 - . DOWNLOAD U81X0 Download (6) – USB Driver Install 1. You have to do FlashRW USB Driver Installation only at the first time of installation .

201 - .7. Select “Search for a suitable driver for my device” in Found New Hardware Wizard . Push “the Next Button” in Found New Hardware Wizard 3. DOWNLOAD U81X0 Download (7) – USB Driver Install 2.

. Push “the Browse Button” . Select “Specify a location” in Found New Hardware Wizard 5.202 - . and then select “USB driver Information file” This File is provided with FlashRW.7. DOWNLOAD U81X0 Download (8) – USB Driver Install 4.

Push “the Next Button” in Found New Hardware Wizard 7.203 - . Push “the Finish Button” in Found New Hardware Wizard .7. DOWNLOAD U81X0 Download (9) – USB Driver Install 6.

7. just do as same as U81X0 Download (5) – Connect & Download says .204 - . Remove & Insert Main battery to reset the phone % This action for USB Driver Install is done only at the first time of installation If you want to download Software. Close FlashRW.exe 9. DOWNLOAD U81X0 Download (10) – USB Driver Install 8.

DOWNLOAD U81X0 Download (11) – Connect & Download < While Downloading > < After Downloading finished > .205 - .7.

2.Trouble shooting • Check these questions when trouble happens. Do not change RS-232 baud rate(115200BPS).206 - . Check if UART & USB Cable is connected. It is fixed and never changed. 1. DOWNLOAD U81X0 Download (12) . 3. .7. Check if UART & USB Port configuration is right.

Window2000.1 H/W Environment .National Instrument GPIB &VISA (ver 2.2 XCALMON Environment 8.Serial port configuration : Baud rate:115200 /Char length:8bit /No Parity/No Flow control Stop bits:1 bit 8.60 full)driver install .3 Configuration Diagram of Calibration Environment Figure 8-1. RF cable.OS :Window98. WCDMA Band RF partscalibration and Battery calibration.1 General Description This document describes the construction and the usage of the software used for the calibration of LG’s GSM/GPRS/WCDMA Multimedia Mobile Phone (U8110). 8.GSM/GPRS/WCDMA Multimedia Mobile Set (U8110) . From now on. This calibration software includes GSM.WindowXP .Agilent 8960 VXI driver(E1960)install .XCALMON EXE files . CALIBRATION 8. Calibration Configuration Figure . Serial cable. Power cable. Dummy battery) 8.8.2 S/W Environment .2.Agilent 8960 Series 10 E5515C Instrument (E1985B ver04. This calibration software was called “XCALMON(eXtended CALibration and MONitor program)”.207 - .2. The calibration menu and their results are displayed in PC terminal by Mobile phone. the calibration software will be called XCALMON in this document.ETC (GPIB cable.2.08) . DCS. CALIBRATION 8.Tektronix PS2521G Power Supply .PC with RS-232 Interface & GPIB card installed .

RSSI Cal i br at i on C.RF VCO Center Frequency Calibration .when any of calibration is done.MODA-D(MD bit)Delay Calibration .it is explained each calibration item in the XCALMON. At first.RSSI and AGC Calibration B.RX AGC Gain Max and Rx RSSI Calibration . 8.RXVCO Varactor Operating Point Calibration .1 Overview In this section.TX Power Calibration . DCS 1800 Band .3.208 - .TXVCO Varactor Operating Point Calibration .TX LPF Bandwidth Calibration . WCDMA Band . CALIBRATION 8.2 Calibration Items A.VCXO Calibration .Also the explanation includes technical information such as basic formula of calibration and settings for key parameters in each calibration procedure.the results are displayed in the XCALMON result window and the result of calibration will be stored in GDFS(Global Data Flash Storage).TXVCO Varactor Operating Point Calibration .TX Loop Bandwidth Calibration . EGSM 900 Band .RXVCO Varactor Operating Point Calibration .RX LNA Gain Switch and AGC Hysteresis Calibration .TX Power Table Calibration .3.TX Carrier Suppression Calibration .8.TX Open Loop Power Control Calibration .3 Calibration Explanation 8.TX Power Calibration .TX Maximum Output Power Calibration .RX LPF Bandwidth Calibration .TX Loop Bandwidth Calibration .

A threshold value of >20 deg indicates that the PLL is running in the forbidden time region. 6.It also ensures that the MOD signals have stable values when they are clocked into the divider of the Phase-Locked Loop (PLL). 3.no delay. Wait approximately 300 us to 400 us to allow the PLL to lock. 10. Delay Settings for the MOD-A MD 00(0) 01(1) 10(2) 11(3) 00(0) 01(1) 10(2) 11(3) . Set the ME to mid channel in the GSM TX band. Step up the delay setting according to Table 8.that is. Choose delay setting that gives maximum distance to the consecutive field of corrupted RMS phase error values in the vector. 7.209 - .1 below. Set the delay setting in default mode. Index [0] [1] [2] [3] [4] [5] [6] [7] DIMC 0 0 0 0 1 1 1 1 Table 8-1. Save the RMS phase error result locally.Pur pose The procedure is designed to calibrate the timing alignment between the MODA-D signals and the reference signal (13 MHz).3 EGSM 900 Calibration Items A. 9.3. . Measure the RMS phase error.8. 5. Reset the radio. 2. Store delay setting both to the GD_RF_Mod_Delay and to the GD_DirMod_Mod_Delay. Repeat from step 4. 4. CALIBRATION 8. 8. MOD-A(MD bit) Delay Calibration .Procedure Proposal 1.

C.Pur pose The loop bandwidth is calibrated to match the pre-filtering of the modulation in DB 2000 by adjusting the phase detector current. 4. 2. This is necessary to secure that all RX channels can be reached. If there are several CVCO values that fulfill the loop voltage requirements. 3. RXVCO Varactor Operating Point Calibration . If there are several CVCO values that fulfill the loop voltage requirements. This will ensure a correct transfer function for the modulation and keep phase error to a minimum.so that the loop voltage of the TXVCO (measured with an ADC in AB 2000) is within the valid range. This is necessary to secure that all TX channels can be reached. 0 ~7.then the optimum CVCO value is the one that centers the loop voltage within the specified limits. 2. D.8. Note:This also indirectly adjusts the VCO gain that can otherwise not be calibrated. 4.210 - .Pur pose To adjust the varactor diode to a pre-determined operating point. Find a CVCO value that fulfills the requirements on loop voltage for low and high channel. (GD_RX_VCO_Centre_Frequency_Adjustment_Band) 5. Store the selected CVCO in the memory. TX Loop Bandwidth Calibration . 3. that is. Measure the loop voltage with the AB 2000 ADC for all CVCO settings.Procedure Proposal 1. Reset the radio. Reset the radio. .Pur pose To adjust the varactor diode to a pre-determined operating point.so that the loop voltage of the RXVCO (measured with an ADC in AB 2000) is within the valid range. Find a CVCO value that fulfills the requirements on loop voltage for low and high channel. . (GD_TX_VCO_Centre_Frequency_Adjustment_Band) 5. Measure the loop voltage with the AB 2000 ADC for all CVCO settings. CALIBRATION B. . TXVCO Varactor Operating Point Calibration . 0 ~7. Store the selected CVCO in the memory. Put the phone in static TX mode.Procedure Proposal 1. that is. Put the ME in static RX mode.then the optimum CVCO value is the one that centers the loop voltage within the specified limits.

and check tuning range. Depending on the calibration procedure. Frequency Interval 0 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -2 -2 -2 -2 -1 -1 -1 -1 -1 -2 -2 -2 -2 -1 -1 -1 -1 -1 -2 -2 -2 -2 -1 -1 -1 -1 -1 -2 -2 -2 -2 -1 -1 -1 -1 -1 -2 -2 -2 -2 -1 -1 -1 -1 -1 -2 -2 -2 -2 -1 -1 -1 -1 -1 -2 -2 -2 -2 -1 -1 -1 -1 -1 -2 -2 -2 -2 -1 -1 -1 -1 -1 Table 8-2. IPHD Compensation for EGSM Band E. . Calculate and store the IPHD values in GDFS (GD_IPHD_8Temperature_and_24Channel_Compensation_Band) 5.choose the lowest value. Tune the phase detector current (IPHD)until the phase error is minimized.8.Procedure Proposal 1. VCXO Calibration .2 and all offsets refer to the calibrated value (Trim) at mid channel in room temperature.and that the temperature compensation table for VCXO is completed accordingly.or W-CDMA RF frequency at the antenna and then translating the measured frequency to the 13 MHz VCXO frequency.211 - . 2.Measure 10 bursts for each value.If two IPHD settings gave the same RMS. Note:The frequencies in this section are related to the 13 MHz VCXO-frequency. Put the ME in switched low power TX mode with a modulated carrier on a mid channel. .the 13 MHz VCXO frequency can be acquired by first measuring an EGSM. The offsets in the table are steps in the IPHD Table 8. Put the ME in switched TX mode on mid channel in frequency interval 11 for EGSM (with random modulation). Tune DAC3 in AB 2000 (VCXOCONT)to end and mid values.It also ensures that the VCXO tuning range is sufficient. Measure the RMS phase error at the RF connector. 3. 2.DCS. 4. CALIBRATION .Pur pose This procedure aims to calibrate the value of DAC3 to establish a VCXO-frequency that is sufficiently close to 13 MHz at room temperature.Procedure Proposal 1. Use the calibrated value of the cap array and phase detector current.

8. with the results stored in the memory (GD_RF_SYNT_CONFIG_ID).that gives zero frequency error at the mid channel. 3.fmid.05.Procedure Proposal 1. 2.which calculatesand st or e t he val ues in memory (GD_IntermediatePower_Up/Down_1. Acquire the ME temperature.VCXOCONTCal. . 5.However.Pur pose These procedures describe how to tune the different power levels of the power amplifier to output powers corresponding to values in GSM 05.CDMA)to the 13 MHz VCXO-frequency. 6. CALIBRATION Acquire the following VCXO (13 MHz)frequencies: fmin =13 MHz VCXO-frequency @DAC3=1 fmid =13 MHz VCXO-frequency @DAC3=1024 fmax =13 MHz VCXO-frequency @DAC3=2047 Note that it is necessary to translate the measured RF-frequency (EGSM.or W. and select a‚ mid channel using the trimmed value on the capacity array for VCO tuning and a default IPHD value as phase detector current.212 - .5 dB.and explain how to calculate intermediate power levels that will ensure a good power versus time performance. .shall not be less than 0. measured at the same frequency. 3.from the temperature sensor in ME.7_Band). Calculate K_LO =(fmid –fmin)/1023 K_HI =(fmax –fmid)/1023 Each value is then multiplied by 100 and rounded to nearest integer. 4.DCS.fmax and TCal for calculation.and store the value in the memory (GD_RF_SYNT_CONFIG_ID and GD_VCXO) 6. Store DAC values in memory (GD_FullPower_Band). Use the Multi-burst method to characterize the relation between output power and the DACvalue.Then store the DAC values that give the closest approximations to the power targets defined in Table 8-3. Initiate the intermediate value calculation. AFC_DAC_STEP_LO =ROUND(100*K_LO) AFC_DAC_STEP_HI =ROUND(100*K_HI) where ROUND(x)=x rounded to the nearest integer. TX Power Calibration . Store fmin. To avoid yield problems with the power template and switching transients spectrum a margin to the compression point of the PA should be observed. Reset the DIRMOD-block. Calculate the DAC-value. Turn on dummy burst modulation.the output power must be kept within the tolerances specified in Table 8-3.TCal. 5. The difference between the transmitter power at two adjacent power control levels. F.5 dB and not more than 3. 4. using piecewise linear interpolation.

5 ±0. .5 ±0. Select switched receiver on a mid EGSM Channel. Target Power Levels for EGSM G.5 ±0. calculate the RSSI table and store the value in GDFS as parameter: GD_RXLEVS_DBM_BURST_M_BAND.0 13.5 Vol Vol Vol Vol Vol Vol Vol Vol Vol Vol Vol Vol Vol Vol Vol Table 8-3.Procedure Proposal 1.0 15. now feed a modulated -50dBmsignal and measure the RSSI value. Feed a modulated -68.0 7.0 29. on the same mid EGSM-Channel to the antenna input. RSSI and AGC Calibration .5 ±0.0 ±0. (Where k is the slope value.5 ±0. Measure the RSSI value.0 5. and m is an offset value.5 ±0. y the actual level.0 25.5 ±0.0 23.5 ±0.8.5 ±0. 2.0 9. This value together with a pre-defined slope figure is then used to calculate the RSSI value of an arbitrary received antenna power. The attenuation value is stored in the flash memory and used when very high input signals are fed into the ME.0 17. The formula y=kx+m is used. On the same channel.5 – 1.3 ±0.5 ±0.0 Tolerances (dB) +0.213 - .5 ±0.5 ±0.5dBmsignal.Purpose This procedure satisfies the two following requirements: Calibrate an absolute power level on the antenna to a corresponding RSSI value.0 21.0 11. 3.0 31.0 27.0 19. x the RSSI value. . CALIBRATION Parameter PL 5 PL 6 PL 7 PL 8 PL 9 PL 10 PL 11 PL 12 PL 13 PL 14 PL 15 PL 16 PL 17 PL 18 PL 19 Target Full Power (dBm) 33.) Calculate the attenuation when the Low Noise Amplifier is switched off in the receiver branch.

8. (GD_BAND_RX_VCO_Centre_Frequency_Adjustment) 5.Purpose The loop bandwidth is calibrated to match the pre-filtering of the modulation in DB 2000 by adjusting the phase detector current. Find a CVCO value that fulfills the requirements on loop voltagefor low and high channel. This is necessary to secure that all RX channels can be reached. C.Procedure Proposal 1.Purpose To adjust thevaractordiode to a pre-determined operating point. Store the selected CVCO in the memory.214 - . . Measure the loop voltage with the AB 2000 ADC for all CVCO settings. that is. 4.Procedure Proposal 1. Reset the radio. so that the loop voltage of the TXVCO (measured with an ADC in AB 2000) is withinthe valid range. This is necessary to secure that all TX channels can be reached. Put the ME in static RX mode.0.4 DCS 1800 Calibration Items A. Calculate the difference between on and off (converting the result to‚ real dB attenuation) and store the result in GD_MPH_RX_AGC_Parameters_Band. 0 ~ 7. CALIBRATION 4. Note: This also indirectly adjusts the VCO gain that can otherwise notbe calibrated.Purpose To adjust thevaractordiode to a pre-determined operating point. and measure the RSSI value. then the optimum CVCO value is the one that centers the loop voltage within the specified limits. Measure the loop voltage with the AB 2000 ADC for all CVCO settings. Put the phone in static TX mode. Find a CVCO value that fulfills the requirements on loop voltagefor low and high channel. Reset the radio. 2. If there are several CVCO values that fulfill the loop voltage requirements. This will ensure a correct transfer function for the modulation and keep phase error to a minimum. 0 ~ 7. 8. 4. . TXVCO Varactor Operating Point Calibration . If there are several CVCO values that fulfill the loop voltage requirements. 3. that is. (GD_BAND_TX_VCO_Centre_Frequency_Adjustment) 5. B. 5. 3. TX Loop Bandwidth Calibration . 2. then the optimum CVCO value is the one that centers the loop voltage within the specified limits. Store the selected CVCO in the memory.3. RXVCO Varactor Operating Point Calibration . so that the loop voltage of the RXVCO (measured with an ADC in AB 2000) is withinthe valid range.1. . Switch off the LNA. using the command FREC=3.

IPHD Compensation for DCS Band D. 4. Then store the DAC values that give the closest approximations to the power targets defined in Table 8-5. 2. The offsets in the table are steps in the IPHD Table 8. CALIBRATION .8. Measure 10 bursts for each value.Purpose To tune the different DCS power levels of the power amplifier tooutput powers corresponding to values in GSM 05.Procedure Proposal 1. . Frequency Interval 0 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 Table 8-4. choose the lowest value. Tune the phase detector current (IPHD) until the phase error is minimized. Turn on dummy burst modulation.215 - . 2. 3.05 and calculate the intermediate levels that ensure a good power versus time performance. Measure the RMS phase error at the RF connector. and select a ‚mid channel using the trimmed value on the capacity array for VCO tuning and a default IPHD value as phase detector current. TX Power Calibration . Calculate and store the IPHD values in GDFS (GD_IPHD_8Temperature_and_24Channel_Compensation_Band) 5. Use the Multi-burst method to characterize the relation between output power and the DAC-value. Reset the DIRMOD-block. .Procedure Proposal 1.4 andall offsets refer to the calibrated value (Trim) at mid channel in room temperature. If two IPHD settings gave the same RMS. Put the ME in switched TX mode on mid channel in frequency interval 11 for DCS (with random modulation).

Target Power Levels for DCS . Parameter PL 0 PL 1 PL 2 PL 3 PL 4 PL 5 PL 6 PL 7 PL 8 PL 9 PL 10 PL 11 PL 12 PL 13 PL 14 PL 15 Target Full Power (dBm) 30.5 ±0. CALIBRATION 3.5 ±0. However.216 - .0 26.5 ±0.5 ±1 Vol Vol Vol Vol Vol Vol Vol Vol Vol Vol Vol Vol Vol Vol Vol Vol Table 8-5.5 ±0.0 ±0. the output power must be kept within the tolerances specified in Table 8-5. 4. To avoid yield problems with the power template and switchingtransients spectrum a margin to the compression point of the PA should be observed.0 4.5 ±0. which calculatesand store the values in memory (GD_IntermediatePower_Up/Down_1.0 Tolerances (dB) +0.0 22.0 18. 6.5 ±0.0 24.5 ±0. shall not be less than 0.0 16.5 ±0.5 ±0.0 2. 5.5 ±0. Initiate the intermediate value calculation.0 6. Store DAC values in memory (GD_FullPower_Band). The difference between the transmitter power at two adjacent power control levels.5 ±0.8.0 8.0 20.0 0.5 ±0. measured at the same frequency.3 ±0.0 14.0 10.5 dB and not more than 3.0 12.5 dB.7_Band).5 – 1.0 28.

5dBmsignal. Measure the loop voltage (WRFLOOP). on the same mid DCS Channel to the antenna input. and store it to the memory (GD_BAND_RXLEVS_DBM_BURST_M[2]) –1 byte. Store the calibrated CVCO value in GD_RF_SYNT_CONFIG_ID. x the RSSI value. TX Carrier Suppression Calibration . B. 3. to the wanted signal at the IQ-modulator output. y the actual level. It impairs the modulation accuracy and results in a high vector magnitude (EVM). Start the VCXO and RFVCO. The objective of the calibration is to determine a CVCO (Center VCO) value that guarantees the functionality of the RFLO (Radio Frequency Local Oscillator). (Where k is the slope value. 2.8. Use typical TX settings. . . CALIBRATION E. 0-7. RF VCO Center Frequency Calibration . Ericsson AB 2000 DAC3. The outcome of the calibration is values for RECDCI and RECDCQ that minimize the carrier. . then the optimum CVCO value is that that centers the loop voltage within the specified limits. and m is an offset value).Procedure Proposal 1. Set the ME in TX mode on mid-channel.5 WCDMA Calibration Items A.217 - . The leakage is caused by imperfections in the basebandIQ-path and inside the IQ-modulator. The formula y=kx+m is used. Feed a modulated -68. that is.Purpose This procedure calibrates an absolute power level on the antennaagainst a corresponding RSSI value.Purpose This procedure is designed to calibrate the RFVCO (Radio Frequency Voltage Controlled Oscillator) center frequency of the Ericsson RF 2110 (hereafter referred to as the RF 2100) and ensure that all channels can be reached with sufficient margin. . with the AB 2000 ADC (GPA4). Start with the best value from earlier calibrated units on RECDCI on RECDCQ.Procedure Proposal 1. Find a CVCO value that fulfills the requirements on loop voltage for low and high channel. calculate the RSSI table. This value together with a pre-defined slope figure is then used to calculate the RSSI value of an arbitrary received antenna power.Procedure Proposal 1. Measure the RSSI value. 8. If there are several CVCO values that fulfill the loop voltage requirements.3. VCXOCONT is set to its calibrated value. Select switched receiver on a mid DCS-Channel. for all CVCO settings. 2.Purpose DC offset compensation the carrier. Generate 960 kHz square-wave on both I and Q with amplitude = 8 (sine-wave could be used instead). RSSI Calibration .

The objective of this calibration is to determine the values forLPQ and LPBW that offer the best trade off against the system-related requirements.218 - . D. Store the calibrated parameters in GD_RF_TX_CONFIG_ID. VGA and QVGA settings that fulfill ACLR requirements for maximum output power. repeat steps 3. Find and set RECDCQ to the value that minimizes the 1950 MHz carrier. Jump to 6 if the requirement is met. Step RECDCI from 0 to 3. Generate a 960 kHz square-wave at baseband without phase shift between I and Q. Span = 8 MHz. wait 1 ms and continue with stepping from 5 to 7. C. .Procedure Proposal 1.8. 5 once with the new RECDCI and RECDCQ (found in 4 and 5) as initial values. If the requirements are not met. Measure the relative power between the 1950 MHz carrier and 1949.Purpose These procedures verify that the ME can meet the requirements onmaximum output power. Spectrum analyzer settings (example): RBW = 300 kHz. If this involves a change of sign the TXON switching and delay sequence in point 3 must beexecuted. 5. Start with the best value from earlier calibrated units. TX Maximum Output Power Calibration . both in high. Use typical TX settings.Procedure Proposal 1. 3. Use typical TX settings. 3. Set TXON = 1. . 7. These settings determine the cut-off frequency and should always have the same value. 4 and.88 MHz (fc+ 3*960 kHz) and 1949. RECDCI and RECDCQ. 4. 6. . The amplitude should be about 50% of fullscale.Purpose The low pass filters within the Ericsson DB 2100 (hereafter referred to as DB 2100) are designed to prevent spurious emissions output from the TX IQ-D/A (Digital-Analog) converters Πwithout adversely affecting the signal or causing a deterioration of the modulation accuracy. Save the finaldBcvalue (for statistics).04 MHz at the antenna output. 2. Measure the relative power between 1952. CALIBRATION 2.121. Otherwise proceed with step 6. and low gain mode. Set RECDCI to the value that minimizes the 1950 MHz carrier. Also save thedBcand the decided LPQ = LPBW value for statistics. medium. This can be made by stepping RECDCQ from 0 to 7 with the TXON switching and delay sequence in step 3. These calibrations are designed to conform to the ME maximum output power and ACLR requirements specified in 3GPP Spec TS34. TX LPF Bandwidth Calibration . Find the setting of LPQ =LPBW between 3 and 15 that obtains the dBcvalue closest to the typical value. Store the calibrated parameters in GD_RF_TX_CONFIG_ID.04 MHz (fc Π960 kHz) in dB at the antenna output. Set LPQ=LPBW to the found value in 2. if necessary. Set TXON = 0 and wait 1 ms before changing RECDCI from 3 to 5. The calibration aims to establishWPABias. mid channel. 2. Jump to step 6 if the requirement is met. Set gain to the best value based upon previous calibrated units.

Set gain to maximum power in medium gain mode and measure ACLR at this power level. RFBiasshould be set to 1 andWPABiasshould be set to the same value as for maximum output power. . described in Table 11 are not met. PABias should not be offset and RFBIAS should be 1. This power. Set gain to maximum power in low gain mode and measure ACLR at this power level. The purpose of this calibration is to complete the TX Power gain table with values for VGA. Interpolate the gain steps in between the averaged measured values. 13. 8. If the ACLR requirements. inner loop power control. calculate the test step necessary to achieve the correct power. 9.Procedure Proposal This calibration consists of two parts: first measurements and then an off-line calculation. (5) WPABias gain step size. step the gain down and measure ACLR until the requirements are met. PABias should not be offset and RFBIAS should be 1. Use correlation from earlier calibrated units to calculate the new gain setting (default correlation between VGA and output power is 1 dB and for QVGA 0. reduce VGA and QVGA.Pmax measMG. 10.Purpose The calibration data contained within the TX Power Table controls the gain for all types of power change.RFBiasshould be set to 1 andWPABiasshould be set to the same value as for maximum output power. This provides the value forTPmax. the inner-loop power control and maximum output power of the platform. WPABias. 11. change of TFC and (PRACH preamble tolerances)requirements specified in 3GPP Spec TS34. E. The measurement results are used for characterizing the hardware so that proper settings can be calculated for all tables. This power. If the requirements are not met. step the gain down and measure ACLR until the requirements are met. 1. 4. and gain setting provides input to the calibration of TX power table. Use correlation from earlier calibrated units to calculate the new gain setting. Settings and limitations are also used from maximum output calibration. (2) VGA behavior in MG (Medium Gain mode). 6. including.8. 7. is input to the calibration of TX power table. Measure output power as broadband power. If the requirements are not met. Every eighth setting is measured twice. Use known correlation from earlier calibrated units to calculate the new gain setting. 12. These calibrations are designed to conform to the ME maximum output power. The size of hysteresis area must also be found. 14. Measure and store the temperature at this point. (3) QVGA behavior in LG mode (4) IQ-Gain behavior in LG mode.Pmax measLG. This power and gain setting is to be used in calibration of TX power table. Measure ACLR at this power level. QVGA. 5. RFBIAS. Perform measurements (1) VGA behavior in LG (Low Gain) mode. CALIBRATION 3.121. . If the ACLR requirement is not met.25dB). TX Power Table Calibration . For better accuracy take the average of each step pair. and WDCDCREF that meet the specified requirements for inner-loop powercontrol and Maximum output power.219 - . The correlation between ACLR and output power is that 1 dB in power equals typical 3 dB in ACLR.

Perform offline calculations (1) Calculate the compensation values for Table 8-6. One WPABias table: 44 bytes. CALIBRATION (6) WDCDCREF gain step size. The main purpose is to find the relative difference at different frequencies. -15 0 15 30 45 60 75 90 Table 8-6. Store this in GD_RF_TX_FREC_INT_ID. (7) Size of step between LG/MG and MG/HG and between each setting of RFBIAS (1-7). Compensation needed for maximum output power over the band (13 channels). For better accuracy take the average of each step pair. One value for IQ-Gain: 1 bit (will occupy 1 byte). One WDCDCRef table: 44 bytes. maximum and minimum steps reported. Average value of minimum and maximum should be used in following calculations.The Complete Gain Compensation Table 9612 9637 9662 9687 9712 9737 9763 9788 9813 9838 9863 9888 . One Low-gain table: 44 bytes. Store these values in GD_RF_TXGAIN_TB_SEL_ID.8. Each set of tables shall include: One High-gain table: 44 bytes. One value for UPPER_LIMIT: 1 byte. (4) Calculate and store the 24 sets of tables. Distribute with equal frequency offset except if there are known ‚worst-case frequencies. One value for TABLE_OVERLAP: 1 byte. One RFBias table: 22 bytes. GD_RF_TX_GAIN_TB0_ID to GD_RF_TX_GAIN_TB23_ID. (2) Extract the range of needed compensation tables (minimum and maximum). (5) Calculate the actual compensation (for maximum output power) that each of these 24 tables will give. 2. Interpolate the gain steps in between the averaged measured values. 3.220 - . (3) Calculate the expected compensation for each table in dB (use ‚table 0 for the table that is ‚0 dB or closest to ‚0 dB) and spread out the rest to achieve equidistant compensations. (8) Measure properties: Measure the following properties using a modulated signal: WPA-gain expansion versus output power on mid channel. Measured at 5 channels. Store data in GDFS UARFCN Temp. Every fifth setting is measured twice.

A2. P1 and P2 in GD_RF_TX_GAIN_PARAM_ID. Example of Position versus Power and Calculated Equations . Create a curve fitting for the low-gain region. Use data (positions and output power. use powerlevels from P2: Position = B2 * Pout + A2 6. in dBm) from table 0. Save A1. 4. A3. Figure 8-2. Extract A1 and B1 9. Extract A2 and B2 7. Do a curve fitting for the high-gain region (where RFBias = 0) of the high-gain region: Position = B1 * Pout + A1 8. 5.221 - . This is a pure off-line calculation. 3. B2. Do a curve fitting for the mid-gain region (where RFBias > 0) of the high-gain region.8.Procedure proposal 1. Curve fitting should be done preferably with minimum square method. B1. CALIBRATION E. The output power at this position sets the parameter P1. The power level (output power) at the highest position in the low-gain region sets the parameter P2. Divide the high-gain region into two regions at the split between mid-gain and high-gain. Extract A3 and B3. TX Open Loop Power Control Calibration . B3. System related requirements: Open loop power control Maximum allowed UL TX Power UE Transmitted power .Purpose The purpose of the calibration of open loop power control is to store parameters for the Open Loop Power Control algorithm. use positions with a power greater than -50 dBm: Position = B3 * Pout + A3 2.

AGC Block Diagram (Parameter Ak. LPQ=LPBW=8. Figure 8-3. Set UE in RX-mode on 10695ch. 6.8. N should be as large as possible. that is. and Pref) . Calculate Average_Ak (Ak_IB) according to the equation below. IF_SYM = Ak_IB . . 3. The procedure also verifies that the IF-filter is properly matched. with respect to time consumption. 4. 7. If the requirement is not met. 11. Get Ak (output2) from N slots. decrease LPBW and LPQ one step and repeat from 8.Purpose This procedure calibrates the LPF bandwidth. Set UE on 10705ch and get Ak (output2). Output1. 2. Calculate Ak (Ak_OB) according to the Equation 1. 9. RX LPF Bandwidth Calibration . Set RF 2110 LPQ and LPBW to 8. Feed a CW carrier at 2140 MHz with a power of -60dBm into the antenna connector.Ak_LB 8. GLNA is forced to high gain mode.222 - .Procedure Proposal 1. Set UE on 10685ch and get Ak (output2). Store the resulting LPBW and LPQ in GD_RF_RX_CONFIG_ID. Ak_SE = Ak_OB – Ak_IB 10. The bandwidth of the channel filters will affect system parameters as reception sensitivity and adjacent channel selectivity. Calculate selectivity level using following equation. CALIBRATION F. Calculate Average_Ak (Ak_LB) according to the Equation 1. Set the AGC_UL and AGC_LL to minimum. Calculate IF-filter symmetry using the following equation. 5.

4. GLNA is forced to low gain mode. It also calibrates AGC_UL and AGC_LL. 8. AGC_LL and AGC_UL are AGC algorithm parameters and are set to DB 2100 RFIF.223 - . CALIBRATION F. (Ak_LG) . the upper and lower Ak values where the AGC should switch between high and low LNA gain (AGC hysteresis). Set the UE in RX-mode on 10695ch.8. RX LNA Gain Switch and AGC Hysteresis Calibration . that is. Round off (Correction) to integer (AGC_CR) and store it in GDFS (GD_RF_RX_CONFIG_ID). Calculate AGC_LL=8+AGC_CR and AGC_UL=18+AGC_CR and store them in GDFS (GD_RF_RX_CONFIG_ID). . Get average Ak from Equation 1 and save it. AGC_CR is an AGC algorithm parameter and is set to DB 2100 RFIF. 9. (Ak_LG) 5. Get average Ak. GLNA is forced to high gain mode. 6. Set the AGC_UL and AGC_LL to minimum. Set the AGC_UL and AGC_LL to maximum.Procedure Proposal 1. LNA Gain Switch and AGC Hysteresis Parameters . 3. it establishes the gain difference in the LNA between high gain mode and low gain mode.Purpose This procedure calibrates the gain correction parameter of Ak in the AGC algorithm between GLNA=0 and GLNA=1. Figure 8-4. Feed a CW carrier at 2140 MHz with a power level of -65dBm. 2. (Ak_HG) 7.(Ak_HG) = (Correction).

5.224 - . 12. . N in Equation 1 should be as large as possible. 10. Then increase the output level of the signal generator to -80. The specified accuracy requirement is applied to the received power from -94 through -50 dBm. Store Average_Ak_110 and Pin_Corrected_110 according to step 4. 9. the AGC anti-wind up is turned on using AGC_GMAX=127. This is the last RX calibration. AGC_CR. Position 2 to 5 should be set to zero. the first position in the table (Ak=0) should be replaced with the table number (0-23) in bcd format and the second position (Ak=1) set to 0xffff to flag that the table is calibrated. 11. rounded off to an integer. 3. Read Ak value (output2) and calculate Average_Ak (Equation 1). CALIBRATION G. (GD_RF_RX_AK_TB0_ID). Set the AGC parameter AGC_GMAX to the calibrated value. 2. Change the CW carrier power level to -95 dBm. Use the average Ak values and Pin_Corrected from the two lowest power levels (-95 and -80 dBm) to extrapolate Ak and Pin_Corrected for -110 dBm according to: Average_Ak_110 = 2*Average_Ak_95 – Average_Ak_80 Pin_Corrected_110 = Pin_Corrected_95 – Pin_Corrected_80 8. -40 and -25 dBm and store the corrected RF input level and Ak to the memory respectively. Perform the offline calculations and check the requirements. Measure the ME temperature (T) and save for offline calculations. When stored in GDFS. Clear Ak ‚table 0. Use the calibrated value after step 2. Pin_Corrected = Pin-round(Average_Ak)+Average_Ak Equation 2 6. Perform the interpolation. LPBW.8. AK_BANK_SEL in DB 2100 shall be set to 0. Store Pin_Corrected (Equation 2) at Ak=round(Average_Ak). -60. . 7. 4. Reference [6] specifies that the reporting range of the RSSI should be between -100 dBm to -25 dBm. LPQ. add 6 to the value and store it in GDFS as AGC_GMAX (GD_RF_RX_CONFIG_ID).Procedure Proposal 1. Store the result to GDFS. RX AGC Gain Max and RX RSSI Calibration . otherwise the AGC wind up may occur at the beginning of the RSSI calibration.Purpose To prevent wind up in AGC algorithm. this procedure calibrates the absolute power levels at the antenna connector against RSSI values and the maximum gain setting for AGC. AGC_LL and AGC_UL must be calibrated according to above calibrations respectively and applied to this calibration. Feed a CW carrier at 2140 MHz with a power level of -105 dBm. Set the ME in RX-mode on channel 10695. Initially. Get average_Ak (output2).

225 - .Purpose Calibrates the voltage table for the power management functionality. Set voltage on VBATT to 4. Battery Voltage Calibration Limits . Send the command LVBA=5. Voltage Level on VBATT (V) 3.6 Baseband Calibration Item A.20 V. 6. 2. 7. 3C 60 96 150 Unit HEX DEC HEX DEC Table 8-7.1 64 100 Typ. .3. Send the command LVBA=0 to reset local values in Test Program. CALIBRATION 8.8. 4.Procedure Proposal 1. Send the command LVBA=1 to store local values into global data.0x140 to read the low voltage level from ADC. 19 25 4.0x19A to read the high voltage level from ADC. Send the command LVBA=5. 5. 3. Set voltage on VBATT to 3. Send the command LVBA=3 to view and record values stored in global data. 2E 42 7E 125 Max. Some voltage measurements in the remaining test will be done with calculated voltage levels from this test.10 V.2 Min. Battery Voltage Calibration .

it checks the connection of instruments and initializes them automatically. please execute the XCALMON program. . Tektronix PS2521G) control . DCS 1800.Command window which supports interactive ITP commands like Hyper terminal Figure 8-5.8.Calibration of EGSM 900. Running the XCALMON program. And if you finish making configuration. If XCALMON program would be executed. XCALMON supports three functions. and WCDMA band .4 Program Operation 8. CALIBRATION 8.226 - . XCALMON Window .UART communication with U8110 mobile phone XCALMON has three windows and each window support different function.1 XCALMON Program Overview When you try to calibrate the U8110 mobile phone. .4.Instrument (Agilent8960. The result of checking and initializing instruments was shown like Figure7-6.Calibration tree window . you should show XCALMON program window like Figure7-5.ITP(Integrated Test Program) starting window using production loader . you should make a configuration of calibration environment like Figure7-1.

then you should see the calibration tree window. DOS Window Icon When you click the DOS window icon. you should select “Calibration” and push “F4” button in your keyboard.8.INSTRUMENT : Control and view instrument connection status .4.227 - . XCALMON ITP Command Window B. Figure 8-6. you should get the response of the present running ITP version information from U8110 mobile phone. If you want to calibrate U8110 mobile phone for all calibration items. if you will enter command “VERS” and enter the return key. then you should see the ITP command window like DOS window of DOS-operating system.UART : Control and view UART connection status . For example. . Also there are four tap view in calibration window.2 XCALMON Icon Description A. Calibration Tree Window Icon When you click the calibration window icon ”C”.OUTPUT : All results of calibration . you should communicate with U8110 mobile phone which is running in ITP mode. That will be shown all calibration items. CALIBRATION 8.STATUS : Summary of calibration result . In ITP command window.

8. XCALMON Calibration Tree Window (OUTPUT Tab) Figure 8-8. CALIBRATION Figure 8-7.228 - . XCALMON Calibration Tree Window (INSTRUMENT Tab) .

8. XCALMON Calibration Tree Window (UART Tab) C. To change ITP start address is possible when we download “Production loader” previously. When it will occur power-on. .229 - . That dialog window just wait for power-on of U8110 mobile phone. CALIBRATION Figure 8-9. it automatically start ITP running. you could change that address directly. then you should see the ITP starting window. If you want to change the start address of ITP. ITP Starting Window Using Production Loader When you click the ITP starting window icon”L”.

you should see the characters “TP. then you will see the ITP start window like Figure7-10. XCALMON ITP Starting Window (Using Production Loader) 8. .8. . Click the “L” icon.Calibration start using XCALMON . B.3 Calibration Procedure Calibration procedure of XCALMON was the same as below procedure.Running ITP using production loader . CALIBRATION Figure 8-10. When you will turn on the U8110 mobile phone. If configuration will be accomplished. you should run ITP using “L” ITP starting icon at first. the production loader will be downloaded automatically like Figure7-11 and then it will execute the ITP at once.Verification of calibration result A. Configuration of Calibration Configure to calibrated U8110 mobile phone like Figure7-1.4. OK” in ITP command window like Figure7-12. If the ITP will operate normally.Configuration of calibration . Running ITP Using Production Loader If XCALMON will be executed. start XCALMON program.230 - .

Production Loader Downloading Figure 8-12.8. CALIBRATION Figure 8-11.231 - . ITP Start Complete Window .

Calibration Start Using XCALMON If you want to calibrate U8110 mobile phone. To start calibration. Verification of calibration result If the calibration will be ended. Figure 8-13. And then you will see the calibration tree window like Figure7-6.232 - . Additionally. D. it is possible to check the calibration result with OUTPUT & STATUS tab view.8. On the contrary. you will see several message window and the result of calibration through OUTPUT & STATUS tab view. if the calibration is over with some error.4. click the calibration icon “C”.4. CALIBRATION C. “FAIL” message window will show up like Figure7-14. “PASS” message window will show up like Figure7-13. Calibration PASS Message Window .4 Calibration Result Message If the calibration is over without error. The detail explanation of those will be described in chapter 7. you should select “Calibration” item and push “F4” button in your keyboard. in all of the cases.4 8.

8.233 - . Calibration Result from OUTPUT Tab View . CALIBRATION Figure 8-14. Calibration FAIL Message Window Figure 8-15.

Calibration Result from STATUS Tab View .8. CALIBRATION Figure 8-16.234 - .

235 - . CIRCUIT DIAGRAM 1 2 3 4 5 6 7 8 9 10 11 12 A A C1012 22p ANT G4 G3 G2 G1 WCDMA_TX TX RX N1002 DFYK61G95LBNCB WCDMA_RX B C1013 W1001 KMS-507 RF G2 G1 ANT B C1000 6.7u R1811 0 C1802 10u 2012 VCCB N1800 LP2985AIBP-2. DEVELOPMENT GROUP 1 TITLE: Size: A2 12 1 8 A H Drawn by: SG Kang R&D CHK: DOC CTRL CHK: MFG ENGR CHK: Changed by: SG Kang ANT SW to ANT U8100 PT V1.6nH GND4 GND3 GSM1900_RX GSM1800_RX V1001 RN47A4 15 13 5 7 3 GND2 GND1 GND5 VC2 VC1 9 10 VDD VCG 11 VCCB C C1010 1000p 3 4 R1002 NA 2 16 4 2 C1011 22p 1 C DCS_RX R1007 1 5 51 GSM_RX ANTSW3 ANTSW2 ANTSW1 ANTSW0 D R1001 NA R1006 0 R1005 0 R1004 0 R1003 0 D C1007 0.033u H Engineer: SG Kang LG ELECTRONICS INC.8p ANTPAD GSM_TX 22p DCS_TX 12 GSM900_RX GSM1800_1900_TX 14 GSM900_TX 6 WCDMA 8 ANT N1000 LMSP54MA-213 L1001 12nH L1002 5.8 6 VEN BYPASS 7 GND2 5 0 R1826 0 V_wivi_B G G 2 3 VOUT_SE 4 GND1 C1851 0.8 EXTLDO F R1804 NA 5 ON_OFF GND 1 2 3 R1801 NA BYPASS R1800 NA VBATI C1800 0. September 04. 3G HANDSETS LAB. 2003 Time Changed: 5:01:55 pm QA CHK: 1 2 3 4 5 6 7 8 9 10 11 12 .3 Staggered AMD REV: Drawing Number: Page: 1 Date Changed: Tuesday.01u C1008 10p C1003 0.1u C1852 10u 2012 LP3981ILD-2.1u 4 VIN NA VOUT F C1801 1000p R1825 V_wivi_A R1851 0 N1850 1 VOUT VIN R1850 0 C1850 0.9.01u C1001 10p C1009 10p C1002 0.01u C1004 0.01u C1005 10p E VDD_A R1810 E VCCA 0 VDD_B C1810 10u 2012 C1811 4.

3G HANDSETS LAB.3 Staggered AMD REV: Drawing Number: A2 12 1 8 A Date Changed: Tuesday. 2003 Time Changed: 12:50:11 pm QA CHK: Page: 2 1 2 3 4 5 6 7 8 9 10 11 12 .01u C1731 22p C1741 22p R1740 10 VCCB R1730 10 WDAT R1723 F WCLK WSTR R1431 0 R2108 C1720 5600p 0 WRFLOOP F GPRFCTRL CLKREQ 100 FROM MARITA SIDE FOR POWER SAVING G G H Engineer: SG Kang LG ELECTRONICS INC.9.01u C1425 2200p C1424 22p C1444 22p 1608 C1431 22p A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 C4 C5 C6 C7 C1777 47p B10 C10 D10 E10 F10 G10 H10 J10 C8 D8 E8 F8 G8 H8 C1776 4.3K R1430 10 VCCB C1772 330p C1773 4.01u D C1401 WCDMA_RX 22p C1400 NA L1401 2.2nH L1411 6.01u C1454 0.01u R1401 0 R1410 0 R1440 0 NA L1422 68nH L1760 1uH C1421 R1760 0 MCLK C1761 82p C 1608 C1448 C1447 0. September 04.01u R1411 3.01u C1452 RXIB 0.7p B1770 TSX-8A 3 HOT2 2 GND1 GND2 4 C C1760 0.01u L1402 NA R1721 R1720 5.01u C1422 27p C1423 27p C1451 RXQA RXQB RXIA 0.6K TP1401 TP1402 TP1403 C1721 390p 0 C1722 NA C1730 0.236 - .01u 0.2p RFLO R1505 NA C1751 22p K2 K3 K4 K5 K6 K7 K8 K9 K10 H3 H4 H5 H6 H7 RFLOBAR XOOA XOOB E O2 G3 IN G1 1 2 3 E G2 LK20A O1 Z1400 6 5 4 C1407 22p C1740 0.8nH C1402 1000p INDBYP RFOUT VCCPLL VCCPHD PHDOUT VTUNE VCCVCO VCCRFLO RFLOOB XOOON RXON GNDPLL GNDPHD GNDTUNE B1 C1 D1 E1 F1 G1 H1 J1 K1 C3 D3 E3 F3 G3 C1413 1.2p C1442 2200p B L1441 100nH 1608 C1453 B VCCB 0. DEVELOPMENT GROUP 1 TITLE: Size: H Drawn by: SG Kang R&D CHK: DOC CTRL CHK: MFG ENGR CHK: Changed by: SG Kang UMTS RX (WOPY) U8100 PT V1.7p V1770 R1771 10K R1770 1K C1770 0. CIRCUIT DIAGRAM 1 2 3 4 5 6 7 8 9 10 11 12 A A Z1420 TMX-M453 6 5 4 1 2 3 INSHIELD OUT+ IN+ GND OUT- C1441 2200p C1443 1.2p IFOUTB VCCMIX MIXINA MIXINB GNDBIAS GNDEME RFIN GNDBYP VCCRF GNDIF DATA CLK STROBE GLNA IFOUT GNDMIX VCCIF IFINA IFINB VCCLF QRA QRB IRA IRB CDQ CDI GNDLF MCLK VCXOCONT N1400 LZT-108-5323 VCCREF XOIA XOIB VCCBUS IFLOA IFLOB GNDRFLO RFLOOA XOOA XOOB GNDREF GNDBUS REFON GNDVCO BBY58-02W C1778 HOT1 1 D 56p R1772 10K 13MHz IFLO IFLOBAR C1750 22p C1412 1.01u L1421 68nH C1403 22p C1404 C1414 22p 0.

7u L1601 C1627 4.01u C1513 0.237 - .3 Staggered AMD REV: Drawing Number: Date Changed: Tuesday.01u C1509 10p R1603 C1701 0.7K C1711 3300p V_wivi_B R1703 0 G G H Engineer: SG Kang LG ELECTRONICS INC. 3G HANDSETS LAB. CIRCUIT DIAGRAM 1 2 3 4 5 6 7 8 9 10 11 12 A A WCDMA_TX N1650 CE0401G95DCB000-TT1 GND2 GND1 OUT GND4 GND3 R1633 VBATI NA B R1630 IN B VCCWPA R1629 N1630 11 10 R1621 R1623 0 R1997 VDETECT VCC_DET GND2 VCC_BIAS2 VCC_BIAS1 GND1 VCTRL2 VCTRL1 22 GND10 23 GND11 GND9 RFIN 8 VBATI 7 6 R1631 15 VCC21 VCC22 GND8 VCC11 VCC12 5 4 3 2 R1632 19 C1631 10p 1 0 C1635 NA R1617 L1604 NA L1605 NA 0 C1626 330p C1636 NA 0 R1626 33K C1622 22p 0 0 A1 A2 A3 A4 B4 N1620 MAX1820ZEBC _SKIP COMP OUT REF GND SYNC _SHDN BATT LX PGND B1 C1 C2 C3 4.9.2nH C1504 10p 0 C1602 22p C1601 0.01u WDAT WCLK WSTR F V_wivi_A F 0 C1501 47p L1502 15nH R1504 680 C1502 4p H8 G8 F8 E8 D8 C8 I10 H10 G10 F10 E10 D10 C10 B10 R1711 0 C1712 NA C1710 150p R1710 4.2p J2 J3 J4 J5 J6 J7 J8 J9 J10 H3 H4 H5 H6 H7 E A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 C4 C5 C6 C7 C1507 4p R1502 680 L1501 15nH R1501 C1505 22p GNDRFVCO2 STROBE GNDRFPLL TXON GNDRFPHD GNDRFVCO1 GNDTUNERF VCCRFVCO VCCRFPLL PHDRFOUT VCCRFPHD GNDIFVCO2 GNDTUIF VTUNEIF OUT OUTBAR GNDRF MIXOUT MIXOUTBAR VCCIF IFBP IFBPBAR VTUNERF GNDRFLO2 GNDRF1 GNDRF2 GNDRF3 GNDIF N1700 LZT-108-5322 QINBAR QIN INBAR IN VCCBB VCCIFPHD PHDIFOUT VCCIFPLL GNDIFVCO1 VCCIFVCO CLK GNDIFPHD GNDIFPLL WON TXQB TXQA TXIB TXIA C1503 22p R1702 10 V_wivi_B C1704 22p C1703 0.01u C1511 10p C1512 10p C1510 0. September 04. DEVELOPMENT GROUP 1 TITLE: Size: A2 12 1 8 A H Drawn by: SG Kang R&D CHK: DOC CTRL CHK: MFG ENGR CHK: Changed by: SG Kang UMTS TX (WIVI) to ISOLATOR U8100 PT V1.01u 16 17 18 C WPAREF 0 IFLOBAR RFLO C1715 100p L1720 C1714 100p 20 21 IFLO RFLOBAR V_wivi_A D L1507 75 BLM15BB750SN1J R1503 0 R1510 0 NA C1716 4.01u D V_wivi_B V_wivi_A L1503 5. 2003 Time Changed: 5:04:02 pm QA CHK: Page: 3 1 2 3 4 5 6 7 8 9 10 11 12 .01u TP1701 TP1702 XOOA XOOB B1501 G3 F3 E3 D3 C3 J1 I1 H1 G1 F1 E1 D1 C1 B1 C1508 VO 3 TP1504 TP1503 TP1502 TP1501 E GNDRFLO1 GNDIFLO DATA GNDBUS GNDBB VCCRF RFLOBAR RFLO VCCIFLO IFLOBAR IFLO VCCBUS XOOC XOOB V_wivi_A 4 V+ RTEMP R1605 0 R1606 NA R1604 NA L1506 NA 1 2 3 Z1500 SX-S205B G1 S_OUT G2 B_IN2 G3 B_IN1 GND1 2 GND2 NC 5 1 LM20BIM7X 6 5 4 L1505 10nH 2.6nH L1504 8.7uH C4 C1623 10u C1624 4.7p R1701 10 C1702 22p C1514 0.7u L1602 L1603 R1628 100K C1628 1000p 3838 L1621 R1627 0 WDCDCREF GND4 RFOUT GND3 9 RF9266 VCCWPA 12 13 14 GND5 GND6 GND7 WPOWERSENSE 39K C C1632 0.

September 04.068u L1333 75 C1335 22p R1333 C1113 22p C1334 22p C1336 NA C1327 33p C1331 22p 10 R1342 560 R1340 560 C1102 L1331 15nH L1100 3.3nH DCS_RX R1140 100K G1 G2 G3 C1333 10p TXON 0 R1113 A1 B1 C4 E8 F4 F7 G3 G4 H8 A2 B5 B7 F5 F8 H6 C1142 C1141 0.068u C1143 0. DEVELOPMENT GROUP 1 TITLE: Size: H Drawn by: JS Joo R&D CHK: DOC CTRL CHK: MFG ENGR CHK: Changed by: JS Joo GSM/DCS (INGELA) U8100 PT V1. 2003 Time Changed: 7:25:06 pm QA CHK: Page: 4 1 2 3 4 5 6 7 8 9 10 11 12 .9.01u F1 AVDD D5 QDAT A4 IDAT C5 DCLK TP1141 TP1142 TP1143 PAREG 0 C1322 R1329 1K R1328 NA R1321 1K IOUT C VDIG 150p FF_IN EXPOUT R1302 0 C1320 470p N1330 LDB21897M15C R1338 1 UB GND1 GND2 NC B1 3 B2 4 I2CDAT I2CCLK SYSCLK2 RESOUT3n TP1151 TP1152 D3 I2CDAT D1 I2CCLK G8 MCLK D2 RESETB A8 IRA A7 IRB A6 QRA A5 QRB B4 RXSTR E4 F2 F3 G1 B8 B6 C6 C7 C8 D6 D8 D7 QDATA IDATA DCLK C C1321 470p VDDPA VSSPA C1300 0.068u C1140 0.01u C1151 NA VDIG R1150 0 VDIG_HERTA C1153 NA C1155 NA 2 5 6 C2 C1 D4 E2 H2 H3 B2 E1 GND4 VCC1 D C1144 0.01u C1313 22p VDDBUF PASENSE+ R1327 0 C1326 NA R1325 R1326 0.9nH 10p B7714 4 6 O1 O2 Z1100 IN C1100 10p L1101 3.068u 0. 3G HANDSETS LAB.6nH 1608 C1270 VCCA XOOB F XOOA R1273 NA 1000p NC4 GNDVAR GNDVCO5 GNDVCO4 GNDVCO3 GNDVCO2 PHDOUT VTUNE VCCVCO GNDVCO6 GNDSILENT NC2 NC1 GNDVCO1 NC5 MODA MODB MODC MODD VCCPLL XOOB XOOC NC6 GNDBUF NC3 PS GNDPLL XOOLA N1100 LZT-108-5325 RFHD RFHC GNDRF RFLB RFLA VCCRF QRB QRA IRB IRA REON CLK DATA STROBE R1103 0 R1104 0 R1105 0 R1106 0 F H8 G8 F8 E8 D8 C8 J10 H10 G10 F10 E10 D10 C10 B10 R1240 R1250 GPRFCTRL 0 C1240 NA PULSESKIP 0 C1250 NA TP1201 L1220 2012 RADCLK RADDAT G RADSTR L1202 TP1202 TP1203 R1222 120 C1224 1200p R1223 390 C1222 560p G R1224 R1220 560 C1221 0. CIRCUIT DIAGRAM 1 2 3 4 5 6 7 8 9 10 11 12 A A VBATI BLM31PG601SN1 B R1301 0 L1300 B C1315 C1311 10u 10u 2012 2012 C1312 0.068u 14 15 16 17 2 5 6 1 3 5 VDIG_HERTA G2 NC1 H1 NC2 RXON E BSEL0 PCTL MODA R1212 R1334 0 R1213 100 C1230 NA C1231 NA G3 F3 E3 D3 C3 K1 J1 H1 G1 F1 E1 D1 C1 B1 L1230 C1112 33p L1110 18nH C1111 33p E Z1110 B7705 3 2 O1 G1 IN O2 G2 4 5 C1110 1 33p L1111 10nH GSM_RX MODB R1211 100 MODC R1210 PCTL BSEL RXON TXON GNDPLANE TXOHA TXOHB VCCBUF TXOLA TXOLB GNDRF2 RFHB RFHA GNDRF1 100 K2 K3 K4 K5 K6 K7 K8 K9 K10 H3 H4 H5 H6 H7 MODD VCCA R1121 NA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 C4 C5 C6 C7 C1104 0.05 VDIG PASENSE0 R1320 R1322 NA C1323 1200p R1323 NA R1151 V1330 2SD2216J NA R1324 NA C1325 100p 0 C1156 0.068u C1324 100p 20 8 7 6 RXON 0 R1339 NA R1337 NA C1332 33p VCC2 BGND3 L1330 33nH C1343 NA C1341 C1342 NA L1340 1.01u C1103 22p L1120 L1200 100 C1205 22p C1201 0.01u C1220 NA 100uH C1225 1800p VLOOP 0 VCCA C1223 330p C1203 22p C1202 0.3 Staggered AMD REV: Drawing Number: A2 12 1 8 A Date Changed: Tuesday.238 - .8nH L1350 2.2nH C1351 NA C1340 NA 21 9 10 11 12 BGND4 GND5 BGND2 GND3 EGSM_IN GND2 GND1 BGND1 19 5 4 3 2 1 18 R1332 0 D GSM_TX DCS_TX EGSM_OUT GND6 GND7 33p C1352 10p N1300 CX77304-16 DCS_PCS_OUT GND8 BGND5 DCS_PCS_IN BGND0 R1335 0 L1332 75 R1341 BLM15BB750SN1J 1 B2 UB GND1 GND2 NC B1 3 4 BS 22 APC C1350 NA 13 VCCA N1331 LDB211G8020C C1330 22p C1114 7p 2 C1115 NA C1101 10p AUXI1 CCO MICIP DAC01 MICIN GPA0 DAC02 GPA1 DAC03 GPA2 N1101 GPA3 LZT-108-5321 GPA4 DACCLK GPA5 DACDAT GPA6 DACSTR GPA7 DEC1 H7 PCMDL DEC2 F6 PCMCLK DEC3 G6 PCMSYN DEC4 E7 ADSTR DEC5 E3 REXT VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 AUXO2 BEARP BEARN PCMUL GPDAT GPCLK H4 G5 H5 G7 E6 E5 C3 B3 A3 C1150 0.01u C1271 R1272 NA 1000p L1201 5.01u H Engineer: JS Joo LG ELECTRONICS INC.

7uF.9K C2605 0.1u ROP-101-3029_2C C4 ONSWA C5 ONSWB A7 ONSWC B7 INTLCKB RESETB IRQ PWRRST LED1 LED2 32KHZ SIMOFF SIMVCC A9 C1 B8 A6 B6 L1 C2 F1 C2301 H3 G1 G2 F3 C2300 F2 B12 A11 C11 M11 L12 L2 C2203 1u A2 A4 A5 R3345 0.54SF AUDIO AMP C3273 R2606 NA 33K L2606 L2605 C2606 0.1u C2212 0.8 USBSENSE R2233 51K USB REGULATOR H IRDA REGULATOR Engineer: TAE-SUNG.9.2u 2012 1 LP2985IM5X-3. 2003 Time Changed: 7:25:29 pm QA CHK: REV: Drawing Number: Page: 5 1 2 3 4 5 6 7 8 9 10 11 12 .7u C2211 0.1u 3 D2 2 G1 1 S1 S2 4 G2 5 D1 6 EN_LED_TC R2107 NA R3376 0 B ONSWAn ONSWBn ONSWC RESOUT0n IRQ0n PWRRSTn C2302 & C2303 CLOSER TO SIM SOCKET TP3316 INDICATOR LED 1 2 3 4 11 12 C2303 C2312 0 X2300 5 P5 P1 6 P6 P2 7 P3 P7 8 P4 P8 9 GND3 GND1 10 GND4 GND2 FB3 SIM HOLDER R3248 B RTCCLK TP3000 TP2311 TP2310 R3002 0 VDIG 10K R2312 M1 XTAL1 M2 XTAL2 SIMDAT0 SIMCLK0 SIMRST0 MCLK I2CDAT I2CCLK CLKREQ PWRREQn C R2101 100K VBATI 4.068u 22p C2618 C2610 22p D1 D3 C2 D5 C2611 100u C2609 0.1u R3019 R2205 VDIG 0 0 R2220 100K H1 SDAT J3 SCLK H2 SRST K9 MCLK C8 SDA B9 SCL K3 CLK_REQ C10 SLEEP J12 L5 K6 K7 H12 VREF DEC0 DEC1 DEC2 IREF 1608 1u R2305 15K R2313 0 R2306 47 V3202 RB521S-30 FB4 R2614 NA C2635 NA VBATI R2615 NA C2634 NA SIMDAT SIMCLK SIMRST CDCDA CDCDB VDD_A VDD_B EXTLDO VDD_D VDD_E VDDLP TGBUZZ NA R2314 C2302 V2300 DALC208SC6 1 2 IO1 REF2 IO2 R2201 1608 R2202 0 R2203 1K 1608 BA3000 C3247 VRTC C2202 BACKUP BATTERY 4.1u 0 SPKMUTE DCIN_3 C2280 NA 1608 Q2201 Si5441DC 8 1 D1 D6 7 2 D2 D5 3 6 D3 D4 4 5 G S R2214 R2215 0.068u C3266 10p 5 2 3 4 6 1 X2602 C2607 2012 R3379 R3382 0 R3328 8.1u M9 VDDBEAR 3.3 Staggered AMD H Drawn by: TAE-SUNG.1u E10 G12 C12 E12 E11 D11 D12 C3278 100p VSSPA VDDPA_DAC VDDBUF PASENSE+ PASENSEPAREG IOUT VDIG VEXT15 N2203 VDIG 2 C2274 1 0.05 R2216 0.05 E2 DCIO D1 CHREG D3 CHSENSE+ D2 CHSENSEF11 FGSENSE+ EARP TP3319 L2608 BLM15BB750SN1J EARM N2602 R2613 22p C2614 C2615 10 0.7u L2202 VBATI BLM18PG121SN1 1608 120 OHM BEAD C2205 L2200 V2201 RB521S-30 22uH 10u 2012 10u 2012 0 IO4 REF1 IO3 6 0 KPD9D-8S-2. September 04.1u K8 VSSADC K5 VSSCODEC K4 VSSBEAR PWRRSTn N3000 3 2 ON_OFF BYPASS C3046 100p 4 VIRDA R3050 0 5 C3052 4.3V REG N2204 C2276 100p 4 VUSB VDDADC G C2207 0.22 ELL5GM220M CHOKE COIL C3274 NA D 4 U3106 NA N2000 VINCENNE DACO1 DACO2 DACO3 TXON EXPOUT FF_IN BEARP BEARN AUXO1 CCO B5 G11 H11 A8 G10 F10 M4 L3 L4 L9 C2608 1u 1608 22K R2617 C2619 100u R3031 0 AMPCTRL R2610 100K D WDCDCREF WPAREF VCXOCONT TXON EXPOUT FF_IN C2638 C2637 NA NA 2012 C3248 0.068u IP4025CX20 MICP MICN ATMS ATMS_CAP AFMS_R AFMS_L VDD A2 A1 A3 A4 B4 A5 B5 C3277 NA 4.1u R2607 3.239 - .7u R2232 10K C3051 2.7u C3013 C2281 4.1u C2213 C2214 0.51 2125 Q2200 R2208 0. 3G HANDSETS LAB.1u R3385 NA R3395 0 R3303 100K C3275 NA R3386 NA D2015 R3381 RB521S-30 47K VIN VSS VOUT NC 3 C2272 4 1u 1608 F S-817A15ANB-CUE-T2 K1 PCMSYN J1 PCMCLK K2 PCMO J2 PCMI M5 VDDCODEC GPA6 1. CIRCUIT DIAGRAM 1 2 3 4 5 6 7 8 9 10 11 12 DCIN_3 A A R3378 3.2u 2012 1 LP2985IM5X-2.3K E VDIG B C Q3203 DTA114EETL D2010 R2106 EN_LED_R 100K 1SS388 C2621 TP3004 0.1u L2603 BLM15BB750SN1J R2619 R2618 C3221 0 0 TP3318 R2213 0.2K 1% R3327 180K 1% NA MOTOR_BATT 24 B11 BDATA B3 VIBR C9 DACDAT B10 DACSTR A10 DACCLK HOOK R3294 DACDAT DACSTR DACCLK B1 GND1 B2 GND2 B3 GND3 C3 GND4 C4 GND5 C5 GND6 R3041 100K R3042 100K R3043 100K NA PT1 47K 1% D2016 RB521S-30 C3267 NA TJATTE2 C3268 47p C3269 47p F VSSPA VDDPA VDDBUF PASENSE+ PASENSEPAREG IOUT PCMSYN PCMCLK PCMDATB PCMDATA VDIG R3045 100K R3046 100K R3047 100K R3049 100K R2217 0 R2218 0 C2209 0.3 100K C2277 4. 2012 C2616 X2603 SUMY0005601 OBG-15S44-C2KU NA C3270 NA 1 F12 C3271 47p C3272 47p H10 G3 C6 E3 D10 B1 D4 DCIN_2 E VBATI VBAT VSS_A VSS_B VSS_C VSS_D SUB VSSBUCK TEST MIC1P MIC1N AUXI1 MIC2P MIC2N AUXI2 GPA5 AUXO2 VSSTH31 VSSTH30 VSSTH29 VSSTH28 VSSTH27 VSSTH26 VSSTH25 VSSTH24 VSSTH23 VSSTH22 VSSTH21 VSSTH20 VSSTH19 VSSTH18 VSSTH17 VSSTH1 VSSTH2 VSSTH3 VSSTH4 VSSTH5 VSSTH6 VSSTH7 VSSTH8 VSSTH9 VSSTH10 VSSTH11 VSSTH12 VSSTH13 VSSTH14 VSSTH15 VSSTH16 M8 L8 M6 M7 L7 L6 K12 J4 E4 F4 G4 H4 J5 J6 J7 J8 H9 G9 F9 E9 D8 D7 D6 F7 G7 G6 E5 E6 E7 E8 F8 G8 H8 H7 H6 H5 G5 F5 D5 D2 C2617 0.5V REGULATOR GPIO05 M3 C2210 0.033u 2 FGSENSE- D4 AFMS_R_INT C1 CCO MICP_INT MICN_INT ATMS_INT ATMS_AD AFMS_L_INT C2630 22p 22p C2631 22p 22p E C2612 0. HA LG ELECTRONICS INC.1 0.7u G IRDA_REG_CTRL GND VIN VOUT 5 R3051 VBATI 3 2 ON_OFF BYPASS GND VIN VOUT VBUS C2278 2.9K B2 SD_SEL SD_MODE B3 GND LM4898ITL R2609 33K E1 B4 C7 M10 L10 K10 L11 K11 J11 J10 J9 D9 0.01u R3397 0 C2613 0. HA R&D CHK: DOC CTRL CHK: MFG ENGR CHK: Changed by: mentor Date Changed: Tuesday.33u 1608 C2632 22p C2633 1000p VDD_B EXTLDO VBAT_C R2235 0 1u 5 4 22p VDIG VDD_A 1608 C 22p C3 A3 A2 R2621 0 3 R2200 VDIG VMEM C2200 0 C2603 1u 1608 N2601 B1 C1 VDD ININ+ VO2 VO1 BYPASS SPKP R2620 0 A12 M12 A3 SPKM VBAT_A VBAT_B VDDBUCK VBAT_C PBUCK VBAT_D NBUCK MOD1 ADSTR GPA0 GPA1 GPA2 GPA3 GPA4 GPA6 GPA7 GPA12 GPA13 SWBUCK VBUCK VDD_IO A1 B2 C3 R2608 3. DEVELOPMENT GROUP 1 TITLE: Size: A2 BB MAIN PCB 12 1 8 A VINCENNE U8100 PT V1.1u A1 C2 VBACKUP VBAT_C R3026 100K R2212 0 C3246 0.1u 0.22 R2210 C2206 10u VCORE LM20BIM7X 5 1 GND2 NC 2 GND1 V+ VO 3 R3384 NA R3396 ADCSTR RTEMP VLOOP WPOWERSENSE WRFLOOP GPA6 VBACKUP SI1555DL 0 VCORE VDIG N2603 ADG702 1 6 D VDD 2 5 S NC 3 4 GND IN C2604 0.

4 0.8 PITCH 10 X 8 X 1.5V U8100 WS01-5 VCORE VMEM VRTC VEXT15 MCP 64/08.4 0.4 0.8 PITCH 10 X 8 X 1.4 0.4 0.1u C2245 0.0 A R2223 R2241 R2221 R2222 R3103 R2237 R2100 U8100 ES01-1 DEFAULT RTCCLK ONSWC A 47 RF I/F MODA MODB MODC MODD DCLK IDATA QDATA TXON RXON RADCLK RADSTR RADDAT BSEL0 GPRFCTRL ANTSW0 ANTSW1 ANTSW2 ANTSW3 PCTL OPTION U8100 ES01-2 U8100 ES01-3 TOSHIBA 0 0 0 0 0 0 ADDRESS X DATA = 2^23 X 2^4 = 2^27 = 128MBIT A22 = 128MBIT.3 MEM_CS0_N MEM_CS1_N MEM_CS3_N DAT(0) H8 K8 H7 J7 K5 J4 H4 K3 J8 G7 K7 H6 H5 K4 G4 J3 H2 B5 J2 D6 D5 C5 E5 B2 B4 H3 C6 C2 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 NA B VDDMC VDDDM VDDUSB VDDRTC VDDA0 VDDA1 VDDA2 K20 E1 J21 AA11 Y12 AA13 R14 AA19 N1 R12 Y14 M20 D20 B12 R1 Y1 AA7 H20 A15 L21 A17 B1 K2 A9 B6 R20 M2 N2 Y10 C2 B16 A13 A11 B8 A5 A3 H2 U1 AA1 AA3 Y6 Y18 V20 N21 B21 A19 U3103 S71WS256HC0BAW00 _CEF1 _CEF2 _CE1S CE2S_ZZ _RESET _WP RDY _ADV CLK _OE _WE ACC _UB _LB ADR(12) ADR(13) ADR(14) ADR(15) ADR(16) ADR(17) ADR(18) ADR(19) 100K ADR(11) R3323 MCP RESOUT0n VMEM C J5 VCCF1 L5 VCCF2 VCCS J6 ADR(20) ADR(21) ADR(22) ADR(23) ADR(24) R3338 MEM_WAIT_N MEM_ADV_N MEM_CLK MEM_OE_N MEM_WE_N 100K DAT(0:15) C3136 0.5V 1.4 .768KHz C2100 C2101 0.8 PITCH 10 X 8 X 1.4 0.4 0.4 0.1u C2243 0.4 0.1u C2261 NC1 NC2 RFU1 RFU2 RFU3 RFU4 RFU5 RFU6 RFU7 RFU8 RFU9 RFU10 RFU11 32.8 PITCH 10 X 8 X 1.09.1.13 VDDE 1. YOU R&D CHK: DOC CTRL CHK: MFG ENGR CHK: Changed by: mentor Date Changed: Tuesday.4 0.7K VDIG 3.4 U8100 ES01-6 TOSHIBA OPTION U8100 PT V1.8 PITCH 10 X 8 X 1. A21 = 64MBIT TP3100 TP3101 TP3102 TP3103 4 MC-146 B2100 C2100 and C2101 close to B2100 32.3K Rout track on inner layer DAT(0:15) DAT(15) DAT(14) DAT(13) DAT(12) DAT(11) DAT(10) A22 = 128MBIT NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 ADR(1:24) D8 E5 F4 F5 E4 D3 G7 F7 E7 C7 D7 F6 E6 C6 D6 C3 E3 F3 D2 C2 E2 F2 G2 ADR(23) ADR(22) ADR(21) ADR(20) ADR(19) ADR(18) ADR(17) ADR(16) ADR(15) ADR(14) ADR(13) ADR(12) ADR(11) ADR(10) ADR(9) ADR(8) ADR(7) ADR(6) ADR(5) ADR(4) ADR(3) ADR(2) ADR(1) DAC USB F HSSL HSSLRXCLK HSSLRX HSSLTXCLK HSSLTX TCK TMS TDI TDO TRST_N RTCK TEMU0_N TEMU1_N IRRX IRTX IRCTRL MMCCLK MMCCMD MMCDAT MSSCLK MSBS MSSDIO SIMDAT0 SIMRST0_N SIMCLK0 SIMDAT1 SIMRST1_N SIMCLK1 KEYOUT0_N KEYOUT1_N KEYOUT2_N KEYOUT3_N KEYOUT4_N KEYOUT5_N KEYIN0_N KEYIN1_N KEYIN2_N KEYIN3_N KEYIN4_N PCMCLK PCMSYN PCMDATA PCMDATB TSYP TSYM TSXP TSXM NC0 NC W8 R10 Y9 AA9 V9 Y8 P11 V10 P20 P19 M15 L19 J14 J19 K19 K14 K15 N18 N19 N20 M19 L15 M18 P14 AA17 Y17 W17 V16 W18 AA15 Y15 W15 V15 W16 V3 W1 W2 V4 R13 V13 W14 Y13 K18 E3 J18 R11 V12 W13 V14 L4 M7 W9 E4 D15 D13 G10 G9 H8 A2 G4 R4 U4 R9 V8 Y16 V18 Y21 F18 A21 D16 L18 R3322 R3337 CAMERA I/F CS2 MEM_CS2_N 100K for Intel I2CDAT CIPCLK CIVSYNC CIHSYNC CIRES_N CID0 CID1 CID2 CID3 CID4 CID5 CID6 CID7 DAT(9) DAT(8) DAT(7) DAT(6) DAT(5) DAT(4) VMEM DAT(3) DAT(2) DAT(1) DAT(0) J7 H6 J6 H5 J4 H4 J3 H3 G6 K6 G5 K5 K4 G4 K3 G3 VSSE00 VSSE01 VSSE02 VSSE100 VSSE102 VSSE104 VSSE106 VSSE108 VSSE110 VSSE112 VSSE200 VSSE201 VSSE202 VSSE203 VSSE204 VSSE205 VSSE206 VSSE207 VSSE208 VSSE209 VSSE210 VSSE211 VSSMC VSSDM VSSUSB VSSRTC VSSA0 VSSA1 VSSA2 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 U3104 AM29BDS128HD9VKI FLASH H2 _CE D5 _RESET F1 _WP C4 RDY G1 _AVD E1 CLK J2 _OE C5 _WE D4 ACC R2122 3. 3G HANDSETS LAB DEVELOPMENT GROUP1 TITLE: Size: A2 BB MAIN PCB 12 1 8 A MARITA U8100 PT V1.4 0.1u C2223 0. September 04.1u C2258 0.4 0.1u VIRDA SIMDAT0 SIMRST0 SIMCLK0 R3333 NA I2CCLK_CAMERA C3225 0.1u C2218 0.1u C2221 0.4 0.5V VEXT15 VCORE 1.8 PITCH 9 X 12 X 1.1u C2255 0.1u C2250 0.8 PITCH 10 X 8 X 1.0 Staggered TOSHIBA U8100 PT V1.1u C2216 0.8 PITCH 9 X 12 X 1.8 PITCH 9 X 12 X 1.5 X 1.1u C2263 0.8 PITCH 9 X 12 X 1.4 0.8 PITCH 9 X 12 X 1.1u C2252 0.1u C2262 R2238 0.1u C2217 0. 2003 Time Changed: 9:42:54 am QA CHK: REV: Drawing Number: Page: 6 1 2 3 4 5 6 7 8 9 10 11 12 .1u C2257 0.1u C2219 0.8 PITCH 10 X 8 X 1.8 PITCH 10 X 8 X 1.8 PITCH 9 X 12 X 1.8 PITCH 9 X 12 X 1.1u C2260 1 R3110 R2403 22p R3325 22p 2 3 0.3V VUSB 1.5V 1.8 PITCH 10 X 8 X 1.1u C2251 0.4 0. CIRCUIT DIAGRAM 1 2 3 4 5 6 7 8 9 10 11 12 * MEMORY CHANGE HISTORY U8100 WS01-1 U8100 WS01-2 U8100 WS01-3 U8100 WS01-4 2002.4 0.3K R3330 NA DAT(0) DAT(1) DAT(2) DAT(3) DAT(4) ADR(1) ADR(2) ADR(3) ADR(4) ADR(5) ADR(6) ADR(7) ADR(8) ADR(9) ADR(10) E2 J7 F3 F2 K4 K3 L7 G3 G2 K8 H4 G1 H3 K7 J2 J4 J3 J1 L8 DAT(7) DAT(6) DAT(5) DAT(4) DAT(3) DAT(2) DAT(1) VDDC00 VDDC01 VDDC02 VDDC03 VDDC04 VDDC05 VDDC06 VDDC07 VDDC08 VDDC09 VDDC10 VDDC11 VDDC12 VDDC13 VDDC14 VDDC15 VDDC16 VDDC17 VDDC18 VDDE00 VDDE01 VDDE02 VDDE101 VDDE102 VDDE104 VDDE106 VDDE108 VDDE110 VDDE112 VDDE200 VDDE201 VDDE202 VDDE203 VDDE204 VDDE205 VDDE206 VDDE207 VDDE208 VDDE209 C R2123 VPPFLASH 120K B TP2100 TP2101 C2102 330p P13 R3 T2 T3 L3 R2 F4 L1 P8 U2 U3 M8 T4 M3 M4 V2 M14 P18 R21 R8 P9 AA2 Y3 W4 V5 Y4 V6 W5 Y5 AA5 W6 V7 W7 Y7 P10 P15 N14 W20 V19 W21 U18 T18 U19 U20 N15 U21 T19 T20 R19 R18 V17 AA21 Y19 AA20 W19 Y20 P3 P2 P4 P7 J15 J20 H19 N3 N8 N4 N7 L14 E5 E MCLK TP3126 SYSCLK1 SYSCLK2 PWRRSTn R2104 100K R2109 47 RESOUT0n RESOUT1n TP2102 RESOUT3n C 100K P_MODE R2105 C2104 1000p 130K NA PWRREQn ISSYNCn ISEVENTn MCLK SYSCLK0 SYSCLK1 SYSCLK2 SERVICE_N RESPOW_N RESOUT0_N RESOUT1_N RESOUT2_N RESOUT3_N RESOUT4_N CLKREQ PWRREQ_N ISSYNC_N ISEVENT_N IRQ0_N GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 DACCLK DACDAT DACSTR ADCSTR USBDP USBDM USBPUEN DIRMOD0 DIRMOD1 DIRMOD2 DIRMOD3 DCLK IDATA QDATA TXON RXON RFCLK RFSTR RFDAT BANDSEL0 BANDSEL1 ANTSW0 ANTSW1 ANTSW2 ANTSW3 PCTL R3100 NA Q2100 RN1107 R2102 CLKREQ BL_PWL 7C_LED_VDD_EN CAMERA_DET GPIO05 AMPCTRL TGBUZZ UARTRX0 UARTTX0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VMEM CS 0.8 PITCH 9 X 12 X 1.0 NMBI TOSHIBA U8100 PT V1.1u C2259 0.22u 50V 1608 IrDA 8 SHIELD C3137 VCC SD RXD TXD LEDK LEDA 6 0.240 - .1u C2253 0.1u C2247 0.8 PITCH 9 X 12 X 1. 64/64/16 64/64/16 64/64/16 64/64/16 64/64/16 64/64/16 64/64/16 64/64/16 64D/64D/16PS 128L/128L 64/64/16 64/64/16 128/128/64 128 0.3 Staggered AMD H Drawn by: SUNG-JU.4 0.1u C2256 0.22u 50V 1608 RFU12 RFU13 RFU14 RFU15 RFU16 RFU17 RFU18 RFU19 RFU20 RFU21 MEM_BE1_N MEM_BE0_N D4 C4 G3 VSS1 J9 VSS2 L4 VSS3 C3133 NC3 NC4 0.1u 0.8 PITCH 10 X 8 X 1.4 0.1u C2244 0.8 PITCH 10 X 8 X 1.1u TP3313 H9 K2 K6 K9 L2 L3 L6 L7 L8 L9 VMEM RB521S-30 TP3117 TP3118 TP3115 TP3116 TP3111 TP3112 TP3113 TP3114 VPPFLASH V2203 UART0 D IRQ0n DAT(5) DAT(6) DAT(7) DAT(8) DAT(9) DAT(10) DAT(11) DAT(12) DAT(13) DAT(14) DAT(15) M1 M10 UART1 VDIG R2301 NA UARTRX1 UARTTX1 UARTRTS1 UARTCTS1 CAM_REG_EN CAM_FLASH_ON TP2125 D CAM_FLASH_SHOT D2000 ROP-101-3035_1 PULSESKIP MARITA R3319 KEY_LED_ONOFF LCDVSYNCI SPKMUTE CS0_N CS1_N CS2_N CS3_N WE_N OE_N MEMBE0_N MEMBE1_N MEMADV_N MEMCLK MEMWAIT_N PDIRES_N PDIC0 PDIC1 PDIC2 PDIC3 PDIC4 PDID0 PDID1 PDID2 PDID3 PDID4 PDID5 PDID6 PDID7 I2CSCL I2CSDA CIPCLK CIVSYNC CIHSYNC CIRES_N CID0 CID1 CID2 CID3 CID4 CID5 CID6 CID7 MEM_CS0_N MEM_CS1_N MEM_CS2_N MEM_CS3_N MEM_WE_N MEM_OE_N MEM_BE0_N MEM_BE1_N MEM_ADV_N MEM_CLK ADR(1:24) ADR(24) TP3344 VMEM 1K MEM_WAIT_N LCDRESX LCDCSX_SUB LCDWRX LCDRS LCDCSX_MAIN LCDRDX PDID0 PDID1 PDID2 PDID3 PDID4 PDID5 PDID6 PDID7 E USBSENSE BL_EN FOLDER_DET EN_LED_R EN_LED_G EN_LED_B IRDA_REG_CTRL DACCLK DACDAT DACSTR ADCSTR USBDP USBDM USBPUEN HSSLRXCLK HSSLRX HSSLTXCLK HSSLTX TP2404 TP2405 TP2401 TP2402 TP2403 E R3320 R3321 D2012 1SS388 ADDRESS X DATA = 2^23 X 2^4 = 2^27 = 128MBIT A1 A2 A7 A8 B1 B2 B7 B8 C1 C8 E8 H7 LCD I/F VDIG R2304 3.8V VMEM 3.25 0.1 Staggered AMD 128/128/64 128 128/128 128/128/64 128 128/128/64 128 128/128/64 0 128 0.1u C2222 0.1u C3135 C3134 0.8 PITCH 9 X 12 X 1.5V VDDC 1.8V 2.9.4 0. H:SHUTDOWN) LOW POWER MODE : LEDA VCC Engineer: SUNG-JU.75V VDIG VDDC 1.3K R2121 NA A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 F 100K NA VMEM R3126 R3127 R2622 RESOUT0n 100K 100K D1 VCC1 J5 VCC2 F8 VIO1 H1 VIO2 G8 VSS1 J1 VSS2 K2 VSS3 K7 VSS4 G JTAG I/F KEYOUT0 KEYOUT1 KEYOUT2 KEYOUT3 KEYOUT4 KEYOUT5 KEYIN0 KEYIN1 KEYIN2 KEYIN3 KEYIN4 PCMCLK PCMSYN PCMDATA PCMDATB MARITATCK MARITATMS MARITATDI MARITATDO MARITATRST MARITARTCK MARITATEMU0 MARITATEMU1 N3100 CIM-80S7B-T GND 7 1 2 3 I2CCLK Q3202 PMST3904 RTC_GND 470 MEM_WAIT_N MEM_ADV_N MEM_CLK MEM_OE_N MEM_WE_N G C3276 0.7K R3329 4. YOU LG ELECTRONICS INC.1u C2242 0.8 PITCH 14 X 8 X 1.1u C3222 0.47u 5 4 R3346 3 2 1 1608 KEY I/F PCM I/F VPPFLASH 27 H8 J8 K1 K8 L1 L2 L7 L8 M1 M2 M7 M8 NC13 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 H SIR TRANCEIVER SD(L:ACTIVE.1u C2220 0.8 PITCH 10 X 8 X 1.8 PITCH 9 X 11.768KHz 0.4 0.1u C2246 Rout track on inner layer DAT(0:15) DAT(15) DAT(14) DAT(13) A1 A10 B3 B6 B7 B8 B9 C9 F5 F6 G5 G6 G8 0 ADR(1:24) A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 F9 E9 E6 D7 E4 F4 G9 D9 F8 E8 D8 C8 F7 E7 C7 C3 D3 E3 F3 D2 E2 F2 G2 ADR(23) ADR(22) ADR(21) ADR(20) ADR(19) ADR(18) ADR(17) ADR(16) ADR(15) ADR(14) ADR(13) ADR(12) ADR(11) ADR(10) ADR(9) ADR(8) ADR(7) ADR(6) ADR(5) ADR(4) ADR(3) ADR(2) ADR(1) TP3317 100 DAT(12) B TP2106 RTC_GND 0 DAT(11) DAT(10) DAT(9) DAT(8) W10 RTCBDIS_N V11 RTCIN W11 RTCOUT P12 RTCDCON W12 RTCCLK ADR(1:24) C17 B17 G13 C16 C15 B15 H12 D14 B14 C14 G12 B13 C13 H11 D12 C12 G11 D11 C11 H10 C10 D10 H9 C9 A7 B7 C7 D7 C6 B5 C5 D6 B4 C4 D5 B3 D4 C3 B2 A1 J8 H7 B10 D9 C8 D8 C1 D3 B9 G8 D2 NA D19 C19 D18 C20 C21 E18 B18 D17 C18 B19 A20 H13 G14 B20 Y2 W3 H18 H15 G21 E19 E20 E21 H14 F19 F20 G18 G19 G20 VDIG VCORE R2303 4.

Y SEOK LG ELECTRONICS INC. September 04. 2003 Time Changed: 2:11:39 pm QA CHK: REV: Drawing Number: Page: 7 1 2 3 4 5 6 7 8 9 10 11 12 .1u 0.7K 20p 20p 20p 20p D2007 GND GND GND B2 B2 B2 B2 GND C D2009 20p CURRENT LIMIT 15mA x 16 = 240mA CAMERA I/F KEYPAD BACKLIGHT BLUE LED I/F D D B'd to B'd CONNECTOR I/F HF DETECTION Q3201 4 VDIG R3210 NA 3 DCIN_2 TP3200 VBATI U3102 1 IN 2 GND 3 EN OUT ADJ 5 R3332 240K 4 5 R3353 R3352 R3351 R3350 NA NA NA NA UMC4N CAM_REG_EN R3344 MIC5219BM5 100K C3244 2.241 - .75V DTC SENSE TP3205 CAMERA_DET NA N3200 A3212ELH 1 VDD 3 GND OUT 2 L2500 1 6 D1 D4 2 5 3_3V GND 3 4 D2 D3 USBUF01W6 VBAT USBDP C3205 10p R3341 C3204 0.9.1u 0.3 Staggered AMD H I/O CONNECTOR Drawn by: S .1u HF SPK P TP3204 R3227 R3228 R2502 0 0 E CRS08 V3200 NA VBUS 0 VCAM V2500 R3229 R3230 0 0 1K VBATI RB521S-30 NA UARTRTS1 R2319 G R3206 UARTRX1 R2503 100K R2500 PCMDATB NA R3232 R3233 0 NA G R3235 R3236 NA 2. CIRCUIT DIAGRAM 1 2 3 4 5 6 7 8 9 10 11 12 VBATI A CONN_10_5087_060_920_829 X3200 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 VDIG VBATI A ONSWAn KEYIN0 KEYIN1 KEYIN2 KEYIN3 KEYIN4 7C_LED_VDD CAM_FLASH_ON CAM_FLASH_SHOT CID4 BL_PWL FOLDER_DET KEY_LED- C3200 1u 1608 X3201 PDM : ENBY0017602 AXK7L80225 VCAM R3388 R3263 4.1u C3212 1000p C3213 1000p C3219 1000p 100K 0.Y SEOK R&D CHK: DOC CTRL CHK: MFG ENGR CHK: Changed by: mentor Date Changed: Tuesday.01u USBDM R3237 0 C3215 0 33u 3216 C2208 1u 1608 R3398 C2304 C2500 C2279 R2504 R2501 NA NA SP3205 SP3200 SP3206 SP3207 SP3201 SP3208 SP3202 SP3209 SP3203 SP3210 SP3211 SP3204 SP3212 6 5 4 3 SMF05C USB FILTER H GND CAMERA ROTATION DETECTOR UARTTX1 2 V3201 D5 D4 D3 D2 D1 USBPUEN 1 NA Engineer: S . DEVELOPMENT GROUP1 TITLE: Size: A2 BB MAIN PCB MULTIMEDIA INTERFACE 12 1 8 A U8100 PT V1.7 SC600B N3201 1 2 3 4 VOUT CF1+ VIN FID0 FID1 SC600BIMSTR CF2+ CF1GND CF2EN 10 9 8 7 6 R3389 100 D2013 1SS388 C3201 1u 1608 7C_LED_VDD 0 G3 10 G4 11 12 13 14 15 16 17 18 R3366 R3367 51 R3364 R3365 51 FB2 1608 C3202 10u 2012 CID5 CIVSYNC CID1 R3357 51 9 8 5 7C_LED_VDD_EN EN_LED_TC B B CHARGE PUMP C3203 1u 1608 R3390 100 D2014 1SS388 I2CCLK_CAMERA 7 51 EARM EARP BL_EN MOTOR_BATT SPKP SPKM LCDCSX_SUB LCDRESX LCDVSYNCI LCDWRX LCDRS LCDCSX_MAIN LCDRDX PDID0 PDID1 PDID2 PDID3 PDID4 PDID5 PDID6 PDID7 EN_LED_R EN_LED_G EN_LED_B KEYOUT0 KEYOUT1 KEYOUT2 KEYOUT3 KEYOUT4 KEYOUT5 MARITATEMU1 MARITATEMU0 MARITARTCK MARITATRST MARITATDO MARITATDI MARITATMS MARITATCK CID2 CIPCLK CID0 4 51 R3360 51 6 5 CIRES_N FB1 1608 CIHSYNC I2CDAT R3363 51 3 2 1 C3255 C3252 C3249 A3 C1 C3 A1 A3 C1 C3 A1 CID3 SYSCLK1 SUB LCD BACKLIGHT 4.2u 2012 C3243 470p R3252 R3331 300K N2300 VBAT C4 IP4022CX20 VBACKUP R3347 NA C3245 10u VDIG 1 VCAM KNATTE R3211 E NA E NA 2 VCC PDM : ENEY0003301 GT059-24P-3BL-P800 X3203 25 VBAT_GND_1 26 VBAT_GND_2 1 BATT_ID 2 HF_MODE 3 DSR 4 PWR_+5V_1 5 PWR_+5V_2 6 ON_SW1 7 PCM_RXA_IN 8 PCM_CLK 9 PCM_SYNC 10 USB_RX 11 PCM_TXA_OUT 12 PWR_GND_1 13 RXD 14 TXD 15 USB_TX 16 USB_PWR 17 DCD 18 RI_TMS 19 PWR_GND_2 20 RFR_RTS 21 PWR_+4_2V_1 22 PWR_+4_2V_2 23 CTS 24 DTR TP3307 27 V_BAT_1 5V 28 V_BAT_2 29 V_BAT_3 30 GND1 31 GND2 100K TP3342 TP3341 F TP3306 GND5 GND4 GND3 GND2 GND1 CAMERA REGULATOR UARTCTS1 UARTRX1 UARTTX1 UARTRX0 UARTTX0 VPPFLASH ONSWBn DCIN_3 D2 D3 C3 D4 TP3337 D5 TP3336 D1 C5 DTMS_i DFMS_i CTMS_i CFMS_i VPPFLASH_i CTS_ON_i DCIO_i DTMS_e DFMS_e CTMS_e CFMS_e VPPFLASH_e CTS_ON_e DCIO_e A1 A2 A3 A4 A5 B1 B5 TP3338 TP3339 TP3343 TP3340 PCMCLK PCMSYN R3220 R3249 R3222 NA 0 NA BLM18PG121SN1 L2201 F R3223 HF MIC TP3202 R3225 0 NA R2505 C2 C1 B4 B3 B2 NA PCMDATA C B HF SPK N TP3203 Q2300 RN1107 C3220 0. 3G HANDSETS LAB.5V CID6 19 CID7 20 C3261 C3260 C3259 A1 A3 C1 C3 A1 A3 C1 C3 G1 CSPESD304 G2 CSPESD304 D2008 CSPESD304 D2018 CSPESD304 C3258 ESD1 ESD2 ESD3 ESD4 ESD1 ESD2 ESD3 ESD4 ESD1 ESD2 ESD3 ESD4 ESD1 ESD2 ESD3 20p 20p ESD4 KEY_LEDR3207 12 R3208 12 EMX18 Q3200 1 2 3 6 5 4 KEY_LED_ONOFF C R3209 2.

5V 1.1u C2238 0.3K C3265 47p D E U3 EMIF_AWE_N T3 EMIF_ARE_N U2 EMIF_AREADY N12 EXT_MEM_UBUS10 T14 EXT_MEM_UBUS11 R14 EXT_MEM_UBUS12 E17 EXT_FRAME_STROBE CLK INTERFACE D15 TESTMODE E11 ANALOG_ENABLE C11 APLL_BYPASS A11 CS_BYPASS F TP2119 TP2116 C17 BOOTMODE0 B17 BOOTMODE1 E13 BOOTMODE2 C15 BOOTMODE3 VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSSA_CS_APLL VSSA_RX VSSA_TX VSSA_BG VINCENNE INTERFACE DACCLK DACDAT DACSTR U11 L17 K13 K15 K16 J15 J13 H15 H13 GPO0 GPO1 GPO2 GPO3 GPO4 GPO5 GPO6 GPO7 N6 CPU_IACK R5 CPU_XF N7 CPU_IRQ1 R6 CPU_IRQ0 M17 CPU_CLKOUT F TP2120 1% R2400 43K C2215 0.5V VCORE 1.1u C2230 0. DEVELOPMENT GROUP 1 TITLE: Size: A2 BB MAIN PCB 12 1 8 A WANDA U8100 PT V1.5V 1.1u C2234 0. CHO LG ELECTRONICS INC.1u C2240 0.1u C2241 0.1u C2236 0.242 - .1u C 100K C R2402 100K B1 D2 G1 K2 M1 R1 T2 U5 R13 U16 R16 N17 K17 H17 F17 D16 A17 B14 A12 B8 A6 A3 L15 R12 T17 U6 U10 R11 VDIG VCORE G16 G17 G15 F16 G13 E15 F13 JTAG_TRSTN JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO EMU1 EMU0 VDD21 VDD20 VDD19 VDD18 VDD17 VDD16 VDD15 VDD14 VDD13 VDD12 VDD11 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 VDD0 VDD_DPLL VDDA_CS_APLL VDD_CLK32 VDDA_TX VDDA_RX VDDA_BG B2 EMIF_A23 E5 EMIF_A22 A1 EMIF_A21 A2 EMIF_A20 B3 EMIF_A19 C4 EMIF_A18 B4 EMIF_A17 E6 EMIF_A16 C6 EMIF_A15 A5 EMIF_A14 E7 EMIF_A13 B6 EMIF_A12 C7 EMIF_A11 A7 EMIF_A10 A8 EMIF_A9 E8 EMIF_A8 C8 EMIF_A7 E9 EMIF_A6 C9 EMIF_A5 B9 EMIF_A4 C10 EMIF_A3 A10 EMIF_A2 E10 EMIF_A1 D RF CONTROL 3 2 Q3204 PMST3904 1 WCLK WDAT RXIA RXIB RXQA RXQB ADCSTR TXIA TXIB TXQA TXQB C2400 WSTR R17 RADIO_CLK P15 RADIO_DAT M13 RADIO_STR R10 N10 R9 T9 T10 N9 0. 3G HANDSETS LAB.7K 3.1u C2225 0.1u C2233 0.1u C2224 0.1u C2232 0. 2003 Time Changed: 9:42:54 am QA CHK: REV: Drawing Number: Page: 8 1 2 3 4 5 6 7 8 9 10 11 12 .1u M16 N8 U8 U7 R7 T7 ADC_I_IN ADC_I_IN_INV ADC_Q_IN ADC_Q_IN_INV ADC_RXEXTREF_P ADC_RXEXTREF_N AD_STR R3326 RF RX DATA NA D2006 DAC_I_OUT DAC_I_OUT_INV DAC_Q_OUT DAC_Q_OUT_INV DAC_TXEXTRES RF TX DATA E ROP-101-3033_1 HSSL LINK (MARITA) HSSLTX HSSLRXCLK HSSLRX HSSLTXCLK ISSYNCn ISEVENTn MCLK RTCCLK CLKREQ RESOUT1n C2103 330p B16 HSSLRX_D A16 HSSLTX_CLK A15 HSSLTX_D C14 HSSLRX_CLK D4 ID_BALL A13 IS_SYNC_N B12 IS_EVENT_N U12 APLL_ATEST1 U13 MCLK T16 CLK32 R15 HCLK T15 CLKRQ N13 RESET_N N15 DAC_CLK L13 DAC_DAT M15 DAC_STR BG_REF E12 UART_TX C13 UART_RX EMIF_D0 EMIF_D1 EMIF_D2 EMIF_D3 EMIF_D4 EMIF_D5 EMIF_D6 EMIF_D7 EMIF_D8 EMIF_D9 EMIF_D10 EMIF_D11 EMIF_D12 EMIF_D13 EMIF_D14 EMIF_D15 EMIF_D16 EMIF_D17 EMIF_D18 EMIF_D19 EMIF_D20 EMIF_D21 EMIF_D22 EMIF_D23 EMIF_D24 EMIF_D25 EMIF_D26 EMIF_D27 EMIF_D28 EMIF_D29 EMIF_D30 EMIF_D31 C2 C1 F5 E3 G5 E1 F2 F1 G3 G2 H5 H1 H2 J2 J3 J5 K3 K5 K1 L1 L3 M2 L5 N1 M3 M5 P2 P3 R2 T1 N5 U1 R3383 R3380 2.1u C2228 0.1u C2235 0.1u C2237 0.1u C2231 0.1u R2401 B C2229 0. CHO R&D CHK: DOC CTRL CHK: MFG ENGR CHK: Changed by: mentor Date Changed: Tuesday.5V VEXT15 WANDAVDDA VCORE WANDAVDDD VCORE VRTC VEXT15 A R2224 R2236 0 0 B C2227 0.9. September 04.1u C2226 0.3 Staggered AMD H Drawn by: MYUNG-LAE. CIRCUIT DIAGRAM 1 2 3 4 5 6 7 8 9 10 11 12 A 1.1u C2239 0.1u R2120 NA TP2320 TP2321 TP2117 G TP2322 TP2118 D3 F3 H3 L2 N3 R3 R4 T4 U15 U17 P16 L16 J16 H16 F15 C16 B15 C12 B11 B10 B7 C5 C3 T6 T12 N11 T8 R8 T11 G H Engineer: MYUNG-LAE.

2003 Time Changed: QA CHK: REV: Drawing Number: Page: 1 1 2 3 4 5 6 7 8 9 10 11 12 .8V HSMR-C191 R1130 100K QSMR-C138 LD2 QSMR-C138 LD3 QSMR-C138 LD6 QSMR-C138 LD5 QSMR-C138 LD8 QSMR-C138 LD11 QSMR-C138 LD13 QSMR-C138 LD4 QSMR-C138 LD9 QSMR-C138 LD14 QSMR-C138 LD10 QSMR-C138 LD12 QSMR-C138 LD16 QSMR-C138 LD17 QSMR-C138 LD7 FOLDER_DET QSMR-C138 LD18 QSMR-C138 LD19 QSMR-C138 LD20 C26 0.2V KEYPAD VDIG_2.09 Date Changed: FEB.01.02. 3G HANDSETS LAB.8V 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CN962 ONSWAn KEYIN0 KEYIN1 KEYIN2 KEYIN3 KEYIN4 ONSWAn KEYIN0 KEYIN1 KEYIN2 KEYIN3 CAM_FLASH_ON EARP EARM EN_LED_R EN_LED_B R1152 R1151 270 270 CONN_40_AXK840145J CAM_FLASH_ON CAM_FLASH_SHOT BL_PWL FOLDER_DET KEY_LED- C27 C28 47p 47p C29 C30 C31 C32 C33 C34 AVL14K02200 AVL14K02200 30p 30p 30p 30p 30p 30p C23 C24 C22 470p 470p 470p INSTPAR KB1 KB6 KB11 KB16 KB21 LCDVSYNCI LCDWRX LCDRS LCDCSX_MAIN LCDRDX PDID0 PDID1 PDID2 PDID3 PDID4 PDID5 PDID6 PDID7 EN_LED_R EN_LED_G EN_LED_B KEYOUT0 KEYOUT1 KEYOUT2 KEYOUT3 KEYOUT4 KEYOUT5 MARITATEMU1 MARITATEMU0 MARITARTCK MARITATRST MARITATDO MARITATDI MARITATMS MARITATCK R1097 LCDRESX NA R1145 R1140 R1141 R1142 R1143 R1144 100 100 100 100 100 100 C35 C36 C37 C38 C39 C40 LCDCSX_MAIN LCDRESX LCDVSYNCI LCDCSX_SUB LCDRS LCDRDX UCLAMP0501H TVS2 LCDCSX_SUB AVL14K02200 INSTPAR 470 UCLAMP0501H EARM EARP BL_EN MOTOR_BATT SPKP SPKM VA1 VA2 VA3 TVS1 BL_PWL PDID1 PDID3 PDID5 PDID7 LCDWRX R1134 R1135 R1136 R1137 R1138 R1139 100 100 100 100 100 0 30p 30p 30p 30p 30p 30p PDID6 PDID4 PDID2 PDID0 BL_EN EN_LED_G R1146 R1147 R1148 R1149 R1150 R1153 100 100 100 100 100 270 C43 C44 C45 C46 C41 C42 40 39 38 VBATI_4.9.11.3 BB KEY PAD PCB 2004.8 U8100 KEY PT V1. CIRCUIT DIAGRAM 1 2 3 4 8 9 10 11 12 A VBATI_4.1u C25 0.18 LCDRESX PULL DOWN R MOVE TVS VDIG KEYOUT4 2004.14 ESD EMI FILTER -> RC Filter SEND KB5 CLEAER KB10 BACK KB15 GAME KB20 LEFT KB25 KEYOUT5 MENU F SEARCH MULTI CAM OK F VBATI_4.2V A B C D 64 63 62 61 60 59 58 7C_LED_VDD 57 56 55 54 53 52 51 VDIG_2.1u R1098 R1099 R1133 R1100 R1131 36 36 47 36 36 KEY_LED- FOLDER OPEN DETECTOR U1 A3212ELH 1 VDD 3 GND OUT 2 G QSMR-C138 LD1 C21 10p G H Engineer: KEYPAD BACKLIGHT BLUE LED LG ELECTRONICS INC.2V 37 36 35 34 33 32 31 30 29 28 VDIG_2.1 2003.8V 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 7C_LED_VDD 10 9 8 7 6 5 4 3 2 1 CN963 KEYIN4 U8100_SIDEKEY_PAD KB26 D1 B SIDE1 SIDE2 SIDE3 R1103 470 R1102 470 R1104 END 1SS388 CN964 1 2 3 4 R1154 470 KEYOUT0 KEYOUT1 C 1 4 7 * UP KB2 KB7 KB12 KB17 KB22 KEYOUT2 2 5 KB8 8 0 DOWN D KB23 30p 30p 30p 30p 30p 47p KB3 KB13 KB18 SPKM SPKP MOTOR_BATT CAM_FLASH_SHOT 1 3 4 5 D1 D2 D3 D4 D5 6 KEYOUT3 NA D2 2 GND 3 TOSHIBA LCD I/F KB4 6 KB9 9 # RIGHT SMF05C BOARD TO BOARD CONECTOR E KB14 KB19 KB24 E U8100 KEY V0. DEVELOPMENT GROUP 1 TITLE: Size: A2 12 1 8 A H Drawn by: R&D CHK: DOC CTRL CHK: MFG ENGR CHK: Changed by: mentor U8100 KEY PT V1.17.243 - .

244 - .10. PCB LAYOUT .

10.245 - . PCB LAYOUT .

10.246 - . PCB LAYOUT .

PCB LAYOUT .10.247 - .

EXPLODED VIEW & REPLACEMENT PART LIST 11.1 EXPLODED VIEW .248 - .11.

MASTER(for U8110 HUK) BOX.0x4.5x3.SHELL MLAQ0001601 MPAD0004601 MPAD0004602 PACKING.2t N -249- .UNIT(for U8110 HUK) LABEL.UNIT LABEL.MASTER BOX.SHELL(for U8110 HUK_Lower(Bottom)) Y Y Y 3 3 3 MPBZ00 MPCY00 MPCY01 PAD PALLET PALLET MPBZ0043101 MPCY0009501 MPCY0010901 PAD(for H3G_Substitute for H3G Manual) PALLET(G7100 for Orange UK_EUR) PALLET(for H3G Main package_Cap) Y N N 3 2 3 2 3 3 4 5 5 5 5 5 5 5 5 5 5 4 5 5 MPCY02 AMBA00 MMBB00 APEY00 ABGA00 ACGG00 ACGH00 MCCZ00 MCJH00 MDAC00 MDAH MDAH00 MGAD00 MMAZ00 MTAA MTAA00 MTAA01 ACGJ00 MCJJ00 MDAY00 PALLET MANUAL ASSY.K.SHIELD FORM MAGNET TAPE.2 Replacement Parts <Mechanic component> Level Location No.05t x 85 x 195) BAG(for G5300iVDF to pallet)(255*325) BOX.11.MASTER BOX(G4010 for Cingular) Specification SVC N N Y Y N Y N Color Silver Silver Dark Blue Silver Silver Silver Metalic Silver Dark Gray Silver Dark Blue Dark Blue Black Dark Blue Dark Blue Remark 3 3 3 MLAQ00 MPAD00 MPAD01 LABEL.DECO TAPE.RECEIVER GASKET.MASTER BOX Part Number TIFF0001002 ABEZ0037901 MBAD0005201 MBAZ0002401 MBEE0044101 MBEF0053401 MLAJ0002201 BOX ASSY(for U8110 HUK) BAG.FOLDER COVER ASSY.0 KW2000 FOLDER LOWER D3*1.VINYL(PE)_GSM Phone(LDPE 0.DIAL COVER ASSY.SHELL(for U8110 HUK_Upper(Top)) PACKING.DECO TAPE.2t INNER_2 OUTER DECO_1 5. 1 2 3 3 3 3 3 ABEZ00 MBAD00 MBAZ00 MBEE00 MBEF00 MLAJ00 Description IMT.DECO COVER ASSY.FOLDER BOX ASSY BAG.FOLDER(UPPER) DECO MPCY0010902 AMBA0030501 MMBB0113401 APEY0070022 ABGA0002401 ACGG0033302 ACGH0012002 MCCZ0005402 MCJH0009603 MDAC0006301 MDAH0002001 MDAH0001901 MGAD0035201 MMAZ0000101 MTAA0023301 MTAA0023101 MTAA0023201 ACGJ0028701 MCJJ0021501 MDAY0006801 PALLET(for H3G Main package_Angle) U8110 Manual ASSY for Hutchison in U.UNIT BOX PACKING. U8110 User Manual for Hutchison in UK U8110 HUKSV N Y Y N Y Y Y N N Silver Silver Silver Silver M18 M40 M11 Silver Silver Silver Silver Gold M7 0.5t DECO SIDE DECO RECEIVER OUTER DECO RECEIVER INNER N N N Y Y Y Y Y Y N Silver Silver M2 0.OPERATION MANUAL.SHELL PACKING.VINYL(PE) BAG BOX.OPERATION PHONE BUTTON ASSY.FOLDER(UPPER) COVER.RECEIVER DECO.SIDE DECO.FOLDER(LOWER) DECO.FOLDER(LOWER) CAP COVER.

LCD VIBRATOR.MSWR3(FN) .2t Y Y Y Y Y N N N N N N Y N N N Y Y Y Gray Silver Silver Gold M8 M9 Brown Silver Silver Silver M17 Silver Black 5.3 0. U8120 KW2000.0 .FRONT BUTTON.FRONT(LOWER) WINDOW.CHIP RES.1/16W.5 FOLDER N 4 4 4 GMZZ00 MCCH00 MDAF00 SCREW MACHINE CAP.LCD Part Number MFBC0007401 MICA0001201 MPBG0018201 MPBQ0013101 MTAE0013301 ACGK0020902 MBJL0008102 MCCC0007801 MCJK0014602 MICB0000601 MWAG0002301 ALAY0005301 AFBZ0004402 MFEZ0002302 MPBG0010602 MPBS0002301 MGAD0044101 MGAD0035201 SACY0016001 EDLM0004301 ERHY0000203 ERHY0000203 ERHY0000203 SPCY0026701 AWAB0009201 0.1/16W.3t 2.R/TP .LCD PAD.G8000 VIBRATOR DECO FOLDER LOWER KW2000.3t 55.LCD PAD.3.5 mm.3.SIDE CAP.MOTOR MHFD0006901 MTAA0023401 MTAB0036801 MTAB0020101 MWAC0025801 SJMY0004201 3 V.Level Location No.LCD(SUB) MWAF0017001 3.DECO TAPE.5*3.FRONT PAD.SHIELD FORM PCB ASSY. DIA = 1.EARPHONE JACK COVER..CHIP PCB.SPEAKER INSERT. IN-MOLD Y Y Y Y Y Y Dark Blue Dark Blue Dark Blue Silver Gray Metalic Silver Metalic Silver M12 M13 M16 M1 5 BFAA00 FILM.FLEXIBLE DIODE.STR .FOLDER GASKET.J.7mm+2.R/TP 10 ohm.2t Specification SVC Y Color Remark LG-G510.J.PROTECTION TAPE.CHIP RES.FOLDER LOWER Y Y Y Y Y Y M10 M15 M14 M4 -250- .FOLDER TAPE.N .7X3.SHIELD FORM GASKET.R/TP POLYI .511.IRDA LCD ASSY FRAME ASSY FRAME PAD.2t_LCD 0. U8110. mm.DOUBLE .12*3.0x4.MODULE RES.1005.FOLDER(LOWER) GMZZ0003201 MCCH0012101 MDAF0003203 Y Y Y 4 4 4 4 4 4 MHFD00 MTAA00 MTAB MTAB00 MWAC00 SJMY00 HINGE.4 .512 common use.80*41.R/TP 10 ohm.5x3.SCREW DECO.3 LED..PROTECTION WINDOW.MINI FLASH LED 10 ohm.LCD(SUB) TAPE.WINDOW(SUB) COVER ASSY.5 DIA3. 5 5 5 5 5 4 5 5 5 5 5 4 5 6 6 6 5 5 5 6 6 6 6 6 4 MFBC00 MICA00 MPBG00 MPBQ00 MTAE00 ACGK00 MBJL00 MCCC00 MCJK00 MICB00 MWAG00 ALAY00 AFBZ00 MFEZ00 MPBG00 MPBS00 MGAD0 MGAD00 SACY00 EDLM00 R1 R2 R3 SPCY00 AWAB00 Description FILTER.0 KW2000 FOLDER LOWER WHITE . M1.LED.12 A.1/16W.5*1.FRONT INSERT.FLEXIBLE WINDOW ASSY.5 mm.1005.INMOLD BFAA0014001 Dark Blue N 5 MWAF00 WINDOW.0.1005. U8100.80 t0.J.

REAR CONTACT ASSY.LOCKER COVER ASSY.SHIELD FORM INSULATOR INSULATOR LOCKER.CAMERA DECO.7X3.CAMERA(FRONT) COVER.MSWR3(FN) .2t_LCD Specification 8 ohm.BATTERY LOCKER.3.108 dB. M1.ANTENNA COVER.REAR DECO..BATTERY PAD.CAMERA(FRONT) MAGNET SPRING TAPE.15t RIGHT LEFT 2.ETC SCREW MACHINE CAP. SVC Y Y Y Color Remark M3 M5 Silver M33 LG-G510.CAMERA WINDOW. MAIN REAR Y Y Y Y N N N N Y Y Y N N N N N N N N N N N Y Y Y Silver Silver Silver Silver Black Metalic Silver Silver Silver Silver Metalic Silver Gold Silver White Silver M27 M31 M29 M24 M25 M26 M30 M35 M37 M36 M39 M23 Silver M41 M28 Silver Silver Silver Dark Blue Silver Silver Silver Silver M6 MWAE0000301 0.19 mm.BATTERY FRAME.5 mm.Level Location No.REAR GASKET.CAMERA SPRING.5t SMZY0006501 GMZZ0003201 MCCF0008501 MCCH0012201 MCJA0004202 MFEA0003501 MLAK0007202 REAR VGA CMOS CAMERA MODULE 3.N ..STR .2t 0.CAMERA COVER ASSY.32 ohm..SHIELD LABEL.MODEL Part Number SUVT0002701 SVLM0005401 ACGM0017802 ACFY0000501 MCJN0011802 MDAK0001102 MGAD0044101 MIDZ0039401 MIDZ0036101 MLEA0008901 MLEA0008801 MPBT0004601 MSDC0003901 ACGN0001101 ACGP0000301 MCJP0000901 MMAZ0000301 MSDZ0000801 MTAA0035901 MBIC0000201 MBIZ0001301 MCCK0000301 MDAD0002501 MDAD0002601 Cr 2500 Gauss (+-500) 0.511.SCREW COVER.512 common use.CAMERA DECO.5 Y Y Y Y -251- .MOBILE SWITCH CAP.5 mm. 4 4 3 4 4 4 4 4 4 4 4 4 4 3 4 5 5 5 5 4 4 4 4 4 4 4 3 3 3 3 3 3 SUVT00 SVLM00 ACGM00 ACFY00 MCJN00 MDAK00 MGAD00 MIDZ MIDZ00 MLEA MLEA00 MPBT00 MSDC00 ACGN00 ACGP00 MCJP00 MMAZ00 MSDZ00 MTAA00 MBIC00 MBIZ00 MCCK00 MDAD00 MDAD01 MWAE00 SMZY00 GMZZ00 MCCF00 MCCH00 MCJA00 MFEA00 MLAK00 Description TWO-WAY MODE SPEAKER LCD MODULE COVER ASSY.90 dB.DECO BUSHING.2-WAY MODE SPEAKER for KW-2000 .CAMERA MODULE.CAMERA(LEFT) BUSHING CAP.5 DIA3.

CERAMIC.J.0.CERAMIC.1005.CHIP Part Number SAEY0025801 ADCA0010901 SAEA0010301 ECCH0000110 ECCH0000139 ECCH0000139 ECCH0000139 ECCH0000182 ECCH0000182 ECCH0000122 ECCH0000122 ECCH0000118 ECCH0000118 ECCH0000118 ECCH0000118 ECCH0000118 ECCH0000118 ECCH0000118 ECCH0000118 ECCH0000118 ECCH0000118 ECCH0000118 ECCH0000118 ECCH0000118 ECCH0000122 ECCH0000118 ECCH0000118 ECCH0000118 ECCH0000118 ENBY0004302 ENBY0013004 EDSY0010401 EDLH0004502 EDLH0004502 EDLH0004502 EDLH0004502 10 pF.X5R .R/TP 470 pF.HD.CHIP CAP.50V.LED.R/TP 30 pF.J.CHIP CAP.KEYPAD DOME ASSY.CERAMIC.NP0.50V.50V.BOARD TO BOARD CONNECTOR.4 mm.CERAMIC.1005.R/TP 30 pF.J.CERAMIC.R/TP 30 pF.NP0.R/TP 47 pF.50V. 1-1G1A .K .50V.LED.0.R/TP 30 pF.1005.TC.50V.X7R.50V.CERAMIC.TC.1005.CHIP CAP.CHIP CAP.NP0.R/TP 0.NP0.1005.J.50V.NP0.J.CERAMIC.CHIP CAP.K .50V.J.1608 .1608 .R/TP 30 pF.NP0.J.CHIP CAP.1005.50V.50V.R/TP 47 pF.50V.CERAMIC.R/TP 30 pF.CERAMIC.TC.CERAMIC.1005.1 uF.AUTO CAP.1005.R/TP 60 PIN.35T Specification SVC Y N N N N N N N N N N Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y N N N Y Y Y Y Color Remark M21 M19 -252- .5 mm.LED.CHIP CAP.TC.35T BLUE .CHIP CAP.50V.CERAMIC.50V.CERAMIC.NP0.1005.NP0.CHIP CAP.CERAMIC.TC.1005.35T BLUE .R/TP .1005.TC.1005.D.R/TP 30 pF.1005.K.50V.50V.35T BLUE .1005.50V.1005.CHIP CAP.R/TP 30 pF.NP0.STRAIGHT .TC.R/TP .CHIP CAP.R/TP .1005.TC.J.TC.SWITCHING DIODE.CERAMIC.50V.CERAMIC.METAL PCB ASSY.11.X7R.J.J.TC.CERAMIC.R/TP 470 pF.TC.CHIP CAP.HD.TC.0.0.50V.J.K.CHIP CONNECTOR.1005.X7R.0.R/TP 30 pF.CERAMIC.CHIP CAP.CERAMIC.TC.40 V.NP0.CERAMIC.NP0.TC.J.J.10V .NP0.CHIP CAP.J.Au .50V.TC.CHIP CAP.NP0.BOARD TO BOARD DIODE.TC.NP0.CERAMIC.R/TP 30 pF.1 uF.CERAMIC.R/TP 47 pF.R/TP 30 pF.R/TP .TC.J.J.J.R/TP 30 pF.CERAMIC.10V .CHIP CAP.TC.1005.CHIP CAP.R/TP 30 pF.CHIP DIODE.1005.NP0.TC.1005.Au over Ni . 3 4 4 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 SAEY00 ADCA00 SAEA00 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 CN962 CN963 D1 LD1 LD10 LD11 LD12 Description PCB ASSY.CHIP DIODE.1608 .CHIP CAP.CHIP DIODE.CHIP CAP.J.CHIP CAP.CERAMIC.NP0.CHIP CAP.1608 .ETC .R/TP 470 pF.NP0.1005.CHIP CAP.HD .1005.2 Replacement Parts <Main component> Level Location No.300 A.50V.NP0.R/TP 30 pF.1005 .CERAMIC.X5R .NP0.R/TP 30 pF.HD .1005.CERAMIC.R/TP .HD.R/TP 30 pF.0.CHIP CAP.TC.CHIP CAP.Silicon Epitaxial Schottky Barrier Type Diode BLUE .J.CHIP CAP.R/TP 30 pF.TC.K.J.B to B CNT(Socket) 40 PIN.1005.50V.1005 .R/TP 0.50V.50V.NP0.CERAMIC.KEYPAD.NP0.LED.

1/16W .1608 .CHIP DIODE.CHIP RES.1005.CHIP RES.35T BLUE .CHIP RES.CHIP RES.LED.CHIP RES.1005.35T BLUE .35T BLUE .1608 .1/16W.0.J.1/16W.R/TP 100 ohm.CHIP Part Number EDLH0004502 EDLH0004502 EDLH0004502 EDLH0004502 EDLH0004502 EDLH0004502 EDLH0004502 EDLH0004502 EDLH0004502 EDLH0004502 EDLH0004502 EDLH0004502 EDLH0004502 EDLH0004502 EDLH0004502 ERHY0006603 ERHY0006603 ERHY0006603 ERHY0000233 ERHY0000233 ERHY0000233 ERHY0000280 ERHY0006603 ERHY0000213 ERHY0000220 ERHY0000220 ERHY0000220 ERHY0000220 ERHY0000220 ERHY0000201 ERHY0000220 ERHY0000220 ERHY0000220 ERHY0000220 ERHY0000220 ERHY0000220 ERHY0000220 ERHY0000220 ERHY0000220 Specification BLUE .0. 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 LD13 LD14 LD16 LD17 LD18 LD19 LD2 LD20 LD3 LD4 LD5 LD6 LD7 LD8 LD9 R1098 R1099 R1100 R1102 R1103 R1104 R1130 R1131 R1133 R1134 R1135 R1136 R1137 R1138 R1139 R1140 R1141 R1142 R1143 R1144 R1145 R1146 R1147 R1148 Description DIODE.J .J.CHIP RES.1/16W .1/16W.CHIP DIODE.R/TP 470 ohm.CHIP RES.1/16W.LED.1608 .R/TP 100 ohm.1005.1608 .LED.1005.1608 .1005.1/16W.1/16W.CHIP RES.R/TP .CHIP RES.R/TP 100 ohm.1608 .R/TP 100 ohm.R/TP 100 ohm.1608 .R/TP .R/TP 470 ohm.R/TP SVC Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y N N N N N N N N N Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Color Remark -253- .0.R/TP 100 ohm.1/16W.J.LED.R/TP 100 ohm.CHIP DIODE.CHIP DIODE.35T BLUE .1/16W.CHIP RES.1005 .1005.R/TP 100 ohm.J.CHIP RES.CHIP DIODE.CHIP DIODE.CHIP RES.0.1005.1005.J.CHIP RES.R/TP 100 ohm.1005.1005.1/16W.35T BLUE .1608 .1005 .R/TP 470 ohm.R/TP 100 ohm.1/16W .1608 .1/16W.CHIP RES.CHIP DIODE.CHIP RES.35T BLUE .CHIP DIODE.1608 .35T BLUE .LED.1005.1005.J.0.LED.J .1005.1608 .CHIP RES.CHIP DIODE.1608 .J.R/TP .1608 .LED.CHIP RES.J.1005.1/16W.1/16W.0.0.R/TP .35T BLUE .R/TP .CHIP RES.1/16W.R/TP .1005 .1005 .CHIP DIODE.R/TP 100 ohm.1/16W.LED.0.1608 .J .1/16W.CHIP RES.R/TP .35T BLUE .J.R/TP 100 ohm.Level Location No.1005.LED.0.J.J.R/TP .J.35T BLUE .R/TP 36 ohm.CHIP DIODE.1/16W.J.R/TP .35T 36 ohm.1/16W.J.0.R/TP .CHIP DIODE.1005.R/TP 100K ohm.J .CHIP RES.CHIP RES.R/TP .LED.0.0.R/TP .0.R/TP .J.35T BLUE .CHIP DIODE.1005.1005.J.1608 .0.J.R/TP 36 ohm.LED.CHIP RES.R/TP 0 ohm.1005.CHIP RES.R/TP 36 ohm.J.1/16W.CHIP DIODE.R/TP 47 ohm.CHIP RES.J.1/16W.35T BLUE .R/TP .LED.R/TP 100 ohm.LED.R/TP .LED.1005.1/16W.35T BLUE .35T BLUE .0.R/TP 100 ohm.LED.J.1/16W .

CERAMIC.R/TP 10 nF.CHIP RES.R/TP 10 pF.CERAMIC.NP0.1/16W.TC.1005.1005.50V.1/16W.NP0.K.HD.50V.1005.CHIP CAP.1005.D.1005.K.SMD .CERAMIC. 14 V.CHIP CAP.CHIP CAP.50V.MAIN LABEL.CHIP CAP.3 .CHIP RES.CHIP CAP.16V.HD.CHIP EDTY0007301 EUSY0129501 SEVY0000702 SEVY0000702 SEVY0000702 SAKY0002602 SAFY0084201 MLAB0000601 SAFA0031301 EUSY0170601 EXXY0016801 EXXY0004601 ECCH0001001 ECCH0000110 ECCH0000155 ECCH0000155 ECCH0000155 ECCH0000110 ECCH0000155 ECCH0000110 ECCH0000110 ECCH0000143 ECCH0000115 ECCH0000115 ECCH0000115 ECCH0000110 ECCH0000110 ECCH0000110 ECCH0000115 ECCH0000155 N N N N N N Y M20 M32 HUMIDITY STICKER Y N SC70 .K.J.1/16W.10 pF.TC.J.TC.CERAMIC.5 V.NP0 .50V.HD. SOD-523 .J.50V.1005.240 W. 6.CERAMIC.CHIP RES.TC.40 ohm.4 mm.SMD .CHIP CAP.9*1.1005.D.J.1005 .CERAMIC.3 PIN.19 PPM.CERAMIC.5 V.CHIP CAP.MAIN.R/TP 22 pF.TC.1005.R/TP 10 nF.CERAMIC.50V.CERAMIC.D.R/TP .20*0.1005.50V. 0..65000 ohm.R/TP 10 pF.NP0.R/TP 22 pF.50V.16V.1005.CHIP CAP.50V.8 pF.CERAMIC.1005.1005.CERAMIC.K.1/16W.R/TP .J.1005.1005.CHIP CAP.J.CHIP CAP.CERAMIC.1005.10% .1005.R/TP 270 ohm.TVS IC VARISTOR VARISTOR VARISTOR PCB ASSY.R/TP N Y Y Y N N N N N N N N N N N N N N N N N -254- .NP0.R/TP 270 ohm.5 PIN.5*3.TC.NP0.CERAMIC.CERAMIC.K. 5 5 5 5 5 5 5 5 R1149 R1150 R1151 R1152 R1153 R1154 SPEY00 TVS1 RES.CERAMIC.HD.X7R.1/16W.TC .R/TP 10 pF.1005.1005.X7R.D.240 W.R/TP FR-4 .16V.50V .C . SVC Y Y N N Y Y N N Color Remark PCB.CHIP CAP.DOUBLE .SMD .50V.R/TP 470 ohm.Level Location No.CERAMIC.HD.TC.J.NP0.HD.D.50V.R/TP 10 pF.CERAMIC.X7R.32768 MHz.SIDEKEY PCB ASSY.1005.CHIP Description Part Number ERHY0000220 ERHY0000220 ERHY0000228 ERHY0000228 ERHY0000228 ERHY0000233 SPEY0019202 EDTY0007301 Specification 100 ohm.10% .TC.TC.NP0.R/TP 100 ohm.1005.HALL EFFECT SWITCH 14 V.1005.CHIP CAP.D.K.TC.R/TP 22 pF.16V.R/TP 22 pF.CHIP RES.50V.KEYPAD DIODE.NP0.TVS 5 5 5 5 5 4 3 4 4 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 TVS2 U1 VA1 VA2 VA3 SAKY00 SAFY00 MLAB00 SAFA00 B1501 B1770 B2100 C1000 C1001 C1002 C1003 C1004 C1005 C1007 C1008 C1009 C1010 C1011 C1012 C1013 C1100 C1101 C1102 C1103 C1104 DIODE.7 .SMD .X7R.J.R/TP 1 nF.CHIP CAP.AUTO IC X-TAL X-TAL CAP.SINGLE LINE TVS DIODE FOR ESD SOD-523 .4*1.6.CHIP RES.R/TP 10 nF.CERAMIC.X7R.A/S PCB ASSY.CHIP CAP. 14 V.12.NP0.R/TP .J.R/TP 10 pF.10% .R/TP 10 pF.R/TP 270 ohm.1005.R/TP 10 nF.5 pF.CHIP CAP.20 PPM.16V.X7R.R/TP 10 nF.SINGLE LINE TVS DIODE FOR ESD SC-74A FIT .D.CHIP CAP.R/TP .J.CHIP CAP.TC.1/16W.1005.TEMPERATURE SENSOR 13 MHz.R/TP 10 pF.NP0.SMD .NP0.

NP0.HD.R/TP 68 nF.1005 .CHIP CAP.R/TP 1.CHIP CAP.K.CHIP CAP.1005.TC.1005.50V .2012 .X5R.TC.K.R/TP 7 pF.Level Location No.HD .CHIP CAP.J.50V.CERAMIC.1005.CERAMIC.R/TP 68 nF.J.R/TP 33 pF.X5R .R/TP 22 pF.CERAMIC.3V.R/TP 330 pF.50V.NP0.CERAMIC.HD.CHIP CAP.50V.X5R.1005.J .1005.50V.R/TP 10 nF.TC .HD.1005.J.CERAMIC.K.16V.NP0 .NP0.1005 .X5R .50V .CHIP CAP.CERAMIC.CERAMIC.CERAMIC.R/TP 100 pF.1005 .CERAMIC.CERAMIC.R/TP 10 uF.1005.6.CHIP CAP.X7R.TC .1005.HD.3V.R/TP 68 nF.50V.CERAMIC.K.X7R.CHIP CAP.50V.R/TP 22 pF.CERAMIC.J.3V .50V.TC.X5R.R/TP 150 pF.X7R.6.K.CHIP Part Number ECCH0000186 ECCH0000186 ECCH0000186 ECCH0000115 ECCH0000108 ECCH0000165 ECCH0000165 ECCH0000165 ECCH0000165 ECCH0000165 ECCH0000155 ECCH0000155 ECCH0000155 ECCH0000155 ECCH0000115 ECCH0000115 ECCH0000155 ECCH0000140 ECCH0000137 ECCH0000144 ECCH0000146 ECCH0000143 ECCH0000143 ECCH0000165 ECCH0006501 ECCH0000155 ECCH0000115 ECCH0006501 ECCH0000139 ECCH0000139 ECCH0000130 ECCH0000144 ECCH0000128 ECCH0000128 ECCH0000186 ECCH0000115 ECCH0000115 ECCH0000186 ECCH0000110 Specification 33 pF.X5R.8 nF.HD.TC .50V.CERAMIC.CHIP CAP.K.6.CHIP CAP.50V.R/TP 10 nF.CHIP CAP.CHIP CAP.HD.J .J.X5R.TC.16V.X7R.1005.1005.CHIP CAP.CHIP CAP.R/TP 33 pF.50V .CHIP CAP.50V.CHIP CAP.CHIP CAP.3V.CERAMIC.R/TP 22 pF.TC.CHIP CAP.X7R .CHIP CAP.CERAMIC.J.1005.1005.R/TP 68 nF.6.NP0.K.TC.CERAMIC.16V.R/TP 10 nF.1005.NP0 .X7R.CERAMIC.R/TP 1.1005.R/TP 470 pF.HD.50V.CHIP CAP.16V.NP0.1005.1005 .6.NP0 .CERAMIC.J.CHIP CAP.TC.50V.CHIP CAP.3V .1005.X7R.K.K.K.CERAMIC.K.HD.CHIP CAP.50V.R/TP 100 pF.1005.CHIP CAP.3V.HD.TC .50V .D.CERAMIC.1005.X7R.J.TC .HD.CERAMIC.K.X7R.NP0 .R/TP 33 pF.2 nF. 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C1110 C1111 C1112 C1113 C1114 C1140 C1141 C1142 C1143 C1144 C1150 C1156 C1201 C1202 C1203 C1205 C1221 C1222 C1223 C1224 C1225 C1270 C1271 C1300 C1311 C1312 C1313 C1315 C1320 C1321 C1322 C1323 C1324 C1325 C1327 C1330 C1331 C1332 C1333 Description CAP.CHIP CAP.R/TP 10 nF.CERAMIC.NP0.CHIP CAP.K.SL.HD.CERAMIC.50V .NP0 .50V.1005.CHIP CAP.NP0.X7R.CERAMIC.CERAMIC.K.CHIP CAP.2012 .R/TP 68 nF.50V .1005.CERAMIC.R/TP 1 nF.1005.16V.NP0.1005.1005.1005.50V.CERAMIC.CERAMIC.CHIP CAP.1005.K.HD.HD.CERAMIC.D.K.CERAMIC.R/TP 68 nF.CHIP CAP.J .CHIP CAP.CERAMIC.CERAMIC.R/TP 10 nF.6.1005 .TC.1005 .CERAMIC.X5R.K .R/TP 33 pF.K .CERAMIC.HD.X7R.HD.3V.X7R.TC .R/TP 10 uF.K.CHIP CAP.50V.HD.CERAMIC.R/TP 10 nF.CHIP CAP.HD.J .6.2 nF.R/TP 1 nF.R/TP SVC N N N N N N N N N N N N N N N N N N N N N N N N Y N N Y N N N N N N N N N N N Color Remark -255- .TC.CHIP CAP.K .CHIP CAP.R/TP 22 pF.K.CERAMIC.HD.TC.1005.J.16V.50V.CHIP CAP.R/TP 22 pF.CHIP CAP.R/TP 1.1005.R/TP 560 pF.CERAMIC.X7R.NP0.K.NP0.CHIP CAP.3V.HD.K.1005.R/TP 10 pF.50V.TC.1005.TC .R/TP 470 pF.X7R.6.1005.R/TP 22 pF.HD.CERAMIC.X7R.50V.1005.J .CERAMIC.

CERAMIC.CERAMIC.CHIP CAP.R/TP 22 pF.X7R.1005.K.X7R.C.R/TP 33 pF.TC.R/TP 10 nF.CERAMIC.NP0.CERAMIC.1005.C.1005.CHIP CAP.CERAMIC.50V.16V.50V.D. 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C1334 C1335 C1341 C1352 C1401 C1402 C1403 C1404 C1407 C1412 C1413 C1414 C1422 C1423 C1424 C1425 C1431 C1441 C1442 C1443 C1444 C1447 C1448 C1451 C1452 C1453 C1454 C1501 C1502 C1503 C1504 C1505 C1507 C1508 C1509 C1510 C1511 C1512 C1513 Description CAP.NP0 .50V.CERAMIC.TC.2 nF.TC.K.1005.NP0.R/TP 10 nF.CERAMIC.TC .CERAMIC.R/TP 10 pF.R/TP 10 pF.K.CHIP CAP.R/TP 1.CERAMIC.R/TP 22 pF.1005.CHIP CAP.C .50V.16V.X7R.50V.HD.CHIP CAP.1005.TC.CHIP CAP.HD.J.50V.TC.K.NP0.HD.50V.NP0.TC.X7R.1005.R/TP 10 nF.1005 .16V.50V.2 pF.R/TP 10 nF.1005.K.CHIP CAP.CHIP CAP.R/TP 2.R/TP 2.K.CHIP CAP.NP0.50V.NP0.NP0.CERAMIC.R/TP 10 nF.1005.CHIP CAP.R/TP SVC N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N Color Remark -256- .CERAMIC.HD.CHIP CAP.D.NP0.K.1005.NP0.CHIP CAP.CHIP CAP.CHIP CAP.CHIP Part Number ECCH0000115 ECCH0000115 ECCH0000186 ECCH0000110 ECCH0000115 ECCH0000143 ECCH0000115 ECCH0000155 ECCH0000115 ECCH0000701 ECCH0000701 ECCH0000115 ECCH0000117 ECCH0000117 ECCH0000115 ECCH0000147 ECCH0000115 ECCH0000147 ECCH0000147 ECCH0000701 ECCH0000115 ECCH0000155 ECCH0000155 ECCH0000155 ECCH0000155 ECCH0000155 ECCH0000155 ECCH0000122 ECCH0000105 ECCH0000115 ECCH0000110 ECCH0000115 ECCH0000105 ECCH0000901 ECCH0000110 ECCH0000155 ECCH0000110 ECCH0000110 ECCH0000155 Specification 22 pF.NP0.CHIP CAP.R/TP 10 pF.CHIP CAP.X7R.CERAMIC.50V.NP0.TC.1005.CERAMIC.1005.NP0 .1005.CERAMIC.TC.CHIP CAP.CERAMIC.J.1005.NP0.NP0.J.TC.50V.NP0.J.D.CHIP CAP.R/TP 10 nF.TC.CHIP CAP.1005.X7R.1005.CERAMIC.C .50V.R/TP 27 pF.J.Level Location No.CHIP CAP.TC .NP0.1005.CERAMIC.CERAMIC.R/TP 22 pF.1005.X7R.R/TP 27 pF.50V.NP0 .CERAMIC.HD.16V.CERAMIC.NP0.TC.R/TP 10 nF.1005.J.1005.CHIP CAP.50V .1005.NP0.16V.1005.CHIP CAP.HD.D.16V.K.CERAMIC.CERAMIC.CERAMIC.50V.X7R.1005.1005.CHIP CAP.R/TP 22 pF.50V.CHIP CAP.CHIP CAP.NP0.K.50V .CERAMIC.TC.CERAMIC.R/TP 22 pF.CERAMIC.J.X7R.CERAMIC.HD.CERAMIC.CHIP CAP.R/TP 22 pF.R/TP 10 pF.1005.K.HD.2 nF.1005.1005.X7R.C .50V .TC.HD.TC.CERAMIC.X7R.HD.TC.CERAMIC.R/TP 1.CHIP CAP.X7R.50V.CHIP CAP.R/TP 4 pF.C .CERAMIC.X7R.50V.1005.2 pF.TC.J.TC .CHIP CAP.2 pF.TC.2 nF.CERAMIC.2 pF.16V.HD.R/TP 2.J.R/TP 4 pF.1005.CHIP CAP.TC .50V.R/TP 1.50V.TC.1005.TC.CERAMIC.TC.TC.1005.R/TP 10 nF.NP0.CERAMIC.R/TP 22 pF.J.50V.D.R/TP 22 pF.NP0 .J.R/TP 1 nF.CHIP CAP.CHIP CAP.K.16V.NP0.CERAMIC.R/TP 10 nF.CHIP CAP.CERAMIC.CERAMIC.K.J.1005.HD.50V.50V.1005.CHIP CAP.R/TP 2.1005 .NP0.1005 .CHIP CAP.50V.R/TP 10 pF.50V .CHIP CAP.NP0 .CHIP CAP.J .50V.1005 .R/TP 47 pF.R/TP 22 pF.TC .J.1005.R/TP 22 pF.K.CHIP CAP.CERAMIC.1005 .16V.HD.50V.50V .J.CERAMIC.

TC .TC.TC.1005.TC.CERAMIC.R/TP 10 uF.TC.CERAMIC.16V.J.50V.NP0.R/TP 4.X7R.16V.NP0.CERAMIC.R/TP 22 pF.7 uF.1005.CERAMIC.C .SL.NP0 .R/TP 330 pF.CHIP CAP.HD.3 nF.K.R/TP 22 pF.7 pF.CHIP CAP.TC.CERAMIC.HD .16V.CHIP CAP.CHIP CAP.CERAMIC.K.1005 .Y5V.R/TP 10 nF.J.CHIP CAP.X7R.K.X7R.1 uF.CHIP CAP.NP0.CERAMIC.NP0 .HD.CHIP CAP.CHIP CAP.10V .1005 .X7R.NP0.TC .CHIP CAP.CERAMIC.R/TP 10 nF.TC.R/TP 4.6.1005.CHIP CAP.1005.TC.50V.CHIP CAP.HD .16V.K .50V.NP0 .2012 .R/TP 47 pF.Level Location No.K.D.CHIP CAP.K.16V.K.K.CHIP CAP.CERAMIC.1005.R/TP 82 pF.K.R/TP 1 nF.TC.CHIP CAP.J.50V .2012 .1005.7 pF.R/TP 22 pF.CERAMIC.J.HD.10V .TC.R/TP 22 pF.HD.1005.25V.50V.1005 .16V.50V.CERAMIC.CHIP CAP.K.Y5V .CERAMIC.1005.K.1005.CERAMIC.50V .J.R/TP 3.3V .CERAMIC.1005.R/TP SVC N N N N Y N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N Y Color Remark -257- .CERAMIC.1005.1005.CERAMIC.Y5V .CERAMIC.NP0.CERAMIC.1005.CERAMIC.16V.CHIP CAP.HD.R/TP 4.CHIP CAP.HD.2012 .TC.R/TP 0.CHIP CAP.7 uF.1005.C .CERAMIC.CERAMIC.CHIP CAP.16V.50V.CERAMIC.1005.R/TP 100 pF.50V.CERAMIC.Z .K.6 nF.CHIP Part Number ECCH0000155 ECCH0000155 ECCH0000115 ECCH0000115 ECCH0006501 ECCH0003803 ECCH0000137 ECCH0003803 ECCH0000143 ECCH0000110 ECCH0000155 ECCH0000155 ECCH0000115 ECCH0000155 ECCH0000115 ECCH0000130 ECCH0000149 ECCH0000128 ECCH0000128 ECCH0000181 ECCH0000152 ECCH0000138 ECCH0000155 ECCH0000115 ECCH0000155 ECCH0000115 ECCH0000115 ECCH0000115 ECCH0000155 ECCH0000127 ECCH0000155 ECCH0000137 ECCH0000181 ECCH0000181 ECCH0000122 ECCH0000124 ECCH0000168 ECCH0000143 ECCH0006501 Specification 10 nF.J.X7R.NP0.HD.K .R/TP 5.Z.NP0.1005.CHIP CAP.50V.CERAMIC.J.CHIP CAP.HD.50V.HD .R/TP 100 pF.1005.50V.50V.CHIP CAP.CHIP CAP.X5R .R/TP 4.CERAMIC.X7R.CERAMIC.CERAMIC.NP0.NP0.R/TP 10 nF.CERAMIC.CHIP CAP.J.J.K .X7R.CHIP CAP.C .CHIP CAP.X7R .CERAMIC.1005.2012 . 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C1514 C1601 C1602 C1622 C1623 C1624 C1626 C1627 C1628 C1631 C1632 C1701 C1702 C1703 C1704 C1710 C1711 C1714 C1715 C1716 C1720 C1721 C1730 C1731 C1740 C1741 C1750 C1751 C1760 C1761 C1770 C1772 C1773 C1776 C1777 C1778 C1800 C1801 C1802 Description CAP.1005.TC .X7R .R/TP 22 pF.CERAMIC.50V.HD.CHIP CAP.3V .R/TP 22 pF.1005.1005.TC.Z .X7R.HD.NP0.K.6.50V.1005.CHIP CAP.J.CERAMIC.R/TP 390 pF.X7R.R/TP 4.50V.CERAMIC.CERAMIC.CHIP CAP.CHIP CAP.CHIP CAP.X7R.R/TP 10 nF.X7R.CHIP CAP.NP0.50V.TC .1005.X7R.K.HD .HD.HD.1005.CHIP CAP.CERAMIC.R/TP 10 nF.X7R.50V .CHIP CAP.1005.R/TP 1 nF.R/TP 10 nF.CHIP CAP.16V.CERAMIC.50V .R/TP 22 pF.CERAMIC.TC.1005.HD.1005.7 pF.K .1005.1005.CHIP CAP.J.J.1005 .50V.R/TP 330 pF.J.50V.1005.R/TP 10 nF.NP0.R/TP 56 pF.1005 .50V.R/TP 10 nF.TC.R/TP 22 pF.J.50V.TC.X5R .CERAMIC.TC.HD.TC .R/TP 10 pF.R/TP 10 uF.CHIP CAP.K.CERAMIC.NP0.CERAMIC.16V.50V .X7R.CHIP CAP.NP0.HD.R/TP 150 pF.

CERAMIC.CHIP CAP.CERAMIC.1 uF.Y5V.10V.R/TP 0.1005.2012 .Y5V.CHIP CAP.Z.1 uF.CHIP CAP.3V .16V.1005.16V.3V .HD.16V.CHIP CAP.16V.1005.1 uF.K .K.1005 .2012 .HD.1005.7 uF.K .CERAMIC.1005.CHIP CAP.Y5V. 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C1810 C1811 C1850 C1851 C1852 C2100 C2101 C2102 C2103 C2104 C2200 C2202 C2203 C2205 C2206 C2207 C2208 C2209 C2210 C2211 C2212 C2213 C2214 C2215 C2216 C2217 C2218 C2219 C2220 C2221 C2222 C2223 C2224 C2225 C2226 C2227 C2228 C2229 C2230 Description CAP.HD.HD.CHIP CAP.50V.Y5V.CERAMIC.CERAMIC.CHIP CAP.1005.Z.Y5V.Y5V.16V.X7R .CHIP CAP.1005.Z .1005.1005.R/TP 0.HD .CHIP CAP.1 uF.HD.CERAMIC.CERAMIC.CERAMIC.CERAMIC.Z.CHIP CAP.HD.1608.Z.CHIP CAP.Y5V.1005.CHIP CAP.HD.R/TP 0.R/TP 10 uF.3V .CHIP CAP.R/TP 33 nF.HD.2012 .1608.Y5V.CHIP CAP.R/TP 10 uF.X5R .1005.50V .3V .CHIP CAP.R/TP 0.HD.R/TP 0.2012 .CHIP CAP.1005.R/TP 0.HD.16V.TC .X5R .R/TP 0.CERAMIC.CERAMIC.CHIP CAP.Z.1 uF.1 uF.1005.1005.Y5V.CERAMIC.HD.HD.R/TP 0.16V.CHIP CAP.CERAMIC.CERAMIC.HD.R/TP 10 uF.16V.R/TP 22 pF.Z.CHIP CAP.1005.HD.16V.CERAMIC.1 uF.R/TP 0.CERAMIC.Z.R/TP 0.1005.HD .HD.K.K .Z.TC.R/TP 330 pF.CERAMIC.HD.CHIP CAP.1005 .Y5V.1 uF.R/TP 10 uF.R/TP 0.CERAMIC.HD.CERAMIC.R/TP 0.Y5V.HD.Y5V.CERAMIC.CERAMIC.16V.X7R.CERAMIC.3V .R/TP 0.2012 .16V.R/TP 0.HD.CERAMIC.CERAMIC.K .CHIP CAP.1005.50V.R/TP 0.1 uF.CERAMIC.Z.Y5V.Y5V.CERAMIC.HD .R/TP 0.2012 .R/TP SVC Y N N N Y N N N N N Y N N Y Y N N N N N N N N N N N N N N N N N N N N N N N N Color Remark -258- .R/TP 1 nF.Y5V.Z.Z.6.R/TP 22 pF.HD.R/TP 0.TC.K .CHIP CAP.16V.HD.Z.R/TP 0.3V .1 uF.16V.CERAMIC.R/TP 330 pF.CERAMIC.1 uF.1 uF.CHIP CAP.Z.CHIP CAP.X5R .16V.16V.1 uF.Z.1005.Z.CERAMIC.K .TC .CHIP CAP.X7R .J.2012 .R/TP 10 uF.HD.CHIP CAP.16V.CERAMIC.6.K .R/TP 4.CHIP CAP.J.Z.R/TP 0.1 uF.CERAMIC.X5R .1 uF.R/TP 1 uF.16V.Z.16V.1005.Y5V.16V.Z.Y5V.1 uF.CERAMIC.16V.1005.6.CERAMIC.1005.1005.10V .1005.Y5V.Y5V.R/TP 1 uF.1005.1 uF.Z.CERAMIC.Z.HD.Y5V.HD.CHIP Part Number ECCH0006501 ECCH0006501 ECCH0000168 ECCH0000161 ECCH0006501 ECCH0000115 ECCH0000115 ECCH0000137 ECCH0000137 ECCH0000143 ECCH0006501 ECCH0003803 ECCH0000276 ECCH0006501 ECCH0006501 ECCH0000168 ECCH0000276 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 Specification 10 uF.16V.10V.1 uF.HD.CHIP CAP.HD.R/TP 0.50V .NP0.Level Location No.6.CHIP CAP.HD.CHIP CAP.1 uF.1 uF.R/TP 0.Y5V .1005.X7R.CERAMIC.TC .CHIP CAP.Y5V.R/TP 0.6.CERAMIC.Y5V.Z.50V.X5R .Y5V.Z.TC .CHIP CAP.CHIP CAP.HD.1005.R/TP 0.1005.TC .NP0.R/TP 0.X5R .16V.6.CHIP CAP.1 uF.1 uF.CHIP CAP.Z.1005.CHIP CAP.1 uF.CERAMIC.Y5V.16V.TC .Y5V.Z.CHIP CAP.K .CERAMIC.16V.Z.1 uF.CERAMIC.Z.CHIP CAP.Y5V.16V.

CHIP CAP.HD .CERAMIC.HD.R/TP 0.16V.HD.16V.HD.CHIP CAP.HD.R/TP 0.CHIP CAP.Z.1 uF.Z.R/TP 0.1 uF.1005.R/TP 0.10V .CHIP CAP.Z.CERAMIC.CERAMIC.16V.CERAMIC.CHIP CAP.Z.Y5V.R/TP 0.CERAMIC.CERAMIC.CHIP CAP.1005.HD.R/TP 0.16V.CHIP CAP.1 uF.CERAMIC.Z.CERAMIC.1005.1 uF.1005.2 uF.CHIP CAP.CHIP CAP.R/TP 0.10V.Z.Z.1005.R/TP 0.CHIP CAP.HD.Level Location No.1608.CHIP CAP.CERAMIC.Y5V.Z.Y5V .Z.16V.Y5V.16V.CHIP CAP.1608.16V.16V.R/TP 0.CHIP CAP.R/TP 0.Y5V.CHIP CAP.Z.R/TP 0.CHIP CAP.R/TP SVC N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N Color Remark -259- .CERAMIC.Z.R/TP 0.1 uF.Z.Z.HD.16V.2012 .10V .HD.R/TP 10 nF.CHIP CAP.Z.1 uF.HD.Z.CERAMIC.Z.X7R.1005.HD.16V .Z.CHIP CAP.R/TP 1 uF.Z.HD.HD.1005. 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C2231 C2232 C2233 C2234 C2235 C2236 C2237 C2238 C2239 C2240 C2241 C2242 C2243 C2244 C2245 C2246 C2247 C2250 C2251 C2252 C2253 C2255 C2256 C2257 C2258 C2259 C2260 C2261 C2262 C2263 C2272 C2274 C2276 C2277 C2278 C2279 C2281 C2301 C2302 Description CAP.R/TP 0.1 uF.Y5V.1 uF.Y5V.CHIP CAP.16V.R/TP 0.CERAMIC.Z.50V.1 uF.HD.R/TP 0.1005.CHIP CAP.Y5V.1005.16V.16V.1 uF.HD.1 uF.2012 .HD.1005.R/TP 0.Z.HD.16V.CERAMIC.CERAMIC.1 uF.Z.Z.1005.1005.1 uF.R/TP 4.Y5V.CHIP CAP.R/TP 2.R/TP 0.1005.7 uF.Y5V.CERAMIC.Y5V.CHIP CAP.CERAMIC.CERAMIC.1 uF.R/TP 4.16V.16V.Z.Y5V.10V.2012 .R/TP 0.CHIP CAP.1 uF.Y5V.1 uF.CHIP CAP.Z.1005.Y5V.HD.Z.16V.16V.1005.1 uF.R/TP 0.1005.R/TP 0.HD.Y5V.CERAMIC.CERAMIC.HD.Y5V.16V.1005.Z .CHIP CAP.Y5V.1 uF.Y5V.CERAMIC.1 uF.Y5V.1005.16V.Z.CERAMIC.1005.CHIP CAP.HD.Y5V.Y5V.1005.1005.Z.1005.CHIP CAP.Y5V.CHIP CAP.CHIP CAP.CHIP CAP.Y5V.Y5V.1 uF.1005.R/TP 0.HD.1 uF.CERAMIC.16V.Y5V.TC.HD.HD.HD.R/TP 0.R/TP 0.R/TP 0.HD.16V.16V.Z .NP0.CHIP Part Number ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000276 ECCH0000168 ECCH0000128 ECCH0003803 ECCH0000380 ECCH0000155 ECCH0003803 ECCH0000276 ECCH0000276 Specification 0.CHIP CAP.1005.16V.HD.16V.R/TP 0.HD.Y5V.CERAMIC.CERAMIC.HD.CERAMIC.CERAMIC.16V.HD .Y5V.Z.1005.Z.CERAMIC.HD.1005.16V.1005.R/TP 0.CERAMIC.CHIP CAP.CHIP CAP.CERAMIC.CERAMIC.K.1 uF.Z.1005.1005.CHIP CAP.10V.16V.Z.Y5V.1 uF.R/TP 0.CERAMIC.CHIP CAP.1 uF.CERAMIC.Y5V.CERAMIC.HD.16V.1 uF.CERAMIC.CHIP CAP.16V.Z .CERAMIC.CERAMIC.HD .HD.1 uF.HD.Y5V .CHIP CAP.1 uF.Z.CHIP CAP.HD.J.Y5V.Y5V.R/TP 0.7 uF.Y5V.16V.Y5V.Y5V .HD.Y5V.16V.CERAMIC.1005.CHIP CAP.1 uF.Y5V.Z.1 uF.R/TP 100 pF.1005.1005.R/TP 0.1 uF.Z.1608.CERAMIC.1 uF.R/TP 1 uF.CERAMIC.R/TP 1 uF.1005.HD.16V.R/TP 0.

R/TP 1 uF.CERAMIC.3V .R/TP 22 pF.CERAMIC.22 uF.10V .CERAMIC.CHIP CAP.CERAMIC.Z.Z.50V.Z.50V.TC .K.1608 .6.3V.1005.CHIP CAP.16V.50V.L_ESR .Z.1005.CHIP.R/TP 22 pF.CHIP CAP.J.HD.CHIP CAP.R/TP 22 pF.CERAMIC.J.16V.HD.1 uF.10V.HD .2 uF.CHIP Part Number ECCH0000143 ECCH0000168 ECCH0000115 ECCH0000168 ECCH0000168 ECCH0000276 ECCH0000168 ECCH0000168 ECCH0000275 ECCH0000276 ECCH0000155 ECCH0000115 ECTZ0002802 ECCH0000165 ECCH0000161 ECCH0000115 ECCH0000165 ECCH0000115 ECCH0000165 ECCH0000115 ECTZ0002802 ECCH0000168 ECCH0000115 ECCH0000115 ECCH0000115 ECCH0000115 ECCH0003803 ECCH0000128 ECCH0000380 ECCH0003803 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000274 ECCH0000279 ECCH0000276 ECCH0000276 ECCH0006501 ECCH0000276 Specification 1 nF.L_ESR .CHIP CAP.1 uF.CHIP CAP.1005.Z.3V.Z.R/TP 22 pF.7 uF.50V.16V.CERAMIC.TC.Z.6.HD.CHIP CAP.16V.50V.HD.CERAMIC.J.HD.R/TP 68 nF.16V.TANTAL.R/TP 0.CERAMIC.CHIP CAP.1 uF.R/TP 100 uF.50V.HD .Y5V.Z .1608.J.R/TP 68 nF.CERAMIC.HD.Y5V.CHIP CAP.1005.1005.NP0.CHIP CAP.CHIP CAP.HD.R/TP 0.R/TP 0.R/TP 22 pF.CHIP CAP.HD.Y5V.16V.J.1005.CHIP CAP.X5R.R/TP 0.K.1005.1608.CHIP CAP.16V.CERAMIC.16V.R/TP 22 pF.CHIP CAP.MAKER CAP.J.CERAMIC.TC.NP0.R/TP 0.TC.CHIP CAP.TC.R/TP 22 pF.HD.6.1005.CERAMIC.3V.1608.CHIP CAP.HD.CHIP CAP.R/TP 0.R/TP 0.10V.Z.47 uF.HD.K.6.TC.Y5V.CHIP CAP.10V.TC.TC.CERAMIC.1005.NP0.CERAMIC.TC.R/TP 0.HD.CERAMIC.CHIP CAP.1005.ETC .R/TP 4.CERAMIC.CERAMIC.CHIP CAP.M .16V.1 uF.1005.1005.J.Y5V.CERAMIC.Y5V .1608.HD .2012 .HD.Level Location No.X7R.2012 .R/TP 100 pF.X7R.16V.10V.1005.R/TP 0.HD.CERAMIC.MAKER CAP.CHIP CAP.Y5V.R/TP 33 nF.J.CERAMIC.CHIP CAP.Z.HD.CERAMIC.50V.CHIP CAP.K .1005.Y5V.1 uF.10V.CERAMIC.1005.1005.3V .CHIP CAP.M .1005.7 uF.CHIP CAP.R/TP 1 uF.TC.R/TP 0.Z .NP0.2012 .CHIP CAP.Z.HD.2012 .Z.CHIP CAP.CHIP.X5R .CHIP CAP.CERAMIC.NP0.R/TP 0.R/TP 22 pF.R/TP 4.Y5V.HD.Y5V.CHIP CAP.CHIP CAP.CERAMIC.CERAMIC.3V .1005.HD.NP0.HD.CERAMIC.NP0.X7R.R/TP 1 uF.Y5V .16V.CERAMIC.1005.1005.Y5V.1005.X5R.50V.Y5V.CHIP CAP.6.Y5V .R/TP 68 nF.Z .HD.CERAMIC.CERAMIC.16V.CERAMIC.1005.J.R/TP 10 nF.1005.Y5V.NP0.16V.HD.1608.CERAMIC.CERAMIC.CERAMIC.R/TP 0.CERAMIC.1608.K.Y5V.Y5V .Y5V.50V.CERAMIC.ETC .Z .K.1 uF.NP0.Z.R/TP 1 uF.K.Z.CHIP CAP.1005.R/TP 1 uF.X5R.HD .R/TP 10 uF.1 uF.Z.TANTAL.10V .R/TP 2.CERAMIC.R/TP 100 uF.6.1 uF. 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C2303 C2304 C2312 C2400 C2500 C2603 C2604 C2605 C2606 C2608 C2609 C2610 C2611 C2612 C2613 C2614 C2615 C2616 C2617 C2618 C2619 C2621 C2630 C2631 C2632 C2633 C3013 C3046 C3051 C3052 C3133 C3134 C3135 C3136 C3137 C3200 C3201 C3202 C3203 Description CAP.R/TP 22 pF.50V.Y5V.NP0.33 uF.Z.1 uF.CHIP CAP.CERAMIC.16V .R/TP SVC N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N Y N Color Remark -260- .TC.10V .J.Z.CHIP CAP.CHIP CAP.1608.50V.Y5V.HD.1005.

TC.1005.R/TP 100 pF.CHIP CAP.CHIP CAP.1005.1005.Y5V.16V.CERAMIC.16V.TC.NP0.289 PIN.200 mW.J.R/TP 0.50V.CHIP CAP.HD.50V.ASIC / BASEBAND CONTROLLER / MARITA u181 BGA . 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C3204 C3205 C3212 C3213 C3215 C3219 C3220 C3221 C3222 C3225 C3243 C3244 C3245 C3246 C3247 C3248 C3249 C3252 C3255 C3258 C3259 C3260 C3261 C3265 C3266 C3268 C3269 C3271 C3272 C3276 C3278 D2000 Description CAP.15 KV.1005.Y5V .1005.NP0.MAKER CAP.R/TP 10 uF.1005.1005.CHIP CAP.J.R/TP .1005.TC.16V .CERAMIC.J.50V.CERAMIC.1005.R/TP 0.K.200 mW.NP0.R/TP u289 BGA .CERAMIC.TVS EDTY0006701 CSP .TVS EDTY0006701 N 5 D2008 DIODE.50V.50V.1 uF.Z.CERAMIC.CHIP CAP.J.1005.J.CERAMIC.CHIP CAP.R/TP 2.J.Z .22 uF.1005.R/TP 0.1005.D.CERAMIC.HD.1 uF.J.NP0.CHIP IC Part Number ECCH0000168 ECCH0000110 ECCH0000143 ECCH0000143 ECTZ0000318 ECCH0000143 ECCH0000168 ECCH0000115 ECCH0000168 ECCH0000274 ECCH0000139 ECCH0000380 ECTZ0003601 ECCH0000168 ECCH0000168 ECCH0000168 ECCH0000114 ECCH0000114 ECCH0000114 ECCH0000114 ECCH0000114 ECCH0000114 ECCH0000114 ECCH0000122 ECCH0000110 ECCH0000122 ECCH0000122 ECCH0000122 ECCH0000122 ECCH0000168 ECCH0000128 EUSY0135001 Specification 0.CERAMIC.K.50V.R/TP 20 pF.CERAMIC.50V.CERAMIC.2012 .NP0.TC.K.ASIC / WCDMA AIR INTERFACE / WANDA CSP .Z.STD .CHIP CAP.200 mW.CHIP CAP.NP0.R/TP 47 pF.TC.2 uF.NP0.1005.50V.CERAMIC.15 KV.2012 .50V.R/TP 47 pF.TVS EDTY0006701 CSP .NP0.50V.4 CHANNEL ESD ARRAY N 5 D2009 DIODE.CERAMIC.NP0.Z.HD.Z.R/TP .CERAMIC.HD.1005.50V.R/TP 20 pF.X7R.CERAMIC.4 CHANNEL ESD ARRAY SVC N N N N N N N N N N N N Y N N N N N N N N N N N Y N N N N Y Y Y Color Remark 5 D2006 IC EUSY0135201 Y 5 D2007 DIODE.CHIP CAP.HD.X7R.CHIP CAP.NP0.R/TP .1005.K.R/TP 10 pF.R/TP 47 pF.1005.CHIP CAP.1005.Y5V.CERAMIC.1608.CERAMIC.NP0.Y5V.Z.HD .1005.1 uF.CERAMIC.CERAMIC.CHIP CAP.R/TP 47 pF.Level Location No.50V.R/TP 0.Z.R/TP 20 pF.CHIP CAP.CERAMIC.TC.16V.Y5V.1005.CHIP CAP.J.CERAMIC.CHIP CAP.CERAMIC.TC.TC.Y5V.1 uF.50V.16V.1005.Z.CHIP CAP.J.CHIP CAP.CHIP CAP.M .NP0.R/TP 0.50V.CERAMIC.50V.Y5V.CHIP CAP.50V.CERAMIC.M .CERAMIC.1005.50V.CHIP CAP.CERAMIC.MAKER CAP.16V.HD.R/TP 33 uF.CHIP CAP.NP0.R/TP 47 pF.R/TP 1 nF.J.CHIP CAP.TC.TC.HD.50V.HD.NP0.50V.J.R/TP 20 pF.TANTAL.J.CHIP CAP.TC.16V.CERAMIC.TC.NP0.Z.ETC .L_ESR .R/TP 470 pF.1005.CERAMIC.X7R.R/TP 0.R/TP 20 pF.16V.CHIP CAP.D.1005.R/TP .R/TP .CHIP CAP.CHIP CAP.181 PIN.1005.16V.1005.HD.R/TP 22 pF.CHIP.R/TP 0.TC.Y5V.NP0.CHIP CAP.4 CHANNEL ESD ARRAY N -261- .10V .15 KV.1005.TANTAL.10V .R/TP 1 nF.R/TP 20 pF.1 uF.J.HD.CERAMIC.HD.X7R.CHIP.CHIP CAP.1 uF.Y5V.1005.CERAMIC.TC.J.R/TP 1 nF.HD.50V.R/TP 20 pF.TC.TC.R/TP 10 pF.1 uF.

1005 .R/TP 100 nH.40 V.R/TP .R/TP 3.BEAD.CHIP INDUCTOR.S.R/TP .R/TP 68 nH.CDMA 3.8 nH.1005.J.R/TP .SWITCHING EDSY0011901 N 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 D2018 FB1 FB2 FB3 FB4 L1001 L1002 L1100 L1101 L1110 L1111 L1120 L1200 L1201 L1202 L1220 L1230 L1300 L1330 L1331 L1332 L1333 L1340 L1350 L1401 L1411 L1421 L1422 L1441 L1501 DIODE.R/TP 75 ohm.5V(IF=200mA) .1005 .BEAD.30 V.1005 .BEAD.CHIP INDUCTOR.R/TP SVC N Color Remark 5 D2012 DIODE.R/TP 10 nH.2012 .CHIP INDUCTOR.R/TP 75 ohm.CHIP INDUCTOR.R/TP .R/TP .R/TP .1 A. IR=30uA(VR=10V) CSP .CHIP INDUCTOR.CHIP BEAD.1005 .CHIP FILTER. 2000mA 120 ohm.BEAD. 75 ohm.CHIP INDUCTOR.CHIP INDUCTOR.5V(IF=200mA) .300 A.1005 . 2000mA 30 ohm.SWITCHING Part Number EDSY0010401 Specification 1-1G1A .Silicon Epitaxial Schottky Barrier Type Diode 1-1G1A .8 nH.1005.CHIP INDUCTOR.R/TP .1608 .R/TP .CHIP FILTER.K .J.S .Silicon Epitaxial Schottky Barrier Type Diode 1-1G1A .CHIP BEAD.R/TP . 5 D2010 Description DIODE.CHIP FILTER.3000mA.VF=1. 75 ohm.CHIP INDUCTOR.CHIP FILTER.CHIP FILTER.BEAD.30 V.300 A.CHIP INDUCTOR.2 nH.2 nH.1005 .1005.3000mA.40 V.CHIP EDTY0006701 SFBH0002302 SFBH0002302 SFBH0008901 SFBH0008901 ELCH0005003 ELCH0001407 ELCH0001420 ELCH0001405 ELCH0001402 ELCH0001001 SFBH0007103 SFBH0007103 ELCH0007404 SFBH0007103 ELCH0007403 SFBH0007103 SFBH0007802 ELCH0005006 ELCH0001401 SFBH0007103 SFBH0007103 ELCH0005010 ELCH0001427 ELCH0001427 ELCH0001408 ELCH0000716 ELCH0000716 ELCH0001511 ELCH0001401 N N N Y Y Y Y N N N Y Y Y N Y N N N N N N N N N N N N N N N -262- .CHIP FILTER.SWITCHING EDSY0011901 N 5 D2016 DIODE.1608 .S . 300mA 75 ohm.K .R/TP .CHIP INDUCTOR.VF=1.3 nH.1005. BEAD for LARGE CURRENT 30 ohm.S. BEAD for LARGE CURRENT 12 nH.R/TP .2012 .Level Location No.R/TP .R/TP 68 nH. 300mA 75 ohm.CHIP FILTER.1005 .CHIP INDUCTOR. 300mA 5. 2.CHIP INDUCTOR.J.40 V.2012 .15 KV.CHIP BEAD.CHIP FILTER.R/TP 18 nH.SWITCHING EDSY0010401 N 5 D2014 DIODE. 15 nH.CHIP FERRITE BEAD 33 nH.S.1005.1005 .CHIP FILTER. IR=30uA(VR=10V) EMD2 .R/TP .4 CHANNEL ESD ARRAY 120 ohm.R/TP 15 nH.9 nH.1005 .CHIP INDUCTOR.CHIP INDUCTOR.CHIP INDUCTOR.Silicon Epitaxial Schottky Barrier Type Diode 1-1G1A .1608.300 A.TVS FILTER.S .6 uH.3216 .BEAD.SWITCHING EDSY0010401 N 5 D2015 DIODE.CHIP BEAD.1608 . 300mA 1.Silicon Epitaxial Schottky Barrier Type Diode EMD2 . 300mA 100 uH.S .1608.J.40 V.CHIP FILTER.6 nH.CHIP BEAD.BEAD.1005 .BEAD.CHIP BEAD. 6. 2.R/TP .J.J.SWITCHING EDSY0010401 N 5 D2013 DIODE.R/TP . 300mA 600 ohm.CHIP BEAD.1 A.1005 .BEAD.BEAD.J .1005.CHIP INDUCTOR. 5.BEAD.1608.CHIP INDUCTOR.1005 .300 A.1005.CHIP BEAD.200 mW.J.J .

0*1.BEAD.1005 .-58 dBc.BEAD.R/TP .IMT IC IC PAM TRANSFORMER.83 A.1005 .56 PIN.M .1.0*4.R/TP .23.CHIP FILTER.1.0*6.EMI FILTER & LINE TERMINATION for USB 75 ohm.BEAD.CHIP BEAD.COIL TYPE 22 uH.5 .SMD .MATCHING TRANSFORMER.64 PIN.MATCHING IC IC SDMY0000301 EUSY0132801 EUSY0133101 SMPY0002901 STMY0018402 STMY0018401 EUSY0133001 EUSY0136001 N Y Y Y Y Y Y Y 5 5 5 5 5 N1630 N1650 N1700 N1850 N2000 PAM ISOLATOR.6 PIN.CHIP BEAD.CHIP FILTER.0*1. 300mA 75 ohm.1608 .R/TP .CHIP FILTER.8.56 PIN.SMD .R/TP . 2000mA 4.6*9.R/TP . 1950 MHz.7 CHANNEL ESD FILTER ARRAY.CHIP FILTER.8 ANTENNA SWITCH MODULE 1950 MHz.R/TP .1005 .23.2 nH.ASIC / POWER MANAGEMENT IC / VINCENNE SC-82AB . 2000mA 120 ohm.5V OUTPUT/ 2.SMD .143 PIN. 6 PIN.40 dB.POWER FILTER.POWER INDUCTOR.CHIP FILTER.CHIP BEAD.SMD .9 .CHIP BEAD. 1000 nH.5 dB.R/TP 10 nH.2140 MHz.CHIP FILTER.8V u143 BGA . 2000mA 120 ohm.CHIP BEAD.R/TP 8.U8000 RF IC 30 dBm.40 dB.CHIP FILTER.10 PIN.CHIP INDUCTOR.J.R/TP .4 .1005.1.RFIC BGA64 .CHIP BEAD.CHIP INDUCTOR.SMD.BEAD.80 A.8*3.CHIP BEAD.R/TP .6 PIN.SEPERATOR Part Number ELCH0001401 ELCH0001407 ELCH0001004 ELCH0001001 SFBH0007103 SFBH0002302 SFBH0002302 SFBH0002302 ELCP0005101 ELCH0003811 ELCP0004701 SFBH0002302 SFBH0002302 EUSY0163501 SFBH0007103 SFBH0007103 SFBH0007103 SFBH0007103 SFAY0003101 15 nH.CHIP BEAD.8*1.1 SOT-23 . 56 ball .4. 300mA 120 ohm.1005 .K .10*5.BEAD.0 dB.8 .0*1.ETC .SMD .1005 .1608 .CHIP INDUCTOR.BEAD.BEAD.5 . 2000mA SOT323-6L .3*1.R/TP .CHIP FILTER.1005.1608 .40 %.SMD.1005.6 nH.Level Location No.R/TP .300mA CMOS LDO / 2.5 PIN.WCDMA TXIC Wivi LLP-6 .CHIP INDUCTOR.150mA 3.CHIP INDUCTOR.2100 . 2000mA 120 ohm.BEAD.SMD .U8000 RF IC 3 X 4 UCSP .3V LDO CSP .J.2*5.94 .DCS TX BALUN uBGA .CHIP BEAD.1920~1980MHz 56 . 120 ohm.1608 .20 PIN.R/TP .2*1.CHIP FILTER.0 dB.CHIP BEAD.2*4.7 uH.600 mA BUCK REGULATORS / DYNAMIC OUTPUT VOLTAGE 26 dBm.15 dB.CMOS LDO 1.5.1608 .56 PIN.11.2.R/TP 5.45 %.1*1.25 dB. 300mA 75 ohm.R/TP .4 dB.BEAD.1005.R/TP Specification SVC N N N N N N N N N N N N N N N N N N N Color Remark 75 ohm.CHIP IC FILTER.S.25 dB.M .4 PIN. 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 L1502 L1503 L1504 L1505 L1507 L1601 L1602 L1603 L1621 L1760 L2200 L2201 L2202 L2500 L2603 L2605 L2606 L2608 N1000 Description INDUCTOR.J. 300mA 75 ohm.5. KNATTE 5 5 5 5 5 5 5 5 N1002 N1100 N1101 N1300 N1330 N1331 N1400 N1620 DUPLEXER.5 dB.R/TP . 300mA 900 .R/TP .1608 .3.50 dBc.IMT IC IC IC SMPY0002801 SQMY0000201 EUSY0132901 EUSY0122502 EUSY0132701 Y N Y Y Y 5 5 5 N2203 N2204 N2300 IC IC IC EUSY0122402 EUSY0171302 EUSY0171401 Y Y N -263- .BEAD.0 X 2.GSM Tx Balun 6 PIN.

1005.R/TP 100 ohm.J.1/16W.CHIP RES.9 PIN.NPN TR.1005.3 PIN.1/16W.150 mW.1/16W.10*1.CHIP RES.2kb/s SC-74A FIT .R/TP 0 ohm.1005.6 CHANNEL ESD FILTER.R/TP .1/16W.20 A.27 W.J.CHIP RES.R/TP .1/16W.6 PIN.J.SMD .IRDA DATA 1.Level Location No.R/TP 0 ohm.R/TP 100 ohm.25 PIN.1/16W.1/16W.1005.1005.J.1/16W.0.150mA 2.1/16W.BJT.J.1005.100 mW.BJT.57 1206-8 chipFET .BJT.66 A.CHIP RES.R/TP .CHIP RES.1(t) 2-2H1A .J.1/16W.CHARGER PUMP // LED DRIVER / 4.1/16W.975*1.1005.R/TP .J.CHIP RES.R/TP 0 ohm.1005.5 PIN.R/TP 100 ohm.R/TP SVC Y Y Y Y Y Y Y Y N N Color Remark THERMISTOR TR.1005.R/TP 0 ohm.R/TP 120 ohm.CHIP RES.R/TP .1/16W.J.NPN SWITCHING TR 0 ohm.1005.NPN RES.1/16W. EMP SOLUTION SOT23-6 .F GRADE 2-2H1A .Dual(Pchannel:PD=0.NPN TR.47 Kohm. SOT323 .J.1005.J.8V LDO SURFACE MOUNT .1005.R/TP .J.3.J.0.1W AUDIO AMP CSP .P-CHANNEL 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Q2201 Q2300 Q3200 Q3202 Q3203 Q3204 R1003 R1004 R1005 R1006 R1007 R1103 R1104 R1105 R1106 R1113 R1140 R1150 R1151 R1210 R1211 R1212 R1213 R1220 R1222 R1223 R1224 TR.R/TP 0 ohm.J.R/TP .1005.J.R/TP 0 ohm.BJT.J.1005.J.1005.CHIP RES.CHIP RES.DUAL TRANSISTORS SOT323 .CHIP RES.R/TP 0 ohm..J.R/TP .27W.200 mW.R/TP .BJT.R/TP 100 ohm.NPN TR.5 W.CHIP RES.1/16W.VDS=-8V.1/16W.R/TP .J.1005.SPST SWITCH / 2 OHM SOT-23 .NPN SWITCHING TR EMT3 .7 PIN.CHIP RES.R/TP .R/TP .CHIP RES.ID=0.FET.2.J.1/16W.1/16W.200 mW.1005.BJT.201 W.J.1/16W.1005.R/TP 390 ohm.R/TP 0 ohm.CHIP RES.NPN TR.R/TP 100K ohm.R/TP . 5 5 5 5 5 5 5 5 5 5 N2601 N2602 N2603 N3000 N3100 N3200 N3201 PT1 Q2100 Q2200 IC IC IC IC IC IC IC Description Part Number EUSY0196101 EUSY0171201 EUSY0148801 EUSY0171301 EUSY0122301 EUSY0129501 EUSY0088502 SETY0005701 EQBN0013301 EQFP0003601 Specification BUMP MICRO SMD .PNP TR.FET.CHIP RES.1/16W.3 LOW POWER TRANSCEIVER / 115.R/TP 0 ohm.CHIP EQFP0004401 EQBN0013301 EQBN0013701 EQBN0014901 EQBP0002401 EQBN0014901 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000214 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000280 ERHY0000201 ERHY0000201 ERHY0000220 ERHY0000220 ERHY0000220 ERHY0000220 ERHY0000235 ERHY0000222 ERHY0000231 ERHY0000201 N N N N N N N N N N N N N N N N N N N N N N N N N N N -264- .CHIP RES.CHIP RES.1005.CHIP RES.1/16W.10 PIN.VEBO=6V EMT6 .CHIP RES.1/16W.VEBO=6V SOT-363 .20 V.HALL EFFECT SWITCH MSOP-10 .P-CHANNEL TR.1005.J.100 mW.CHIP RES.R/TP .1005.R/TP 51 ohm.R/TP 0 ohm.R/TP 560 ohm.-20 V.R/TP .R/TP 0 ohm.5V 120mA NTC .

R/TP 0 ohm.CHIP RES.R/TP 0 ohm.J.1/16W.F.CHIP RES.CHIP RES.1005.R/TP 0 ohm.CHIP RES.CHIP RES.1/16W.1/16W.CHIP RES.CHIP RES.R/TP 0 ohm.R/TP 3.CHIP RES.1/16W.CHIP RES.Level Location No.CHIP RES.1005. 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 R1240 R1250 R1301 R1302 R1320 R1321 R1325 R1326 R1327 R1329 R1332 R1333 R1334 R1335 R1338 R1340 R1341 R1342 R1401 R1410 R1411 R1430 R1431 R1440 R1501 R1502 R1503 R1504 R1510 R1603 R1605 R1617 R1621 R1623 R1626 R1627 R1628 R1629 R1630 RES.1005.1005.J.1005.CHIP RES.J.1005.1005.1005.1005.J.1/16W.1/16W.1/16W.R/TP 0 ohm.J.J.R/TP 0 ohm.R/TP 0 ohm.1005.2012 .CHIP RES.R/TP 10 ohm.1005.R/TP 680 ohm.1005.CHIP Description Part Number ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000241 ERHY0000201 ERHY0008601 ERHY0000201 ERHY0000241 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000224 ERHY0000210 ERHY0000224 ERHY0000201 ERHY0000201 ERHY0000250 ERHY0000203 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000111 ERHY0000201 ERHY0000111 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000138 ERHY0000271 ERHY0000280 ERHY0000201 ERHY0000201 Specification 0 ohm.1005.CHIP RES.1005.R/TP 0 ohm.1005.1/16W.1/16W.J.CHIP RES.1005.1/16W.1005.J.R/TP 0.1/4W .R/TP 100K ohm.1/16W.1/16W.J.1005.J.R/TP 0 ohm.1/16W.R/TP 0 ohm.1/16W.R/TP 0 ohm.R/TP 0 ohm.1/16W.J.R/TP 180 ohm.J.R/TP 0 ohm.CHIP RES.J.1005.1/16W.R/TP 33K ohm.1005.J.J.R/TP 0 ohm.R/TP 39K ohm.1005.CHIP RES.1/16W.R/TP 0 ohm.J.J.R/TP 1K ohm.CHIP RES.1/16W.CHIP RES.1005.1/16W.J.J.R/TP 0 ohm.1/16W.CHIP RES.J.1/16W.J.CHIP RES.1005.R/TP 0 ohm.1/16W.J.1005.1005.R/TP 0 ohm.CHIP RES.1005.CHIP RES.J.J.F.1/16W.J.1/16W.J.CHIP RES.1005.CHIP RES.CHIP RES.1/16W.1/16W.05 ohm.CHIP RES.J.1/16W.CHIP RES.1005.1005.R/TP 0 ohm.R/TP 680 ohm.J .1005.CHIP RES.J.1/16W.1/16W.1005.1005.1/16W.1005.CHIP RES.R/TP 180 ohm.R/TP 1K ohm.F.CHIP RES.1/16W.1/16W.1005.CHIP RES.J.R/TP 0 ohm.1/16W.J.R/TP 30 ohm.J.R/TP SVC N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N Color Remark -265- .1005.R/TP 0 ohm.1/16W.1/16W.R/TP 0 ohm.1005.J.CHIP RES.CHIP RES.3K ohm.CHIP RES.J.1/16W.R/TP 0 ohm.R/TP 0 ohm.CHIP RES.1/16W.1/16W.1005.CHIP RES.CHIP RES.R/TP 0 ohm.J.J.CHIP RES.1005.

J.3K ohm.1/16W. 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 R1631 R1632 R1701 R1702 R1703 R1710 R1711 R1720 R1721 R1723 R1730 R1740 R1760 R1770 R1771 R1772 R1810 R1811 R1825 R1826 R1850 R1851 R1997 R2100 R2101 R2102 R2104 R2105 R2106 R2108 R2109 R2122 R2123 R2200 R2201 R2202 R2203 R2205 R2208 RES.J.R/TP 1K ohm.1005.R/TP 0 ohm.J.R/TP 10 ohm.22 ohm.CHIP RES.1/16W.1005.R/TP 4.1005.R/TP 47 ohm.1005.R/TP 100K ohm.R/TP 10K ohm.R/TP 120K ohm.1005.1/16W.CHIP RES.J.R/TP 5.1005.CHIP RES.R/TP 3.1/16W.R/TP 47 ohm.1005.1/16W.R/TP 100 ohm.CHIP RES.1/16W.1/16W.CHIP RES.1005.1005.J.1/16W.1/16W.R/TP 0 ohm.1005.R/TP 0 ohm.R/TP 0 ohm.1005.1/16W.1005.1005.1005.1/16W.R/TP SVC N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N Color Remark -266- .CHIP RES.1/16W.1/16W.CHIP RES.1005.CHIP Description Part Number ERHY0000201 ERHY0000201 ERHY0000203 ERHY0000203 ERHY0000201 ERHY0000254 ERHY0000201 ERHY0000255 ERHY0000201 ERHY0000201 ERHY0000203 ERHY0000203 ERHY0000201 ERHY0000241 ERHY0000261 ERHY0000261 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000213 ERHY0000280 ERHY0000280 ERHY0000280 ERHY0000283 ERHY0000280 ERHY0000220 ERHY0000213 ERHY0000250 ERHY0000282 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000445 ERHY0000201 ERHY0008701 Specification 0 ohm.CHIP RES.1/16W.1005.1/16W.R/TP 100K ohm.J.R/TP 0 ohm.CHIP RES.1005.CHIP RES.1005.J.J.CHIP RES.1/16W.1/16W.J.J.1005.J.1005.CHIP RES.1/16W.CHIP RES.1/16W.1005.1/16W.7K ohm.R/TP 0 ohm.J.6K ohm.1005.1005.1005.J.J.1005.1/16W.1/16W.R/TP 0 ohm.1/16W.1005.1/16W.J.CHIP RES.R/TP 0 ohm.J.1/16W.CHIP RES.1005.J.1/16W.1/4W .1005.1/16W.1005.R/TP 1K ohm.R/TP 100K ohm.1/16W.CHIP RES.1/16W.CHIP RES.R/TP 100K ohm.CHIP RES.J .CHIP RES.R/TP 10 ohm.1/16W.CHIP RES.R/TP 0.J.R/TP 10 ohm.1005.CHIP RES.1608.J.2012 .J.CHIP RES.J.J.J.CHIP RES.1005.CHIP RES.R/TP 0 ohm.R/TP 10K ohm.R/TP 0 ohm.R/TP 0 ohm.R/TP 0 ohm.CHIP RES.J.J.R/TP 0 ohm.CHIP RES.1/16W.R/TP 0 ohm.J.CHIP RES.J.CHIP RES.1005.CHIP RES.J.CHIP RES.1/16W.J.J.CHIP RES.CHIP RES.J.1005.R/TP 0 ohm.J.1/16W.1/16W.J.1005.CHIP RES.CHIP RES.CHIP RES.R/TP 0 ohm.1/16W.1005.CHIP RES.J.J.R/TP 10 ohm.Level Location No.1005.CHIP RES.J.R/TP 0 ohm.1/16W.1005.R/TP 130K ohm.1/16W.CHIP RES.J.J.1/16W.

J.CHIP RES.R/TP 0.05 ohm.3K ohm.1005.CHIP RES.CHIP RES.J.CHIP RES.R/TP 0 ohm.J.1/16W.1/16W.2012 .1/16W.1/16W.1005.J.CHIP RES.J.1/16W.R/TP 0 ohm.J.1005.R/TP 15K ohm.R/TP 0 ohm.CHIP RES.1005.1005.1 ohm.1005.R/TP 0.1/4W .1/16W.1005.F.CHIP RES.CHIP RES.R/TP 0 ohm.R/TP 0 ohm.1/16W.1/16W.R/TP 0 ohm.CHIP RES.J.J.CHIP RES.1005.J .J.1/16W.J.1005.1/16W.1/16W.CHIP RES.J .R/TP SVC N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N Color Remark -267- .1/16W.CHIP Description Part Number ERHY0000201 ERHY0000201 ERHY0008701 ERHY0008602 ERHY0008601 ERHY0008601 ERHY0000201 ERHY0000201 ERHY0000280 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000261 ERHY0000274 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000254 ERHY0000250 ERHY0000263 ERHY0000213 ERHY0000261 ERHY0000201 ERHY0000201 ERHY0000241 ERHY0000143 ERHY0000280 ERHY0000280 ERHY0000201 ERHY0000138 ERHY0000252 ERHY0000252 ERHY0000138 ERHY0000280 ERHY0000203 ERHY0000266 Specification 0 ohm.CHIP RES.J.R/TP 0 ohm.CHIP RES.J.R/TP 100K ohm.R/TP 22K ohm.R/TP 33K ohm.1/16W.1/16W.R/TP 10K ohm.CHIP RES.22 ohm.CHIP RES.F.1005.1/16W.CHIP RES.1005.R/TP 51K ohm.J .1005.J.R/TP 0 ohm.CHIP RES.1005.1005.R/TP 10K ohm.1/16W.1/16W.CHIP RES.1/16W.J.J.R/TP 3.1/16W.R/TP 100K ohm.1005.1005.1005.R/TP 10 ohm.1/16W.R/TP 0 ohm.R/TP 33K ohm.1/4W .Level Location No.R/TP 0 ohm.1005.1/16W.CHIP RES.J.2012 .1/16W.1/16W.J.CHIP RES.1005.J.J.1/16W.1005.1005.9K ohm.1005.J.1/16W.J.1/16W.2012 .CHIP RES.CHIP RES.J.1/16W.CHIP RES.1005.R/TP 4.J.CHIP RES.CHIP RES.J .7K ohm.2012 .1005.1005.CHIP RES.CHIP RES.R/TP 0 ohm.05 ohm.J.1005.J.1/16W.1/4W .R/TP 3.1005.R/TP 0 ohm.1/16W.R/TP 100K ohm.1005.J.1005.CHIP RES.CHIP RES.J.1/16W.9K ohm.1005.J.1005.CHIP RES.R/TP 0.1/16W.1005.1/16W.J.CHIP RES.F.CHIP RES.J.CHIP RES.R/TP 47 ohm.CHIP RES.R/TP 43K ohm.1/4W .R/TP 1K ohm.R/TP 0 ohm.1005.J.1/16W.1/16W.R/TP 3.R/TP 0.R/TP 0 ohm.R/TP 100K ohm. 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 R2210 R2212 R2213 R2214 R2215 R2216 R2217 R2218 R2220 R2221 R2222 R2223 R2224 R2232 R2233 R2235 R2236 R2237 R2238 R2241 R2303 R2304 R2305 R2306 R2312 R2313 R2314 R2319 R2400 R2401 R2402 R2502 R2606 R2607 R2608 R2609 R2610 R2613 R2617 RES.1005.CHIP RES.CHIP RES.CHIP RES.J.CHIP RES.1/16W.R/TP 0 ohm.1005.

1005.R/TP 100K ohm.J.1005.CHIP RES.1/16W.R/TP 0 ohm.R/TP 0 ohm.J.R/TP 0 ohm.R/TP 100K ohm.R/TP 100K ohm.1005.1/16W.R/TP 0 ohm.R/TP 0 ohm.CHIP RES.1/16W.CHIP RES.CHIP RES.CHIP RES.CHIP RES.R/TP SVC N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N Color Remark -268- .J.CHIP RES.R/TP 0 ohm.1005.1/16W.1005.J.1005.1/16W.CHIP RES.1005.CHIP RES.1/16W.1005.1005.1/16W.R/TP 100K ohm.1/16W.R/TP 100K ohm.1/16W.R/TP 2.J.J.CHIP RES.1/16W.CHIP RES.1005.1/16W.1/16W.R/TP 0 ohm.CHIP RES.CHIP RES.CHIP RES.1005.J.1005.1/16W.J.1/16W.CHIP RES.J.1/16W.1/16W.CHIP RES.CHIP RES.J.1/16W.J.1005.1005.J.7 ohm.1005.1/16W.CHIP RES.1005.1/16W.CHIP RES.CHIP RES.J.R/TP 100K ohm.R/TP 0 ohm.1005.R/TP 0 ohm.R/TP 0 ohm.R/TP 0 ohm.CHIP RES.J.CHIP RES.1005.1/16W.1005.CHIP RES.CHIP RES.CHIP RES.1/16W.1/16W.J.R/TP 100K ohm.J.CHIP RES.1005.J.CHIP RES.CHIP Description Part Number ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000233 ERHY0000201 ERHY0000201 ERHY0000280 ERHY0000201 ERHY0000280 ERHY0000280 ERHY0000280 ERHY0000280 ERHY0000280 ERHY0000280 ERHY0000280 ERHY0000201 ERHY0000280 ERHY0000201 ERHY0000201 ERHY0000280 ERHY0000280 ERHY0000280 ERHY0000204 ERHY0000204 ERHY0000249 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000202 ERHY0000280 ERHY0000241 ERHY0000280 Specification 0 ohm.R/TP 100K ohm.R/TP 0 ohm.J.1/16W.1/16W.J.R/TP 12 ohm.J.1005.1/16W.1/16W.1/16W.CHIP RES.J.R/TP 0 ohm.R/TP 100K ohm.R/TP 0 ohm.R/TP 470 ohm.J.R/TP 100K ohm.CHIP RES.1/16W.CHIP RES.J.R/TP 0 ohm.1/16W.1005.J.1005.J.1/16W.J.R/TP 12 ohm.R/TP 0 ohm.1/16W.CHIP RES.1005.1005.J.1/16W.J.1005.J.J.1/16W.R/TP 100K ohm.R/TP 100K ohm.CHIP RES.R/TP 0 ohm.J.1005.R/TP 0 ohm. 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 R2618 R2619 R2620 R2621 R2622 R3002 R3019 R3026 R3031 R3041 R3042 R3043 R3045 R3046 R3047 R3049 R3050 R3051 R3103 R3110 R3126 R3127 R3206 R3207 R3208 R3209 R3223 R3227 R3228 R3229 R3230 R3232 R3237 R3248 R3249 R3263 R3303 R3319 R3322 RES.1005.1005.1/16W.J.CHIP RES.1005.1/16W.J.1005.1005.R/TP 4.R/TP 100K ohm.1005.CHIP RES.CHIP RES.1/16W.CHIP RES.J.CHIP RES.J.J.1/16W.1005.Level Location No.R/TP 100K ohm.1005.7K ohm.1005.1005.J.1005.J.R/TP 1K ohm.1005.CHIP RES.1/16W.1/16W.J.

CHIP RES.CHIP RES.CHIP RES.8V) USV .3K ohm.1/16W.1/16W.115 PIN.CHIP RES.1/16W.1/16W.7K ohm.J.R/TP 0.J.J.ADj.1/16W.NPN // PNP & R.1/16W.1/16W.1005.CHIP RES.R/TP 51 ohm.1/16W.J.1/16W.J.R/TP 100 ohm.8V) FBGA .1005.2 Kohm.3K ohm.J.1/16W.1005.1005.1005.1005.1005.1/16W.NMBI 8 .1005.R/TP 51 ohm.1/16W.F .J. SOT-23-5 . V / 500 mA PEAK LDO REGULATOR BGA .R/TP 100K ohm.1/16W.R/TP 4.8 mm.J.R/TP 51 ohm.128M FLASH MEMORY(1.CHIP RES.J.R/TP 8.J.CHIP RES.R/TP 51 ohm.CHIP RES.CHIP RES.R/TP 3.1/16W.7 ohm.R/TP 27 ohm.R/TP 100K ohm.3K ohm.1/16W.J.J.200 mW.J.R/TP .J.R/TP 0 ohm.1005.1/16W .R/TP .1/16W.1005.R/TP .R/TP 300K ohm. 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 R3323 R3325 R3327 R3328 R3329 R3330 R3331 R3332 R3341 R3344 R3345 R3346 R3347 R3357 R3360 R3363 R3364 R3365 R3366 R3367 R3376 R3378 R3379 R3380 R3381 R3382 R3383 R3388 R3389 R3390 R3395 R3396 R3397 R3398 SPFY00 U3102 U3103 U3104 V1001 RES.1005.1005.CHIP RES.2012 .1/16W.CHIP RES.1005.R/TP 51 ohm.1005.1/16W.R/TP 0 ohm.R/TP FR-4 .1/16W.R/TP 3.CHIP RES.R/TP 0 ohm.1/16W.R/TP 0 ohm.CHIP RES.J.CHIP RES.CHIP RES.F.5 PIN.R/TP 180K ohm.CHIP RES.CHIP RES.J.1/16W.J.J.1005.R/TP 3.1005.J.CHIP RES.1005.CHIP RES.CHIP RES.7K ohm.1/16W.CHIP RES.J.CHIP RES.1005.1005.1005.CHIP PCB.J.1/16W.1/16W.1/16W.1005.1005.1005.1005 .1005.J.1005.R/TP 2.J.R/TP 0 ohm.1/16W.R/TP 100 ohm.CHIP RES.R/TP 51 ohm.1005.CHIP RES.BJT.MAIN IC IC IC Description Part Number ERHY0000280 ERHY0000220 ERHY0000160 ERHY0008603 ERHY0000254 ERHY0000250 ERHY0000290 ERHY0000288 ERHY0000201 ERHY0000280 ERHY0000714 ERHY0000209 ERHY0000280 ERHY0000214 ERHY0000214 ERHY0000214 ERHY0000214 ERHY0000214 ERHY0000214 ERHY0000214 ERHY0000201 ERHY0000250 ERHY0000201 ERHY0000250 ERHY0000273 ERHY0000202 ERHY0000249 ERHY0000201 ERHY0000220 ERHY0000220 ERHY0000201 ERHY0000201 ERHY0000201 ERHY0000280 SPFY0061403 EUSY0045305 EUSY0192901 EUSY0192801 EQBA0002501 Specification 100K ohm.J.J.CHIP RES.R/TP 100K ohm.CHIP RES.R/TP 47K ohm..51 ohm.CHIP RES.R/TP 100 ohm.J.J.CHIP RES.1005.J.CHIP RES.1005.CHIP RES.1/16W.ARRAY -269- .1/16W.R/TP 4.1005.R/TP 240K ohm.1005.J.J.1/16W.CHIP RES.J.1/16W.1005.R/TP .1/16W. BUILT-IN TR SVC N N N N N N N N N N Y N N N N N N N N N N N N N N Y N N N N N N N N N Y Y Y N Color Remark TR.J .1/16W.1005.1/8W .CHIP RES.80 PIN.256FLASH 64PSRAM (1.R/TP 51 ohm.R/TP 0 ohm.R/TP 0 ohm.CHIP RES.Level Location No.

VF=1.5 mm.6.U8100 BACK-UP BATTERY 1.0.1. DCS RX RF SAW 942.TVS DIODE ARRAY SC70-6L .R/TP .TVS DIODE.SMD .100 W.15 mAh.0 .FIXED MICROPHONE EDSY0011901 EDTY0007001 EDTY0006401 EDSY0011901 ENWY0003001 ENSY0009901 ENJE0003401 ENBY0004202 ENBY0017602 ENEY0004101 SFSY0012901 SFSY0013001 SFSY0014201 SFSY0012501 SFSY0014301 SBEY0002901 SNMF0007401 SUMY0005601 N N N N Y Y Y Y N Y Y Y Y N N Y Y Y M38 M34 M22 -270- .5*2.2.5)T 1842. SOCKET for CAMERA 24 PIN.Au .SOCKET CONN. EMD2 .54 mm.SMD .0.R/TP .BOARD TO BOARD CONNECTOR.STRAIGHT .RF SWITCH CONN.9T .2T UIM CONNECTOR WITH BRIDGE . 60 PIN.1 A.30 V.SWITCHING CONN.0*1.6T 8 PIN.R/TP .9 V.2.0X3.U8100 MIC SVC N N Color Remark 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 3 3 3 V2203 V2300 V3201 V3202 W1001 X2300 X2602 X3200 X3201 X3203 Z1100 Z1110 Z1400 Z1420 Z1500 SBEY00 SNMF00 SUMY00 DIODE.JACK/PLUG.U8100 DUAL BAND(GSM.VF=1.UMTS Tx RF SAW 1.-44 dB.8 . IR=30uA(VR=10V) STRAIGHT .09 pF.4 mm.5 V.3.5*0.2.0.R/TP .0*1.SAW BATTERY.SMD .6 dB.GSM RX RF SAW 2140 MHz.8X3.8 .1 A.5 V.R/TP . IR=30uA(VR=10V) SOT23-6 .0.MOBILE.VARIABLE CAP DIODE.ETC ANTENNA.0*0.0*2.TVS DIODE.8*1.8*3.BOARD TO BOARD CONN.3*10*(3+1.EARPHONE CONNECTOR.5V(IF=200mA) . dB.RECEPTACLE FILTER.5V(IF=200mA) .5 MHz.30 V. W.STRAIGHT .1 A. IR=30uA(VR=10V) EMD2 .2.WCDMA) ASSY .SWITCHING Part Number EDVY0001801 EDSY0011901 Specification SCD80 .SMD .SAW FILTER.5*0.8 .8 .25.9t.B to B CNT(Header) 20 PIN.SAW FILTER.0.5 MHz. .3.3 .2 .SMD .SAW FILTER. 5 5 V1770 V2201 Description DIODE.WCDMA RX IF SAW 1900 MHz.SMD . EMD2 .SWITCHING DIODE.VF=1.AU .2.5V(IF=200mA) .WCDMA Rx RF SAW 190 MHz.0*2.ETC .5*2.Level Location No. PIN.2.SMD .30 V.SAW FILTER.R/TP .

CE.5.7 V.CB .U8150 STD BATTERY PACK DK-40G .Cresyn FREE .50 Hz.2 V.PRISMATIC . 2 MHBY00 Description HANDSTRAP Part Number MHBY0000404 130mm 3.800 mA.UK(IO.24P) V074I Bundle CD SW Version 1.AC-DC SOFTWARE SOFTWARE SBPL0072201 SGDY0005601 SGEY0003701 SSAD0007835 WSYY0115011 WSYY0115211 Y Y Y Y N N -271- .0 Specification SVC Y Color Dark Gray Remark 2 2 2 2 2 2 SBPL00 SGDY00 SGEY00 SSAD00 WSYY00 WSYY01 BATTERY PACK.LI-ION DATA CABLE EAR PHONE/EAR MIKE SET ADAPTOR.K8000 24PIN I/O + USB A TYPE U8110 .3 Accessory Level Location No.1200 mAh.11.1 CELL.

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