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Book 2

Module 4

** ..

.. *

.... ..

.... ..

...........

TRANSISTORS

TED. CIRCUIT ~~~:z:""IRb.uj'.i.'~'BO' - . __ :"".L'.:

J': .... ;';'~~:";:i"~\\':;'" ".~~,!,;y~?}<.:l."., ~ ..... ~,.I~.:~~~~

Licence By Post

The staples in this book can catch fingers. Not suitable for smallchildren. Care when handlinz.

Licence By Post © Copyright

8 4.1.2 to 4.2 ISSUE 2 62

AUTHORITY

It is IMPORTANT to note that the information in this book is for study /training purposes only.

When carrying out a procedure/work on aircraft/aircraft equipment you. MUST always refer to the relevant aircraft maintenance manual or equipment manufacturer's handbook.

You should also follow the requirements of your national regulatory authority (the CAA in the UK) and laid down company policy as regards local procedures, recording, report writing, documentation etc.

For health and safety in the workplace you should follow the

tegulaticns / guidelines as specified by the equipment manufacturer, your company, national safety authorities and national governments.

CONTENTS

Transistor theory & construction Transistor testing

Transistor as an amplifier Directly coupled amplifiers Classes of amplifiers Multivibrators

Flip-flops

JUGFETs

MOSFETs

CMOS

Feedback in amplifiers Oscillators

The transistor as a switch Integrated circuits Operational amplifiers Logic circuits

SR flip-flops

Clocks

JK flip-flops PCBs

Page

1

5

5 15 17 21 24 26 28 30 31 33 34 35 38 45 50 51 52 54

HOW TO TACKLE THIS BOOK

The same applies to this book as applies to book 1. This means that it is written to the 82 level, and 81 people should check the syllabus to see what subjects should be learnt and to what depth. None of the contents applies to the A Line Mechanic.

For category 8 engineers the book will probably need at least 2 read throughs to get the information to sink in - in some cases it may need more.

TRANSISTORS

Construction and Theory of Operation

The bi-polar or junction transistor consists of two P-N junctions in the same crystal. If two P-N junctions were fused together so that the two 'N' regions form a very thin (0.1 to 1mm thick) lightly doped layer between the two more heavily doped 'P' regions a P N P transistor is formed. Figure 1 shows the layout of the transistor and its symbol. Note the electrodes are called COLLECTOR, BASE and EMITIER (emitter - the one with the arrow in the symbol). The emitter is more heavily doped than the collector.

Collector C

B Base B

Emitter E

Fig. 1 PNP TRANSISTOR

Similarly if two heavily doped 'N' regions are separated by a very thin lightly doped 'P' region then an N P N transistor is formed. Figure 2 shows the layout and its symbol. The emitter is again more heavily doped than the collector.

Note. For both the PNP and NPN transistors the arrows show the direction of conventional current flow.

Collector C

Emitter E

Fig. 2 NPN TRANSISTOR

- 1 -

Action of NPN Transistor

For transistor action to occur the BASE-EMITIER junction must be forward biased (POSITIVE to 'P', NEGATIVE to 'N') and the COLLECTOR-BASE junction must be reverse biased (POSITIVE to 'N', NEGATIVE to 'P').

It should be noted that the battery E, is much smaller than the battery Ee, it must also be of sufficient voltage to overcome the barrier potential of O.6v for silicon.

n p n

E!~ctr~~s 112: 7ZI!lJ>

-electrons now out

Ec

._,__e--_--i 1111 ~ +

Forward bias

Reverse bias

ARROWS INDICATE ELECTRON FLOW CONVENTIONAL FLOW IS IN THE OPPOSITE DIRECTION

Fig. 3 NPN OPERATION

Under the influence of the electric field due to battery Ee electrons cross the junction into the base. Only a small proportion (about 1 to 2%) of the electrons combine with holes in the base due to it being very thin and lightly doped. Most of the electrons (98 to 99%), under the very strong positive influence of the battery Ee, are swept through the base to the collector to E, to form the collector current in the external circuit.

Electrons are the majority carriers in the N P N transistor.

The small amount of electron-hole combination in the base gives it a momentary negative charge, which is immediately corrected by battery E, supply holes, or can be considered as electron flow. Remember conventional current flow is in the opposite direction.

So transistor action is the controlling of a large current in the high resistance (reverse biased) collector-base junction by a small current through the low resistance (forward biased) base-emitter junction.

. .

: Base

Fig. 4 CONVENTIONAL CURRENT FLOW NPN TRANSISTOR

Action of P N P Transistor

Again the base-emitter junction is forward biased and the collector-base junction is reverse biased.

Under the influence of the electric field due to battery Ee, holes cross the junction into the base. Only 1 to 2% of holes recombine with free electrons in the base due to it being very thin and lightly doped. The majority of the holes 98 to 99% are accelerated towards the Vf~ry strong negative influence of battery Ec. Holes are the majority carriers in the P N P transistor.

Forward bias

Reverse bias

ARROWS INDICATE ELECTRON FLOW _CONVENTIONAL FLOW IS IN THE OPPOSITE DIRECTION

Fig. 5 PNP OPERATION

Due to recombination of holes and electrons in the base, the base loses free electrons and will therefore exhibit a positive charge. The electrons will be attracted by battery E, into the base to 'make-up' for those lost by recombining with holes. Figure 6 shows the conventional current flow through the transistor.

- 3 -

Base

Fig. 6 CONVENTIONAL CURRENT FLOW PNP TRANSISTOR

Since the carriers in the N P Nand P N P transistors originate at the emitter and distribute themselves between base and collector, the sum of the base and collector currents must always be equal to the emitter current, therefore:

I, = l, + Ib

Type:'

BF'194

BCJ08

ZTX300

2N3705

2N3053 & BIT5l

B E C C BE C BE B C E C B E
MM10B 1018 E-line (X59) T092a 105 (metal can
[plastic] (metal) (PIss tic) [plastic] connected to C)
Fig. 7 TYPICAL TRANSISTORS The transistor can be used as an AMPLIFIER circuit and also as a SWITCH. The amplifier action is based on applying a low current to the base-emitter with a higher current flowing through the collector-emitter.

The switching action is the effect of applying a small current to the base for the unit (NPN) to 'switch on' allowing current to flow between the collector-emitter. Removing the base-emitter current will cause the unit to switch off. These switching times can be very fast (say 2ns or 2 x 10-9 seconds or 0.000 000-002 seconds) (ns = nano seconds). Fast switching times are needed in computing.

- --t -

Testing Transistors

Using an analogue multi meter switched to the ohms range. On most analogue multimeters on the ohms range the negative (-) terminal has a positive polarity and the positive terminal (+) has a negative polarity. This is an important point with regards to identifying N P Nand P N P transistors. If a digital multimeter is used then check the polarities of the terminals on the ohms range.

Figure 8 shows the readings you would expect using an analogue multimeter.

LOW RESISTANCE HIGH RESISTANCE

c

+

LOW RESISTANCE HIGH RESISTANCE

MULTIMETER

+

+

+

NPN

PNP

c

Fig. 8 TESTING TRANSISTORS USING A MULTIMETER

LINEAR circuits are amplifying-type circuits. They will have analogue inputs and the output will vary continuously and be more or less an exact but amplified copy of the input, ie the output is a linear representation of the input. Many class A transistor amplifiers, eg audio frequency and radio frequency amplifiers, are linear circuits.

TRANSISTOR AS AN AMPLIFIER

First of all we need to look at how the bias is applied in a practical circuit. In our previous discussions batteries were used for the bias.

+

Fig. 9 AMPLIFIER CIRCUIT - 1

-

- J -

If dc only is applied to the circuit shown figure l O then Rl and R2 will divide the t""',

supply voltage into the same ratio as that of the resistors. So if the resistor values

were 80kD and 20kD then with a supply voltage of lOv the voltages across Rl and

R2 would be 8v and 2v respectivelv.

Fig. 10 AMPLIFIER CIRCUIT - 2

The voltage across must be 0.6V to overcome the barrier potential. This could be achieved by removing RE and making R2 of such a value so that 0.6V is dropped across it, however t.he problem here would be R2 would have to be quite low and the amplification would be restricted

The voltage across the base emitter Junction (VSE) must be O.6V and is the difference between the voltage across R: and RE. VSE = VR2 - VRE.

t

-t

1.4v

~

2v

Fig. 11 AMPLIFIER CIRCUIT - 3

So RE must be of a value that when the standing de current is flowing l.4v will be dropped across RE leaving VSE to be 0.6v.

So in the static condition, ie dc only applied, a standing current (quiescent current) flows through the circuit and TR l, Ri , R2 andRE provide the bias necessary to operate TR 1 and allow current to flow.

- 6 -

---5v

Fig. 12 AMPLIFIER CIRCUIT - 4

With current flow through RL and TRI there will be a voltage drop across RL. Let us assume this voltage drop is 5v so that the standing voltage is 10-5 = 5v.

This is the condition that when dc is applied to the amplifier, all bias voltages are applied and a standing voltage is at the collector of TR 1.

We now need to look at applying a signal to the amplifier. This will be a small ac signal (which may be superimposed on a dc level), so only ac must be applied to the amplifier.

Capacitor CI will block any de component, and also the output amplified ac value must only be passed onto the next stage if again C2 blocks a de component. These capacitors are known as COUPLING CAPACITORS.

It is also essential that the voltage across RE remains constant, and therefore VBE remains constant so that the ac input signal adds to and subtracts from the steady VBE bias.

Fig. 13 AMPLIFIER CIRCUIT WITH COUPLING/ DECOUPLING CAPACITORS

- I -

To ensure this, a capacitor is connected across RE This capacitor will have a ,1"""\

capacitive reactance at the operating frequency very much lower than RE This

means that if the ac "bypasses" RE it will leave a steady dc across RE. This

capacitor C3 is known as a DECOUPLING CAPACITOR.

Please note the figures quoted are purely explanatory, and actual values will depend on the individual circuits. Also, the transistor used is an N P N but everything applies equally as well when using a P N P transistor except the positive rail would be at the bottom.

Action With an ac Signal

Assume that with de applied the voltage at the collector is 5V. If a 2.5mV signal is applied as the input then when the ac signal goes positive it will add to the de bias. The transistor will switch on more and the current through the transistor will increase and the voltage drop across RL will increase, so the collector voltage

will fall. Assume if falls to by O.25V. ~

2.5mV c·

~ +-H-'

Fig. 14 AMPLIFIER ACTION - 1

When the ac voltage goes negative, it opposes the bias and the transistor conducts

less, the current through RL is less so the volts drop is less and the collector ~

voltage rises.

2.5mV

Fig. 15 AMPLIFIER ACTION - 2

- 8 -

So you can see with an input voltage of 2.5mV we get an output swing of 0.25V so

therefore there is a gain (output) 0.25 = 100

(Input) 2.5mV

Please note again the values used are for explanatory purposes only.

Also note the function of RL (load resistor) without it there would be no voltage changes at the collector and no amplification.

Another purpose, (probably its more well known one) for RE. the resistor in the emitter lead, is as a temperature compensating resistor.

If the temperature increases, the resistance of the transistor decreases, this causes greater current through the transistor and therefore a greater voltage drop across RE. If you remember the voltage across the base-emitter junction is VR2- Vbe and this will decrease thus reducing the forward bias, reducing the current, compensating for the original increase.

This amplifier configuration is known as a COMMON EMlTIER AMPLIFIER. As you have seen it has a VOLTAGE GAIN Vout typically 100 - 600.

v;

It also has a CURRENT GAIN lout = k typically 50 - 300.

lin Ib

So it is a current amplifier as well as a voltage amplifier.

If there is a current gain and voltage gain then there must be a power gain Power out typically several thousands.

Power In

The input impedance is (Zin = Vin) typically 600 - 2000 n lin

And the output impedance is (Zout = Voud typically 10 - 50 kn. lout

Also note the phase relationship between the input and the output is 180°.

The COMMON EMlTIER amplifier is used for the majority of amplifier applications.

There are two other amplifier configurations, the COMMON BASE and the COMMON COLLECTOR.

- 9 -

Common Base Amplifier

With reference to figure 16. If the input goes positive then the emitter is positive to the base and this reduces the bias voltage and the current through the transistor falls. The volts drop across RL falls and the voltage at the collector rises. When the input goes negative t.he emitter is negative with respect to the base and the bias increases, the current increases and the volts drop across RL will increase and the collector voltage falls.

Fig. 16 COMMON BASE AMPLIFIER

Other characteristics of the common base amplifier are:

Current Gain (Ie/Ic) Vol tage Gain

Power Gain

Input impedance Output impedance

medium low high

less than 1, typically 0.98 typically 500 - 800

compared to common emitter typically 500 to 2000 typically 100kO to 1 MO

Input and Output signals are in phase. Because of their very low input impedance and high output impedance they are used as impedance matching devices.

Common Collector Amplifier (Emitter Follower)

When the input goes positive this will increase the bias, the transistor will conduct more and the volts drop across RE will increase and the top of RE will go more positive. When the signal goes negative the bias will decrease, the transistor Wi11 conduct less the voltage across RE will decrease and the top of RE goes more negative.

- 10 -

+

c,

p; -1 ~---+-t::~ ~ o/p PD-

Fig. 17 COMMON COLLECTOR AMPLIFIER

Other characteristics are:

Current Gain (Ie Zlb] Voltage Gain

Power Gain

Input Impedance Output Impedance

low high low

typically 20 - 200 less than 1

compared to Ca and CE 20kD to 100kn

20n to soon

The input and output signals are in phase. Because of its high input impedance and low output impedance it again is used for impedance matching.

Figure 18 shows the comparison between the three amplifiers.

Each amplifier has the word common in front. This means that the input and output signals are common to whichever electrode is stated.

COMMON EMMITTER

INPUT BETWEEN BASE & EMITTER

OUTPUT BETWEEN COLLECTOR & EMITTER

COMMON BASE

INPUT BETWEEN EMITTER & BASE OUTPUT BETWEEN COLLECTOR & BASE

COMMON COLLECTOR (EMITTER FOLLOWER)

INPUT BETWEEN BASE & COLLECTOR OUTPUT BETWEEN EMITTER & COLLECTOR

If you have difficulty

Identifv

SIGNAL IN

identify

SIGNAL OUT

- 1 1 -

WHATS LEFT IS WHAT ITS ALL ABOUT 11

SIGNAL IN on base }

What's left? - emitter SIGNAL OUT on collector

eg

Hence common emitter.

COMMON COLLECTOR

VOUT

i

I COMMON EMITTER

,--.---------- - --,-- --.- ----.---------t---

I 2010200 i

CURRENT

, GAIN

r--------t---------------+-

I VOLTAGE GAIN I 100 to 600

I POWER GAIN I High

COMMON BASE

, 1 '

(0.95~0.9~

500 to 800 I

Medium

20 tO~~ __ J

I

< 1

Low

I
1 --- 1---
"_--_- --
INPUT 500 to 20000 I 50 to 2000 20kD to 100kD
IMPEDANCE
I OUTPUT 10kO tv 50kn I 1001.11 to 1 MO :2JO to 5000
I IMPEDANCE I
INPUT-OUTPUT
PHASE 1800 out of phase In phase In phase
RELATIONSHIP
TYPICAL I Impedance Impedance
USE Normal amplifier I matching matching
I {low to high) (high to low) Fig. 18 TABLE OF COMPARISONS

In many cases the amplifications of a single stage amplifier is insufficient and several stages have to be used. If this is so the output.of one stage is the input to the next, ie they are connected in cascade.

- 12 -

22kO

7000

S~f """F---4t-+ 0 I p signal

ilp signal

3.3kO

50).lf

Fig. 19 TWO STAGE RC COUPLED AMPLIFIER

Figure 19 shows a resistor (R3) and a capacitor (C2) coupled two stage common emitter amplifier.

\.

~,," c·_"""''''·

,._

Another method of coupling stages of an amplifier is by using transformers. Using the correct turns ratio the high output impedance of stage 1 can be matched to the low input impedance of stage 2, thus giving a considerable increase in gain over RC coupled stages. However, due to the change in impedance with frequency, its frequency response is poor compared with the RC coupled amplifier. The uneven response, shown in figure 20, causes distortion.

However, they are often used between the output stage and a loudspeaker load. (High to low impedance matching).

TRANSFORMER COUPUNG

~

. .

....... ;;; ..

r ...

. .

R-C COUPLING

.

,

100 1;000

FREQUENCY (c/s)-."~

Fig. 20 TRANSFORMER & RC COUPLED RESPONSE CURVES

10,000

- 13 -

--~---------r--------------r-.--------.------------+~

o

0.1 uf

01 uf

Fig. 21 TWO STAGE TRANSFORMER COUPLED AMPLIFIER

If the gain of stage 1 is 5 and the gain of stage 2 is 20 then the overall gain is 100 (5 x 20). The overall gain is the product of the individual gains.

DIRECTLY-COUPLED AMPLIFIERS

Coupling amplifier stages to one another via capacitors or transformers makes it easv to couple together points with differing dc voltage levels. However, this form \)f amplifier will only amplify an alternating signal, completely ignoring de voltages and will respond poorly to signals of very low frequencies

Many control systems found in aircraft produce signals that vary only infrequently and this makes it necessary to use directly-coupled amplifiers in order to amplify those variations. Careful matching of transistors and associated components IS essential if these amplifiers are to perform correctly. They are particularly sensitive to voltage and temperature variations.

Simple Direct Coupling of two Bi-polar Transistor Amplifiers

The emitter bias resistor in TR2's circuit (R) produces a series current negative feedback, reducing the overall gain of the amplifier to a minimum. Figure 22.

- 14 -

INPUT

Fig. 22 DIRECT COUPLED BI-POLAR TRANSISTOR AMPLIFIER

Direct Coupling with Zener Diode Bias

A Zener diode in the emitter circuit of TR2 (figure 23) maintains a constant voltage at the emitter and thus increases the overall gain of the amplifier. It also goes some way towards decreasing the effects of any variation in supply voltage.

L.ORt. 1

L.ORO a

OUTPUT

INPUT

Fig. 23 DIRECT COUPLING WITH ZENER DIODE BIAS

DIfFERENTIALLY CONNECTED AMPLIFIERS

If two identical directly-coupled amplifiers have the same power source, then a change in supply voltage will not cause a change in the difference of their outputs. There is similarly' no change in the difference of their outputs if the ambient temperature changes.

- 1 S -

The only thing that will produce a change in the difference at their output is a ~

variation in their signal inputs.

The 'Long-Tailed Pair' Differential Amplifier

Figure 24 shows the arrangement of the 'long tailed pair'. Note the output is across the collectors of the two transistors, and that they have a common emitter via a resister (R).

OUT,.UT

INPUT 2

Fig. 24 THE LONG TAILED DIFFERENTIAL AMPLIFIER

o

II

Fig. 25 THE DARLINGTON PAIR

The Darlington Pair

This arrangement (figure 25) gives a high current gain. It can also be used in the Common Collector or Emitter Follower configuration with currents in the order of milliamps, in which case its main benefit is the increase in input impedance due to the reduction of current taken bv the first transistor.

- 16 -

Classes of Amplification

When a transistor is used as an amplifier the input circuit is normally biased to some particular working point. There are three basic classes of bias, named according to the working point chosen.

Class A

The amplitude of the input signal and bias are such that there is an output current for the full cycle of the input signal. This is the most commonly used class of bias in amplifier circuits.

Class B

The bias is such that current flows for only half of the cycle of input signal, for the other half of the input cycle the transistor is "cut off'. This is usually employed in power amplifiers.

Class C

The bias and amplitude of input signal are such that current flows for less than half of each cycle. Used in oscillators and selective amplifiers.

Efficiency

This is defined by ac power output to load x 100%

dc power taken from supply

An amplifier which produces low power output has an efficiency which is no greater than 50%. This is oecause it is worki.ig under Class A c.mditions and the de standing (no input) current is large and produces wasted de power.

To overcome this problem in power amplifiers the push-pull amplifier was introduced.

blank

- 17 -

..

~----::;O"".~'::::'_-""':::"':""'~:---'o:;J.....-: .... : ---I •• time

: : :

: : :

l ; ~

,~,- 'A---'Io-6-7I'--P-~'--- .. time

· .

· .

· .

· .

· .

· .

· .

vAl ;:I~

~B~ ~---~:---~.~~---+:-~ ... time

: :

_,_ 'It-'-~~-..;.__...o~~--. .. time

Fig. 26 GRAPHS OF INPUTS AND OUTPUTS FOR CLASSES A, B, & C AMPLIFIERS

Push-Pull Amplifier

Figure 27 shows a simple push-pull power amplifier using an N P N type and P N P type transistors. The load is a loudspeaker and is connected to both emitters via a dc blocking capacitor.

AO--~

+ Vee

AC INPUT

-Vee

B 0--------------'

Fig. 27 PUSH PULL AMPLIFIER

- 18 -

Operation

When an input is applied, assuming at this moment in time that the input at A is positive to 8 (positive half cycle), the base emitter junction of TRJ is forward biased. There is therefore an output to the loudspeaker (positive half cycles). During this time TR2 is reverse biased (base negative with respect to emitter).

Negative half cycles of the input (8 positive to A) will reverse bias TRJ and it will cut off and forward bias TR2, this time there is again an output; this time on the negative half cycles.

As each transistor conducts for one half of each complete input cycle, the amplifier is working in Class 8 conditions.

When there is no input, neither transistor conducts, therefore no de power is wasted. The maximum efficiency of a Class 8 power amplifier is high (78%) when compared with a Class A amplifier (50%).

One disadvantage of the simple circuit is that each transistor does not tum on until the input is about 0.6V. As a result there is a dead zone producing 'crossover' distortion (see figure 28).

+
0
'~"l
i; ..
+
TR1
EMITTER
CURRENT 0 I
I
TR2 o I
EMITTER I II
I II
CURRENT I II
I ~
+
OUTPUT 0
VOLTAGE ; I VOLTAGE II TR2

II

I ~

CROSSOVER DISTORTION

Fig. 28 CROSSOVER DISTORTION

- 19 -

This is overcome by forward biasing the base-emitter junctions of both transistors. Figure 29 shows a push-pull amplifier with this biasing to the two transistors being provided by resistors R 1, R2 and R3 via the secondary winding of transformer T 1.

Fig. 29 PUSH-PULL AMPLIFIER

Operation

Under static (no input signal) conditions, equal currents will flow through the two halves of T2's primary winding and through the two transistors and R3 to the -ve rail. There will therefore be no resultant flux in T2 from this de source. Therefore no de power is wasted and its efficiency is high (78%).

Transformer T1 is a phase-splitter, providing inputs to the transistors which are equal but in anti-phase.

When the top of T1's secondary winding is positive, TR1 will be switched ON (circuit via base-emitter -- CL] and TR2 will be switched OFF. As the collector current of TR 1 increases, that of TR2 decreases. More current will flow from the +ve rail through the top half of T2's primary winding, collector - emitter TR 1 and R3 to the -ve rail.

When the bottom of Tl's secondary is positive, TR2 will be switched ON (circuit via base-emitter - C 1) and TR 1 will be switched 0 FF. As the collector current of TR2 increases, that of TR 1 decreases.

Current will flow from the +ve rail through the bottom half of T2's primary winding, collector - emitter of TR2 and R3 to the -ve rail.

- 20 -

The changing currents in the primary of T2 results in an output which is an amplification of each half of the input signal.

This is then operating in Class AB conditions, being a compromise between the low distortion, low efficiency Class A amplifier and the higher efficiency, higher distortion Class B amplifier.

MULTIVIBRATORS

These are transistor switching circuits of two stages with the output of one stage being fed back to the input of the other by coupling resistors or capacitors. The output of one is 'high' the other is 'low' and this occurs alternatively producing a square wave output. There are three basic types:

l. 2. 3.

Astable or free running multivibrator Bistable or flip-flop

Monostable or 'one shot'

Figure 30 shows the basic circuit of a Bistable Multivibrator.

BISTABLE

Fig. 30 BISTABLE MULTIVIBRA TOR

Operation

When the de supply is switched on then, because of the slight differences in manufacture, one transistor will conduct more than the other. This causes say, TRJ to switch fully on while TR2 switches off.

At this point TRJ collector voltage is low (high voltage drop across R3), there is therefore iiisufficient voltage to drive current through Rl to the base of TR2. TR2 remains off and its collector voltage being high there is current flow through R2 to maintain TRJ switched on. The output at Q is high (logic statel) and the output at Q is low (logic state 0).

- ::2 1 -

By applying a positive signal to the base of TR2 via R6 (shown on the diagram as a ("']

switch but in a practical circuit would be a temporary input signal) TR2 would

conduct, causing its collector voltage to fall to a low value (lower than 0.6v). TRI

base current ceases and TRI switches off, its collector voltage rises to a high value

and this is fed through Rl to the base of TR2 keeping it switched on. Q is

therefore low (logic 0) and Q is high and therefore at logic state 1.

Each transistor can be made to 'flip' to a high collector voltage or 'flop' to a low collector voltage changing the outputs on Q and Q. The switching can also be achieved by applying a negative voltage to the base of the transistor that is conducting.

The inputs R & S would be supplied by a trigger pulse and this circuit is the basis of the SR flip-flop Q = 0 Q = 1 -;- reset condition, Q = 1 Q = 0 ~ set condition. These are used in memory circuits and binary counters in digital computers.

ASTABLE MULTIVIBRATOR

When the supply is connected as before one transistor conducts faster than the other (due to slight manufacturing differences) and cuts the other one off. In this multivibrator each transistor then switches automatically to its other state and then back to its first state, producing an output of square wave pulses.

Action

With reference to figure 31 Assume TR2 ON and TRI OFF. The base of TRI is negative at the moment, but is approaching cut on (base voltage going positive) on a time constant determined by C2 R2.

Fig. 31 ASTABLE MULTIVIBRATOR

- .2.2 -

When TRI conducts, its collector voltage falls to a low value and since capacitor Ci cannot change its charge instantaneously there is no change of capacitor voltage during the rise of conduction of TRI.

Therefore the fall of collector voltage at TRI causes TR2 base to fall by the same amount causing TR2 to cut off, causing TR2 collector voltage to rise.

This multivibrator produces a continuous stream of almost square wave pulses, ie it is a square wave oscillator. It requires no input trigger and is

sometimes called a relaxation oscillator.

It is extensively used for producing timing (clock) pulses for digital systems. Remember, everything in computing works in synchronisation with a (very fast) electronic clock.

MONOSTABLE VIBRATOR

Figure 32 refers. Again, when the supply is switched on the circuit settles into the state TRI OFF and TR2 ON, therefore Q == O.

A positive trigger pulse, represented by the switch in the diagram will switch TRI ON, Cr right hand plate falls rapidly switching off TR2 making the output Q go high. Now the capacitor charges up through R, making the right hand plate go low TR2 is switched on again and the Q output goes low.

~--------~-----r----------.-------e+Vcc

(6V)

TR1

+6V .......... -c==r----+------c Q OUTPUT _fl_ OV

TR2

Fig. 3-2 MONOSTABLE MULTMBRATOR

This multivibrator has one stable state and one unstable state. It can be switched into its unstable state for a certain time (determined by the-values of C and R) and then returns to its stable state. It can be used to create a pulse of known timing to act as a delay circuit in digital systems.

- 23 -

The Multivibrators we have seen are using junction transistors, however, they can rJ be constructed using Field Effect Transistors (FET's) logic gates and operational amplifiers (to be discussed later).

FLIP-FLOPS

The JK Flip-Flop

Figure 32 shows the JK flip-flop. Study it for a few minutes and note the layout of the system including the inputs at J and K.

SUPPLY: G 11011.10 do

~----------------~--~+

Fig. 33 JK FLIP-FLOP

Operation

Suppose that TR4 is conducting and that TR3 is cut off. Q is at logic O. If logic 1 is applied to J and logic 0 to K, there would be no effect because there would be

no change to the diodes 01 and 02. A falling (1-0) signal at T will cause the <:»

transistors to change over in the usual way, so Q now goes to logic 1. However, a further falling pulse at T will have no effect on the circuit if J is still at logic 1. It follows, therefore, that a trigger pulse at T will only change the state if the logic

levels atJ and K are reversed. From this it can be seen that A TRIGGER PULSE

AT 'T' WILL ONLY CHANGE THE STATE IF THE LOGIC LEVELS AT 'J' AND 'Q'

ARE DIFFERENT. It also follows that a Logic 0 or a Logic 1 can be stored at J

until a trigger pulse arrives at T, when it will be released at Q.

R S FLIP FLOP

Operation

With reference to figure 34 (circuit and symbol). When power is applied, currentbiasing will be applied to each transistor base-emitter by way of R2-R4 to T1 and R 1- R3 to T2. Although the two 'sides' are identical, mis-matching will mean that one transistor will start to conduct before the other. If silicon transistors are being used, 0.6 volts is needed across the base-emitter for switching ON.

eli Q
S R -

Q

Q

SUPPLY: 6 V

OUTPUT;

5

R

Fig. 34 RS FLIP-FLOP CIRCUIT & SYMBOL

Suppose that T2 reaches the point of switch-on before Tl. When T2 conducts, the volts drop across R2 becomes almost 6 volts and the T2 collector voltage now applied via R4 to the base of T1 becomes almost zero, forcing T1 into a 'cut-off non-conducting condition.

The volts drop across R1 is almost zero and so 6 volts is applied via R3 to the base of T2, keeping it switched hard-on. Under these conditions, the two outputs are:

Q six volts (Logic 1) and Q zero volts (Logic 0).

A positive pulse at S (SET) will cause T 1 to conduct and the ensuing volts drop across R 1 will switch T2 off. The two outputs will now be:

Q zero volts )Logic 0) and Q six volts (Logic 1).

A positive pulse at R (RESET) will send the outputs back again to the original condition. So, a pulse at S sets Q at Logic 1 and a pulse at R sets Q at Logic 0:

These devices are widely used in storage and timing device circuits.

FIELD EFFECT TRANSISTORS

("\ ..

There are two basic types of Field Effect Transistors (FET's). A Junction Gate FET (JUGFET) and a Metal Oxide Semiconductor FET (MOSFET)

JUGFET

With reference to figure 35. The bar of N-type material provides the medium through which the majority carriers (electrons) pass. In doing so, they have to pass between the two sections of P-type material, known as the Gate. The two Ptype sections are usually connected together electrically (so are at the same potential) and are used as the Control electrode. Current enters at the SOURCE electrode and leaves at the DRAIN electrode.

SOURCE Terminal

....... D_R_A I N

Terminal

/ p-t.ype

GATE

-, N-t.ype

Channel

Fig. 35 JUGFET

As in any semiconductor device containing P-N junctions, depletion zones exist at these junctions. In this device, the P-type gate sections are more heavily doped

than the N-type channel. This results in the depletion zone extending further into .:»

the channel than it does into the gate.

Souroe

Souroe

N-CHANNEL

P-CHANNEL

Fig. 36 JUGFET SYMBOLS

- 26 -

Note: The opposite arrangement of a P-type channel and N-type gate is also available.

Operation

With reference to figure 37. The Drain-Source voltage Vos sets up a current flow of majority carriers through the channel. The Gate-Source voltage VGS reversebiases the gate-channel junction, thus increasing the width of the depletion

zones. As can be seen in the diagram, these zones are not uniform in shape. This is because the potential gradient between drain and source produces a greater potential difference between the gate and the channel towards the drain than it does towards the source. Thus we have characteristic 'wedge' shaped depletion zones.

Vos

Fig. 37 JUGFET SCHEMATIC

Since no majority carriers exist in the depletion zones, the width of the channel through which they can flow is dependent on the size of these zones and hence on the value of VGs. It is in this way that VGS controls the current flow. Under normal operating conditions, the gate-channel junction is reverse-biased so that only a very small leakage current flows in the gate-source circuit. It has, therefore, got a very high input impedance.

Uses

The JUGFET can be used as an amplifier or a switch and the next diagram shows it connected as an amplifier. Its input resistance is very high compared with that of a transistor (1 x 10 lOD compared to 1 to 5kD for a transistor). Its output impedance is SOkD to 1 MD compared to a transistors output impedance of 10- SOkD.

- 27 -

Rl

Signal In

~: Rg l1aint.aln~ a High Input.

Imp.dong •.

Fig. 38 JUGFET AMPLIFIER

MOSFET

Also called an Insulated Gate Field Effect Transistor - IGFET. The basic construction of an n-chanriel MOSFETand symbol is shown in figure 39.

D

DRAIN D·

N CHANNEL

s

SOURCE S

Fig. 39 MOSFET & SYMBOL (N CHANNEL DEPLETION)

-

The main difference between this device and the JUGFET is that there is no direct electrical connection between the gate terminal and the semiconductor material.

Instead they are insulated from one another by a very thin layer of highly .:»

insulative silicon oxide.

ID/mA

DEPLETION MODE ---

\{)s = 20V

A ·3 ·2 ·1

1 2 3 4

't>SN

Fig. 40 OUTPUT CURVE - MOSFET (N CHANNEL DEPLETION)

28 -

The voltage between the gate and the source (VGs) controls the electron concentration in the channel. If the drain (D) is made positive to the Source (S) and VGS is zero a current will flow. If VGS is made negative, positive holes are attracted into the channel so reducing the number of free electrons in the channel and therefore channel current decreases. This is known as the DEPLETION MODE. IfVGS is positive, electrons are attracted into the channel from the P substrate increasing current flow - this is known as the ENHANCEMENT MODE. If a P-channel FET (figure 41) was used in the enhancement mode, the conduction is by holes.

OXIDE

o

G~

s

s

Fig. 41 MOSFET & SYMBOL (N CHANNEL ENHANCEMENT)

The MOSFET has a higher input impedance than the JUGFET > 1 Xl0120, however its output impedance is similar to that of a bi-polar transistor 10 to 50kn. When used as a switch its switching time is very fast.

Fig. 42 OUTPUT CURVE~ MOSFET (N CHANNEL ENHANCEMENT)

MOSFET structure is very compact and is widely used in integrated circuits. Great care has to be taken to protect MOSFETS from electrostatic charges, which could break down the insulated oxide layer. They are supplied with a metal clip short circuiting the leads, which should be left in place until connected in the circuit.

- 29 -

CMOS (Complementary Metal Oxide Semiconductor)

This is one of the most important families of logic gates which uses a

P-channel and an N-channel MOSFET to create all the relevant logic gates. An example of an invertor gate is shown in figure 43. The great advantage of CMOS is that in both the HIGH and LOW states the current consumption is very small (1 x 10-9A). Power consumption is therefore low and the fan out is high (typically 50). The speed of operation is poorer than TTL.

...------0 voo - IOV

T:;z

(p-ch ... u"ol)

T,

(D-ch ....... 11

Fig. 43 CMOS INVERTOR GATE

FEEDBACK IN AMPLIFIERS

-

Feedback is the return of a portion of the output signal of an amplifier back into the input signal of the same system. There are many variations on this but the following deals with the broader principles.

Signal In

Signal Out.

Prc-pc-rtiC-"t'-l rco:co:dbo.C:"

Fig. 44 FEEDBACK AMPLIFIER

- 30 -

There are generally two types of feedback - which, incidentally, occurs in all forms of control systems whether mechanical, electrical, electronic etc, these are Positive Feedback and Negative feedback.

Positive Feedback

When the returned portion of the output signal assists the input signal, it is called Positive Feedback. This causes an increase in the overall gain. It can be many times larger than the gain without feedback, but can also lead to instability and oscillation.

The Gain of an amplifier with Positive feedback is given by:

Af= A

1 - fJA

Where

Af = Gain with feedback

A = Gain without feedback

fJ = Feedback fraction = Feedback Output

It can be seen that, if fJA equals unity, the gain is infinite and oscillation occurs.

Negative Feedback

When the returned portion of the output signal opposes or tries to cancel the input signal, it is called Negative Feedback. This is the most common form of feedback (in all control systems), having several advantages and uses.

The Gain of an amplifier with Negative feedback is given by:

Af = A which gives a reduction in overall gain.

1 + (JA

Negative Feedback is used to:

a) Improve the stability of the gain. It is less affected by changes in transistor parameters and temperature changes.

b) Effectively change the input and output impedances.

c) Reduce 'noise' and distortion.

d) Increase bandwidth. (see below)

- 3 1 -

VOLTAGE Go.in Without

GAIN F'~~dbo.c:1<.

Max ". ..

M a x .. ·.... ...:;.::. ... ;.1106 ........ ~~ ........ - ......... ""!--..,:: 0.707 ..

0.707

1 Without . r F' 'Bo.c:1<. ~

(BANDWIDTH)

+- Vi i t h F' e ~ d b 0. c: I<. .-+i

Hz

Fig. 45 FREQUENCY RESPONSE CURVE

Frequency Response and Bandwidth

The GAIN of an electronic amplifier is determined by such things as the type of amplifying device being used and by its associated circuit components. Any particular circuit arrangement will provide maximum gain at a single frequency (or over a narrow band of frequencies) and less gain at all other frequencies. Since many amplifiers are required to provide amplification over a wide range of frequencies it is common practice to provide each amplifier with a graph showing how its gain varies with frequency. This is known as the amplifier's Frequency Response Curve. Figure 45 shows an example.

--

The Effects of Negative Feedback on Bandwidth

An amplifier's Gain is generally considered to be adequate as long as it is equal to, or greater than, half the Maximum Power Gain.

(OR)

An amplifier's Gain is generally considered to be adequate as long as it is equal to, or greater than, 0.707 of the Maximum Voltage Gain

The range of frequencies over which this requirement is satisfied is known as the amplifier's BANDWIDTH.

- 32 -

As stated above, negative feedback has the effect of reducing the gain of an amplifier but it also has the very valuable effect of increasing its bandwidth. Figure 45 shows graphs of an amplifier's gain and associated bandwidth, both with and without negative feedback.

OSCILLATORS

With reference to figure 46 assume the capacitor is charged from an external supply.

When the switch is closed the capacitor will discharge, thus changing magnetic field causes an induced voltage into the coil, the back emf opposes this discharge and this therefore takes some time. Eventually the capacitor discharges and its electrical energy has been transferred to the coil. At this time the magnetic field begins to collapse, current now flows to charge up the capacitor, lower plate +ve.

Once charged the capacitor discharges in the opposite sense creating a magnetic field of opposite polarity.

c

L

Fig. 46 SIMPLE OSCILLATOR CIRCUIT

This oscillation would continue indefinitely if the circuit had no resistance, but the coil has resistance, so the oscillations gradually decrease. To maintain the oscillation some energy must be continuously fed into the LC circuit. Most oscillators are amplifiers with positive feedback which means the feedback is in phase with the input and makes good the energy losses in the oscillatory circuit.

Radio Frequency Oscillators

With reference to figure 47, the basic operation of this circuit is_as follows.

- 33 -

Switching on the power supply charges up the capacitor and starts the oscillations. Feedback is obtained by the changing magnetic field in Ll inducing an emf into L2. Thus emf is applied between the base and emitter, which causes more collector current and therefore more current in Ll, this continues until oscillation is maintained.

r---------- ...... ---------o +Va;

c~

Fig. 47 OSCILLATOR CIRCUIT

The feedback from L2 being enough to draw de from the supply to make good the energy losses and keep the oscillation gomg. So the oscillator converts de to ac.

For very high frequency stability crystal oscillators are used in the range 1 to 10 MHz.

Audio frequency oscillators using resistors and capacitors are used up to 50 MHz.

You have already seen the commonest square wave type oscillator, that is the Astable Multivibrator.

--

THE TRANSISTOR AS A SWITCH

-

The transistor has no moving parts and can switch at very high speeds.

In switching applications the transistor is treated as a two state device, ie the transistor is either fully conducting or cut-off.

In figure 48, when the input voltage reverse biases the base-emitter junction and the transistor is cut-off and acts as an open switch. If the input voltage switches to a large forward bias the transistor will conduct and act as a closed switch.

O/P =

O/P

:·R·;/O-p-+I

O/P

=

,._---+ O/P

Fig. 48 THE TRANSISTOR AS A SWITCH

;t~: Fast switching is desirable and N-P-N types are preferred because their majority carriers, which are electrons, travel faster than the majority carriers (holes) in PN-P types.

MOSFETS can be used as switches, their switching speed being about ten times faster than a transistor.

INTEGRATED CIRCUITS

An integrated circuit (IC) is a complete electronic circuit on a chip of silicon about 5mm square and O. 5mm thick.

Figure 49 shows a typical IC cutaway so you can see the silicon chip and the

leads radiating from it to the pins. The diagram shows a dual in-line package, but circular packages are available.

l'Cs are assembled this way to allow their fitment to PCBs (Printed Circuit Boards) etc. Otherwise they would be too small for handling and connection purposes.

- 35 -

CHIP (oo 5 X 5 X l rnrn]

CONNECTORS (from chip to pins)

NOTCH

..!!y- PINS (for connection to PCB or connector block) (spacing .. 2.5mm)

DOT

Fig. 49 IC PACKAGE

SILICON WAFER about IOcm diameter containing hundreds of Integrated Circuits (IC s]

Fig. 50 SILICON WAF'ER

Silicon is the base material used, as it has a high degree of purity and a continuous regular monocrystalline structure. A silicon wafer (about I Ocm in diameter) is produced onto which hundreds of Ie's can be formed. Figure 51 shows how areas of silicon oxide deposited on the silicon are selectively removed. It is basically a photographic process where areas of the ("lip are masked and then the surface is subject to uv light. The unmasked areas are 'eaten' away using a solvent leaving those areas that are required. Finally the unmasked silicon oxide

area is removed by etching.

blank

36 -

SILICON OXIDE

II 111111111111111111111"11'1'1 (a) SILICON SLICE

[ SILICON SLICE WITH OXIDE SURFACE

PHOTO RESIST _, ........•••..•..•.••••••••.•• 1

f 111111111111111111 r r II r rill r I (b) :~~~~~~~I~~;:~~D TO

MASK + + + + + + + +

E· .... mrrrr; (01 PHOTO RES'ST MASKED AND

r r I r r EXPOSED TO UV LIGHT

EXPOSED AREA OF

PHOTO RESIST

, 1 t 'I d) "ASK E"O 0 E

r I 1II11I11 (11111 ! ILL L I [ L rIll ( ';EA;F ;H~;g ~~I~~E~~ED

BY A SOLVENT

11111 ! 11111I 11111111 I. III (f) FINAlLY THE REMAINING PHOTO

RESIST IS REMOVED LEAVING A 'WINDOW IN THE OXIDE LAYER

L- ~

Fig. 51 IC PRODUCTION - 1

Figure 52 shows how a transistor is made using the diffusion process, ie exposing the wafer at high temperature to the vapour of boron or phosphorus so their atoms diffuse through the window producing a 'P' or 'N' type area.

/SILICON IfTT"rrTTTrrrTTT"TTrrTTTTTT1rTTTrr/T11 0 XIDE

1111111111111111111111111111111111 (a) OXIDIZED

N TYPE SILICON N

r i (b) BASE WINDOW MADE BY PHOTO N RESIST PROCESS

~------~------~

(f) BASE AND EMITTER CONTACT WINDOWS OPENED IN THE OXIDE FILM

e~~"~ ~ (h)~~~~~~~UAl

<; -'- --' SEPARATED AND

_.._ -:.:. ._ MOUNTED

Fig. 52 IC PRODUCTION - 2

- 37 -

Monolithic integrated circuits are manufactured by an extension of the planar diffusion process. The active elements (transistors), and the passive elements (diodes, resistors and capacitors) are all created by modifying the conductive properties of the silicon.

n

. ;

Integrated diodes are made by forming a P-N junction similar to that previously described. Integrated resistors are thin layers, the resistance being defined by the length and width of the layer. Integrated capacitors are made by using the capacitance of reverse biased P-N junctions.

There are two broad types of IC

1. Linear (analogue)

2. Digital (logic)

Linear Circuits

Most linear IC's are based on bi-polar transistors but in some cases FET's are used exclusively or in addition to bi-polar types. The majority of today's linear integrated circuits use operational amplifiers (op-amps).

OPERATIONAL AMPLIFIERS

II, typical op-amp contains twenty transistors as well as resistors and small capacitors.

The chief properties of op-amps are:

1. Very high open loop gain

2. High input impedance (1 x 106 to 1 X 10120)

3. Low output impedance (typically 10000)

blank

- 38 -

Fig. 53 CIRCUIT - OPERATIONAL AMPLIFIER

Fig. 54 SYMBOL

With reference to figure 55, the basic op-amp has one output and two inputs. The NON-INVERTING (NI) input is marked + and the INVERTING (I) input is marked -. In the diagram point E is the common reference for the input and output volts. The de power supply is typically _:!:5V to _:!: 15V with OV being the reference level.

With the N 1 input grounded (chassis potential), an input at I, causes a voltage or opposite polarity to appear at the output.

- 39 -

...
Power
Supply
I
.-
i E
Load
...
Vin Power
I Supply

f-"' .

Fig. 55 BASIC OP-AMP CIRCUIT

NOT OUTPUT OFFSET
USED, +Vs I NULL
./
NOTCH 5
IN CASE TL081C
SMALL DOT
./ + -Vs
OFFSET INPUTS
NULL
Fig. 56 SYMBOL With the I input grounded and an input at Nl, causes a voltage of the same polarity to appear at the output.

When signals are applied to both input terminals the output is the difference tctv.'cen to the two inputs, ie two identical signals will produce zero output. The op-arnp is basically a differential amplifier.

Inverting Input I--~

NI +

Non-inverting Input

Power Supply Positive

>----- Output

Power Supply Negative

Fig. 57 OP-AMP SYMBOL

Although the power supplies positive and negative are shown in the basic op-amp symbol they are usually omitted on wiring diagrams.

Most op-amps use negative feedback, ie feeding some of the output back to the inverting input. The coupling between the stages is direct coupling. In practice even when de bias conditions are met and no input signal is applied, there may be a small voltage at the input, called the differential input offset voltage. It may be caused by different manufacturing tolerances of the components of the op-amp. This offset voltage produces a voltage at the output (with no input signal remember) and in certain applications is undesirable. For the 741 op-amp this is achieved by placing a variable resistor across the offset null pins (1 and 5) and adjusting it until the output is zero when the input is zero.

In ac operation a coupling capacitor at the output removes any dc component caused by the offset voltage. Slew rate is the maximum rate of change of large amplitude output voltages that an op-amp can allow before it behaves nonlinearly, it is measured in volts per micro-second (V /Jls).

As previously stated the op-amp is basically a differential amplifier so it is useful to look at its operation.

/

Vin, Vin,

Fig. 58 DIFFERENTIAL AMPLIFIER

The circuit shown produces an output which is proportional to the difference between the two inputs. If Rs = RF then Vout is equal to the difference in input voltages. If RF and Rs have different values then the circuit gain (A-6)= RF/Rs.

In general the output is

V 0 = Ao (V 2 - V i]

- .:+ 1 -

-_...-

Op-arnp as an Inverting Amplifier

With reference to figure 59, the input voltage VI is applied to the inverting terminal via resistor RI. The non-inverting input is grounded. Feedback is applied from the inverting input via R2 which because of the inversion of the amplifier acts as negative feedback. Output is of opposite polarity to input.

/. ,

Fig. 59 OP-AMP INVERTING AMPLIFIER

RZ

Vo Load

. ,

Fig. 60 OP-AMP NON INVERTING AMPLIFIER

Op-amp as a Non-inverting Amplifier

-.

Figure 60 shows a non-inverting op-amp. The input voltage is applied to the noninverting input (+) with the inverting input grounded. The feedback resistor is still-connected to the inverting input to obtain negative feedback. Output is the same

polarity as the input.

Op-amp as a Simple Voltage Comparator

With reference to figure 61 the op-amp compares VI to Vref. When VI is slightly greater than Vref the op-ampsaturates in one direction and when Vref is greater than V I it saturates in the other direction. It is therefore behaving as a two-state digital device with Vo switching from high to low, ie comparing voltages. When fed with an ac input the op-amp in its saturated condition is converting a continuously varying analogue signal into a two-state digital one, ie converting a

sine wave into a square wave.

. 42 -

Fig. 61 SIMPLE COMPARATOR

Fig. 62 OP-AMP INTEGRATOR

Op-amp as an Integrator

The circuit shown (figure 62) is similar to an inverting amplifier but feedback is via a capacitor. It therefore inverts, amplifies the input signal over a period of time determined by the values of Ri and Cr.

Op-amp as a Differentiaior (Figure 63)

This circuit responds only to changes of input Vi. It is only during these input changes that current flows through Ci and Rr. The output is the inversion of the

input rate of change.

.'~

Fig. 63 DIFFERENTIATING OP-AMP

- 43 -

Op-amp as a Voltage Follower (Figure 64)

This is a special case of the non-inverting amplifier in which 100% negative feedback is applied by connecting the output directly back to the inverting terminal. This effectively gives a situation where the output voltage follows the input and almost exactly equals it. It has an extremely high input impedance and a low output impedance and its main application is for impedance matching, ie to act as a buffer amplifier.

Fig. 64 VOLTAGE FOLLOWING OP-AMP

Op-amp as a Summing Amplifier (Figure 65)

The output voltage Vo is equal to the inverted sum of the inputs

, ...

Fig. 65 SUMMING OP-AMP

Other uses of Op-amps

Linear IC's are used in audio amplifiers, radio frequency amplifiers and video amplifiers. but are of specialised types and require a small number of external components. Figure 66 shows a radio frequency amplifier .

.. 44 -

100~.n.

L 1

.. 1.SV

>-+---i OUTPUT r'

OV

Fig. 66 RADIO FREQUENCY AMPLIFIER

LOGIC CIRCUITS

There are two main types of logic circuit:

a) TIL (Transistor Transistor Logic)

b) CMOS (Complimentary Metal Oxide Semiconductor)

The following shows the scales of integration which refer to the number of gates contained in a single package:

* Small scale integration (SSI) - containing not more than 11 gates

* Medium scale integration (MSI) - containing up to 100 gates

* Large scale integration (LSI) - containing between 100 - 1000 gates

* Very large scale integration (VLSI) - containing over 1000 gates

The following diagrams show some TIL and CMOS gates.

Fig. 67 TTL 'AND' GATE

45 -

F

+5V

+

5V

F

Fig. 68 TTL 'NAND' GATE

Figure 68 shows a two input NAND gate which uses a multiple emitter N-P-N transistor. If both inputs to Tl are high, then no current flows from the base to the emitter. Current does flow through the base collector circuit to switch on T2. The output F is near zero volts. If either input A or B go low then Tl conducts, this causes current flow from collector of T2 (positive charges) through Tl to ground which switches T2 off and the output goes high.

D1 D2 Js + 5V
A
T2 ~
B
T3
D 3~
I F
Tl ~ T41
ys
I
Fig. 69 CMOS 'NOR' GATE
-_./
;;P->5V
Tli ~
A t-
T2
0 0
F'
B t-D
T3 ~
T4 )

1..
Fig. 70 CMOS 'NAND' GATE - 46 -

Properties of TTL and CMOS

TTL uses bi-polar transistors along with diodes and transistors formed to microscopic dimensions on a slice of silicon (chip). TTL must have a steady 5V de supply, while CMOS will work on de voltages between 3 and 15V and usually requires much less power. CMOS uses uni-polar Field Effect Transistors (FET) with metal-oxide-silicon technology; this lends itself to VLSI as they take up less room on a chip, compared to the TTL. CMOS has a much higher input impedance.

One important point with CMOS is that if static electric charges are allowed to build up on it's input pins, these voltages can break down the thin layer of silicon oxide insulation between the gate and the other electrodes of MOSFET's and this will destroy the l C. So anti-static protection is important.

Gate operating parameters include:

a) b) c) d) e)

Speed of operation Fan in

Fan out

Noise margin Power dissipation

Speed of operation - the time that elapses between the application of a signal to an input terminal and the resulting change in the logical state at the output terminals.

Fan in - number of inputs coming from similar circuits that can be connected to the gate without adversely affecting its performance.

Fan out - the maximum number of similar circuits that can be connected to it's output terminals without the output falling outside the limits at which logic levels 1 and 0 are specified.

Noise margin - this is maximum noise voltage (unwanted voltage) that can appear at it's input terminals without producing a change in output state.

Power dissipation - as in any circuit, supply voltage multiplied by the current (Power = V x I) gives the power in the circuit and this heat must be dissipated.

Typical figures for TTL and CMOS are shown below.

Speed of Fan Fan Noise Power
Operation in out margin dissipation
Standard TTL 9nS 8 10 O.4v 40mW
CMOS 30nS 8 50 1.5v O.OOlmW - 47 -

If you look back at the diagrams for the TIL AND gate and the TIL NAND gate you (",

will see that the NAND gate uses fewer components and is therefore

cheaper to produce.

This also applies to the NOR gate, ie it is cheaper to produce than the OR gate.

NAND gates can be connected together to form any of the other basic gates - thus reducing production costs by manufacturing one gate only. The following drawings show how these gates can be formed.

NOT GATES (INVERTING)

AND GATES

'_-

NOR GATE

NAND GATE

Fig. 71 USE OF NAND GATES

Figure 72 shows the pin connections of l C's for different gate configurations. There is no need to remember them but it does give a good idea of how the chip (with the gates in) is connected - although the chip itself is so small that it looks

like a piece of silver metal 4 or 5mm square.

TTL NOR GATE

CMOS NOR GATE

TTL AND GATE

CMOS AND GATE

Fig. 72 IC PIN CONNECTIONS

- 49 -

IC's are made which also perform the function of encoding, decoding, performing binary addition (adders) and multiplexers.

In sequential logic circuits flip-flops are extensively used all of which are manufactured on JC's.

The SR Flip-Flop

The SR flip-flop has two output terminals Q and Q. Figure 73 shows the SR flipflop using NAND gates.

Q

-

Q

Fig. 73 THE SR FLIP-FLOP

With reference to figure 73.

When S = 1 R = 0 Q = 1 Q = 0 the flip-flop is SET

When S = 0 R = 1 Q = 0 Q = 1 the flip-flop is RESET

When S = 0 R = 0 then no change occurs Q and Q will be what they were before.

When S = 1 and R = 1 then Q = 1 and Q equals 1. The circuit is stable while S = R = 1, but if they are changed simultaneously from 1 to 0 then due to ~ifferent

switching times of the gates we cannot predict whether Q or Q will be 1. --

The output state is said to be indeterminate so S =, R = 1 should not be allowed to occur. The truth table is shown below.

S R Q Q
1 0 1 0
0 1 0 1
0 0 Depends on state before inputs applied
1 1 Indeterminate - so -

So basically the flip-flop can exist in two stable states:

Q=l(Q=O) or Q=O(Q=l)

Clocks

In sequential logic circuits where there may be a large number of flip-flops, it is important they all act at the same time, so no circuit operates out of sequence.

This is achieved by a CLOCK pulse from a high frequency pulse generator. The circuits may be triggered when the clock pulse changes from 1 to 0 or when it changes from 0 to 1 (edge triggered) or when the level is 1 or O. Figures 74 and 75 shows a clocked SR flip-flop and it's truth table .

............. _ _._._- -_ _ .. -_ .......• - -_. __ •............ _ \

s

n

a

CK (CLOCK)

:n

Q

QAAWlNG SYMBOl

R

i ;

~-------.-- .. --- .. --.- .. --- - --.---.- ..

Fig. 74 CLOCKED SR FLIP-FLOP

OUTPUTS OUTPUTS
DURING BEFORE AFTER
INPUTS CLOCK CLOCK CLOCK COMMENTS
PULSE PULSE PULSE
S 1 R A B Q Q Q Q
0 0 1 1 1 0 1 0 NO CHANGE
0 0 1 1 0 1 0 1 IN
OUTPUTS
1 I 0 I 0 1 1 0 1 0 FLIP-FLOP SETS
1 0 0 1 0 1 1 0 WITH
Q=l&Q=O
0 1 1 1 0 1 0 0 1 FLIP-FLOP
0 I 1 1 0 0 1 0 1 RESETS WITH
Q=O&Q=l
-_-_-
1 I 1 ) 0 0 1 0 1 1 THIS INPUT
I
1 i 1 -; 0 0 0 1 1 1 IS
! , 1 NOT ALLOWED Fig. 75 TRUTH TABLE - CLOCKED SR FLIP-FLOP

- 51 -

D Type SR Flip-flop

This is a modified SR flip-flop. The D stands for Delay. If you look at the truth table, when the clock pulse changes (rises), whatever is at D is transferred to Q, when clock pulse falls Q stays at that level. NO MATIER WHAT IS APPLIED TO D, Q will only change state at the next clock pulse. The truth table shows that the output equals the input one clock pulse earlier, ie the data is held back until the clock pulse = 1.

o

ft -b__J_

DRAWING SYMBOl

. .

······· __ ··············1···_············_···_···_· __ ·· _._ - _,

1

o _fl_ CK (CLOCK)

Fig. 76 CLOCKED D TYPE FLIP-FLOP

,-----r-.--.- ... ,--- -- OUTPUTS _ .... -v-r-r-r- I
~I I OUTPUTS
BEFORE AFTER
CLOCK PULSE CLOCK PULSE
I----
IDS R I Q Q_- Q Q
._-j---. t-
O I 0 1 1 0 0 1
0 0 1 0 1 0 1
1 1 0 1 0 1 0
1 1 0 0 1 1 0 Fig. 77 TRUTH TABLE CLOCKED D TYPE FLIP-FLOP

JK Flip-flop

Figures 78 and 79 show the layout and truth table of the JK flip-flop using NAND gates.

- 5.:2 -

CK (CLOCK)

~_n_

Q

IT H

l _._. .. __ .. ._ .. _ _._. __ _._. __ _:

Fig. 78 JK FLIP-FLOP

OUTPUTS DURING OUTOUTS
INPUTS BEFORE CLOCK AFTER CLOCK
CLOCK PULSE PULSE PULSE COMMENTS
J K Q Q A B Q Q
0 0 1 0 1 1 1 0 NO CHANGE IN
0 0 0 1 1 1 0 1 OUTPUTS
1 0 1 0 1 1 1 0 STAYS AT OR
1 0 0 1 0 1 1 0 SETS TO
Q=l&l=l
0 1 1 0 1 0 0 1 STAYS AT OR
0 1 0 1 1 1 0 1 RESETS TO
_0 = 0 &Q = 1
1 1 1 0 1 0 0 1
1 1 0 1 0 1 1 0 TOGGLES Fig. 79 TRUTH TABLE JK FLIP-FLOP

The two inputs are called J and K and the operation is described in the truth table. J = K = 1 is allowed (unlike S = R = 1 in a SR flip-flop) and toggles (changes state) when this input is applied.

Shift Registers, which store a binary number and shifts it out when required usually consist of a number of flip-flops and manufactured in IC's as are counters and memories.

The Astable, Monostable and Bistable multivibrators are also manufactured on IC's using op-amps as the diagrams below.

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Fig. 80 ASTABLE MULTIVIBRATOR

T rlQQ ~Lr";"""---'"""----i Input..

C1

Fig. 81 MONOSTABLE MULTIVIBRATOR

>" ,

Fig. 82 BISTABLE MULTIVIBRATOR

PRINTED CIRCUIT BOARDS (PCBs)

In this technique metallic foil is bonded onto a base board made from insulating material, and a pattern is printed onto the foil and chemical etching on to the foil forms a series of current conducting paths. The components are then mounted to the board and soldered to the appropriate points to make-up the circuit required. The boards are usually made-up of layers of phenolic resin impregnated paper, or epoxy resin impregnated glass-fibre cloth.

The thickness of the boards depends in the strength and stiffness required. The boards are manufactured in three basic configurations:

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1) Single layer

2) Multilayer

3) Multilayer sandwich

These boards contain all printed conducting paths on one side with the components mounted on the opposite side.

These have printed conducting paths on both sides and the components may also be mounted on both sides.

These boards are many thin boards laminated together with the components mounted on one or both external sides.

The most commonly used conducting material is copper foil. To bond the copper to the board, copper foil sheets are cut to the size of the board and steel separate plates are interposed between the layers as shown in figure 83.

SINGLE CLAD

==:0 STAINLESS STEEL PlATE --- COPPER FOil

f<88X88)§l8)I BASE METAl.

BONDING OF CONDUCTOR MATERIAl.

SINGLE CLAD

Fig. 83 MAKE UP OF PCBs

The layered sheets are bonded in a hot press. The heat during the pressing operation melts the resin in the base material so that it flows and fully wets the material and the copper foil. As polymerisation of the resin mix proceeds, each layer of base material reaches the fully cured state with the copper foil is bonded to it. When cooled each board is trimmed to the required size, inspected and packed in polythene bags.

Next a master diagram must be produced to show clearly the conductor pattem-fa sort of wiring pattern) required and where the components are to be located. This is usually done by computer aided design techniques.

- ::J::J -

The printing process may be by the etching or additive process. In the etching process the copper foil is cleaned and coated with a photo-sensitive solution known as a 'resist', this solution has the property of becoming soluble when exposed to strong light. The master diagram is then placed over the board and exposed for a time in a printing machine. The resist is washed away to leave the resist etched away around the circuit pattern. The board is then placed in a bath of ferric chloride to etch away all the unprotected copper.

PRINTED CIRCUIT

BASE MIITERIAl

Fig. 84 ETCHING PROCESS

An alternative process is the additive method. In this process the copper is deposited only in the areas where conductors are required. Again the board is coated with a photo resist solution. A negative of the master diagram is then screen printed onto the board, exposing the areas for the conductor layout These exposed areas are chemically activated and the whole board is immersed in a copper plating solution, when the required thickness is obtained the board is withdrawn from the solution.

PHOTO SENSITIVE COATiNG (RESIS T) apploed

PRINTED CIRCUIT

BASE MATERIAl.

Resist washed away 'rom areas

• "POSed 10 IIghl ""ar prinllng process. (In thiS case the neQiltl¥e 0' the one described above)

Fig. 85 ADDITIVE PROCESS

--The components are soldered to the board by two main methods (a) by hand, (b) mass soldering.

S6 -

In mass soldering all joints are soldered simultaneously by bringing the board into contact with an oxide free surface of molten solder, which is contained in a special bath. The solder specification for mass soldering is 60/40 tin/lead. To prevent oxidation a flux is used and in the automated mass soldering system a fluxer unit is incorporated, removal of any flux residue is by solvents.

CIRCUIT MODULE DESIGNATION (eg SIGNAl SELECTOR)

PRINTED CIRCUIT

-¥l 4,

--

COMPONENT SOLDER LOCATIONS

BASE MATERIAL FINGER OR EDGE CONNECTOR

FRONT REAR

Fig. 86 TYPICAL DOUBLE SIDED PCB

IC PACKAGE

Fig. 87 BOARD COMPONENTS

Flexible printed wiring circuits are available and usually serve as a means of interconnecting units and are basically copper foil conductors bonded to a base of thin flexible insulator (polyester, epoxy glass cloth and polyimide) and covered with the same material.

Printed circuit boards are widely used in components on a modern large transport aircraft. When removing or replacing these boards strict precautions must be observed.

~ J I ~

The reason for this is that the static electricity or charge that we have in our body can cause serious damage to the software of the components on the boards. The table shows ty-pical electrostatic voltages that may be developed.

! ELECTROSTATIC VOLTAGES
MEANS OF STATIC GENERATION RELATIVE HUMIDITY (%)
10 TO 20 65 TO 90
WALKING ON CARPET 35,000 1,500
WALKING ON VINYL FLOOR 12,000 250
WORKING AT BENCH 6,000 100
VINYL (PLASTIC) DOCUMENT ENVELOPES 7,000 600
'POLY BAG' PICKED UP FROM BENCH I 20,000 1,200
I CHAIR PADDED WITH POLYURETHANE 18,000 1,500
I FOAM ! Fig. 88 TABLE OF TYPICAL ELECTROSTATIC CHARGES

If we were to touch the edge connectors or some other exposed metal part then a surge of current due to the difference in potential between our body and the PCB would cause damage to the components. The following table lists static

sensitive devices and voltages that can cause damage. These devices are often referred to as ESD's (electrostatic sensitive devices).

I TYPE OF DEVICE RANGE WHERE DAMAGE J
- CAN OCCUR (V)
i MOS FET 150 TO 1,000
[ CMOS 250 TO 1,000
l BIPOLAR TRANSISTOR 4,000 TO 15,000
I SILICON CONTROLLED RECTIFIER (SCR) 4,000 TO 15,000 I
THIN FILM RESISTORS 150 TO 1,000
! Fig. 89 TABLE OF VOLTAGE SENSITIVITY

To identify components fitted with ESO's a symbol is used on the line replacement unit (LRU) and associated documentation, transport bags etc.

To overcome the static discharge problem the person removing the PCB must use a conducting wrist strap which is connected to a convenient grounding point on the aircraft and the person, to initially discharge any energy WIthin the body.

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COMMERCIAL

GOIIERNMENT

BOEING

TYPICAL SYMBOLS

CAUTION

0111 IV, 'l'tAU' 10111 '01 MAO'~11IIi E~ECTROSUTlC SENSITIvE DEvICES

/\ THIS ASSE .... ~T

~ CONTAINS

[\~ ELECTROSTATIC SEHSI TIVE DEviCES

(" n.llc J .\oj HOS !TIY

C Imlt )

![OUTIV'

Fig. 90 ESD DECALS AND WARNINGS

When removing an ESD PCB (or any PCB for that matter) electrical power is removed, the wrist strap is connected to the ground (there is usually a convenient point nearby on the aircraft), attach strap to your wrist and remove the PCB using the extractors provided. Place the PCB immediately into a special conductive bag (designed for ESD components) and identify with a label, do NOT use staples or adhesive tape. Remove wrist strap if not immediately refitting a new PCB. Do not forget any documentation such as JAA form 1 etc.

If you are removing the complete LRU then it is important you do not touch the connector pins and place dust caps on all connectors.

REMEMBER STATIC DISCHARGE CAN CAUSE DAMAGE!

"'''''' "

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