(IJCSIS) International Journal of Computer Science and Information Security, Vol. 8, No.

9, December 2010

A Survey on Static Power Optimization in VLSI
A. Janaki Rani and Dr. S. Malarkkan
Abstract---Power has become one of the primary constraints for both the high performance and portable system design. The growing market of battery powered electronic systems like cellular phones, personal digital assistants demands the design of microelectronic circuits with low power consumption. Power dissipation in these systems may be divided into two major components namely static and dynamic power dissipation. The static power is the standby power that is wasted even if the device is not performing any function. As technology scales down the static power dissipation is dominant in VLSI circuits which are mainly due to leakage current in transistors. Hence a focus is necessary on the leakage currents. These leakage currents are mainly due to sub-threshold leakage and gate oxide leakage. The sub-threshold leakage is dominant which can be minimized by reducing the supply voltage, reducing the transistor size, decreasing the temperature and increasing the threshold voltage. In this paper a survey is presented on static power optimization in VLSI. It presents the possible solutions to reduce the leakage power in various digital logic circuits like CMOS, I2C etc. Index Terms—Leakage, Low-Power, Power Gating, Semicustom, Input Vector Control, Body Bias Control, Sleep Transistor Sizing, Sleepy Stack, Zigzag Power Gating (ZPG) I. INTRODUCTION

The power dissipation can be minimized only if the source of power dissipation is analyzed. Power dissipation in digital CMOS circuits is caused due to sources as follows. (a) The leakage current, which is primarily found by the fabrication technology, consists of four components namely sub-threshold leakage current (Isub), gate direct tunneling current (Ig), gateinduced drain leakage current IGIDL) and reverse-biased junction leakage current (Irev) , (b) the standby current which is the DC current drawn continuously from Vdd to ground, (c) the short-circuit (rush-through) current which is due to the DC path between the supply rails during output transitions, (d) the capacitance current which flows to charge and discharge capacitive loads during logic changes. The term static power dissipation describes the sum of leakage and standby dissipations. The static power dissipation is dominated by the leakage components and is given by Pstatic = Ileak * Vdd ------------------------------------ (1) The sub-threshold leakage current and gate direct tunneling current are dominant in the sub-100nm CMOS circuits. The sub-threshold leakage current is given by Isubth=I0 exp[(Vgs-Vt) / (n VT) ] [1- exp (-Vds/VT)] — And I0=μeff Cox (W/L)VT2 -----------------(2) (3)

I

N the past, the major concerns of the VLSI designer were area, performance, cost and reliability; power considerations were mostly of only secondary importance. In recent years, however, this has begun to change and, increasingly, power is being given comparable weight to area and speed. Several factors have contributed to this trend. Portable computing and communication devices demand highspeed computation and complex functionality with low power consumption. Heat production in high-end computer products limits the feasible packing and performance of VLSI circuits and increases the packaging and cooling costs. Circuit and device reliability deteriorate with increased heat dissipation, and thus the die temperature. Heat pumped into the rooms, the electricity consumed and the office noise diminishes with low power LSI chipset. Leakage-power problems are a serious issue in portable electronic systems that operate mostly in standby mode. Lowering power-supply voltage in the system is one of the most effective schemes to reduce the power dissipation. As the VLSI technology and threshold/supply voltage continue scaling down, leakage power has become more and more significant in the power dissipation of today’s CMOS circuits. For example, it is projected that subthreshold leakage power can contribute as much as 42% of the total power in the 90nm process generation [1].

Where μeff is the electron/hole mobility, Cox is the gate capacitance per unit area, W and L are width and length of the channel respectively, Vt is the threshold voltage, n is the subthreshold swing co-efficient, VT is the thermal voltage, Vgs is the transistor gate to source voltage and Vds is the drain to source voltage. The sources of static power dissipation is summarized above and the following section of this paper presents the literature survey on the different techniques for reducing leakage current which are power supply gating, dual threshold voltage, input vector control, body bias control, sleepy stack, forced stacking and use of MTCMOS, VTCMOS and guarding. II. LITERATURE SURVEY

A. Janaki Rani, Research Scholar Sathyabama University, Chennai, India. Dr. S. Malarkkan, Principal, Manakulavinayagar Institute of Technology, Pondicherry, India.

Mutoh et al, [3] presented the concept of Multi Threshold CMOS (MTCMOS). In this technique, a high-threshold voltage transistor is inserted in series with the power supply and the existing design and ground as shown in Figure 1. During active mode of operation, the high threshold Vt transistors are turned on, thereby facilitating normal operation of the circuit as there exists a direct path from the output to
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(IJCSIS) International Journal of Computer Science and Information Security, Vol. 8, No. 9, December 2010

ground and Vdd. During standby mode, these transistors are turned off creating a virtual power supply and ground rail and cutting off the circuit from supply. The high Vt transistors are called sleep transistors.

Fig.1 MTCMOS Circuit

Fig.3 Sleepy stack inverter circuit

Narendra et al, [4] showed that stacking of two off transistors significantly reduces sub-threshold leakage compared to a single off transistor. It is an effective way to reduce leakage power in active mode. Transistor stacking technique uses the dependence of Isub on the source terminal voltage Vs. With the increase of Vs of the transistor, the subthreshold leakage current reduces exponentially. If natural stacking of transistors does not exist in a circuit, then to utilize the stacking effect a single transistor of width W is replaced by two transistors each of width W/2. This is called forced stacking as shown in Figure 2.

Preetham Lakshmikanthan et al, [6] presented a selfcontrolling leakage reduction technique called VCLEARIT for CMOS circuits. Signal probabilities determine the mode of operation (active or standby) of the gates making up complex circuits. Cancellation of leakage effects in both the pull up network (PUN) as well as the pull down network for CMOS gates results in leakage reduction. A combination of high Vt and standard Vt control transistors achieve voltage balancing in the pull up and pull down paths. Results show up to 61% reduction in leakage power of combinational circuits.

Fig. 2 Forced stacking circuit Fig. 4 VCLEARIT Circuit

J.C. Park et al, [5] described a sleepy stack technique which combines the sleep transistor approach during active mode and the stack approach during standby mode. In this technique, forced stacking is first implemented. Then to one of the stacked transistors a sleep transistor is inserted in parallel. Thus during active mode, the sleep transistors are on thereby reducing the effective resistance of the path. This leads to reduced propagation delay during active mode as compared to the forced stacking method. During standby mode, the sleep transistor is turned off and the stacked transistor suppresses the leakage power. Figure 3 shows the circuit of a sleepy stack inverter, where the S and S’ are sleep control signals.
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Yu et al, [7] proposed a power optimization technique on reduced leakage power with thermal awareness using dual threshold voltage. Dual- Vth design is an effective leakage power reduction technique at behavioral synthesis level. It permits designers to replace modules on non-critical path with the high-Vth implementation. Though, the existing constructive algorithms fail to find the optimal solution due to the complexity of the problem and do not consider the on-chip temperature variation. In his research, a two-stage thermal dependent leakage power minimization algorithm is proposed by using dual- Vth library during behavioral synthesis. In the
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first stage, the timing impact on other modules caused by replacing certain modules with high Vth is quantitatively evaluated. Based on this analysis and the characteristics of the dual- Vth module library, a small set of candidate solutions is generated for the module replacement. Then in the second stage, the on-chip thermal information is obtained from thermal-aware floor planning and thermal analysis to select the final solution from the candidate set. Experimental results show an average of 17.8% saving in leakage energy consumption and a slightly shorter runtime compared to the best known work. In most cases, this algorithm can actually find the optimal solution obtained from a complete solution space exploration. One of the most effective design techniques for reducing leakage is dual- Vth design [8], where performance-critical transistors are made of low- Vth to provide the required performance and high- Vth transistors are used everywhere else to reduce leakage. Dual- Vth assignment or allocation can be applied to all phases of the design flow. Although transistor level dual- Vth allocation is the most effective for leakage reduction, it is also the most challenging due to the complexity of dealing with the billions of transistors in modern ICs. Thus it has been proposed [9, 10] to allocate Vth at behavioral level, where the solution space is much smaller than that at the transistor level. At behavioral level, dual- Vth allocation can be converted to the module selection problem. The modules on noncritical path are selected to be replaced with high- Vth implementation. Due to factors such as module sharing in behavioral level, it is difficult to model the timing relationship of modules precisely. And consequently, the optimal module selection will be hard to obtain. Kawaguch et al, [11] proposed a circuit called Super Cutoff CMOS (SCCMOS), which is an alternate to MTCMOS power gating. In this technique, the sleep transistors are under-driven (NMOS) or over-driven (PMOS) when in the standby mode. An NMOS transistor will be turned off with a slight negative gate voltage instead of zero voltage. This negative gate voltage decreases the subthreshold leakage current exponentially. In this scheme the sleep transistor and the logic transistors are having the same standard Vt. Therefore the circuit operates fast in the active mode. During standby mode, since the transistor is turned off with a negative gate voltage, sub-threshold leakage current reduces exponentially. Yuan et al, [12] presented an Input Vector Control approach for leakage current reduction. IVC takes advantage of transistor stack effect to apply the minimum leakage vector (MLV) to the primary inputs of the circuit during the standby mode. Though, IVC technique becomes less effective for circuits of large logic depth because the MLV at primary inputs has little impact on internal gates at high logic level. In his research, a technique is presented to overcome this limitation by directly controlling the inputs to the internal gates that are in their worst leakage states. Specifically, a gate replacement technique is proposed that replaces such gates by other library gates while maintaining the circuit’s correct functionality at the active mode. This alteration of the circuit does not require changes of the design flow, but it opens the
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door for further leakage reduction, when the MLV is not effective. The author then describes a divide and-conquer approach that combines the gate replacement and input vector control techniques. It incorporates an algorithm that finds the optimal MLV for tree circuits, a fast gate replacement heuristic, and a genetic algorithm that connects the tree circuits. Behnam et al, [13] discussed on the leakage minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology. Aggressive CMOS scaling results in the low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing subthreshold and tunneling gate leakage currents has become one of the most important criteria in the design of VLSI circuits. His research puts forth a method based on dual-Vt and dual-Tox assignment to reduce the total leakage power dissipation of SRAMs while maintaining their performance. The technique is based on the observation that read and writes delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. Thus, the idea is to implement different configurations of six-transistor SRAM cells corresponding to different threshold voltage and oxide thickness assignments for the transistors. Different to other techniques for low leakage SRAM design, the proposed technique incurs neither area nor delay overhead. In addition, it results in a minor change in the SRAM design flow. The leakage saving obtained by using this technique is a function of the values of the high threshold voltage and the oxide thickness, as well as the number of rows and columns in the cell array. CMOS scaling beyond the 90nm technology node requires not only very low threshold voltages (Vt) to retain the device switching speeds, but also ultra-thin gate oxides (Tox) to maintain the current drive and keep threshold voltage variations under control when dealing with short-channel effects [14]. Low threshold voltage results in an exponential increase in the subthreshold leakage current, whereas ultrathin oxide causes an exponential increase in the tunneling gate leakage current. The leakage power dissipation is approximately proportional to the area of a circuit. Since in many processors caches occupy about 50% of the chip area [15], the leakage power of caches is one of the major sources of power consumption in high performance microprocessors. While one of the ways in reducing the subthreshold leakage is to use higher threshold voltages in some parts of a design, to suppress tunneling gate leakage, high-k dielectrics or multiple gate oxides may be used. In [16, 17] a comparative study of using high-k dielectric and dual oxide thickness on the leakage power consumption has been presented and an algorithm for simultaneous high-k and high-Tox assignment has been proposed. Although some investigation has been done on Zirconium- and Hafnium-based high-k dielectrics [18], there are unresolved manufacturing process challenges in way of introducing high-k dielectric material under the gate (e.g., related to the compatibility of these materials with Silicon [19] and the need to switch to metal gates); hence, high-k dielectrics are not expected to be used before 45nm
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technology node [18,20], leaving multiple gate oxide thicknesses as the one promising solution to reduce tunneling gate leakage current at the present time. Kyung Ki Kim et al, [21] proposed a novel design method to minimize the leakage power during standby mode using a novel adaptive supply voltage and body-bias voltage generating technique. Based on the temperature and process conditions, the optimal supply voltage is generated to reduce leakage power. The body bias voltage is automatically adjusted continuously by the control loop to adapt to the process voltage and temperature (PVT) variations. By tuning body-bias voltage using leakage monitoring circuit, circuits can be biased at the optimal point where sub-threshold leakage current and band-to-bandtunneling (BTBT_ leakage current are balanced to accomplish the minimum leakage power. Changbo et al, [23] puts forth a Distributed Sleep Transistor Network for power reduction. Sleep transistors are efficient to reduce dynamic and leakage power. The cluster-based design (Refer Fig. 4) was presented to reduce the sleep transistor area by clustering gates to minimize the simultaneous switching current per cluster and then inserting a sleep transistor per cluster. In the research, the author proposes a novel distributed sleep transistor network (DSTN), and show that DSTN is intrinsically better than the cluster based design in terms of the sleep transistor area and circuit performance. The author reveals properties of optimal DSTN designs, and then develops an efficient algorithm for gate level DSTN synthesis. The algorithm obtains DSTN designs with up to 70.7% sleep transistor area reduction when compared to cluster-based designs. Furthermore, the author presents custom layout designs to verify the area reduction by DSTN. In the clusterbased structure shown in Figure 4, a module is decomposed into several logic clusters, and each cluster is supported by one local sleep transistor. Figure 5 shows the distributed structure called Distributed Sleep Transistor Network (DSTN). In the DSTN structure, the cluster-based sleep transistor deployment is enhanced by connecting all the virtual ground lines (VGND) together, thus allowing the operating current from each cluster to flow through all the sleep transistors. In this way, the discharged current among the sleep transistors tends to be balanced.

Fig. 6 Distributed Sleep Transistor Network (DSTN)

Narender Hanchate et al, [23] proposed a novel technique called LECTOR (Refer Fig. 6) for reducing leakage power in CMOS circuits. He introduced two leakage control transistors (LCT) a PMOS and NMOS within the logic gate. The gate terminal of each LCT is controlled by the source of the other. In this arrangement, one of the LCT’s is always near its cutoff voltage for any input combination. This increases the resistance of the path from Vdd to ground leading to significant decrease in leakage currents. This technique works effectively in both active and idle states of the circuit, resulting in better leakage reduction. The experimental results indicate an average leakage reduction of 79.4% for MCNC “91 benchmark circuits. De-Shiuan et al, [24] discussed on the power reduction using sleep transistor sizing for leakage power minimization considering charge balancing. One of the efficient techniques to reduce leakage power is power gating. Previously, a DSTN was proposed to reduce the sleep transistor area for power gating by connecting all the virtual ground lines together to minimize the Maximum Instantaneous Current flowing through sleep transistors. In his research, a new methodology is proposed for determining the sizes of sleep transistors of the DSTN structure. The author presents novel algorithms and theorems for efficiently estimating a tight upper bound of the voltage drop and minimizing the sizes of sleep transistors. The author also presents mathematical proofs of the theorems and lemmas in detail. The experimental results show 23.36% sleep transistor area reduction when compared to the previous work on space reduction.

Fig. 5. Cluster based design Fig. 7 LECTOR Circuit

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Youngsoo et al, [25] presented a Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements. ZPG solved the long wake-up delay of standard power gating, but its requirement for both nMOS and pMOS current switches, in a zigzag pattern, requires complicated power networks, limiting application to custom designs. The Zigzag Power gating (ZPG) circuit is shown in Figure 7. The author proposed a design framework for cell-based semicustom design of ZPG circuits, using a new power network architecture that allows the unmodified conventional logic cells to be combined with custom circuitry such as ZPG flipflops, input forcing circuits, and current switches. The design flow, from the register transfer level description to layout, is described and applied to a 32-b microprocessor design using a 1.2-V 65-nm triple-well bulk CMOS process. The use of a sleep vector in ZPG needs additional switching power when entering standby mode and returning to active mode. The switching power must be minimized so that is does not outweigh the leakage saved by employing ZPG scheme. The author formulates the selection of a sleep vector as a multiobjective optimization problem, minimizing both the transition energy and the total wire length of a design. The author solved the problem by employing multiobjective genetic-based algorithm. Experimental results of the author technique show an average saving of 39% in transition energy and 8% in total wire length for several benchmark circuits in 65-nm technology.

benchmark circuits. The results from the author’s algorithm can lead to about 22% less power dissipation subject to the same timing constraints. Hyunsik et al [27] developed a technique called variable threshold CMOS, or VTCMOS to reduce standby leakage currents. VTCMOS relies on a triple well process where the device Vt is dynamically adjusted by biasing the body terminal. By applying maximum reverse biasing during the standby mode, the threshold voltage is shifted higher and the sub-threshold leakage current is reduced. The threshold voltage can be tuned during active mode to optimize performance. III. CONCLUSION

As technology scales down below 90 nm, leakage currents have become a critical issue. In the past, circuit techniques and architectures ignored the effects of these currents because they were insignificant compared to the switching currents and threshold voltages were high enough. However, in modern technologies, the role of the leakage currents cannot be ignored and becomes increasingly significant issue with further scaling. Therefore, new circuit techniques and design considerations must be developed to control leakage currents in standby mode in order to provide low-power solutions. After analyzing various leakage reduction techniques, it can be concluded that there is a strong correlation between the three performance metrics: leakage power, dynamic power and propagation delay. If one metric is optimized, it leads to a compromise of other metrics. It can be concluded that super cutoff CMOS scheme provides efficient leakage power savings in standby mode and forced stacking is a very effective leakage power saving scheme for active mode of operation. However, if propagation delay is the main criteria, it is recommended that a single sleep transistor based circuits are used in standby mode, though leakage savings of upto an order of magnitude is sacrificed. In active mode of operation, the sleepy stack based approach is suitable for faster circuit operation. REFERENCES
[1] [2] [3] J. Kao, S. Narendra, A. Chandrakasan, “Subthreshold Leakage Modeling and Reduction Techniques”, Proceedings of ICCAD, pp. 141-148, 2002 Borivoje Nikolic, “Design in the Power Limited Scaling Regime,” IEEE Transactions On Electron Devices, vol. 55, no. 1, January 2008. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, “1-v Power Supply High Speed Digital Circuit Technology with Multi-threshold Voltage CMOS,” IEEE Journal of Solid State Circuits, vol.30, no.8, pp. 847-854, August 1995 S. Narendra, S. Borkar, V. De, D.Antoniadis, and A. Chandrakasan, ‘Scaling of Stack effect and its Application for Leakage Reduction,” in proceedings of the International Symposium on Low Power Electronics and Design, augusty 2001, pp.195-200. Jun Cheol Park and Vincent J. Mooney,’Sleepy Stack Reduction of Leakage Power,” IEEE Transactions on Very Large Scale Integration (VLSI) systems, vol. 14, no. 11, November 2006, pp. 1250-1263. Preetham Lakshmikanthan and Adrian Nunez,” A Signal Probability based Self-Controlling Leakage Reduction Technique for CMOS Circuits,”International Conference on Electrical and Electronics Engineering (ICEEE 2007), September 2007.

Fig. 8. Zigzag Power Gating (ZPG) Circuit

Liu et al, [26] presented a novel power optimization technique by gate sizing. Gate sizing and threshold voltage (Vt) assignment are famous techniques for circuit timing and power optimization. Existing methods are either sensitivitydriven heuristics or based on discretizing continuous optimization solutions. Sensitivity-driven methods are easily trapped in local optima and the discretization may be subject to remarkable errors. In his research, a systematic combinatorial approach is proposed for simultaneous gate sizing and Vt assignment. The core idea of this technique is joint relaxation and restriction, which employs consistency relaxation and coupled bi-directional solution search. The process of joint relaxation and restriction is performed iteratively to systematically improve solutions. The authors’ algorithm is compared with a state-of-the-art previous work on
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