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Espoo 2006 Report 43
DIGITAL SIGNAL PROCESSING AND DIGITALTOANALOG
CONVERTERS FOR WIDEBAND TRANSMITTERS
Marko Kosunen
Dissertation for the degree of Doctor of Science in Technology to be presented with due permis
sion of the Department of Electrical and Communications Engineering for public examination
and debate in Auditorium S4 at Helsinki University of Technology (Espoo, Finland) on the 10th
of November, 2006, at 12 noon.
Helsinki University of Technology
Department of Electrical and Communications Engineering
Electronic Circuit Design Laboratory
Teknillinen korkeakoulu
Sähkö ja tietoliikennetekniikan osasto
Piiritekniikan laboratorio
Distribution:
Helsinki University of Technology
Department of Electrical and Communications Engineering
Electronic Circuit Design Laboratory
P.O.Box 3000
FIN02015 HUT
Finland
Tel. +358 9 4512271
Fax: +358 9 4512269
ISBN10 951228409X
ISBN10 9512284103 (PDF)
ISBN13 9789512284092
ISBN13 9789512284108 (PDF)
ISSN 14558440
Otamedia Oy
Espoo 2006
Abstract
In this thesis, the implementation methods of digital signal processing and digital
toanalog converters for wideband transmitters are researched. With digital signal
processing, the problems of analog signal processing, such as sensitivity to interfer
ence and nonidealities of the semiconductor processes, can be avoided. Also, the pro
grammability can be implemented digitally more easily than by means of analog signal
processing.
During the past few years, wireless communications has evolved from analog to
digital, and signal bandwidths have increased, enabling faster and faster data trans
mission. The evolution of semiconductor processes, decreasing linewidth and supply
voltages, has decreased the size of the electronics and power dissipation, enabling the
integration of larger and larger systems on single silicon chips.
There is little overall beneﬁt in decreasing linewidths to meet the needs of analog
design, since it makes the design process more difﬁcult as the device sizes cannot be
scaled according to minimum linewidth and because of the decreasing supply voltage.
On the other hand, the challenges of digital signal processing are related to the efﬁcient
realization of signal processing algorithms in such a way that the required area and
power dissipation does not increase extensively.
In this book, the problems related to digital ﬁlters, upconversion algorithms and
digitaltoanalog converters used in digital transmitters are researched. Research re
sults are applied to the implementation of a transmitter for a thirdgeneration WCDMA
basestation.
In addition, the theory of factors affecting the linearity and performance of digital
to analog converters is researched, and a digital calibration algorithm for enhancement
of the static linearity has been presented. The algorithmhas been implemented together
with a 16bit converter; its functionality has been demonstrated with measurements.
Keywords: Direct digital synthesizer, Digital transmitter, modulator,
CORDIC, digitaltoanalog converter, calibration.
Tiivistelmä
Tässä väitöskirjassa on tutkittu digitaalisen signaalinkäsittelyn toteuttamista ja digi
taalisesta analogiseksimuuntimia laajakaistaisiin lähettimiin. Digitaalisella signaalin
käsittelyllä voidaan välttää monia analogiseen signaalinkäsittelyyn liittyviä ongelmia,
kuten häiriöherkkyyttä ja puolijohdeprosessien epäideaalisuuksien vaikutuksia. Myös
ohjelmoitavuus on helpommin toteutettavissa digitaalisesti kuin analogisen signaalin
käsittelyn keinoin.
Viime vuosina on langattomien tietoliikennejärjestelmien kehitys kulkenut anal
ogisesta digitaaliseen, ja käytettävät signaalikaistanleveydet ovat kasvaneet mahdol
listaen yhä nopeamman tiedonsiirron. Puolijohdeprosessien kehitys, kapeneva min
imiviivanleveys ja pienemmät käyttöjännitteet, on pienentänyt elektroniikan kokoa ja
tehonkulutusta mahdollistaen yhä suurempien kokonaisuuksien integroimisen yhdelle
piisirulle. Viivanleveyksien pieneneminen ei kuitenkaan suoraan hyödytä analogia
suunnittelua, jossa piirielementtien kokoa ei välttämättä voida pienentää viivanlevey
den pienentyessä, ja jossa madaltuva käyttöjännite ennemminkin hankaloittaa kuin
helpottaa suunnittelua. Siksi yhä suurempi osa signaalinkäsittelystä pyritään tekemään
digitaalisesti. Digitaalisen signaalinkäsittelyn ongelmat puolestaan liittyvät algorit
mien tehokkaaseen toteuttamiseen siten, että piirien pintaala ja tehonkulutus eivät
kasva liian suuriksi.
Tässä kirjassa on tutkittu digitaalisessa lähettimessä tarvittavien digitaalisten suo
dattimien, ylössekoitusalgoritmien ja digitaalisesta analogiseksimuuntimien toteut
tamiseen liittyviä ongelmia. Tutkimustuloksia on sovellettu kolmannen sukupolven
WCDMAtukiasemalähettimen toteutuksessa.
Lisäksi on tutkittu digitaalisesta analogiseksimuuntimien lineaarisuuteen ja suori
tuskykyyn vaikuttavien seikkojen teoriaa, ja esitetty digitaalinen kalibrointialgoritmi
muuntimen staattisen suorituskyvyn parantamiseksi. Algoritmi on toteutettu 16bittisen
muuntimen yhteydessä ja se on osoitettu toimivaksi mittauksin.
Avainsanat: Suora digitaalinen syntetisaattori, digitaalinen lähetin, modulaattori,
CORDIC, digitaalisesta analogiseksimuunnin, kalibrointi.
Preface
The research for this thesis was carried out at the Electronic Circuit Design Laboratory
(ECDL) of Helsinki University of Technology during the years 19982005. The work
presented in this book has been carried out in research projects funded by Nokia Net
works, Nokia Research Center and Finnish National Technology Agency. I also thank
the Nokia Foundation, the Finnish Society of Electronics Engineers, and the Founda
tion of Technology for their ﬁnancial support.
I express my gratitude to Professor Kari Halonen for his guidance and support,
and for the opportunity to carry out this research in such an inspiring and relaxed
environment as the Electronic Circuit Design Laboratory. My warmest thanks go to
Dr. Jouko Vankka, my supervisor, for his guidance and new ideas during the years we
worked together. I would also like to express my gratitude to Jussi Pirkkalaniemi for his
contribution to the research presented in this book. I also warmly thank Professors Jiren
Yuan and Trond Ytterdal for reviewing this thesis, and for their valuable comments and
suggestions.
I gratefully acknowledge all my colleagues with whom I have been honored to
work throughout the years. Special thanks go to Mikko Waltari, Jonne Lindeberg,
Väinö Hakkarainen and Jacek Flack for the very interesting conversations we had dur
ing the years through which we shared out room. In addition to those mentioned above,
I would like to express my sincerest gratitude to Rami Ahola, Asko Kananen, Jaakko
Ketola, Kimmo Koli, Lauri Koskinen, Saska Lindfors, Mika Länsirinne, Esa Tiiliharju,
Ari Paasio, Jussi Pirkkalaniemi and Helena Yllö for their professional assistance, and,
most of all, for their active participation in our notsoprofessional recreational activi
ties, including our gooddoing at 4 a.m., the endless planning of trips to the museum of
former president Kekkonen, and listening to my neverending environmental preach
ing. Special thanks also to Marja and Outi.
I would like to thank my former teachers Varpu Rönnholm, Kaarina Koskinen, and
Eino Sandelin for guidance they have given me, and, express my warmest thanks to
all my friends, with whom I have shared many great moments throughout the years.
vi
Pikkutomi, Tumppi, Attila, Kimmo and the other ”Boys of Puotila”, Natski, Jomi,
Oippa, Pamppu, Kartsa et al., thanks for the fun, and for keeping me relatively sane.
I would also like to thank my inlaws for their support, beer, great cooking, beauti
ful daughter, and great sense of humor.
I would like to thank my mother and father for their love, teachings, and support.
Thanks also to my sister Marjo and my nephew Antti.
The rest of this page was reserved for the praise of my intelligent and goodlooking
wife, and my beautiful and loving daughters. Being an engineer, not a poet, my writ
ings seem to turn out to be either dimwitted or naive. Therefore I chose to be short and
compact. Katri, Auri, and Ira, I could not love you more. Thanks for your existence.
Puotila, Helsinki, September 2006
Marko Kosunen
Contents
Abstract i
Tiivistelmä iii
Preface v
Contents vii
Symbols and abbreviations xi
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Organization of the thesis and research contribution . . . . . . . . . . 2
2 Direct sequence spreadspectrum quadrature amplitude modulation 5
2.1 Principle of QAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Pulse shaping ﬁltering . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Performance metrics . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Transmitter structures 13
3.1 Direct conversion transmitter . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Twostep transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Phase modulating synthesizers . . . . . . . . . . . . . . . . . . . . . 15
3.4 Constant envelope transmitters for power ampliﬁer linearization . . . 16
3.4.1 Envelope elimination and restoration . . . . . . . . . . . . . . 17
3.4.2 LINC transmitter . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5 Digital QAM transmitter . . . . . . . . . . . . . . . . . . . . . . . . 18
4 Resourceefﬁcient digital ﬁlter design 21
4.1 Filter design algorithms . . . . . . . . . . . . . . . . . . . . . . . . . 22
viii
4.1.1 Pulse shaping ﬁlter design algorithm . . . . . . . . . . . . . . 22
4.1.2 Halfband ﬁlters for interpolation . . . . . . . . . . . . . . . 26
4.2 Mapping the ﬂoating point ﬁlter coefﬁcients to canonic signed digit
format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3 Efﬁcient FIR ﬁlter structures . . . . . . . . . . . . . . . . . . . . . . 28
4.3.1 Polyphase FIR ﬁlters in sampling rate converters . . . . . . . 28
4.3.2 Efﬁcient realizations of FIR ﬁlters . . . . . . . . . . . . . . . 31
4.3.2.1 Direct form structure . . . . . . . . . . . . . . . . 33
4.3.2.2 Transposed direct form structure . . . . . . . . . . 34
4.3.2.3 Pipelining/interleaving technique . . . . . . . . . . 35
4.3.2.4 Reduction of the sign bit load . . . . . . . . . . . . 35
4.3.2.5 Word length effects and scaling . . . . . . . . . . . 36
5 Methods for direct digital frequency synthesis and modulation 39
5.1 Direct digital frequency synthesizers using the lookup table method. . 39
5.2 CORDIC vector rotation algorithm based frequency synthesizer and
modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.3 Survey of digital frequency synthesizers . . . . . . . . . . . . . . . . 45
5.4 Other digital modulation methods . . . . . . . . . . . . . . . . . . . 47
5.4.1 Modulation to quarter of the sampling rate . . . . . . . . . . . 47
5.4.2 Frequency synthesis with nonlinear D/A converter . . . . . . 47
6 Currentsteering digitaltoanalog converter design 49
6.1 General description of the current steering D/A converter . . . . . . . 50
6.2 Performance metrics . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.2.1 Static linearity: Gain error, DNL and INL . . . . . . . . . . . 53
6.2.2 Linearity and noise: SNR, SFDR, THD, SINAD and ENOB . 55
6.2.3 Time domain performance: Settling and glitches . . . . . . . 56
6.3 Models and relations of transistor mismatch and static linearity . . . . 57
6.3.1 Current source mismatch and yield . . . . . . . . . . . . . . . 57
6.3.2 Statistical model of the static linearity . . . . . . . . . . . . . 59
6.3.3 INL yield models . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.4 Regression model for the INL and DNL yields . . . . . . . . 75
6.4 Calibration techniques . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.5 Effects of output impedance variation . . . . . . . . . . . . . . . . . 89
6.5.1 Distortion due to low frequency impedance variation . . . . . 90
6.5.2 Frequency dependency of the output impedance . . . . . . . . 93
6.6 From discrete to continuoustime domain . . . . . . . . . . . . . . . 104
6.7 Sampling jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
ix
6.7.1 Effects of sinusoidal timing jitter . . . . . . . . . . . . . . . . 110
6.7.2 Distortion due to signaldependent jitter . . . . . . . . . . . . 116
6.7.3 Jitter due to codedependent clock load . . . . . . . . . . . . 119
6.7.4 Jitter due to powerrail interference . . . . . . . . . . . . . . 122
6.8 Layout techniques for current source mismatch reduction . . . . . . . 126
6.9 Survey of published D/A converters . . . . . . . . . . . . . . . . . . 133
7 Prototypes and experimental results 139
7.1 Prototype of WCDMA transmitter . . . . . . . . . . . . . . . . . . . 139
7.1.1 Frequency planning . . . . . . . . . . . . . . . . . . . . . . . 141
7.1.2 Interpolation strategy . . . . . . . . . . . . . . . . . . . . . . 141
7.1.3 Digital FIR ﬁlter and interpolator design . . . . . . . . . . . . 142
7.1.4 CORDIC and inverseSINC ﬁlter design . . . . . . . . . . . . 147
7.1.4.1 CORDIC design . . . . . . . . . . . . . . . . . . . 147
7.1.4.2 InverseSINC ﬁlter design . . . . . . . . . . . . . . 149
7.1.5 Simulated QAM performance . . . . . . . . . . . . . . . . . 149
7.1.6 Digital ASIC synthesis ﬂow . . . . . . . . . . . . . . . . . . 149
7.1.7 14bit 70MHz Digitaltoanalog converter . . . . . . . . . . . 152
7.1.7.1 Static matching . . . . . . . . . . . . . . . . . . . 152
7.1.7.2 Enhancement of dynamic properties . . . . . . . . 153
7.1.7.3 Layout issues . . . . . . . . . . . . . . . . . . . . 156
7.1.7.4 D/A converter simulations . . . . . . . . . . . . . . 156
7.1.8 Experimental results . . . . . . . . . . . . . . . . . . . . . . 157
7.1.8.1 Measurement setup . . . . . . . . . . . . . . . . . 157
7.1.8.2 D/Aconverter performance . . . . . . . . . . . . . 159
7.1.8.3 Static performance of the D/Aconverter . . . . . . 159
7.1.8.4 Dynamic performance of the D/Aconverter . . . . 159
7.1.8.5 QAM Performance . . . . . . . . . . . . . . . . . 166
7.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 171
7.2.1 Current source dimensions and DC matching . . . . . . . . . 172
7.2.2 Output impedance . . . . . . . . . . . . . . . . . . . . . . . 174
7.2.3 Current source matrices . . . . . . . . . . . . . . . . . . . . 177
7.2.4 Dynamic performance . . . . . . . . . . . . . . . . . . . . . 179
7.2.5 Logic for digital calibration . . . . . . . . . . . . . . . . . . 184
7.2.6 DNL measurement for calibration . . . . . . . . . . . . . . . 188
7.2.7 Experimental results . . . . . . . . . . . . . . . . . . . . . . 189
7.2.7.1 Static linearity . . . . . . . . . . . . . . . . . . . . 191
7.2.7.2 Dynamic performance . . . . . . . . . . . . . . . . 193
7.2.7.3 Summary . . . . . . . . . . . . . . . . . . . . . . . 195
x
Conclusions 201
Bibliography 203
A Photomicrograph of the WCDMA transmitter 219
B Photomicrograph of the D/A converter with digital calibration 221
C Jitter energy as a function of signal frequency and jitter amplitude 223
D Fourier transforms of some functions used in this book 227
D.1 Elementary relations . . . . . . . . . . . . . . . . . . . . . . . . . . 227
D.2 Elementary functions and operations . . . . . . . . . . . . . . . . . . 227
Symbols and abbreviations
α Roll of factor of rootraised cosine ﬁlter
β Current factor of a MOS transistor
∆F Width of the transition band of a ﬁlter
∆ Quantization step due to the internal word length of a
ﬁlter
∆φ Phase increment of a DDS or a CORDIC vector rotator
∆Σ DeltaSigma, e.g. ∆Σmodulator
∆
o
Quantization step at the output of a ﬁlter
ε
2
f
Squared approximation error of the yield regression model
ε
i
Error current of i
th
ε
ri
Error of i
th
current source, relative to I
lsb
B(n) The mean of B(n)
ω Angular frequency (in general)
ω
c
Angular carrier frequency
ω
i f
Angular intermediate frequency
ω
r f
Angular radio frequency
Φband Don’tcare band of a ﬁlter
Φ(C, M) and X(C, M) Yield functions of a converter
φ(n) Discretetime angle value
φ
d
(t) Phase angle signal of EER transmitter
xii
φ
k
Precomputed rotation angle value of the k
th
rotation stage
of a CORDIC rotator
ρ
t
(k1, k2) Correlation factor of INLvalues with input codes k1 and
k2
σ
2
β
Variance of the β of a transistor
σ
2
Id
Variance of the drain current
σ
2
vt
Variance of the V
t
σ
2
DNLmax
Variance of the maximum value of DNL
σ
2
I
lsb
Variance of a LSB current source
σ
2
INL
t
(k) Variance of INL with input code k
σ
2
INLmax
Variance of the maximum value of INL
σ
2
iwl
Variance of the noise generated by limited internal word
length of a ﬁlter
σ
2
lsb
Relative variance of a LSBunit currentsource of a ther
mometer coded D/A converter
σ
2
n
Variance of the noise
σ
2
op
Variance of the quantization noise at the output of a ﬁlter
σ
2
s
Variance of the symbol error
τ Time misalignment between two pulse sequences
A Matrix for calculation of ISI
rms
A(n), B(n), and C(n) Subbuses of the phase value bus φ(n) in DDS sine com
pression
A(t) Amplitude signal of EER transmitter
A
beta
Current factor matching parameter of a transistor
A
c
Matrix for calculation of the center coefﬁcient of a ﬁlter
a
c
Amplitude of c(t)
a
d
Amplitude of d (t)
A
vt
Threshold voltage matching parameter of a transistor
xiii
ACLR
n
Adjacent channel leakage power ratio deﬁned for n
th
ad
jacent channel
ACPR
n
Adjacent channel power ratio deﬁned for n
th
adjacent
channel
B Binary matrix for computing INL of a binary weighted
D/A converter
B Internal word length of a ﬁlter
B
d
Energy band width of d (t)
B
o
Number of output bits of a ﬁlter
B
s
Energy band width of s(t)
BER Bit error rate
c(t) Spreading pulse sequence
C
s
, c
sk
1
,k
2
Covariance matrix of INLs of a segmented converter and
it’s element
C
t
Covariance matrix of a thermometer coded D/Aconverter
c
t
(k
1,
k
2
) Covariance of INLvalues with input codes k
1
and k
2
D( f ) Power density function of d (t)
d (t) Continuoustime data signal
DNL Differential nonlinearity
E
b
Error vector of normally distributed random variables
with zero mean and variance σ
2
lsb
E
p
Matrix notation for passband power
E
s
Matrix notation for stopband power
ENOB Effective number of bits
EVM Error vector magnitude
EVM
rms
Rootmeansquare error vector magnitude
F
c
Pulse rate of the spreading sequence c(t)
F
d
Data rate of d (t)
xiv
F
pb
Passband edge frequency
F
sd
Sampling rate after decimation or downsampling
F
si
Sampling rate after interpolation or upsampling
F
s
Sampling frequency, Sampling rate
g
ds
Drainsource conductance of a transistor
g
m
Transconductance of a transistor
G
s
Spreading gain
H(s) Impulse response of a ﬁlter in s domain
h(n) Discretetime ﬁlter
H
1
( f ) Frequency response of the n
th
subsystem
h
n
(t) Impulse response of the n
th
subsystemof a D/Aconverter
model
h
r
(n) Discretetime channel ﬁlter of a receiver
h
sd
(n) Discretetime ﬁlter with signeddigit coefﬁcients
h
tr
(n) Combination of the transmitter and receiver channel ﬁl
ters
H
t
( f ) Frequency response of a transmit ﬁlter
h
t
(n) Discretetime channel ﬁlter of a transmitter
i (n) and q(n) Discrete time inphase and quadrature data signals
i (t), q(t) Continuoustime inphase and quadrature signals
I
lsba
Actual average LSB current
I
lsb
LSB current of a D/A converter
INL Integral nonlinearity
INL
s
INL vector for segmented D/A converter
INL
t
INLvector of a thermometer coded D/A converter
INL
t
(k) INLvalue with input code k normalized to I
lsba
xv
INL
zdi
INL of due to ﬁnite output impedance, differential output
INL
zsemax
Maximum value of INL
zsemax
INL
zse
INL due to ﬁnite output impedance, single ended output
ISI Intersymbol interference
ISI
rms
Rootmeansquare intersymbol interference
L Channel length of a MOS transistor
L Oversampling ratio,interpolation factor, also the channel
length of a transistor
L(h
t
, λ) Langrangian cost function for transmit ﬁlter optimization
M Decimation ratio
M
input
, M
out put
Maximum presentable number at the input and output of
a digital ﬁlter, respectively
N
c
Index of the center coefﬁcient of the ﬁlter
P( f ) Power transfer function
P
cchan
Power of the current signal channel
P
cchan
Power of the current signal channel
P
nth_ad j_chan
Power of n
th
adjacent frequency channel
P
p
and pp
i,k
Matrix for passband power computation and one of it’s
elements
P
s
and ps
i,k
Matrix for stopband power computation and one of it’s
elements
r (t) Despread data signal
R
c
(τ) Autocorrelation function of c(t)
R
d
(τ) Autocorrelation function of d (t)
R
s
(τ) Autocorrelation function of s(t)
RCOS Raisedcosine
RCOS( f ) Frequency response of a raisedcosine ﬁlter
xvi
rcos(n) Discretetime impulse response of a raisedcosine ﬁlter
rcos(t) Continuoustime impulse response of a raisedcosine ﬁl
ter
rrc(t) Continuoustime rootraised cosine impulse
S Code matrix for a segmented D/A converter
S( f ) Power density function of s(t)
s(n) and ∆s(n) Discretetime signal s(n) and discretetime derivative s(n)−
s(n−1)
s(t) Spread data signal
S
beta
Constant for distance dependency of the current factor
matching of a transistor
S
n
and sn
a,b
One of the convolution matrices and it’s elements
s
rq
(t), s
ri
(t) Received inphase and quadrature signals
s
t
(t) Transmitted signal
S
vt
Constant for distance dependency of the threshold volt
age matching of a transistor
SER Symbol error rate
SFDR Spuriousfree dynamic range
SFDR
zdi
SFDR due to ﬁnite output impedance, differential output
SFDR
zse
SFDR due to ﬁnite output impedance, single ended out
put
SINAD Signaltonoise and distortion ratio
SNR Signaltonoise Ratio
T
c
Pulse duration of c(t)
T
d
Pulse duration of d (t)
T
f
Fall time
T
r
Rise time
T
s
Sampling interval
xvii
THD Total harmonic distortion
u(t) Unit step function
V
gs
Gatesource voltage of a MOS transistor
V
ss
Negative supply voltage
V
T
Threshold voltage of a MOS transistor
W Channel width of a MOS transistor
W
b
and w
i
Weighting vector for computing the INL of a binary weighted
D/A converter and its element
W
db
Diagonal weighting matrix
Diag(W
b
)
W
s
Weight matrix of a segmented D/A converter
WL
opt
Optimum area of a transistor in static matching sense
x(n) Discrete time signal (in general)
x
d
( f ) and x
i
( f ) Downsampled and upsampled signals in frequency do
main
x
d
(n) and x
i
(n) Downsampled and upsampled discrete time signals
X
k
(n), Y
k
(n) Amplitude outputs of k
th
CORDIC rotator stage
Z
c
Load impedance of a unit current branch of a D/A con
verter in conducting state
Z
k
(n) Phase output of k
th
CORDIC rotator stage
Z
l
Load impedance of a D/A converter
Z
op
Load impedance of a unit current branch of a D/A con
verter in nonconducting state
Z
u
Impedance variation of a unit current source of a D/A
converter due to switching
F { } Fourier transform
3G Third generation wireless communication systems
ADC Analogtodigital converter
xviii
BiCMOS Complementary metal oxide semiconductor process with
bipolar transistors
Bluetooth Wireless communications standard for shortrange appli
cations
CALvalue Code value at the input of the converter that selects the
thermometer current source to be calibrated
CDF Cumulative distribution function
CDMA Code Division Multiple Access
CMOS Complementary metal oxide semiconductor
CORDIC Coordinate rotation digital computer
CSD Canonic signeddigit, see also SD and MSD
DDS Direct digital synthesizer
EDGE Enhanced data rate for GSM evolution
EER Envelope elimination and restoration
FFT Fast Fourier transform
FIR Finite impulse response
GBW Gain bandwidth product of an ampliﬁer
GPRS General Packet Radio Service
GSM Group special mobile/Global system for mobile commu
nications
I and Q Inphase and quadrature
LINC Linear ampliﬁcation with nonlinear components
LO Local oscillator
LSB Least signiﬁcant bit
LUT Lookup table
MOS Metal oxide semiconductor
MSD Minimum signeddigit, see also SD and CSD
xix
MUX Multiplexer
MVN Multivariate normal distribution
NCO Numerically controlled oscillator
NMOS Ntype metal oxide semiconductor
NRZ Nonreturn to zero
P/I Pipelining/interleaving
PA Power ampliﬁer
PDF Probability density function
PLL Phaselocked loop
QAM Quadrature Amplitude Modulation
REFvalue Code value at the input of the converter that is compared
to CALvalue
RF Radio frequency
RMS Rootmeansquare
ROM Readonly memory
RZ Returntozero
SAR Successive approximation
SD Signeddigit, see also CSD and MSD
TQFP Thin quad ﬂat pack package
UMTS Universal Mobile Telecommunications System
VCO Voltagecontrolled oscillator
VLSI Very large scale integrated circuits
WCDMA Wideband Code Division Multiple Access
WiFi Wireless Fidelity, General term for 802.11 standard net
work
Wimax Worldwide Interoperability for Microwave Access
WLAN Wireless Local Area Network
Chapter 1
Introduction
1.1 Motivation
The rapid growth of the wireless communications market has been the primus motor
of the development of integrated circuit technology during the past decade. This is
because the portable electronic devices for wireless communication has to be optimized
for low power consumption, light weight, and low manufacturing cost, and the fact that
these requirements can be met simultaneously by increasing the integration level of the
electronics. The minimum linewidth of the semiconductor processes has seemed to
be everdecreasing, enabling the integration of increasingly complicated systems on a
single chip.
Even though the evolution of the silicon processes has reduced the minimum line
width, operation voltages and, thereafter, the power dissipation of the digital parts, the
devices required for analog processing have not scaled along with the minimum line
width, and the decreasing operation voltages tends to make the analog circuit design
more challenging.
In wireless communication systems, the trend has been to move from analog to
digital signal processing and increase the bandwidth. Wireless digital communications
have evolved from GSM through services such as GPRS and EDGE towards WCDMA
and 3G, which are capable of handling both the narrowvoice band and wide data bands.
Simultaneously, wireless data transmission systems such as WLAN/WiFi and Wimax
have gained popularity. It is beneﬁcial to perform most of the computation of the sys
tem in the digital the domain. Analog signal processing is sensitive to noise generated
in several sources, whereas the accuracy of the digital signal processing (DSP) may
be selected almost arbitrarily. Digital signal processing also enables ﬂexibility in the
system, since programmability and reconﬁgurability can be implemented more easily
digitally. Beneﬁts of ﬂexibility are obvious in systems like transmitters and receivers,
2 Introduction
in which the usage of DSP enables the realization of multimode transmitters such as
GSM/EDGE/WCDMA or softwareconﬁgurable radio.
Digital signal processing can be performed with a general signal processor; how
ever, it is not capable of handling the high data rates typical of digitalIF transmitters.
A dedicated DSP system for transmitter purposes is therefore usually used. The ﬁrst
part of this work is based on research into hardware efﬁcient realization methods of the
digital signal processing required for baseband and the intermediate frequency of the
multicarrier wideband code division multiple access (WCDMA) basestation trans
mitter of the 3
rd
generation (3G) wireless communication system. This system is also
often referred to as the Universal Mobile Telecommunications System (UMTS). Area
efﬁcient digital IF transmitters reduce the manufacturing cost of the transmitter chip,
decrease power consumption, and thus reduce the need for cooling and maintenance.
The second part of this work is based on research into the currentsteering digitalto
analog converters, which are the performance bottleneck of the digitalIF transmitter.
Research results are applied in the design of two prototype circuits, the ﬁrst consist
ing of the digitalIF WCDMA transmitter and the second being a currentsteering D/A
converter with a digital calibration algorithm.
1.2 Organization of the thesis and research contribu
tion
The research of the digitalIF transmitters presented in this book was performed during
the years 19982001 under the supervision of Dr. Jouko Vankka, who also performed
most of the algorithm design of the transmitter prototype. The author participated in
the algorithm design and is responsible for the design and implementation of the digital
signal processing blocks and D/A converter of the transmitter prototype.
The research of currentsteering D/A converters was carried out during the years
20012005. The author, with help fromDr. Mikko Waltari, is responsible for the design
of the calibration algorithm, and also designed and implemented the D/A converter
core and analog parts related to calibration. The digital part of the calibration was
implemented by Jussi Pirkkalaniemi, M.Sc. under the supervision of the author.
During the research, the new ideas and circuits presented in this thesis have been
partially reported in related publications [1][15]. The results obtained are also applied
in design presented in [16] and [17].
The thesis is organized as follows. Chapters 25 represent the background for the
design of a digitalIF transmitter. In Chapter 2, the basic principles of the spread
spectrum quadrature amplitude modulation is presented and the performance metrics
of the transmitter are given. In Chapter 3, the most common transmitter architectures
1.2 Organization of the thesis and research contribution 3
are brieﬂy introduced. In Chapter 4, methods for resourceefﬁcient digital ﬁlter design
are introduced, and, in Chapter 5, the methods for direct digital frequency synthesis
and digital modulation are discussed.
Chapter 6 contains the theory of the currentsteering D/A converter design. Sec
tions 6.1 and 6.2 give an introduction to currentsteering converters and their perfor
mance metrics. In Section 6.3, the static linearity of the converter is analyzed. The
previously published linearity yield models are compared, and the yield model devel
oped and published by the author, Dr. Vankka and Ilari Teikari M.Sc. [13] is pre
sented. Section 6.4 is about calibration techniques. Previously published calibration
methods are discussed, and the method developed by the author, Mikko Waltari, and
Jussi Pirkkalaniemi [14] is presented. Section 6.5 considers the distortion effects due
to the output impedance variation. In Section 6.6, the signal conversion from discrete
time digital to continuous time analog is discussed, and distortion mechanisms are
analyzed. In Section 6.7, timingrelated nonlinearities are discussed. Results are also
partially published in [15]. Section 6.8 considers the layout techniques used to reduce
the effect of the process gradients on the current source mismatch. Section 6.9 is a
survey of published D/A converters.
Chapter 7 describes the designed prototypes. Section 7.1 describes the design and
experimental results of the WCDMA transmitter prototype.In this prototype, the author
is responsible of hardware optimization and implementation of digital signal process
ing blocks, system simulations, and the design and implementation of the D/A con
verter. Dr. Waltari also gave valuable instructions for the D/A converter design. The
design project was supervised by Dr. Jouko Vankka, who also developed algorithms
related to ﬁlter design and digital upconverter. The measurements of the prototype
were carried out by the author and Dr. Vankka. The results of this section are partially
published in [1][12].
Section 7.2 describes the design and experimental results of the D/A converter pro
totype. The author is responsible of design and implementation of the D/A converter
core including the comparator chain. Calibration algorithm is developed by the author,
Jussi Pirkkalaniemi and Dr. Mikko Waltari. The digital parts of the calibration algo
rithm were designed and implemented by Jussi Pirkkalaniemi under supervision of the
author. Measurements were carried out by the author and Jussi Pirkkalaniemi.
Finally, conclusions are drawn.
Chapter 2
Direct sequence
spreadspectrum quadrature
amplitude modulation
In CDMA systems, the data of different users are transmitted on the frequency band
common to all users. The capacity of the frequency band is divided among the users
by assigning a code channel to a single user by using a spreading code. A user in
the system may use one or multiple code channels simultaneously. The spreading also
improves system capacity by introducing the gain to the signaltonoise ratio (SNR).
In the following sections, the fundamentals of direct sequence spreadspectrum
QAM are presented in order to give some insight into the design presented in Chapter
7. More detailed information on the subject can be found in textbooks [18] and [19].
2.1 Principle of QAM
In the quadrature amplitude modulation scheme, two carriers, in phase and quadrature,
are modulated with the data sequences i (t) and q(t) (Fig. 2.1)
s
t
(t) = i (t)cos(ω
c
t) +q(t)sin(ω
c
t)
=
i (t)
2
+q(t)
2
cos(ω
c
t −φ
d
(t)), (2.1)
φ
d
(t) = arctan
q(t)
i (t)
. (2.2)
In other words the information is shifted in frequency around the carrier frequency
ω
c
by multiplying with two orthogonal signals. While receiving, the signal s
t
(t) is
6 Direct sequence spreadspectrum quadrature amplitude modulation
ω cos( t )
i(t)
q(t)
c
+90
o
s
t
(t) = ( ) t ω
c
i(t) q(t) cos sin ( ) t ω +
c
Figure 2.1 The principle of QAM.
downconverted around zero frequency.
s
ri
(t) = s
t
(t)cos(ω
c
t)
=
1
2
i (t)(1+cos(2ω
c
t)) +
1
2
q(t)sin(2ω
c
t) (2.3)
s
rq
(t) = s
t
(t)sin(ω
c
t)
=
1
2
i (t)sin(2ω
c
t) +
1
2
q(t)(1−cos(2ω
c
t)) . (2.4)
After downconversion, the data signals i (t) and q(t) can be extracted by lowpass
ﬁltering.
The beneﬁt of the QAM is that twice as much data as in bare inphase modulation
can be transmitted over the same frequency band due to the fact that both the amplitude
and the phase of the carrier are modulated (see. Eq. (2.1)).
2.2 Spreading
Let’s assume that the data signal d (t) is an inﬁnite random sequence of pulses with
amplitude a
d
and duration T
d
(Fig. 2.2). This signal has an autocorrelation function
t
a
−a
...
T
Figure 2.2 The data signal.
2.2 Spreading 7
R
d
(τ) =
a
2
d
1−
τ
T
d
, τ ≤T
d
0 , τ > T
d
, (2.5)
where τ is the time misalignment between the two pulse sequences [18].
The power density function D( f ) of the data signal d (t) is the Fourier transform
of its autocorrelation function
D( f ) =
Z
+∞
−∞
R
d
(τ)e
−j2πf τ
dτ
= a
2
d
T
d
sin
2
(πf T
d
)
(πf T
d
)
2
= a
2
d
T
d
sinc
2
(πf T
d
)
=
a
2
d
F
d
sinc
2
πf
F
d
, (2.6)
where F
d
is the data rate. The main lobe, which contains most of the signal energy,
has the width of B
d
=
2
T
d
= 2F
d
centered at the zero frequency, so the upconverted data
occupies the frequency band of 2F
d
.
Next we may deﬁne a sequence c(t), which is a pulse sequence with magnitude
value a
c
=1 and pulse duration T
c
and pulse rate F
c
=
1
T
c
. The autocorrelation function
of c(t) is
R
c
(τ) =
1−
τ
T
c
, τ ≤T
c
0 , τ > T
c
. (2.7)
Next the data signal d (t) is multiplied by c(t).
s(t) = c(t)d (t) (2.8)
Since c(t) and d (t) are independent of each other, the autocorrelation function of s(t)
is a product of the autocorrelation functions R
c
(t) and R
d
(t).
R
s
(τ) = R
c
(τ)R
d
(τ) =
a
2
1−
τ
T
d
−
τ
T
c
+
τ
2
T
d
T
c
, τ < T
c
0 , τ > T
c
. (2.9)
The power density function of s(t) may now be calculated as [18].
S( f ) =
Z
∞
−∞
R
s
(τ)e
−j2πf τ
dτ
≃ a
2
1
T
d
+
1
T
c
sin
2
(πT
c
f )
π
2
f
2
. (2.10)
8 Direct sequence spreadspectrum quadrature amplitude modulation
When T
d
≫T
c
, Eq. (2.10) can be approximated as
S( f )
∼
= a
2
c
T
c
sin
2
(πT
c
f )
T
2
c
π
2
f
2
= a
2
c
T
c
sinc
2
(πT
c
f )
=
α
2
F
c
sinc
2
πf
F
c
, (2.11)
which has a main lobe of width B
s
=
2
T
c
= 2F
c
centered at zero frequency. This means
that the energy of the signal d (t) is spread to G
s
=
2T
d
2T
c
=
F
c
F
d
times wider frequency
band. G
s
is called spreading gain for the reason given in the next paragraph. The
spreading pulses are also called chips, so T
c
is also called the chip time and F
c
the chip
rate. After the spreading, data may be transmitted with, for example, an ordinary QAM
structure. Such a structure is presented in Fig. 2.1.
While receiving, the sequence of spread data is multiplied with the same sequence
that has been spread with
r (t) = d (t)c(t)c(t −τ), (2.12)
where τ is the timing misalignment. This multiplication despreads the data signal to
its original frequency band while it spreads all possible jamming signals. Other data
signals that have been spread with the codes uncorrelated with the spreading signals
are not despread. The quality of despreading improves as the τ diminishes. In the ideal
case τ = 0, the power of the received signal is maximized relative to the noise. This is
the main idea of the code division multiple access; users in the system can send their
data on the same frequency band and the data sequences can be separated from each
other by using uncorrelated spreading sequences for each user. This is presented in
Figs. 2.3, 2.4 and 2.5.
Signal
f
E
Figure 2.3 Signal before spreading.
The gain due to the despreading of the signal is G
s
, which means, that after de
2.3 Pulse shaping ﬁltering 9
Jammer
Other users
Noise
Signal
E
f
Figure 2.4 Spread signal in noisy environment with jammer signal and other users.
Other users
Noise
Jammer
Signal
Filter
E
f
Figure 2.5 Signal in receiver after despreading.
spreading and ﬁltering, the signal to noise ratio is increased with that factor compared
to SNR at the receiver input. This means that the same bit error rate (which is the func
tion of SNR) can be achieved with G
s
times worse SNR at the receiver input than in the
nonspreading systems.
2.3 Pulse shaping ﬁltering
Usually it is necessary to limit the frequency band occupied by the signal in order not
to disturb the signals transmitted on other frequency bands of the same or different
systems. The ﬁltering of the data sequences has to be performed in the time domain
so that sequential pulses do not disturb each other. This is the reason why the channel
bandwidth limiting ﬁlters are usually called pulse shaping ﬁlters when used in trans
mitters.
In a WCDMA system, the signal to be transmitted is data sequence spread with the
spreading sequence. The spreading is performed with chip rate F
c
and the ﬁltering is
10 Direct sequence spreadspectrum quadrature amplitude modulation
accomplished with a rootraised cosine ﬁlter [20], which has the impulse response
rrc(t) =
sin
π
t
T
c
(1−α)
+4α
t
T
c
cos
π
t
T
c
(1+α)
π
t
T
c
1−
4α
t
T
c
2
. (2.13)
where T
c
is the chip duration and α is the rolloff factor. A causal discrete time coun
terpart of Eq. (2.13) with N samples (N is odd) is
rrc(n) =
sin
π
(1−α)(n−N
c
)
L
+
4α(n−N
c
)
L
cos
π
(1+α)(n−N
c
)
L
π
(n−N
c
)
L
1−
4α(n−N
c
)
L
2
, 0 ≤n ≤N−1. (2.14)
where N
c
=
N−1
2
is the index of the center coefﬁcient, L =
T
c
T
s
=
F
s
F
c
is the oversampling
ratio, T
s
is the sampling interval and F
s
=
1
T
s
is the sampling frequency. Typically
L =
T
c
T
s
is an integer.
When used for pulse shaping ﬁltering in the transmitter and channel ﬁltering at the
receiver, the combination of these two ﬁltering operations corresponds to a raised co
sine (RCOS) ﬁltering [21]. The ideal raisedcosine ﬁlter has two important properties.
It has a bandlimited frequency response given by
RCOS( f ) =
1
F
c
, 0 ≤ f  ≤(1−α)
F
c
2
1
2F
c
1−sin
π
1
αF
c
 f  −
F
c
2
, (1−α)
F
c
2
≤ f  ≤(1+α)
F
c
2
0 ,  f  > (1+α)
F
c
2
,
(2.15)
and an impulse response
rcos(t) =
¸
sin
π
t
T
c
π
t
T
c
¸
¸
¸
sin
απ
t
T
c
1−
2α
t
T
c
2
¸
, (2.16)
which has a causal discrete time equivalence of length N [21] given by
rcos(n) =
sin
π(n−N
c
)
L
π(n−N
c
)
L
cos
πα(n−N
c
)
L
1−
2α(n−N
c
)
L
2
, 0 ≤n ≤N−1, (2.17)
where N
c
=
N−1
2
is the index of the center coefﬁcient (N is odd) and L =
T
c
T
s
is the
oversampling ratio. This impulse response has the property of having a zero value for
any integer value of n =
N−1
2
±kL, 0 < k < −∞. This means that there is no inter
symbol interference (ISI) at the multiples of sampling interval T
s
. The sequence of
raised cosine impulses is presented in Fig. 2.6.
2.4 Performance metrics 11
T 2T 3T 4T 5T 6T 7T 8T 9T 10T 11T 12T 13T 14T 15T 16T 17T
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
Raised cosine impulses
M
a
g
n
i
t
u
d
e
Sampling time
Figure 2.6 ISIfree impulses.
Because neither the transmit ﬁlter nor the receive ﬁlter are ideal rootraised cosine
ﬁlters and neither have inﬁnite length, the ISI value is not zero in practical cases. The
ISI value is one of the performance metrics discussed in next section.
2.4 Performance metrics
Two fundamental metrics of digital communication system performance are bit error
rate (BER) and symbol error rate (SER), which are the probabilities that an error oc
curs when receiving one transmitted bit or one transmitted symbol, respectively. Both
of them are dependent of modulation type, signaltonoise ratio (SNR), channel char
acteristics, detection type etc. [18]. However, when the basestation transmitter is
designed, information on the other signal processing parts of the system is not neces
sarily available, so only the contribution of the subsystem under design to SNR and
BER can be controlled.
In this book, SNR is deﬁned via the error vector magnitude (EVM), which is de
ﬁned to be the root mean square (RMS) deviation of the received symbol given as a
percentage of the symbol magnitude [20]. Actually, this is an RMS noise amplitude
given as a percentage of the symbol magnitude. EVM consists of all noise in the sys
tem, including ISI and quantization noise etc. When designing the transmitter, EVM
12 Direct sequence spreadspectrum quadrature amplitude modulation
as a function of ISI and quantization noise has to be determined and minimized.
EVM
rms
is deﬁned as
EVM
rms
=
σ
2
s
+σ
2
n
S
=
ISI
2
rms
+
σ
2
n
S
2
, (2.18)
where σ
2
s
is the variance of the symbol error generated by the nonidealities of the
combination of the transmit and receive ﬁlters, σ
2
n
is the noise added by the system,
and S is the magnitude of the received symbol.
ISI
rms
is deﬁned as
ISI
rms
=
σ
s
S
=
∑
K
i=−K, i=0
h
tr
(N
c
+iL)
2
h
tr
(N
c
)
, K = f loor
N
c
−1
L
, (2.19)
where h
tr
(n) is the combination of the channel ﬁlters of transmitter and the receiver.
L is the oversampling ratio and N
c
=
N−1
2
is the index of the center coefﬁcient of the
ﬁlter h
tr
(n). N is the number of the ﬁlter coefﬁcients (odd).
In addition to ISI
rms
, the contribution of the current frequency channel to EVM
of the adjacent frequency channels has to be minimized. This means minimization of
the contribution to the additive noise σ
2
n
of the adjacent channel. The amount of this
contribution is given as the adjacent channel power ratio (ACPR
n
) in decibels
ACPR
n
= 10log
10
P
nth_ad j_chan
P
cchan
, (2.20)
or as the adjacent channel leakage power ratio, which is the inverse of ACPR
n
ACLR
n
= 10log
10
P
cchan
P
nth_ad j_chan
, (2.21)
where P
nth_ad j_chan
is the power of n
th
adjacent frequency channel and P
cchan
is the
power of the current signal channel.
ACLR
n
and EVM
rms
are considered to be the key performance metrics of the base
station transmitter throughout the design process described in this book.
Chapter 3
Transmitter structures
The most commonly used (and published) transmitter architectures are direct conver
sion [22], [23], [24], [25], [26], [27] and twostep transmitter [22], [28], [29], [30],
[31], [32], [33], [34], [35], [36], [37]. A two step transmitter can be realized either
with an analog or digital intermediate frequency (IF) part.
Direct conversion and twostep transmitter structures are usually used in the ampli
tude modulators, whereas the frequency synthesizer based transmitters [38], [39], [40],
[41], [42], [43] are used in narrow band phase and frequency modulators.
Two transmitter types used with the power ampliﬁer (PA) linearization techniques
[44], [45] are also described, because the linearization techniques require that the
signals are presented in a different format at the IF frequency compared to the feed
forward or lookup table methods[46], [47] in which the signal at the IF is still basically
the sinusoidal carrier multiplied by the ﬁltered data.
3.1 Direct conversion transmitter
The principle of the direct conversion transmitter is presented in Fig. 3.1. In direct
90
o
i(t)
q(t)
cos( ω ) t
rf
D/A
D/A
Digital
baseband
signal
processing
s
t
(t) = sin( i(t)cos( ω ) t
rf
q(t) ω ) t
rf
+
Figure 3.1 Direct conversion transmitter.
conversion transmitters, the bandlimited baseband signals are converted directly up to
the radio frequency ω
r f
with inphase and quadrature carriers. The bandpass ﬁlter
14 Transmitter structures
after the signal summation is used to suppress the outofband signals generated by the
harmonic distortion of the carrier. The structure of this kind of transmitter is quite sim
ple; however, it suffers from the following drawback. The strong signal at the output
of the power ampliﬁer may couple to the local oscillator (LO), which is usually a volt
age controlled oscillator, causing the phenomenon that is known as injection pulling
[22], [48]. This means that the frequency of the local oscillator is pulled away from
the desired value. The severity of the injection pulling is proportional to the difference
between the frequency of the local oscillator and the frequencies at the output of the
PA. By taking advantage of that, the problem of injection pulling can be alleviated by
using an offset LO directconversion structure (Fig. 3.2). In this structure the carrier
90
o
i(t)
q(t)
D/A
D/A
Digital
baseband
signal
processing
cos( ) t ω
rf
−ω
if
( )
cos( ω ) t
if
s
t
(t) = sin( i(t)cos( ω ) t
rf
q(t) ω ) t
rf
+
Figure 3.2 Offset LO directconversion transmitter.
signal is formed by mixing two lower frequency signals. An additional bandpass ﬁlter
is needed to ﬁlter away the undesired carrier at the frequency ω
r f
−2ω
i f
.
3.2 Twostep transmitter
The injection pulling can also be avoided by using the twostep transmitter presented
in Fig. 3.3. The two (or multiple) step transmitter can be considered as a dual of the
superheterodyne receiver [22]. In this structure, the baseband data is ﬁrst upconverted
i(t)
q(t)
D/A
D/A
Digital
baseband
signal
processing
cos( ω ) t
if
90
o
cos( ) t ω
rf
−ω
if
( )
s
t
(t) = sin( i(t)cos( ω ) t
rf
q(t) ω ) t
rf
+
Figure 3.3 Twostep transmitter.
to the intermediate frequency ω
i f
and then to the desired radio frequency ω
r f
. The two
step transmitter has two advantages. First, the quadrature modulation is performed at a
ﬁxed lower frequency resulting in better matching between inphase and quadrature (I
and Q) carriers, which in turn diminishes the crosstalk between I and Q data streams.
Second, the additional attenuation of the adjacent channel spurs and noise may be
achieved by using a bandpass ﬁlter at the IF. The drawback is that the stop band
3.3 Phase modulating synthesizers 15
attenuation at the RF frequency has to be larger than in a direct conversion transmitter
because the signal component at the frequency ω
r f
−2ω
i f
has the same power as the
desired sideband.
3.3 Phase modulating synthesizers
When the narrow band phase or frequency modulation is performed, the phase modu
lating synthesizer is often used [38], [39], [40], [41]. The synthesizer can be either an
analog one, such as a phase locked loop (PLL) or a direct digital synthesizer (DDS),
often also called a numerically controlled oscillator (NCO) . The PLLbased modula
tor is presented in Fig. 3.4. This kind of transmitter generates the modulated carrier
H(s)
divider
∆Σ
Mod
Pulse shaping
data
Phase
Comp.
ref
ω
ω
rf
Figure 3.4 PLL based modulator.
by controlling the frequency divider of the PLL with a pulse shaped ∆Σmodulated
data stream, thus modulating either phase or frequency. The phase comparator detects
the phase difference between the reference oscillator and the output of the divider and
tunes the voltagecontrolled oscillator (VCO) to minimize the average phase differ
ence, thus producing a phase modulated carrier at radio frequency (RF). The usable
bandwidth of the data is limited by the bandwidth of the loop ﬁlter H(s), preventing
the usage of this kind of transmitter in wideband systems. This kind of transmitter is
used in systems such as GSM [39], [40] or Bluetooth [49].
Instead of using an analog frequency synthesizer, the phase modulator can also be
realized with a digital frequency synthesizer [50], [43], [42]. The basic principle of
the digital phase modulator is presented in Fig. 3.5. With this kind of structure, both
frequency and phase synthesizers can be realized (the data could also be added to the
”frequency control” shown in Fig. 3.5 ). They are often used in the same kind of
applications as their analog counterparts, but they do not suffer from loop ﬁlter band
width limitations like the PLL based synthesizers do. Because of this, it has become
increasingly interesting to implement multimode basestation transmitters, where the
16 Transmitter structures
Phase
accumulator
Pulse
shaping
Cosine
ROM
Sine
ROM
DAC
Frequency
control
Data
Figure 3.5 Digital phase modulation.
phase or frequency modulation is added to the digital frequency synthesizer used for
the digital QAM modulator enabling the same transmitter to be used in multiple com
munications standards such as GSM, EDGE, and WCDMA. [17].
3.4 Constant envelope transmitters for power ampliﬁer
linearization
The PA linearization techniques described in this section require special signal decom
position at the baseband or at the IF frequencies. They can therefore be considered as
separate transmitter architectures, whereas techniques such as feedforward [46] and
lookuptablebased methods [47] are basically conventional QAM transmitters with
linearizing predistortion.
With constant envelope signals, it is possible to use nonlinear powerefﬁcient (class
C, D, E or F) ampliﬁers because the constant envelope signals produce less distortion
in the signal frequency band than the signals with a varying envelope [22]. Constant
envelope signals are, for example, phase or frequency modulated signals, which have,
however, a poor spectral efﬁciency. In order to increase the spectral efﬁciency, modu
lation techniques in which both the amplitude and phase are varying (such as the mul
tilevel QAM) have to be used. Difﬁculties arise when the average transmitted power is
much lower than the maximum peak power.
The ratio of the peak power to average power is called the crest factor. A high crest
factor causes the following problems. First, it is not possible to use a nonlinear (power
efﬁcient) PA, because the distortion destroys the signal integrity and detection of the
information that is coded to the amplitude becomes more difﬁcult or impossible. Also,
the distortion of the nonconstant envelope signal causes spectral regrowth (widens
the signal spectrum) and therefore disturbs the adjacent signal bands [51]. Even if
the distortion problem is solved by using a more linear (class A or AB) ampliﬁer, the
efﬁciency is even further reduced because the ampliﬁer has to be biased according to
the maximum signal amplitude.
3.4 Constant envelope transmitters for power ampliﬁer linearization 17
Both of the methods described in this section are based on the decomposition of the
IF signal. The IF signal is decomposed in the constant envelope components, which
allows the usage of a nonlinear power ampliﬁer.
3.4.1 Envelope elimination and restoration
The envelope elimination and restoration (EER) [44], [52] transmitter is presented in
Fig. 3.6. The relationship between the general amplitude modulation and the decom
PA
A(t)
A(t)
Vdd
Vdd adj.
cos( ωt φ
d
(t))
−
cos( ωt φ
d
(t))
−
Figure 3.6 Envelope elimination and restoration.
posed presentation of Fig. 3.6 is
S
t
(t) = i (t)cos(ωt) +q(t)sin(ωt)
= A(t)cos(ωt −φ
d
(t)), (3.1)
where
A(t) =
i (t)
2
+q(t)
2
φ
d
(t) = arctan
q(t)
i (t)
. (3.2)
The cos(ωt −φ
d
) term in Eq. (3.1) has a constant envelope and can be ampliﬁed with
a nonlinear PA. The amplitude information A(t) is added to the signal by controlling
the supply voltage of the ampliﬁer.
The main weakness of this method is that it requires good matching between the
amplitude branch and the carrier branch.
3.4.2 LINC transmitter
LINC is an abbreviation meaning linear ampliﬁcation with nonlinear components [45],
[53] (a.k.a. as an outphasing method [54]). The LINC transmitter is presented in Fig.
3.7.
18 Transmitter structures
PA
PA
A(t)cos( ωt ) − φ
d
(t)
cos( ωt ) φ
d
(t) φ
dc
(t) − +
A
max
2
cos( ωt ) φ
d
(t) φ
dc
(t) − −
A
max
2
Figure 3.7 LINC power ampliﬁcation.
The input signals of the power ampliﬁers are formed by further expanding Eq.
(3.1), resulting in
s(t) = A(t)cos(ωt −φ
d
(t))
= A
max
cos(φ
dc
)cos(ωt −φ
d
(t))
=
A
max
2
cos(ωt +φ
dc
−φ
d
(t)) +
A
max
2
cos(ωt −φ
dc
−φ
d
(t)), (3.3)
in which
A(t) =
i (t)
2
+q(t)
2
A
max
= max(abs(A(t)))
φ
dc
(t) = arccos
A(t)
A
max
= arccos
¸
i (t)
2
+q(t)
2
A
max
¸
. (3.4)
The main weakness in the LINCrealizations, as in the EER method, is the matching
between the signal paths in the analog domain. If the matching is not perfect, the
quality of the signal is degraded. Also, the bandwidth of the signal components is
increased when compared to the original signal, and therefore a high sampling rate is
usually required for the DSP. In addition, the lossless summation of highpower signals
is very difﬁcult, resulting in efﬁciency degradation.
3.5 Digital QAM transmitter
The digital QAM transmitter is presented in Fig. 3.8. The digital signal processing
part of the transmitter usually consists of digital pulse shaping ﬁlters and a digital
frequency synthesizer, which are discussed in Chapters 4 and 5. In order to make
digital modulation possible, the sampling rate conversion (interpolation) between the
data input sampling rate and the sampling rate of the frequency synthesizers is needed.
3.5 Digital QAM transmitter 19
i(t)
q(t)
D/A
Digital
baseband
signal
processing
cos( ω ) t
if
90
o
s
t
(t) = sin( i(t)cos( ω ) t
rf
q(t) ω ) t
rf
cos( ) t ω
rf
−ω
if
( )
+
Figure 3.8 Digital QAM transmitter.
This also requires ﬁltering, which is discussed in more detail in Chapter 4.
The main beneﬁt of the digital QAM transmitter is that the modulation does not suf
fer from any kind of physical accuracy limitations or distortion that may occur when an
analog multiplication is used to produce the QAM signal. Another beneﬁt is that there
is only one signal branch in the analog domain, eliminating the gain and phase im
balance problems between I and Q branches. When used in multicarrier transmitters,
the digital QAM has the beneﬁt of lossless signal addition and mismatchfree perfor
mance. The digital QAM also has all the beneﬁts that DSP provides. For example, the
frequency resolution of the digital frequency synthesizer can be selected arbitrarily.
This allows the frequencies of the carriers to be freely selectable within the frequency
band allocated to the system. It is also possible to implement several types of signal
enhancement techniques with digital signal processing, including, but not limited to,
amplitude and phasedistortion compensation and powerampliﬁer linearization with
predistortion techniques. The main limitations of the usage of the digital QAM are
the high power dissipation, which makes it unusable in portable devices, and the accu
racy of the D/A converter. Digital transmitters are mainly used in systems like cable
modems and basestation transmitters, in which the large power dissipation is not a
problem [37], [36], [35].
Chapter 4
Resourceefﬁcient digital ﬁlter
design
Resourceefﬁcient DSP generally becomes a topic when the system size integrated on
a single chip increases. The main resources that we are dealing with are power, speed
and area. It can be shown that each of these can be traded off against each other, hence
it is only a question of which one of these properties is the most important one in a
speciﬁc design case. For the mobile applications, it is almost always power, then area.
For the nonportable application, the power optimization is less important, although
not meaningless. Less power means the possibility of integrating more on a single chip
without meltingup the package or without needing to install a cooling fan.
Speed of computation is often considered a ﬁgure of merit when speaking about
DSP chips. The fact is that speed can be increased by using such techniques as pipelin
ing and parallelism, that is, by increasing the chip area. The same techniques may also
be applied in order to achieve lowpower performance. However, increasing the area
means increasing the price of the chip.
In this chapter, some techniques for a resourceefﬁcient ﬁlter design are discussed.
It should be kept in mind that, in the design described in Section 7.1, the order of pri
orization of the resources is ﬁrst area, then power. The computation speed is ﬁxed by
the system speciﬁcation, so the special methods for highspeed designs are not con
sidered. The topdown method is used to describe the techniques of the areaefﬁcient
ﬁlter design.
22 Resourceefﬁcient digital ﬁlter design
4.1 Filter design algorithms
4.1.1 Pulse shaping ﬁlter design algorithm
The pulse shaping ﬁlter design has two main objectives: minimization of the inter
symbol interference (ISI) and maximization of the adjacent channel leakage power
ratio (ACLR). Most of the algorithms used for the ﬁnite impulse response (FIR) ﬁlter
design, such as the methods introduced in [55], [56], [57] and [58], are suitable for
only the stopband attenuation maximization (or equiripple ﬁlter design) and does not
take ISI into account.
One way to design ﬁlters that have at least some kind of ISI properties is to use
the sampled impulse response of the rootraised cosine ﬁlter (Eq. (2.17)) as ﬁlter co
efﬁcients. However, the performance is far from ideal, and the stopband attenuation
is usually poor with a small number of coefﬁcients. This problem may be alleviated
by using some window function, such as Kaiser, but this worsens ISI performance.
Windowing may also widen the pass band, which is not desirable. With the windowing
method, the stopband attenuation and ISI may be traded off against each other, but
usually the number of coefﬁcients for the practical values of ACLR and ISI becomes
quite high. A better method for ﬁnding the pulse shaping ﬁlter coefﬁcients was de
scribed in [6], which is based on Lagrange optimization. The Lagrange optimization
method is also used in [59] to design ﬁlters or multirate systems.
The method goes as follows. An ideal rootraised receive ﬁlter is approximated
with h
r
(n) with length I (odd). We try to design a transmit ﬁlter h
t
(n) of length K
in such a way that ISI
rms
is minimized and ACLR is maximized. Both ﬁlters have the
same oversampling ratio L. The combination of these two ﬁlters is the time domain
convolution of their impulse responses
h
tr
(n) =
K−1
∑
i=0
h
t
(i)h
r
(n−i) n = 0. . . N−1, N = K+I −1
= h
T
t
S
n
h
r
, (4.1)
in which S
n
is a I ×K convolution matrix with elements
sn
a,b
= 1, b = n+2−a, 1 ≤b ≤K 1 ≤a ≤I,
sn
a,b
= 0 otherwise. (4.2)
Next ISI
rms
has to be deﬁned as a function of h
t
(n). ISI
rms
can be presented in
4.1 Filter design algorithms 23
matrix form
ISI
2
rms
=
∑
M
i=−M, i=0
h
T
t
(S
N
c
+iL
h
r
)(S
N
c
+iL
h
r
)
T
h
t
h
T
t
(S
N
c
h
r
)(S
N
c
h
r
)
T
h
r
, M = f loor(
N
c
−1
L
), N
c
=
N−1
2
=
h
T
t
AA
T
h
t
h
T
t
A
c
A
T
c
h
t
, (4.3)
where
A =
M
∑
i=−M,i=0
S
N
c
+iL
h
r
(4.4)
and
A
c
= S
N
c
h
r
, (4.5)
in which N
c
=
N−1
2
(N odd) is the index of the center coefﬁcient of the combination
of transmit and receive ﬁlters. Now, we have a matrix presentation for the normalized
ISI.
Next the matrix equations for the passband and stopband power of the transmit
ﬁlter h
t
(n) are derived. The amplitude frequency response of the ﬁlter may be written
as
H
t
( f ) =
K−1
∑
n=0
h
t
(n)e
−j
2πf n
F
s
=
K−1
∑
n=0
h
t
(n)
cos
2πf n
F
s
− j sin
2πf n
F
s
, (4.6)
where F
s
is the sampling frequency. The power transfer function may then be written
as
P( f ) = H
t
( f )
2
=
K−1
∑
i=0
K−1
∑
k=0
h
t
(i)h
t
(k)e
−j
2πf i
F
s
e
j
2πf k
F
s
(4.7)
=
K−1
∑
i=0
K−1
∑
j=0
h
t
(i)h
t
( j)cos
2πf (i −k)
F
s
− j
K−1
∑
i=0
K−1
∑
k=0
h
t
(i)h
t
(k)sin
2πf (i −k)
F
s
.
Because sin(−x) =−sin(x), the term
j
K−1
∑
i=0
K−1
∑
k=0
h
t
(i)h
t
(k)sin
2πf (i −k)
F
s
(4.8)
in Eq. (4.8) equals zero, and the power transfer function of the transmit ﬁlter h
t
(n)
24 Resourceefﬁcient digital ﬁlter design
may be written as
P( f ) = H
t
( f )
2
=
K−1
∑
i=0
K−1
∑
k=0
h
t
(i)h
t
(k)cos
2πf (i −k)
F
s
. (4.9)
Now we may discover the integrated power on some passband from −F
pb
to F
pb
.
E
p
=
Z
F
pb
−F
pb
P( f )df
=
K−1
∑
i=0
K−1
∑
k=0
h
t
(i)h
t
(k)
F
s
π(i −k)
sin
2πF
pb
(i −k)
F
s
, (4.10)
and for stop bands from
−F
s
2
to F
sb
and F
sb
to
F
s
2
E
s
=
Z
−F
sb
−
F
s
2
P( f )d f +
Z F
s
2
F
sb
P( f )df
=
K−1
∑
i=0
K−1
∑
k=0
h
t
(i)h
t
(k)
F
s
π(i −k)
sin(π(i −k)) −sin
2πF
sb
(i −k)
F
s
. (4.11)
We may write the passband power in the matrix form
E
p
= h
T
t
P
p
h
t
(4.12)
in which P
p
is a K×K square matrix with elements
pp
i,k
=
2F
pb
, when i −k = 0
F
s
π(i−k)
sin
2πF
pb
(i−k)
F
s
otherwise.
(4.13)
Similarly, for the stopband power we get
E
s
= h
T
t
P
s
h
t
, (4.14)
in which P
s
is a K×K matrix with elements
ps
i,k
=
F
s
−2F
sb
, when i −k = 0
−
F
s
π(i−k)
sin
2πF
sb
(i−k)
F
s
otherwise.
(4.15)
Now, when we have the matrix equations for ISI
2
rms
, E
p
and E
s
, we may write the
4.1 Filter design algorithms 25
Lagrangian cost function to be maximized
L(h
t
, λ) = h
T
t
P
p
h
t
−ah
T
t
P
s
h
t
−bh
T
t
AA
T
h
t
+λ
h
T
t
A
c
−1
, (4.16)
in which the a and b are the weight factors for the stop bandpower and the ISI
2
rms
. λ
rule sets the value of the center coefﬁcient of h
tr
(n) to be one. By taking the partial
derivatives and setting them to zero we get
∂L(h
t
, λ)
∂h
t
= 2P
p
h
t
−2aP
s
h
t
−2bAA
T
h
t
+λA
c
= 0 (4.17)
∂L(h
t
, λ)
∂λ
= h
T
t
A
c
−1 = 0. (4.18)
By setting
Q = 2P
p
−2aP
s
−2bAA
T
(4.19)
and solving Eqs. (4.17) and (4.18) we obtain
h
t
=
Q
−1
A
c
(Q
−1
A
c
)
T
A
c
, (4.20)
which is the Lagrange optimized transmitter ﬁlter.
It should be noted that the ﬁlter that was used for the receiver may also include
the combination of all ﬁlters in the transmitter after the pulse shaping ﬁlter. With this
method, the effect of the ﬁlters after the pulse shaping ﬁlter in the transmitter may be
compensated.
The main shortcoming of this algorithm is that the effect of the weighting factors a
and b has to discovered by trial and error. Results of different ﬁlter design methods are
compared in Table 4.1. The number of the ﬁlter coefﬁcients is 37 for each ﬁlter.
Table 4.1 Comparison of ﬁlter design methods.
Method ACLR ISI
Truncation 45.30dB 59.21dB
Window with Kaiser, β = 4 36.15dB 40.07dB
Lagrange 73.38dB 45.08dB
Rootraised cosine with 1001 coefﬁcients 71.22dB 106.10dB
In simulations, the oversampling ratio is 2 and the sample frequency is normalized
to that. The pass band is deﬁned to be from 0 to 0.61Hz and the stop band (adjacent
channel) from 0.61Hz to 1Hz. It can be seen that the ACLR value of the ﬁlter de
signed with the window method suffers from the increased width of the pass band. The
frequency responses of the ﬁlters are presented in Fig. 4.1.
26 Resourceefﬁcient digital ﬁlter design
0.25 0.5 0.61 0.75
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Comparison of filter design methods
R
e
l
a
t
i
v
e
p
o
w
e
r
[
d
B
]
Normalized frequency
Truncation
Window
Lagrange
Ideal
Figure 4.1 Frequency responses of the ﬁlters designed with different design methods.
4.1.2 Halfband ﬁlters for interpolation
When sampling rate conversion takes place, digital ﬁlters are needed. Filters used in
sampling rate conversion must fulﬁll two criteria. The ﬁrst and most important is that
they have to ﬁlter out the image band in the case of interpolation, or the aliasing band
in the case of decimation. The second is that they should be as simple as possible.
When we have to interpolate or decimate signals with a reasonably wide bandwidth
compared to sampling frequency, the usage of comb ﬁlters [60], [61] is not preferable
because they introduce droop on their pass band. The second best approach compared
to comb ﬁlters is to interpolate in steps of two if possible. This is because the number
FIR ﬁlter coefﬁcients needed for the ﬁltering has an approximate dependency [58]
N
∼
= K
F
s
∆F
, (4.21)
where K is a factor depending on the stopband and passband ripple characteristics
of the ﬁlter, F
s
is the sample frequency and ∆F is the width of the transition band. In
addition, when interpolating by two, halfband ﬁlters may be used. Halfband ﬁlters
have the center of their transition band at the quarter of the sampling frequency. They
can be designed with any of the ﬁlter design algorithms described in, for example,
[58]. However a shortcut for their design has been introduced in [62]. Halfband ﬁlters
4.2 Mapping the ﬂoating point ﬁlter coefﬁcients to canonic signed digit format 27
have the property that every other of their coefﬁcients except the center coefﬁcient (odd
N) has zero value. This is expandable to s.c. Φband ﬁlters [63], in which every L
th
coefﬁcient is zero except the center one [62]. Φband ﬁlters are ﬁlters that have L−1
don’t care bands. The halfband ﬁlters that are used in the transmitter of Chapter 7 are
designed with the Least Squares error minimization algorithm [58] and by using the
”trick” described in [62].
4.2 Mapping the ﬂoating point ﬁlter coefﬁcients to canonic
signed digit format
In the previous section, the method for efﬁcient ﬁlter design for ﬂoating point presen
tation of the ﬁlter coefﬁcients was presented. Because the ﬂoating point computation
is quite tricky to perform on the silicon, it is preferable to use ﬁxed point presentations
of the ﬁlter coefﬁcients. Moving from ﬂoating point to the ﬁxed point presentation de
grades the accuracy of the presentation and introduces error into the ﬁltering operation.
Multiplication of two ﬁxed point number consumes a lot more power and area on
silicon when compared to summation. In the case when the ﬁlter has constant coefﬁ
cients it is preferable to use a signed digit (SD) presentation for the ﬁlter coefﬁcients
[64]. In SD presentation, the ﬁlter coefﬁcient is presented as sums and differences of
powers of two
h(n) =
∞
∑
i=−∞
c
ni
2
i
, c
ni
∈ {−1, 0, 1}. (4.22)
In digital ﬁlters, it is convenient to normalize the maximum value of the ﬁlter coef
ﬁcient so that the maximum power of two is zero. It is also possible to present the ﬁlter
coefﬁcient only with some limited accuracy by ﬁxing the minimum value of i. This
leads to the approximation of h(n)
h
sd
(n) =
0
∑
i=−p
c
ni
2
i
, c
ni
∈ {−1, 0, 1}. (4.23)
When the number is presented with a minimum number of nonzero digits, the
presentation is said to be a minimum signed digit (MSD) presentation. There can be
multiple MSD representations for a single number, but there is only one MSD presen
tation in which there is no nonzero digits in parallel. This representation is called the
canonic signed digit presentation (CSD). For example 0.75, in decimal notation can
be presented as ”1 0 1” or ”0 1 1” in signed digit presentation, of which ”1 0 1” is
CSD presentation. The beneﬁt of the SD representations is that the multiplication op
28 Resourceefﬁcient digital ﬁlter design
eration can be realized by using only adders/subtracters and shift operations that can
be realized with hardwired shifts.
Several algorithms have been presented for mapping the ﬂoating point or regular
two’s complement presentation to the CSD presentation [65], [66], [67], [68], [69]. In
the design described in Chapter 7, the modiﬁcation of the method presented in [67]
was used. The method was modiﬁed in order to trade off ACLR and ISI rather than the
peak amplitude ripple and ISI. This is because the parameter to be optimized is the ad
jacent channel power relative to the channel power, not the ripple of the power transfer
function. The equiripple design algorithms usually give poorer power attenuation on
the stop band than the ﬁlters that have been designed in the sense of the least squares
stopband. Almost same kind of method was used in [70].
4.3 Efﬁcient FIR ﬁlter structures
Once the ﬁlters have been converted to the SD representation, the further area and
power reductions may be achieved by rearranging the computation on the silicon chip.
In this chapter, a couple of well known methods are described.
4.3.1 Polyphase FIR ﬁlters in sampling rate converters
The basic operations in sampling rate conversion are converting the sampling rate up
wards (i.e. interpolation) and downwards (i.e. decimation). The interpolation consists
of upsampling followed by ﬁltering, while the decimation consists of ﬁltering followed
by downsampling. The decimation and interpolation and their efﬁcient realizations are
described in the following paragraphs.
The upsampling operation for the data sequence x(n) may be described with
x
i
(n) =
x
n
L
,
n
L
∈ Z
0 otherwise,
(4.24)
which means that L−1 zeros are inserted between the samples. Equation (4.24) can
also be presented with discrete Fourier series as
x
i
(n) =
1
L
L−1
∑
l=0
x
n
L
e
j
2πnl
L
, (4.25)
which is a suitable format when, for example, analyzing upsampling in the frequency
domain.
4.3 Efﬁcient FIR ﬁlter structures 29
Downsampling may be described with
x
d
(n) = x(nM), (4.26)
which means that only every M
th
sample of x(n) is included in x
d
(n).
The effects of the upsampling in the frequency domain can be discovered by cal
culating the Ztransform of x
i
(n) and by evaluating it on the unit circle (i.e. by substi
tuting Z = e
j
2πf
F
s
), resulting in
X
i
( f ) =
1
L
L−1
∑
l=0
L(N−1)
∑
n=0
x
n
L
e
j
2πnl
L
e
−j
2πf n
LF
s
=
1
L
L−1
∑
l=0
N−1
∑
b=0
x(b)e
−j
2πb
F
si
L
f −l
F
si
L
=
1
L
L−1
∑
l=0
X( f −l
F
si
L
)
=
1
L
L−1
∑
l=0
X( f −lF
s
) = X( f ) (4.27)
where F
s
is the sampling frequency before interpolation,
n
L
= b and LF
s
= F
si
. This
means that the spectrumis the same, although the sampling frequency has been changed,
meaning that there are unwanted images between the new sampling frequency and the
original signal band. The effects in the frequency domain are presented in Fig. 4.2.
F
s
F
s
0
f
2 L F
s
F
s
F
s
0
f
2 L F
s
Images
Figure 4.2 Effects of interpolation in the frequency domain.
The images should be ﬁltered out after upsampling because they contain redundant
30 Resourceefﬁcient digital ﬁlter design
information, which may, for example contaminate signals on the adjacent frequency
bands.
For downsampling, x
d
(n) in the frequency domain may be written as
X
d
( f ) =
N−1
M
∑
n=0
x(nM)e
−j
2πn f
F
sb
=
N−1
∑
b=0
1
M
M−1
∑
l=0
x(b)e
j
2πbl
M
e
−j
2πb f
F
s
=
1
M
M−1
∑
l=0
N−1
∑
b=0
x(b)e
−j
2πb
F
s
(f −l
F
s
M
)
=
1
M
M−1
∑
l=0
X( f −lF
sd
), (4.28)
in which b = nM and F
sd
=
F
s
M
. This means that the spectrum after decimation contains
aliased components from the frequency bands centered l
F
s
M
, l = 1. . . M−1. In order to
avoid aliasing (Fig. 4.3), the signal should be bandlimited before decimation (i.e. the
signal power of the aliasing bands should be zero).
0
f
F
s
0
f
F
s
F
s
M
2 F
s
M
Figure 4.3 Effects of decimation in the frequency domain.
Interpolation and decimation ﬁlters can be realized efﬁciently by using socalled
polyphase decomposition. Polyphase decomposition is based on identities presented
in Fig. 4.4 and holds for every L and M [58]. The polyphase decomposition of the
interpolation ﬁlter and one possible realization of it are presented in Figs. 4.5 and
4.3 Efﬁcient FIR ﬁlter structures 31
L H( Z ) Z
L
H( )
L
H( Z ) Z H( )
M
M
M
Figure 4.4 Identities for the order of ﬁltering and up/down sampling.
4.6. The decomposed ﬁlter for decimation and one possible implementation of it are
H (Z)
0
H (Z)
1
X(Z)
F
s
L
L
Y
i
(Z)
LF
s
Z
L Z
L−1
H ) (Z
−(L−1)
−1
Figure 4.5 Polyphase decomposition of the interpolation ﬁlter.
presented in Figs. 4.7 and 4.8.
The advantage of the polyphase decompositions is that the computation can al
ways be performed with the lower clock frequency, resulting in either the possibility
of reducing supply voltage in order to minimize power dissipation or the use of the
pipelining/interleaving (P/I) technique in order to minimize the area [71].
In the case of FIR ﬁlters with symmetrical or anti symmetrical coefﬁcients (linear
phase FIR ﬁlters), the symmetry of the coefﬁcients can be exploited in order to further
reduce the area. The maximum number of symmetrical subﬁlters in sampling rate
conversion with different ﬁlter tap and samplingrate combinations are listed in Table
4.2 [72].
4.3.2 Efﬁcient realizations of FIR ﬁlters
In this section, the two main structures of digital FIR ﬁlters, namely the direct form
and the transposed direct form, are presented. The pros and cons of both of them are
32 Resourceefﬁcient digital ﬁlter design
H (Z)
0
H (Z)
1
L−1
H ) (Z
X(Z)
Y
i
(Z)
F
s
LF
s
Figure 4.6 One possible realization of polyphase decomposed interpolation ﬁlter.
X(Z)
F
s
Y
i
(Z)
H (Z)
1
L−1
H ) (Z
Z
−(L−1)
H (Z)
0
Z
−1
M
M
M
F
s
M
Figure 4.7 Polyphase decomposition of the decimation ﬁlter.
Table 4.2 Maximum number of symmetrical subﬁlters.
Odd number of coefﬁcients Even number of coefﬁcients
Odd L or M 1 1
Even L or M 2 0
considered and some methods for reducing the amount of hardware in ﬁlter realizations
are also discussed.
4.3 Efﬁcient FIR ﬁlter structures 33
X(Z)
F
s
Y
i
(Z)
H (Z)
1
L−1
H ) (Z
H (Z)
0
F
s
M
Figure 4.8 One possible realization of the polyphase decomposed decimation ﬁlter
4.3.2.1 Direct form structure
The folded direct form FIR ﬁlter structure is presented in Fig. 4.9. Folding is only
Z
−1
Z
−1
Z
−1
Z
−1
X(n)
Y(n)
Figure 4.9 Folded regular direct form FIR ﬁlter structure.
applicable when the FIR ﬁlter has a linear phase, i.e. the coefﬁcients are either sym
metrical or antisymmetrical relative to the center coefﬁcient. Applications where the
34 Resourceefﬁcient digital ﬁlter design
coefﬁcients may not be symmetrical are, for example, subﬁlters in polyphase decom
positions and in the predistortion ﬁlters for phase error correction.
In the folded regular direct form, the number of bits needed in the delay elements
are deﬁned by the number of input bits rather than the required word length of the ﬁlter,
which may lead to a reduced amount of hardware. Another advantage of the transposed
direct form is that, if the ﬁlter coefﬁcients are updated (for example, in programmable
ﬁlters), the effect is seen immediately at the ﬁlter output. On the other hand, the delay
path from the registers to the output can be straightforwardly pipelined if the latency is
allowed [72].
4.3.2.2 Transposed direct form structure
The transposed direct form structure is presented in Fig. 4.10. Basically the amount of
Z
−1
Z
−1
Z
−1
Z
−1
X(n)
Y(n)
Figure 4.10 Folded transposed direct form FIR ﬁlter structure.
hardware is almost the same in direct form and transposed direct form FIR ﬁlters. The
beneﬁt of the transposed direct form is that the maximum delay path in this structure
is shorter compared to the regular direct form, resulting in faster performance. Also,
the redundant arithmetic addition, such as carrysave addition, may be applied to the
adders between the register stages resulting in increased speed. This, however, requires
a doubling of the register elements, because the signal is divided into carry and sum
signals and an additional adder before the output to sum up the carry and sum signals.
4.3 Efﬁcient FIR ﬁlter structures 35
Transposed direct form ﬁlters can also be pipelined, but it may be more difﬁcult than
in a regular direct form structure, at least in the case of pipelining a single adder stage.
The subexpression sharing method can be applied to both of the structures, reduc
ing the amount of hardware effectively [73],[74], [75].
4.3.2.3 Pipelining/interleaving technique
The pipelining/interleaving (P/I) technique [71] is applicable when, for example, the
same ﬁltering operation is to be performed for several independent data streams. In
stead of using K times the same hardware, parallel data streams are interleaved in time,
and the computation is made with a K times higher clock frequency. Finally, the data
streamis deinterleaved either in K or some other amount of parallel data streams. When
having K parallel data streams to be ﬁltered with the same ﬁlter, the same hardware for
ﬁlter coefﬁcients may be used. However, register stages has to be added to the ﬁlter.
Instead of one delay element we have to have K delay elements. The P/I structure of
the polyphase interpolation ﬁlter is presented in Fig. 4.11. The main drawback of this
K*F
K pcs
F
IN
K:1
2:N
N pcs
2*K*F/N
OUT
Inter−
leaver 1
H (Z
K
)
H
2
(Z
K
)
De−inter
leaver
Figure 4.11 Pipelined/Interleaved polyphase ﬁlter.
method is that the additional register stages increase the power consumption, because
the amount of the registers is the same as in parallel realization, but the clock frequency
is higher.
4.3.2.4 Reduction of the sign bit load
In the ﬁlters that are realized with the SD coefﬁcients, the sign bit loading due to
the sign bit extension in shift and add operations may become a problem. This is
because the load at the sign bit position may slow down the circuit or it may require a
large amount of buffering. The loading is avoided by the usage of the constant vector
addition method proposed in [72]. In this method, the sum of sign bit extension vector
is computed a priori and added to the output of the ﬁlter. In this case, the sign bit
extension does not have to be performed inside the ﬁlter, and the extensive loading of
the sign bit is avoided.
36 Resourceefﬁcient digital ﬁlter design
4.3.2.5 Word length effects and scaling
In order to get the best possible trade off between the signaltonoise ratio and ACLR
at the output of the digital ﬁlter and the amount of hardware, the minimum accuracy
needed has to be found. Basically there are three sources of noise due to the ﬁnite
precision arithmetic in the FIR ﬁlter. The ﬁrst source is the quantization of the result
of the multiplication. The second is the noise due to the truncation at the ﬁlter output,
and the third is the noise due to the overﬂows.
The variance of the quantization noise due to the ﬁnite internal word length is
σ
2
n
=
∆
2
12
=
2
−2B
3
, (4.29)
where ∆ is 2
−B+1
, and B is the internal word length of the ﬁlter. It is assumed here that
the computation is made in a 2’s complement format and that the most signiﬁcant bit
(sign bit) has the weight of 2
0
= 1, so the absolute value of the number is less than, or
equal to, 1. Assuming an N tap transposed form ﬁlter, the noise variance at the ﬁlter
output due to the internal word length quantization is
σ
2
iwl
= Nσ
2
n
. (4.30)
If we want to keep the noise added by the ﬁltering operation below the desired noise
level indicated by B
o
output bits, the internal word length of the ﬁlter should be
B ≥B
o
+
ln(N)
2ln(2)
≈B
o
+0.721ln(N). (4.31)
The noise variance added due to the quantization at the ﬁlter output is
σ
2
op
=
∆
2
o
3
=
2
−2B
o
3
, (4.32)
in which ∆
o
=2
−B
o
+1
and B
o
is the number of bits at the ﬁlter output after quantization.
This means that quantization at the ﬁlter output has less effect on the signaltonoise
ratio than shortening the internal word length of the ﬁlter. In the case of cascaded ﬁlter
stages, only minor hardware savings can be achieved by truncation of the ﬁlter output.
The third source of noise is the noise generated by overﬂows in the ﬁlter. The
overﬂows of the ﬁlter may be avoided if the internal word length of the ﬁlter is selected
so that the maximum presentable number in the ﬁlter is
M
out put
= M
input
N−1
∑
n=0
h(n) , (4.33)
4.3 Efﬁcient FIR ﬁlter structures 37
where M
input
is the maximum value at the ﬁlter input [76]. However this usually gives
overpessimistic values for the bandlimited signals. Other methods for discovering the
dynamic range of the signal are presented in [76],[77] and [78], but they do not guar
antee an overﬂowfree performance. The noise due to the overﬂows may be minimized
by using saturating logic in the adders [78]. This leads to clipping instead of overﬂows,
which reduces remarkably the generated noise. Because the maximum output value is
dependent on the statistics of the signal, the number of internal bits needed can also be
approximated with simulations, while the saturation logic may be applied in order to
minimize the effect of occasional overﬂows.
Chapter 5
Methods for direct digital
frequency synthesis and
modulation
The core of the digital QAM modulator is the direct digital synthesizer (DDS). The
most often used methods for the direct digital frequency synthesis are the lookup table
(LUT) based frequency synthesis methods and the methods based on the CORDIC
vector rotation algorithm. These methods are described in the following sections.
5.1 Direct digital frequency synthesizers using the look
up table method.
The most straightforward approach for digital modulation is the LUTbased method
used in, for example, [79],[80], [35]. In this method, the carrier is formed by addressing
the memory with the phase value and mapping the current phase to the value of the
sinusoidal signal. Then the generated carrier is multiplied with the modulating data by
using digital multipliers. Advantages of this method are the good frequency resolution
and relative simplicity. Drawbacks are that the multipliers and memories may require
a large area, especially with high resolutions, and memories may become the speed
bottleneck at high sampling rates.
With a lookup table method, it is possible to realize every function y = f (x) of
variable x by mapping the value x to the output y with some mapping element, usually
a memory block. The accuracy of the mapping depends on the resolution of the input
value x and the area (=accuracy) of the mapping element. When this is applied to the
40 Methods for direct digital frequency synthesis and modulation
frequency synthesis, the variable to be mapped is usually the phase of the sinusoid
and is mapped to the corresponding amplitude value [81]. The principle of the LUT
based frequency synthesis is presented in Fig. 5.1. ∆φ is the phase increment, which is
z
−1
∆
p
p k
Cosine
ROM
( ) t ω cos
a
φ
Figure 5.1 LUTbased DDS
integrated over time with a digital integrator also called a phase accumulator. The phase
value obtained by integration is then used as the address to the ROM memory, which
maps the phase value to the desired amplitude value. The accuracy of the synthesis is
controlled by the values of p, k and a (Fig. 5.1) [79], [80].
The enhancement of the performance of the synthesizer is usually achieved by
increasing the values of k and a. The value p affects mostly the frequency resolution
of the synthesizer that is not the speed bottleneck. The phase accumulator can be made
almost arbitrarily fast with pipelining techniques, for example [82]. The increase of
the values a and k results the increase of the area of the ROM memory. The increase of
this area may slow down the operation of the memory block and limit the achievable
frequency band. Therefore, several techniques of memory size reduction have been
developed.
The compression techniques can be roughly divided into three categories, namely
the symmetry reduction techniques [83], [84], [85], segmentation techniques [86], and
subtractive techniques [87], [88].
The symmetry reduction techniques are based on the fact that the shape of the
sinusoid is the same in each quadrant, so only the ﬁrst quadrant should be coded into
the memory. The values in other three quadrants are obtained by controlling the sign of
the phase and magnitude (Fig. 5.2). In quadrature synthesizers, additional symmetry
Comp−
lementor
Phase
accu
Comp−
lementor
Phase
increment
MSB 2
nd
MSB
2
nd
MSB MSB
ROM
Sine
Figure 5.2 Symmetry reduction technique.
5.1 Direct digital frequency synthesizers using the lookup table method. 41
reductions may be achieved by taking into account that [85]
cos(φ) = sin
π
2
−φ
, 0 ≤φ ≤
π
2
. (5.1)
In the subtractive reductions, the number of output bits of memory is reduced by
subtracting some simple function out of the sine function and by saving only the differ
ence into the memory. The simplest subtractive method, called sinephase difference
algorithm, is to subtract the phase out of the sine and add it to the output of the memory
[87], but also more complex functions such as double trigonometric [88], slope opti
mized linear function [89], quadratic [90] and quadline approximation [91] have been
used.
With segmentation techniques, the large memory is divided into smaller units by
exploiting the trigonometric identities, for example
sin(φ(n)) = sin
π
2
(A(n) +B(n) +C(n))
= sin
π
2
(A(n) +B(n))
cos
π
2
C(n)
(5.2)
+cos
π
2
(A(n) +B(n))
sin
π
2
C(n)
,
where A(n), B(n), and C(n) are subbuses of the phase value bus φ(n). For symmetry
reasons φ(n) is limited to be 0 ≤φ(n) ≤
π
2
. If C(n) is chosen to be small (i.e. few least
signiﬁcant bits, LSBs), Eq. (5.2) may be approximated with
sin(φ(n)) ≈sin
π
2
(A(n) +B(n))
+cos
π
2
(A(n) +B(n))
sin
π
2
C(n)
, (5.3)
where B(n) is the mean value of B(n). Now the ﬁrst term of Eq. (5.3) can be stored
in a coarse ROM and the second term in a ﬁne ROM (Fig. 5.3).
Phase
accu
Phase
increment
Coarse
ROM
Fine
ROM
A(n)+B(n)
A(n)+C(n)
φ(n)
Figure 5.3 Memory compression by trigonometric approximation.
A wide variety of segmentation techniques have been presented during the past few
years using trigonometric identities [83], [86], [92], interpolating [93], [94], and inter
polating with nonlinear addressing [95]. With these methods, symmetry and subtrac
tive reductions are usually also applied. The effectiveness of the compression method
is a tradeoff between the memory size and complexity of the additional hardware re
42 Methods for direct digital frequency synthesis and modulation
quired to form the actual sinusoidal output. A comparison of memory compression
ratios obtained with various compression methods is presented in [95]; however, the
comparison of the memory compression ratios does not tell the whole truth, since the
highest compression ratios may be achieved with the methods that require an exten
sive amount of additional hardware. A comparison of the respective areas required for
implementation of various DDS circuits is presented in Table 5.1 in Section 5.3
It is preferable to use the combination of the different compression methods, for
example, subtraction reduction, symmetry reduction, and segmentation [87], [96]. The
speed of the synthesizer can be increased with, for example, the parallel structures [97].
5.2 CORDICvector rotation algorithmbased frequency
synthesizer and modulator
CORDIC is an abbreviation for the coordinate rotation digital computer, which was
introduced by J. Volder in 1959 [98].
CORDICtype algorithms are suitable for calculating trigonometric functions [98],[99],
[100], hyperbolic trigonometric functions [101], logarithmic and exponent functions
[102], sine wave generation [103], [104], linear transformations [105],[106], digital ﬁl
ters and matrix based DSP algorithms [105] and inverse trigonometric functions [107].
The CORDIC algorithm is also suitable for digital modulator/demodulator applications
[108], [103],[6], [109] [110]. When applied to frequency synthesis and modulation, the
algorithm provides as good a frequency resolution as the LUTbased method, but the
modulation can be performed without any multipliers as in [103].
In hybrid realizations of the CORDIC algorithm [111], [112], [109], [110], a com
bination of LUT and the CORDIC rotator is used in order to further reduce the area of
the synthesizer.
The CORDIC based modulation can be presented as follows. Discretetime QAM
modulation may be presented as a matrix multiplication as
M
r
=
¸
i (n)cos(φ(n)) +q(n)sin(φ(n))
−i (n)sin(φ(n)) +q(n)cos(φ(n))
¸
=
¸
cos(φ(n)) sin(φ(n))
−sin(φ(n)) cos(φ(n))
¸¸
i (n)
q(n)
¸
, (5.4)
where φ(n) =ωnT
s
, T
s
is the sampling interval and ω is the desired angular frequency.
Eq. (5.4) gives the desired modulation result as the ﬁrst element of the resulting column
5.2 CORDIC vector rotation algorithm based frequency synthesizer and modulator 43
vector. By notifying that
¸
cos(φ
1
±φ
2
) sin(φ
1
±φ
2
)
−sin(φ
1
±φ
2
) cos(φ
1
±φ
2
)
¸
=
¸
cos(φ
2
) ±sin(φ
2
)
∓sin(φ
2
) cos(φ
2
)
¸
×
¸
cos(φ
1
) sin(φ
2
)
−sin(φ
1
) cos(φ
1
)
¸
, (5.5)
it may be stated that the rotation φ(n) in Eq. (5.4) can be achieved by the chain of
multiplications
M
r
≃M
ra
=
N−1
∏
k=0
¸
cos(φ
k
) σ
k
(n)sin(φ
k
)
−σ
k
(n)sin(φ
k
) cos(φ
k
)
¸¸
i (n)
q(n)
¸
, (5.6)
where σ
k
(n) ={−1, 1} and it is determined by
Z
0
(n) = φ(n)
σ
k
(n) = sign(Z
k
(n)) (5.7)
Z
k+1
(n) = Z
k
(n) −σ
k
(n)φ
k
.
Z
k+1
in Eq. (5.7) is the residual angle to be rotated after k
th
stage. To operate properly,
Eq. (5.6) has two terms of convergence [98]. First, the angle φ(n) should be bounded
and presentable by the sum of φ
k
’s
N−1
∑
k=0
φ
k
+φ
N−1
≥ φ(n) , −π ≤φ(n) ≤π.
φ
k
≤ φ
N−1
+
N−1
∑
i=k+1
φ
i
(5.8)
Second, the residual rotation angle should converge to zero
lim
k→∞
Z
k
(n) = 0, (5.9)
which is always satisﬁed when
Z
k+1
(n) ≤φ
k
. (5.10)
Furthermore Eq. (5.6) can be simpliﬁed by taking cos (φ
k
) as a common subexpression.
This results in
M
ra
=
¸
cos(φ
0
) σ
0
(n)sin(φ
0
)
−σ
0
(n)sin(φ
0
) cos(φ
0
)
¸
×
44 Methods for direct digital frequency synthesis and modulation
N−1
∏
k=1
cos(φ
k
)
¸
1 σ
k
(n)tan(φ
k
)
−σ
k
(n)tan(φ
k
) 1
¸¸
i (n)
q(n)
¸
. (5.11)
By selecting
φ
k
= arctan
2
−k+1
(5.12)
and φ
0
=
π
2
to satisfy the Eq. (5.8), we may write the Eq. (5.11) in a form
M
ra
= K
¸
0 σ
0
(n)
−σ
0
(n) 0
¸
×
N−1
∏
k=1
¸
1 σ
k
(n)2
−k+1
−σ
k
(n)2
−k+1
1
¸¸
i (n)
q(n)
¸
, (5.13)
where
K =
N−1
∏
k=1
cos(φ
k
). (5.14)
The values of φ
k
and K can be computed beforehand because the number of stages
N is known and because the sign of cos(φ
k
) = cos(−φ
k
) is always positive, when
0 ≤ φ
k
<
π
2
. The value of K is only dependent on the number of stages, approaching
1.6468 with large N. If the constant scaling factor of the modulated signal is allowed,
the effect of K can be discarded resulting in the modulation equation
M
b
=
¸
0 σ
0
(n)
−σ
0
(n) 0
¸
×
N−1
∏
k=1
¸
1 σ
k
(n)2
−k+1
−σ
k
(n)2
−k+1
1
¸¸
i (n)
q(n)
¸
. (5.15)
Eq. (5.15) can be computed with the series of N CORDIC rotation blocks, which
may be realized by using only adders/subtracters and negators in the zero stage. The
inputoutput relation of the stages are
X
k+1
(n) = X
k
(n) +sign(Z
k
(n))Y
k
(n)2
−k+1
Y
k+1
(n) = −sign(Z
k
(n))X
k
(n)2
−k+1
+Y
k
(n) (5.16)
Z
k+1
(n) = Z
k
(n) −sign(Z
k
(n))φ
k
for k
th
stage and
X
1
(n) = sign(Z
0
(n))Y
0
(n)
= sign(φ(n))q(n)
Y
1
(n) = −sign(Z
0
(n))X
0
(n)
5.3 Survey of digital frequency synthesizers 45
= −sign(φ(n))i (n)
Z
1
(n) = Z
0
(n) −sign(Z
0
(n))φ
0
= φ(n) −sign(φ(n))
π
2
(5.17)
for the zero stage. φ(n) can be generated with the same kind of phase accumulator as
is presented in Fig. 5.1. It should be noted that the values of φ
k
are presented with the
same notation as φ(n), usually in the two’s complement format.
One possible architecture for the CORDIC rotator is presented in Fig. 5.4. It takes
Phase
accu
φ(n)
∆φ
a
a
p
k=0 k=1 k=N−1
X
k+1
φ
k
Y
k
Z
k
Add/
sub
k+1
Y
Add/
sub
Add/
sub
Z
k+1
X
k
s
s
X
k+1
φ
k
Y
k
Z
k
Add/
sub
k+1
Y
Add/
sub
Add/
sub
Z
k+1
X
k
s
s
s=shift by 2
−k+1
X
k+1
φ
k
Y
k
Z
k
Add/
sub
k+1
Y
Add/
sub
Add/
sub
Z
k+1
X
k
s
s
s=shift by 2
−k+1
0
0
i(n)
q(n)
+ cos( ) sin ( ) i(n) q(n) φ(n) φ(n)
− q(n) i(n) sin ( ) cos( ) φ(n) φ(n)
Figure 5.4 CORDIC vector modulator.
the data values i (n) and q(n) as the input and the modulated carrier is X output of
the last stage. The accuracy of the modulation performed with the CORDIC rotator
is dependent on the number of stages N, number of bits p (Fig. 5.4) on the phase
computation path, and the number of bits a on the X/Y path. The frequency resolution
is selected by the number of bits in the phase accumulator. The effects of N, a and p
(Fig. 5.4) are analyzed in [113], [114] and [115]. The CORDIC may also be used as a
frequency synthesizer if q(n) and i (n) are constants.
With the CORDIC rotator, no digital multipliers are needed for the modulation of
the carrier, as is with the LUTbased digital frequency synthesizer. Also no memories
are required, thus enabling pipelining. If only the frequency synthesis is performed,
there is no or little advantage of the multiplierfree realization and the LUTbased or
LUT/CORDIC hybrid may result in a smaller area. Very efﬁcient hybrid mixers have
also been presented [109], [110].
5.3 Survey of digital frequency synthesizers
Area, speed and resolution of various LUT and CORDICbased frequency synthesizer
implementations are presented in Table 5.1. It can be noticed that, with a hybrid re
alization based on the combination of LUT and CORDIC vector rotation algorithm,
effective savings of hardware may be achieved. It should be noted that if the ”Mixer”
feature column in Table 5.1 contains ”No”, at least three multipliers are required in
addition to the reported hardware in order to enable quadrature modulation.
46 Methods for direct digital frequency synthesis and modulation
Areaspeedresolution tradeoff between LUT and CORDIC realizations is ana
lyzed in detail in [112].
Table 5.1 Comparison of DDS implementations.
Method Type Process (P)hase,
(A)mpl.
resol.
Sampl.
freq.
[MHz]
Area
[mm
2
]
Mixer Comments
Sunderland
[83]
segm.
LUT
3.5µm
CMOS
P=14
A=12
7.5 48.1 No External
DAC
Nicholas
[86]
segm.
LUT
1.25µm
CMOS
P=15
A=12
150 24.55 No 8b DAC
Bellaouar
[93]
interp.
LUT
0.8µm
CMOS
P=12
A=9
30 0.9 No Core area,
no DAC, IQ
Langlois1
[94]
interp.
LUT
0.35µm
CMOS
P=18
A=14
100 0.110 No Core area,
no DAC, IQ
Langlois2
[94]
interp.
LUT
0.35µm
CMOS
P=16
A=12
320 0.282 No Core area,
no DAC, IQ
Langlois3
[94]
interp.
LUT
0.35µm
CMOS
P=16
A=12
100 0.079 No Core area,
no DAC, IQ
Curtic˘ apean
[92]
seqm.
LUT
0.35µm
CMOS
P=16
A=16
30 0.23 No Core area,
no DAC, IQ
De Caro
[116]
poly
nom.
0.35µm
CMOS
P=14
A=12
80.4 0.31 No Core area,
no DAC, IQ
Yang [91] segm.
LUT
0.35µm
CMOS
P=11
A=9
800 1.3 No Core area,
9b DAC
Gielis
[103]
COR. 1.0µm
bipolar
P=12
A=10
540 24.96 Yes No DAC,
IQ
Madisetti
[117]
hybr.
COR.
1.0µm
CMOS
P=22
A=16
100 12.00 No Core area,
no DAC, IQ
Janiszewski
[112]
hybr.
COR.
0.35µm
CMOS
P=20
A=16
310 3.72 No Core area,
no DAC
Curtic˘ apean
[118]
hybr.
COR.
0.35µm
CMOS
P=19
A=16
100 0.46 No Core area,
no DAC, IQ
Torosyan1
[109]
hybr.
COR.
0.25µm
CMOS
P=19
A=13
300 0.36 Yes Core area,
no DAC, IQ
Torosyan2
[109]
hybr.
COR.
0.25µm
CMOS
P=19
A=13
600 0.72 Yes Core area,
no DAC, IQ
Song1
[119]
hybr.
COR.
0.35µm
CMOS
P=18
A=16
150 1.4 No Core area,
no DAC, IQ
Song2
[110]
hybr.
COR.
0.25µm
CMOS
P=18
A=15
330 0.51 Yes Core area,
no DAC, IQ
5.4 Other digital modulation methods 47
5.4 Other digital modulation methods
5.4.1 Modulation to quarter of the sampling rate
Similarly to CORDICmodulation, multipliers are not needed with this method [36],[37]
[120]. The upconversion is made to a quarter of the system clock frequency by multi
plying the data values repeatedly by sequence [1, 0, −1, 0]. If the sequence [+1, −1]
is used, the data is upconverted to half of the sampling frequency. The only hard
ware required for this modulation is a negator and a multiplexer. The sign control can
also be included in, for example, coefﬁcients of a digital ﬁlter [37]. A shortcoming
of the method is the ﬁxed carrier frequency. This method can be expanded in order to
generate carrier frequencies other than the quarter of a single sampling frequency. In
this case, the method is called multistage modulation and is described in, for example,
[121].
5.4.2 Frequency synthesis with nonlinear D/A converter
A memoryfree method for frequency synthesis is presented in [122]. In this method,
the phasetosinusoid mapping is achieved by a nonlinear D/A converter. While the
usage of memories is avoided, the implementation of a goodquality nonlinear D/A
converter is not trivial. Also, the amplitude modulation has to be performed in the
analog domain; the advantage of DSP in modulation is lost.
Chapter 6
Currentsteering
digitaltoanalog converter
design
Currentsteering digitaltoanalog converters have become the mainstream architecture
of D/A converters since the late 80’s. This is due to following properties of current
steering architecture. With this it is possible to provide relatively large currents (10
to 20mA) to 50Ω load without buffering. The operation speed of a currentsteering
converter is determined by the ability to drive the gates of the switches, instead of
the gain bandwidth product (GBW) of the buffer circuitry, as in resistorstring and
switchedcapacitor D/A converters. Sample rates of several hundreds of millions of
samples per second can therefore be achieved, which makes the currentsteering D/A
converter the most suitable architecture for, for example, digital IF transmitters and
direct digital synthesizers. In addition, only transistors are used to provide the output
current; this enables the usage of the standard CMOS process, whereas highaccuracy
resistors and capacitors are required in resistorstring or switchedcapacitor converters.
This chapter describes the theory of currentsteering D/A converters applied in the
design of the prototype circuits presented in Chapter 7. As an introduction to the
subject, some general issues considering the currentsteering D/A converters and their
performance metrics are discussed in Sections 6.1 and 6.2. In Section 6.3, the static
linearity as a function of transistor mismatch is analyzed. The previously published
linearity yield models are compared with simulations, and the yield model developed
and published by the author [13] is presented. Section 6.4 discusses the previously
published calibration methods that are used to improve the static linearity of the con
verters above 12 bits. Also the digital calibration method developed and published by
50 Currentsteering digitaltoanalog converter design
Cascode transistors
Switches
Vdd Vdd
O+ O
Load
I 2I 2
B1
I
Binary weighted
current sources
2
B
I 2
B
I 2
B
I
Thermometer coded
current sources
Vdd
Bias
Switch drivers
Clock
Data
Bias
Digital
Figure 6.1 Block diagram of a typical currentsteering D/A converter.
the author and his team [14] is presented. Section 6.5 considers the effects due to the
output impedance variation. In Section 6.6, the signal conversion from discrete time
digital to continuous time analog is discussed and mathematically modeled, while dis
tortion sources such as transition asymmetry are analyzed. In Section 6.7, the timing
nonlinearities are added to the model presented in Section 6.6. The effect of the jitter
on the spectral performance is analyzed by simulations, and the performance degrada
tion due to codedependent clock load and power supply interference is demonstrated.
The jitter analysis is also partially published by the author in [15]. Section 6.8 is about
the layout techniques used to reduce the effect of the process gradients on the current
source mismatch. The previously published methods are discussed, and methods used
in the prototype circuit presented in Section 7.2 are described.
6.1 General description of the current steering D/Acon
verter
A block diagram of a typical currentsteering D/A converter is presented in Fig. 6.1
A currentsteering D/A converter consists of current sources and cascode transistors
that are often used to increase the impedance of the current source. Switches are used
to combine the current of the current sources and form an output signal. Gates of the
switches are driven by control signals decoded from input data with digital circuitry.
Clock buffers and some analog bias circuitry are also required. These circuit blocks
together form a complex mixedmode circuit entity.
In an Nbit converter, there are 2
N
input codes, of which one is zero, resulting
6.1 General description of the current steering D/A converter 51
−Thermometer coders
−Calibration
−Control logic
−Dynamic equalizing
DIGITAL
−Clock amplifier
−Clock buffers
−Clock distribution network
CLOCK
−Current sources
−Cascode transistors
−Bias circuitry
−Switches
ANALOG
Io+ Io−
Clock
Data
−Switch control logic
−Switch drivers
MIXED−MODE
−Synchronization flip−flops
Figure 6.2 Domains of the D/A converter.
in a total current requirement of 2
N
−1 times the current corresponding to the LSB
(I
lsb
). Current sources can be weighted (usually binary weighted), thermometer coded,
(i.e. each current source has the same weight), or segmented (i.e. combination of
binary weighted and thermometer coded), which is usually the case. The usage of
binary weighted current sources reduces the number of switches, but introduces difﬁ
culties in switchdriver synchronization, since larger currents require larger switches,
thus providing a larger capacitive load. The timing differences in switch control sig
nals result in glitches, i.e. spikes in the output current. For example, MSB transition
01111−> 1000 in a binaryweighted D/A converter may cause a glitch, since the tran
sition of the MSB bit is slower than the three LSB bits. It is therefore preferable to use
as many as possible thermometercoded bits at the MSB end in order to produce good
synchronization of the most signiﬁcant bit transitions, and use binary weighting for
the LSB part. The practical limit for thermometercoded bits is around 7, due to the
increased area required for the switch drivers and the decoder logic.
A currentsteering D/A converter can be divided into four types of circuitry do
mains each of them having a unique contribution to the performance of the converter.
The domains of the D/A converter are presented in Fig. 6.2.
The digital domain of a D/A converter includes all of the pure digital circuitry of
the converter. The digital domain is less sensitive to noise and interference. It is more
like a source of interference, whose propagation to any of the other domains should be
eliminated, or, at least, minimized. The digital circuitry usually consists of at least a
thermometer decoder, since segmented architecture is often used. Calibration, which
is often needed for accuracies of 12bit or more, requires also some kind of digital
circuitry. Switching activity equalization, which is used to decorrelate the switching
activity from the input code, is also mostly performed in the digital domain.
In the mixedmode domain, the control signals for the switches of the converter are
formed and the switch control signals are synchronized with ﬂipﬂops. The synchro
nization ﬂipﬂops/latches usually convert the digital data signal from a singleended
52 Currentsteering digitaltoanalog converter design
digital bit to an fully differential analog signal, which can then be transformed to an
actual control signal with some simple logic circuitry and buffering. The power sup
plies of the mixedmode domain are usually separated from the digital domain in order
to avoid coupling and interference after synchronization. The transition activity in the
digital domain is related to the input data, thus generating input data dependent in
terference, whose coupling to the mixedmode domain can result in codedependent
timing jitter, and thus harmonic distortion at the converter output. In addition, even
though the switch control signals in the mixedmode domain are sensitive to interfer
ence, they are digital like signals switching from railtorail, and therefore generate
interference that can couple to the analog domain.
In the analog domain, the unit currents are generated and combined in order to
form the analog output signal. Usually one or multiple cascode transistors are used to
increase the output impedances of the current sources in order to reduce the distortion
generated by the code dependent output impedance variation. The analog domain is
sensitive to interference, but, whereas the sensitivity in the mixedmode domain is
mainly related to the jitter of the sampling instance, the sensitivity in the analog domain
is continuous. All nodes in the analog domain (except the output nodes and gates of
the switch transistors) are biased to a certain operating point, and they should remain
stable even when switching occurs. Unfortunately this kind of stability is unachievable.
Interference can, and will, couple to every possible node in the analog domain. Effects
are more severe on one node than on another, and they can be reduced by various
means, such as shielding with ground planes; however, coupling to the analog domain
cannot be totally prevented.
The sensitivity of the clock domain is related to sampling. Interference in the clock
domain will cause jitter. Because the clock takes care of all synchronization in the
converter, the interference in the clock domain will be reﬂected in the performance of
the whole converter. The higher the sampling frequency, the more severe the effect of
the jitter on the performance of the converter. Unfortunately, the clock net, and thus the
clock domain, has to be distributed around the converter because it is connected to both
digital and mixedmode domains. Therefore it is subjected to interference originated
in both of these domains. It is also sensitive to the coupling of the analog output to
the clock signal, but because the clock domain is not directly connected to the analog
domain, this kind of coupling can be more easily avoided.
6.2 Performance metrics 53
Input code
O
u
t
p
u
t
v
a
l
u
e
Actual
Ideal
Figure 6.3 Gain error of the D/A converter.
6.2 Performance metrics
6.2.1 Static linearity: Gain error, DNL and INL
In the ideal case, the output current of the converter is linearly dependent on the input
code, i.e. the input code “7” causes 7I
lsb
current to ﬂow to the output load. If the
average LSB step is smaller or larger than was originally intended, there is gain error
(Fig. 6.3). The gain error is usually not a problem, since the relative accuracy of the
conversion is much more important than the absolute accuracy, i.e. it is more impor
tant than that with input code “8”, the output is twice as large as with input code “4”
regardless of the actual output values corresponding to “4” and “8”. However, in some
applications, such as I/Q transmitters, where two converters have to have equal gain,
the gain error is an important parameter, since the imbalance between I and Q signal
branches results in reduced sideband rejection in I/Q mixers and interchannel interfer
ence in reception. Gain calibration between converters is therefore usually needed in
that kind of application.
Within a single converter, the gain error is usually not a problem, since the error
does not introduce nonlinearity, which would distort the output signal. More severe
nonidealities are the Differential Nonlinearity (DNL) and Integral Nonlinearity (INL).
They are nonlinearities mainly caused by a mismatch of the current source transistors
and limited output impedance of the current branch. The INL of a D/A converter is
deﬁned as the difference between the analog output value and the straight line drawn
between output values corresponding to the smallest and the largest input code, divided
54 Currentsteering digitaltoanalog converter design
Input code
O
u
t
p
u
t
v
a
l
u
e
Ideal
Actual DNL
Average LSB step
INL
Figure 6.4 Differential Nonlinearity and Integral Nonlinearity.
by the average LSB step. INL is sometimes also deﬁned as the difference of the analog
output and bestﬁt straight line throughout the output values [123]. In this book, the
former deﬁnition is used. DNL is deﬁned as the variation of the step size relative to
average LSB step. It should be noted that, because DNL and INL are obtained by
referring the actual output to the linear output obtained by using the average LSB step,
INL values corresponding to the smallest and the largest input codes are always zero.
Deﬁnitions of DNL and INL presented in Fig. 6.4.
The information included in DNL can be further analyzed as follows. DNL tells us
how much the step at code transition from k to k +1 actually differs from the average
step size. If the value of DNL is less than 1, the converter is no longer monotonic,
i.e. the output value decreases as the input code increases. Fully thermometercoded
converters are always monotonic. Monotonicity can only be lost with binary weighted
converters. A converter is considered to have N bit accuracy if DNL does not exceed
±0.5LSB, i.e. the output value is within the bounds of quantization error.
INL is a curve that tells us how much the actual output corresponding to input
code k differs from linear (not ideal) output. INL is often reported as a single ﬁgure
(maximum INL = x) or as a range (INL =±x), but these ﬁgures will not tell us much
about a single converter. More important is the shape of INL curve, because it includes
all information about the lowfrequency nonlinearity of the converter.
DNL and INL are important performance metrics in the sense that they deﬁne the
limits of the linearity of the converter. Linearity is further degraded by dynamic non
idealities as the signal frequency and sampling rate are increased. The role of DNL
6.2 Performance metrics 55
and INL of the converters as a performance metric is twofold. On the one hand, they
deﬁne the quality of the low frequency operation, on the other, with modern Nyquist
rate converters with sample rates from 100MHz to 1GHz, the dynamic nonlinearities
are clearly limiting the performance, and therefore the static linearity of the converter
is quite meaningless.
6.2.2 Linearity and noise: SNR, SFDR, THD, SINAD and ENOB
In addition to DNL and INL, various ﬁgures of merit are commonly used to indicate
the quality of a D/A converter.
A signaltonoise ratio (SNR) is the ratio of the signal power (usually the power of
a sinusoidal signal) and the noise power integrated over certain signal band in decibels.
When Nyquistrate converters are considered, SNR is usually deﬁned for the signal
band from 0 to half of the sample rate. The upper limit of the SNR is deﬁned by
quantization noise,
σ
2
n
=
∆
2
12
, (6.1)
in which ∆ is the size of the quantization step. Presenting the sinusoidal signal with an
amplitude A with Nbits results in
∆ =
2A
2
N
, (6.2)
and SNR of
SNR = 6.02N +1.76. (6.3)
SNR will be further degraded by other noise sources, such as thermal noise and 1/f
noise.
Very often interference spurs exist in the output spectrum of the converter. These
spurs are most often due to harmonic distortion, i.e nonlinearity, of the converter, but
they can also occur for some other reason, such as coupling. The ﬁgure of merit that
tells us the level of highest spurious tone relative to the signal power is the spurious
free dynamic range (SFDR), which is given in decibels relative to (given) signal power.
Total harmonic distortion (THD) is the sum of the power of the all harmonic dis
tortion components, relative to signal power. THD is also usually given in decibels.
The signaltonoise and distortion ratio SINAD is the sum of noise and distortion
power relative to signal power. With SINAD, it is possible to calculate the effective
number of bits (ENOB) of the converter. Assuming the SINAD is determined, ENOB
can be deﬁned as
ENOB =
SINAD−1.76
6.02
. (6.4)
In current steering D/Aconverters, the ﬁgures of merit that are generally announced
56 Currentsteering digitaltoanalog converter design
RC−settling
Settling
Glitch
Figure 6.5 Settling and glitches.
are DNL, INL and SFDR since they give a comparable ﬁgure for the linearity of the
device. However, very often the SFDR (and therefore also the SINAD) of the device is
so low that the ENOB of the device is quite far from the value deﬁned by INL or DNL.
6.2.3 Time domain performance: Settling and glitches
In Fig. 6.5, a typical timedomain waveform of a current steering D/A converter is pre
sented. There are two major timedomain properties that are often referred to, namely
settling and glitches.
Settling is the time required by the output signal to settle to its current value after
transition with certain accuracy, e.g. within a 0.5 LSB range of the “ideal value”. There
are several types of settling, depending on the load of the converter. With RCloads,
the settling is lowpass type RCsettling, indicating ﬁltering of the higherfrequency
components. With RLC type of loads, the settling takes place as damped oscillations.
Because the settling is a ﬁltering operation for the output signal, no serious harmresults
from it as long as the ﬁltering does not affect the desired signal band (from 0 to half of
the sampling frequency in general).
“Glitch” is a spike on the output signal. Glitches can be generated in various ways,
and often they are referred as a form of signal degradation. Glitches can be problematic
when they are generated by the timing differences in synchronization. Also unequal
rise and fall times in binary weighted converters may generate glitches even with dif
ferential output, whereas in thermometer coded converters the asymmetry in transitions
is usually canceled by differentiality. It is essential to understand what the phenomena
behind the glitch is, because most of the glitches or spikes at the output do not intro
duce any kind of nonlinearity to the signal. As long as the glitch is linearly dependent
6.3 Models and relations of transistor mismatch and static linearity 57
on the signal or its discrete time derivative, it only carries part of the signal energy, or
indicates that some signal energy is missing, as later demonstrated in Section 6.6.
6.3 Models and relations of transistor mismatch and
static linearity
In this section, the analysis of the statistical behavior of INL yield as a function of
the current source mismatch is presented. It is demonstrated how the segmentation of
current sources affects the statistical behavior of INL and DNL. Various yield mod
els published during the past decade are analyzed and compared by simulations. In
addition, regression models for DNL and INL yields are presented. These models are
applicable in cases of 10 to 16 bits with 1 to 6 and 1 to 3 thermometer coded MSB bits
for INL and DNL, respectively. The regression model presented is published by the
author in [13].
6.3.1 Current source mismatch and yield
DNL and INL are generated by the mismatch of the drain currents of the current source
transistors. The mismatch of the drain currents is due to global and local variations dur
ing the manufacturing process of a silicon chip. The relative variance of the difference
between the two transistors, having the same dimensions, orientation and operation
point, can be expressed as [124] [125]
σ
2
Id
I
2
d
=
4σ
2
vt
(V
gs
−V
T
)
2
+
σ
2
β
β
2
=
4A
2
vt
WL(V
gs
−V
T
)
2
+
4S
2
vt
D
2
(V
gs
−V
T
)
2
+
A
2
β
WL
+S
2
β
D
2
, (6.5)
where A
vt
, A
β
, S
vt
, and S
β
are process related constants, V
gs
is the gatesource voltage
of the transistor, V
T
is the threshold voltage of the transistor, W is the channel width
and L is the channel length.
The magnitudes of INL and DNL are dependent on the mismatch of the drain cur
rents of the current sources and the structure of the D/A converter. The following
ﬁgures represent DNLs of a 14bit thermometercoded (Fig. 6.6) and binaryweighted
(Fig. 6.7) D/A converter. It can be seen that the maximum value of DNL is strongly
dependent on the structure of the D/A converter, i.e. segmentation has an effect on
DNL. Obviously, it is dependent on the number of current sources switched when
moving from one input code to another.
In Fig. 6.8 and Fig. 6.9 the standard deviations of DNL values of the thermometer
58 Currentsteering digitaltoanalog converter design
Figure 6.6 20 DNLs of the thermometer coded D/A converter.
Figure 6.7 20 DNLs of the binary weighted D/A converter.
6.3 Models and relations of transistor mismatch and static linearity 59
0 2000 4000 6000 8000 10000 12000 14000 16000
1.15
1.2
1.25
1.3
1.35
1.4
1.45
x 10
−3
Standard deviation of DNL
S
T
D
d
e
v
i
a
t
i
o
n
o
f
D
N
L
[
L
S
B
]
Input code
Figure 6.8 Standard deviation of 500 DNLs of the thermometer coded D/A converter.
coded and binary weighted D/A converters are presented. It can be observed, that the
variance of the maximum value of DNL is
σ
2
DNLmax
= Bσ
2
lsb
, (6.6)
[126], where B is the maximum number of unit current sources switched in the single
code transition and σ
lsb
is the relative standard deviation of the error current of a unit
current source.
The same kind of simulations were carried out for the INL of the thermometer
coded and binaryweighted D/A converters. INL curves for these converters are pre
sented in Fig. 6.10 and Fig. 6.11 The dependency of INL on the converter structure is
analyzed in the following sections.
6.3.2 Statistical model of the static linearity
In order to analyze the static behavior of INL, equations for the variances and covari
ances of INL as function of the input code are derived for the thermometercoded and
binaryweighted D/A converter.
The singleended output current of the thermometer coded D/A converter that cor
60 Currentsteering digitaltoanalog converter design
0 2000 4000 6000 8000 10000 12000 14000 16000
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
Standard deviation of DNL
S
T
D
d
e
v
i
a
t
i
o
n
o
f
D
N
L
[
L
S
B
]
Input code
Figure 6.9 Standard deviation of 500 DNLs of the binary weighted D/A converter.
Figure 6.10 20 INLs of the thermometer coded D/A converter.
6.3 Models and relations of transistor mismatch and static linearity 61
Figure 6.11 20 INLs of the binary weighted D/A converter.
responds to the offset binary type input code k can be written as
I
out
(k) =
k
∑
i=0
I
lsb
+
k
∑
i=0
ε
i
, I
out
(0) = 0, ε
0
= 0 (6.7)
where I
lsb
is the ideal LSB current and ε
i
is the error current of i
th
current source. ε
i
is
assumed to have a normal distribution with zero mean and variance σ
2
I
lsb
. Because the
shape of the envelope of the INL is the same for both the singleended and differential
case, only the singleended case is examined here for simplicity. The actual LSB step
can be found by ﬁtting the straight line between the end points of the curve obtained
by sweeping the value of k from 0 to 2
N
−1, where N is the number of bits resulting in
I
lsba
= I
lsb
+
2
N−1
∑
i=1
ε
i
2
N
−1
, (6.8)
where the summation term corresponds to the gain error of the converter. Now it is
62 Currentsteering digitaltoanalog converter design
possible to deﬁne INL relative to I
lsba
as the function of k as
INL
t
(k) =
I
out
−kI
lsba
I
lsba
=
I
lsb
∑
k
i=1
ε
i
I
lsb
−k∑
2
N
−1
i=1
ε
i
I
lsb
(2
N
−1)
I
lsb
1+∑
2
N
−1
i=1
ε
i
2
N
−1
. (6.9)
If it is assumed that the denominator of the right side of Eq. (6.9) is approximately I
lsb
,
Eq. (6.9) can be approximated as
INL
t
(k) ≈
k
∑
i=1
ε
ri
−k
2
N
−1
∑
i=1
ε
ri
2
N
−1
, (6.10)
where ε
ri
=
ε
i
I
lsb
is error of the i
th
current source relative to LSB current I
lsb
. The
subscript t in I
t
(k) stands for the thermometer coded D/A converter.
The INL of the converter can also be presented with the matrix notation
INL
t
= K
T
E −
K
T
I
vt
I
T
vt
E
2
N
−1
= K
T
(I
t
−
I
vt
I
T
vt
2
N
−1
)E = K
T
A
t
E
t
, (6.11)
where K is a 2
N
−1 ×2
N
matrix with each column containing k 1’s starting from the
topmost element and 2
N
−k zeros, I
vt
is 2
N
−1 ×1 unity vector, I
t
is a unity matrix,
and E
t
is 2
N
−1 ×1 vector containing the relative error values. From Eq. (6.11), the
covariance matrix of INL values at code values k
1
and k
2
can be calculated, and result
in
C
t
= E
INL
t
×INL
T
t
= E
K
T
A
t
E
t
E
T
t
A
T
t
K
=
K
T
A
t
A
T
t
K
σ
2
lsb
, (6.12)
where σ
2
lsb
= VAR[ε
ri
] is the relative error variance of the unit current source. The
elements of C
t
are
c
t
(k
1,
k
2
) =
MIN(k
1
, k
2
) −
k
1
k
2
2
N
−1
σ
2
lsb
(6.13)
and they represent the covariances between INL
t
(k
1
) and INL
t
(k
2
). By setting k
1
=
k
2
= k, the variance of the INL at the code value k is obtained.
σ
2
INL
t
(k) =
k −
k
2
2
N
−1
σ
2
lsb
(6.14)
6.3 Models and relations of transistor mismatch and static linearity 63
which are the values on the diagonal of C
t
. The correlation coefﬁcient between the two
INL values is
ρ
t
(k1, k2) =
COV [INL
t k1
, INL
t k2
)]
σ
Ik1
σ
Ik2
=
MIN(k
1
, k
2
) −
k
1
k
2
2
N
−1
k
1
−
k
2
1
2
N−1
k
2
−
k
2
2
2
N−1
. (6.15)
In a similar manner, the covariance matrix for the binary weighted and segmented
D/A converter can be computed. The INL of the binaryweighted converter can be
written as
INL
b
≈ B
T
W
db
E −
B
T
W
b
I
T
vb
W
db
E
2
N
−1
= B
T
I
b
−
W
b
I
T
vb
2
N
−1
W
db
E = B
T
A
b
E
b
, (6.16)
where B is an N ×2
N
matrix with each column containing the binary presentation of
k, W
b
is an N ×1 weighting vector with elements w
i
= 2
N−1−i
, i = [0...N −1], W
db
=
Diag(W
b
), and E
b
is an N ×1 error vector of normally distributed random variables
with zero mean and variance σ
2
lsb
.
By combining the INL matrix equations of the binaryweighted and thermometer
coded converters, the INL equation for the segmented converter is obtained as
INL
s
≈ S
T
W
ds
E
s
−
S
T
W
s
I
T
vs
W
ds
E
s
2
N
−1
= S
T
I
s
−
W
s
I
T
vs
2
N
−1
W
ds
E
s
= S
T
A
s
E
s
, (6.17)
where
S =
¸
K
s
B
s
¸
, (6.18)
W
s
=
¸
2
B
×I
vt
W
b
¸
, (6.19)
K
s
is a matrix with columns containing 2
N−B
−1 thermometer coded MSB bits and B
s
with columns containing B binary weighted LSB bits, W
ds
=
Diag(W
s
), and E
s
is
2
N−B
+B−1×1 error vector of normally distributed random variables wit h zero mean
and variance σ
2
lsb
.
64 Currentsteering digitaltoanalog converter design
The INL covariance matrix of the segmented D/A converter is
C
s
= E
INL
s
×INL
T
s
= E
S
T
A
s
E
s
E
T
s
A
T
s
S
=
S
T
A
s
A
T
s
S
σ
2
lsb
(6.20)
with elements
c
sk
1
,k
2
=
S
T
k
1
W
T
ds
W
ds
S
k
2
−
k
1
k
2
2
N
−1
σ
2
lsb
(6.21)
The variances of INL can be found on the diagonal of C
s
resulting in
σ
2
INL
sk
=
k −
k
2
2
N
−1
σ
2
lsb
. (6.22)
The correlation coefﬁcients are given by
ρ
sk
1
,k
2
=
COV [INL
sk
1
, INL
sk
2
)]
σ
Ik1
σ
Ik2
=
S
T
k
1
W
T
ds
W
ds
S−
k
1
k
2
2
N
−1
k
1
−
k
2
1
2
N−1
k
2
−
k
2
2
2
N−1
. (6.23)
To give an example of the differences between the correlation matrices of a thermometer
coded and binaryweighted D/A converter, correlation matrices for 3bit converters are
presented. The correlation matrix R
t
for the 3bit thermometercoded D/A converter is
R
t
=
0 0 0 0 0 0 0 0
0 1 0.6455 0.4714 0.3536 0.2582 0.1667 0
0 0.6455 1 0.7303 0.5477 0.4000 0.2582 0
0 0.4714 0.7303 1 0.7500 0.5477 0.3536 0
0 0.3536 0.5477 0.7500 1 0.7303 0.4714 0
0 0.2582 0.400 0.5477 0.7303 1 0.6455 0
0 0.1667 0.2582 0.3536 0.4714 0.6455 1 0
0 0 0 0 0 0 0 0
. (6.24)
6.3 Models and relations of transistor mismatch and static linearity 65
Correlation matrix R
b
for the 3bit binary weighted D/A converter is
R
b
=
0 0 0 0 0 0 0 0
0 1 −0.2582 0.4714 −0.4714 0.2582 −1 0
0 −0.2582 1 0.7303 −0.7303 −1 0.2582 0
0 0.4714 0.7303 1 −1 −0.7303 −0.4714 0
0 −0.4714 −0.7303 −1 1 0.7303 0.4714 0
0 0.2582 −1 −0.7303 0.7303 1 −0.2582 0
0 −1 0.2582 −0.4714 0.4714 −0.2582 1 0
0 0 0 0 0 0 0 0
.
(6.25)
Correlation matrix for the 3bit converter with 2 segmented MSB bits
R
s
=
0 0 0 0 0 0 0 0
0 1 −0.2582 0.4714 −0.4714 0.2582 −1 0
0 −0.2582 1 0.7303 0.5477 0.4000 0.2582 0
0 0.4714 0.7303 1 0.1667 0.5477 −0.4714 0
0 −0.4714 0.5477 0.1667 1 0.7303 0.4714 0
0 0.2582 0.4 0.5477 0.7303 1 −0.2582 0
0 −1 0.2582 −0.4714 0.4714 −0.2582 1 0
0 0 0 0 0 0 0 0
.
(6.26)
The following observations can be made about the covariance matrices C
t
, C
b
, and
C
s
, and correlation matrices R
t
,R
b
, and R
s
:
1) Values on the edges of the covariance matrices are zero which means that INL
values at k =0 and k =2
N
−1 are zero, and therefore they can be discarded from
the statistical model of INL.
2) If the edge rows and columns are discarded from C
t
, the resulting matrix C
t2
is
a symmetrical positive deﬁnite matrix and hence invertible. Its inverse is also
positive deﬁnite. The square root of the positive deﬁnite matrix is nonsingular.
3) If the edge rows and columns are discarded from C
b
and C
s
, the resulting matri
ces C
b2
and C
s2
are singular, their determinants are zero, and therefore they are
not invertible. They are symmetrical positive semideﬁnite matrices.
4) The correlation factors of INLs of the thermometercoded D/A converters are
positive and their values are less than one.
5) The correlation factors of the segmented and binaryweighted D/A converters
can be negative. The correlation factors of the binaryweighted converter be
66 Currentsteering digitaltoanalog converter design
0 2000 4000 6000 8000 10000 12000 14000 16000
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
Standard deviation of INL
S
T
D
d
e
v
i
a
t
i
o
n
o
f
I
N
L
[
L
S
B
]
Input code
Simulated
Calculated
Figure 6.12 RMS of 500 INLs of the thermometercoded D/A converter.
tween INLs positioned symmetrically relative to the midpoint of the INL curve
have the correlation factor 1, indicating the perfect negative correlation.
Figs 6.12 and 6.13 represent the simulated and computed values of the standard
deviation of INL for the thermometercoded and binaryweighted D/A converter. It
can be seen that the simulated values follow quite accurately the values computed with
Eq. (6.14).
Once the variances, covariances and correlation factors are calculated, it is possible
to try to ﬁnd a statistical model for the INL. One good candidate for the statistical
distribution model of the INL is the multivariate normal distribution (MVN) . The
probability density function (PDF) of the MVN is
f
x
(x) =
1
(2π)
n
2
C
x

1
2
e
−
1
2
(x−m
x
)C
−1
x
(x−m
x
)
, (6.27)
where x = [x
1
, x
2
, ...x
n
]
T
is a vector of n real valued randomvariables, m
x
= [m
1
, m
2
, ...m
n
]
T
is a vector containing the means of x, and C
x
is a symmetric positive deﬁnite covariance
matrix.
For INL
t2
(INL, from which the ﬁrst and last values are discarded because they are
6.3 Models and relations of transistor mismatch and static linearity 67
0 2000 4000 6000 8000 10000 12000 14000 16000
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
Standard deviation of INL
S
T
D
d
e
v
i
a
t
i
o
n
o
f
I
N
L
[
L
S
B
]
Input code
Simulated
Calculated
Figure 6.13 RMS of 500 INLs of the binaryweighted D/A converter.
always zero), the MVN density function can be written as
f
INL
t2
(INL
t2
) =
1
(2π)
2
N
−2
2
C
t2

1
2
e
−
1
2
INL
T
t2
C
−1
t2
INL
t2
, (6.28)
but for INL
b2
and INL
s2
(INL, from which the ﬁrst and last values are discarded be
cause they are always zero) this is not possible, since C
b2
and C
s2
are singular and
therefore not invertible, and because their determinants are zero.
Once the PDF is deﬁned, the cumulative distribution function (CDF) of INL
t2
can
be deﬁned as
F
INL
t2
(INL
t2
) =
1
(2π)
2
N
−2
2
C
t2

1
2
Z
I
1
−∞
...
Z
I
2
N−2
−∞
e
−
1
2
INL
T
t2
C
−1
t2
INL
t2
dI
1
...dI
2
N
−2
. (6.29)
In order to validate the assumption of the multinormal distribution, simulations
were performed by generating vectors of random variables that have the desired vari
ance and covariance properties. This is achieved by variable transformation
X =C
−
1
2
t2
INL
t2
, INL
t2
=C
1
2
t2
X, (6.30)
where X is a vector of an independent N(0,1) distributed random variable. Simulation
68 Currentsteering digitaltoanalog converter design
−1.5 −1 −0.5 0 0.5 1 1.5
0
1
2
3
4
5
6
7
8
9
10
Probability density function of INL
P
r
o
b
a
b
i
l
i
t
y
d
e
n
s
i
t
y
PDF: Monte Carlo
PDF: Multivariate normal distr.
Figure 6.14 PDF of INL of a thermometercoded D/A converter with various values of σ.
results for the 8bit thermometer coded D/A converter are presented in Figs. 6.146.17.
It can be observed, that the results obtained with MonteCarlo simulation follows quite
accurately the MVN distribution generated by variable transformation. Similarly,
the comparison can be made for the segmented 8bit converter with 4 binaryweighted
bits. The results are presented in Figs. 6.186.21.
Simulation results indicate that the assumption of the multivariate normal distribu
tion is valid for INL values of the thermometercoded D/A converter. Due to the fact
that the covariance matrices for the binaryweighted and the segmented D/A converter
are not invertible, the multivariate normal distribution is not directly applicable. Sin
gular Value Decomposition can be used in order to calculate an approximation of the
inverse of covariance matrices; however, this does not solve the problem related to the
zerovalued determinant of the singular covariance matrices.
Eq. (6.29) is probably solvable by numerical methods [127],[128],[129]; however,
in all practical cases (N > 12), the number of random variables (2
N
−2) is much larger
than the number of variables (7) that the program presented in [127] could handle.
However, if we take into account the development of computer resources, the N = 14
case is perhaps solvable with modern computers.
Despite the difﬁculties solving Eq. (6.29), we may write the exact deﬁnition of INL
yield in the case of thermometercoded D/A converter (assuming that the distribution
6.3 Models and relations of transistor mismatch and static linearity 69
−1.5 −1 −0.5 0 0.5 1 1.5
0
0.2
0.4
0.6
0.8
1
Cumulative probability density function of INL
P
r
o
b
a
b
i
l
i
t
y
CDF: Monte Carlo
CDF: Multivariate normal distr.
Figure 6.15 CDF of INL of a thermometercoded D/A converter with various values of σ.
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
0
5
10
15
Probability density function of MAX(ABS(INL))
P
r
o
b
a
b
i
l
i
t
y
d
e
n
s
i
t
y
PDF: Monte Carlo
PDF: Multivariate normal distr.
Figure 6.16 PDF of the maximum absolute value of INL of a thermometercoded D/A converter
with various values of σ.
70 Currentsteering digitaltoanalog converter design
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
0
0.2
0.4
0.6
0.8
1
Cumulative probability density function of MAX(ABS(INL))
P
r
o
b
a
b
i
l
i
t
y
CDF: Monte Carlo
CDF: Multivariate normal distr.
Figure 6.17 CDF of the maximum absolute value of INL of a thermometercoded D/A converter
with various values of σ.
−1.5 −1 −0.5 0 0.5 1 1.5
0
1
2
3
4
5
6
7
8
9
10
Probability density function of INL
P
r
o
b
a
b
i
l
i
t
y
d
e
n
s
i
t
y
PDF: Monte Carlo
PDF: Multivariate normal distr.
Figure 6.18 PDF of INL of a segmented D/A converter with various values of σ.
6.3 Models and relations of transistor mismatch and static linearity 71
−1.5 −1 −0.5 0 0.5 1 1.5
0
0.2
0.4
0.6
0.8
1
Cumulative probability density function of INL
P
r
o
b
a
b
i
l
i
t
y
CDF: Monte Carlo
CDF: Multivariate normal distr.
Figure 6.19 CDF of INL of a segmented D/A converter with various values of σ.
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
0
5
10
15
Probability density function of MAX(ABS(INL))
P
r
o
b
a
b
i
l
i
t
y
d
e
n
s
i
t
y
PDF: Monte Carlo
PDF: Multivariate normal distr.
Figure 6.20 PDF of the maximum absolute value of INL of a segmented D/A converter with
various values of σ.
72 Currentsteering digitaltoanalog converter design
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
0
0.2
0.4
0.6
0.8
1
1.2
Cumulative probability density function of MAX(ABS(INL))
P
r
o
b
a
b
i
l
i
t
y
CDF: Monte Carlo
CDF: Multivariate normal distr.
Figure 6.21 CDF of the maximum absolute value of INL of a segmented D/A converter with
various values of σ.
follows the MVN distribution)
Yield
INL
t
= P(INL
t2
 < 0.5) ×100% (6.31)
= (2F
INL
t2
(INL
t2
) −1) ×100%, (6.32)
INL
t2
= [0.5, 0.5...0.5]
T
. (6.33)
This equals the proportion of converters selected from a random set of converters
that fulﬁlls INL speciﬁcation INL ≤0.5. Thus, because the yield is a function of the
relative variance of the unit current source, which is a function of transistor area and
operation point [124], we could, in theory, discover the area and operating point that
would give a desired yield.
The result that the INL of the converter follows the multivariate normal distribution
is also presented by Cong an Geiger in [130]. The yield analysis presented in this book
was performed by the author most likely at the same time as Cong and Geiger without
knowledge of their work. The analysis is included in this book also to complete the
analysis of the previously published yield models, performed in the next section.
6.3 Models and relations of transistor mismatch and static linearity 73
6.3.3 INL yield models
Because the solution of Eq. (6.29) is quite hard to compute, the relation of Yield
INL
and
σ
2
lsb
has to be deﬁned by other means. Various methods [124], [131], [126], [132] has
been suggested for evaluating the maximum current source variance allowed in order
to achieve the desired accuracy of the converter (or, in other words, a highenough
yield). In [124] the assumption is made that the INL values are independent, and thus
the probability to have a certain INL value can be computed as a product of normally
distributed probabilities over the input range. Using this assumption yields pessimistic
results. This is commented on [133] and the model is improved in [131] so that only the
two most probable error values at MSB transition are taken into account; however, this
model results in optimistic results as demonstrated by simulations later in this section.
In [126], an observation is made that the maximum standard deviation of the output
values is achieved at the two centermost input codes; the value is 0.5
2
N
σ
lsb
(half
of the maximum value due to ﬁtting a line between the endpoints). This statement is
veriﬁed with simulations. The result is approximately the same as the results obtained
with Eq. (6.14) and Eq. (6.22).
In [132], it is assumed that, if an INL error occurs when passing through all the
possible input codes, there is a 50% chance that the error still occurs for ﬁctive code
2
N
. resulting in
Yield
inl
=
P
Y
2
N
< 0.5
−0.75
×4×100%, (6.34)
where Y
2
N
is normally distributed error at the ﬁctive input code 2
N
, with variance
2
N
σ
2
lsb
, and P
Y
2
N
< 0.5
can be obtained from the CDF of the normal distribution.
This model does not take into account the ﬁtting of the output between the code values
0 and 2
N
−1. Also with probability values P
Y
2
N
< 0.5
< 0.75 the Yield
inl
be
comes negative, which is not possible in any case, since the yield is inherently positive
for all ﬁnite error variance values. However, according to simulation results presented
in [132],it seems to model the statistical behavior of the sum of error sources very
accurately in the certain parameter range.
The model presented in [132] gives a quite accurate estimate of the statistical be
havior of INL+gain error, and therefore it is worth of trying to further improve it to
model the actual INL yield with line ﬁtted between the endpoints. Assuming that if
there is a INL error somewhere at the code positions k = 0...2
N−1
−2, there is a proba
bility of 0.5 that it still exists at the ﬁctive code position k =
2
N
−1
2
. If it is assumed that
the probability of an INL error existing at some code position k = 2
N−1
−2...2
N
−1
is equal to the probability of an INL error existing in the code range k = 0...2
N−1
−2,
and that the INL error values of these two halves are uncorrelated (which is not true),
74 Currentsteering digitaltoanalog converter design
0.5 1 1.5 2 2.5 3 3.5
0
10
20
30
40
50
60
70
80
90
100
INL yield simulations
C
Y
i
e
l
d
[
%
]
Product method
Product method (2 middle)
Normal distribution
Van den Bosch et. al.
Van den Bosch et. al. (modified)
Simulated
Figure 6.22 INL yield as a function of standard deviation divider C.
the following equation for INL yield can be written
Yield
inl2
=
P
Y
2
2
N
−1
2
< 0.5
−0.75
×4
2
×100%, (6.35)
where Y
2
2
N
−1
2
is a normally distributed randomvariable with variance σ
2
y
2
=
2
N
−1
4
σ
2
lsb
,
which is obtained from Eq. (6.14).
As a reference, it is also tested how an INL yield follows the normal distribution
with variance σ
2
inl
= (2
N
−1)σ
2
lsb
. This equals the assumption that the maximum INL
is the sum of the error currents.
In order to ﬁnd out, which of these models gives the most reliable results for the
D/A converter design, they are compared to the results obtained with MonteCarlo
simulations. In Fig. 6.22 the simulated yield and different estimation methods are
compared. The simulated converter is a 14bit segmented one with 10 binary weighted
bits. One thousand converters are used in MonteCarlo simulations. The relative stan
dard deviation of a unit current source is assumed to be σ
lsb=
1
2C
√
2
N
−1
.
The INL yield obtained with various methods as the function of unit current source
standard deviation is presented in Fig. 6.23. In order to demonstrate the shortcoming
of the modiﬁcation of the Van den Bosch method, the simulations were also carried
out for the 5 and 6bit thermometercoded D/A converters (Fig. 6.24 and Fig. 6.25).
6.3 Models and relations of transistor mismatch and static linearity 75
10
−2.9
10
−2.8
10
−2.7
10
−2.6
10
−2.5
10
−2.4
10
−2.3
10
−2.2
0
10
20
30
40
50
60
70
80
90
100
INL yield simulations
Sigma [LSB]
Y
i
e
l
d
[
%
]
Product method
Product method (2 middle)
Normal distribution
Van den Bosch et. al.
Van den Bosch et. al. (modified)
Simulated
Figure 6.23 INL yield as a function of standard deviation of the unit current source.
It can be observed that, when a 14bit segmented case, the results obtained from
the proposed model are somewhat optimistic, in the 5bit case, results are (almost)
identical compared to MonteCarlo simulations, and in the 6bit case, the results are
just slightly optimistic. So, it can be seen that the accuracy of the model depends on
the number of bits of the converter.
Based on the simulation results, it is justiﬁed to say that none of presented INL
yield approximations gives an accurate basis for the design of the D/A converter.
For accurate information, the designer is still dependent on MonteCarlo simulations.
With the assumption of normally distributed INL with the standard deviation σ
inl
=
√
2
N
−1σ
lsb
, pessimistic yield estimations are obtained in the practical yield range. It
can be used as a “rule of thumb”model: “The Rule of three sigmas” results in high
enough yield.
6.3.4 Regression model for the INL and DNL yields
Due to difﬁculties in the evaluation of the cumulative distribution function of the INL
yield, it is mandatory to use some kind of approximative approach if an accurate es
timation of the yield is required. Instead of the sophisticated variations of guessing
discussed in the previous section, one can always rely on numerical methods.
In [130], it was argued that, for certain INL and DNL yields, the required relative
76 Currentsteering digitaltoanalog converter design
0.5 1 1.5 2 2.5 3 3.5
0
10
20
30
40
50
60
70
80
90
100
INL yield simulations
C
Y
i
e
l
d
[
%
]
Product method
Product method (2 middle)
Normal distribution
Van den Bosch et. al.
Van den Bosch et. al. (modified)
Simulated
Figure 6.24 Modiﬁcation of the Van den Bosch method in 5 bit case.
0.5 1 1.5 2 2.5 3 3.5
0
10
20
30
40
50
60
70
80
90
100
INL yield simulations
C
Y
i
e
l
d
[
%
]
Product method
Product method (2 middle)
Normal distribution
Van den Bosch et. al.
Van den Bosch et. al. (modified)
Simulated
Figure 6.25 Modiﬁcation of the Van den Bosch method in 6 bit case.
6.3 Models and relations of transistor mismatch and static linearity 77
0.8 1 1.2 1.4 1.6 1.8 2 2.2
0
10
20
30
40
50
60
70
80
90
100
Average INL yield with various values of M
C
Y
i
e
l
d
[
%
]
M=1
M=2
M=3
M=4
M=5
M=6
Figure 6.26 Average INL yield as a function of C for various number of segmented bits (M).
standard deviation of the unit current source can be written as
σ
lsb
≈
A
√
2
N
Z(Yield), (6.36)
where A is the range limit to where INL and DNL values should be, and Z(Yield)
is a weighting function that is independent of the number of bits (N). Because of
this, the required σ
lsb
can be discovered easily with, for example, tabulated values of
Z(Yield). It was demonstrated that the binaryweighted and the thermometercoded
D/A converters have different Z(Yield), and that the binaryweighted D/A converters
have worse differential nonlinearity (DNL) performance.
INL yield is dependent on the segmentation of the converter as can be seen from
Fig. 6.26. C in the ﬁgure is the divider of the relative standard deviation of the LSB
σ
lsb
=
1
2C
√
2
N
−1
. This is obtained from Eq. (6.36) by substitution A=
1
2
and Z(Yield) =
1
C
. 2
N
in Eq. (6.36) is substituted by 2
N
−1 in order to deﬁne the required σ
lsb
to be
dependent on the total number of current sources in the converter. By deﬁning σ
lsb
this
way, the effect of the number of bits on the yield is small (also in [130]) (absolute error
to average yield, is ±4%, Fig. 6.28 and Fig. 6.29) on the bit range from 10 to 16, as
explained later. Therefore the average of the yields obtained with a different number
of bits can be used in Fig. 6.26 and Fig. 6.27.
78 Currentsteering digitaltoanalog converter design
0.8 1 1.2 1.4 1.6 1.8 2 2.2
0
10
20
30
40
50
60
70
80
90
100
Averege DNL yield with various values of M
C
Y
i
e
l
d
[
%
]
M=1
M=2
M=3
Figure 6.27 Average DNL yield as a function of C with various number of segmented bits (M).
INL yield is also a function of the number of segmented bits, as shown in, for ex
ample, Fig. 6.26, and the model can be developed in such a way that it also includes the
dependency on the segmentation level. The yield as a function of C and segmentation
could be tabulated, or curves could be given as in [130]. The solution proposed in [14]
is a regression model based on the results of MonteCarlo simulations. The number of
INL curves simulated per each N, M,C combination is 2500. It is emphasized, that the
regression model is applicable only within the variable ranges that it was developed
in.
As a basis of the model, the following assumptions are made. The range of bits is
1016, which is applicable for most of the design cases at the moment. The number of
thermometercoded bits is selected to vary from 16.
It is also assumed, that INL and DNL yields are dependent on the number of
thermometercoded MSB bits because of their larger weight. This assumption is vali
dated by simulations by using the variable ranges under consideration; however, it does
not hold when the total number of bits is small, indicating that the dependency of the
required σ
lsb
on N can not be modeled with Eq. (6.36) for all N.
With the help of Eq. (6.36), and by taking into account the number of segmented
6.3 Models and relations of transistor mismatch and static linearity 79
Table 6.1 gcoefﬁcients of X(C, M) of the INL model
1 M
1
M
2
M
3
1 0.29711 1.75315 0.55515 0.04734
C
−1
1.75115 11.75819 3.72128 0.31774
C
−2
4.03389 29.83137 9.46103 0.81011
C
−3
4.49109 34.85655 11.14615 0.96023
C
−4
2.25836 18.06717 5.89139 0.51356
C
−5
0.37269 3.45830 1.15067 0.10156
bits also, INL yield can be written as
Yield = Φ(C, M), (6.37)
where C is related to σ
lsb
as σ
lsb
=
1
2C
√
2
N
−1
and M is the number of segmented bits.
The range of C is from 0.65 to 2.25. Φ(C, M) can be found by ﬁtting some proper
function to the average of the data obtained by MonteCarlo simulations. The chosen
function is
Φ(C, M) = e
X(C,M)
(6.38)
X(C, M) = g
0
+
g
1
C
... +
g
i
C
i
... +g
i+1
M... +
g
(i×l)
M
l
C
i
,
where i and l are the highest powers of C and M, respectively. The ﬁtting is performed
by minimizing the sum of squared errors between the MonteCarlo simulation results
and the model, resulting in
∑
ε
2
f
= (L
Y
C,M
−XG)
T
(L
Y
C,M
−XG), (6.39)
where L
Y
C,M
= ln(AVG
N
(Y
N,C,M
)) is a vector containing the natural logarithm of the
average of the simulated yield values over the range of bits (N) from 1016, corre
sponding to a certain C and M. X is a matrix with rows containing the elements of
X(C, M) corresponding to certain values of C and M, and G =
g
0
...g
(i×l)
T
. The min
imum of ∑ε
2
f
is obtained by setting the derivative of ∑ε
2
f
relative to G to zero. This
occurs when
G = (X
T
X)
−1
X
T
L
Y
C,M
. (6.40)
In the proposed model the values of i and l are chosen to be 5 and 3, respectively,
in order to achieve reasonable accuracy. The terms of X(C, M) and corresponding
coefﬁcients are presented in Table 6.1.
In Fig. 6.28 the error between the MonteCarlo simulation results and the proposed
80 Currentsteering digitaltoanalog converter design
0.8 1 1.2 1.4 1.6 1.8 2 2.2
−4
−3
−2
−1
0
1
2
3
4
INL yield error M=4
C
Y
i
e
l
d
e
r
r
o
r
[
%
]
N=10
N=11
N=12
N=13
N=14
N=15
N=16
Figure 6.28 Error between simulated INL yields and values given by the model as a function of
C. M = 4.
model is presented in the case M = 4. Error bounds between the simulated INL yields
and the model are presented in Fig. 6.29.
The model for DNL yield is obtained with a similar method. The coefﬁcients g for
the DNL yield model are presented in Table 6.2.
The error between the simulated DNL yields and the values given by the model is
presented in Fig. 6.30.
Table 6.2 gcoefﬁcients of DNL model
1 M
1
M
2
1 2.52953 2.64437 0.64198
C
−1
14.14603 14.25724 3.47087
C
−2
30.28905 27.82176 6.63958
C
−3
32.86155 25.81305 5.73440
C
−4
16.94454 11.77177 2.35736
C
−5
3.34097 2.08428 0.36716
6.3 Models and relations of transistor mismatch and static linearity 81
0.8 1 1.2 1.4 1.6 1.8 2 2.2
−4
−3
−2
−1
0
1
2
3
4
Limits of INL yield error as a function of C
C
Y
i
e
l
d
e
r
r
o
r
[
%
]
Figure 6.29 Error bounds between simulated INL yields and values given by the model as a
function of C.
0.8 1 1.2 1.4 1.6 1.8 2 2.2
−4
−3
−2
−1
0
1
2
3
4
Limits of DNL yield error as a function of C
C
Y
i
e
l
d
e
r
r
o
r
[
%
]
Figure 6.30 Error bounds between simulated DNL yields and values given by the model as a
function of C.
82 Currentsteering digitaltoanalog converter design
6.4 Calibration techniques
The static linearity of the currentsteering D/A converter is dependent on the dimen
sions of the current sources and their placement, as stated in Section 6.3. Various
layout techniques have been developed in order to reduce the effects of the gradients
on the silicon die and various algorithms have been developed in order to dimension
the current sources to achieve adequate static matching. However, the fact is that static
accuracy above 12 bits is hardly achievable with present silicon technologies, no mat
ter how good the gradient cancellation might be, since the variances of INL and DNL
are inversely proportional to area of the current source Eq. (6.5). There is no way to
improve the matching without increasing the area, and the area required becomes quite
large when linearity above 12 bit is targeted.
Because there is no practical way to measure the INL of the converter onchip, the
calibration algorithms usually calibrate the DNL of the converter; this also has an effect
on INL.
Since in any practical case of currentsteering D/A converter design the structure
of the converter is either binary weighted or segmented, the DNL of the converter is
determined by the currents with the largest weight as
σ
2
dnl
≈Bσ
2
lsb
, (6.41)
in which B is the number of LSB currents switched during the code transition (assum
ing no calibration is used). DNL can be reduced by reducing B by increasing the num
ber of thermometercoded bits. It is also possible to use multiple thermometercoded
segments, which, in practice, divides the large DNL values of the binary weighted part
into multiple smaller DNLs, but does not affect DNL values at the transitions of the
current sources with largest weight. In addition, DNL can be reduced by minimizing
the error of the current sources of large weight by using calibration. The calibration
techniques usually concentrate on tuning the erroneous current values.
Several calibration techniques have been developed to reduce the amount of error
of the MSB current sources. Two main categories of calibration can be identiﬁed:
continuous and quantized.
An example of continuous calibration is presented in [134]. It is continuous be
cause the tuning process is purely analog, and no quantization of the error occurs in
any phase of the calibration cycle, thereby enabling the tuning of the current to be
achieved theoretically with inﬁnite accuracy. The principle of the tuning is presented
in Fig. 6.31. It can be observed, that the tuning of the current is performed by stor
ing the V
gs
of the diode connected transistor into the capacitance between the gate and
source of the current source transistor. By using the same reference source for all of
6.4 Calibration techniques 83
Iref Iref
Operation Calibration
Figure 6.31 Principle of continuous tuning of an MSB current source.
DAC Core
Calibration
DAC
Memory
Error Measurement
A/D Conversion
&
Figure 6.32 Principle of quantizing calibration of currentsteering D/A converter.
the MSB current sources, it is possible to equalize the currents of the MSB sources.
However, because the switches are nonideal, the calibration suffers from charge in
jection from the switches and leakage currents, which is the main drawback of this
method. Because of leakage current the calibration of the source has to be repeated
continuously in order to maintain the accuracy. This problem can be avoided by using
digital memory to store the error value.
The most common calibration technique is to use digital storage elements to store
the error values of the MSB current sources and use these values to tune the currents.
The principle of this calibration method is presented in Fig. 6.32. This approach is used
in, for example, [135], [136], [137], [138] and [139]. The common factor for these
methods is the quantization of the measured error and the usage of additional digital
toanalog converters to tune the values of the MSB current sources. These additional
digital to analog converters are usually called ”Calibration DACs”; there can be either
one large calibration DAC, as in [138] and [136], or multiple smaller calibration DACs
for each of the MSB sources, as in [135], [137] and [139].
84 Currentsteering digitaltoanalog converter design
Calibration
Unit
DAC
VDD
R
Control Clk Data
R
Figure 6.33 Block diagram of the D/A converter with calibration using digital predistortion.
The methods differ from each other mainly in ways of performing the measurement
of the error and actual way of tuning the current, but the principle is the same; error is
measured, A/D converted, stored digitally and MSB currents are tuned by D/A conver
sion of the stored error. The term quantized is therefore more valid in this context than
the term ”digital”, since the only digital part of these calibration methods is the storage
element; the tuning is made by analog means.
Also, the main drawback of these methods is related to quantization. Whereas the
continuous method was purely analog and therefore accurate but sensitive to nonide
alities, the quantized method is inaccurate due to quantization noise, but insensitive
to interference due to the digital storage element. The quality of the calibration is
determined by the accuracy of the measurement, quality of the A/D conversion, and
resolution of the calibration DAC.
A slightly different technique is suggested by the author and presented in [14]. The
main difference between this method and previously introduced methods is that there is
no particular calibration DAC. Instead, redundancy is added to the converter by biasing
the MSB current sources so that the current of a single MSB source is less than the sum
of the LSB sources. Because of the redundancy, the input code space and output range
of the converter are extended with four additional MSB current sources, enabling the
correction of the errors of the MSB sources by digital predistortion of the input code.
The principle of the proposed calibration method is presented in Fig. 6.34 and Fig.
6.34.
The calibration is performed as follows: the MSB sources, including the additional
6.4 Calibration techniques 85
1/8 LSB
LSB
Input code
Bias offset
Offset
Output
MSB1 MSB2
CAL REF
Figure 6.34 Principle of the calibration algorithm using digital predistortion.
sources, are biased so that the current of the MSB source is less than the sum of the
LSB sources. This ensures, that the output value of the converter decreases as a new
MSB current source is added to the output. Then the REFvalue in Fig. 6.34 is set to
CAL1. While calibrating, the REF values are ﬁrst decreased in 4 LSB steps. When
the output corresponding to the REF is less than that corresponding to the CAL, the
REF value is increased by steps of 1/8 LSB as long as the output corresponding to
REF is again greater than the output corresponding to the CALvalue. This is simply
a successive approximation register (SAR) A/D conversion of the error value. The
difference between the ﬁnal CAL and REF values is then stored to memory as an
offset value. The CALvalue is then increased in order to add the next MSB current to
output, and the SARcycle is repeated. After all of the offsets are measured and stored,
the calibration cycle is completed and the offsets can be used in normal operation mode
to predistort the input code in order to linearize the transfer function of the converter.
The functionality of the calibration algorithm was veriﬁed with simulations. Figs.
6.35  6.39 represent the minmax envelope curves for DNL and INL uncalibrated and
calibrated 16bit D/A converter with 6 thermometer coded MSB bits under various
matching conditions for the LSB and MSB current sources. DNL and INL yield curves
for various matching conditions are presented in Fig. 6.40. The number of converters
in each of the yield simulations is 1000.
In each of the presented cases DNL and INL yields for uncalibrated converters
is 0%. In the curves for the uncalibrated converters, the effect of the bias offset on
the yield is removed, so that the presented curves indicate directly the effect of the
matching on the yield.
86 Currentsteering digitaltoanalog converter design
16k 32k 48k
−5
−4
−3
−2
−1
0
1
2
3
4
5
INL uncalibrated
I
N
L
[
L
S
B
]
Input code
16k 32k 48k
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
INL calibrated
I
N
L
[
L
S
B
]
Input code
16k 32k 48k
−1.5
−1
−0.5
0
0.5
1
1.5
DNL uncalibrated
D
N
L
[
L
S
B
]
Input code
16k 32k 48k
−0.1
−0.05
0
0.05
0.1
DNL calibrated
D
N
L
[
L
S
B
]
Input code
Figure 6.35 Result of calibration, σ
LSB
=
1
2×3
√
2
16
−1
I
LSB
, σ
MSB
=
16
√
2
10
2×3
√
2
16
−1
I
LSB
.
16k 32k 48k
−5
−4
−3
−2
−1
0
1
2
3
4
5
INL uncalibrated
I
N
L
[
L
S
B
]
Input code
16k 32k 48k
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
INL calibrated
I
N
L
[
L
S
B
]
Input code
16k 32k 48k
−1.5
−1
−0.5
0
0.5
1
1.5
DNL uncalibrated
D
N
L
[
L
S
B
]
Input code
16k 32k 48k
−0.125
0
0.125
DNL calibrated
D
N
L
[
L
S
B
]
Input code
Figure 6.36 Result of calibration, σ
LSB
=
2
2×3
√
2
16
−1
I
LSB
, σ
MSB
=
16
√
2
10
2×3
√
2
16
−1
I
LSB
.
6.4 Calibration techniques 87
16k 32k 48k
−5
−4
−3
−2
−1
0
1
2
3
4
5
INL uncalibrated
I
N
L
[
L
S
B
]
Input code
16k 32k 48k
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
INL calibrated
I
N
L
[
L
S
B
]
Input code
16k 32k 48k
−1.5
−1
−0.5
0
0.5
1
1.5
DNL uncalibrated
D
N
L
[
L
S
B
]
Input code
16k 32k 48k
−0.25
0
0.25
DNL calibrated
D
N
L
[
L
S
B
]
Input code
Figure 6.37 Result of calibration, σ
LSB
=
4
2×3
√
2
16
−1
I
LSB
, σ
MSB
=
16
√
2
10
2×3
√
2
16
−1
I
LSB
.
16k 32k 48k
−5
−4
−3
−2
−1
0
1
2
3
4
5
INL uncalibrated
I
N
L
[
L
S
B
]
Input code
16k 32k 48k
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
INL calibrated
I
N
L
[
L
S
B
]
Input code
16k 32k 48k
−1.5
−1
−0.5
0
0.5
1
1.5
DNL uncalibrated
D
N
L
[
L
S
B
]
Input code
16k 32k 48k
−0.5
−0.25
0
0.25
0.5
DNL calibrated
D
N
L
[
L
S
B
]
Input code
Figure 6.38 Result of calibration, σ
LSB
=
8
2×3
√
2
16
−1
I
LSB
, σ
MSB
=
16
√
2
10
2×3
√
2
16
−1
I
LSB
.
88 Currentsteering digitaltoanalog converter design
16k 32k 48k
−5
−4
−3
−2
−1
0
1
2
3
4
5
INL uncalibrated
I
N
L
[
L
S
B
]
Input code
16k 32k 48k
−1.2
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
1.2
INL calibrated
I
N
L
[
L
S
B
]
Input code
16k 32k 48k
−1.5
−1
−0.5
0
0.5
1
1.5
DNL uncalibrated
D
N
L
[
L
S
B
]
Input code
16k 32k 48k
−1.25
−1
−0.75
−0.5
−0.25
0
0.25
0.5
0.75
1
1.25
DNL calibrated
D
N
L
[
L
S
B
]
Input code
Figure 6.39 Result of calibration, σ
LSB
=
16
2×3
√
2
16
−1
I
LSB
, σ
MSB
=
16
√
2
10
2×3
√
2
16
−1
I
LSB
.
0 0.002 0.004 0.006 0.008 0.01 0.012
40
50
60
70
80
90
100
INL and DNL yields of 16−bit calibrated DACs
σ
LSB
Y
i
e
l
d
INL
DNL
Figure 6.40 DNL and INL yields of a calibrated 16b D/A converter as a function of σ
LSB
.
6.5 Effects of output impedance variation 89
Simulation results indicate that DNL and INL yields are strongly dependent on
the matching of the LSB current sources which determines the achievable DNL and
INL yield. It can be seen that, when the matching of the LSB sources is deteriorated,
it begins to dominate the DNL, and thus the INL yield. It is also demonstrated that
acceptable yield levels can be achieved with very poor MSB matching, thus making it
possible to effectively reduce the area required for the MSB sources.
The amount of the error that can be calibrated with the algorithm is determined
by the amount of additional MSB current sources. Assuming zero mean error in the
sources, the maximum error that can be calibrated equals the bias offset of the MSB
current sources, whereas the sum of the bias errors cannot exceed the additional code
range obtained by adding the sources. In the presented case, the code range added is
4096 LSBs and the number of MSB sources is 67, resulting in a maximum correctable
error of 61 LSBs.
6.5 Effects of output impedance variation
The ﬁnite impedance of the current sources causes codedependent variation on the
output impedance of the currentsteering D/A converter, introducing nonlinearity to
the output signal. In this section, Taylorseries approximations of the INL of a single
ended and differential converter are presented in order to give equations of the non
linearities, which are then used to compute the analytical result of maximum INL and
SFDR as a function of output impedance.
Nonlinearities due to impedance variation have been previously discussed in [140],
[141], [142], and [143]. The secondorder nonlinearities due to impedance variation
are discussed in [140], [141] and [142], thirdorder distortion is analyzed in [143], and
the frequency dependency of the output impedance is discussed in [142].
Results presented in this section equal the results presented in [142] for a single
ended case; however, results for the SFDR of differential converter differ from the
results presented in [143].
The frequency dependency of the output impedance is analyzed mathematically
in detail and the results are veriﬁed with simulations. Results differ slightly when
compared to [142]. The limits of moving the poles and zeros of output impedance in
frequency are determined.
The analysis of the output impedance analysis is linked to implementation by an
alyzing the effect of transistor dimensions on the frequency response of the output
impedance, demonstrating the effect of various design parameters, and the boundaries
of the output impedance optimization.
90 Currentsteering digitaltoanalog converter design
Z
u
k
k I
lsb l
Z
Vout
Figure 6.41 Output impedance variation of the singleended D/A converter.
6.5.1 Distortion due to low frequency impedance variation
Let a single current source branch of a fully thermometer coded D/A converter have the
impedance Z
c
when the switch is conducting, and impedance Z
op
when it is not. In this
case, the change in the impedance due to switching can be modeled as an impedance
in parallel with the impedance Z
u
of the open (not conducting) switch. Z
u
can be
computed as
Z
u
=
Z
c
Z
op
Z
op
−Z
c
. (6.42)
Since Z
op
is usually very large at low frequencies, the low frequency analysis can
be performed by observing the value of the current branch in the conducting state;
however, in highfrequency analysis it is important to isolate Z
op
, since it is constant
and thus does not introduce any distortion. However, Z
op
may introduce some unde
sired phenomena such as frequencydependent attenuation and, in that sense, it should
be taken into account. Frequency dependency is discussed in more detail in Section
6.5.2.
The lowfrequency effects of the impedance variation can be analyzed as follows.
In Fig. 6.41, the simpliﬁed circuit for a singleended D/A converter is presented. The
single ended converter has the output voltage
V
out
(k) =
kI
lsb
Z
l
1+
kZ
l
Z
u
, (6.43)
in which Z
l
is the load impedance and Z
u
is the impedance of the unit current source.
INL caused by the ﬁnite output impedance of the current source can be written as
INL
zse
(k) =
kZ
l
1+
kZ
l
Z
u
−
kZ
l
1+
Z
l
(
2
N
−1
)
Z
u
Z
l
1+
Z
l
(
2
N
−1
)
Z
u
. (6.44)
By performing thirdorder Taylorseries expansion for INL
zse
with respect to k, k ≈
6.5 Effects of output impedance variation 91
2
N
−1
2
, Eq. (6.44) can be written as
INL
zse
(k) ≈
Z
l
Z
u
2+(2
N
−1)
Z
l
Z
u
3
−8
1+
2
N
−1
Z
l
Z
u
k
2
+
8
2
N
−1
+6
2
N
−1
2 Z
l
Z
u
−
2
N
−1
3
Z
2
l
Z
2
u
k
+
2
N
−1
3 Z
l
Z
u
+
2
N
−1
4
Z
2
l
Z
2
u
. (6.45)
If k is considered as a real number instead of an integer, the maximum value of INL
due to ﬁnite impedance of the current source is
INL
zsemax
≈
1
32
Z
l
Z
u
2
N
−1
2
(16+16
2
N
−1
Z
l
Z
u
+
2
N
−1
2 Z
2
l
Z
2
u
)
(2+(2
N
−1)
Z
l
Z
u
)(1+(2
N
−1)
Z
l
Z
u
)
(6.46)
at
k
max
≈
2
N
−1
2
−
1
16
Z
l
Z
u
2
N
−1
2
2+
2
N
−1
Z
l
Z
u
1+(2
N
−1)
Z
l
Z
u
. (6.47)
For differential output, fourthorder Taylorseries approximation of INL with re
spect to k, k ≈
2
N
−1
2
can be written as
INL
zdi
(k) ≈
1
2
Z
2
l
Z
2
u
2
N
−1
−2k
2+(2
N
−1)
Z
l
Z
u
4
−16
1+
2
N
−1
Z
l
Z
u
k
2
(6.48)
+16
2
N
−1
1+
2
N
−1
Z
l
Z
u
k +
Z
2
l
Z
2
u
2
N
−1
4
(6.49)
with the maximum absolute value
INL
zdimax
≈
Z
2
l
Z
2
u
2
N
−1
3
6
√
3
1+
z
l
Z
u
(2
N
−1)
2+
z
l
Z
u
(2
N
−1)
(6.50)
at
k
max
≈
2
N
−1
2
±
2
N
−1
2+
2
N
−1
Z
l
Z
u
4
√
3
1+(2
N
−1)
Z
l
Z
u
(6.51)
92 Currentsteering digitaltoanalog converter design
It can be observed that INL
zsemax
is linearly dependent on
Z
l
Z
u
whereas INL
zdimax
is
dependent on
Z
2
l
Z
2
u
. It can therefore be assumed that the evenorder distortion generated
in a singleended converter is much greater that the oddorder harmonics in a differen
tial case. However, in real design, it is impossible to cancel all evenorder distortion
with differential structure, although the secondorder distortion is usually attenuated
about 20 dB.
INL equations, Eq. (6.45) and Eq. (6.49), include all nonlinearities due to output
impedance variation normalized to LSB. Thus the harmonic distortion can be discov
ered by applying sinusoidal input k =
(2
N
−1)(1+sin(ωt))
2
Eq. (6.45) and Eq. (6.49),
from which the amplitudes of the second and the third harmonic components can be
determined.
In the singleended case, the spurious free dynamic range (SFDR) is determined by
the second harmonic component. SFDR computed from Eq. (6.45) is approximately
SFDR
zse
≈
4+2
2
N
−1
Z
l
Z
u
(2
N
−1)
Z
l
Z
u
(6.52)
SFDR
zse
≈ 12.04−6.02N +20log
10
Z
u
Z
l
dB,
Z
l
Z
u
≪
1
2(2
N
−1)
. (6.53)
In the differential case, SFDR is determined by the third harmonic, being approxi
mately
SFDR
zdi
≈
16+16
2
N
−1
Z
l
Z
u
+7
2
N
−1
2 Z
2
l
Z
2
u
(2
N
−1)
2
Z
2
l
Z
2
u
(6.54)
SFDR
zdi
≈ 28.08−12.04N +40log
10
Z
u
Z
l
dB,
Z
l
Z
u
≪
1
16(2
N
−1)
. (6.55)
Comparison of simulated accurate distortion values and approximations from Eqs.
(6.52) and (6.54) are presented in Fig. 6.42. It can be observed that the accuracy of
Taylor approximations is exacerbated with large values of
Z
l
Z
u
.
It was stated that the evenorder harmonics cannot be canceled, only attenuated. It
is therefore good to use Eq. (6.52) to ﬁnd the required
Z
u
Z
l
ratio in order to have good
enough SFDR. For example, with a 14bit converter it requires approximately
Z
u
Z
l
to be
greater than 72.9 ×10
6
(157.25dB) in order to have SFDR better than 85 dB. If the
load impedance Z
l
= 50Ω, the impedance of the unit current source has to be greater
than 3.6×10
9
Ω.
6.5 Effects of output impedance variation 93
10
−10
10
−9
10
−8
10
−7
10
−6
10
−5
10
−4
0
50
100
150
200
250
300
SFDR approximations
S
F
D
R
[
d
b
]
Z
l
/Z
u
Single−ended accurate
Single−ended Taylor series
Differential accurate
Differential Taylor series
Figure 6.42 Comparison of simulated and approximated values of SFDR for a singleended and
differential converter.
6.5.2 Frequency dependency of the output impedance
The frequency behavior of the output impedance also affects the distortion, since the
impedance tends to decrease as the frequency increases, as presented in Fig. 6.43.
Fig. 6.44 represents a single current branch of a D/A converter with two cascode
transistors above the current source transistor.
By using a smallsignal equivalent circuit for a transistor and by discarding the
capacitances on the drain node of M4, which are included in constant impedance Z
op
,
94 Currentsteering digitaltoanalog converter design
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
0
20
40
60
80
100
120
140
160
180
200
SFDR due to output impedance variation
S
F
D
R
[
d
B
c
]
Frequency [Hz]
Differential
Single−ended
Figure 6.43 SFDR as a function of frequency.
RL RL
C1
C3
C2
Vc1
Vc2
Vb
o+ o−
M1
M2
M3
M4
Zu
Figure 6.44 Current source with two cascode transistors and switches.
6.5 Effects of output impedance variation 95
it is possible to write the equation for Z
u
in Sdomain as
Z
u
(s) =
N(s)
D(s)
(6.56)
N(s) = s
3
C
1
C
2
C
3
+s
2
C
3
C
2
(g
m2
+g
ds2
+g
ds1
)
+s
2
C
3
C
1
(g
m3
+g
ds3
+g
ds2
)
+s
2
C
2
C
1
(g
m4
+g
ds4
+g
ds3
)
+sC
3
((g
m3
+g
ds3
)(g
m2
+g
ds2
+g
ds1
) +g
ds2
g
ds1
)
+sC
2
(g
m2
+g
ds2
+g
ds1
)(g
m4
+g
ds4
+g
ds3
)
+sC
1
((g
m4
+g
ds4
)(g
m3
+g
ds3
+g
ds2
) +g
ds3
g
ds2
)
+(g
m4
+g
ds4
)(g
m3
+g
ds3
)(g
m2
+g
ds2
+g
ds1
)
+(g
m4
+g
ds4
+g
ds3
)g
ds2
g
ds1
(6.57)
D(s) = s
3
C
1
C
2
C
3
g
ds4
+s
2
C
3
C
2
(g
m2
+g
ds2
+g
ds1
)g
ds4
+s
2
C
3
C
1
(g
m3
+g
ds3
+g
ds2
)g
ds4
+s
2
C
2
C
1
g
ds4
g
ds3
+sC
3
((g
m3
+g
ds3
)(g
m2
+g
ds2
+g
ds1
) +g
ds2
g
ds1
)g
ds4
+sC
2
(g
m2
+g
ds2
+g
ds1
)g
ds3
g
ds4
+sC
1
g
ds4
g
ds3
g
ds2
+g
ds4
g
ds3
g
ds2
g
ds1
. (6.58)
Because g
m
≫g
ds
, Eq. (6.56) can be approximated with
Z
u
(s) ≈
N
a
(s)
D
a
(s)
(6.59)
N
a
(s) = g
m4
g
m3
g
m2
s
3
C
1
C
2
C
3
g
m4
g
m3
g
m2
+s
2
C
3
C
2
g
m4
g
m3
+
C
3
C
1
g
m4
g
m2
+
C
2
C
1
g
m3
g
m2
+s
C
3
g
m4
+
C
2
g
m3
+
C
1
g
m2
+1
(6.60)
D
a
(s) = g
ds4
g
ds3
g
ds2
g
ds1
s
3
C
1
C
2
C
3
g
ds3
g
ds2
g
ds1
+s
2
C
3
C
2
g
m2
g
ds3
g
ds2
g
ds1
+
C
3
C
1
g
m3
g
ds3
g
ds2
g
ds1
+
C
2
C
1
g
ds2
g
ds1
+s
C
3
g
m3
g
m2
g
ds3
g
ds2
g
ds1
+
C
2
g
m2
g
ds2
g
ds1
+
C
1
g
ds1
+1
. (6.61)
96 Currentsteering digitaltoanalog converter design
It is possible to further simplify Eq. (6.61) with the following assumptions. Usually
C
1
is very large compared to C
2
and C
3
because its value is determined by the routing
of the current source matrix. If
C
1
g
ds1
≫
C
3
g
m3
g
m2
g
ds3
g
ds2
g
ds1
, the factorization results in
Z
u
(s) ≈
g
m4
g
m3
g
m2
g
ds4
g
ds3
g
ds2
g
ds1
s
C
1
g
m2
+1
s
C
3
g
m4
+1
s
C
1
g
ds1
+1
s
C
3
g
m3
g
ds3
g
ds2
+1
. (6.62)
On the other hand, if
C
3
g
m3
g
m2
g
ds3
g
ds2
g
ds1
≫
C
1
g
ds1
Z
u
(s) ≈
g
m4
g
m3
g
m2
g
ds4
g
ds3
g
ds2
g
ds1
s
C
3
g
m4
+1
s
C
3
g
m3
g
m2
g
ds3
g
ds2
g
ds1
+1
. (6.63)
Poles p1, p2, and p, and zeros z1 and z2 of Z
u
in the twocascode case are at frequen
cies
ω
z1
≈
g
m2
C
1
(6.64)
ω
z2
≈
g
m4
C
3
(6.65)
ω
p1
≈
g
ds1
C
1
(6.66)
ω
p2
≈
g
ds3
g
ds2
C
3
g
m3
,
C
1
g
ds1
≫
C
3
g
m3
g
m2
g
ds3
g
ds2
g
ds1
(6.67)
ω
p
≈
g
ds3
g
ds2
g
ds1
C
3
g
m3
g
m2
,
C
3
g
m3
g
m2
g
ds3
g
ds2
g
ds1
≫
C
1
g
ds1
(6.68)
Similarly, we may write the equations for the case of only one cascode and current
source (Fig. 6.45) and current source only (Fig. 6.46). In the onecascode case, the
output impedance can be written as
Z
u
(s) ≈
g
m3
g
m2
g
ds3
g
ds2
g
ds1
s
C
2
g
m3
+1
s
C
1
g
m2
+1
s
C
1
g
ds1
+1
s
C
2
g
ds2
+1
,
C
1
g
ds1
≫
C
2
g
m2
g
ds2
g
ds1
(6.69)
Z
u
(s) ≈
g
m3
g
m2
g
ds3
g
ds2
g
ds1
s
C
2
g
m3
+1
s
C
2
g
m2
g
ds2
g
ds1
+1
,
C
2
g
m2
g
ds2
g
ds1
≫
C
1
g
ds1
, (6.70)
6.5 Effects of output impedance variation 97
C1
C2
RL RL
o+ o−
M3
Vc1
Vb M1
M2
Zu
Figure 6.45 Current source with one cascode transistor.
C1
RL RL
Vb M1
o+ o−
M2
Zu
Figure 6.46 Current source without cascode transistor.
98 Currentsteering digitaltoanalog converter design
resulting in poles p1, p2, and p, and zeros z1 and z2 on frequencies
ω
z1
≈
g
m2
C
1
(6.71)
ω
z2
≈
g
m3
C
2
(6.72)
ω
p1
≈
g
ds1
C
1
(6.73)
ω
p2
≈
g
ds2
C
2
,
C
1
g
ds1
≫
C
2
g
m2
g
ds2
g
ds1
(6.74)
ω
p
≈
g
ds2
g
ds1
C
2
g
m2
,
C
2
g
m2
g
ds2
g
ds1
≫
C
1
g
ds1
. (6.75)
Similarly for the case of current source only, the output impedance variation is
Z
u
(s) ≈
g
m2
g
ds2
g
ds1
s
C
1
g
m2
+1
s
C
1
g
ds1
+1
(6.76)
with pole p and zero z
ω
z
≈
g
m2
C
1
(6.77)
ω
p
≈
g
ds1
C
1
. (6.78)
As analyzed in [142], it is obvious that the best frequency performance is obtained
when routing capacitances C
1
, C
2
, and C
3
are minimized. Next, whether it is possible to
improve the frequency behavior by adjusting the dimensions (i.e.
g
m
g
ds
ratio) of cascodes
and switches will be analyzed. The assumed parameter dependencies are presented in
Eqs. (6.79)(6.83)
g
m
∼ k
gm
W/L (6.79)
g
ds
∼
k
gds
L
(6.80)
C
1
constant (6.81)
C
2
∼ A
cc
W
3
L
3
(6.82)
C
3
∼ A
cc
W
4
L
4
. (6.83)
Dependencies of the capacitances are made on the assumption that C
1
is determined
by the large routing capacitance from current sources to cascode transistors, whereas
C
2
, and C
3
are determined by the channel capacitances of the transistors, and therefore
they are dependent on the dimensions of the transistors. Dependencies of the g
m
and
g
ds
are generally known [144].
6.5 Effects of output impedance variation 99
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
40
60
80
100
120
140
160
180
Scaling of W4 and L4, 2 cascodes
2
0
l
o
g
1
0
(
Z
u
/
Z
l
)
Frequency [Hz]
Scale 1
Scale 2
Scale 3
Scale 4
Scale 5
Figure 6.47 Scaling W
4
and L
4
in 2cascode case.
Frequency dependency of the impedance Z
u
can be analyzed with MATLAB. Fig.
6.47 presents the behavior of Z
u
when both W
4
and L
4
are scaled by the same factor
varying from 1 to 5. It can be observed that as the dimensions are increased, pole p2
in Eq. (6.62) is moved towards lower frequencies due to increasing C
3
, until it cancels
the zero z1. Further increasing the dimensions makes pole p dominant, resulting in Eq.
(6.63). The zero z2 is moved down in frequency due to increasing C
3
.
If C
3
is determined by the routing, the scaling of W
4
and L
4
does not affect its value,
resulting in the behavior presented in Fig. 6.48.
The scaling of W
3
and L
3
affects Z
u
, as presented in Fig. 6.49. The pole p2 in Eq.
(6.62) is moved towards lower frequencies due to the decrease of g
ds3
, until it cancels
the zero z1. Further increasing the dimensions makes the pole p dominant resulting in
Eq. (6.63). The zero z2 is unaffected. Scaling up W
3
and L
3
increases C
2
, but its effect
on z
u
is negligible. Therefore, it really does not matter whether C
2
is constant or not,
as long as
g
m2
C
2
g
ds2
g
ds1
≪
C
1
g
ds1
.
The scaling of W
2
and L
2
affects Z
u
, as presented in Fig. 6.50. The pole p2 in Eq.
(6.62) is moved towards lower frequencies due to decreasing g
ds2
until it cancels the
zero z1. Further increasing the dimensions makes the pole p dominant, resulting in Eq.
(6.63). The zero z2 is unaffected.
The scaling of W
3
and L
3
in the 1cascode case of Fig. 6.45 affects Z
u
as presented
100 Currentsteering digitaltoanalog converter design
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
40
60
80
100
120
140
160
180
Scaling of W4 and L4, 2 cascodes
2
0
l
o
g
1
0
(
Z
u
/
Z
l
)
Frequency [Hz]
Scale 1
Scale 2
Scale 3
Scale 4
Scale 5
Figure 6.48 Scaling W
4
and L
4
in 2cascode case with constant C
3
.
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
40
60
80
100
120
140
160
180
Scaling of W3 and L3, 2 cascodes
2
0
l
o
g
1
0
(
Z
u
/
Z
l
)
Frequency [Hz]
Scale 1
Scale 2
Scale 3
Scale 4
Scale 5
Figure 6.49 Scaling W
3
and L
3
in 2cascode case.
6.5 Effects of output impedance variation 101
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
40
60
80
100
120
140
160
180
Scaling of W2 and L2, 2 cascodes
2
0
l
o
g
1
0
(
Z
u
/
Z
l
)
Frequency [Hz]
Scale 1
Scale 2
Scale 3
Scale 4
Scale 5
Figure 6.50 Scaling W
2
and L
2
in 2cascode case.
in Fig. 6.51. The pole p2 in Eq. (6.69) is moved towards lower frequencies due to
increasing C
2
until it cancels the zero z1. Further increasing the dimensions makes the
pole p dominant, resulting in Eq. (6.70). The zero z2 is moved down in frequency due
to increasing C
2
.
If C
2
is determined by the routing, the scaling of W
3
and L
3
does not affect its value,
and results in behavior similar to that shown in Fig. 6.48.
The effect of scaling W
2
and L
2
is as presented in Fig. 6.52. The pole p1 in Eq.
(6.69) is moved to lower frequencies due to decreasing of g
ds2
, until it cancels the zero
z1. Further increasing the dimensions makes the pole p dominant, resulting in Eq.
(6.70). The zero z2 remains unaffected.
The behavior of the output impedance of a current source without cascode transis
tors is presented in Fig. 6.53. Since C
1
is the only capacitance present and determined
by routing, the pole p in Eq. (6.76) is not affected, nor is the zero z. Increasing the
dimensions only scales the gain and thus increases the output impedance.
The effects of the cascode transistors and scaling of the transistor dimensions can
be concluded as follows. Adding cascode transistors will, in general, increase the
output impedance. Output impedance at higher frequencies is absolutely limited by
Eqs. (6.63), (6.70), and (6.76), once the dominant pole is not caused by the routing
capacitance C
1
. In any case, it is beneﬁcial to increase the impedance by scaling g
m
102 Currentsteering digitaltoanalog converter design
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
40
60
80
100
120
140
160
180
Scaling of W3 and L3, 1 cascodes
2
0
l
o
g
1
0
(
Z
u
/
Z
l
)
Frequency [Hz]
Scale 1
Scale 2
Scale 3
Scale 4
Scale 5
Figure 6.51 Scaling W
3
and L
3
in 1cascode case.
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
40
60
80
100
120
140
160
180
Scaling of W2 and L2, 2 cascodes
2
0
l
o
g
1
0
(
Z
u
/
Z
l
)
Frequency [Hz]
Scale 1
Scale 2
Scale 3
Scale 4
Scale 5
Figure 6.52 Scaling W
2
and L
2
in 1cascode case.
6.5 Effects of output impedance variation 103
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
40
60
80
100
120
140
160
180
Scaling of W2 and L2, no cascodes
2
0
l
o
g
1
0
(
Z
u
/
Z
l
)
Frequency [Hz]
Scale 1
Scale 2
Scale 3
Scale 4
Scale 5
Figure 6.53 Current source with one cascode transistor.
and g
ds
of the switch, since it increases the impedance at all frequencies, whereas
scaling the cascodes seems to increase the impedance on the frequencies below the
second pole.
The impedance can also be increased by scaling only W of transistors; however,
the impedance is more effectively increased if L is also scaled. It should be noticed
that it is not possible to increase L, since it would affect the operating point and drop
the transistors out of the saturation.
As a rule of thumb, the impedance should be increased ﬁrst by maximizing the gain
of the switch (the topmost transistor) within the limits set by the driving capability
of the switch driver and capacitive coupling from the switch gates. After that, the
impedance on the lower frequencies can be further boosted by increasing the size of
the cascode transistors if the pole due to the capacitor at the source node of the switch
is not dominant.
From the output impedance pointofview, it would be probably beneﬁcial to use
either transistor M2 or M3 as a switch and place additional cascodes above them; in this
case, the large transistor would not reduce the switching speed. This kind of structure
is used in the prototype described in Section 7.1.
104 Currentsteering digitaltoanalog converter design
6.6 From discrete to continuoustime domain
In the digital domain, the signal is a train of impulses with certain values without any
other nonideality but quantization noise. When the signal is fed to the D/A converter,
the converter adds nonidealities to the signal while converting it to the analog form. In
previous sections, the static nonlinearities were discussed and it was stated that INL
sets the limit of the linearity of the converter. In this section, the conversion from the
discretetime to continuoustime domain is analyzed by presenting the D/A converter
as a system consisting of several subsystems each providing a response to the digital
discretetime excitation signal. Typical subsystem impulse responses and their Fourier
transforms are presented in Appendix D. Observations on the nonidealities generated
due to conversion are listed at the end of the section.
The discretetime excitation signal can be modeled as a continuoustime signal
sampled with a sequence of Dirac’s delta impulses (the effect of the quantization is not
considered here)
s(t) = s(nT
s
) = s(n) =
∞
∑
n=−∞
δ(t −nT
s
), (6.84)
in which T
s
is the sampling interval. The time domain sampling signal has an frequency
domain equivalent of
S( f ) = F
s
∞
∑
n=−∞
δ( f −nF
s
), (6.85)
in which F
s
is the sampling frequency. Sampling of signal X
c
(t) with the sampling
signal S(t) results in a continuoustime model of the sampled signal
x(t) = x(nT
s
) = x(n) = x
c
(t)
∞
∑
n=−∞
δ(t −nT
s
), (6.86)
which has a spectrum
X ( f ) = F
s
∞
∑
n=−∞
X ( f −nF
s
). (6.87)
A system diagram of a D/A converter is presented in Fig. 6.54. An ideal D/A con
verter can be modeled with only one subsystem h
1
(t), which usually has the impulse
response of a unit pulse of length T
s
(τ = T
s
), forming a sampledandheld nonreturn
tozero (NRZ) type output signal (Fig. 6.55). The sampleandhold impulse response
of the subsystem is deﬁned as
h
1
(t) = u(t) −u(t −τ), (6.88)
6.6 From discrete to continuoustime domain 105
1
(t) h
h (t)
2
h (t)
n
f (x(t))
n
f
2
(x(t))
(t) w
n
(t)
2
w (t)
2
y
(t)
n
y
(t) y
1
x(n) y(t)
Figure 6.54 System diagram of the D/A converter.
Y(t)
t
X(n)
n
X(n)
n
Y(t)
t
Ts
τ
Figure 6.55 Sampleand hold response of the D/A converter.
106 Currentsteering digitaltoanalog converter design
in which τ is the hold time. The sampleandhold system has a frequency response
H
1
( f ) = τ
sin(πf τ)
πf τ
. (6.89)
If τ = T
s
, the system is an NRZ sample and hold. The response y
1
(t) of the subsystem
h
1
(t) to excitation signal X (t) can now be determined as a convolution of the input
and the impulse response
y
1
(t) = x(t) ⊗h
1
(t)
=
Z
∞
−∞
x(t)h
1
(t −τ)dt
=
∞
∑
−∞
x(nT
s
)(u(t −nT
s
) −u(t −nT
s
−τ)), (6.90)
which can be presented in the frequency domain as
Y
1
( f ) =
τ
T
s
sin(πf τ)
πf τ
∞
∑
n=−∞
X ( f −nF
s
). (6.91)
In addition to the sampleandhold subsystem, there may exist several subsystems that
may or may not provide nonlinearity to the output signal. One of the simplest nonide
alities to be included in the converter model is the effect of the ﬁnite rise and fall times
and their asymmetry.
The effect of the ﬁnite rise and fall times can be included in the model by adding a
subsystem h
2
(t) which provides an impulse response, which, together with the sample
andhold impulse response of h
1
(t), models the ﬁnite rise/fall time during the transition
(Fig. 6.56).
The impulse responses corresponding to the linear rising and falling transitions can
be written as
h
r
(t) =
t
T
r
−1
(u(t) −u(t −T
r
)) (6.92)
h
f
(t) =
t
T
f
−1
(u(t) −u(t −T
f
)), (6.93)
in which T
r
and T
f
are the rise and fall time, respectively. The Fourier transforms of
h
r
and h
f
are
H
r
( f ) =
e
−jωT
r
−1
−1
ω
2
T
r
−
1
jω
(6.94)
H
f
( f ) =
e
−jωT
f
−1
−1
ω
2
T
f
−
1
jω
(6.95)
6.6 From discrete to continuoustime domain 107
2
(t) h
1
(t) h
t
t
Figure 6.56 Modeling the transition with subsystem h
2
(t).
The effect of the ﬁnite transition time can be modeled as follows.
y
2
(t) =
w
2
(t) ⊗h
r
(t), w
2
(t) ≥0
w
2
(t) ⊗h
f
(t), w
2
(t) < 0
(6.96)
in which w
2
(t) is the discretetime derivative of the input signal
w
2
(t) = (x
c
(t) −x
c
(t −T
s
))
∞
∑
n=−∞
δ(t −nT
s
). (6.97)
The Fourier transform of w
2
(t) is
W
2
( f ) =
1−e
−
2πf
F
s
∞
∑
n=−∞
X ( f −nF
s
), (6.98)
which approaches jωX (F)as F
s
approaches inﬁnity, corresponding to the Fourier trans
form of the continuoustime derivative of the signal x
c
(t).
The effect of the difference of the rise and fall can be determined by decomposing
the response of the subsystem h
2
as follows. The average response common for both
the rising and falling edges can be deﬁned as
h
2a
(t) =
h
r
(t) +h
f
(t)
2
, (6.99)
108 Currentsteering digitaltoanalog converter design
resulting in average transition response
y
2a
(t) = w
2
(t) ⊗h
2c
(t). (6.100)
The difference in the rise times can be included by adding a subsystem having an
impulse response
h
2b
(t) =
h
r
(t) −h
f
(t)
2
(6.101)
with excitation signal
w
2b
(t) = x
c
(t) −x
c
(t −T
s
)
∞
∑
n=−∞
δ(t −nT
s
)
= w
2
(t ) , (6.102)
resulting in response due to differences between rise and fall times
y
2b
(t) = w
2b
(n) ⊗h
2b
(t). (6.103)
For the sine signal, the spectrum of w
2b
can be computed by using Eqs. (D.6),
(D.8), (D.7), and (D.19) resulting in
W
2b
( f ) = A
1−e
j2πf
0
F
s
∞
∑
n=−∞
∞
∑
k=−∞,odd
1
πk
(δ( f −(k +1) f
o
−nF
s
) −δ( f −(k −1) f
o
−nF
s
)). (6.104)
From Eq. (6.104), it can be clearly seen that the absolute value of a sine signal con
tains evenorder harmonic components. When the transition shapes of the converter
output are known, the amount of distortion due to transition asymmetry can be easily
computed with Eqs. (6.103) and (6.104).
As a conclusion, the following observations are made:
1) The shape of the impulse response of a subsystem does not introduce any non
linearity as long as it is independent from the excitation signal. This means that
glitches at the output do no harm as long as they are a part of the signal inde
pendent impulse response of the subsystem. Therefore, observing the glitches at
the output of the converter does not necessarily give any information about the
linearity of the converter.
2) Transitions can be modeled with a subsystem with discretetime derivative as
an excitation signal. Differentiation is a linear operation and therefore ﬁnite
transition speed does not generate distortion if the rising and falling transitions
are symmetrical.
6.7 Sampling jitter 109
3) Asymmetry in transitionrelated nonidealities can be modeled with a subsystem
with an absolute value of the discretetime derivative of the input signal as an
excitation signal. Absolute value is a nonlinear even function, introducing even
order harmonics, as demonstrated in the case of the sine signal in Eq. (6.104).
Total power of the harmonic component is deﬁned by the shapes of transitions
according to Eq. (6.103).
4) With sinusoidal signals, the amplitude of the derivative is linearly dependent on
the signal frequency (Eq. (D.7)), resulting in increased distortion as the signal
frequency increases. This holds for all transitionrelated nonidealities, including
jitter, as can be seen later in Section 6.7.
5) As the converters are usually segmented, the effect of the subsystems for the
binary weighted part should be analyzed on a per switch basis. However, the
performance is usually dominated by the thermometer coded part.
6.7 Sampling jitter
During the past few years, timing has become an important issue in the design of
currentsteering D/A converters, due to the rapid increase of the sampling rates. The
importance of the static timing mismatch has been demonstrated by Chen et al. [145],
and the reduction of the data dependent clock load (which is a source of jitter) was
mentioned by Schoﬁeld et al. [139]. Special attention has been paid on timing and
jitter issues in the design reported in [146]. Also, various analyzes of timing and jitter
have been published [147], [148], [149].
In this section, a jitter model for a fully thermometercoded D/A converter is de
veloped. Thermometer coding is chosen because it simpliﬁes the computation while
not resulting in signiﬁcant inaccuracies, since the effect of timing inaccuracy of the
binary weighted LSB bits is typically the order of
1
64
to
1
16
compared to the effect of
thermometercoded MSB bits (6 to 4 thermometercoded MSB bits). Jitter analysis for
the binaryweighted part has to be performed on a per switch basis and would result in
very large signal matrices, because, in simulations, a high oversampling ratio has to be
used in order to be able to model the jitter.
In the following sections, a brief introduction to the relations of the jitter on SNR
of the converter is given. It is demonstrated by simulations how certain types of timing
uncertainty are mapped to the output signal of a D/A converter. Some sources of jitter
in currentsteering D/A converters are identiﬁed and analyzed by design examples.
110 Currentsteering digitaltoanalog converter design
6.7.1 Effects of sinusoidal timing jitter
The jitter analysis in this book concentrates on the sinusoidal jitter signals because they
are most likely to produce spurious or harmonic tones to the output of a converter, thus
limiting SFDR.
The output signal of a nonreturntozero (NRZ) D/A converter with sampling jitter
can be deﬁned as the sum of the ideal sampledandheld signal and the timingjitter
induced error signal (Eq. (6.105) and Eq. (6.106))
y(t) =
∞
∑
n=−∞
x(nT)[u(t −nT)
−u(t −(n+1)T)] +e(t), (6.105)
e(t) = ∆x(n)g(t)
=
∞
∑
n=−∞
[x(nT) −x((n−1)T)]
×[u(t −nT −w(nT))) −u(t −nT)], (6.106)
in which T is the sampling interval, u(t) is the unit step function x(nT) is the digital
discretetime input of a converter, and w(nT) is the value of the timingjitter signal at
the time instant nT (Fig. 6.57). For simplicity, it is assumed here that the rise time of
the signal is zero. The effect of the nonzero rise time is analyzed later in this section.
A block diagram of the jitter model is presented in Fig. 6.58
The effect of jitter on the output signal of the converter can be determined by com
puting the spectrum of the jitter signal g(t) as
G( f ) =
∞
∑
n=−∞
Z
∞
nT+w(n)
e
−jωt
dt −
Z
∞
nT
e
−jωt
dt (6.107)
=
∞
∑
n=−∞
e
−jωw(nT)
−1
e
−jωnT
jω
. (6.108)
The spectrum of the error signal g(t) resulting from the sinusoidal jitter signal
w(n) = asin(ω
1
nT) is then
G( f ) =
∞
∑
n=−∞
e
−jωasin(ω
1
nT)
−1
e
−jωnT
jω
. (6.109)
If a is small, Eq. 6.109 can be approximated with the Taylorseries expansion as
G( f ) ≈ F
s
∞
∑
n=−∞
−a
j2
(σ( f + f
1
+nF
s
) −σ( f − f
1
+nF
s
)). (6.110)
6.7 Sampling jitter 111
Actual
Ideal
y(t)
x(n)=x(n)−x(n−1) ∆
w(n)
e(t)
g(t)=u(t−nT−w(n))−u(t−nT)
Figure 6.57 Components of the output y(t).
112 Currentsteering digitaltoanalog converter design
Error pulse
Transition D
Time shift
Sample & Hold
−1
y(t) x(n)
w(n)
Figure 6.58 Block diagram of the jitter model.
An analytical solution for the power spectrum of sinusoidal signals with the pres
ence of sinusoidal jitter and Gaussian noise is presented in[150], and is given as
S( f ) =
C( f )
2
(πf T)
2
∑
p,q
∑
k=1,odd
A
2
k
sin
2
(πf T)
4
I
p
(M)σ( f ± f
k
−pf
1
−qf
s
), (6.111)
C( f )
2
= e
−ω
2
σ
2
E
(6.112)
M =
8π
2
f
2
σ
2
E
A
2
1
(2
N
−1)
sin
ω
1
T
2
, (6.113)
where C( f ) is the Fourier transform of the autocorrelation function of jitter, A
k
is the
amplitude of the signal and its harmonic components and I
p
(M) is a p
th
order modiﬁed
Bessel function of the 1
st
kind and σ
E
is the standard deviation of the Gaussian noise.
Further analysis of the effects of jitter are made by simulations in order to gain
some insight into the jitter behavior.
Fig. 6.59 represents the eight ﬁrst pulses of the jitter error signal of
g(t) = u(t −nT −w(n)) −u(t −nT), (6.114)
w(n) = 0.01T sin(2π0.188n), (6.115)
where the jitter signal w(n) has the frequency of 0.188F
s
and amplitude of 0.01T, T
being the sampling interval.
The spectrum of g(t) with T
r
= 0 is presented in Fig. 6.60, in which the power
of the signal g(t) is presented relative to the power of sinusoid sin(ωnT). It can be
observed that, in the frequency range 0 to
Fs
2
, the dominant frequency component is at
the frequency 0.188F
s
, indicating that the energy of the jitter is mainly concentrated on
the frequency of the jitter signal, as predicted by Eq. (6.110). It may also be observed
that a signiﬁcant amount of energy lies at frequencies higher than
F
s
2
.
6.7 Sampling jitter 113
0 1 2 3 4 5 6 7 8 9
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
Error pulse sequence
Time [t/T]
g
(
t
)
Tr=0
Figure 6.59 Error pulse signal g(t), T
r
= 0.
0 1 2 3 4 5
−120
−100
−80
−60
−40
−20
0
Spectrum of jitter−generated error pulses
Relative Frequency [Fs]
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
c
]
Tr=0
Figure 6.60 Spectrum of error pulse signal g(t).
114 Currentsteering digitaltoanalog converter design
0 1 2 3 4 5 6 7 8 9
−0.06
−0.04
−0.02
0
0.02
0.04
0.06
Effect of the rise time
Time [t/T]
g
(
t
)
Tr=0.2T
Tr=0.4T
Tr=0.8T
Figure 6.61 Eight ﬁrst pulses of g(t) with various T
r
.
As the rise time increases, for example, because of the capacitive load at the output
of the converter, it effects the duration and amplitude of the g(t) according to
g(t) =
t −nT −w(n)
T
r
u(t −nT −w(n)) −
t −nT −T
r
−w(n)
T
r
u(t −nT)
−
t −nT
T
r
u(t −nT) +
t −nT −Tr
T
r
u(t −nT −Tr). (6.116)
The effect of ﬁnite rise and fall time on the timedomain error pulses can be seen from
Fig. 6.61. It can be observed that the shape of the error pulse is an isosceles trapezoid
with duration and amplitude dependent on w(n). Spectra of error pulses under various
risetime conditions are presented in Figs. 6.62 and 6.63. w(n) is still deﬁned by Eq.
(6.115).
It is obvious that, as the rise time increases, the energy at the higher frequencies is
reduced, resulting in reduced total jitter energy, whereas energy in the frequency range
of 0 to
F
s
2
is barely affected. This is veriﬁed by simulations, and the result is presented
in Fig. 6.63, which represents the signaltoerror power ratio and SFDR as a function
of rise time.
The signaltoerror power ratio is computed from the timedomain signal, whereas
SFDR is calculated from spectral components from 0 to F
s
/2. Simulation results in
dicate that, in the case when SFDR is determined by the jitter, SFDR can neither be
6.7 Sampling jitter 115
0 1 2 3 4 5
−120
−100
−80
−60
−40
−20
0
Spectrum of jitter−generated error pulses
Relative Frequency [Fs]
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
c
]
Tr=0.4Ts
Figure 6.62 Spectrum of g(t) with T
r
= 0.4T.
0 1 2 3 4 5
−120
−100
−80
−60
−40
−20
0
Spectrum of jitter−generated error pulses
Relative Frequency [Fs]
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
c
]
Tr=0.8Ts
Figure 6.63 Spectrum of g(t) with T
r
= 0.8T.
116 Currentsteering digitaltoanalog converter design
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
15
20
25
30
35
40
45
Effect of the rise time
Relative Rise Time
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
c
]
SFDR
Signal−to−Error Power Ratio
Figure 6.64 Signaltoerror power ratio and SFDR as a function of rise time.
increased by altering the rise time nor does there exist an optimal rise time in the
SFDR sense, meaning that SFDR is determined by only the standard deviation of w(n).
Typical behavior of SFDR as a function of the jitter magnitude of sinusoidal jitter w(n)
is presented in Fig. 6.65.
For Gaussian jitter, the derivation for the jitter energy on a certain frequency band
from −F
b
to F
b
resulting in SNR for a single sinusoid at the frequency F
sig
sampled
with the rate F
s
, is presented in Appendix C.
SNR(F
b
) ≈
F
2
s
4π
2
F
2
sig
F
b
σ
2
w
(6.117)
In the case of returntozero (RZ) type of signals, jitterinduced SFDR decreases,
since shortening the signal pulse reduces signal energy linearly, whereas the amount of
jitter error energy remains constant.
6.7.2 Distortion due to signaldependent jitter
Fig. 6.66 represents the spectra of a quantized sinusoidal signal x(nT) and a jitter
signal w(nT), which has secondorder dependency on the input signal as
x(nT) = Q[sin(2πf nT)] (6.118)
6.7 Sampling jitter 117
10
−3
10
−2
10
−1
−80
−70
−60
−50
−40
−30
−20
−10
0
10
Jitter Effects
Relative RMS jitter [T]
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
c
]
SFDR
Jitter−to−signal power ratio
Figure 6.65 Signaltoerror power ratio and SFDR as a function of jitter magnitude.
w(n) = Kx(nT) −x((n−1)T)
2
, (6.119)
in which K is chosen so that
max
K(x(nT) −x((n−1)T))
2
= 0.01T. (6.120)
w(n) in Eq. (6.119) is chosen to be dependent on the absolute value of the discrete
time derivative of the input signal since it reﬂects the physical origin of the jitter; often
the jitter is caused by activity of the circuitry, which is usually dependent on the number
of changing thermometercoded bits.
In Fig. 6.67, the spectrum of e(t) in the case of second order jitter w(nT) is
presented.
It can be observed that due to multiplication by the discrete time derivative (Eq.
(6.119)), the resulting distortion is of odd order. As a conclusion it can be stated that
evenorder dependency of the w(nT) on the input signal x(nT) results in oddorder
distortion of the output signal y(t) and vice versa.
The signaldependent jitter can originate from powerrail interference of the switch
driver circuitry of the converter or from the digital circui try due to the substrate cou
pling, from which the ﬁrst one is usually the dominant source of jitter. Clock loading,
if not taken into account, may also result in jitter. Examples of these two jitter sources
118 Currentsteering digitaltoanalog converter design
0 0.2 0.4 0.6 0.8 1
−120
−100
−80
−60
−40
−20
0
Power spectrum
Relative Frequency [Fs]
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
c
]
X(f)
W(f)/T
Figure 6.66 Spectra of the sinusoidal signal x(nT) and second order jitter signal.
0 0.2 0.4 0.6 0.8 1
−120
−100
−80
−60
−40
−20
0
Power spectrum
Relative Frequency [Fs]
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
c
]
E(f)
Figure 6.67 Spectrum of the error signal e(t) caused by second order jitter signal w(n).
6.7 Sampling jitter 119
D D
CLK
Figure 6.68 Buffering of the switch drivers with single buffer.
are given in following sections.
6.7.3 Jitter due to codedependent clock load
Sometimes, in the cases in which relatively accurate synchronization is required, the
clock pins of the synchronizing elements may be driven by one, usually very large,
buffer (Fig. 6.68). If the synchronizing elements driven are the latch/ﬂipﬂop stages of
the switchdriver stage of the D/A converter, this may result in distortion of the output
signal. This is because the load of the clock driver is dependent on the internal states
of the switch driver ﬂipﬂops, which are dependent on the data that is fed to them.
It can be assumed that codedependent clock load causes codedependent jitter. This
assumption can be validated by simulations as follows.
Fig. 6.69 represents the output spectrum of a 16bit currentsteering D/A converter
with the clock driving scheme of Fig. 6.68. This spectrum is the result of the transistor
level simulation of the converter implemented in a 0.35 µm SiGe BiCMOS process.
In order to validate the assumption that the thirdorder distortion in Fig. 6.69 is due to
jitter, the jitter was extracted from the clock signal of the transistorlevel simulation.
In Fig. 6.70, the output signal and the relative timing error of the clock signal are
presented. It can be observed that the jitter seems to be correlated with the output
signal, and thus dependent on the input code, and that the dependency is secondorder.
As stated before, in the case of evenorder jitter, odd order distortion may be expected
at the output as in Fig. 6.69.
In order to verify the origin of the distortion to be jitter, the jitter extracted from the
simulation is applied to the model described by Eqs. (6.105) and (6.106). The spectra
of x(nT) and w(n) from the jittermodel simulations are presented in Figs. 6.71 and
6.72.
It can be observed that the spectral behavior due to jitter follows quite accurately
the spectrum obtained from the transistorlevel simulation, and therefore it is justiﬁed
to say that the distortion is due to the codedependent jitter.
Distortion caused by codedependent clock loading can be reduced by, for example,
adding a small buffer to drive the clock pin of each of the switch driver ﬂipﬂops (Fig.
6.73). The simulation results for the D/A converter with modiﬁed clock buffering are
120 Currentsteering digitaltoanalog converter design
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10
8
−120
−100
−80
−60
−40
−20
0
Power spectrum
Frequency [Hz]
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
c
]
Figure 6.69 Simulated spectrum obtained from the transistorlevel simulation.
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10
−7
−4
−2
0
2
4
x 10
−3
Relative variation of sampling period
Time [s]
T
i
m
i
n
g
E
r
r
o
r
[
T
]
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10
−7
−1
−0.5
0
0.5
1
Signal
Time [s]
V
o
u
t
[
V
]
Figure 6.70 Relative timing error and the output signal of a 16bit D/A converter.
6.7 Sampling jitter 121
0 0.2 0.4 0.6 0.8 1
−120
−100
−80
−60
−40
−20
0
Power spectrum
Relative Frequency [Fs]
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
c
]
X(f)
W(f)/T
Figure 6.71 Spectra of the input signal x(nT) and w(nT).
0 0.2 0.4 0.6 0.8 1
−120
−100
−80
−60
−40
−20
0
Power spectrum
Relative Frequency [Fs]
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
c
]
X(f)
E(f)
Figure 6.72 Spectra of the input signal x(nT) and error signal e(t).
122 Currentsteering digitaltoanalog converter design
D D
CLK
Figure 6.73 Modiﬁed clock buffering.
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10
8
−120
−100
−80
−60
−40
−20
0
Power spectrum
Frequency [Hz]
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
c
]
Figure 6.74 Simulated spectrum of the D/A converter with modiﬁed clock buffering.
presented in Figs. 6.74 and 6.75. It can be observed that the jitterinduced distortion
is effectively reduced with the altered buffering scheme.
6.7.4 Jitter due to powerrail interference
It can be assumed that the parasitic resistance of the power supply rails of the switch
driver circuitry may cause codedependent interference during the transitions of the
switch driving signals, which may result in jitter. The interference on the supply rails
affects not only the clock signal (in those cases where the clock buffers share the same
supply rails), but also the switch driving signals. Therefore, in order to extract the
proper jitter signal from the transistorlevel simulations, the jitter is extracted from the
switch driver signals instead of the clock signal. In order to reduce the code depen
dency of the supplyrail interference, a transition of the switch driver signal may be
6.7 Sampling jitter 123
0 0.2 0.4 0.6 0.8 1
−120
−100
−80
−60
−40
−20
0
Power spectrum
Relative Frequency [Fs]
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
c
]
X(f)
E(f)
Figure 6.75 Effect of the jitter with modiﬁed clock buffering.
ensured on every clock cycle by using the differentialquad switching scheme [151].
Switch drivers are designed so that, when a transition occurs, the switch is opened be
fore the other switch is closed. Jitter is extracted by monitoring the time instants when
V
gs
−V
T
of the closing transistor is zero, ensuring that there is only one conducting
transistor at that time instant.
A lumped resistor model is used for the supplyrail resistance in order to avoid
distortion being dependent on the position of the switch driver, which would be the
case with a distributed resistance model. The positiondependency of the jitter would
further exacerbate the performance of the D/A converter; it is, however, beyond the
scope of this analysis.
Fig. 6.76 represents the output spectrumof the converter obtained fromthe transistor
level simulation, and Figs. 6.77 and 6.78 represent the reconstruction of the output
spectrum with the mathematical jitter model. It can be observed that resistive sup
ply rails can generate an excessive amount of jitter even though the differentialquad
switching scheme [151] is used to reduce the code dependency of the power supply in
terference. The beneﬁts of using the differentialquad switching scheme are discussed
in more detail in Section 7.2.4.
In this section, the effects of the jitter on the spectral performance are demonstrated
by using a mathematical jitter model. Two designrelated examples of the jitterinduced
distortion are given by analyzing the jitter signal extracted from transistorlevel simu
124 Currentsteering digitaltoanalog converter design
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10
8
−120
−100
−80
−60
−40
−20
0
Power spectrum
Frequency [Hz]
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
c
]
Figure 6.76 Simulated output spectrum of the D/A converter with resistive supply rails.
0 0.2 0.4 0.6 0.8 1
−120
−100
−80
−60
−40
−20
0
Power spectrum
Relative Frequency [Fs]
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
c
]
X(f)
W(f)/T
Figure 6.77 Spectra of the input signal x(nT) and w(n) due to supply rail interference.
6.7 Sampling jitter 125
0 0.2 0.4 0.6 0.8 1
−120
−100
−80
−60
−40
−20
0
Power spectrum
Relative Frequency [Fs]
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
c
]
X(f)
E(f)
Figure 6.78 Effect of the jitter due to supply rail interference.
lations with the developed mathematical model. This model can be used to determine
whether the distortion at the output of the converter is due to jitter or not.
As a summary, the following observations can be made of these analyzes: spectral
components due to jitter are deﬁned by the discretetime derivative of the input signal
and the jitter signal w(n) The jitter signal that has an oddorder dependency on the
output signal of the converter will generate evenorder harmonics due to multiplication
by the discretetime derivative of the signal and vice versa.
Even though the total jittertosignal energy ratio is affected by the transition of the
signal, the increase in transition time mainly reduces the frequency component above
F
s
2
thus indicating that SFDR due to jitter can not be optimized by altering the transition
times.
It is demonstrated by simulations that the jittertosignal power ratio increases 3 dB
if the amplitude of the jitter is doubled. However, SFDR on the Nyquist band increases
6 dB due to the fact that increasing jitter amplitude transfers jitter energy from higher
to lower frequencies.
126 Currentsteering digitaltoanalog converter design
6.8 Layout techniques for current source mismatch re
duction
In addition to random variation of the process parameters that was discussed in Section
6.3, the gradient errors are an additional source of static nonlinearity. The gradient
errors are mainly due to the variation of the oxide thickness on the wafer, which is
stated to have a linear dependency on the distance between devices [125], and die
stress gradients, which has been reported to have a quadratic behavior over the device
matrix [152]. The gradient errors have a signiﬁcant effect on the static linearity of the
converter, since the error due to gradients correlate with each other and therefore the
errors may accumulate, resulting in a large INL. The effect of accumulation can be
reduced by choosing the switching order so that the gradient errors of current sources
corresponding to the subsequent code values cancel each other. On the other hand, if
the errors do not correlate, the switching order has no statistical effect on the INL.
There have been several proposals for the layout techniques (also called ”Switching
schemes”) for the reduction of nonlinearity caused by process gradients. The methods
can be divided in two categories. In heuristic methods [153], [154], [155], [156],
[126], [157] , the cancellation of the gradient effect is based purely on the geometrical
aspects without any knowledge of the relations between linear and quadratic (odd and
evenorder) gradients. In the analytical methods presented in [158], [159], the optimal
placement of the current sources (i.e. the optimal switching sequence) in the INL sense
is evaluated by numerical methods. These methods require a priori knowledge about
the relations of the linear and quadratic gradients.
In the following paragraphs, the layout techniques are presented in the order of
publication to demonstrate the evolution of the layout techniques. The layout method
used in the prototype circuit presented in Section 7.2 is also discussed since it differs
slightly from the previously published methods.
The simplest possible sequence for ordering the current sources is presented in
Fig. 6.79. In this ”sequential switching” scheme, the current sources are selected in
the order they appear in the matrix in such a manner that, after all the sources in the
ﬁrst row are selected, then the ﬁrst source of the second row is selected and so on. This
method results in the accumulation of the error in both X and Y directions.
The ﬁrst improvement is the ”symmetrical switching” presented in [153]. The
principle of symmetrical switching is presented in Fig. 6.80. A symmetrical switching
scheme ensures the cancellation of the linear gradient errors; however, the quadratic
errors ere accumulated.
The symmetrical switching scheme is further improved in [154], introducing the
”hierarchical symmetrical switching” scheme (Fig. 6.81), which is designed to reduce
the effect of the quadratic error gradient. In Fig. 6.81, the switching sequence in X
6.8 Layout techniques for current source mismatch reduction 127
0
0
0 0
1 2 3 4 5 6 7 8
1
2
3
4
5
6
7
8
Figure 6.79 Sequential switching.
0
0
0 0
1
2
3
4
5
6
7
8
1 2 3 4 5 6 7 8
Figure 6.80 Symmetrical switching.
128 Currentsteering digitaltoanalog converter design
0
0
0 0
1 2 3 4 5 6 7 8
2
1
3
4
5
6
7
8
Figure 6.81 Hierarchical symmetrical switching.
direction is ordered according to ”Type A” hierarchical symmetrical switching, and Y
direction is ordered according to ”Type B” hierarchical symmetrical switching.
Hierarchical symmetrical switching is further improved in [155]. All introduced
switching schemes so far exploit ”RowColumn Decoding”, meaning that all the cur
rent sources on the row are selected before the row is changed. It is correctly stated in
[155] that this results in an accumulation of the error, since the error builds up column
wise while the error in the direction of rows is canceled. This problem is avoided in
[155] by using four identical current source matrices mirrored with respect to X and Y
axis. Mirroring is also exploited in [126], [156].
The effect of using mirror symmetric matrices can be analyzed in the following
way. Let us begin with the plain current source matrix without any of the mirror sym
metry presented in Fig. 6.82. The solid lines represent gradient, dashed lines represent
canceled gradient. It is well known that the linear (and oddorder) gradient can be can
celed by using common centroid matrices of unity current source transistors, as in Fig.
6.83. Again, the dashed line represents the canceled gradient. This kind of structure,
however, does not necessarily cancel or reduce the second (and even) order gradient
effects. The second (and even) order mismatch can be reduced by further splitting the
unity current source and by using the mirror symmetric submatrices (Fig. 6.84).
The theory can be generalized as follows. For simplicity it is assumed that the
oddorder mismatch has only the ﬁrst order (linear) component and the evenorder
6.8 Layout techniques for current source mismatch reduction 129
Matrix dimension
Figure 6.82 Current source matrix with even and odd order error gradient.
Matrix dimension
Figure 6.83 Compensation of linear (and odd order) gradient with mirror symmetry.
Matrix dimension
Figure 6.84 Reduction of second (and even order) error gradient by further splitting the matrix.
130 Currentsteering digitaltoanalog converter design
mismatch has only the secondorder component. In addition, we may assume that any
constant error has no effect, since it is the same for all the units.
The linear dependency can be removed as in Fig. 6.83, and the residual second or
der mismatch in Xdimension is deﬁned by the parabola with its extreme at the middle
of the chip and zeros at the edges of the chip. The equation for this parabola can be
written as
E
1
(x) = M(x −p
1
)(x −p
2
). (6.121)
It has its extreme at
x
e1
=
(p
1
+ p
2
)
2
, (6.122)
which is exactly in the middle of the zero points. This extreme has the value
E
e1
=
M(p
1
−p
2
)(p
2
−p
1
)
4
. (6.123)
The line that goes through the point (p
1
, 0) and (x
e1
, E
e1
) has the equation
S
11
(x) =
M(p
1
−p
2
)(x −p
1
)
2
. (6.124)
This linear mismatch is again canceled if the current source is further split and divided
into the common centroid matrices that are mirror symmetric relative to the centerline
of the original matrix. After Eq. (6.124) is subtracted from Eq. (6.121) the residual
error can be written as
E
2
(x) = M(x −p
1
)
x −
(p
2
+ p
1
)
2
. (6.125)
This is a parabola with zeros at p
1
and
p
1
+p
2
2
and the extreme at x
e2
=
3p
1
+p
2
4
=
x
e1
+p
1
2
.
The extreme value is
E
e2
=
M(p
2
−p
1
)(p
1
−p
2
)
16
. (6.126)
It can be seen from Eq. (6.123) and Eq. (6.126) that the ratio of these extreme values is
R
e
=
E
e1
E
e2
= 4, so every time the unity source is halved and mirrored in one dimension,
the residual error in that dimension is divided by four.
Figure 6.85 represents the cancellation of linear and quadratic gradients by using
mirror symmetry. Gradients are modeled as
G
x
(x) = g
x1
xcos(θ) +g
x2
x
2
, −1 ≤x ≤1 (6.127)
G
y
(y) = g
y1
ysin(θ) +g
y2
y
2
, −1 ≤y ≤1, (6.128)
in which x and y ranges have been normalized to be ±1 at the matrix boundary,
g
x1
, g
x2
, g
y1
,n and g
y1
are the gain factor for linear and quadratic gradients in x and
6.8 Layout techniques for current source mismatch reduction 131
0 50 100 150 200 250 300 350
0
1
2
3
4
5
6
7
Cancellation of gradient effect with mirror symmetry
Plane angle θ [deg]
M
A
X
A
B
S
I
N
L
[
L
S
B
]
No mirroring
Split to 4
Split to 16
Figure 6.85 Reduction of INL of 16 current sources with mirror symmetry.
y direction, and θ is the plane angle of the linear gradient. The effectiveness of the mir
ror symmetry in removing the linear gradient can be clearly seen. Additional splitting
further reduces the INL due to quadratic gradient by a factor of 4, as calculated.
In the simulation result presented in Fig. 6.85, the plain ”sequential switching”
scheme was used. The effect of the residual error can be further reduced by using
some of the switching schemes discussed before.
In addition to mirror symmetry, the splitting of the current source into smaller
units can be used to very effectively reduce the gradient error. In [157], it was pre
sented that if the current sources are divided into 2
2
N elements, and if these elements
are arranged so that a current source has an element on every row and every column,
both linear and quadratic errors are canceled. The main shortcoming of this method
is the large number of unit elements. To overcome this problem, a new switching
scheme was developed for larger numbers of thermometercoded bits providing very
promising results. The principle of this switching scheme is to translate the positions
of 2
2N
elements to positions of unit current sources of 2N thermometercoded bits with
a simple algorithm developed with numerical optimization to minimize the effect of
the quadratic gradient. This algorithm seems to be a very promising solution for the
gradient cancellation, and the main advantage of this method is that it does not need
any kind of a priori knowledge about the gradients.
132 Currentsteering digitaltoanalog converter design
2 4 1 3
2 4 1 3
3 1 4 2
3 1 4 2
3
1
4
2
3
1
4
2
1
3
2
4
1
3
2
4
7
3
14
10
1
5
12
16
12
9
8
4
3
1
4
2
3
1
4
2
1
3
2
4
1
3
2
4
11
15
2
6
3
1
4
2
19
9
4
14
7
17
12
2
11
1
16
6
5 1 2 4 3
15
5
20
10
3
13
8
18
Figure 6.86 Reduction of INL with optimal rowcolumn sequencing.
A rather similar method was developed by the author and used in the prototype pre
sented in this book. The method is based on the ideas of switching sequences presented
in [159].
It is possible to minimize the maximum value of accumulated linear error of the
unit elements in dimension (X or X) by selecting them in certain order. Let us call this
an “”optimal sequence”. The principle of ﬁnding optimal sequences was presented in
[159]. As mentioned earlier, the problem with the ”RowColumn Decoding” is the ac
cumulation of the error in one dimension while it is canceled in the other. This problem
can be alleviated by applying optimal sequences in the both dimensions simultaneously
(this kind of result is also obtained by applying the technique presented in [157]). Two
examples are given in Fig. 6.86. The number sequences around the matrices indicate
the order of selection and the numbers inside the matrices indicate the number of the
source, i.e. source number 1 is placed ﬁrst into the position indicated by numbers 1,1
of sequences etc.
This technique has at least two shortcomings. First, if the number of rows and
columns are not relatively prime, the number of positions selectable with one sequence
pair is deﬁned by the length of the longer sequence, after which a newoptimal sequence
has to be selected as was done in the case of 4x4 matrix in Fig. 6.86. The newly
selected optimal sequence should also be valid in such a manner that alreadyoccupied
positions are not selected again. It can be seen that in 4x4 case, there are too few
optimal sequences, so suboptimal sequences have to be used. On the other hand, there
is no problem if the number of rows and columns are relatively prime, as in the case of
the 4x5 matrix of Fig. 6.86.
Usually, the number of current sources (including biasing) is 2
N
in the matrix, and
therefore it may become difﬁcult to ﬁnd the optimal sequences, since 2
N
cannot be
presented as the product of relatively prime numbers. If, for some reason, such as in
6.9 Survey of published D/A converters 133
0 50 100 150 200 250 300 350
0
0.2
0.4
0.6
0.8
1
1.2
Cancellation of gradient effect with mirror symmetry
Plane angle θ [deg]
M
A
X
A
B
S
I
N
L
[
L
S
B
]
No mirroring
Split to 4
Split to 16
Figure 6.87 INL and effect of splitting with developed switching sequence.
the case of digital calibration, or due to including the LSB sources into the matrix,
the number of sources differ from 2
N
, the situation can be easier to handle. Simula
tion results for this sequence in the case of 4x4 matrix is presented in Fig. 6.87. Its
effectiveness can be veriﬁed by comparing Fig. 6.87 to Fig. 6.85.
The methods of the layout design of binaryweighted converters are seldom dis
cussed in the papers. Due to the binary weighting, the number of unit sources is large
for currents of larger weight, resulting in almost automatic cancellation of gradient er
rors. Two examples are given in Fig. 6.88. The basic principle is to ﬁll every other
empty position, starting from the opposite corners of the matrix simultaneously. The
ﬁlling of a row is started from side opposite the previous row was started. The same
holds for the sources of different weights.
6.9 Survey of published D/A converters
In this section, the key features and design methods of the recently published current
steering D/A converters are brieﬂy introduced. The ﬁgures of merit of the converters
are listed in Table 6.3.
In [153], the principle of symmetrical switching was introduced and used to allevi
ate the processgradientrelated mismatch of the current sources.
134 Currentsteering digitaltoanalog converter design
3
2
3
2
1
3
M
3
3
0
3
1
2
3
2
3
D
3
2
D
3
1
M
3
2
3
3
2
3
0
1
3
D
2
3
D
Figure 6.88 Two possible current source matrices for 4bit binary weighted D/A converter.
In [154], the switching method was further improved from symmetrical switching
to hierarchical symmetrical switching.
In [160], a switch structure is introduced to improve the switch driver timing, re
duce the switching asymmetry and code dependent glitching at the output. Segmenta
tion is mentioned as a technique for glitch reduction.
In [126], the development of the switching schemes continued with four quadrant
randomization technique. INL and DNL are analyzed as a function of the segmentation,
and the estimates of the standard deviations of INL and DNL are given based on Monte
Carlo simulations. It is mentioned that glitches that are linearly dependent on the code
transition do not introduce distortion. The effect of segmentation is emphasized, and
the segmentation level is optimized in order to optimize DNL, INL, SFDR and area.
The cascode current sources are also used.
In [155], the switching sequence optimization is continued by the introduction of
a hierarchical symmetrical switching scheme using common centroid matrices. Linear
and quadratic error gradients are discussed. A Gaussian distribution is used as an
approximation for INL. Glitches due to switch driver feedthrough are minimized.
Segmentation in two thermometercoded segments with different weights is also used.
In [161] the returntozero output stage is used to reduce the effect of glitches,
codedependent settling and timing skew between current sources.
In [158], the linearity errors due to current source mismatches are further optimized
with the Q
2
random walk switching scheme. A dynamic latch is used for the switch
driver synchronization and the crossing point of the switch driver signals is optimized.
The effect of linear and quadratic gradients are analyzed.
In [162], a selftrimming D/A converter with a trackandattenuate output stage is
presented. Selftrimming is based on the error value stored on the gate capacitance
of the current source, and the error is measured with a Σ∆ analogtodigital converter
(ADC) over the resistance in series with the current source transistor.
6.9 Survey of published D/A converters 135
In [163], a converter capable of 1 GS/s operation is presented. The effect of output
impedance is taken into account, and the effort is put on the design of the highspeed
switch driver. A doublecentroid switching scheme (mirror symmetry) is used to re
duce gradient effects.
In [164], as in the previous design, the effort is put on the switch driver optimiza
tion and signal symmetry in order to achieve highspeed operation. A triple centroid
switching scheme (16 units in one current source + mirror symmetry) is used to im
prove the static matching.
In [137], the static accuracy is improved by calibration based on trimmable current
sources, which are adjusted with an additional calibration DAC.
In [138], the static performance is improved with calibration. The static nonlinear
ity is measured with a 16bit Σ∆ calibration ADC; values are stored in the memory and
addressed with the 6 MSB bits. An additional calibration DAC is used to adjust the
currents of the MSB sources.
In [139], a successive approximation calibration routine is used to trim the MSB
current sources to 18b accuracy. The effect of the nonlinear capacitance at the source
node of the switches is emphasized, and backgatebuffering (bulkbootstrapping of
the switches) is used to reduce the effect of the nonlinear capacitance. Switch driver
timing is also emphasized, and the timing inaccuracies in switching are reduced by
using a local voltage generator that follows the source voltage of the switches. Also, a
differentialquad switching scheme [151] is applied in order to equalize the switching
activity, and thus the charge ﬂow from the supply lines.
In [165], trimming of the ﬂoatinggate current source transistors is used to improve
the static nonlinearity. In addition, a returntozero output stage is used to improve
dynamic performance.
In [166], dynamic element matching is used to average the current source array
errors. 7bit segmentation is used in order to improve dynamic performance and MSB
current sources are composed of 16 unit cells, which are divided into 16 current source
arrays in order to reduce the effect of process gradients.
In [167], capacitive current memory type of calibration is used to trim the MSB
current sources. An RZ stage is used at the output to improve the dynamic perfor
mance. The dynamic performance is also compared to case in which the RZstage is
disabled, indicating that with this particular converter, better highfrequency operation
is obtained with the RZ output stage.
In [168], the importance of the switching dynamics is emphasized. The differential
quad switching scheme is applied and kickback (variation of the source node voltage
of the switch) is minimized with switchdriver crossingpoint control.
In [146], attention is paid to the reduction of timing errors, and power supply and
bias disturbances targeting the elimination of the nonlinearity instead of removing it
136 Currentsteering digitaltoanalog converter design
from the output. Currentmode logic is used to reduce the supplyrail and substrate
cross talk. The timing of the switch drivers is equalized with a replica structure similar
to as the prototype presented in Section 7.2.
6.9 Survey of published D/A converters 137
Table 6.3 Survey of published D/A converter implementations.
Publication Process Bits Sampl.
freq.
[MHz]
SFDR
[dBc]
@
[MHz]
Area
[mm
2
]
Power
[mW]
Comment
Miki
[153]
2µm
CMOS
8 80 ? 3.79 145
Nakamura
[154]
1µm
CMOS
10 70 ? 3.78 170
Mercer
[160]
2µm Bi
CMOS
16 40 80 @
1.23
8.25 500 SFDR @
10MS/s
Lin [126] 0.35µm
CMOS
10 500 51 @
240
0.6 125
Bastos
[155]
0.5µm
CMOS
12 300 40 @
60
3.2 320
Bugeja1
[161]
0.5µm
CMOS
14 100 74 @
8.5
14.42 750
Van der
Plas [158]
0.5µm
CMOS
14 150 61 @ 5 13.10 300
Bugeja2
[162]
0.35µm
CMOS
14 100 72 @
42.5
11.83 180
Van den
Bosch1
[164]
0.35µm
CMOS
10 1000 61.2
@ 490
0.35 110 Core area
Van den
Bosch2
[163]
0.25µm
CMOS
12 500 62 @
125
7.14 102
Tiilikainen
[137]
0.18µm
CMOS
14 100 64 @ 1 1.0 20
Cong
[138]
0.13µm
CMOS
14 180 50 @
63
0.1 16.7 Power
@100MS/s,
core area
Schoﬁeld
[139]
0.25µm
CMOS
16 400 73 @
190
? 400
Hyde
[165]
0.18µm
CMOS
14 300 71 @
120
0.44 53 Power
@250MS/s,
core area
O’Sullivan
[166]
0.18µm
CMOS
12 320 60 @
60
0.44 82
Huang1
[167]
0.18µm
CMOS
14 200 60 @
90
1.0 97 RZmode,
core area
Huang2
[167]
0.18µm
CMOS
14 200 43 @
90
1.0 97 NRZmode,
core area
Schafferer
[168]
0.18µm
CMOS
14 1400 67 @
260
6.25 400
Doris
[146]
0.18µm
CMOS
12 500 60 @
220
1.13 216 Core area
Chapter 7
Prototypes and experimental
results
In this chapter, the methods used in the WCDMAprototype circuit design are described
and the measurement arrangements and the experimental results obtained from the
fabricated transmitter chip are reported.
The target of the design process was to advance our knowledge of the efﬁcient
realization of the DSP algorithms, discover the system limitations set by the digitalto
analog converter, learn more about the D/A converter design and apply the knowledge
gained to the design of the IF DSP part of the transmitter to see how the different
parameters affect the transmitter performance. The performance of the transmitter is
characterized by EVM and ACLR.
7.1 Prototype of WCDMA transmitter
The principle of the designed WCDMA transmitter is presented in Fig. 7.1. The trans
mitter consists of pulse shaping ﬁltering and interpolator blocks for four independent
I and Q data streams in order to alter the sampling rate from the input symbol rate
to the sampling rate used in the CORDIC vectorrotationalgorithmbased quadrature
modulators. After the modulation, the modulated carriers are summed and fed to the
inverse SINC predistortion ﬁlter [169]. The purpose of the ﬁlter is to eliminate the
SINC attenuation caused by the sampleandhold function of the D/A converter. Two
constant scalers are used to maximize the signal dynamics before feeding it to the D/A
converter. The values of the scalers are discovered with simulations. Finally, the data
is fed to the D/A converter. A 14bit current steering architecture is chosen because of
its capability in terms of highspeed operation and good static linearity. The design of
140 Prototypes and experimental results
L
L
B
a
s
e
b
a
n
d
D
S
P
Quadrature Modulation Pulse shaping
L
L
B
a
s
e
b
a
n
d
D
S
P
Quadrature Modulation Pulse shaping
L
L
B
a
s
e
b
a
n
d
D
S
P
Quadrature Modulation Pulse shaping
L
L
B
a
s
e
b
a
n
d
D
S
P
Quadrature Modulation Pulse shaping
DAC
Analog IF RF IF 2
Scaler Scaler
Inverse
SINC
I
Q
COS(Wt)
COS(Wt)
−1
SIN(Wt)
I
Q
COS(Wt)
COS(Wt)
−1
SIN(Wt)
I
Q
COS(Wt)
COS(Wt)
−1
SIN(Wt)
I
Q
COS(Wt)
COS(Wt)
−1
SIN(Wt)
LO1
LO2
Figure 7.1 Multicarrier transmitter.
Table 7.1 Design parameters of the system.
Symbol rate 3.84 Msymbols/s
Pulse shaping ﬁlter Rootraised cosine α = 0.22
Number of carriers 4
Assumed input signal statistics Normally distributed and truncated with crest factor 10
dB
Signal bandwidth 3.84MHz
Carrier spacing 5MHz
EVM Tested with 4QAM signal with symbol magnitude 40dB
below maximum
ACLR
123
Simulated with channel separation of 5, 10 and 15 MHz
respectively
Number of input bits 13
the IF ﬁlters, mixers and PA are beyond of the scope of this work.
The parameters and signal conditions used in the transmitter design are listed in
Table 7.1.
7.1 Prototype of WCDMA transmitter 141
7.1.1 Frequency planning
The design begins with the frequency planning. The number of carriers and carrier
spacing of 5MHz deﬁnes the total bandwidth that needs to be 19.68MHz. However,
in order to make the image ﬁltering possible after the D/A conversion and after the
upconversion to the second IF, the frequency band used is 5.1624.84MHz. To get the
ﬁrst image far enough to be ﬁltered, the sampling frequency should be selected high
enough. The lowest integer multiple of the input symbol frequency 3.84MHz that is
high enough to make the ﬁltering possible is 61.44MHz, which is selected to be the
clock frequency of the CORDIC rotator, resulting in the total interpolation ratio of 16
for the input data.
7.1.2 Interpolation strategy
In order to be able to select the most effective strategy for the interpolation, the total
number of ﬁlter coefﬁcients must be determined. The number of FIR ﬁlter coefﬁcients
required for the PSF with certain stopband and passband ripples and relative tran
sition bandwidth can be approximated with the equation that holds for the equiripple
lowpass FIR ﬁlter [58]
N
1
≈
−20log
10
√
σ
p
σ
s
−13
14.6∆f
+1 = K
L
1
F
s
f
s
− f
p
+1 L
1
> 1 (7.1)
in which K =−20log
10
√
σ
p
σ
s
−13, F
s
is the sampling rate at the input of the PSF,
L
1
is the oversampling ratio of the PSF, σ
p
and σ
s
are the passband and stopband
ripples, respectively, ∆f =
f
s
−f
p
L
1
F
s
is the width of the transition band relative to the
out sampling frequency of the PSF, and f
s
and f
p
are the stop and passband edge
frequencies, respectively.
When a chain of interpolation ﬁlters is used to perform the possible residual in
terpolation after the PSF, the number of taps required for each of these interpolation
stages may be calculated as
N
k
≈ K
L
k
L
pk
F
s
L
pk
F
s
−2f
s
+1 = K
L
k
1−
2 f
s
L
pk
F
s
+1 L
k
> 1, k > 1 (7.2)
in which L
k
is the interpolation ratio of the current stage, and L
pk
= ∏
k−1
i=1
L
i
. With
equations (7.1) and (7.2), the total number of coefﬁcients for each interpolation strat
egy can be calculated. It can be observed that the total number of ﬁlter coefﬁcients is
minimized either when the interpolation is made in four cascaded stages, each interpo
lating by factor two, or with the cascaded interpolation stages with interpolation factors
2, 2, and 4, respectively. Comparison of the efﬁciency of the interpolation strategies is
142 Prototypes and experimental results
2 2 2 2
Channel filter 1st Half band 2nd Half band 3rd Half band
Figure 7.2 Interpolation chain.
presented in Table 7.2. The four cascaded ﬁlter stages with an interpolation factor of 2
Table 7.2 Comparison of interpolation strategies
Order of inter
polators
Number of
coefﬁcients per
stage
Total number of
coefﬁcients
16 297 297
8, 2 149, 11 160
4, 4 74, 25 100
4, 2, 2 74, 13 ,11 99
2, 8 38, 84 122
2, 4, 2 38, 43, 11 92
2, 2, 4 38, 22, 24 84
2, 2, 2, 2 38, 22, 13, 11 84
is chosen because it facilitates the use of halfhand (HB) ﬁlters after the PSF. The use
of the HB ﬁlters further reduces the amount of hardware because approximately half of
their coefﬁcients are zero valued. The structure of the interpolation chain is presented
in Fig. 7.2.
7.1.3 Digital FIR ﬁlter and interpolator design
The multistep interpolation with an interpolation factor of 2 was chosen as an inter
polation strategy because of its hardware efﬁciency, After the decision on the inter
polation strategy, the ﬂoating point prototypes of the channel ﬁlters and the half band
interpolation ﬁlters were designed. The channel ﬁlter was designed with the Lagrange
algorithm described in Section 4.1.1. The half band ﬁlters were designed with the
least square error algorithm and with the “trick”method described in [62]. With this
method, an evenorder prototype ﬁlter with desired passband characteristics and a
transmission zero at half of the sampling frequency is converted to an oddorder half
band ﬁlter by inserting a zero between the coefﬁcients of the prototype and changing
the centermost zero to 1. In this design phase, some margin was left for the degradation
of the performance caused by CSD presentation and ﬁnite word length effects in order
to ensure that the performance of the transmitter can be designed to be limited by the
D/A converter.
7.1 Prototype of WCDMA transmitter 143
1.92 5.76 9.6 13.44 17.28 21.12 24.96 28.8
−100
−80
−60
−40
−20
0
Frequency responses of the filters
R
e
l
a
t
i
v
e
p
o
w
e
r
[
d
B
]
Frequency [MHz]
Figure 7.3 Frequency responses of the ﬁlters.
Once the coefﬁcients of the prototype ﬁlters were discovered, the coefﬁcients were
converted to CSD format with the modiﬁcation of the algorithm presented in [67]. The
algorithm was modiﬁed in order to maximize ACLR rather than to minimize the peak
ripple on the stopband.
The frequency responses of the designed ﬁlters are presented in Fig. 7.3 and the
frequency response of the interpolation chain is presented in Fig. 7.4. ISI
rms
of the
designed CSD interpolation ﬁlter chain is 45.022dB (0.561%) and ACLR values for
the ﬁrst, second and the third adjacent channel are 85.89dB, 99.13dB and 92.15dB,
respectively. The quantization noise due to the D/A conversion or ﬁnite word length
effects is not included at this point.
The lower limit of EVM is set by ISI of the channel ﬁlter. The ﬁnite accuracy of
the computation in the ﬁlters and CORDIC modulator, and the quantization in the D/A
converter adds noise to the signal thus increasing EVM. Similarly, the limit of ACLR is
set by the D/A converter, the stopband attenuation of the ﬁlters and the noise added by
the ﬁlters and CORDIC modulator. Since the 14bit D/A converter sets the ACLR value
approximately to 75dB, the objective of the design was to obtain EVM
rms
performance
better than 40dB (1%) and ACLR to be limited by the D/A converter.
After the CSD coefﬁcients were discovered, the analysis of the ﬁnite word length
effects was performed. The simulation script was written in Matlab that modeled the
144 Prototypes and experimental results
1.92 5.76 9.6 13.44 17.28 21.12 24.96 28.8
−120
−100
−80
−60
−40
−20
0
Frequency responses of the cascaded filters
R
e
l
a
t
i
v
e
p
o
w
e
r
[
d
B
]
Frequency [MHz]
Figure 7.4 Frequency response of the interpolation ﬁlter chain.
behavior of the transmitter. The effects of the CORDIC and inverse SINC ﬁlter were
left out at this point, and an ideal upconversion and reception was used. The D/A con
verter was modeled as a quantization at the transmitter output. A normally distributed
and truncated data stream with the crest factor of 10dB was used as the input in ACLR
simulations in order to model the sum of 4 QAM data of 100 code channels (central
limit theorem [19]). In EVM simulations, the single 4 QAM modulated signal with a
symbol magnitude of 40dB below the maximum was used. The internal word length
of one ﬁlter was swept from 10 to 20 bits when the internal word lengths of the other
ﬁlters were kept at 20 bits. With this method, the effects of the one single ﬁlter to ACLR
and EVM were discovered. In Fig. 7.5, the effects of the internal word lengths and the
effect of the D/A converter on ACLR
1
are presented. The effects on EVM are presented
in Fig. 7.6. Similar simulations were carried out for ACLR
2
and ACLR
3
. The internal
word lengths chosen for the channel ﬁlter (pulse shaping ﬁlter) and for the ﬁrst, second
and third halfband ﬁlters are 17, 18, 18, and 18 respectively. The simulated ACLR
123
values with the ﬁnite word length effects included in the ﬁlters are 73.92dB, 75.62dB
and 73.70dB, respectively, and the EVM
rms
is 40.5398dB (0.94%).
The polyphase structure that was described in section 4.3.1 was used in the realiza
tion of the ﬁlters. In order to further reduce the area used by the ﬁlters, the interleaving
technique described in Section 4.3.2.3 was used [71]. In addition to the area reduction,
7.1 Prototype of WCDMA transmitter 145
11 12 13 14 15 16 17 18 19 20
−90
−85
−80
−75
−70
−65
−60
−55
−50
−45
Adjacent channel power ratio
R
e
l
a
t
i
v
e
p
o
w
e
r
[
d
B
]
Number of bits
PSF
HB1
HB2
HB3
D/A
D/A− limit
Figure 7.5 ACLR
1
as a function of the internal word lengths.
11 12 13 14 15 16 17 18 19 20
−50
−45
−40
−35
−30
−25
−20
−15
−10
Error vector magnitude
R
e
l
a
t
i
v
e
p
o
w
e
r
[
d
B
]
Number of bits
PSF
HB1
HB2
HB3
D/A
D/A− limit
Figure 7.6 EVM
rms
as a function of internal word lengths and D/A converter resolution.
146 Prototypes and experimental results
8 pcs
F 16*F
16*F
I1
Q1
I2
Q2
I3
Q3
I4
Q4
To CORDICs
16*F
2 2
2
2
16*F
2
2
2
2
Figure 7.7 Pipelined/Interleaved interpolation ﬁlter chain.
Table 7.3 Number of ﬁlter coefﬁcients and the number of realized coefﬁcients in polyphase
decomposition.
Channel
ﬁlter
1
st
half
band
2
nd
half
band
3
rd
half
band
Number of coefﬁcients 37 23 11 11
Maximum number of terms in CSD
coefﬁcient
6 5 4 4
Maximum shift in CSD coefﬁcient 13 13 12 12
Number of realized coefﬁcients
in polyphase composition (subﬁlter
1/subﬁlter 2)
9/10 6/1 3/1 3/1
Internal word length 17 18 18 18
the advantage of using the interleaving technique is that all the clock frequencies used
in the ﬁlters are above the desired signal frequency band, reducing the possible spurs
generated by substrate coupling. The clock frequencies were selected so that the maxi
mum clock frequency equals the one used in the CORDIC rotator, 61.44MHz. The ﬁrst
ﬁlter, however, uses a clock of only 30.72MHz because there are only 8 data streams
to interleave and because the polyphase structure allows the computation at half of the
sampling frequency (sampling frequency after the interpolation). The structure of the
interleaved interpolation ﬁlter chain is presented in Fig. 7.7. The number of ﬁlter coef
ﬁcients and realized ﬁlter coefﬁcients in the polyphase composition are listed in Table
7.3.
The simulated ACLR and ISI
rms
and EVM
rms
values for the CSDﬁlters without
and with the ﬁnite word length effects are listed in Table 7.4.
7.1 Prototype of WCDMA transmitter 147
Table 7.4 ACLR and ISI
rms
/EVM
rms
values.
ACLR
1
ACLR
2
ACLR
3
ISI
rms
and EVM
rms
Without internal
word length effects
85.89dB 99.13dB 92.15dB 45.022dB (0.561%)
With internal word
length effects
73.92dB 75.62dB 73.70dB 40.5398dB (0.94%)
7.1.4 CORDIC and inverseSINC ﬁlter design
7.1.4.1 CORDIC design
The word lengths of the CORDIC and the inverse SINC ﬁlter were determined in a
manner similar to that in the interpolation ﬁlter chain. The output of the interpolation
ﬁlter chain was used as the input of the CORDIC rotator and the number of stages
(N = 15) (Fig. 5.4), number of bits in the amplitude path (a = 20) and the number of
bits on the phase calculation path (p = 17) were discovered.
According to the theory presented in Section 5.2, the maximum output value of the
CORDIC rotator is A
outmax
= 1.6468
√
2 = 2.3281, assuming the input values to be 1.
However, when summing up four modulated wide band signals, it is very unlikely that
the signal has the value 4A
outmax
. It can be calculated as in [170], that the I/Qmodulated
signal with Gaussian distributed I and Q data values and standard deviation σ is also
Gaussian distributed with standard deviation σ, and thus the multicarrier signal also
has a Gaussian distribution with variance linearly dependent on the number of carriers.
The simulated probability density of the sum of 1, 2, 3, and 4 wideband signals are
presented in Fig. 7.8, and the probability density function of the Gaussian distribution
with corresponding standard deviations are presented in Fig. 7.9
Since the ratio of the variance (i.e. power) and maximum amplitude does not
change as the number of carrier increases, the consequence is that the power of a sin
gle carrier is reduced relative to quantization noise, thus increasing EVM and ACLR.
Also, because the probability of overﬂow in the case of a limited number of bits is rel
ative to the standard deviation of the signal, the number of bits should be increased as
a function of standard deviation (
√
N, N = Number of carriers) instead of theoretical
maximum amplitude, in order to maintain the probability of overﬂows.
One method to handle the occasional overﬂows and reduce the overﬂow originated
signal degradation is clipping. To clip the large values of the multicarrier signal, the
saturating scaler is added to the output of the CORDIC. In the case when the peak
value of the signal is just slightly above the half of the full scale, approximately 6dB
of the dynamic range is lost when the signal is truncated. Scaler maximizes the dy
namic range of the signal and saturates the output in the cases of overﬂow. This also
minimizes the amount of hardware needed in the inverse SINC ﬁlter, since the internal
148 Prototypes and experimental results
−1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1
0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
Probability density function of the output
P
r
o
b
a
b
i
l
i
t
y
Normalized output value
1 carrier, σ=0.1080
2 carriers, σ=0.1542
3 carriers, σ=0.1884
4 carriers, σ=0.2183
Figure 7.8 Probability density function of simulated multicarrier signals.
−1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1
0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
Probability density function of the normal distribution
P
r
o
b
a
b
i
l
i
t
y
Normalized output value
σ=0.1080
σ=0.1542
σ=0.1884
σ=0.2183
Figure 7.9 Probability density functions of normal distribution with standard deviations of
simulated multicarrier signals.
7.1 Prototype of WCDMA transmitter 149
wordlength of the ﬁlter is reduced. The value of the scaler is determined by simula
tions. The effects of the clipping and various algorithms for clipping the wide band
signals are discussed in more detail for example in [171].
7.1.4.2 InverseSINC ﬁlter design
The inverseSINC predistortion ﬁlter is used to compensate the droop in the frequency
response of the transmitter caused by the sample and hold operation of the D/A con
verter. This droop is 2.476dB at 24.84MHz which is not acceptable.
The inverseSINC ﬁlter was designed by the method described in [169]. It has
7 coefﬁcients which are symmetric relative to the center coefﬁcient. The transposed
direct form is used in the realization of the ﬁlter. After correction, the gain ripple at
the band from 5.16 to 24.84MHz is 0.0895dB. The simulated internal word length for
the correction ﬁlter is 18 bits. A scaler similar to one after the CORDIC is used at the
output of the ﬁlter in order to maximize the signal dynamics. After scaling, the signal
is rounded to 14 bits and fed to the D/A converter.
7.1.5 Simulated QAM performance
After the internal resolution and the values of the scalers had been deﬁned, the overall
performance of the multicarrier QAM modulator was determined by simulation. The
ﬁnal EVM value is 40.38dB (0.96%), and the ﬁnal ACLR
123
values are 73.58dB,
75.58dB, and 73.65dB, respectively. The simulated spectrum of the multicarrier signal
at the transmitter output is presented in Fig. 7.10. The single carrier case is presented
in Fig. 7.11.
7.1.6 Digital ASIC synthesis ﬂow
The digital part of the QAM modulator was realized with logic synthesis based on high
level description language. The synthesis ﬂow is presented in Fig. 7.12.
Tools that was used for the synthesis were Synopsys Design Analyzer for the logic
synthesis and static timing veriﬁcation, Synopsys VSS for VHDL simulations, Syn
opsys Formality for static functional veriﬁcation, Cadence Envisia Design Planner
and Silicon Ensemble for ﬂoorplanning, Cadence Envisia Silicon Ensemble for place
and route, Cadence Envisia PBopt and CTgen for placementbased optimization and
clocktree generation and Mentor Graphics ICStation for toplevel manual editing,
layout versus schematic checking and designrule checking.
150 Prototypes and experimental results
2.5 7.5 12.5 17.5 22.5 27.5
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Power spectrum of modulator output
R
e
l
a
t
i
v
e
p
o
w
e
r
[
d
B
]
Frequency [MHz]
Figure 7.10 Spectrum of the multicarrier WCDMA signal at the output of the transmitter.
2.5 7.5 12.5 17.5 22.5 27.5
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Power spectrum of modulator output
R
e
l
a
t
i
v
e
p
o
w
e
r
[
d
B
]
Frequency [MHz]
Figure 7.11 Spectrum of the single carrier WCDMA signal.
7.1 Prototype of WCDMA transmitter 151
Yes
No
Matlab simulations
OK?
VHDL description
OK?
Logic synthesis
OK?
Static timing
verification
Static functional
Verification or
functional
simulation
OK?
OK?
Yes
Yes
Yes
Yes
No
No
No
No
Floorplanning
Timing driven
Placement
Is the failure in the
floorplanning or in
the logic synthesis?
Foorplanning
Logic synthesis
Clock tree generation
Timing driven
routing
Final routing
OK?
Static timing
verification
No
Yes
Top level manual
layout editing
LVS and DRC
OK?
No
Yes
To fabrication
Placement
optimization
Placement
optimization
Figure 7.12 Logic synthesis ﬂow
152 Prototypes and experimental results
Cascade transistors
Current switches
8 LSBs 6 MSBs
Vdd
Vb Vb
Vout+ Vout−
Binary
Weighted
2 Weighted
4 Unweighted
C
o
n
t
r
o
l
l
o
g
i
c
Data
in
clk
Figure 7.13 Block diagram of the D/Aconverter.
7.1.7 14bit 70MHz Digitaltoanalog converter
In this section, only the theory applied to this particular design is discussed. In case
a more accurate analysis of the design methods is performed after the design of this
prototype, references are given.
The D/A converter designed for the transmitter is a segmented current steering
type converter. It has two current source matrices. The matrix of 8 LSBs is binary
weighted and the matrix for the 6 MSBs is partially weighted. Two least signiﬁcant
bits of the MSB matrix are binary weighted and four MSB bits are thermometer coded
(unweighted). Each of the ﬁfteen MSB current sources corresponding to the four ther
mometer coded MSB bits provides a current of four times the least signiﬁcant bit of
the MSB matrix. The topology of the D/A converter is presented in Fig. 7.13.
7.1.7.1 Static matching
It was assumed as a coarse approximation that INL follows the normal distribution
with variance
σ
INLmax
=
2
N
−1
σ
lsb
I
lsb
. (7.3)
7.1 Prototype of WCDMA transmitter 153
The analysis of INL presented in Section 6.3 reveals that this assumption is not ab
solutely accurate, but gives a good starting point for the dimensioning of the current
sources.
Method for ﬁnding the dimensions of the current sources is presented in Section
7.2.1. The area of the LSB current source is obtained by using the matching equations
presented in [125], [124]
σ
2
id
I
2
d
=
4A
2
vt
WL(V
gs
−V
T
)
2
+
A
beta
√
WL
+B
beta
2
, (7.4)
where A
vt
, A
beta
and B
beta
are process dependent constants given by the silicon ven
dor, V
gs
is the gatesource voltage of the transistor, V
T
is the threshold voltage of the
transistor, W is the channel width and L is the channel length.
The area of the LSB current source required for 14bit matching, as determined by
equations Eq. (7.3) and Eq. (7.4), was too large to be realized. Therefore the area used
for the current source was determined in order to obtain 12bit linearity (INL and DNL
< 2LSB).
In order to increase output impedance of a single current branch, additional cascode
transistors were added between the load and the current switches. These transistors
were made common to all of the switches connected to the particular signal branch.
Cascode transistors are also used between the current switch and the current source
transistor to further increase the output impedance of the current sources. Analysis of
the behavior of the output impedance is presented in more detail in Sections 6.5 and
7.2. The topology of the one current source, switch and output cascode set is presented
in Fig. 7.14.
7.1.7.2 Enhancement of dynamic properties
In order to minimize the capacitive coupling, swing as small as possible is used to drive
the switches. It is also ensured that both of the switches are not closed at the same time,
which would lead to the situation where no current ﬂows through the current source.
In this case, the sources of the switch transistors would be driven to V
ss
. This would
cause a spike at the output, and the current sources would require a relative long time
to recover from the bounce. The switch driving principle is presented in Fig. 7.15.
Inaccuracies in synchronization of the switch drivers may cause harmonic distor
tion. Because the currents in LSB and MSB matrices are different, the switches are
also of different size, which minimizes the difference between bias points and thus im
proves the static matching. The synchronization of switching is enhanced by adding
dummy transistors in parallel with the gates of the smaller LSB switches in order to
equalize the load seen by the switch driver (Fig. 7.16).
154 Prototypes and experimental results
V
dd
V
ss
I
bias
V
c1
V
s
V
s
c2
V
c2
V
V
ss
Figure 7.14 One set of current source, switches and cascode transistors.
V
s
V
s
Optimal swing
Figure 7.15 The switching waveform.
7.1 Prototype of WCDMA transmitter 155
V
ss
V
ss V
ss
I
out
I
out
V
s V
s
Figure 7.16 Dummy transistor as additional load.
156 Prototypes and experimental results
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d d d d d d d d d d d d d d d d d d d
d d d d d d d d d d d d d d d d d d
d d
d d d d
d d
24 11 22 13 20 15 18 16 19 14 21 12 23 10
17 16 19 14 21 12 23 8 10 24 9 11 22 17 20 15 18 13
13 18 15 20 17 22 11 9 24 10 m 23 12 21 14 19 16 17
10 23 12 21 14 19 16 18 15 20 13 22 11 24
Figure 7.17 The common centroid MSB current source matrix.
7.1.7.3 Layout issues
In order to achieve the best possible static matching, it is preferable to make the en
vironment of each current source identical to each other. The best way to do this is
to put the current sources in matrices and add some dummy transistors around the
current source transistors. It is also preferable to use the common centroid approach
when drawing the matrices in order to minimize the effect of the lineargradienttype
processing parameter variation as the function of position on the wafer. It is also prefer
able that the transistors are arranged so that all of the transistors of one source are not,
for example, on the periphery of the matrix. A better way is to balance the location so
that the mean distance from the center of the matrix is constant. This means that, if
two transistors of the single current source are at the edge of the matrix, another two
are near the center. The method used for the MSB current source matrix is presented
in Fig. 7.17. The sources are numbered from 8 to 24. The transistor marked with ”m”
is for current mirroring. The transistors labeled with 8 and 9 are the weighted sources
consisting of 1 and 2 transistors, respectively. The rest of the current sources have 4
transistors each. The common centroid matrix approach has also been used in the bias
generation. The layout techniques for improving the static matching are analyzed more
thoroughly in Sections 6.8 and 7.2.3.
In addition to the static matching optimization by common centroid matrices, the
dynamic performance is enhanced by using different supply voltage sources for the
analog part and bias, switch drivers and digital logic. Also, guard lines are used wher
ever possible. Ground planes are also added to decrease the capacitive coupling be
tween the digital and analog signals.
7.1.7.4 D/A converter simulations
The simulations for the spectral purity of the D/A converter were carried out with sinu
soidal signals of different frequencies. The sampling frequency used for the simulation
was 66.67MHz. In Fig. 7.18 a spectrum of a 5.43MHz sine signal is presented. It can
7.1 Prototype of WCDMA transmitter 157
2.5 7.5 12.5 17.5 22.5 27.5
−120
−100
−80
−60
−40
−20
0
Power spectrum
F
r
e
q
u
e
n
c
y
[
M
H
z
]
Relative power [dBc]
Figure 7.18 Spectrum of 5.43MHz sine signal.
be seen that the third and the ﬁfth harmonic component dominates SFDR and that the
level of the even harmonics is low. The values for the 3
rd
and 5
th
harmonic components
are 80.32dB and 89.92dB, respectively.
In Fig. 7.19 the signal frequency of the sine is increased to 28.5MHz. Now the
dominant components of SFDR are the 2
nd
and the 3
rd
harmonic component.
7.1.8 Experimental results
The chip was fabricated in a 5 metal 2 poly 0.35µm BiCMOS process, but only CMOS
transistors were used. Isolation between the digital part of the chip and the D/A con
verter is achieved by the usage of isolation rings. The same kind of isolation is also
available in triple well CMOS processes. The design features that are not available in
conventional CMOS processes are also used. Such features are, for example, isolated
NMOS transistors.
7.1.8.1 Measurement setup
The measurement setup for the circuit is shown in Fig. 7.20. The parallel port of the PC
is used to control the functionality of the chip. The control program, which controls
the parallel port, is written in C programming language [172]. With the program, it
158 Prototypes and experimental results
2.5 7.5 12.5 17.5 22.5 27.5
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Power spectrum
F
r
e
q
u
e
n
c
y
[
M
H
z
]
Relative power [dBc]
Figure 7.19 Spectrum of 28.5MHz sine signal.
PC
Pattern
Generator
Measurement
PCB
Clock Signal
Generator
Spectrum
Analyzer
Voltmeter
DC power supply
with current meter
Figure 7.20 Measurement setup for the circuit.
is possible to set the carrier frequencies and select which part of the chip is tested.
It is possible to test each of the ﬁlters separately and also to test the CORDICs by
selecting either one or all of them to be used. The D/A converter can be measured
either as connected to the digital transmitter or in a standalone mode. Manufacturers
7.1 Prototype of WCDMA transmitter 159
Table 7.5 Types of the measurement equipment
Pattern generator Tektronix TLA 720
Clock signal generator RohdeSchwartz 1062.5502.11
Voltmeter HewlettPackard 3457A
Spectrum/Vector analyzer RohdeSchwartz 1088.3494.30/FSIQ
DCsupply HewlettPackard E3631A
and models of the measurement equipment are listed in the Table 7.5.
7.1.8.2 D/Aconverter performance
The dynamic performance of the D/Aconverter was measured with the sample fre
quency of 61.44MHz and the static performance with the sample frequency of 1Hz.
The supply voltage was 3V, which is the typical operation condition for the converter
used in the transmitter. The bias current of the current source matrices was 200µA,
as designed; however, the bias current for the switching level setting were increased
from 100µA to 450µA in order to lower the switching voltage levels at the input of
the switches. It is assumed that this enhances the dynamic performance of the D/A
converter because the switches stay better in the saturation region when they are open,
resulting in a reduced level of the 2
nd
harmonic component.
7.1.8.3 Static performance of the D/Aconverter
The static performance of the D/Aconverter is characterized by the differential non
linearity and integral nonlinearity. These are measured by feeding the ramp signal with
1 LSB step to the D/Aconverter operating with a 1Hz sampling frequency. The mea
sured DNL and INL are presented in Fig. 7.21. The maximum absolute values of DNL
and INL are 1.87LSB and 2.165LSB, respectively.
In Fig. 7.22 the ideal sine signal is fed to the Matlab function that distorts the
signal with the static nonlinearities of the D/Aconverter. It can be seen that the static
nonlinearities limits the spurious free dynamic range to be about 83dB.
7.1.8.4 Dynamic performance of the D/Aconverter
In Figs 7.23  7.30 the spectra of the sine signals of frequencies 1, 3, 7.5, 12.5, 17.5,
22.5, 27.5 and 30MHz are presented. It can be seen that the third harmonic domi
nates at the low frequencies. The second harmonic increases as the signal frequency
is increased and becomes dominant at the signal frequencies near half of the sampling
frequency. The spurious free dynamic range of the converter vs. signal frequency is
presented in Fig. 7.31.
160 Prototypes and experimental results
2000 4000 6000 8000 10000 12000 14000 16000
−2
−1
0
1
2
Static nonlinearities relative to LSB
D
N
L
[
L
S
B
’
s
]
Number of sample
2000 4000 6000 8000 10000 12000 14000 16000
−2
−1
0
1
2
I
N
L
[
L
S
B
’
s
]
Number of sample
Figure 7.21 Differential and integral nonlinearities of the D/Aconverter.
2.5 7.5 12.5 17.5 22.5 27.5
−120
−100
−80
−60
−40
−20
0
Sine signal under influence of static nonlinearities
R
e
l
a
t
i
v
e
p
o
w
e
r
[
d
B
c
]
Frequency [MHz]
Figure 7.22 Sine signal distorted with the static nonlinearities.
7.1 Prototype of WCDMA transmitter 161
Figure 7.23 Spectrum of the 1MHz sine signal.
Figure 7.24 Spectrum of the 3MHz sine signal.
162 Prototypes and experimental results
Figure 7.25 Spectrum of the 7.5MHz sine signal.
Figure 7.26 Spectrum of the 12.5MHz sine signal.
7.1 Prototype of WCDMA transmitter 163
Figure 7.27 Spectrum of the 17.5MHz sine signal.
Figure 7.28 Spectrum of the 22.5MHz sine signal.
164 Prototypes and experimental results
Figure 7.29 Spectrum of the 27.5MHz sine signal.
Figure 7.30 Spectrum of the 30MHz sine signal.
7.1 Prototype of WCDMA transmitter 165
0 5 10 15 20 25 30
45
50
55
60
65
70
75
80
85
Spurious Free Dynamic Range
S
F
D
R
[
d
B
]
Frequency [MHz]
Figure 7.31 Spurious free dynamic range vs. signal frequency.
Figure 7.32 Spectrum of multiple carriers.
In Fig. 7.32 the spectrum of the sum of four carrier signals of frequencies 7.5, 12.5,
17.5, and 22.5MHz is presented.
166 Prototypes and experimental results
Figure 7.33 Wideband signal at 7.5MHz.
The total power dissipation of the D/A converter was measured to be 141mW. The
high power dissipation is mostly due to the static current ﬂowing through the switch
drivers. The contribution of the switch drivers to the power consumption is 93mW.
The static current is used to set the level of the switch driving voltage. The power con
sumption can be reduced if an invertertype driver is used to drive the switch. However,
then the voltage level has to be generated by other means, with the regulator outside
the chip, for example. The area of the D/A converter is 3.45mm
2
.
7.1.8.5 QAM Performance
The QAM performance was measured with normally distributed and truncated data
with the crest factor of 10dB. In the multicarrier case, the data had to be scaled with the
factor of 0.9 before the transmission because of a slight bug in the system. There was
saturating adders at the output of the CORDIC. If the two signals saturates the adder
and the third signal has the opposite sign, the signal is no longer saturated, and the
step type error is generated, resulting in spurs generated on the sidebands. The system
clock frequency was 61.44MHz. The data was fed to the transmitter with the pattern
generator which was synchronized to the system clock. ACLR was measured with the
spectrum analyzer. The spectra of the WCDMA signal with different combinations of
the carrier frequencies are presented in Figs 7.33  7.37.
EVM was measured with the single and four carriers each modulated with 4 QAM
signals with the symbol magnitude 40dB below the maximum. The measured constel
7.1 Prototype of WCDMA transmitter 167
Figure 7.34 Wideband signal at 12.5MHz.
Figure 7.35 Wideband signal at 17.5MHz.
168 Prototypes and experimental results
Figure 7.36 Wideband signal at 22.5MHz.
Figure 7.37 Multicarrier WCDMA signal.
7.1 Prototype of WCDMA transmitter 169
Re f L v l
 4 0 d Bm
Re f L v l
 4 0 d Bm
Re f L v l
 4 0 d Bm
Re f L v l
 4 0 d Bm
 4 . 1 6 6 6 6 6 7 4 . 1 6 6 6 6 6 7 REAL
CF 1 2 . 5 MHz
SR 3 . 8 4 MHz SR 3 . 8 4 MHz
Me a s Si g n a l
Co n s t e l l a t i o nCo n s t e l l a t i o n
De mo d QPSK De mo d QPSK
I MAG
T1
)
Re f L v l
 4 0 d Bm
Re f L v l
 4 0 d Bm
Re f L v l
 4 0 d Bm
Re f L v l
 4 0 d Bm
CF 1 2 . 5 MHz
SR 3 . 8 4 MHz SR 3 . 8 4 MHz
Sy mb o l / Er r o r s
De mo d QPSK De mo d QPSK
*
 1 . 5
1 . 5
1
Ma r k e r 1 [ T1 ] 4 2 1 . 0 0 s y m
Ma g n i t u d e 9 9 9 . 3 6 7 m
Ph a s e 1 3 4 . 2 0 d e g
0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 0 1 1 1 1 0 0 1 0 1 1
4 0 1 1 1 0 1 1 0 0 1 1 1 1 1 1 0 1 1 0 1 0 1 1 0 0 0 0 1 1 0 1 0 1 1 0 1 1 0 1 1 1
8 0 1 1 0 1 0 0 1 0 0 1 1 1 0 1 1 1 1 0 0 1 1 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1 1 1 0 1
Ma r k e r 1 [ T2 ] 0 s y m
Va l u e 2
E r r o r S u mma r y
E r r o r V e c t o r Ma g 1 . 3 3 % r ms 3 . 0 9 % P k a t s y m 1 0 6
Ma g n i t u d e E r r o r 1 . 0 5 % r ms  3 . 0 6 % P k a t s y m 2 6 8
P h a s e E r r o r 0 . 4 7 d e g r ms 1 . 4 8 d e g P k a t s y m 1 0 6
F r e q E r r o r  3 . 6 6 H z  3 . 6 6 H z P k
Amp l i t u d e Dr o o p 0 . 2 7 d B / s y m Rh o F a c t o r 0 . 9 9 8 2
I Q Of f s e t 0 . 0 4 % I Q I mb a l a n c e 0 . 0 5 %
D a t e : 4 . D E C . 2 0 0 0 1 6 : 0 6 : 5 5
S ym b o l T a b l e
Figure 7.38 Signal constellation and statistics of EVM measurement.
lation for the 22.5MHz carrier and the corresponding EVM, phase error and amplitude
error are presented in Fig. 7.38. The supply voltage of the digital signal processing
part has a huge effect on the total power consumption of the transmitter. The lowest
possible supply voltage for the digital part was determined by measurement. The de
pendence of the power consumption and the supply voltage is presented in Fig. 7.39.
The minimum supply voltage that the digital transmitter operated with was 2.165V and
the maximum clock frequency that the transmitter operated with a 3V supply voltage
was 73MHz. The measured performance metrics are listed in Table 7.6.
ACLR speciﬁcation of the WCDMA base station transmitter [20] is 45 and 50dB
for ACLR
12
and 17.5% for EVM. It can be said that this digital IF part of the mul
ticarrier WCDMA base station transmitter is applicable to the 3
rd
generation wireless
communications systems. There is also some margin left for the signal degradation in
the analog signal processing part.
170 Prototypes and experimental results
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3
600
700
800
900
1000
1100
1200
1300
1400
Power dissipation of the DSP
P
o
w
e
r
[
m
W
]
Supply voltage [V]
Figure 7.39 Power dissipation of the digital transmitter as a function of the supply voltage.
Table 7.6 Measured performance characteristics of the transmitter.
Symbol rate 3.84MHz
Channel bandwidth 3.84MHz
Carrier spacing 5MHz
Nominal clock frequency 61.44MHz
Worst case ACLR
12
in single carrier case
(22.5MHz carrier)
62.09/62.76 dB
ACLR in multicarrier case 57.80/58.14dB
Worst case EVM
rms
37.5 dB(1.33%)
Power dissipation with nominal (3V) digital
power supply
1.33W+141mW=1.47W
Power dissipation with optimal (2.165 V) power
supply
660mW+141mW=801mW
Maximum operation frequency 73MHz
Area die/core/D/A converter 25.75/19.18/3.45mm
2
7.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 171
T
h
e
r
m
o
m
e
t
e
r
c
o
d
e
r
+
d
i
g
i
t
a
l
c
a
l
i
b
r
a
t
i
o
n
D1
Vdd
Switches
bits (+0.5, 0.25 &0.125
calibration)
63 (+4)
DNL
Measurement
6 thermometer coded
MSB bits (+4 sources for
10 Binary weighted LSB
10 (+3)
10 (+3)
63 (+4)
Cascode transistors
sources for calibration
R
Vdd
R
Out+ Out−
2
−
t
o
1
M
U
X
Serial controlregister
20
20
D2
S
w
i
t
c
h
d
r
i
v
e
r
f
l
i
p
−
f
l
o
p
s
Analog bias circuitry
Off chip
Figure 7.40 Block diagram of the prototype
7.2 Prototype of the 16bit 400 MS/s D/Aconverter with
digital calibration
In this section, the design and experimental results of a 16bit 400 MS/s D/A converter
prototype fabricated in a 3.3V 0.35 µm SiGe BiCMOS process are presented. The
converter is designed with CMOS transistors only.
The designed converter consists of converter core, digital calibration circuitry, con
trol registers, and measurement circuitry for the current source mismatch. The block
diagram of the converter is presented in Fig. 7.40.
The architecture is a segmented currentsteering converter with 6 thermometer
coded and 10 binaryweighted bits. Four thermometercoded current sources are added
to MSB sources in order to introduce redundancy in the transfer function. Redundancy
is required by the calibration algorithm as described in Section 6.4. Three additional
binaryweighted current sources with weights 0.5, 0.25, and 0.125 LSB, respectively,
are added in order to have adequate resolution for the calibration. The 2to1 multi
plexer (MUX) is used at the input, in order to be able to achieve 400MS/s input data
rate.
Fig. 7.41 represents the single current branch and switch set used in the converter.
Two cascode transistors are used to increase the output impedance and reduce the dis
tortion due to output impedance variation. An additional set of switches is used to
enable the differential quadrature switching scheme [151] [168], which will be dis
cussed later in this section.
172 Prototypes and experimental results
T D
RL RL
o+ o−
Vc2
Vc1
Ibias
T D T D T D
Figure 7.41 Single current branch of the converter.
7.2.1 Current source dimensions and DC matching
Once the DC operation point of a current branch was deﬁned in order to have adequate
output swing and large enough V
ds
for all the transistor in order to keep them in the
saturation region, the dimensions for the current source transistors were determined in
order to have adequate matching. Even though the usage of calibration alleviates the
matching requirement of the MSB current sources, the matching of the LSB sources is
important since it will deﬁne the quality of the calibration and thus the static linearity
of the converter. The methods for analyzing the INL and DNL behavior as a function
of matching were discussed in detail in Section 6.3.
Assuming the standard deviation of the maximum value of the INL is related to the
standard deviation of the current source as
σ
INLmax
=C
1
2
N
−1
σ
lsb
I
lsb
, (7.5)
as presented in Section 6.3.3, and by deﬁning the INL yield to be
Yield
INL
= P(−INL
limit
≤MAX (INL) ≤INL
limit
) (7.6)
= P(−C
2
σ
INLmax
≤MAX (INL) ≤C
2
σ
INLmax
) (7.7)
7.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 173
we obtain
σ
INLmax
≤
INL
limit
C
2
, (7.8)
σ
LSB
I
LSB
≤
INL
limit
C
1
C
2
√
2
N
−1
(7.9)
=
INL
limit
C
√
2
N
−1
, (7.10)
in which the product of constants C
1
and C
2
can be combined in a single constant C.
Combining the transistor matching equation Eq. (6.5) and Eq. (7.10), the product
of channel width and length of the current source transistor are obtained as
WL =
4A
2
vt
(V
gs
−V
T )
2
+A
2
β
INL
2
limit
C
2
(2
N
−1)
−
4S
2
vt
D
2
(V
gs
−V
T )
2
−S
2
β
D
2
, (7.11)
In which D is the average separation of two current sources. On the other hand, for the
MOS transistor in saturation holds
W
L
≈
2I
lsb
µ
o
C
ox
(V
gs
−V
T
)
2
. (7.12)
Together these two equations determine the dimensions of the LSB current source tran
sistor.
It can be observed from the MonteCarlo simulation curves presented in Section
6.3.3 that, by choosing C ≈ 2 , Yield
INL
very close to 100% should be achieved.
In the early phase of the design process, it was assumed as a coarse simpliﬁcation
that the maximum absolute value of the INL follows the normal distribution, and, by
selecting C = 3, the Yield
INL
= 99.7 should be obtained. However, in the 16bit case,
the total area required would become very large. Therefore the dimensions of the
current sources are determined by the maximum area that can be used for the converter.
Due to the limited area available, it was decided to increase the error limit to be
INL
limit
= 8, which corresponds to the linearity requirement of a 12bit converter. Re
ferring to research results presented in Section 6.3, it can be stated that, when compar
ing the above mentioned approximation method and MonteCarlo simulation results,
the same area of the current sources is obtained with C = 2 and INL
limit
≈ 5.33, indi
cating that, with the used current source area, nearly 100% of converters should have
INL ≤5.33 instead of INL ≤8. The area required for 16bit matching (INL
limit
= 0.5,
C = 2) is 113.7 times the current area, assuming the effect of increased distance be
tween sources is negligible. On the other hand, there exists an optimum area of the
current source that gives the best matching for a certain number of bits, as presented in
174 Prototypes and experimental results
[173]. Assuming that the average distance between the current sources is
D =
2(2
N
−1)WL, (7.13)
the area WL that results minimizes the
σ
LSB
I
LSB
in Eq. 7.10 can be calculated to be
WL
opt
=
4A
2
vt
+2A
2
β
(V
gs
−V
T
)
2
4S
2
vt
(2
N
−1) +2S
β
(2
N
−1)(V
gs
−V
T
)
2
(7.14)
Increasing the area beyond this limit will, however, exacerbate the matching. How
ever, at the time of designing the prototype, the accurate information of the transistor
matching as a function of distance between transistor was not known.
7.2.2 Output impedance
As analyzed in Section 6.5, the variation of the output impedance may have a signif
icant effect on the harmonic distortion of a current steering D/A converter. Increas
ing the W and L of the switches instead of using minimum L increases the switching
impedance, as presented in Section 6.5. Simulation results for simultaneously stepping
the W and L of the MSB switch from minimum to 5 times the minimum is presented
in Fig. 7.42. The impedance value is 20log
2
10
×Z
umsb
50
corresponding to the effect of
MSB current source referred to the value of LSB unit impedance.
Increasing the W and L rapidly increases the Z
u
. The practical scaling range is from
1 to 5 times the minimum due to the fact that the area of the switches can not be further
increased due to the ﬁnite driving capability of the switch drivers. Also, capacitive
coupling may introduce undesired behavior if the area of the switches becomes large.
Fig. 7.42 indicates that the pole p with ω
p
≈
g
ds3
g
ds2
g
ds1
C
3
g
m3
g
m2
of Eq. (6.68) dominates
when the scaling factor is larger than 2, and therefore the impedance on the frequency
range from 10kHz to about 100MHz cannot be further improved by scaling the switch
transistor dimensions (in contrast to the situation presented in Fig. 7.43). Further
increasing the scaling factor will move the dominant pole to lower frequencies and
increase the DC impedance, which is already large enough. It can also be observed that
the capacitance of the source node of the switches (C
3
in Fig. 6.44) is determined by the
transistor area, since the frequency of the zero z
2
with ω
z2
≈
g
m4
C
3
scales down according
to transistor scaling. Moving down the zero also improves the impedance performance
from 100MHz to 200MHz, i.e. near the Nyquist frequency of the converter, which is
as desired.
In order to demonstrate the frequency behavior of the Z
u
in the presence of the
routing capacitance of current source matrices, the value of the current source capacitor
7.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 175
10
0
10
2
10
4
10
6
10
8
10
10
120
140
160
180
200
220
240
Z
u
of the LSB source
R
e
l
a
t
i
v
e
i
m
p
e
d
a
n
c
e
t
o
5
0
Ω
[
d
B
]
Frequency [Hz]
Scale 1
Scale 2
Scale 3
Scale 4
Scale 5
Figure 7.42 Effective Z
u
of MSB current source reduced to LSB unit switch.
(C
1
in 6.44) is increased to C
1
= 1.2nF, which corresponds to an about 800x800µm
2
metalmetal capacitor in a typical CMOS process. This ensures the C
1
causes the
dominant pole. The result of the simulation is presented in Fig. 7.43. In this case, the
scaling of the switch effectively improves Z
u
on the frequency range from 10KHz to
1MHz according to scaling of
g
m4
g
ds3
, since the pole due to C
3
is not dominant. The zero
z
2
is moved down in frequency according to scaling of C
3
.
In both cases, the usage of the scaling factor 3 is justiﬁed due to improvement of the
impedance within the frequency ranges from 10KHz to 1MHz and from 100MHz to
200MHz. A greater improvement is achieved if C
1
initially causes the dominant pole.
There also seems to exist an additional zero around 1GHz, which is not present in the
smallsignal analysis. However, it is above the Nyquist frequency, thus not affecting
the performance of the converter. Figure 7.44 represents the theoretical SFDR values
obtained with current switch dimensions. The true SFDR performance due to ﬁnite
output impedance lies somewhere between the lines presented in Fig. 7.44, due to the
fact that perfect differentiality can not be achieved.
176 Prototypes and experimental results
10
0
10
2
10
4
10
6
10
8
10
10
120
140
160
180
200
220
240
Z
u
of the LSB source
R
e
l
a
t
i
v
e
i
m
p
e
d
a
n
c
e
t
o
5
0
Ω
[
d
B
]
Frequency [Hz]
Scale 1
Scale 2
Scale 3
Scale 4
Scale 5
Figure 7.43 Effective Z
u
of MSB current source reduced to LSB unit switch when routing
capacitance C
1
is very large.
10
0
10
2
10
4
10
6
10
8
10
10
50
100
150
200
250
300
SFDR as a function of output impedance
S
F
D
R
[
d
B
c
]
Frequency [Hz]
Differential
Single−ended
Differential−C
1
large
Single−ended−C
1
large
Figure 7.44 Effect of the output impedance on SFDR of the converter.
7.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 177
MY Q MXY MX
MX MXY MY Q
Q
Q
MXY MX MY
MY MX MXY
Figure 7.45 MSB current source matrix.
7.2.3 Current source matrices
The current source matrices were designed by using 16 submatrices mirrored in X,
X or both directions in order to produce one commoncentroid current source matrix
that effectively reduces the effect of both even and oddorder gradients. The principle
of the mirroring is presented in Fig. 7.45
The submatrix Q in Fig. 7.45 was designed by applying the optimal sequences
both in x and y direction simultaneously, as presented in 6.8. Sequences were chosen
in order to minimize the effect of evenorder gradient, since the residual gradient not
canceled by symmetry will be of even order. Suitable shape of the matrix is obtained
by using 8x9 grid with four dummies in the corners. The matrix of 67 MSB current
sources and a mirroring transistor are presented in Fig. 7.46. When a dummy transistor
is encountered while placing the current sources according to the sequences presented
in Fig. 7.46, the current source is placed in the next available position. Therefore
source ”3” is not in the corner [3,3], but in the xyposition [4,4], which is the next
available position.
Fig. 7.47 represents the comparison between the maximum absolute value of INL
as a function of the plane angle θ (see Eq. 6.128). It can be seen that the evenorder
optimal sequence results in a smaller error, since it cancels out the residual evenorder
error more effectively than the linear sequence.
Fig. 7.48 represents the comparison between the maximum absolute value of INL
as a function of the plane angle θ in the case where the submatrices are placed in a
4x4 matrix with no mirroring in any direction. Comparison between the Figs 7.47 and
7.48 reveals that most of the beneﬁt is achieved by using mirror symmetry, whereas the
sequence has a large effect when no mirroring is used.
178 Prototypes and experimental results
D
D
53 19 11 36 62
4 21 55 38 46 64
32 M 49 66
D
13
D
44
29
40 7 58 24
47 30 65 14 39 56 5 22
10 61 27 43 2 18 52 35
63 45 12 28 54 3 37 20
25 8 41 59 16 33 67 50
17 1 34 51 9 26 60 42
23 57 6 31 48 15 7
1
9
4
2
6
8
5
3
3 1 5 7 2 4 8 6
0
0
Figure 7.46 MSB submatrix and the optimal sequences used for evenorder gradient cancella
tion.
0 50 100 150 200 250 300 350
0
0.05
0.1
0.15
0.2
0.25
INL obtained by optimal sequence sub−matrices
Plane angle θ [deg]
M
A
X
A
B
S
I
N
L
[
L
S
B
]
Even−order, mirroring
Odd−order, mirroring
Figure 7.47 Maximum absolute INL with various plane angles.
7.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 179
0 50 100 150 200 250 300 350
0
2
4
6
8
10
12
INL obtained by optimal sequence sub−matrices
Plane angle θ [deg]
M
A
X
A
B
S
I
N
L
[
L
S
B
]
Even−order no mirroring
Odd−order, no mirroring
Figure 7.48 Maximum absolute INL with various plane angles.
The layout of the binaryweighted LSB matrix was designed by using principles
presented in Section 6.8. In order to reduce the error between the MSB and LSB
matrices, the current sources are biased with current mirroring ratio 1:2, resulting in
the bias current of the LSB sources to be half of the bias of the MSB sources. This
reduces the effect of the gain error of bias current mirroring, since the bias current
in the LSB matrix is divided when the actual currents are formed, instead of being
multiplied, which would multiply also the gain error.
7.2.4 Dynamic performance
In addition to codedependent output impedance variation, the dynamic performance
(SFDR) of the converter is determined by, for example, jitter and timing differences be
tween signal paths to and fromthe switches. The distortion due to codedependent jitter
can be effectively reduced by using the differential quad switching scheme (Fig.7.41)
[151] and duplicated ”toggle”signal path [168] [139]. The toggle signal changes its
state on those clock cycles on which the actual data bit does not change its state. This
ensures that the circuit activity, and thus the powerrail interference, is constant, and
thus codeindependent. The differential quad switching scheme ensures that the actual
and ”toggle” switch drivers have equal capacitive loading, and therefore the currents
180 Prototypes and experimental results
DT
DT
DT
DT
Analog
supply
D
T
CLK 1
Intermediate
supply Digital supply
2
3
4
Figure 7.49 Switch driver for differentialquad switching.
drawn from supply rails should not vary between clock cycles. It also equalizes the
voltage variation on the source node of the switches.
The switch driver signals are generated from the digital data and ”toggle” bits with
the switch driver presented in Fig. 7.49. The clock buffers (marked with ”1”) are
added in order to remove the data dependent clock load variation, the effect of which
was analyzed in Section 6.7.3. The additional buffering (marked with ”2”) is used to
ensure symmetry in both the signal and its inversion, which is not guaranteed when a
true singlephase clocked input latch is used. The differential latch stage (marked with
”3”) is used to produce a differential switch driver signal and determine the crossing
point of those signals. Finally, a symmetrical NORstage (marked with ”4”) is used to
produce the combinations of data and ”toggle” signals required to steer the switches.
7.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 181
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10
8
−120
−100
−80
−60
−40
−20
0
Power spectrum
Frequency [Hz]
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
c
]
Figure 7.50 Simulated output spectrum of the converter when the differentialquad switching
disabled.
Dedicated power supplies are used for the different stages in the driver in order to
reduce the distortion due to power supplyinterference.
The simulated spectrum when the differentialquad switching is disabled is pre
sented in Fig. 7.50. The simulated SFDR is 78.04 dB on the Nyquist band, and is
limited by the 2
nd
harmonic (DC component not taken into account).
The simulated spectrum when the differentialquad switching is enabled is pre
sented in Fig. 7.51. The simulated SFDR is 62.3 dB in the Nyquist band, and is
limited by the 3
rd
harmonic (DC component not taken into account).
The increase of the third harmonic component can be explained as follows by con
sidering a fully thermometercoded D/A converter for simplicity. The transition on the
switch driver signals causes a bounce on the source node of the switches, as presented
in Fig. 7.52. The bounce can be either due to capacitive coupling or due to simultane
ously conducting switches. In addition, it can be assumed that the source node follows
the output voltage of the conducting current branch attenuated by
g
ds
gm
of the switch.
182 Prototypes and experimental results
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10
8
−120
−100
−80
−60
−40
−20
0
Power spectrum
Frequency [Hz]
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
c
]
Figure 7.51 Simulated output spectrum of the converter when the differentialquad switching is
enabled.
T
Vc1
Vc2
Vb
DT DT
DT
DT
RL RL
o+ o−
D DT
Figure 7.52 Switch driver coupling in differentialquad switching.
7.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 183
Next, let us deﬁne signals
s
p
(n) =
2
N
−1
1
2
+
1
2
sin(∆φn)
(7.15)
s
n
(n) =
2
N
−1
1
2
−
1
2
sin(∆φn)
(7.16)
∆s
p
(n) = s
p
(n) −s
p
(n−1) = ∆s(n) (7.17)
∆s
n
(n) = s
n
(n) −s
n
(n−1) =−∆s(n) (7.18)
∆s
n
(n) = ∆s
p
(n) (7.19)
M
p
(n) = s
p
(n) +
1
2
(∆s
p
(n) −∆s
p
(n)) (7.20)
M
n
(n) = s
n
(n) +
1
2
(∆s
n
(n) −∆s
n
(n)) (7.21)
e
p
(t) = K
g
ds
gm
M
p
(n)s
p
(n) ⊗p(t) (7.22)
e
n
(t) = K
g
ds
gm
M
n
(n)s
n
(n) ⊗p(t) (7.23)
in which s(n) = s(nT) is the smallsignal equivalent of the output for a sinusoidal
input (the ”p” and ”n” subscripts stands for positive and negative output, respectively),
∆s(n) corresponds to the discrete time derivative of the output, M(n) is the number
of unit currents in the thermometercoded converter that does not change the output
branch during the clock period, p(t) is the pulse at the source node caused by the
transition, gm and g
ds
are the transconductance and output conductance of the switch,
K is a constant that is used to model the attenuation of error from the source of the
switches to the output, and e(n) is the error seen at the output due to differentialquad
switching.
Now it is possible to write an equation for the error signal seen at the differential
output as
e(t)
di f f
= e
p
(t) −e
n
(t) (7.24)
= K
g
ds
gm
s
p
(n)
2
−s
n
(n)
2
+
1
2
(s
p
(n) +s
n
(n))∆s(n)
−
1
2
(s
p
(n) −s
n
(n))∆s(n)
⊗p(t) (7.25)
= K
g
ds
gm
2
N
−1
2
sin(∆φn)
+
1
2
(sin(∆φn) −sin(∆φ(n−1)))
−
1
2
sin(∆φn) −sin(∆φ(n−1)) sin(∆φn)
⊗p(t), (7.26)
184 Prototypes and experimental results
which means that instability on the source node of the switches may cause oddorder
harmonic distortion when differentialquad switching is used. However, since the dis
tortion is proportional to the output signal as is also the distortion due to the output
impedance variation, these two sources of distortion are very difﬁcult to distinguish
from each other in any other way than disabling the differentialquad switching.
It can be seen from the experimental results presented later in this chapter, and
from the simulation results presented in Section 6.7.4, that it is beneﬁcial to use the
differentialquad switching scheme even though it seems to reduce the SFDR when
the converter is simulated without the powersupplyrail parasitics, as in Fig. 7.50 and
Fig. 7.51.
The static timing errors due to clock and signal path imbalances may introduce
timingrelated harmonic distortion as presented in [145]. In order to avoid these imbal
ances, the load of the switch drivers is equalized with dummy structures as presented
in Fig. 7.53. The method results in an almost identical operating point, and thus in
the C
gs
, of the dummy and the MSB switches. The main drawback of the presented
method is (in this particular case) the 12.79% increase in static power consumption.
A similar method is also used in [146]. In addition to load equalization, the timing
imbalance was reduced by using a treelike clock and output signaling, ensuring that
the path length from root to leaf is equal for each signal branch.
7.2.5 Logic for digital calibration
The principle of the digital calibration method used in this prototype is described in
Section 6.4.
The block diagram of the required DSP for the digital calibration is presented in
Fig. 7.54 The functionality of the logic is as follows. The ”calibration request signal”
resets the state machine, which takes care of the execution of the calibration algorithm
as described in Fig. 7.55.
After the calibration request, the state machine shuts down all the digital blocks that
are not needed in calibration, connects the comparator to the output of the converter,
and the ﬁrst calibration cycle starts. The state machine sets the CAL input code and
steps down the REF input codes starting from CAL with steps of 4 LSB. Each com
parison is repeated a maximum of N times in order to average out the effect of noise.
There is also the possibility of using a tunable threshold level for comparison in such a
manner that, if the value of the result counter exceeds the positive or negative thresh
old, the decision is made, even though the number of comparisons performed is less
than N (N is also programmable from 1 to 2
30
). This speeds up the calibration, since
the large differences in which the noise does not play an important role, are resolved
faster than smaller differences.
7.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 185
8
VDD_dum
8
o+ o−
8
128/16
12
VDD_dum
12
o+ o−
4
64/16
14
VDD_dum
14
o+ o−
2
32/16
15
VDD_dum
15
o+ o−
1
16/16
1
8
8
VDD_dum
8
o+ o−
2/16
Vb
o+ o−
16
16
1
2
o+ o−
8/16
14
VDD_dum
14
1
4
o+ o−
4/16
12
VDD_dum
12
1
8
8
VDD_dum
8
o+ o−
1/16
1
8
1
2
8
VDD_dum
8
o+ o−
1/16
1
8
1
4
8
VDD_dum
8
o+ o−
1/16
1
8
1
8
8
VDD_dum
8
o+ o−
1/16
1
8
1
16
8
VDD_dum
8
o+ o−
1/16
1
8
1
32
8
VDD_dum
8
o+ o−
1/16
1/8LSB
MSB
Figure 7.53 Switch driver load balancing with biased dummy structures.
186 Prototypes and experimental results
Cumulative
Offset Memory
Calibration
request
When−to−use
Computer
Offset
MUX
Offset selection &
Addition
D/A
CORE
State−
machine
Offset
Computer
Constant offset
adder
Constant offset
Calc. & mem.
Input
Data
Load
Read
Digital
Comparator
Figure 7.54 Block diagram of the calibration logic.
Calibration
request?
Init state
CAL
Load
val.
REF
Load
val.
Compare
Repeated
N times?
Incr/Decr
Res. Count.
IS REF
< CAL?
CAL
Load
val.
REF
Load
val.
Compare
Repeated
N times?
Incr/Decr
Res. Count.
IS REF
> CAL?
Set next
CAL val.
Compute
cum. offset
Store cum.
offset
Final CAL
val. ?
Calc. & store
const. offset
Incr. REF
STEP=
1/8 LSB
Decr. REF
STEP=
Yes
No
Yes
No
No
Yes Yes
No
Yes
No
Yes
No
4 LSB
Figure 7.55 State diagram of the calibration.
7.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 187
Input code
Output value
T1 T2T3T4
O4
O3
O2
O1
O0
Figure 7.56 Offset possibilities for the 10bit LSB segment.
Once the output corresponding to the REFcode is less than the output correspond
ing to the CAL code, the REF code is increased in steps of 1/8LSB, and the comparison
is performed in a manner mentioned above. When the output corresponding to the REF
value exceeds the output corresponding to the CAL, the offset is found with 1/8 LSB
resolution, and the cumulative offset is computed by accumulating the current offsets
with the previous ones.
For each of the CAL values corresponding to the MSB current source, the cumula
tive offset is stored to cumulative offset memory, which consists of 67 12bit registers
in series. RAMmemories could also be used, but the speed requirements could not be
met with the memory elements provided by the silicon vendor, and the usage of the
registers and multiplexers enabled the usage of pipelining and parallelism more freely.
After the offset for the last MSB source is found, a constant offset is computed and
stored as
O
c
=
2
16
−1+4∗2
10
+0.875
LSB−O
67
2
, (7.27)
where O
67
is the cumulative offset for the last MSB current source. The constant offset
is used to align the input code range to the center of the analog output range, since the
whole analog output range is not necessarily used.
After the calibration algorithm is executed, the state machine returns to initial state
to wait for the calibration request, while the converter is in its normal operation mode,
using stored cumulative offset values for the linearization.
The linearization of the conversion is performed in the normal operation mode
as follows. For every input data value, the 67to5 offset MUX selects ﬁve possible
offset values. This is due to the fact that the cumulative offset can be as large as
4x2
10
LSB = 4MSB, so for each 10bit LSB segments there are ﬁve possible offset
values, as presented in Fig. 7.56
188 Prototypes and experimental results
+ −
− +
+ −
− +
+ −
− +
+ −
− +
Vref
In+
In−
S1
S1
S2
S2
S3
S3
C
S4
S1
S2
S3
Cal/ref
from DAC
(dac) S_cal
Sr
Sr
C
(dac) S_ref
Sr
S4
C
R
S4
J
K
Q
Q
J
K
C
Q
Q
R
OUT
Figure 7.57 Comparator chain.
The whentouse computer block is used to calculate the threshold values (T1T4
in Fig. 7.56). The input code is compared to the whentouse value, and the corre
sponding offset (O0O4 in Fig. 7.56) is selected. It would be possible to also store
the whentouse values to memory, but since the memory is the speed bottleneck of
the calibration system, it is justiﬁed to compute the whentouse values separately for
each input code rather than use memories, since the computation of whentouse value
requires only ﬁve subtracters and some registers for pipelining.
Finally, the digital comparator is used to compare the input to the whentouse
values, and the offset value is selected according to Fig. 7.56. The simulation result
demonstrating the effect of the calibration was presented in Fig. 6.39.
7.2.6 DNL measurement for calibration
The key function of the digital calibration is the successive approximation A/D conver
sion of the error of the MSB current source, and the key component in the realization
of the SAR A/D converter is the comparator. The comparator is realized as a chain of
singlestage ampliﬁers with offsetcompensation feedback (Fig. 7.57) In the design of
this comparator chain, the following aspects are taken into account. What is required
is a comparator that is able to provide a 3.3V output with a differential input voltage of
1.2µV, which corresponds to 1/16 LSB, half of the minimum step used in calibration.
Thus, a gain of 128dB is needed.
The chainofampliﬁers type of structure enables the offset voltage cancellation and
ampliﬁcation of the signal before the comparison in such a manner that the signal is
ampliﬁed, but only the charge injection of the third ampliﬁer stage in Fig. 7.57 affects
the result of the comparison (offset and charge injection of the ﬁrst and second stage
7.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 189
are canceled by the feedback of the third ampliﬁer) [174]. Using multiple stages makes
it also possible to use a simple singlestage differential ampliﬁer as a comparator and
obtain the required gain simultaneously. Since the singlestage ampliﬁers are inher
ently stable, no compensation is required, which would otherwise be the case due to
the offsetcancellation unity feedback.
The one comparison cycle is performed as follows. First, the CAL value corre
sponding to the MSB current source to be calibrated (see Section 6.4 and Figs 7.55
7.57 ) is applied at the input of the comparator chain (i.e. output of the D/A con
verter) by triggering signal S
CAL
. After that, the ﬁrst three feedback loops are opened
by opening the switches S
1
, S
2
, and S
3
. Then the REFvalue is applied to the input,
triggered with signal S
REF
. If the REFvalue is larger than the CALvalue the output
of the third comparator is positive, otherwise it is negative. The output of the third
comparator is sampled with the signal S
r
. Sampling of the difference of CAL and REF
will alleviate the 1/fnoise requirements of the ampliﬁers, since it introduces a trans
mission zero on the noise transfer function at the zero frequency [175]. Furthermore
the noise bandwidth is reduced by parallel capacitors at the ampliﬁer outputs. Thermal
noise is reduced by maximizing the gm of the input stage of the ampliﬁer which also
increases the gain. Increasing the dimensions of the input transistors above a certain
point results in attenuation of the signal due to capacitive voltage division between the
series capacitors and C
gs
of the input stage of the ampliﬁer.
After sampling, the feedback of the fourth comparator is opened, and the bottom
plate sampling is completed by closing the switch controlled by the signal C, which
also enables the latching comparator. Finally, the differential output of the latch
comparator is read to JKﬂipﬂop with signal R.
The latchcomparator at the end of the chain is used to further boost the result of
the comparison in order to ensure full railtorail signal to be read to digital calibration
circuitry. Circuit diagrams of the ampliﬁer and the latchcomparator are presented in
Fig. 7.58 and Fig. 7.59.
7.2.7 Experimental results
The circuit was fabricated on a 5 metal 0.35µm BiCMOS SiGE process with metal
insulatormetal capacitors. The photomicrograph of the circuit is presented in Ap
pendix B. The chip was packed into a 160pin TQFP package. The measurement board
was a 4layer FR4 PCB. Two inner layers were dedicated to ground and supply in such
a manner that the ground plane was common to all analog and digital parts, whereas
the positive supply voltages were distributed with separate supply planes. Decoupling
capacitors were placed between the supplies and ground in order to stabilize the supply
voltages. Tunable regulators were used to produce the supply voltages from a single
190 Prototypes and experimental results
Vb
Vbc
In− In+
Out− Out+
Vss
Vdd
Figure 7.58 Singlestage differential ampliﬁer.
Q
Q
C
CD C1
C1D
C
C1D
C1 C1 J K
Ib
Figure 7.59 Comparatorlatch.
7.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 191
supply voltage input. Area and power dissipation characteristics of the converter are
presented in Tables 7.7 and 7.8.
Table 7.7 Area characteristics
Calibration logic D/Acore Total
Area 5.83mm
2
5.77mm
2
14.40mm
2
Table 7.8 Power characteristics
Power dissipation: Logic bypassed Logic active
Digital@65MS/s 142mW 406mW
D/A core@65MS/s 95mW 95mW
Total 65MS/s 237mW 501mW
Digital@400MS/s 320mW 1449mW
D/A core@400MS/s 306mW 306mW
Total 400MS/s 626mW 1755mW
7.2.7.1 Static linearity
The static linearity of the uncalibrated converter was ﬁrst measured in order to discover
the linearity achieved by transistor dimensioning and layout techniques. The DNL and
INL curves in the uncalibrated case are presented in Fig. 7.60. The maximum and
minimum of the DNL are 2.018 LSB and 1.62 LSB, respectively. INL varies between
5.32 LSB and 7.51 LSB.
In order to discover the effect of calibration, offset is applied between the binary
weighted LSB and thermometercoded MSB current source matrices. The static lin
earity of the uncalibrated D/A converter with 14 LSB offset between the LSB matrix
and MSB matrix is presented in Fig. 7.61. In this case, DNL varies between 1.73 LSB
and 15.29 LSB, and INL between 4.26 LSB and 18.93 LSB, respectively.
The effect of the calibration on the DNL can be clearly seen in Fig. 7.62. The
variation of DNL is reduced to vary from 1.47 LSB to 1.41 LSB, while INL varies
from 3.79 LSB to 10.96 LSB.
It seems that, even though DNL is reduced due to calibration, the INL is increased
when compared to the results shown in Fig. 7.60. This is due to fact that DNL errors
in Fig. 7.60 seem to compensate the accumulation of the DNL from the LSB matrix,
whereas in Fig. 7.62, this does not happen. When it comes to the reduction of DNL,
the prototype seems to function as designed; however, due to the limited resolution of
the measurement, the absolute accuracy of the calibration cannot be determined.
192 Prototypes and experimental results
1 2 3 4 5 6
x 10
4
−2
0
2
Static nonlinearities relative to LSB
D
N
L
[
L
S
B
’
s
]
Number of sample
1 2 3 4 5 6
x 10
4
−5
0
5
I
N
L
[
L
S
B
’
s
]
Number of sample
Figure 7.60 Static linearity of the uncalibrated D/A converter.
1 2 3 4 5 6
x 10
4
−10
0
10
Static nonlinearities relative to LSB
D
N
L
[
L
S
B
’
s
]
Number of sample
1 2 3 4 5 6
x 10
4
−10
0
10
I
N
L
[
L
S
B
’
s
]
Number of sample
Figure 7.61 Static linearity of the uncalibrated D/A converter with 14 LSB offset between
current source matrices.
7.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 193
1 2 3 4 5 6
x 10
4
−1
0
1
Static nonlinearities relative to LSB
D
N
L
[
L
S
B
’
s
]
Number of sample
1 2 3 4 5 6
x 10
4
−10
0
10
I
N
L
[
L
S
B
’
s
]
Number of sample
Figure 7.62 Static linearity of the calibrated D/A converter.
7.2.7.2 Dynamic performance
Fig. 7.63 and Fig. 7.64 represents the output spectrum of the converter at sample rate
65Ms/s and signal frequency 22.75MHz with the differentialquad switching disabled
and enabled, respectively.
It can be observed that the level image of the third harmonic component is reduced
23.18dB , whereas the level of the second harmonic component remains the same. Spu
rious free dynamic range at a sample rate of 65MS/s as a function of signal frequency
are presented in Figs 7.65 and 7.65.
Similar measurements were carried out at a 400Ms/s sample rate. Fig. 7.67 and
Fig. 7.68 represent the output spectrumof the 140MHz sine signal with the differential
quad switching disabled and enabled, respectively.
It can be observed that the effect of the differentialquad switching on the third
harmonic is less than in the case of the 65Ms/s sample rate. Enabling the toggler
also increases the other spurious tones. This is mainly due to the increased activity
of the switch driver circuitry, which, together with the toonarrow power supply rails,
causes an increase in the powerrail interference. The effect of the powersupplyrail
interferenceinduced jitter was analyzed in Section 6.7.4. Parasitic resistance of the
power supply rails explains a large part of the degradation of the SFDR as can be
observed from the simulation results with estimated parasitic resistances presented in
194 Prototypes and experimental results
0 5 10 15 20 25 30
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Power Spectrum
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
]
Frequency [MHz]
Figure 7.63 Output spectrum of a 22.75MHz sine signal with sampling frequency of 65MS/s
and differentialquad switching disabled.
0 5 10 15 20 25 30
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Power Spectrum
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
]
Frequency [MHz]
Figure 7.64 Output spectrum of a 22.75MHz sine signal with sampling frequency of 65MS/s
and differential quad switching enabled.
7.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 195
0 5 10 15 20 25 30
40
45
50
55
60
65
70
75
80
85
90
SFDR and Harmonic Distortion
[
d
B
c
]
Frequency [MHz]
SFDR
2nd Harmonic
3rd Harmonic
Figure 7.65 Spurious free dynamic range of the converter sampling frequency of 65MS/s and
differential quad switching disabled.
Fig. 7.69 and Fig. 7.70.
The measured SFDR curves at 400MS/s sample rate are presented in Fig. 7.71 and
Fig. 7.72.
7.2.7.3 Summary
The measured performance of the digital calibration algorithm demonstrates that rela
tively good static performance can be achieved by digital predistortion, even though the
matching of the MSB current sources is initially poor. With the process used, the speed
requirement of 400MHz is hard to achieve. Extensive parallelism, which increases the
power dissipation of the circuit, had to be used. Parallelism also increases the area
required for the calibration. However, in the future, the scaling of the silicon processes
will increase the speed and decrease the size of the digital circuitry, whereas the area
required for the current sources will scale down slower. Therefore the digital calibra
tion may become an interesting option with the deep submicron silicon processes, in
which fast and small memories and digital circuitry are available. Also scaling down
the supply voltages along the scaling of the device size will make it more complicated
to implement high performance analog circuitry, whereas it alleviates the implementa
tion of the digital part. This work reveals that the proposed digital calibration algorithm
196 Prototypes and experimental results
0 5 10 15 20 25 30
40
45
50
55
60
65
70
75
80
85
90
SFDR and Harmonic Distortion
[
d
B
c
]
Frequency [MHz]
SFDR
2nd Harmonic with toggler
3rd Harmonic with toggler
Figure 7.66 Spurious free dynamic range of the converter with sampling frequency of 65MS/s
and differential quad switching enabled.
0 20 40 60 80 100 120 140 160 180 200
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Power Spectrum
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
]
Frequency [MHz]
Figure 7.67 Output spectrum of 140MHz sine signal with sampling frequency of 400MS/s and
differentialquad switching disabled.
7.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 197
0 20 40 60 80 100 120 140 160 180 200
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Power Spectrum
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
]
Frequency [MHz]
Figure 7.68 Output spectrum of 140MHz sine signal with sampling frequency of 400MS/s and
differential quad switching enabled.
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10
8
−120
−100
−80
−60
−40
−20
0
Power spectrum
Frequency [Hz]
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
c
]
Figure 7.69 Simulated spectrum with estimated parasitic power supply resistances and
differentialquad switching disabled.
198 Prototypes and experimental results
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10
8
−120
−100
−80
−60
−40
−20
0
Power spectrum
Frequency [Hz]
R
e
l
a
t
i
v
e
P
o
w
e
r
[
d
B
c
]
Figure 7.70 Simulated spectrum with estimated parasitic power supply resistances and
differentialquad switching enabled.
0 20 40 60 80 100 120 140 160 180 200
25
30
35
40
45
50
55
60
65
70
SFDR and Harmonic Distortion
[
d
B
c
]
Frequency [MHz]
SFDR
2nd Harmonic
3rd Harmonic
Figure 7.71 Spurious free dynamic range of the converter with sampling frequency of 400MS/s
and differential quad switching disabled.
7.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 199
0 20 40 60 80 100 120 140 160 180 200
25
30
35
40
45
50
55
60
65
70
SFDR and Harmonic Distortion
[
d
B
c
]
Frequency [MHz]
SFDR
2nd Harmonic with toggler
3rd Harmonic with toggler
Figure 7.72 Spurious free dynamic range of the converter with sampling frequency of 400MS/s
and differential quad switching enabled.
is a feasible way to perform the calibration of a current steering D/A converter.
The main shortcoming of the prototype is the poor SFDR with a 400MS/s sampling
rate. An adequate level of SFDR is achieved with 65 MS/s. The measured dynamic
performance of the converter differs from the simulated initial performance (Fig. 7.51
and Fig. 7.50) quite a lot due to the fact that the parasitic resistances were underesti
mated in the layout design phase, resulting in an excessive amount of signaldependent
jitter.
The performance degradation was analyzed with simulations including estimates of
postlayout parasitic resistances and capacitances. The postmeasurement simulations
and simulation results match quite well, indicating that the parasitics are the source of
the degradation.
Also, the effect of differentialquad switching was also veriﬁed with simulations
and measurements revealing its effectiveness in reducing oddorder harmonic distor
tion.
The quality of performance of the implemented prototype and the recently pub
lished converters are presented in Table 7.9.
200 Prototypes and experimental results
Table 7.9 Comparison of the prototype and recently published D/A converters
Publication Process Bits Sampl.
freq.
[MHz]
SFDR
[dBc]
@
[MHz]
DNL
max/
min
INL
max/
min
Comment
Nakamura
[154]
1µm
CMOS
10 70 ? 0.5/
0.5
0.5/
0.5
Mercer
[160]
2µm Bi
CMOS
16 40 80 @
1.23
3/
3
4/
4
SFDR @
10MS/s
Lin [126] 0.35µm
CMOS
10 500 51 @
240
0.05/
0.1
0.2/
0.2
Bastos
[155]
0.5µm
CMOS
12 300 40 @
60
0.3/
?
0.5/
0.6
No minmax
DNL
Bugeja1
[161]
0.5µm
CMOS
14 100 74 @
8.5
0.5/
0.5
0.5/
0.5
Van der
Plas [158]
0.5µm
CMOS
14 150 61 @ 5 0.15/
0.1
0.3/
0.25
Bugeja2
[162]
0.35µm
CMOS
14 100 72 @
42.5
0.25/
0.25
0.35/
0.35
Van den
Bosch1
[164]
0.35µm
CMOS
10 1000 61.2
@ 490
0.14/
0.08
0.18/
0.15
Van den
Bosch2
[163]
0.25µm
CMOS
12 500 62 @
125
0.2/
0.25
0.3/
0.25
Tiilikainen
[137]
0.18µm
CMOS
14 100 64 @ 1 0.5/
0.5
0.5/
0.5
Cong
[138]
0.13µm
CMOS
14 180 50 @
63
0.4/
0.2
0.2/
0.4
Schoﬁeld
[139]
0.25µm
CMOS
16 400 73 @
190
0.2/
0.3
0.2/
0.7
Hyde
[165]
0.18µm
CMOS
14 300 71 @
120
0.4/
0.3
0.3/
0.3
O’Sullivan
[166]
0.18µm
CMOS
12 320 60 @
60
0.3/
0.3
0.3/
0.3
Huang1
[167]
0.18µm
CMOS
14 200 60 @
90
0.6/
0.4
0.6/
0.6
RZmode
Schafferer
[168]
0.18µm
CMOS
14 1400 67 @
260
0.8 1.8 No minmax
DNL/INL
Doris
[146]
0.18µm
CMOS
12 500 60 @
220
0.6/
0.6
1/
1
This work 0.35µm
CMOS
16 65 62.9
@
31.68
1.47/
1.41
3.79/
10.96
Calibrated
DNL/INL
This work 0.35µm
CMOS
16 400 41.11
@ 195
2.02/
1.62
5.32/
7.51
Uncalibrated
DNL/INL
This work 1.73/
15.89
4.26/
18.93
Worst case
DNL/INL
Conclusions
Wireless communications have been the driving force of the development of the in
tegrated circuits during the last decade. The trend has been to move from analog to
digital signal processing and increase the bandwidth. It started with analog, while
nowadays the ﬁrst digital wireless systems like GSM are at the end of the trail, mak
ing way for 3G systems. The wireless digital communications have evolved through
services such as GPRS and EDGE towards the WCDMA and 3G, which is capable of
handling both the narrowvoice band and wide data bands. Simultaneously, the wireless
data transmission systems such as WLAN/WiFi and Wimax have gained popularity. In
the world of multiple standards, it is beneﬁcial if a single system is capable of handling
multiple standards, or if the system is reconﬁgurable. This kind of ﬂexibility can be
obtained by using digital signal processing in transmitters and receivers. In this book,
the research of digital signal processing and D/A converters for digitalIF transmit
ters is presented. The ﬁrst part of the book represents the research results obtained
during the design of the multicarrier digital IF transmitter prototype for a WCDMA
basestation transmitter. The theory of the transmitters and the signal processing, and
efﬁcient DSP realizations, was studied. The knowledge gained was then applied to the
practical design, and ﬁnally the experimental results were presented.
The transmitter prototype consists of an interpolateby16 interpolation ﬁlter chain
including a rootraised cosine pulse shaping ﬁlter and three halfband ﬁlters. The root
raised cosine ﬁlter was designed with the Langrangeoptimization algorithm in order to
achieve adequate EVM and ALCR for the 3G WCDMA system. Polyphase structures,
CSDmultipliers, common subexpression sharing and time interleaving was used in
order to reduce the amount of hardware in the ﬁlters.
Upconversion to the digital IF frequency was performed with a digital modulator
based on a CORDIC vector rotation algorithm, which is very suitable for VLSI imple
mentation and performs the modulation without digital multipliers, which are usually
considered area consuming. After upconversion, the multicarrier signal was formed
by summation of eight independent datapaths on four carrier frequencies, and the re
sult was converted to the analog domain with a 14bit currentsteering D/A converter.
202 Prototypes and experimental results
The SINCattenuation due to the sampleandhold function of the D/A converter is
canceled with an inverseSINC predistortion ﬁlter. Optimization of the dynamic range
of the signal was also considered brieﬂy. Further research into sophisticated signal
clipping methods has been carried out at ECDL by Olli Väänänen, and published in
[176].
Experimental results from the transmitter prototype indicate that the selected archi
tecture is suitable for integrated digital IF multicarrier modulator, resulting in reason
able area and power dissipation, and that the quality requirements of the 3G WCDMA
transmitter can be met. The performance of the transmitter is limited by the D/A con
verter. In the future, the requirement for highquality highspeed D/A converters will
increase, since moreandmore signal processing will be performed digitally.
The second part of the book is about the design of the currentsteering D/A con
verters. The currentsteering D/A converter is a complex entity composed of various
details, all of which have to be considered and designed carefully in order to achieve
good performance. The theory part of this book represents the problem scope related
to static linearity, dynamic linearity and timing jitter. The model for the static lin
earity was developed and the effect of the output impedance was analyzed. A digital
calibration method based on predistortion was developed and implemented.
It was demonstrated with the prototype that digital predistortion is one possible
way to realize the calibration of the currentsteering D/A converter. This method has
the advantage of having practically no matching requirement for the additional analog
current sources, as is the case when a dedicated calibration DAC is used to tune the
values of the MSB current source. The main difﬁculty is the measurement of the
nonlinearity and the realization of the DSP required for the predistortion, whereas the
requirements for the matching (and thus area) of the MSB sources are alleviated. In the
future, the size of the digital part will scale down and the speed will increase, whereas
the analog signal processing will become moreandmore challenging making digital
predistortion technique moreandmore attractive.
The future of the IC’s seems to be mainly digital, due to the decreasing cost of
digital signal processing. However, the real world is analog and the conversion between
the two worlds cannot be avoided. This will increase the demand for the various digital
enhancement algorithms of analogsignal processing.
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Appendix A
Photomicrograph of the
WCDMA transmitter
Figure A.1 Photomicrograph of the circuit.
Appendix B
Photomicrograph of the D/A
converter with digital
calibration
Figure B.1 Photomicrograph of the circuit.
Appendix C
Jitter energy as a function of
signal frequency and jitter
amplitude
The continuous time error signal e(t) due to timing jitter is deﬁned by the jitter signal
w(n) and the discretetime derivative ∆x(n) of the signal x(n) as
e(t) =
∞
∑
n=−∞
∆x(n)g(t)
=
∞
∑
n=−∞
[x(nT) −x((n−1)T)]
×[u(t −nT −w(n))) −u(t −nT)], (C.1)
in which ∆x(n) = x(n) −x(n−1) and u(t) is a unit step function. w(n) has the fol
lowing properties.
E [w(n)] = 0 (C.2)
E [w(n) −w(n−1)] = 0, (C.3)
since E [w(n)] = 0 results in time shift of the signal and E [w(n) −w(n−1)] = 0 is
equal to change in sampling period T, therefore not affecting the energy of the signals.
The power of the error signal due to jitter can be computed as
P
j
= lim
C→∞
1
C
Z
C
0
∞
∑
n=−∞
∆x(n)
2
×(u(t −nT −w(n)) −u(t −nT))
2
dt (C.4)
224 Jitter energy as a function of signal frequency and jitter amplitude
= lim
N→∞
N
∑
n=0
1
NT
∆x(n)
2
Z
nT+w(n)
nT
(u(t −nT −w(n)) −u(t −nT))dt
(C.5)
=
1
T
E
∆x(n)
2
w(n)
(C.6)
in which E [] means expectation. By substituting
y = ∆x(n)
2
−µ
d
(C.7)
z = w(n) −µ
a
, (C.8)
in which µ
d
= E
∆x(n)
2
and µ
a
= E [w(n)], Eq. C.6 can be written as
P
j
= ρσ
y
σ
z
+µ
d
µ
a
, (C.9)
ρ =
E [yz]
σ
y
σ
z
. (C.10)
In case correlation factor ρ = 0, ∆x(n)
2
and w(n) are independent resulting in
P
j
= µ
d
µ
a
= E
∆x(n)
2
E [w(n)] . (C.11)
Let us assume, that x(n) is a sinusoidal signal
x(n) = Asin(∆φn) (C.12)
∆φ =
2πF
sig
F
s
, F
sig
≤F
s
/2, (C.13)
and w(n) is an arbitrary jitter signal independent of x(n) In this case the power of the
error signal due to jitter can be computed as
P
j
= E
∆x
2
E [x] (C.14)
= A
2
(1−cos(∆φ))E
¸
w(n)
T
(C.15)
= A
2
1−cos
2πF
sig
F
s
E
¸
w(n)
T
, (C.16)
in which the value of the E
w(n)
T
is deﬁned by the probability distribution and is
linearly dependent on the standard deviation.
It is possible to calculate E
w(n)
T
for some typical jitter signals.
For sine signal
E
asin(2πnT
j
)
=
2a
π
. (C.17)
225
For Gaussian white noise
E [N(0, σ))] =
2
π
σ. (C.18)
For uniformly distributed noise −
a
2
≥w(n) ≤
a
2
E [w(n)] =
a
4
=
√
3
2
σ , σ =
a
2
√
3
. (C.19)
The power spectral density (PSD) function of error signal due to N(σ
w
, 0) Gaussian
jitter can be derived as follows. The Fourier transform of the jitter signal can be written
as
E ( jω) =
∞
∑
−∞
∆x(n)
−jω
e
−jωnT
1−e
jω(nT)
(C.20)
(C.21)
and
E ( jω)
2
= Re{E ( jω)}
2
+Im{E ( jω)}
2
(C.22)
=
∞
∑
n=−∞
∞
∑
k=−∞
∆x(n)∆x(k)
ω
2
e
−jωnT
e
jωkT
1−e
jωw(nT)
1−e
−jωw(kT)
=
∞
∑
n=−∞
∞
∑
k=−∞
∆x(n)∆x(k)
ω
2
cos(ω(n−k)T)
×(1−cos(ωw(nT)) −cos(ωw(kT)) +cos(ω(w(nT) −w(kT))))
Assuming that there is no correlation between ∆x(n), cos(ω(n−k)T) and w(nT), the
only combination of n −k resulting in nonzero value is when n = k, and E ( jω)
2
becomes
E ( jω)
2
=
∞
∑
n=−∞
∆x(n)
2
ω
2
(2−2cos(ωw(nT))). (C.23)
The PSD function of the error signal is obtained by computing the expectation of
E ( jω)
2
. Since the expectation of cos(ωw(nT)) with Gaussian N(σ
w
, 0) distributed
w(nT) is
E [cos(ωw(nT))] = e
−ω
2
σ
2
w
2
, (C.24)
(C.25)
and
E
∆x(n)
2
= VAR[∆x(n)] (C.26)
226 Jitter energy as a function of signal frequency and jitter amplitude
(C.27)
when ∆x(n) has zero mean, the PSD function can be expressed as
S( f ) = VAR[∆x(n)]
2−2e
−
4π
2
f
2
σ
2
w
2
4∗π
2
∗ f
2
. (C.28)
For a sinusoidal signal x(n) at frequency F
sig
, the PSD function is
S( f ) = A
2
1−cos
2π
F
sig
F
s
2−2e
−
(2πf )
2
σ
2
w
2
4∗π
2
∗ f
2
. (C.29)
The power of the error signal on a certain frequency band −F
b
to F
b
can be obtained
by integrating S( f ) resulting in
P
j
(F
b
) = A
2
1−cos
2π
F
sig
F
s
(C.30)
×
e
−2π
2
F
2
b
s
2
+
√
π
√
2πF
b
σ
w
erf
√
2πF
b
σ
w
−1
π
2
F
b
, (C.31)
where
erf
√
2πF
b
σ
w
=
Z
√
2πF
b
σ
w
0
e
−x
2
dx. (C.32)
The ﬁrstorder Taylor series approximation of P
j
(F
b
) is
P
j
(F
b
) ≈ 2A
2
1−cos
2π
F
sig
F
s
F
b
σ
2
w
(C.33)
The total error power is obtained by
lim
F
b
→∞
P
j
(F
b
) = A
2
1−cos
2π
F
sig
F
s
2
π
σ
w
, (C.34)
which is equal to Eq. (C.16) with Gaussian jitter, thus following Parceval’s theorem.
Appendix D
Fourier transforms of some
functions used in this book
D.1 Elementary relations
Notation for transformation
F {x(t)} = X ( f ) (D.1)
Time shift
F {x(t +τ)} = X ( f )e
−jωτ
(D.2)
Derivative
F
¸
x
′
(t)
¸
= jωX ( f ) (D.3)
D.2 Elementary functions and operations
Sampling function
F
∞
∑
n=−∞
δ(t −nT
s
)
¸
=
∞
∑
n=−∞
e
−jωnT
s
(D.4)
According to Poisson’s sum formula
∞
∑
n=−∞
e
−jωnT
s
↔ F
s
∞
∑
n=−∞
δ( f −nF
s
), F
s
=
1
T
s
(D.5)
228 Fourier transforms of some functions used in this book
Sampling
F
x(t)
∞
∑
n=−∞
δ(t −nT
s
)
¸
= F
s
∞
∑
n=−∞
X ( f −nF
s
), F
s
=
1
T
s
(D.6)
Discrete time derivative
F
(x(t) −x(t −T
s
))
∞
∑
n=−∞
δ(t −nT
s
)
¸
=
1−e
j2π
f
F
s
F
s
∞
∑
n=−∞
X ( f −nF
s
), F
s
=
1
T
s
(D.7)
Sine
F {Asin(ω
0
t)} =
A
j2
(δ( f − f
0
) −δ( f + f
0
)), f
0
=
ω
0
2π
(D.8)
Cosine
F {Acos(ω
0
t)} =
A
2
(δ( f − f
0
) +δ( f + f
0
)), f
0
=
ω
0
2π
(D.9)
Trapezoidal pulse (Figure D.1)
Tc Tr Tf
A
0
Figure D.1 Trapezoid pulse.
x(t) =
A
T
r
t (u(t) −u(t −T
r
))
+T
c
(u(t −T
r
) −u(t −(T
r
+T
c
)))
+
T
c
−
(t −T
r
−T
c
)T
c
T
f
×(u(t −(T
r
+T
c
)) −u(t −(T
r
+T
c
+T
f
))) (D.10)
F {x(t)} =
A
ω
2
T
r
e
−jωT
r
−1
−
A
ω
2
T
f
e
−jωT
t
−1
e
−jω(T
r
+Tc)
−
2jA
ω
2
T
r
e
−jω
T
r
2
sinω
T
r
2
+
2jA
ω
2
T
f
e
−jω
T
r
+Tc+
T
f
2
sinω
T
f
2
. (D.11)
D.2 Elementary functions and operations 229
If T
r
= T
f
= T
T
we get
F {x(t)} =
4A
ω
2
T
T
e
−jω(T
T
+
T
c
2
)
sin
ωT
T
2
sin
ω(T
T
+T
c
)
2
(D.12)
The Fourier transform of a triangular pulse with equal rise and fall times is obtained
by setting T
c
= 0 in Eq.D.12 resulting in
F {x(t)} = 4AT
T
e
−jωT
T
sin
2
πf T
T
(πf T
T
)
2
(D.13)
Ramp pulse (Figure D.2)
A
0
Tr
Figure D.2 Ramp pulse.
x(t) =
A
T
r
t (u(t) −u(t −T
r
)) (D.14)
F {x(t)} =
A
ω
2
T
r
e
−jωT
r
−1
−
A
jω
e
−jωT
r
(D.15)
Rectangular pulse (Figure D.3)
A
0
Tc
Figure D.3 Rectangular pulse.
230 Fourier transforms of some functions used in this book
x(t) = A(u(t) −u(t −T
c
)) (D.16)
F {x(t)} =
A
jω
1−e
−jωT
c
(D.17)
= T
c
Ae
jωT
c
sinπf T
c
πf T
c
(D.18)
Signum function of a zeromean periodic signal x(t) with 50% duty cycle (Figure
D.4)
τ
t
sgn(0+)
+1
−1
T
0
Figure D.4 Signum function of signal with 50% duty cycle and time shift τ.
F {sgn(x(t))} =
−sgn(0
+
)e
−jωτ
f
0
sin
2
π
2 f
0
jπf
∞
∑
n=−∞
δ( f −nf
0
) (D.19)
Absolute value function of a zeromean periodic signal x(t) with 50% duty cycle
F {x(t)} =
−sgn(0
+
)e
−jωτ
f
0
sin
2
π
2 f
0
jπf
∞
∑
n=−∞
δ( f −nf
0
)
⊗X ( f ) (D.20)
Distribution: Helsinki University of Technology Department of Electrical and Communications Engineering Electronic Circuit Design Laboratory P.O.Box 3000 FIN02015 HUT Finland Tel. +358 9 4512271 Fax: +358 9 4512269
ISBN10 951228409X ISBN10 9512284103 (PDF) ISBN13 9789512284092 ISBN13 9789512284108 (PDF) ISSN 14558440 Otamedia Oy Espoo 2006
Abstract
In this thesis, the implementation methods of digital signal processing and digitaltoanalog converters for wideband transmitters are researched. With digital signal processing, the problems of analog signal processing, such as sensitivity to interference and nonidealities of the semiconductor processes, can be avoided. Also, the programmability can be implemented digitally more easily than by means of analog signal processing. During the past few years, wireless communications has evolved from analog to digital, and signal bandwidths have increased, enabling faster and faster data transmission. The evolution of semiconductor processes, decreasing linewidth and supply voltages, has decreased the size of the electronics and power dissipation, enabling the integration of larger and larger systems on single silicon chips. There is little overall beneﬁt in decreasing linewidths to meet the needs of analog design, since it makes the design process more difﬁcult as the device sizes cannot be scaled according to minimum linewidth and because of the decreasing supply voltage. On the other hand, the challenges of digital signal processing are related to the efﬁcient realization of signal processing algorithms in such a way that the required area and power dissipation does not increase extensively. In this book, the problems related to digital ﬁlters, upconversion algorithms and digitaltoanalog converters used in digital transmitters are researched. Research results are applied to the implementation of a transmitter for a thirdgeneration WCDMA basestation. In addition, the theory of factors affecting the linearity and performance of digitalto analog converters is researched, and a digital calibration algorithm for enhancement of the static linearity has been presented. The algorithm has been implemented together with a 16bit converter; its functionality has been demonstrated with measurements. Keywords: Direct digital synthesizer, Digital transmitter, modulator, CORDIC, digitaltoanalog converter, calibration.
Tiivistelmä
Tässä väitöskirjassa on tutkittu digitaalisen signaalinkäsittelyn toteuttamista ja digitaalisesta analogiseksimuuntimia laajakaistaisiin lähettimiin. Digitaalisella signaalinkäsittelyllä voidaan välttää monia analogiseen signaalinkäsittelyyn liittyviä ongelmia, kuten häiriöherkkyyttä ja puolijohdeprosessien epäideaalisuuksien vaikutuksia. Myös ohjelmoitavuus on helpommin toteutettavissa digitaalisesti kuin analogisen signaalinkäsittelyn keinoin. Viime vuosina on langattomien tietoliikennejärjestelmien kehitys kulkenut analogisesta digitaaliseen, ja käytettävät signaalikaistanleveydet ovat kasvaneet mahdollistaen yhä nopeamman tiedonsiirron. Puolijohdeprosessien kehitys, kapeneva minimiviivanleveys ja pienemmät käyttöjännitteet, on pienentänyt elektroniikan kokoa ja tehonkulutusta mahdollistaen yhä suurempien kokonaisuuksien integroimisen yhdelle piisirulle. Viivanleveyksien pieneneminen ei kuitenkaan suoraan hyödytä analogiasuunnittelua, jossa piirielementtien kokoa ei välttämättä voida pienentää viivanleveyden pienentyessä, ja jossa madaltuva käyttöjännite ennemminkin hankaloittaa kuin helpottaa suunnittelua. Siksi yhä suurempi osa signaalinkäsittelystä pyritään tekemään digitaalisesti. Digitaalisen signaalinkäsittelyn ongelmat puolestaan liittyvät algoritmien tehokkaaseen toteuttamiseen siten, että piirien pintaala ja tehonkulutus eivät kasva liian suuriksi. Tässä kirjassa on tutkittu digitaalisessa lähettimessä tarvittavien digitaalisten suodattimien, ylössekoitusalgoritmien ja digitaalisesta analogiseksimuuntimien toteuttamiseen liittyviä ongelmia. Tutkimustuloksia on sovellettu kolmannen sukupolven WCDMAtukiasemalähettimen toteutuksessa. Lisäksi on tutkittu digitaalisesta analogiseksimuuntimien lineaarisuuteen ja suorituskykyyn vaikuttavien seikkojen teoriaa, ja esitetty digitaalinen kalibrointialgoritmi muuntimen staattisen suorituskyvyn parantamiseksi. Algoritmi on toteutettu 16bittisen muuntimen yhteydessä ja se on osoitettu toimivaksi mittauksin. Avainsanat: Suora digitaalinen syntetisaattori, digitaalinen lähetin, modulaattori, CORDIC, digitaalisesta analogiseksimuunnin, kalibrointi.
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with whom I have shared many great moments throughout the years. most of all. for his guidance and new ideas during the years we worked together. Kaarina Koskinen. and listening to my neverending environmental preaching. I would also like to express my gratitude to Jussi Pirkkalaniemi for his contribution to the research presented in this book. The work presented in this book has been carried out in research projects funded by Nokia Networks. I gratefully acknowledge all my colleagues with whom I have been honored to work throughout the years. including our gooddoing at 4 a. Special thanks go to Mikko Waltari. Mika Länsirinne. I also thank the Nokia Foundation. I would like to thank my former teachers Varpu Rönnholm. the Finnish Society of Electronics Engineers. and for the opportunity to carry out this research in such an inspiring and relaxed environment as the Electronic Circuit Design Laboratory. Esa Tiiliharju. My warmest thanks go to Dr. I express my gratitude to Professor Kari Halonen for his guidance and support. the endless planning of trips to the museum of former president Kekkonen. and Eino Sandelin for guidance they have given me. and for their valuable comments and suggestions..Preface The research for this thesis was carried out at the Electronic Circuit Design Laboratory (ECDL) of Helsinki University of Technology during the years 19982005. Jonne Lindeberg. Jaakko Ketola. Lauri Koskinen. Saska Lindfors. . In addition to those mentioned above. for their active participation in our notsoprofessional recreational activities. Jouko Vankka. express my warmest thanks to all my friends. Jussi Pirkkalaniemi and Helena Yllö for their professional assistance. Asko Kananen. Väinö Hakkarainen and Jacek Flack for the very interesting conversations we had during the years through which we shared out room. and the Foundation of Technology for their ﬁnancial support. and. Ari Paasio. and.m. Kimmo Koli. my supervisor. I also warmly thank Professors Jiren Yuan and Trond Ytterdal for reviewing this thesis. Special thanks also to Marja and Outi. Nokia Research Center and Finnish National Technology Agency. I would like to express my sincerest gratitude to Rami Ahola.
beautiful daughter. my writings seem to turn out to be either dimwitted or naive. Pamppu. Oippa. I would like to thank my mother and father for their love. Jomi. beer. Attila. September 2006 Marko Kosunen . I could not love you more. great cooking. Thanks for your existence. Katri. Therefore I chose to be short and compact.vi Pikkutomi. and great sense of humor. Puotila. not a poet.. teachings. and Ira. and support. The rest of this page was reserved for the praise of my intelligent and goodlooking wife. Thanks also to my sister Marjo and my nephew Antti. Being an engineer. Kimmo and the other ”Boys of Puotila”. Tumppi. Natski. Kartsa et al. and my beautiful and loving daughters. I would also like to thank my inlaws for their support. Auri. Helsinki. and for keeping me relatively sane. thanks for the fun.
. . . . . . . . . . . . Organization of the thesis and research contribution . . . . . . . . Performance metrics . . . . . Phase modulating synthesizers .Contents Abstract Tiivistelmä Preface Contents Symbols and abbreviations 1 Introduction 1. . . . . . . . . . . . . . . 4 Resourceefﬁcient digital ﬁlter design 4. . . . . . . . . . . .1 1. . .2 2. . . . . . Digital QAM transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse shaping ﬁltering . . .1 3. . . . . . . . . . . . .1 Filter design algorithms . . . . . . . . Constant envelope transmitters for power ampliﬁer linearization . . . . . . . . .2 Motivation . . . . . . . .3 2. . . . . . .1 3. . . . . . . . . . . . 3 Transmitter structures 3. . . . . . . . . . . . . .5 Envelope elimination and restoration . . . . . . . . . . . . . . . . . . . . Twostep transmitter . . . . . . . . . . . . . . . . . . . . . . . . . Spreading . . . . . . . . .4 Direct conversion transmitter . . . LINC transmitter . . . i iii v vii xi 1 1 2 5 5 6 9 11 13 13 14 15 16 17 17 18 21 22 2 Direct sequence spreadspectrum quadrature amplitude modulation 2. . . .3 3. . .4.4 Principle of QAM . . . . . . . . . . .1 2. . . . . . . . . . . . . . . . . . . . . . . . . . .2 3. . . . . . . . . 3. . . . . . . . . . . .4. . . . .
. . . . . . .2. . . . . . . . . . . . THD. . . . 6. .5 Direct form structure . . . .3. .2 6. . . . .3 5. . . .1 5. . .3. . . . . . . . . .4 6. . . . . . . . . . . . . . . . . . . SINAD and ENOB . Models and relations of transistor mismatch and static linearity . .2 4. . . . . . . .2. . . . . .5 Static linearity: Gain error. . .1 4. . . . . . . . . . Statistical model of the static linearity . . . . . . . . 4. . . . Halfband ﬁlters for interpolation . . . . . . . . . . . . . . .2 Modulation to quarter of the sampling rate . . . . .3. . 6. . . .3. . . . . . . .3 6. . 22 26 27 28 28 31 33 34 35 35 36 39 39 42 45 47 47 47 49 50 53 53 55 56 57 57 59 73 75 82 89 90 93 Mapping the ﬂoating point ﬁlter coefﬁcients to canonic signed digit format . . .6 6.2. . . . .5. . . .4 Direct digital frequency synthesizers using the lookup table method. . . . . . . . . . . . . . . .3 6. Current source mismatch and yield . . . . . .4. . . .3. .2 General description of the current steering D/A converter . . .2. .1 6. . . . . . . . . . . . . . . . . . . . . . . . . . . Performance metrics . . . . . . . . . . . . .1 6. . . 6 Currentsteering digitaltoanalog converter design 6. Frequency dependency of the output impedance . . . . . Reduction of the sign bit load . . . . . . . . . . DNL and INL . Efﬁcient FIR ﬁlter structures . . . . . . . .2 4. . Other digital modulation methods . . . .2. . . . . . . . . Effects of output impedance variation . . . . . . . . . . . . . . . .2 4. . . . . . . . . . . . . .1. . . .3. . . . . . .2.1 5. . . . . . . .3 4. . .7 From discrete. 104 Sampling jitter . . . . . . Linearity and noise: SNR. . . . Calibration techniques . . . . 4. . . . . Word length effects and scaling . Survey of digital frequency synthesizers . 5. Pipelining/interleaving technique . . . . . . . . . . 6. . . . . . . .3. . . . . 5 Methods for direct digital frequency synthesis and modulation 5. .2 6. . . . . . . . Transposed direct form structure .3. . .4 6. . Regression model for the INL and DNL yields . . Efﬁcient realizations of FIR ﬁlters . .1 4. . . . 109 . . . . . . . . . INL yield models . .1 4. . . . . . . .3. Time domain performance: Settling and glitches . . . . . . . . .4. . .5. . . . . . .2 Distortion due to low frequency impedance variation . . . CORDIC vector rotation algorithm based frequency synthesizer and modulator . . . . . . .1 6. . . . . . . . . . . . . . . .2. . SFDR. . . . .3. . .1 6. . .3 Pulse shaping ﬁlter design algorithm . . . .4 4. . . . .2 Polyphase FIR ﬁlters in sampling rate converters . .2 5. .viii 4. . .to continuoustime domain . . .3. . . . . . . . . . . . . . . . . . . . .2. . .3 6. Frequency synthesis with nonlinear D/A converter . . .1. . .
. .ix 6. . . . . . . . 157 D/Aconverter performance . . . . . . .6 7. . . . . . . . . 189 7.2. .2. . . 191 Dynamic performance . . . . .8. . . . . . . . . . . . 156 D/A converter simulations . . . . .2. . 174 Current source matrices . . . . . . . . . . . 139 Frequency planning . .1. . . .4. . . .1. . .3 7. . . . . . . . . . .2 7. . 172 Output impedance . 184 DNL measurement for calibration . .8 Experimental results . . . . .1 7. . . . . . . . . . . . . . . . . . . .1 6. . . . . . . . . . . . . . .3 7. . . . . . . . . . . 156 Measurement setup . . . . . . . . . . .1. . . .2 7. . .7. . . . . . .8. 142 CORDIC and inverseSINC ﬁlter design .7. . .2. . . . . 116 Jitter due to codedependent clock load . 126 Survey of published D/A converters .8.5 7. . . . . . . . . .7.1 7. . . .2. . . .1. . . . . . . . . . . .1 7. . . . . . . 141 Interpolation strategy . .8. . .7. . . . . . . . . 122 Layout techniques for current source mismatch reduction . 179 Logic for digital calibration . . 188 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Static performance of the D/Aconverter . . . . . . . . .1.7. . .3 6. . 159 QAM Performance . 110 Distortion due to signaldependent jitter . .1 7.3 7. . . . . . .3 7. . . . . . . . . . .5 7. .2. . . . . . 166 7. . . . . . . . .2 7. . . . 152 Enhancement of dynamic properties .9 Effects of sinusoidal timing jitter . . . . . . . . .1. .1. . . . . . . . . .7. . .7. .1 7. .1.8 6. . . .7 CORDIC design .1. . . . . .1. .7. . . . .2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 171 7. . .2 7. 147 7. . . . . .1. . .4 Static matching . . . . . . 141 Digital FIR ﬁlter and interpolator design . . . . . .2 6.2 7.3 Static linearity . .2. . . . . . . .2. . .1. . . . . . . . .2 7. . . . . . . . . . . . . 147 InverseSINC ﬁlter design . 133 139 7 Prototypes and experimental results 7. . 152 7.1 7. . . . . . . 149 Digital ASIC synthesis ﬂow . . . . . . . . 193 Summary . .1 7. . . 149 Simulated QAM performance . . . . . 157 7. . . . . . . . . . . . . . . . . . . . . . . .1. . .2. . . . . . .2. .4 6. . . . .1. . . . . .4 Prototype of WCDMA transmitter . . 119 Jitter due to powerrail interference . .7. . . 177 Dynamic performance . . . . . . . . . . . . .6 7. 159 Dynamic performance of the D/Aconverter . . . . 149 14bit 70MHz Digitaltoanalog converter . .1. . . . . . . .5 7. . . .1. . . . . . . . . . . . 153 Layout issues . . . . . . .1. . . . . . . . . . . 195 . .1. . .7.4. .4 7. . . . . . . . . . . . . . .7 Current source dimensions and DC matching . . . . . . . . . . . . . . . . . . .4 7. . . . . .1.8. . . . . .7. . . . . . . . . . . . . . . . . .
. 227 . . . . . . . . . . . . . .x Conclusions Bibliography A Photomicrograph of the WCDMA transmitter B Photomicrograph of the D/A converter with digital calibration C Jitter energy as a function of signal frequency and jitter amplitude D Fourier transforms of some functions used in this book 201 203 219 221 223 227 D.1 Elementary relations . . . . . . . 227 D. . . . . . . . . . . .2 Elementary functions and operations . . . . . . . . . . . .
e. M) and X(C.g.Symbols and abbreviations α β ∆F ∆ Roll of factor of rootraised cosine ﬁlter Current factor of a MOS transistor Width of the transition band of a ﬁlter Quantization step due to the internal word length of a ﬁlter Phase increment of a DDS or a CORDIC vector rotator DeltaSigma. ∆Σmodulator Quantization step at the output of a ﬁlter Squared approximation error of the yield regression model Error current of ith Error of ith current source. M) φ (n) φd (t) . relative to Ilsb The mean of B(n) Angular frequency (in general) Angular carrier frequency Angular intermediate frequency Angular radio frequency Don’tcare band of a ﬁlter Yield functions of a converter Discretetime angle value Phase angle signal of EER transmitter ∆φ ∆Σ ∆o ε2 f εi εri B(n) ω ωc ωi f ωr f Φband Φ(C.
k2) σ2 β σ2 Id σ2 vt σ2 DNLmax σ2lsb I σ2 t (k) INL σ2 INLmax σ2 iwl σ2 lsb σ2 n σ2 op σ2 s τ A A(n). B(n). and C(n) Precomputed rotation angle value of the kth rotation stage of a CORDIC rotator Correlation factor of INLvalues with input codes k1 and k2 Variance of the β of a transistor Variance of the drain current Variance of the Vt Variance of the maximum value of DNL Variance of a LSB current source Variance of INL with input code k Variance of the maximum value of INL Variance of the noise generated by limited internal word length of a ﬁlter Relative variance of a LSBunit currentsource of a thermometer coded D/A converter Variance of the noise Variance of the quantization noise at the output of a ﬁlter Variance of the symbol error Time misalignment between two pulse sequences Matrix for calculation of ISIrms Subbuses of the phase value bus φ (n) in DDS sine compression Amplitude signal of EER transmitter Current factor matching parameter of a transistor Matrix for calculation of the center coefﬁcient of a ﬁlter Amplitude of c (t) Amplitude of d (t) Threshold voltage matching parameter of a transistor A (t) Abeta Ac ac ad Avt .xii φk ρt (k1.
k2 Internal word length of a ﬁlter Energy band width of d (t) Number of output bits of a ﬁlter Energy band width of s (t) Bit error rate Spreading pulse sequence Covariance matrix of INLs of a segmented converter and it’s element Covariance matrix of a thermometer coded D/A converter Covariance of INLvalues with input codes k1 and k2 Power density function of d (t) Continuoustime data signal Differential nonlinearity Error vector of normally distributed random variables with zero mean and variance σ2 lsb Matrix notation for passband power Matrix notation for stopband power Effective number of bits Error vector magnitude Rootmeansquare error vector magnitude Pulse rate of the spreading sequence c (t) Data rate of d (t) Ct ct (k1. cs k1 .xiii ACLRn Adjacent channel leakage power ratio deﬁned for nth adjacent channel ACPRn Adjacent channel power ratio deﬁned for nth adjacent channel Binary matrix for computing INL of a binary weighted D/A converter B B Bd Bo Bs BER c (t) Cs . k2 ) D( f ) d (t) DNL Eb Ep Es ENOB EV M EV Mrms Fc Fd .
xiv Fpb Fsd Fsi Fs gds gm Gs H(s) h (n) H1 ( f ) hn (t) Passband edge frequency Sampling rate after decimation or downsampling Sampling rate after interpolation or upsampling Sampling frequency. Sampling rate Drainsource conductance of a transistor Transconductance of a transistor Spreading gain Impulse response of a ﬁlter in s domain Discretetime ﬁlter Frequency response of the nth subsystem Impulse response of the nth subsystem of a D/A converter model Discretetime channel ﬁlter of a receiver Discretetime ﬁlter with signeddigit coefﬁcients Combination of the transmitter and receiver channel ﬁlters hr (n) hsd (n) htr (n) Ht ( f ) ht (n) i (n) and q (n) i (t). q (t) Ilsba Ilsb INL INLs INLt INLt (k) Frequency response of a transmit ﬁlter Discretetime channel ﬁlter of a transmitter Discrete time inphase and quadrature data signals Continuoustime inphase and quadrature signals Actual average LSB current LSB current of a D/A converter Integral nonlinearity INL vector for segmented D/A converter INLvector of a thermometer coded D/A converter INLvalue with input code k normalized to Ilsba .
λ) M Minput . respectively L(ht .xv INLzdi INLzsemax INLzse ISI ISIrms L L INL of due to ﬁnite output impedance. differential output Maximum value of INLzsemax INL due to ﬁnite output impedance. also the channel length of a transistor Langrangian cost function for transmit ﬁlter optimization Decimation ratio Maximum presentable number at the input and output of a digital ﬁlter.k Index of the center coefﬁcient of the ﬁlter Power transfer function Power of the current signal channel Power of the current signal channel Power of nth adjacent frequency channel Matrix for passband power computation and one of it’s elements Matrix for stopband power computation and one of it’s elements Despread data signal Autocorrelation function of c (t) Autocorrelation function of d (t) Autocorrelation function of s (t) Raisedcosine Frequency response of a raisedcosine ﬁlter Ps and psi. Mout put Nc P( f ) Pcchan Pcchan Pnth_ad j_chan Pp and ppi.k r (t) Rc (τ) Rd (τ) Rs (τ) RCOS RCOS ( f ) .interpolation factor. single ended output Intersymbol interference Rootmeansquare intersymbol interference Channel length of a MOS transistor Oversampling ratio.
sri (t) st (t) Svt One of the convolution matrices and it’s elements Received inphase and quadrature signals Transmitted signal Constant for distance dependency of the threshold voltage matching of a transistor SER SFDR SFDRzdi SFDRzse Symbol error rate Spuriousfree dynamic range SFDR due to ﬁnite output impedance.xvi rcos (n) rcos (t) Discretetime impulse response of a raisedcosine ﬁlter Continuoustime impulse response of a raisedcosine ﬁlter rrc (t) S S(f) s (n) and ∆s (n) Continuoustime rootraised cosine impulse Code matrix for a segmented D/A converter Power density function of s (t) Discretetime signal s (n) and discretetime derivative s (n)− s (n − 1) s (t) Sbeta Spread data signal Constant for distance dependency of the current factor matching of a transistor Sn and sna.b srq (t). differential output SFDR due to ﬁnite output impedance. single ended output Signaltonoise and distortion ratio Signaltonoise Ratio Pulse duration of c (t) Pulse duration of d (t) Fall time Rise time Sampling interval SINAD SNR Tc Td Tf Tr Ts .
Yk (n) Zc Zk (n) Zl Zop Zu F{ 3G ADC .xvii T HD u (t) Vgs Vss VT W Wb and wi Total harmonic distortion Unit step function Gatesource voltage of a MOS transistor Negative supply voltage Threshold voltage of a MOS transistor Channel width of a MOS transistor Weighting vector for computing the INL of a binary weighted D/A converter and its element Diagonal weighting matrix Diag(Wb ) Wdb Ws W Lopt x (n) xd ( f ) and xi ( f ) Weight matrix of a segmented D/A converter Optimum area of a transistor in static matching sense Discrete time signal (in general) Downsampled and upsampled signals in frequency domain Downsampled and upsampled discrete time signals Amplitude outputs of kth CORDIC rotator stage Load impedance of a unit current branch of a D/A converter in conducting state Phase output of kth CORDIC rotator stage Load impedance of a D/A converter Load impedance of a unit current branch of a D/A converter in nonconducting state Impedance variation of a unit current source of a D/A converter due to switching } Fourier transform Third generation wireless communication systems Analogtodigital converter xd (n) and xi (n) Xk (n).
see also SD and MSD Direct digital synthesizer Enhanced data rate for GSM evolution Envelope elimination and restoration Fast Fourier transform Finite impulse response Gain bandwidth product of an ampliﬁer General Packet Radio Service Group special mobile/Global system for mobile communications I and Q LINC LO LSB LUT MOS MSD Inphase and quadrature Linear ampliﬁcation with nonlinear components Local oscillator Least signiﬁcant bit Lookup table Metal oxide semiconductor Minimum signeddigit. see also SD and CSD .xviii BiCMOS Complementary metal oxide semiconductor process with bipolar transistors Bluetooth Wireless communications standard for shortrange applications CALvalue Code value at the input of the converter that selects the thermometer current source to be calibrated CDF CDMA CMOS CORDIC CSD DDS EDGE EER FFT FIR GBW GPRS GSM Cumulative distribution function Code Division Multiple Access Complementary metal oxide semiconductor Coordinate rotation digital computer Canonic signeddigit.
xix MUX MVN NCO NMOS NRZ P/I PA PDF PLL QAM REFvalue Multiplexer Multivariate normal distribution Numerically controlled oscillator Ntype metal oxide semiconductor Nonreturn to zero Pipelining/interleaving Power ampliﬁer Probability density function Phaselocked loop Quadrature Amplitude Modulation Code value at the input of the converter that is compared to CALvalue RF RMS ROM RZ SAR SD TQFP UMTS VCO VLSI WCDMA WiFi Radio frequency Rootmeansquare Readonly memory Returntozero Successive approximation Signeddigit. General term for 802.11 standard network Wimax WLAN Worldwide Interoperability for Microwave Access Wireless Local Area Network . see also CSD and MSD Thin quad ﬂat pack package Universal Mobile Telecommunications System Voltagecontrolled oscillator Very large scale integrated circuits Wideband Code Division Multiple Access Wireless Fidelity.
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Even though the evolution of the silicon processes has reduced the minimum line width. Beneﬁts of ﬂexibility are obvious in systems like transmitters and receivers. enabling the integration of increasingly complicated systems on a single chip. and the decreasing operation voltages tends to make the analog circuit design more challenging. wireless data transmission systems such as WLAN/WiFi and Wimax have gained popularity. and the fact that these requirements can be met simultaneously by increasing the integration level of the electronics. the power dissipation of the digital parts. which are capable of handling both the narrow voice band and wide data bands. the devices required for analog processing have not scaled along with the minimum linewidth. This is because the portable electronic devices for wireless communication has to be optimized for low power consumption. the trend has been to move from analog to digital signal processing and increase the bandwidth.Chapter 1 Introduction 1. Digital signal processing also enables ﬂexibility in the system. and low manufacturing cost.1 Motivation The rapid growth of the wireless communications market has been the primus motor of the development of integrated circuit technology during the past decade. since programmability and reconﬁgurability can be implemented more easily digitally. . Simultaneously. thereafter. In wireless communication systems. whereas the accuracy of the digital signal processing (DSP) may be selected almost arbitrarily. light weight. It is beneﬁcial to perform most of the computation of the system in the digital the domain. Wireless digital communications have evolved from GSM through services such as GPRS and EDGE towards WCDMA and 3G. operation voltages and. Analog signal processing is sensitive to noise generated in several sources. The minimum linewidth of the semiconductor processes has seemed to be everdecreasing.
The author. the new ideas and circuits presented in this thesis have been partially reported in related publications [1][15]. M. and also designed and implemented the D/A converter core and analog parts related to calibration.Sc. The results obtained are also applied in design presented in [16] and [17]. the ﬁrst consisting of the digitalIF WCDMA transmitter and the second being a currentsteering D/A converter with a digital calibration algorithm. which are the performance bottleneck of the digitalIF transmitter. 1. The research of currentsteering D/A converters was carried out during the years 20012005. the basic principles of the spreadspectrum quadrature amplitude modulation is presented and the performance metrics of the transmitter are given. who also performed most of the algorithm design of the transmitter prototype. Digital signal processing can be performed with a general signal processor. Mikko Waltari.2 Introduction in which the usage of DSP enables the realization of multimode transmitters such as GSM/EDGE/WCDMA or softwareconﬁgurable radio. and thus reduce the need for cooling and maintenance. Research results are applied in the design of two prototype circuits. Jouko Vankka. During the research. In Chapter 2. The ﬁrst part of this work is based on research into hardware efﬁcient realization methods of the digital signal processing required for baseband and the intermediate frequency of the multicarrier wideband code division multiple access (WCDMA) basestation transmitter of the 3rd generation (3G) wireless communication system.2 Organization of the thesis and research contribution The research of the digitalIF transmitters presented in this book was performed during the years 19982001 under the supervision of Dr. with help from Dr. The author participated in the algorithm design and is responsible for the design and implementation of the digital signal processing blocks and D/A converter of the transmitter prototype. In Chapter 3. it is not capable of handling the high data rates typical of digitalIF transmitters. Chapters 25 represent the background for the design of a digitalIF transmitter. Area efﬁcient digital IF transmitters reduce the manufacturing cost of the transmitter chip. under the supervision of the author. is responsible for the design of the calibration algorithm. The thesis is organized as follows. The digital part of the calibration was implemented by Jussi Pirkkalaniemi. decrease power consumption. This system is also often referred to as the Universal Mobile Telecommunications System (UMTS). The second part of this work is based on research into the currentsteering digitaltoanalog converters. the most common transmitter architectures . however. A dedicated DSP system for transmitter purposes is therefore usually used.
Chapter 7 describes the designed prototypes.8 considers the layout techniques used to reduce the effect of the process gradients on the current source mismatch.4 is about calibration techniques.In this prototype.Sc. who also developed algorithms related to ﬁlter design and digital upconverter. In Section 6. and Jussi Pirkkalaniemi [14] is presented.5 considers the distortion effects due to the output impedance variation. Jussi Pirkkalaniemi and Dr.1.2 give an introduction to currentsteering converters and their performance metrics.6. Jouko Vankka. conclusions are drawn. system simulations.1 describes the design and experimental results of the WCDMA transmitter prototype.1 and 6. Dr. Finally. the static linearity of the converter is analyzed. Mikko Waltari. The digital parts of the calibration algorithm were designed and implemented by Jussi Pirkkalaniemi under supervision of the author. The results of this section are partially published in [1][12]. Section 6. Section 6. Section 7. Previously published calibration methods are discussed. Sections 6. the author is responsible of hardware optimization and implementation of digital signal processing blocks. and.2 Organization of the thesis and research contribution 3 are brieﬂy introduced.3. the signal conversion from discretetime digital to continuous time analog is discussed. In Section 6. Waltari also gave valuable instructions for the D/A converter design. In Section 6. Vankka. and the method developed by the author. timingrelated nonlinearities are discussed.9 is a survey of published D/A converters. In Chapter 4. Results are also partially published in [15]. [13] is presented. in Chapter 5. Section 7. Calibration algorithm is developed by the author. and the yield model developed and published by the author. The previously published linearity yield models are compared. . The measurements of the prototype were carried out by the author and Dr.7. Section 6. and distortion mechanisms are analyzed.2 describes the design and experimental results of the D/A converter prototype. methods for resourceefﬁcient digital ﬁlter design are introduced. The design project was supervised by Dr. Mikko Waltari. Vankka and Ilari Teikari M. Chapter 6 contains the theory of the currentsteering D/A converter design. The author is responsible of design and implementation of the D/A converter core including the comparator chain. and the design and implementation of the D/A converter. Measurements were carried out by the author and Jussi Pirkkalaniemi. Section 6. the methods for direct digital frequency synthesis and digital modulation are discussed. Dr.
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1) (2. the signal st (t) is .Chapter 2 Direct sequence spreadspectrum quadrature amplitude modulation In CDMA systems. While receiving. (2. two carriers. More detailed information on the subject can be found in textbooks [18] and [19]. A user in the system may use one or multiple code channels simultaneously. The capacity of the frequency band is divided among the users by assigning a code channel to a single user by using a spreading code. 2. q (t) i (t) . In the following sections.1 Principle of QAM In the quadrature amplitude modulation scheme.1) st (t) = i (t) cos (ωct) + q (t) sin (ωct) = i (t)2 + q (t)2 cos(ωct − φd (t)).2) φd (t) = arctan In other words the information is shifted in frequency around the carrier frequency ωc by multiplying with two orthogonal signals. the fundamentals of direct sequence spreadspectrum QAM are presented in order to give some insight into the design presented in Chapter 7. in phase and quadrature. are modulated with the data sequences i (t) and q (t) (Fig. 2. The spreading also improves system capacity by introducing the gain to the signaltonoise ratio (SNR). the data of different users are transmitted on the frequency band common to all users.
2). t Figure 2. This signal has an autocorrelation function T a −a . downconverted around zero frequency..1)).2 Spreading Let’s assume that the data signal d (t) is an inﬁnite random sequence of pulses with amplitude ad and duration Td (Fig. the data signals i (t) and q (t) can be extracted by lowpass ﬁltering..3) (2. . 2.4) After downconversion. (2. 2.6 Direct sequence spreadspectrum quadrature amplitude modulation i(t) ω cos( t ) c +90 q(t) o ω s (t) = i(t)cos ( t ) + q(t) sin ω t ) ( c c t Figure 2.2 The data signal. The beneﬁt of the QAM is that twice as much data as in bare inphase modulation can be transmitted over the same frequency band due to the fact that both the amplitude and the phase of the carrier are modulated (see. sri (t) = st (t) cos (ωct) 1 1 = i (t) (1 + cos (2ωct)) + q (t) sin (2ωct) 2 2 srq (t) = st (t) sin (ωct) 1 1 = i (t) sin (2ωct) + q (t) (1 − cos (2ωct)) .1 The principle of QAM. Eq. 2 2 (2.
s (t) = c (t) d (t) (2.7) Next the data signal d (t) is multiplied by c (t). Rs (τ) = Rc (τ) Rd (τ) = τ τ a2 1 − Td − τ + Td Tc Tc 2 0 . (2.10) ≃ a2 .9) The power density function of s (t) may now be calculated as [18]. (2. τ > Tc . which contains most of the signal energy. (2.2 Spreading τ a2 1 − Td d 7 Rd (τ) = 0 .2. τ ≤ Td .6) where Fd is the data rate. so the upconverted data occupies the frequency band of 2Fd . Next we may deﬁne a sequence c (t). τ > Td .8) Since c (t) and d (t) are independent of each other. which is a pulse sequence with magnitude 1 value ac = 1 and pulse duration Tc and pulse rate Fc = Tc . the autocorrelation function of s (t) is a product of the autocorrelation functions Rc (t) and Rd (t). (2. The power density function D ( f ) of the data signal d (t) is the Fourier transform of its autocorrelation function D( f ) = Z +∞ −∞ Rd (τ) e− j2π f τ dτ (π f Td )2 πf Fd = a2 Td d sin2 (π f Td ) = a2 Td sinc2 (π f Td ) d = a2 d sinc2 Fd . π2 f 2 (2.5) where τ is the time misalignment between the two pulse sequences [18]. τ < Tc . τ > Tc . 2 has the width of Bd = Td = 2Fd centered at the zero frequency. The autocorrelation function of c (t) is Rc (τ) = 1 − τ Tc 0 . S(f) = Z ∞ −∞ Rs (τ) e− j2π f τ dτ 1 1 + Td Tc sin2 (πTc f ) . The main lobe. τ ≤ Tc .
3.11) Fc that the energy of the signal d (t) is spread to Gs = 2Td = Fd times wider frequency 2Tc band.1. (2. Such a structure is presented in Fig. 2. (2. The gain due to the despreading of the signal is Gs . Other data signals that have been spread with the codes uncorrelated with the spreading signals are not despread. After the spreading. the power of the received signal is maximized relative to the noise. 2.10) can be approximated as sin2 (πTc f ) S ( f ) ∼ a2 Tc = c Tc2 π2 f 2 = a2 Tc sinc2 (πTc f ) c = which has a main lobe of width Bs = α2 sinc2 Fc πf Fc .3 Signal before spreading. so Tc is also called the chip time and Fc the chip rate.4 and 2. 2. Eq. that after de . E Signal f Figure 2.8 Direct sequence spreadspectrum quadrature amplitude modulation When Td ≫ Tc .12) where τ is the timing misalignment. This is the main idea of the code division multiple access. This is presented in Figs. which means. an ordinary QAM structure. This multiplication despreads the data signal to its original frequency band while it spreads all possible jamming signals.5. Gs is called spreading gain for the reason given in the next paragraph. for example. This means spreading pulses are also called chips. (2. users in the system can send their data on the same frequency band and the data sequences can be separated from each other by using uncorrelated spreading sequences for each user. The quality of despreading improves as the τ diminishes. In the ideal case τ = 0. While receiving. data may be transmitted with. the sequence of spread data is multiplied with the same sequence that has been spread with r (t) = d (t) c (t) c(t − τ). The 2 Tc = 2Fc centered at zero frequency.
In a WCDMA system. the signal to noise ratio is increased with that factor compared to SNR at the receiver input.3 Pulse shaping ﬁltering Usually it is necessary to limit the frequency band occupied by the signal in order not to disturb the signals transmitted on other frequency bands of the same or different systems.4 Spread signal in noisy environment with jammer signal and other users. This means that the same bit error rate (which is the function of SNR) can be achieved with Gs times worse SNR at the receiver input than in the nonspreading systems. This is the reason why the channel bandwidth limiting ﬁlters are usually called pulse shaping ﬁlters when used in transmitters. The spreading is performed with chip rate Fc and the ﬁltering is .5 Signal in receiver after despreading. 2. the signal to be transmitted is data sequence spread with the spreading sequence. E Filter Signal Other users Noise Jammer f Figure 2.2. spreading and ﬁltering.3 Pulse shaping ﬁltering 9 E Jammer Other users Noise Signal f Figure 2. The ﬁltering of the data sequences has to be performed in the time domain so that sequential pulses do not disturb each other.
13) with N samples (N is odd) is sin π (1−α)(n−Nc ) + 4α(n−Nc ) cos π (1+α)(n−Nc ) L L L π (n−Nc ) L 1− 4α(n−Nc ) 2 L rrc (n) = . (2. (2. the combination of these two ﬁltering operations corresponds to a raised cosine (RCOS) ﬁltering [21]. .10 Direct sequence spreadspectrum quadrature amplitude modulation accomplished with a rootraised cosine ﬁlter [20]. 0 < k < −∞. The sequence of raised cosine impulses is presented in Fig.13) where Tc is the chip duration and α is the rolloff factor. 0 ≤  f  ≤ (1 − α) Fc 2 0 and an impulse response t sin π Tc rcos (t) = t π Tc t sin απ Tc t 1 − 2α Tc πα(n−Nc ) L 2 . 2.  f  > (1 + α) Fc . This means that there is no inter2 symbol interference (ISI) at the multiples of sampling interval Ts . The ideal raisedcosine ﬁlter has two important properties. (2. It has a bandlimited frequency response given by 1 Fc 1 π αFc RCOS ( f ) = 1 2Fc 1 − sin  f  − Fc 2 . which has the impulse response t t t sin π Tc (1 − α) + 4α Tc cos π Tc (1 + α) t π Tc t 1 − 4α Tc 2 rrc (t) = . A causal discrete time counterpart of Eq. 2 (2. Typically L= Tc Ts is an integer. When used for pulse shaping ﬁltering in the transmitter and channel ﬁltering at the receiver. L = Tc = Fc is the oversampling 2 Ts 1 ratio. 0 ≤ n ≤ N − 1. 0 ≤ n ≤ N − 1 . (2. (1 − α) Fc ≤  f  ≤ (1 + α) Fc 2 2 . This impulse response has the property of having a zero value for any integer value of n = N−1 ± kL. Ts is the sampling interval and Fs = Ts is the sampling frequency.6. Tc Ts (2.14) Fs where Nc = N−1 is the index of the center coefﬁcient.17) where Nc = is the index of the center coefﬁcient (N is odd) and L = is the oversampling ratio.15) .16) which has a causal discrete time equivalence of length N [21] given by rcos (n) = N−1 2 sin π(n−Nc ) L π(n−Nc ) L cos 1− 2α(n−Nc ) 2 L .
which are the probabilities that an error occurs when receiving one transmitted bit or one transmitted symbol.6 −0.4 Magnitude 0. When designing the transmitter. EV M . information on the other signal processing parts of the system is not necessarily available.4 Performance metrics Two fundamental metrics of digital communication system performance are bit error rate (BER) and symbol error rate (SER). [18]. SNR is deﬁned via the error vector magnitude (EV M). However. Actually. signaltonoise ratio (SNR).4 −0. 2. respectively. including ISI and quantization noise etc. when the basestation transmitter is designed. so only the contribution of the subsystem under design to SNR and BER can be controlled.6 0. the ISI value is not zero in practical cases.2 −0. detection type etc. EV M consists of all noise in the system. Because neither the transmit ﬁlter nor the receive ﬁlter are ideal rootraised cosine ﬁlters and neither have inﬁnite length. which is deﬁned to be the root mean square (RMS) deviation of the received symbol given as a percentage of the symbol magnitude [20]. In this book. this is an RMS noise amplitude given as a percentage of the symbol magnitude.4 Performance metrics 11 Raised cosine impulses 1 0.8 −1 T 2T 3T 4T 5T 6T 7T 8T 9T 10T 11T 12T 13T 14T 15T 16T 17T Sampling time Figure 2. The ISI value is one of the performance metrics discussed in next section.6 ISIfree impulses.8 0.2 0 −0. channel characteristics.2. Both of them are dependent of modulation type.
(2. (2.21) where Pnth_ad j_chan is the power of nth adjacent frequency channel and Pcchan is the power of the current signal channel. which is the inverse of ACPRn ACLRn = 10 log10 Pcchan Pnth_ad j_chan . . i=0 htr (Nc + iL) htr (Nc ) 2 . In addition to ISIrms . L is the oversampling ratio and Nc = N−1 is the index of the center coefﬁcient of the 2 ﬁlter htr (n). EV Mrms is deﬁned as EV Mrms = σ2 + σ2 s n = S 2 ISIrms + σ2 n S2 .12 Direct sequence spreadspectrum quadrature amplitude modulation as a function of ISI and quantization noise has to be determined and minimized. K = f loor Nc − 1 . ISIrms is deﬁned as σs ISIrms = = S ∑K i=−K. n and S is the magnitude of the received symbol. L (2. This means minimization of the contribution to the additive noise σ2 of the adjacent channel. the contribution of the current frequency channel to EV M of the adjacent frequency channels has to be minimized.20) or as the adjacent channel leakage power ratio. ACLRn and EV Mrms are considered to be the key performance metrics of the basestation transmitter throughout the design process described in this book. N is the number of the ﬁlter coefﬁcients (odd). (2. The amount of this n contribution is given as the adjacent channel power ratio (ACPRn ) in decibels ACPRn = 10 log10 Pnth_ad j_chan Pcchan . σ2 is the noise added by the system.18) where σ2 is the variance of the symbol error generated by the nonidealities of the s combination of the transmit and receive ﬁlters.19) where htr (n) is the combination of the channel ﬁlters of transmitter and the receiver.
[41]. [24]. [29]. [35].Chapter 3 Transmitter structures The most commonly used (and published) transmitter architectures are direct conversion [22]. A two step transmitter can be realized either with an analog or digital intermediate frequency (IF) part. [40]. conversion transmitters. The bandpass ﬁlter . [30]. [43] are used in narrow band phase and frequency modulators. Direct conversion and twostep transmitter structures are usually used in the amplitude modulators. [39]. [47] in which the signal at the IF is still basically the sinusoidal carrier multiplied by the ﬁltered data. 3. [28].1 Direct conversion transmitter The principle of the direct conversion transmitter is presented in Fig. [31]. [27] and twostep transmitter [22]. [32]. [42]. Two transmitter types used with the power ampliﬁer (PA) linearization techniques [44]. because the linearization techniques require that the signals are presented in a different format at the IF frequency compared to the feedforward or lookup table methods[46]. [33]. In direct i(t) D/A 90o cos( ω t ) rf Digital baseband signal processing q(t) s (t) =i(t)cos( ω t ) + q(t) sin( ω t ) t rf rf D/A Figure 3. [26]. 3. [36]. [23]. the bandlimited baseband signals are converted directly up to the radio frequency ωr f with inphase and quadrature carriers. whereas the frequency synthesizer based transmitters [38]. [45] are also described.1. [25].1 Direct conversion transmitter. [34]. [37].
In this structure the carrier i(t) D/A cos( ( ω −ω ) t ) rf if 90 o Digital baseband signal processing q(t) s (t) =i(t)cos( ω t ) + q(t) sin( ω t ) t rf rf cos( ω t ) if D/A Figure 3. the additional attenuation of the adjacent channel spurs and noise may be achieved by using a bandpass ﬁlter at the IF. An additional bandpass ﬁlter is needed to ﬁlter away the undesired carrier at the frequency ωr f − 2ωi f . The strong signal at the output of the power ampliﬁer may couple to the local oscillator (LO). signal is formed by mixing two lower frequency signals. [48]. 3. 3. the problem of injection pulling can be alleviated by using an offset LO directconversion structure (Fig.3. the baseband data is ﬁrst upconverted i(t) D/A o Digital baseband signal processing q(t) cos( ω t ) if s (t) =i(t)cos( ω t ) + q(t) sin( ω t ) t rf rf 90 D/A cos( ( ω −ω ) t ) rf if Figure 3.3 Twostep transmitter.14 Transmitter structures after the signal summation is used to suppress the outofband signals generated by the harmonic distortion of the carrier. The drawback is that the stop band . This means that the frequency of the local oscillator is pulled away from the desired value. the quadrature modulation is performed at a ﬁxed lower frequency resulting in better matching between inphase and quadrature (I and Q) carriers. The structure of this kind of transmitter is quite simple. it suffers from the following drawback. The twostep transmitter has two advantages. which is usually a voltage controlled oscillator.2). 3. First.2 Twostep transmitter The injection pulling can also be avoided by using the twostep transmitter presented in Fig. which in turn diminishes the crosstalk between I and Q data streams. In this structure.2 Offset LO directconversion transmitter. The severity of the injection pulling is proportional to the difference between the frequency of the local oscillator and the frequencies at the output of the PA.(or multiple) step transmitter can be considered as a dual of the superheterodyne receiver [22]. causing the phenomenon that is known as injection pulling [22]. The two. By taking advantage of that. however. Second. to the intermediate frequency ωi f and then to the desired radio frequency ωr f .
such as a phase locked loop (PLL) or a direct digital synthesizer (DDS). [39]. often also called a numerically controlled oscillator (NCO) .4. thus producing a phase modulated carrier at radio frequency (RF). With this kind of structure. by controlling the frequency divider of the PLL with a pulse shaped ∆Σmodulated data stream. They are often used in the same kind of applications as their analog counterparts. where the . The usable bandwidth of the data is limited by the bandwidth of the loop ﬁlter H(s). Instead of using an analog frequency synthesizer. Because of this. [41]. The basic principle of the digital phase modulator is presented in Fig. 3. preventing the usage of this kind of transmitter in wideband systems. [42]. it has become increasingly interesting to implement multimode basestation transmitters.3 Phase modulating synthesizers When the narrow band phase or frequency modulation is performed. both frequency and phase synthesizers can be realized (the data could also be added to the ”frequency control” shown in Fig. The PLLbased modulator is presented in Fig. This kind of transmitter is used in systems such as GSM [39]. The phase comparator detects the phase difference between the reference oscillator and the output of the divider and tunes the voltagecontrolled oscillator (VCO) to minimize the average phase difference. H(s) ω rf divider data Pulse shaping ∆Σ Mod Figure 3.5 ). thus modulating either phase or frequency. the phase modulating synthesizer is often used [38].4 PLL based modulator. The synthesizer can be either an analog one. the phase modulator can also be realized with a digital frequency synthesizer [50]. This kind of transmitter generates the modulated carrier ω ref Phase Comp.3 Phase modulating synthesizers 15 attenuation at the RF frequency has to be larger than in a direct conversion transmitter because the signal component at the frequency ωr f − 2ωi f has the same power as the desired sideband. [40] or Bluetooth [49].3. 3.5. [40]. but they do not suffer from loop ﬁlter bandwidth limitations like the PLL based synthesizers do. [43]. 3. 3.
the efﬁciency is even further reduced because the ampliﬁer has to be biased according to the maximum signal amplitude.[46] and lookuptablebased methods [47] are basically conventional QAM transmitters with linearizing predistortion. 3. E or F) ampliﬁers because the constant envelope signals produce less distortion in the signal frequency band than the signals with a varying envelope [22]. With constant envelope signals. In order to increase the spectral efﬁciency. Constant envelope signals are. however. EDGE. phase or frequency modulated signals. [17]. whereas techniques such as feedforward. . Even if the distortion problem is solved by using a more linear (class A or AB) ampliﬁer. it is not possible to use a nonlinear (power efﬁcient) PA. and WCDMA. A high crest factor causes the following problems. the distortion of the nonconstant envelope signal causes spectral regrowth (widens the signal spectrum) and therefore disturbs the adjacent signal bands [51]. modulation techniques in which both the amplitude and phase are varying (such as the multilevel QAM) have to be used. which have. a poor spectral efﬁciency.16 Transmitter structures Sine ROM Frequency control Phase accumulator Cosine ROM DAC Data Pulse shaping Figure 3. Difﬁculties arise when the average transmitted power is much lower than the maximum peak power.5 Digital phase modulation. because the distortion destroys the signal integrity and detection of the information that is coded to the amplitude becomes more difﬁcult or impossible. The ratio of the peak power to average power is called the crest factor.4 Constant envelope transmitters for power ampliﬁer linearization The PA linearization techniques described in this section require special signal decomposition at the baseband or at the IF frequencies. D. Also. First. phase or frequency modulation is added to the digital frequency synthesizer used for the digital QAM modulator enabling the same transmitter to be used in multiple communications standards such as GSM. They can therefore be considered as separate transmitter architectures. for example. it is possible to use nonlinear powerefﬁcient (class C.
The amplitude information A (t) is added to the signal by controlling the supply voltage of the ampliﬁer.4. 3. 3.a. 3. as an outphasing method [54]).4.4 Constant envelope transmitters for power ampliﬁer linearization 17 Both of the methods described in this section are based on the decomposition of the IF signal. The relationship between the general amplitude modulation and the decom Vdd A(t) cos( ω t − φd(t)) Vdd adj. where A (t) = i (t)2 + q (t)2 q (t) . . which allows the usage of a nonlinear power ampliﬁer.3. The IF signal is decomposed in the constant envelope components. [52] transmitter is presented in Fig.k. (3.2 LINC transmitter LINC is an abbreviation meaning linear ampliﬁcation with nonlinear components [45].7.1 Envelope elimination and restoration The envelope elimination and restoration (EER) [44]. 3. i (t) (3.6.1) has a constant envelope and can be ampliﬁed with a nonlinear PA.1) φd (t) = arctan The cos (ωt − φd ) term in Eq. 3. posed presentation of Fig. PA A(t) cos( ω t − φd(t)) Figure 3. [53] (a.2) (3.6 is St (t) = i (t) cos (ωt) + q (t) sin (ωt) = A (t) cos (ωt − φd (t)) . The LINC transmitter is presented in Fig.6 Envelope elimination and restoration. The main weakness of this method is that it requires good matching between the amplitude branch and the carrier branch.
The input signals of the power ampliﬁers are formed by further expanding Eq. If the matching is not perfect. the quality of the signal is degraded. and therefore a high sampling rate is usually required for the DSP. 3. Also. In addition. resulting in efﬁciency degradation. the sampling rate conversion (interpolation) between the data input sampling rate and the sampling rate of the frequency synthesizers is needed. = arccos Amax (3. In order to make digital modulation possible. = 2 2 (3.18 A max 2 Transmitter structures cos( ω t + φdc (t) − φd(t)) PA A(t)cos( ω t − φd(t)) A max cos( ω t − φ (t) − φ (t)) dc d 2 PA Figure 3.7 LINC power ampliﬁcation. the lossless summation of highpower signals is very difﬁcult. 3. which are discussed in Chapters 4 and 5. resulting in s (t) = A (t) cos (ωt − φd (t)) = Amax cos (φdc ) cos (ωt − φd (t)) Amax Amax cos (ωt + φdc − φd (t)) + cos (ωt − φdc − φd (t)) .4) The main weakness in the LINC realizations. (3.1). is the matching between the signal paths in the analog domain.3) in which A (t) = i (t)2 + q (t)2 Amax = max (abs (A (t))) A (t) φdc (t) = arccos Amax i (t)2 + q (t)2 .5 Digital QAM transmitter The digital QAM transmitter is presented in Fig. . The digital signal processing part of the transmitter usually consists of digital pulse shaping ﬁlters and a digital frequency synthesizer. as in the EER method.8. the bandwidth of the signal components is increased when compared to the original signal.
The digital QAM also has all the beneﬁts that DSP provides. eliminating the gain and phase imbalance problems between I and Q branches. It is also possible to implement several types of signalenhancement techniques with digital signal processing. amplitude and phasedistortion compensation and powerampliﬁer linearization with predistortion techniques. The main beneﬁt of the digital QAM transmitter is that the modulation does not suffer from any kind of physical accuracy limitations or distortion that may occur when an analog multiplication is used to produce the QAM signal. This also requires ﬁltering. and the accuracy of the D/A converter. the digital QAM has the beneﬁt of lossless signal addition and mismatchfree performance. Digital transmitters are mainly used in systems like cable modems and basestation transmitters. [36]. which makes it unusable in portable devices. in which the large power dissipation is not a problem [37]. When used in multicarrier transmitters.8 Digital QAM transmitter. . including. [35].5 Digital QAM transmitter i(t) 19 Digital baseband signal processing q(t) 90o cos( ω t ) if D/A cos( ( ω −ω ) t ) rf if s (t) =i(t)cos( ω t ) + q(t) sin( ω t ) t rf rf Figure 3. The main limitations of the usage of the digital QAM are the high power dissipation. the frequency resolution of the digital frequency synthesizer can be selected arbitrarily. but not limited to. which is discussed in more detail in Chapter 4. This allows the frequencies of the carriers to be freely selectable within the frequency band allocated to the system. For example. Another beneﬁt is that there is only one signal branch in the analog domain.3.
.
Speed of computation is often considered a ﬁgure of merit when speaking about DSP chips. . The main resources that we are dealing with are power. The computation speed is ﬁxed by the system speciﬁcation. then area. In this chapter. the order of priorization of the resources is ﬁrst area. it is almost always power. It should be kept in mind that. It can be shown that each of these can be traded off against each other. although not meaningless. some techniques for a resourceefﬁcient ﬁlter design are discussed. For the mobile applications. The same techniques may also be applied in order to achieve lowpower performance. that is.1. in the design described in Section 7. increasing the area means increasing the price of the chip. The topdown method is used to describe the techniques of the areaefﬁcient ﬁlter design. However.Chapter 4 Resourceefﬁcient digital ﬁlter design Resourceefﬁcient DSP generally becomes a topic when the system size integrated on a single chip increases. speed and area. so the special methods for highspeed designs are not considered. by increasing the chip area. then power. Less power means the possibility of integrating more on a single chip without meltingup the package or without needing to install a cooling fan. the power optimization is less important. hence it is only a question of which one of these properties is the most important one in a speciﬁc design case. For the nonportable application. The fact is that speed can be increased by using such techniques as pipelining and parallelism.
The combination of these two ﬁlters is the time domain convolution of their impulse responses K−1 htr (n) = = ht (i)hr (n − i) i=0 htT Sn hr . the stopband attenuation and ISI may be traded off against each other. but this worsens ISI performance. [56].1. Most of the algorithms used for the ﬁnite impulse response (FIR) ﬁlter design.22 Resourceefﬁcient digital ﬁlter design 4. sna.1 Filter design algorithms 4. b = n + 2 − a. This problem may be alleviated by using some window function.b = 0 otherwise. The Lagrange optimization method is also used in [59] to design ﬁlters or multirate systems. However.17)) as ﬁlter coefﬁcients. 1≤b≤K 1 ≤ a ≤ I. The method goes as follows. ISIrms can be presented in . and the stopband attenuation is usually poor with a small number of coefﬁcients. which is not desirable.b = 1. the performance is far from ideal. ∑ n = 0 . . One way to design ﬁlters that have at least some kind of ISI properties is to use the sampled impulse response of the rootraised cosine ﬁlter (Eq. such as the methods introduced in [55]. An ideal rootraised receive ﬁlter is approximated with hr (n) with length I (odd). A better method for ﬁnding the pulse shaping ﬁlter coefﬁcients was described in [6]. N − 1. (2.2) Next ISIrms has to be deﬁned as a function of ht (n). which is based on Lagrange optimization. We try to design a transmit ﬁlter ht (n) of length K in such a way that ISIrms is minimized and ACLR is maximized.1 Pulse shaping ﬁlter design algorithm The pulse shaping ﬁlter design has two main objectives: minimization of the inter symbol interference (ISI) and maximization of the adjacent channel leakage power ratio (ACLR). such as Kaiser. N = K + I − 1 (4. Both ﬁlters have the same oversampling ratio L. . are suitable for only the stopband attenuation maximization (or equiripple ﬁlter design) and does not take ISI into account. but usually the number of coefﬁcients for the practical values of ACLR and ISI becomes quite high. (4. Windowing may also widen the pass band.1) in which Sn is a I × K convolution matrix with elements sna. With the windowing method. [57] and [58].
we have a matrix presentation for the normalized ISI. Fs Fs i=0 k=0 Because sin (−x) = − sin (x). the term K−1 K−1 j i=0 k=0 ∑ ∑ ht (i)ht (k)sin 2π f (i − k) Fs (4.7) K−1 K−1 2π f (i − k) 2π f (i − k) − j ∑ ∑ ht (i)ht (k) sin . Nc = L 2 (4. The amplitude frequency response of the ﬁlter may be written as K−1 Ht ( f ) = = n=0 K−1 n=0 ∑ ht (n)e− j ∑ ht (n) 2π f n Fs cos 2π f n 2π f n − j sin Fs Fs .3) = where A= and i=−M .6) where Fs is the sampling frequency. M = f loor( Nc − 1 N −1 ) .8) equals zero. htT Ac AT ht c (SNc hr ) (SNc hr ) hr T . (4. Next the matrix equations for the passband and stopband power of the transmit ﬁlter ht (n) are derived.1 Filter design algorithms 23 matrix form 2 ISIrms = T M ∑i=−M. in which Nc = N−1 2 (4.8) in Eq. The power transfer function may then be written as P ( f ) = Ht ( f )2 K−1 K−1 = = i=0 k=0 K−1 K−1 i=0 j=0 ∑ ∑ ht (i)ht (k)e− j Fs ∑ ∑ ht (i)ht ( j) cos 2π f i ej 2π f k Fs (4. i=0 htT (SNc +iL hr ) (SNc +iL hr ) ht htT htT AAT ht .5) (N odd) is the index of the center coefﬁcient of the combination of transmit and receive ﬁlters.i=0 ∑ M SNc +iL hr (4. Now. and the power transfer function of the transmit ﬁlter ht (n) .4.4) Ac = SNc hr . (4.
in which Ps is a K × K matrix with elements psi.10) K−1 K−1 i=0 k=0 ∑ ∑ ht (i)ht (k) π(i − k) sin −Fs 2 and for stop bands from Es = = Z −Fsb − Fs 2 to Fsb and Fsb to Z Fs 2 Fs 2 P( f )d f + P( f )d f sin (π (i − k)) − sin 2πFsb (i − k) Fs .11) Fsb K−1 K−1 i=0 k=0 ∑ ∑ ht (i)ht (k) π(i − k) Fs We may write the passband power in the matrix form E p = htT Pp ht in which Pp is a K × K square matrix with elements ppi.13) Similarly. Ep = = Z Fpb −Fpb P( f )d f Fs 2πFpb (i − k) .15) 2 Now. E p and Es .9) Now we may discover the integrated power on some passband from −Fpb to Fpb . for the stopband power we get Es = htT Ps ht . when we have the matrix equations for ISIrms . we may write the . (4. Fs π(i−k) (4.24 Resourceefﬁcient digital ﬁlter design may be written as P ( f ) = Ht ( f )2 K−1 K−1 i=0 k=0 = ∑ ∑ ht (i) ht (k) cos 2π f (i − k) . (4. Fs (4.k = 2Fpb .k = Fs − π(i−k) (4. (4.14) Fs − 2Fsb . Fs (4.12) when sin 2πFpb (i−k) Fs i−k = 0 otherwise. when sin 2πFsb (i−k) Fs i−k = 0 otherwise.
22dB ISI 59.15dB 73.16) 2 in which the a and b are the weight factors for the stop bandpower and the ISIrms . (4. The main shortcoming of this algorithm is that the effect of the weighting factors a and b has to discovered by trial and error. the oversampling ratio is 2 and the sample frequency is normalized to that.4. λ) = htT Pp ht − ahtT Ps ht − bhtT AAT ht + λ htT Ac − 1 .08dB 106.19) (4.1 Comparison of ﬁlter design methods. Method Truncation Window with Kaiser.18) we obtain ht = Q−1 Ac (Q−1 Ac )T Ac . (4. the effect of the ﬁlters after the pulse shaping ﬁlter in the transmitter may be compensated.21dB 40.30dB 36.17) and (4. λ) = 2Pp ht − 2aPs ht − 2bAAT ht + λAc = 0 ∂ht ∂L(ht . It should be noted that the ﬁlter that was used for the receiver may also include the combination of all ﬁlters in the transmitter after the pulse shaping ﬁlter.38dB 71. 4.61Hz to 1Hz. Results of different ﬁlter design methods are compared in Table 4.10dB In simulations. The pass band is deﬁned to be from 0 to 0.07dB 45. β = 4 Lagrange Rootraised cosine with 1001 coefﬁcients ACLR 45.1 Filter design algorithms 25 Lagrangian cost function to be maximized L(ht .17) (4. (4.61Hz and the stop band (adjacent channel) from 0.1. λ) = htT Ac − 1 = 0. The number of the ﬁlter coefﬁcients is 37 for each ﬁlter. λ rule sets the value of the center coefﬁcient of htr (n) to be one. ∂λ By setting Q = 2Pp − 2aPs − 2bAAT and solving Eqs.20) (4.1. With this method. It can be seen that the ACLR value of the ﬁlter designed with the window method suffers from the increased width of the pass band. The frequency responses of the ﬁlters are presented in Fig. Table 4.18) which is the Lagrange optimized transmitter ﬁlter. . By taking the partial derivatives and setting them to zero we get ∂L(ht .
In addition. halfband ﬁlters may be used. The second is that they should be as simple as possible. or the aliasing band in the case of decimation.21) where K is a factor depending on the stopband and passband ripple characteristics of the ﬁlter.1 Frequency responses of the ﬁlters designed with different design methods. for example. The second best approach compared to comb ﬁlters is to interpolate in steps of two if possible. When we have to interpolate or decimate signals with a reasonably wide bandwidth compared to sampling frequency. when interpolating by two.26 Resourceefﬁcient digital ﬁlter design Comparison of filter design methods 0 −10 −20 −30 Truncation Window Lagrange Ideal Relative power [dB] −40 −50 −60 −70 −80 −90 −100 −110 −120 0. Halfband ﬁlters have the center of their transition band at the quarter of the sampling frequency. They can be designed with any of the ﬁlter design algorithms described in. Halfband ﬁlters . This is because the number FIR ﬁlter coefﬁcients needed for the ﬁltering has an approximate dependency [58] N∼K = Fs . Filters used in sampling rate conversion must fulﬁll two criteria.2 Halfband ﬁlters for interpolation When sampling rate conversion takes place.61 0.1. ∆F (4. the usage of comb ﬁlters [60]. The ﬁrst and most important is that they have to ﬁlter out the image band in the case of interpolation.25 0. digital ﬁlters are needed. Fs is the sample frequency and ∆F is the width of the transition band. [58].75 Normalized frequency Figure 4. 4. [61] is not preferable because they introduce droop on their pass band. However a shortcut for their design has been introduced in [62].5 0.
The beneﬁt of the SD representations is that the multiplication op . In SD presentation. 0. Multiplication of two ﬁxed point number consumes a lot more power and area on silicon when compared to summation. it is convenient to normalize the maximum value of the ﬁlter coefﬁcient so that the maximum power of two is zero. Because the ﬂoating point computation is quite tricky to perform on the silicon. the presentation is said to be a minimum signed digit (MSD) presentation. cni ∈ {−1. This is expandable to s. it is preferable to use ﬁxed point presentations of the ﬁlter coefﬁcients. In the case when the ﬁlter has constant coefﬁcients it is preferable to use a signed digit (SD) presentation for the ﬁlter coefﬁcients [64]. (4.2 Mapping the ﬂoating point ﬁlter coefﬁcients to canonic signed digit format 27 have the property that every other of their coefﬁcients except the center coefﬁcient (odd N) has zero value. It is also possible to present the ﬁlter coefﬁcient only with some limited accuracy by ﬁxing the minimum value of i. 4. For example 0. in decimal notation can be presented as ”1 0 1” or ”0 1 1” in signed digit presentation. This representation is called the canonic signed digit presentation (CSD).23) When the number is presented with a minimum number of nonzero digits. the method for efﬁcient ﬁlter design for ﬂoating point presentation of the ﬁlter coefﬁcients was presented. Moving from ﬂoating point to the ﬁxed point presentation degrades the accuracy of the presentation and introduces error into the ﬁltering operation.c. 1} . the ﬁlter coefﬁcient is presented as sums and differences of powers of two h (n) = i=−∞ ∑ ∞ cni 2i . in which every Lth coefﬁcient is zero except the center one [62]. cni ∈ {−1. Φband ﬁlters [63].75. This leads to the approximation of h (n) hsd (n) = i=−p ∑ 0 cni 2i . The halfband ﬁlters that are used in the transmitter of Chapter 7 are designed with the Least Squares error minimization algorithm [58] and by using the ”trick” described in [62]. (4.22) In digital ﬁlters. Φband ﬁlters are ﬁlters that have L − 1 don’t care bands. but there is only one MSD presentation in which there is no nonzero digits in parallel. 0. of which ”1 0 1” is CSD presentation. 1} .2 Mapping the ﬂoating point ﬁlter coefﬁcients to canonic signed digit format In the previous section.4. There can be multiple MSD representations for a single number.
. The decimation and interpolation and their efﬁcient realizations are described in the following paragraphs. for example. The equiripple design algorithms usually give poorer power attenuation on the stop band than the ﬁlters that have been designed in the sense of the least squares stopband. n L 0 otherwise.e. the modiﬁcation of the method presented in [67] was used. while the decimation consists of ﬁltering followed by downsampling. [68]. [69]. The interpolation consists of upsampling followed by ﬁltering.25) which is a suitable format when. Almost same kind of method was used in [70]. 4. a couple of well known methods are described. decimation). 4.24) can also be presented with discrete Fourier series as xi (n) = 1 L−1 n j 2πnl e L . interpolation) and downwards (i. The upsampling operation for the data sequence x (n) may be described with xi (n) = x n L . Several algorithms have been presented for mapping the ﬂoating point or regular two’s complement presentation to the CSD presentation [65]. ∈Z (4.1 Polyphase FIR ﬁlters in sampling rate converters The basic operations in sampling rate conversion are converting the sampling rate upwards (i. This is because the parameter to be optimized is the adjacent channel power relative to the channel power.28 Resourceefﬁcient digital ﬁlter design eration can be realized by using only adders/subtracters and shift operations that can be realized with hardwired shifts. Equation (4. In this chapter. [66]. not the ripple of the power transfer function.24) which means that L − 1 zeros are inserted between the samples. The method was modiﬁed in order to trade off ACLR and ISI rather than the peak amplitude ripple and ISI. analyzing upsampling in the frequency domain. ∑x L l=0 L (4. [67]. the further area and power reductions may be achieved by rearranging the computation on the silicon chip. In the design described in Chapter 7.3 Efﬁcient FIR ﬁlter structures Once the ﬁlters have been converted to the SD representation.3.e.
means that the spectrum is the same.e.4. 4. by substi2π f tuting Z = e j Fs ). The effects in the frequency domain are presented in Fig. resulting in Xi ( f ) = = = = 1 L−1 L(N−1) n j 2πnl − j 2π f n ∑ ∑ x L e L e LFs L l=0 n=0 −j F 1 L−1 N−1 si ∑ ∑ x (b) e L L l=0 b=0 2πb Fsi f −l L (4.2.26) Fsi 1 L−1 ∑ X( f − l L ) L l=0 1 L−1 ∑ X( f − lFs ) = X( f ) L l=0 n L (4. meaning that there are unwanted images between the new sampling frequency and the original signal band. The effects of the upsampling in the frequency domain can be discovered by calculating the Ztransform of xi (n) and by evaluating it on the unit circle (i.2 Effects of interpolation in the frequency domain.3 Efﬁcient FIR ﬁlter structures 29 Downsampling may be described with xd (n) = x(nM).27) = b and LFs = Fsi . which means that only every M th sample of x(n) is included in xd (n). This where Fs is the sampling frequency before interpolation. The images should be ﬁltered out after upsampling because they contain redundant . although the sampling frequency has been changed. 0 Fs 2 Fs L Fs f Images 0 Fs 2 Fs L Fs f Figure 4.
the signal should be bandlimited before decimation (i. .30 Resourceefﬁcient digital ﬁlter design information. .4 and holds for every L and M [58]. 0 Fs f 0 Fs M 2 Fs M Fs f Figure 4. M l=0 (4. The polyphase decomposition of the interpolation ﬁlter and one possible realization of it are presented in Figs. for example contaminate signals on the adjacent frequency bands. Interpolation and decimation ﬁlters can be realized efﬁciently by using socalled polyphase decomposition. which may.5 and . M − 1.e.3). 4. This means that the spectrum after decimation contains M aliased components from the frequency bands centered l Fs . l = 1 . For downsampling.3 Effects of decimation in the frequency domain.28) in which b = nM and Fsd = Fs . Polyphase decomposition is based on identities presented in Fig. In order to M avoid aliasing (Fig. 4. 4. xd (n) in the frequency domain may be written as N−1 M Xd ( f ) = = = = n=0 ∑ x(nM)e ∑ − j 2πn f F sb N−1 b=0 2πbl 1 M−1 ∑ x(b)e j M M l=0 e− j 2πb f Fs Fs 2πb 1 M−1 N−1 ∑ ∑ x(b)e− j Fs ( f −l M ) M l=0 b=0 1 M−1 ∑ X( f − lFsd ). the signal power of the aliasing bands should be zero).
8.5 Polyphase decomposition of the interpolation ﬁlter.7 and 4. In the case of FIR ﬁlters with symmetrical or anti symmetrical coefﬁcients (linear phase FIR ﬁlters).3.4 Identities for the order of ﬁltering and up/down sampling. 4. The pros and cons of both of them are . The advantage of the polyphase decompositions is that the computation can always be performed with the lower clock frequency.2 Efﬁcient realizations of FIR ﬁlters In this section.2 [72]. resulting in either the possibility of reducing supply voltage in order to minimize power dissipation or the use of the pipelining/interleaving (P/I) technique in order to minimize the area [71]. presented in Figs. The maximum number of symmetrical subﬁlters in sampling rate conversion with different ﬁlter tap and samplingrate combinations are listed in Table 4. The decomposed ﬁlter for decimation and one possible implementation of it are F s X(Z) H (Z ) 0 L LF s Y (Z) i H (Z ) 1 L −1 Z H (Z ) L−1 L −(L−1) Z Figure 4. the two main structures of digital FIR ﬁlters. namely the direct form and the transposed direct form. 4. 4.3 Efﬁcient FIR ﬁlter structures 31 L H( Z L) H( Z ) L H( Z M) M M H( Z ) Figure 4. the symmetry of the coefﬁcients can be exploited in order to further reduce the area.4.6. are presented.
2 Maximum number of symmetrical subﬁlters. .32 Resourceefﬁcient digital ﬁlter design F s X(Z) H (Z ) 0 LF s Y (Z) i H (Z ) 1 H (Z ) L−1 Figure 4.6 One possible realization of polyphase decomposed interpolation ﬁlter. Odd L or M Even L or M Odd number of coefﬁcients 1 2 Even number of coefﬁcients 1 0 considered and some methods for reducing the amount of hardware in ﬁlter realizations are also discussed. Table 4.7 Polyphase decomposition of the decimation ﬁlter. Fs X(Z) M Fs M Y (Z) i H (Z ) 0 −1 Z M H (Z ) 1 −(L−1) Z M H (Z ) L−1 Figure 4.
9 Folded regular direct form FIR ﬁlter structure. the coefﬁcients are either symmetrical or antisymmetrical relative to the center coefﬁcient.9. Applications where the .4.1 Direct form structure The folded direct form FIR ﬁlter structure is presented in Fig.8 One possible realization of the polyphase decomposed decimation ﬁlter 4. Folding is only X(n) −1 Z −1 Z −1 Z −1 Z Y(n) Figure 4. i.3.2. 4.3 Efﬁcient FIR ﬁlter structures Fs M Y (Z) i 33 Fs X(Z) H (Z ) 0 H (Z ) 1 H (Z ) L−1 Figure 4. applicable when the FIR ﬁlter has a linear phase.e.
the effect is seen immediately at the ﬁlter output. in programmable ﬁlters). This.10. requires a doubling of the register elements. Basically the amount of X(n) −1 Z −1 Z −1 Z Y(n) −1 Z Figure 4. the redundant arithmetic addition.2. such as carrysave addition. because the signal is divided into carry and sum signals and an additional adder before the output to sum up the carry and sum signals. Another advantage of the transposed direct form is that. may be applied to the adders between the register stages resulting in increased speed. the delay path from the registers to the output can be straightforwardly pipelined if the latency is allowed [72]. if the ﬁlter coefﬁcients are updated (for example. however.3. In the folded regular direct form. subﬁlters in polyphase decompositions and in the predistortion ﬁlters for phase error correction. resulting in faster performance. which may lead to a reduced amount of hardware. 4. 4.10 Folded transposed direct form FIR ﬁlter structure. Also. On the other hand. The beneﬁt of the transposed direct form is that the maximum delay path in this structure is shorter compared to the regular direct form.2 Transposed direct form structure The transposed direct form structure is presented in Fig. the number of bits needed in the delay elements are deﬁned by the number of input bits rather than the required word length of the ﬁlter. hardware is almost the same in direct form and transposed direct form FIR ﬁlters. .34 Resourceefﬁcient digital ﬁlter design coefﬁcients may not be symmetrical are. for example.
parallel data streams are interleaved in time. [75]. but it may be more difﬁcult than in a regular direct form structure. the sum of sign bit extension vector is computed a priori and added to the output of the ﬁlter. The P/I structure of the polyphase interpolation ﬁlter is presented in Fig.3 Efﬁcient FIR ﬁlter structures 35 Transposed direct form ﬁlters can also be pipelined. method is that the additional register stages increase the power consumption. and the computation is made with a K times higher clock frequency. the sign bit extension does not have to be performed inside the ﬁlter.4. Instead of one delay element we have to have K delay elements. at least in the case of pipelining a single adder stage. Finally. . the same hardware for ﬁlter coefﬁcients may be used. 4. This is because the load at the sign bit position may slow down the circuit or it may require a large amount of buffering. In this case. However. the sign bit loading due to the sign bit extension in shift and add operations may become a problem. 4. register stages has to be added to the ﬁlter. When having K parallel data streams to be ﬁltered with the same ﬁlter. The subexpression sharing method can be applied to both of the structures. In this method. because the amount of the registers is the same as in parallel realization. reducing the amount of hardware effectively [73].11 Pipelined/Interleaved polyphase ﬁlter. The main drawback of this F IN Inter− leaver K:1 K*F H 1 (Z ) K K 2*K*F/N De−inter leaver 2:N OUT H 2 (Z ) K pcs N pcs Figure 4.3.[74]. but the clock frequency is higher.11.2.4 Reduction of the sign bit load In the ﬁlters that are realized with the SD coefﬁcients. for example. the same ﬁltering operation is to be performed for several independent data streams.2.3 Pipelining/interleaving technique The pipelining/interleaving (P/I) technique [71] is applicable when. and the extensive loading of the sign bit is avoided. the data stream is deinterleaved either in K or some other amount of parallel data streams. Instead of using K times the same hardware.3. 4. The loading is avoided by the usage of the constant vector addition method proposed in [72].
2. 3 3 (4. only minor hardware savings can be achieved by truncation of the ﬁlter output. and the third is the noise due to the overﬂows. (4. or equal to. The third source of noise is the noise generated by overﬂows in the ﬁlter. the noise variance at the ﬁlter output due to the internal word length quantization is σ2 = Nσ2 .32) in which ∆o = 2−Bo +1 and Bo is the number of bits at the ﬁlter output after quantization. n iwl (4.5 Word length effects and scaling In order to get the best possible trade off between the signaltonoise ratio and ACLR at the output of the digital ﬁlter and the amount of hardware. 12 3 (4. In the case of cascaded ﬁlter stages.3.721ln(N).31) The noise variance added due to the quantization at the ﬁlter output is σ2 = op 2−2Bo ∆2 o = . and B is the internal word length of the ﬁlter. so the absolute value of the number is less than. The ﬁrst source is the quantization of the result of the multiplication. The second is the noise due to the truncation at the ﬁlter output. 1. This means that quantization at the ﬁlter output has less effect on the signaltonoise ratio than shortening the internal word length of the ﬁlter. Assuming an N tap transposed form ﬁlter.30) If we want to keep the noise added by the ﬁltering operation below the desired noise level indicated by Bo output bits. the minimum accuracy needed has to be found. Basically there are three sources of noise due to the ﬁnite precision arithmetic in the FIR ﬁlter. 2ln(2) (4.33) .36 Resourceefﬁcient digital ﬁlter design 4. It is assumed here that the computation is made in a 2’s complement format and that the most signiﬁcant bit (sign bit) has the weight of 20 = 1. The variance of the quantization noise due to the ﬁnite internal word length is σ2 = n ∆2 2−2B = . the internal word length of the ﬁlter should be B ≥ Bo + ln(N) ≈ Bo + 0.29) where ∆ is 2−B+1 . The overﬂows of the ﬁlter may be avoided if the internal word length of the ﬁlter is selected so that the maximum presentable number in the ﬁlter is N−1 Mout put = Minput n=0 ∑ h(n) .
This leads to clipping instead of overﬂows. Other methods for discovering the dynamic range of the signal are presented in [76].3 Efﬁcient FIR ﬁlter structures 37 where Minput is the maximum value at the ﬁlter input [76]. The noise due to the overﬂows may be minimized by using saturating logic in the adders [78]. the number of internal bits needed can also be approximated with simulations. while the saturation logic may be applied in order to minimize the effect of occasional overﬂows.[77] and [78].4. which reduces remarkably the generated noise. . but they do not guarantee an overﬂowfree performance. Because the maximum output value is dependent on the statistics of the signal. However this usually gives overpessimistic values for the bandlimited signals.
.
5.1 Direct digital frequency synthesizers using the lookup table method. it is possible to realize every function y = f (x) of variable x by mapping the value x to the output y with some mapping element. [35]. especially with high resolutions. [79]. the carrier is formed by addressing the memory with the phase value and mapping the current phase to the value of the sinusoidal signal. The most straightforward approach for digital modulation is the LUTbased method used in. Then the generated carrier is multiplied with the modulating data by using digital multipliers. When this is applied to the .Chapter 5 Methods for direct digital frequency synthesis and modulation The core of the digital QAM modulator is the direct digital synthesizer (DDS). usually a memory block. These methods are described in the following sections. In this method. The most often used methods for the direct digital frequency synthesis are the lookup table (LUT) based frequency synthesis methods and the methods based on the CORDIC vector rotation algorithm. Advantages of this method are the good frequency resolution and relative simplicity. for example. The accuracy of the mapping depends on the resolution of the input value x and the area (=accuracy) of the mapping element. With a lookup table method.[80]. Drawbacks are that the multipliers and memories may require a large area. and memories may become the speed bottleneck at high sampling rates.
which maps the phase value to the desired amplitude value. [80]. ∆φ is the phase increment. and subtractive techniques [87]. for example [82]. The increase of this area may slow down the operation of the memory block and limit the achievable frequency band.1. segmentation techniques [86]. The principle of the LUTbased frequency synthesis is presented in Fig. so only the ﬁrst quadrant should be coded into the memory. The values in other three quadrants are obtained by controlling the sign of the phase and magnitude (Fig. The accuracy of the synthesis is controlled by the values of p. additional symmetry 2nd MSB Phase increment Phase accu Comp− lementor Sine ROM MSB Comp− lementor 2nd MSB MSB Figure 5. [88]. The phase accumulator can be made almost arbitrarily fast with pipelining techniques.2). The phase value obtained by integration is then used as the address to the ROM memory. The compression techniques can be roughly divided into three categories. the variable to be mapped is usually the phase of the sinusoid and is mapped to the corresponding amplitude value [81].40 Methods for direct digital frequency synthesis and modulation frequency synthesis.1) [79].1 LUTbased DDS integrated over time with a digital integrator also called a phase accumulator. [85]. . In quadrature synthesizers. k and a (Fig. 5. namely the symmetry reduction techniques [83]. The increase of the values a and k results the increase of the area of the ROM memory. which is ∆φ p −1 z p k Cosine ROM a cos(ω t ) Figure 5. 5. The enhancement of the performance of the synthesizer is usually achieved by increasing the values of k and a. 5. several techniques of memory size reduction have been developed. The symmetry reduction techniques are based on the fact that the shape of the sinusoid is the same in each quadrant.2 Symmetry reduction technique. [84]. Therefore. The value p affects mostly the frequency resolution of the synthesizer that is not the speed bottleneck.
1 Direct digital frequency synthesizers using the lookup table method. symmetry and subtractive reductions are usually also applied.2) may be approximated with sin (φ (n)) ≈ sin π π π (A (n) + B (n)) + cos (A (n) + B (n) ) sin C (n) . The effectiveness of the compression method is a tradeoff between the memory size and complexity of the additional hardware re . Eq. is to subtract the phase out of the sine and add it to the output of the memory [87]. interpolating [93]. [86]. and C(n) are subbuses of the phase value bus φ (n). but also more complex functions such as double trigonometric [88]. and interpolating with nonlinear addressing [95]. 41 reductions may be achieved by taking into account that [85] cos (φ) = sin π −φ . If C (n) is chosen to be small (i. (5. The simplest subtractive method. A wide variety of segmentation techniques have been presented during the past few years using trigonometric identities [83]. 2 0≤φ≤ π . With segmentation techniques. [94].3 Memory compression by trigonometric approximation.5. 2 (5.2) where A(n). the number of output bits of memory is reduced by subtracting some simple function out of the sine function and by saving only the difference into the memory. slope optimized linear function [89]. the large memory is divided into smaller units by exploiting the trigonometric identities. With these methods. A(n)+B(n) Phase increment Phase accu φ(n) A(n)+C(n) Coarse ROM Fine ROM Figure 5. called sinephase difference algorithm.1) In the subtractive reductions.3) 2 2 2 where B(n) is the mean value of B(n). 5. few least 2 signiﬁcant bits. B(n).3). 2 2 (5. Now the ﬁrst term of Eq. (5. for example sin (φ (n)) = sin π (A (n) + B (n) +C (n)) 2 π π (A (n) + B (n)) cos C (n) = sin 2 2 π π + cos (A (n) + B (n)) sin C (n) . LSBs). (5.3) can be stored in a coarse ROM and the second term in a ﬁne ROM (Fig.e. For symmetry reasons φ (n) is limited to be 0 ≤ φ (n) ≤ π . quadratic [90] and quadline approximation [91] have been used. [92].
but the modulation can be performed without any multipliers as in [103]. [96]. [112]. A comparison of memory compression ratios obtained with various compression methods is presented in [95]. Discretetime QAM modulation may be presented as a matrix multiplication as Mr = = i (n) cos (φ (n)) + q (n) sin (φ (n)) −i (n) sin (φ (n)) + q (n) cos (φ (n)) cos (φ (n)) sin (φ (n)) − sin (φ (n)) cos (φ (n)) i (n) . A comparison of the respective areas required for implementation of various DDS circuits is presented in Table 5. CORDIC type algorithms are suitable for calculating trigonometric functions [98]. subtraction reduction. symmetry reduction. the algorithm provides as good a frequency resolution as the LUTbased method. hyperbolic trigonometric functions [101].[99]. logarithmic and exponent functions [102].4) where φ (n) = ωnTs .2 CORDIC vector rotation algorithm based frequency synthesizer and modulator CORDIC is an abbreviation for the coordinate rotation digital computer. In hybrid realizations of the CORDIC algorithm [111]. [103]. [110].[6]. (5.1 in Section 5. Eq. [104]. the comparison of the memory compression ratios does not tell the whole truth. [109]. however. and segmentation [87]. digital ﬁlters and matrix based DSP algorithms [105] and inverse trigonometric functions [107].4) gives the desired modulation result as the ﬁrst element of the resulting column . [109] [110]. sine wave generation [103]. The CORDIC based modulation can be presented as follows. which was introduced by J.3 It is preferable to use the combination of the different compression methods. a combination of LUT and the CORDIC rotator is used in order to further reduce the area of the synthesizer. linear transformations [105]. When applied to frequency synthesis and modulation. [100]. 5. q (n) (5. Volder in 1959 [98].42 Methods for direct digital frequency synthesis and modulation quired to form the actual sinusoidal output. for example.[106]. Ts is the sampling interval and ω is the desired angular frequency. The speed of the synthesizer can be increased with. The CORDIC algorithm is also suitable for digital modulator/demodulator applications [108]. the parallel structures [97]. since the highest compression ratios may be achieved with the methods that require an extensive amount of additional hardware. for example.
4) can be achieved by the chain of Mr ≃ Mra = k=0 ∏ cos (φk ) −σk (n) sin (φk ) σk (n) sin (φk ) cos (φk ) i (n) q (n) .7) ∑ φk + φN−1 ≥ φ (n) . (5. (5. 1} and it is determined by Z0 (n) = φ (n) σk (n) = sign (Zk (n)) Zk+1 (n) = Zk (n) − σk (n) φk .5) it may be stated that the rotation φ (n) in Eq. the angle φ (n) should be bounded and presentable by the sum of φk ’s N−1 k=0 (5. Eq. (5.6) has two terms of convergence [98]. This results in Mra = cos (φ0 ) −σ0 (n) sin (φ0 ) σ0 (n) sin (φ0 ) cos (φ0 ) × . (5. First. N−1 i=k+1 φk ≤ φN−1 + ∑ φi (5. (5. the residual rotation angle should converge to zero lim Zk (n) = 0.8) Second.7) is the residual angle to be rotated after kth stage. −π ≤ φ (n) ≤ π.9) k→∞ which is always satisﬁed when Zk+1 (n) ≤ φk . By notifying that cos (φ1 ± φ2 ) sin (φ1 ± φ2 ) − sin (φ1 ± φ2 ) cos (φ1 ± φ2 ) = cos (φ2 ) ± sin (φ2 ) × ∓ sin (φ2 ) cos (φ2 ) cos (φ1 ) sin (φ2 ) − sin (φ1 ) cos (φ1 ) multiplications N−1 .2 CORDIC vector rotation algorithm based frequency synthesizer and modulator 43 vector. To operate properly. (5. Zk+1 in Eq.6) can be simpliﬁed by taking cos (φk ) as a common subexpression. (5. (5.6) where σk (n) = {−1.5.10) Furthermore Eq.
approaching 2 1. The value of K is only dependent on the number of stages. The inputoutput relation of the stages are Xk+1 (n) = Xk (n) + sign (Zk (n))Yk (n) 2−k+1 Zk+1 (n) = Zk (n) − sign (Zk (n)) φk for kth stage and X1 (n) = sign (Z0 (n))Y0 (n) = sign (φ (n)) q (n) Y1 (n) = −sign (Z0 (n)) X0 (n) Yk+1 (n) = −sign (Zk (n)) Xk (n) 2−k+1 +Yk (n) (5.44 N−1 k=1 Methods for direct digital frequency synthesis and modulation ∏ cos (φk ) 1 σk (n) tan(φk ) −σk (n) tan (φk ) 1 φk = arctan 2−k+1 i (n) . q (n) (5.13) where K= k=1 ∏ cos (φk ) .6468 with large N. the effect of K can be discarded resulting in the modulation equation Mb = 0 σ0 (n) × −σ0 (n) 0 N−1 k=1 ∏ 1 σk (n) 2−k+1 −σk (n) 2−k+1 1 i (n) . (5. which may be realized by using only adders/subtracters and negators in the zero stage. (5.12) π 2 and φ0 = to satisfy the Eq. If the constant scaling factor of the modulated signal is allowed.16) . (5. (5.15) can be computed with the series of N CORDIC rotation blocks. when 0 ≤ φk < π . we may write the Eq.11) in a form Mra = K N−1 k=1 0 σ0 (n) × −σ0 (n) 0 1 −σk (n)2−k+1 N−1 ∏ σk (n)2−k+1 1 i (n) q (n) .8).14) The values of φk and K can be computed beforehand because the number of stages N is known and because the sign of cos(φk ) = cos(−φk ) is always positive.15) Eq.11) By selecting (5. (5. q (n) (5.
3 Survey of digital frequency synthesizers 45 Z1 (n) = Z0 (n) − sign (Z0 (n)) φ0 π = φ (n) − sign (φ (n)) 2 = −sign (φ (n)) i (n) (5.3 Survey of digital frequency synthesizers Area. effective savings of hardware may be achieved. with a hybrid realization based on the combination of LUT and CORDIC vector rotation algorithm. 5. no digital multipliers are needed for the modulation of the carrier. The effects of N. One possible architecture for the CORDIC rotator is presented in Fig. Also no memories are required. [114] and [115]. It takes k=0 i(n) Xk Y k 0 s 0 s Add/ sub Add/ sub X k+1 a Xk Y k s Z k+1 p Zk φk k=1 s Add/ sub Add/ sub X k+1 Xk Y k s Z k+1 Zk φk k=N−1 s Add/ sub Add/ sub X k+1 i(n) cos ( φ(n) ) + q(n)sin ( φ(n) ) q(n) Y k+1 a Y k+1 Y k+1 q(n) cos ( φ(n) ) − i(n) sin ( φ(n) ) ∆φ Phase φ(n) accu Zk φk Add/ sub Add/ sub Add/ sub Z k+1 s=shift by 2 −k+1 s=shift by 2 −k+1 Figure 5. If only the frequency synthesis is performed. usually in the two’s complement format. at least three multipliers are required in addition to the reported hardware in order to enable quadrature modulation.4. It can be noticed that. It should be noted that if the ”Mixer” feature column in Table 5. 5.1.1 contains ”No”. The frequency resolution is selected by the number of bits in the phase accumulator. speed and resolution of various LUT. With the CORDIC rotator. thus enabling pipelining.4 CORDIC vector modulator.and CORDICbased frequency synthesizer implementations are presented in Table 5. The CORDIC may also be used as a frequency synthesizer if q (n) and i (n) are constants.5. Very efﬁcient hybrid mixers have also been presented [109]. It should be noted that the values of φk are presented with the same notation as φ (n).4) on the phase computation path. 5. as is with the LUTbased digital frequency synthesizer. φ (n) can be generated with the same kind of phase accumulator as is presented in Fig. 5.4) are analyzed in [113]. number of bits p (Fig. and the number of bits a on the X/Y path. The accuracy of the modulation performed with the CORDIC rotator is dependent on the number of stages N. the data values i (n) and q (n) as the input and the modulated carrier is X output of the last stage. there is no or little advantage of the multiplierfree realization and the LUTbased or LUT/CORDIC hybrid may result in a smaller area.17) for the zero stage. [110]. 5. a and p (Fig. .1.
72 0.5 150 30 100 320 100 30 80.079 No 0.25µm CMOS 0. IQ Core area.4 800 540 100 310 100 300 600 150 330 Area Mixer Comments [mm2 ] 48.35µm CMOS 0.5µm CMOS 1. no DAC.35µm CMOS 1. hybr. freq.282 No 0. IQ Core area. P=14 A=12 P=15 A=12 P=12 A=9 P=18 A=14 P=16 A=12 P=16 A=12 P=16 A=16 P=14 A=12 P=11 A=9 P=12 A=10 P=22 A=16 P=20 A=16 P=19 A=16 P=19 A=13 P=19 A=13 P=18 A=16 P=18 A=15 Sampl. (A)mpl. Table 5. segm.35µm CMOS 0. LUT interp. LUT seqm. IQ Core area. IQ 24. no DAC.25µm CMOS 0. LUT interp. COR.31 1.35µm CMOS 0. no DAC. IQ Core area. no DAC.35µm CMOS 0.110 No 0. LUT COR.0µm bipolar 1.96 Yes 12. no DAC. hybr. no DAC.1 No External DAC 8b DAC Core area. LUT segm. IQ Core area. no DAC.3 No No No 24. LUT interp.51 No No Yes Yes No Yes .46 0. hybr. no DAC. COR. LUT interp. no DAC. no DAC.1 Comparison of DDS implementations. 9b DAC No DAC.35µm CMOS 0.72 1. COR. IQ Core area.23 0. LUT polynom. IQ Core area.35µm CMOS 0. resol. hybr. no DAC.36 0.25µm CMOS (P)hase.9 No 0. COR. no DAC. COR. IQ Core area.55 No 0. IQ Core area. COR. IQ Core area.8µm CMOS 0. [MHz] 7.00 No 3. hybr.4 0. IQ Core area. COR. hybr.35µm CMOS 0.35µm CMOS 0. IQ Core area. hybr.46 Methods for direct digital frequency synthesis and modulation Areaspeedresolution tradeoff between LUT and CORDIC realizations is analyzed in detail in [112]. Method Type Process Sunderland [83] Nicholas [86] Bellaouar [93] Langlois1 [94] Langlois2 [94] Langlois3 [94] Curtic˘ pean a [92] De Caro [116] Yang [91] Gielis [103] Madisetti [117] Janiszewski [112] Curtic˘ pean a [118] Torosyan1 [109] Torosyan2 [109] Song1 [119] Song2 [110] segm. no DAC Core area.0µm CMOS 0.25µm CMOS 0. 3.
4 Other digital modulation methods 47 5. the amplitude modulation has to be performed in the analog domain. the advantage of DSP in modulation is lost.5. A shortcoming of the method is the ﬁxed carrier frequency.4. the implementation of a goodquality nonlinear D/A converter is not trivial. In this case.[37] [120]. Also. the method is called multistage modulation and is described in. multipliers are not needed with this method [36]. 0. The only hardware required for this modulation is a negator and a multiplexer. If the sequence [+1. This method can be expanded in order to generate carrier frequencies other than the quarter of a single sampling frequency.4 Other digital modulation methods 5. . −1. In this method. 5. The sign control can also be included in. 0].1 Modulation to quarter of the sampling rate Similarly to CORDIC modulation. the phasetosinusoid mapping is achieved by a nonlinear D/A converter. coefﬁcients of a digital ﬁlter [37]. for example.2 Frequency synthesis with nonlinear D/A converter A memoryfree method for frequency synthesis is presented in [122]. the data is upconverted to half of the sampling frequency. for example. While the usage of memories is avoided. [121].4. The upconversion is made to a quarter of the system clock frequency by multiplying the data values repeatedly by sequence [1. −1] is used.
.
Section 6. some general issues considering the currentsteering D/A converters and their performance metrics are discussed in Sections 6. In addition. This is due to following properties of currentsteering architecture. only transistors are used to provide the output current. As an introduction to the subject.1 and 6. and the yield model developed and published by the author [13] is presented.2.4 discusses the previously published calibration methods that are used to improve the static linearity of the converters above 12 bits. With this it is possible to provide relatively large currents (10 to 20mA) to 50Ω load without buffering. The previously published linearity yield models are compared with simulations. the static linearity as a function of transistor mismatch is analyzed.3. Also the digital calibration method developed and published by . as in resistorstring and switchedcapacitor D/A converters. which makes the currentsteering D/A converter the most suitable architecture for. The operation speed of a currentsteering converter is determined by the ability to drive the gates of the switches. this enables the usage of the standard CMOS process. In Section 6. digital IF transmitters and direct digital synthesizers.Chapter 6 Currentsteering digitaltoanalog converter design Currentsteering digitaltoanalog converters have become the mainstream architecture of D/A converters since the late 80’s. instead of the gain bandwidth product (GBW) of the buffer circuitry. This chapter describes the theory of currentsteering D/A converters applied in the design of the prototype circuits presented in Chapter 7. Sample rates of several hundreds of millions of samples per second can therefore be achieved. for example. whereas highaccuracy resistors and capacitors are required in resistorstring or switchedcapacitor converters.
1 Block diagram of a typical currentsteering D/A converter. resulting . The effect of the jitter on the spectral performance is analyzed by simulations. These circuit blocks together form a complex mixedmode circuit entity. The jitter analysis is also partially published by the author in [15].5 considers the effects due to the output impedance variation. Gates of the switches are driven by control signals decoded from input data with digital circuitry. Clock buffers and some analog bias circuitry are also required. In an Nbit converter. In Section 6.7. Section 6. while distortion sources such as transition asymmetry are analyzed.2 are described. 6.6.1 A currentsteering D/A converter consists of current sources and cascode transistors that are often used to increase the impedance of the current source. The previously published methods are discussed.50 Currentsteering digitaltoanalog converter design Vdd Vdd Load ODigital Data Switch drivers Switches O+ Clock Vdd Bias Cascode transistors Bias I 2I Binary weighted current sources 2B1I 2BI 2BI 2BI Thermometer coded current sources Figure 6.8 is about the layout techniques used to reduce the effect of the process gradients on the current source mismatch.6. the timing nonlinearities are added to the model presented in Section 6.1 General description of the current steering D/A converter A block diagram of a typical currentsteering D/A converter is presented in Fig. 6. Section 6. the signal conversion from discrete time digital to continuous time analog is discussed and mathematically modeled. Switches are used to combine the current of the current sources and form an output signal. and methods used in the prototype circuit presented in Section 7. and the performance degradation due to codedependent clock load and power supply interference is demonstrated. the author and his team [14] is presented. of which one is zero. there are 2 N input codes. In Section 6.
due to the increased area required for the switch drivers and the decoder logic. since segmented architecture is often used. i. (i. each current source has the same weight). 6. The usage of binary weighted current sources reduces the number of switches. It is more like a source of interference. The digital circuitry usually consists of at least a thermometer decoder. It is therefore preferable to use as many as possible thermometercoded bits at the MSB end in order to produce good synchronization of the most signiﬁcant bit transitions. thermometer coded. MSB transition 01111− > 1000 in a binaryweighted D/A converter may cause a glitch. requires also some kind of digital circuitry. Current sources can be weighted (usually binary weighted). is also mostly performed in the digital domain. whose propagation to any of the other domains should be eliminated. or. The digital domain is less sensitive to noise and interference.6. but introduces difﬁculties in switchdriver synchronization.1 General description of the current steering D/A converter 51 Data DIGITAL −Thermometer coders −Calibration −Control logic −Dynamic equalizing MIXED−MODE −Synchronization flip−flops −Switch control logic −Switch drivers ANALOG −Current sources −Cascode transistors −Bias circuitry −Switches Io+ Io− Clock CLOCK −Clock amplifier −Clock buffers −Clock distribution network Figure 6. since the transition of the MSB bit is slower than the three LSB bits. Switching activity equalization. The practical limit for thermometercoded bits is around 7.2 Domains of the D/A converter.e. thus providing a larger capacitive load.e. since larger currents require larger switches. A currentsteering D/A converter can be divided into four types of circuitry domains each of them having a unique contribution to the performance of the converter. in a total current requirement of 2 N − 1 times the current corresponding to the LSB (Ilsb ). which is usually the case. The domains of the D/A converter are presented in Fig. The digital domain of a D/A converter includes all of the pure digital circuitry of the converter. In the mixedmode domain. Calibration. minimized. and use binary weighting for the LSB part. combination of binary weighted and thermometer coded). The timing differences in switch control signals result in glitches.2.e. at least. For example. the control signals for the switches of the converter are formed and the switch control signals are synchronized with ﬂipﬂops. which is used to decorrelate the switching activity from the input code. which is often needed for accuracies of 12bit or more. or segmented (i. spikes in the output current. The synchronization ﬂipﬂops/latches usually convert the digital data signal from a singleended .
The higher the sampling frequency. the clock net. . The transition activity in the digital domain is related to the input data. whose coupling to the mixedmode domain can result in codedependent timing jitter. however. the unit currents are generated and combined in order to form the analog output signal. the more severe the effect of the jitter on the performance of the converter. In addition. The analog domain is sensitive to interference. Interference can. The sensitivity of the clock domain is related to sampling. they are digital like signals switching from railtorail. and thus the clock domain. but. Interference in the clock domain will cause jitter. the interference in the clock domain will be reﬂected in the performance of the whole converter. such as shielding with ground planes. thus generating input data dependent interference.52 Currentsteering digitaltoanalog converter design digital bit to an fully differential analog signal. the sensitivity in the analog domain is continuous. even though the switch control signals in the mixedmode domain are sensitive to interference. couple to every possible node in the analog domain. Unfortunately. Effects are more severe on one node than on another. has to be distributed around the converter because it is connected to both digital and mixedmode domains. All nodes in the analog domain (except the output nodes and gates of the switch transistors) are biased to a certain operating point. It is also sensitive to the coupling of the analog output to the clock signal. which can then be transformed to an actual control signal with some simple logic circuitry and buffering. Therefore it is subjected to interference originated in both of these domains. and thus harmonic distortion at the converter output. Unfortunately this kind of stability is unachievable. and therefore generate interference that can couple to the analog domain. coupling to the analog domain cannot be totally prevented. The power supplies of the mixedmode domain are usually separated from the digital domain in order to avoid coupling and interference after synchronization. Because the clock takes care of all synchronization in the converter. but because the clock domain is not directly connected to the analog domain. whereas the sensitivity in the mixedmode domain is mainly related to the jitter of the sampling instance. and will. and they should remain stable even when switching occurs. In the analog domain. Usually one or multiple cascode transistors are used to increase the output impedances of the current sources in order to reduce the distortion generated by the code dependent output impedance variation. and they can be reduced by various means. this kind of coupling can be more easily avoided.
The INL of a D/A converter is deﬁned as the difference between the analog output value and the straight line drawn between output values corresponding to the smallest and the largest input code. If the average LSB step is smaller or larger than was originally intended. it is more important than that with input code “8”. the output is twice as large as with input code “4” regardless of the actual output values corresponding to “4” and “8”. the gain error is an important parameter.2. Gain calibration between converters is therefore usually needed in that kind of application. the input code “7” causes 7Ilsb current to ﬂow to the output load. there is gain error (Fig. They are nonlinearities mainly caused by a mismatch of the current source transistors and limited output impedance of the current branch. More severe nonidealities are the Differential Nonlinearity (DNL) and Integral Nonlinearity (INL). 6.e. the gain error is usually not a problem. such as I/Q transmitters. Within a single converter.3 Gain error of the D/A converter.2 Performance metrics 53 Ideal Actual Output value Input code Figure 6.1 Static linearity: Gain error. where two converters have to have equal gain. DNL and INL In the ideal case. divided .2 Performance metrics 6. which would distort the output signal. However. 6. i.6. since the imbalance between I and Q signal branches results in reduced sideband rejection in I/Q mixers and interchannel interference in reception. in some applications. The gain error is usually not a problem. i.e. the output current of the converter is linearly dependent on the input code. since the relative accuracy of the conversion is much more important than the absolute accuracy. since the error does not introduce nonlinearity.3).
because DNL and INL are obtained by referring the actual output to the linear output obtained by using the average LSB step. the converter is no longer monotonic. It should be noted that. DNL is deﬁned as the variation of the step size relative to average LSB step. If the value of DNL is less than 1. i. A converter is considered to have N bit accuracy if DNL does not exceed ±0. Fully thermometercoded converters are always monotonic.54 Currentsteering digitaltoanalog converter design Ideal Actual Output value Average LSB step DNL INL Input code Figure 6. INL is a curve that tells us how much the actual output corresponding to input code k differs from linear (not ideal) output. DNL tells us how much the step at code transition from k to k + 1 actually differs from the average step size. Monotonicity can only be lost with binary weighted converters. More important is the shape of INL curve. the output value decreases as the input code increases. the former deﬁnition is used. INL is sometimes also deﬁned as the difference of the analog output and bestﬁt straight line throughout the output values [123]. DNL and INL are important performance metrics in the sense that they deﬁne the limits of the linearity of the converter. The role of DNL .4.e. because it includes all information about the lowfrequency nonlinearity of the converter. by the average LSB step.5LSB. but these ﬁgures will not tell us much about a single converter. 6.4 Differential Nonlinearity and Integral Nonlinearity. In this book. INL is often reported as a single ﬁgure (maximum INL = x) or as a range (INL = ±x). Deﬁnitions of DNL and INL presented in Fig. Linearity is further degraded by dynamic nonidealities as the signal frequency and sampling rate are increased. i. The information included in DNL can be further analyzed as follows. INL values corresponding to the smallest and the largest input codes are always zero. the output value is within the bounds of quantization error.e.
on the other.1) in which ∆ is the size of the quantization step. The ﬁgure of merit that tells us the level of highest spurious tone relative to the signal power is the spurious free dynamic range (SFDR). SINAD and ENOB In addition to DNL and INL.4) In current steering D/A converters.2. relative to signal power.02N + 1. These spurs are most often due to harmonic distortion. ENOB can be deﬁned as ENOB = SINAD − 1. The upper limit of the SNR is deﬁned by quantization noise. which is given in decibels relative to (given) signal power. such as thermal noise and 1/fnoise. THD. i.02 (6. of the converter.6. The signaltonoise and distortion ratio SINAD is the sum of noise and distortion power relative to signal power. 12 (6. T HD is also usually given in decibels. When Nyquistrate converters are considered. and therefore the static linearity of the converter is quite meaningless.76.3) 2A . with modern Nyquistrate converters with sample rates from 100MHz to 1GHz. they deﬁne the quality of the low frequency operation. (6. various ﬁgures of merit are commonly used to indicate the quality of a D/A converter. 2N (6.2) SNR will be further degraded by other noise sources. σ2 = n ∆2 . A signaltonoise ratio (SNR) is the ratio of the signal power (usually the power of a sinusoidal signal) and the noise power integrated over certain signal band in decibels. Total harmonic distortion (T HD) is the sum of the power of the all harmonic distortion components. the dynamic nonlinearities are clearly limiting the performance. it is possible to calculate the effective number of bits (ENOB) of the converter. Assuming the SINAD is determined. but they can also occur for some other reason. SNR is usually deﬁned for the signal band from 0 to half of the sample rate. the ﬁgures of merit that are generally announced . Presenting the sinusoidal signal with an amplitude A with Nbits results in ∆= and SNR of SNR = 6. such as coupling.76 . 6.2 Performance metrics 55 and INL of the converters as a performance metric is twofold.2 Linearity and noise: SNR.e nonlinearity. 6. Very often interference spurs exist in the output spectrum of the converter. SFDR. With SINAD. On the one hand.
Because the settling is a ﬁltering operation for the output signal.5 Settling and glitches. Glitches can be problematic when they are generated by the timing differences in synchronization. very often the SFDR (and therefore also the SINAD) of the device is so low that the ENOB of the device is quite far from the value deﬁned by INL or DNL. a typical timedomain waveform of a current steering D/A converter is presented. depending on the load of the converter. However. the settling is lowpass type RCsettling. As long as the glitch is linearly dependent . Glitches can be generated in various ways. and often they are referred as a form of signal degradation. e. are DNL. namely settling and glitches. There are two major timedomain properties that are often referred to. 6. Also unequal rise and fall times in binary weighted converters may generate glitches even with differential output. the settling takes place as damped oscillations. “Glitch” is a spike on the output signal. With RCloads. It is essential to understand what the phenomena behind the glitch is. There are several types of settling. indicating ﬁltering of the higherfrequency components.56 Currentsteering digitaltoanalog converter design Settling RC−settling Glitch Figure 6.2.5 LSB range of the “ideal value”. With RLC type of loads. INL and SFDR since they give a comparable ﬁgure for the linearity of the device. no serious harm results from it as long as the ﬁltering does not affect the desired signal band (from 0 to half of the sampling frequency in general). whereas in thermometer coded converters the asymmetry in transitions is usually canceled by differentiality. within a 0. because most of the glitches or spikes at the output do not introduce any kind of nonlinearity to the signal.3 Time domain performance: Settling and glitches In Fig. Settling is the time required by the output signal to settle to its current value after transition with certain accuracy. 6.g.5.
6. as later demonstrated in Section 6. (6.e. The magnitudes of INL and DNL are dependent on the mismatch of the drain currents of the current sources and the structure of the D/A converter. The mismatch of the drain currents is due to global and local variations during the manufacturing process of a silicon chip. it is dependent on the number of current sources switched when moving from one input code to another. It can be seen that the maximum value of DNL is strongly dependent on the structure of the D/A converter.1 Current source mismatch and yield DNL and INL are generated by the mismatch of the drain currents of the current source transistors.9 the standard deviations of DNL values of the thermometer .6. It is demonstrated how the segmentation of current sources affects the statistical behavior of INL and DNL.7) D/A converter. W is the channel width and L is the channel length. VT is the threshold voltage of the transistor. Svt .3. and Sβ are process related constants. Obviously. segmentation has an effect on DNL. respectively. The regression model presented is published by the author in [13]. having the same dimensions. 6.5) where Avt . i. These models are applicable in cases of 10 to 16 bits with 1 to 6 and 1 to 3 thermometer coded MSB bits for INL and DNL. can be expressed as [124] [125] σ2 σ2 4σ2 β vt Id + 2 = 2 Id (Vgs −VT )2 β = 4A2 vt W L (Vgs −VT )2 + 2 4Svt D2 (Vgs −VT )2 + A2 β WL 2 + Sβ D2 . orientation and operation point.3 Models and relations of transistor mismatch and static linearity 57 on the signal or its discrete time derivative. 6. Various yield models published during the past decade are analyzed and compared by simulations.6. the analysis of the statistical behavior of INL yield as a function of the current source mismatch is presented. it only carries part of the signal energy. 6. regression models for DNL and INL yields are presented. 6. Aβ . or indicates that some signal energy is missing. Vgs is the gatesource voltage of the transistor. 6. In addition.8 and Fig.3 Models and relations of transistor mismatch and static linearity In this section. In Fig.6) and binaryweighted (Fig. The relative variance of the difference between the two transistors. The following ﬁgures represent DNLs of a 14bit thermometercoded (Fig.
Figure 6. .6 20 DNLs of the thermometer coded D/A converter.7 20 DNLs of the binary weighted D/A converter.58 Currentsteering digitaltoanalog converter design Figure 6.
equations for the variances and covariances of INL as function of the input code are derived for the thermometercoded and binaryweighted D/A converter. 6. The singleended output current of the thermometer coded D/A converter that cor .25 1.3 1.2 1. 6. The same kind of simulations were carried out for the INL of the thermometercoded and binaryweighted D/A converters.45 −3 Standard deviation of DNL 1. 6.3 Models and relations of transistor mismatch and static linearity 59 x 10 1.4 STD deviation of DNL [LSB] 1. (6.35 1.6.11 The dependency of INL on the converter structure is analyzed in the following sections.10 and Fig.3. where B is the maximum number of unit current sources switched in the single code transition and σlsb is the relative standard deviation of the error current of a unit current source.8 Standard deviation of 500 DNLs of the thermometer coded D/A converter. It can be observed. that the variance of the maximum value of DNL is 2 σ2 DNLmax = Bσlsb . INL curves for these converters are presented in Fig. coded and binary weighted D/A converters are presented.6) [126].15 0 2000 4000 6000 8000 10000 Input code 12000 14000 16000 Figure 6.2 Statistical model of the static linearity In order to analyze the static behavior of INL.
1 0.60 Currentsteering digitaltoanalog converter design Standard deviation of DNL 0.10 20 INLs of the thermometer coded D/A converter.08 0. Figure 6.06 0.02 0 0 2000 4000 6000 8000 10000 Input code 12000 14000 16000 Figure 6.16 0.12 0.14 STD deviation of DNL [LSB] 0.9 Standard deviation of 500 DNLs of the binary weighted D/A converter. .04 0.
3 Models and relations of transistor mismatch and static linearity 61 Figure 6.8) where the summation term corresponds to the gain error of the converter. where N is the number of bits resulting in 2N−1 Ilsba = Ilsb + i=1 ∑ 2N εi . −1 (6.11 20 INLs of the binary weighted D/A converter. only the singleended case is examined here for simplicity. Because the I shape of the envelope of the INL is the same for both the singleended and differential case. i=0 i=0 k k Iout (0) = 0. The actual LSB step can be found by ﬁtting the straight line between the end points of the curve obtained by sweeping the value of k from 0 to 2N − 1. ε0 = 0 (6. responds to the offset binary type input code k can be written as Iout (k) = ∑ Ilsb + ∑ εi .6. Now it is . εi is assumed to have a normal distribution with zero mean and variance σ2lsb .7) where Ilsb is the ideal LSB current and εi is the error current of ith current source.
From Eq. and result in Ct = E INLt × INLtT topmost element and 2N − k zeros.11).9) is approximately Ilsb .9) can be approximated as INLt (k) ≈ ∑ εri − k i=1 k 2N −1 i=1 ∑ 2N εri . (6. (6. Eq.62 Currentsteering digitaltoanalog converter design possible to deﬁne INL relative to Ilsba as the function of k as INLt (k) = Iout − kIlsba Ilsba εi εi 2 −1 Ilsb ∑k Ilsb − k ∑i=1 I 2N −1 i=1 ) lsb ( N = 2 −1 i Ilsb 1 + ∑i=1 2Nε−1 N . the variance of the INL at the code value k is obtained. 2N − 1 2 −1 (6. (6. It is a unity matrix. The subscript t in It (k) stands for the thermometer coded D/A converter. lsb where σ2 = VAR [εri ] is the relative error variance of the unit current source. −1 (6. and Et is 2N − 1 × 1 vector containing the relative error values. σ2 t (k) = k − INL k2 σ2 lsb 2N − 1 (6. By setting k1 = k2 = k. The INL of the converter can also be presented with the matrix notation INLt = K T E − T K T Ivt Ivt E Ivt I T = K T (It − N vt )E = K T At Et . k2 ) − k1 k2 σ2 lsb 2N − 1 (6. Ivt is 2N − 1 × 1 unity vector.11) where K is a 2N − 1 × 2N matrix with each column containing k 1’s starting from the covariance matrix of INL values at code values k1 and k2 can be calculated.10) where εri = εi Ilsb is error of the ith current source relative to LSB current Ilsb . the = E K T At Et EtT AtT K (6. k2 ) = MIN (k1 . The lsb elements of Ct are ct (k1.12) = K T At AtT K σ2 .9) If it is assumed that the denominator of the right side of Eq.14) . (6.13) and they represent the covariances between INLt (k1 ) and INLt (k2 ).
where S= (6.. Wds = Diag(Ws ).. (6.18) Ws = . and Eb is an N × 1 error vector of normally distributed random variables with zero mean and variance σ2 . i = [0. (6. k2) = = COV [INLt k1 . and Es is 2N−B + B − 1 × 1 error vector of normally distributed random variables with zero mean and variance σ2 . Ib − N 2 −1 (6. The INL of the binaryweighted converter can be written as INLb ≈ BT Wdb E − = BT T BT Wb IvbWdb E N −1 2 T Wb Ivb Wdb E = BT Ab Eb . Wdb = Diag(Wb ).17) Ks Bs 2B × Ivt Wb . Wb is an N × 1 weighting vector with elements wi = 2N−1−i .15) In a similar manner. the covariance matrix for the binary weighted and segmented D/A converter can be computed. The correlation coefﬁcient between the two INL values is ρt (k1. (6. lsb .3 Models and relations of transistor mismatch and static linearity 63 which are the values on the diagonal of Ct .6. lsb By combining the INL matrix equations of the binaryweighted and thermometer coded converters.16) where B is an N × 2N matrix with each column containing the binary presentation of k. the INL equation for the segmented converter is obtained as INLs ≈ ST Wds Es − = ST T ST Ws IvsWds Es N −1 2 T Ws Ivs Is − N Wds Es 2 −1 = ST As Es . INLt k2 )] σIk1 σIk2 1 k2 MIN (k1 .19) Ks is a matrix with columns containing 2N−B − 1 thermometer coded MSB bits and Bs with columns containing B binary weighted LSB bits. k2 ) − 2kN −1 1 k1 − 2N−1 k2 2 k2 − 2N−1 k2 .N − 1].
4714 0.20) with elements T T cs k1 .4000 0.400 0.6455 1 0.5477 0.3536 0.7303 0.6455 0 0 0.3536 0 0 0.23) To give an example of the differences between the correlation matrices of a thermometercoded and binaryweighted D/A converter.7500 0.5477 0.5477 0.3536 0.4714 0.7500 1 0. correlation matrices for 3bit converters are presented.7303 0. (6.24) .2582 0 0 0.64 Currentsteering digitaltoanalog converter design The INL covariance matrix of the segmented D/A converter is T Cs = E INLs × INLs T = ST As As S σ2 lsb T = E ST As Es Es AT S s (6.1667 0 0 0.1667 0.2582 0. lsb 2N − 1 (6.5477 0.2582 0.4714 0.6455 1 0 0 0 0 0 .2582 0.7303 1 0.6455 0.21) The variances of INL can be found on the diagonal of Cs resulting in σ2 s k = k − INL The correlation coefﬁcients are given by ρs k1 .7303 1 0. 0 0 0 0 (6.3536 0.k2 = Sk1 WdsWds Sk2 − k1 k2 σ2 lsb 2N − 1 (6.k2 = = COV [INLs k1 . The correlation matrix Rt for the 3bit thermometercoded D/A converter is 0 0 0 Rt = 0 0 0 0 0 0 1 0.4714 0 0 0.22) k2 2 k2 − 2N−1 k2 . INLs k2 )] σIk1 σIk2 T T 1 k2 Sk1 WdsWds S − 2kN −1 1 k1 − 2N−1 k2 σ2 .
0 0 0 0 (6.2582 −1 0 −1 0.2582 0.2582 −0.Rb .2582 −1 0 0 −0. 0 0 0 0 (6. and therefore they are not invertible.5477 −0.4714 0.7303 −1 0.4714 0.7303 0.2582 0 −0.1667 1 0 0.6.26) 0.4714 −0.2582 0 −0.25) Rb = 0 0 0 0 0. the resulting matrices Cb2 and Cs2 are singular.7303 −0. 3) If the edge rows and columns are discarded from Cb and Cs .7303 0.7303 1 −0.4 0. and therefore they can be discarded from the statistical model of INL. The correlation factors of the binaryweighted converter be .4714 0.4714 −0.5477 0.3 Models and relations of transistor mismatch and static linearity 65 Correlation matrix Rb for the 3bit binary weighted D/A converter is 0 0 0 1 0 −0.4714 0.7303 0. their determinants are zero.4714 0 −0.2582 −0.7303 −1 1 0 0.7303 1 −1 0 −0.5477 0.4714 0 0 −0. Cb . They are symmetrical positive semideﬁnite matrices.2582 1 0.2582 0. 2) If the edge rows and columns are discarded from Ct .7303 1 0.4000 0.2582 0 0 0. the resulting matrix Ct2 is a symmetrical positive deﬁnite matrix and hence invertible. and Rs : 1) Values on the edges of the covariance matrices are zero which means that INL values at k = 0 and k = 2N − 1 are zero. The square root of the positive deﬁnite matrix is nonsingular.7303 −0. 4) The correlation factors of INLs of the thermometercoded D/A converters are positive and their values are less than one.4714 −0.4714 0 0.2582 −1 0 −0.2582 0 0 −1 0 0 0 0 .5477 0. and Cs .4714 0.4714 0 The following observations can be made about the covariance matrices Ct . and correlation matrices Rt .4714 0 Correlation matrix for the 3bit converter with 2 segmented MSB bits 0 0 0 0 Rs = 0 0 0 0 0 1 −0.4714 0.2582 0 0 0.7303 0.2582 1 0.4714 −0.1667 0.4714 0. Its inverse is also positive deﬁnite.2582 1 0 0 0 0 0 . 5) The correlation factors of the segmented and binaryweighted D/A converters can be negative.2582 1 0 0.7303 1 −0.
and Cx is a symmetric positive deﬁnite covariance matrix.06 0. Once the variances.mn ]T is a vector containing the means of x.66 Currentsteering digitaltoanalog converter design Standard deviation of INL 0. The probability density function (PDF) of the MVN is fx (x) = 1 (2π) Cx  n 2 1 2 e− 2 (x−mx )Cx 1 −1 (x−m ) x .08 STD deviation of INL [LSB] 0.05 0. it is possible to try to ﬁnd a statistical model for the INL.03 0.07 0. mx = [m1 .... x2 . (6. .02 0.12 RMS of 500 INLs of the thermometercoded D/A converter..09 0. tween INLs positioned symmetrically relative to the midpoint of the INL curve have the correlation factor 1. indicating the perfect negative correlation. For INLt2 (INL. covariances and correlation factors are calculated.01 0 0 2000 4000 6000 8000 10000 Input code 12000 14000 16000 Simulated Calculated Figure 6.27) where x = [x1 . m2 . from which the ﬁrst and last values are discarded because they are .xn ]T is a vector of n real valued random variables. Figs 6. One good candidate for the statistical distribution model of the INL is the multivariate normal distribution (MVN) . .13 represent the simulated and computed values of the standard deviation of INL for the thermometercoded and binaryweighted D/A converter.14). It can be seen that the simulated values follow quite accurately the values computed with Eq.12 and 6. (6.04 0.
13 RMS of 500 INLs of the binaryweighted D/A converter. (6.05 0. (6. always zero). simulations were performed by generating vectors of random variables that have the desired variance and covariance properties.6.06 0.04 0.. the cumulative distribution function (CDF) of INLt2 can be deﬁned as FINLt2 (INLt2 ) = (2π) 1 2N −2 2 Ct2  1 2 Z I1 −∞ .02 0.29) In order to validate the assumption of the multinormal distribution. from which the ﬁrst and last values are discarded because they are always zero) this is not possible. Simulation . since Cb2 and Cs2 are singular and therefore not invertible.03 0..3 Models and relations of transistor mismatch and static linearity 67 Standard deviation of INL 0.01 0 0 Simulated Calculated 2000 4000 6000 8000 10000 Input code 12000 14000 16000 Figure 6.08 STD deviation of INL [LSB] 0. (6.dI2N −2 .07 0.30) where X is a vector of an independent N(0. Z I N−2 2 −∞ e− 2 INLt2Ct2 1 T −1 INLt2 dI1 .1) distributed random variable.28) but for INLb2 and INLs2 (INL.09 0.. This is achieved by variable transformation X = Ct2 2 INLt2 .. −1 1 2 INLt2 = Ct2 X. Once the PDF is deﬁned. the MVN density function can be written as fINLt2 (INLt2 ) = (2π) 1 2N −2 2 Ct2  1 2 e− 2 INLt2Ct2 1 T −1 INLt2 . and because their determinants are zero.
however. The results are presented in Figs. However.186. Eq.29) is probably solvable by numerical methods [127]. (6.5 Figure 6. that the results obtained with MonteCarlo simulation follows quite accurately the MVN distribution generated by variable transformation. Despite the difﬁculties solving Eq. Simulation results indicate that the assumption of the multivariate normal distribution is valid for INL values of the thermometercoded D/A converter. the number of random variables (2 N − 2) is much larger than the number of variables (7) that the program presented in [127] could handle. It can be observed. 6.17. if we take into account the development of computer resources. however.5 0 0. Probability density −1. we may write the exact deﬁnition of INL yield in the case of thermometercoded D/A converter (assuming that the distribution . the N = 14 case is perhaps solvable with modern computers. 6.5 1 1. the comparison can be made for the segmented 8bit converter with 4 binaryweighted bits.146.68 Currentsteering digitaltoanalog converter design Probability density function of INL 10 9 8 7 6 5 4 3 2 1 0 PDF: Monte Carlo PDF: Multivariate normal distr.5 −1 −0.[129].14 PDF of INL of a thermometercoded D/A converter with various values of σ. the multivariate normal distribution is not directly applicable.[128]. Singular Value Decomposition can be used in order to calculate an approximation of the inverse of covariance matrices.29). in all practical cases (N > 12). Due to the fact that the covariance matrices for the binaryweighted and the segmented D/A converter are not invertible. results for the 8bit thermometer coded D/A converter are presented in Figs. (6. Similarly. this does not solve the problem related to the zerovalued determinant of the singular covariance matrices.21.
6.2 0.5 0 0.6 0.6 0.8 1 1.4 0.5 −1 −0. .4 0. Probability density 10 5 0 0.5 1 1.2 1.16 PDF of the maximum absolute value of INL of a thermometercoded D/A converter with various values of σ. Probability density function of MAX(ABS(INL)) 15 PDF: Monte Carlo PDF: Multivariate normal distr.8 Figure 6.6 1.3 Models and relations of transistor mismatch and static linearity 69 Cumulative probability density function of INL CDF: Monte Carlo CDF: Multivariate normal distr.2 0 −1.5 Figure 6.4 1. 1 0.8 Probability 0.15 CDF of INL of a thermometercoded D/A converter with various values of σ.
6 0.6 1.4 0.17 CDF of the maximum absolute value of INL of a thermometercoded D/A converter with various values of σ. Probability density −1.8 Figure 6. Probability density function of INL 10 9 8 7 6 5 4 3 2 1 0 PDF: Monte Carlo PDF: Multivariate normal distr.2 0 0.8 1 1.5 1 1.18 PDF of INL of a segmented D/A converter with various values of σ. .5 Figure 6.5 −1 −0.2 0.4 1. 1 0.70 Currentsteering digitaltoanalog converter design Cumulative probability density function of MAX(ABS(INL)) CDF: Monte Carlo CDF: Multivariate normal distr.8 Probability 0.6 0.2 1.5 0 0.4 0.
2 1.8 Figure 6.4 1.6 0. Probability density 10 5 0 0.8 1 1.2 0.8 Probability 0.4 0. 1 0.3 Models and relations of transistor mismatch and static linearity 71 Cumulative probability density function of INL CDF: Monte Carlo CDF: Multivariate normal distr.6. Probability density function of MAX(ABS(INL)) 15 PDF: Monte Carlo PDF: Multivariate normal distr.4 0.5 1 1.5 −1 −0.5 Figure 6.20 PDF of the maximum absolute value of INL of a segmented D/A converter with various values of σ.5 0 0.19 CDF of INL of a segmented D/A converter with various values of σ.6 1. .6 0.2 0 −1.
5) × 100% = (2FINLt2 (INLt2 ) − 1) × 100%.2 0.5. The analysis is included in this book also to complete the analysis of the previously published yield models. 0. we could. 1 0.5.4 0.6 0.31) (6. because the yield is a function of the relative variance of the unit current source. in theory. INLt2 = [0.8 Probability 0. .72 Currentsteering digitaltoanalog converter design Cumulative probability density function of MAX(ABS(INL)) 1.33) This equals the proportion of converters selected from a random set of converters that fulﬁlls INL speciﬁcation INL ≤ 0.21 CDF of the maximum absolute value of INL of a segmented D/A converter with various values of σ. discover the area and operating point that would give a desired yield.2 0 0.. The yield analysis presented in this book was performed by the author most likely at the same time as Cong and Geiger without knowledge of their work.8 1 1.5] . which is a function of transistor area and operation point [124]..32) (6.6 1.2 1. T (6. performed in the next section.5.6 0.4 1.0.8 Figure 6. follows the MVN distribution) YieldINLt = P (INLt2  < 0. The result that the INL of the converter follows the multivariate normal distribution is also presented by Cong an Geiger in [130]. Thus.4 0.2 CDF: Monte Carlo CDF: Multivariate normal distr.
5 − 0. If it is assumed that the probability of an INL error existing at some code position k = 2N−1 − 2. This model does not take into account the ﬁtting of the output between the code values 0 and 2N − 1.75 the Yieldinl be comes negative. according to simulation results presented in [132]. this model results in optimistic results as demonstrated by simulations later in this section.3 INL yield models Because the solution of Eq.5 < 0. with variance 2 2N σlsb .14) and Eq. In [124] the assumption is made that the INL values are independent.29) is quite hard to compute. Assuming that if there is a INL error somewhere at the code positions k = 0.. which is not possible in any case. −1 bility of 0... [126]. Various methods [124]. [132] has lsb been suggested for evaluating the maximum current source variance allowed in order to achieve the desired accuracy of the converter (or.5 2N σlsb (half of the maximum value due to ﬁtting a line between the endpoints). (6. In [126].6. there is a probaN is equal to the probability of an INL error existing in the code range k = 0.2N−1 − 2. and P Y 2N < 0. and thus the probability to have a certain INL value can be computed as a product of normally distributed probabilities over the input range.it seems to model the statistical behavior of the sum of error sources very accurately in the certain parameter range. if an INL error occurs when passing through all the possible input codes. the relation of YieldINL and σ2 has to be deﬁned by other means. a highenough yield). however. Also with probability values P Y 2N < 0. (6. (6. since the yield is inherently positive for all ﬁnite error variance values. an observation is made that the maximum standard deviation of the output values is achieved at the two centermost input codes. In [132]. (6.2N − 1 .3 Models and relations of transistor mismatch and static linearity 73 6.. The result is approximately the same as the results obtained with Eq. [131].. there is a 50% chance that the error still occurs for ﬁctive code 2N .5 can be obtained from the CDF of the normal distribution. it is assumed that.5 that it still exists at the ﬁctive code position k = 2 2 .. and therefore it is worth of trying to further improve it to model the actual INL yield with line ﬁtted between the endpoints. in other words.22). This statement is veriﬁed with simulations.3. However.75 × 4 × 100%. and that the INL error values of these two halves are uncorrelated (which is not true). The model presented in [132] gives a quite accurate estimate of the statistical behavior of INL+gain error. the value is 0. resulting in Yieldinl = P Y 2N < 0. Using this assumption yields pessimistic results.2N−1 − 2. This is commented on [133] and the model is improved in [131] so that only the two most probable error values at MSB transition are taken into account.34) where Y 2N is normally distributed error at the ﬁctive input code 2 N .
75 × 4 × 100%. (6.14).35) N −1 −1 where Y2 2 2 is a normally distributed random variable with variance σ22 = 2 y which is obtained from Eq. The simulated converter is a 14bit segmented one with 10 binary weighted bits.23. which of these models gives the most reliable results for the D/A converter design. 6. the simulations were also carried out for the 5 and 6bit thermometercoded D/A converters (Fig. The INL yield obtained with various methods as the function of unit current source standard deviation is presented in Fig.5 3 3. Van den Bosch et.22 INL yield as a function of standard deviation divider C. (modified) Simulated 1 1.5 − 0. the following equation for INL yield can be written Yieldinl2 = N P Y2 2N − 1 2 2 < 0. The relative standard deviation of a unit current source is assumed to be σlsb= √1N .5 C Figure 6.5 0 0.25). al.74 Currentsteering digitaltoanalog converter design INL yield simulations 100 90 80 70 60 Yield [%] 50 40 30 20 10 Product method Product method (2 middle) Normal distribution Van den Bosch et. (6. In Fig. 4 σ2 . lsb As a reference. One thousand converters are used in MonteCarlo simulations. In order to demonstrate the shortcoming of the modiﬁcation of the Van den Bosch method. 6. 6.5 2 2.24 and Fig. 2C 2 −1 . it is also tested how an INL yield follows the normal distribution with variance σ2 = (2N − 1)σ2 . al. they are compared to the results obtained with MonteCarlo simulations. In order to ﬁnd out. 6.22 the simulated yield and different estimation methods are compared. This equals the assumption that the maximum INL inl lsb is the sum of the error currents.
it was argued that. the designer is still dependent on MonteCarlo simulations. pessimistic yield estimations are obtained in the practical yield range. With the assumption of normally distributed INL with the standard deviation σinl = √ 2N − 1σlsb . one can always rely on numerical methods. It can be observed that. and in the 6bit case. the results obtained from the proposed model are somewhat optimistic.7 10 −2. when a 14bit segmented case. for certain INL and DNL yields. So.6 10 −2. al.9 0 10 −2. For accurate information. Instead of the sophisticated variations of guessing discussed in the previous section.8 10 −2. In [130]. the required relative . (modified) Simulated 10 −2. It can be used as a “rule of thumb”model: “The Rule of three sigmas” results in highenough yield. it is mandatory to use some kind of approximative approach if an accurate estimation of the yield is required. it can be seen that the accuracy of the model depends on the number of bits of the converter.3 10 −2.2 Sigma [LSB] Figure 6.3 Models and relations of transistor mismatch and static linearity 75 INL yield simulations 100 90 80 70 60 Yield [%] 50 40 30 20 10 Product method Product method (2 middle) Normal distribution Van den Bosch et. Van den Bosch et. the results are just slightly optimistic.6. Based on the simulation results. 6. results are (almost) identical compared to MonteCarlo simulations.4 Regression model for the INL and DNL yields Due to difﬁculties in the evaluation of the cumulative distribution function of the INL yield.3.23 INL yield as a function of standard deviation of the unit current source. al.4 10 −2. it is justiﬁed to say that none of presented INL yield approximations gives an accurate basis for the design of the D/A converter.5 10 −2. in the 5bit case.
5 0 0.5 2 2.5 C Figure 6.76 Currentsteering digitaltoanalog converter design INL yield simulations 100 90 80 70 60 Yield [%] 50 40 30 20 10 Product method Product method (2 middle) Normal distribution Van den Bosch et. Van den Bosch et.5 C Figure 6. al.5 2 2. (modified) Simulated 1 1.5 3 3. . al. (modified) Simulated 1 1. INL yield simulations 100 90 80 70 60 Yield [%] 50 40 30 20 10 Product method Product method (2 middle) Normal distribution Van den Bosch et.5 0 0.5 3 3. al.25 Modiﬁcation of the Van den Bosch method in 6 bit case. al. Van den Bosch et.24 Modiﬁcation of the Van den Bosch method in 5 bit case.
26 Average INL yield as a function of C for various number of segmented bits (M). tabulated values of Z(Yield). Therefore the average of the yields obtained with a different number of bits can be used in Fig.26. the required σlsb can be discovered easily with.2 1. and that the binaryweighted D/A converters have worse differential nonlinearity (DNL) performance. 6. It was demonstrated that the binaryweighted and the thermometercoded D/A converters have different Z(Yield). 6.27. as explained later.26 and Fig. (6. 2N (6. C in the ﬁgure is the divider of the relative standard deviation of the LSB σlsb = √1N .8 2 2. Fig.36) where A is the range limit to where INL and DNL values should be. for example. 6. This is obtained from Eq. 6.4 C 1.28 and Fig.29) on the bit range from 10 to 16.6 1. standard deviation of the unit current source can be written as A σlsb ≈ √ Z (Yield) . .2 M=1 M=2 M=3 M=4 M=5 M=6 Figure 6.8 1 1.36) is substituted by 2N − 1 in order to deﬁne the required σlsb to be C dependent on the total number of current sources in the converter. INL yield is dependent on the segmentation of the converter as can be seen from Fig. the effect of the number of bits on the yield is small (also in [130]) (absolute error to average yield.36) by substitution A = 1 and Z(Yield) = 2 2C 2 −1 1 . 2N in Eq. Because of this.3 Models and relations of transistor mismatch and static linearity 77 Average INL yield with various values of M 100 90 80 70 Yield [%] 60 50 40 30 20 10 0 0. 6. By deﬁning σlsb this way.6. (6. is ±4%. and Z(Yield) is a weighting function that is independent of the number of bits (N).
2 1. With the help of Eq. 6.8 1 1. This assumption is validated by simulations by using the variable ranges under consideration.8 2 M=1 M=2 M=3 2. indicating that the dependency of the required σlsb on N can not be modeled with Eq. The yield as a function of C and segmentation could be tabulated. the following assumptions are made.2 Figure 6. M. It is emphasized. which is applicable for most of the design cases at the moment. The number of INL curves simulated per each N. The solution proposed in [14] is a regression model based on the results of MonteCarlo simulations. The number of thermometercoded bits is selected to vary from 16. or curves could be given as in [130].C combination is 2500. It is also assumed. (6.78 Currentsteering digitaltoanalog converter design Averege DNL yield with various values of M 100 90 80 70 Yield [%] 60 50 40 30 20 10 0 0. however. for example. and the model can be developed in such a way that it also includes the dependency on the segmentation level. INL yield is also a function of the number of segmented bits.36). and by taking into account the number of segmented . it does not hold when the total number of bits is small. that the regression model is applicable only within the variable ranges that it was developed in.4 C 1.36) for all N. as shown in.27 Average DNL yield as a function of C with various number of segmented bits (M).6 1. As a basis of the model. The range of bits is 1016. (6. that INL and DNL yields are dependent on the number of thermometercoded MSB bits because of their larger weight.26. Fig.
respectively.81011 0.75315 11..C.46103 11. + gi+1 M. + C g(i×l) M l Ci (6.M − XG)T (LYC.3 Models and relations of transistor mismatch and static linearity 79 Table 6.M − XG).49109 2.28 the error between the MonteCarlo simulation results and the proposed .03389 4.55515 3.25. Φ(C.83137 34. and G = g0 . corresponding to a certain C and M. X is a matrix with rows containing the elements of T X(C.37269 M1 1. + Cii .. M). M) and corresponding coefﬁcients are presented in Table 6.40) In the proposed model the values of i and l are chosen to be 5 and 3. (6.72128 9. M) = g0 + g1 . resulting in ∑ ε2f = (LYC. 6.1. respectively.10156 bits also. M) of the INL model 1 C−1 C−2 C−3 C−4 C−5 1 0.89139 1. where i and l are the highest powers of C and M.06717 3.31774 0. in order to achieve reasonable accuracy.45830 M2 0. The minimum of ∑ ε2 is obtained by setting the derivative of ∑ ε2 relative to G to zero..65 to 2.04734 0.14615 5. The terms of X(C.39) where LYC.. (6.75819 29.. 2C 2 −1 The range of C is from 0.25836 0.6.M )) is a vector containing the natural logarithm of the average of the simulated yield values over the range of bits (N) from 1016. M) can be found by ﬁtting some proper function to the average of the data obtained by MonteCarlo simulations.M . M) = eX(C. This f f occurs when G = (X T X)−1 X T LYC. INL yield can be written as Yield = Φ(C.15067 M3 0. (6. In Fig.M) g X(C..M = ln (AV GN (YN.85655 18.1 gcoefﬁcients of X(C..75115 4.96023 0. The chosen function is Φ(C.29711 1.51356 0.38) . The ﬁtting is performed by minimizing the sum of squared errors between the MonteCarlo simulation results and the model.37) where C is related to σlsb as σlsb = √1N and M is the number of segmented bits.. M) corresponding to certain values of C and M.g(i×l) .
80 Currentsteering digitaltoanalog converter design INL yield error M=4 4 3 2 1 0 −1 −2 −3 −4 N=10 N=11 N=12 N=13 N=14 N=15 N=16 Yield error [%] 0.94454 3.4 C 1.30.2 gcoefﬁcients of DNL model 1 C−1 C−2 C−3 C−4 C−5 1 2. 6.25724 27.8 2 2.82176 25.47087 6.29. Error bounds between the simulated INL yields and the model are presented in Fig. Table 6.36716 .8 1 1.34097 M1 2.14603 30.28905 32.64198 3. The error between the simulated DNL yields and the values given by the model is presented in Fig. 6. The coefﬁcients g for the DNL yield model are presented in Table 6. model is presented in the case M = 4. The model for DNL yield is obtained with a similar method.52953 14.64437 14.86155 16.2 Figure 6.35736 0.08428 M2 0.81305 11.73440 2.63958 5.77177 2.2 1.6 1.28 Error between simulated INL yields and values given by the model as a function of C.2. M = 4.
6.8 2 2.8 1 1. . Limits of DNL yield error as a function of C 4 3 2 1 0 −1 −2 −3 −4 Yield error [%] 0.29 Error bounds between simulated INL yields and values given by the model as a function of C.30 Error bounds between simulated DNL yields and values given by the model as a function of C.2 Figure 6.6 1.6 1.2 1.8 2 2.2 1.3 Models and relations of transistor mismatch and static linearity 81 Limits of INL yield error as a function of C 4 3 2 1 0 −1 −2 −3 −4 Yield error [%] 0.8 1 1.4 C 1.4 C 1.2 Figure 6.
Since in any practical case of currentsteering D/A converter design the structure of the converter is either binary weighted or segmented. that the tuning of the current is performed by storing the Vgs of the diode connected transistor into the capacitance between the gate and source of the current source transistor. which. thereby enabling the tuning of the current to be achieved theoretically with inﬁnite accuracy. The principle of the tuning is presented in Fig. divides the large DNL values of the binary weighted part into multiple smaller DNLs. and no quantization of the error occurs in any phase of the calibration cycle. DNL can be reduced by minimizing the error of the current sources of large weight by using calibration. since the variances of INL and DNL are inversely proportional to area of the current source Eq. the calibration algorithms usually calibrate the DNL of the converter. An example of continuous calibration is presented in [134]. 6. the DNL of the converter is determined by the currents with the largest weight as σ2 ≈ Bσ2 . no matter how good the gradient cancellation might be. Several calibration techniques have been developed to reduce the amount of error of the MSB current sources.4 Calibration techniques The static linearity of the currentsteering D/A converter is dependent on the dimensions of the current sources and their placement. the fact is that static accuracy above 12 bits is hardly achievable with present silicon technologies. The calibration techniques usually concentrate on tuning the erroneous current values.82 Currentsteering digitaltoanalog converter design 6.3. Various layout techniques have been developed in order to reduce the effects of the gradients on the silicon die and various algorithms have been developed in order to dimension the current sources to achieve adequate static matching. in practice.5). but does not affect DNL values at the transitions of the current sources with largest weight. and the area required becomes quite large when linearity above 12 bit is targeted. Two main categories of calibration can be identiﬁed: continuous and quantized. There is no way to improve the matching without increasing the area. However. In addition. this also has an effect on INL. By using the same reference source for all of .41) in which B is the number of LSB currents switched during the code transition (assuming no calibration is used). dnl lsb (6. (6. It can be observed.31. Because there is no practical way to measure the INL of the converter onchip. as stated in Section 6. It is also possible to use multiple thermometercoded segments. It is continuous because the tuning process is purely analog. DNL can be reduced by reducing B by increasing the number of thermometercoded bits.
32. The principle of this calibration method is presented in Fig.31 Principle of continuous tuning of an MSB current source. The common factor for these methods is the quantization of the measured error and the usage of additional digitaltoanalog converters to tune the values of the MSB current sources.6. the calibration suffers from charge injection from the switches and leakage currents. [137] and [139]. it is possible to equalize the currents of the MSB sources. Error Measurement & A/D Conversion DAC Core Calibration DAC Memory Figure 6. there can be either one large calibration DAC.32 Principle of quantizing calibration of currentsteering D/A converter. which is the main drawback of this method. or multiple smaller calibration DACs for each of the MSB sources. as in [135]. [138] and [139]. for example. because the switches are nonideal. [135]. [137]. This approach is used in. Because of leakage current the calibration of the source has to be repeated continuously in order to maintain the accuracy. These additional digital to analog converters are usually called ”Calibration DACs”. However. This problem can be avoided by using digital memory to store the error value. 6.4 Calibration techniques 83 Iref Iref Calibration Operation Figure 6. as in [138] and [136]. the MSB current sources. The most common calibration technique is to use digital storage elements to store the error values of the MSB current sources and use these values to tune the currents. . [136].
34 and Fig. the quantized method is inaccurate due to quantization noise. stored digitally and MSB currents are tuned by D/A conversion of the stored error. Because of the redundancy. enabling the correction of the errors of the MSB sources by digital predistortion of the input code. The calibration is performed as follows: the MSB sources. The main difference between this method and previously introduced methods is that there is no particular calibration DAC. Whereas the continuous method was purely analog and therefore accurate but sensitive to nonidealities. the input code space and output range of the converter are extended with four additional MSB current sources. The principle of the proposed calibration method is presented in Fig. the tuning is made by analog means.34. but insensitive to interference due to the digital storage element. and resolution of the calibration DAC. 6. Instead.33 Block diagram of the D/A converter with calibration using digital predistortion. A slightly different technique is suggested by the author and presented in [14]. quality of the A/D conversion. error is measured.84 Currentsteering digitaltoanalog converter design VDD R R DAC Calibration Unit Clk Data Control Figure 6. The term quantized is therefore more valid in this context than the term ”digital”. since the only digital part of these calibration methods is the storage element. the main drawback of these methods is related to quantization. 6. The methods differ from each other mainly in ways of performing the measurement of the error and actual way of tuning the current. but the principle is the same. The quality of the calibration is determined by the accuracy of the measurement. A/D converted. Also. including the additional . redundancy is added to the converter by biasing the MSB current sources so that the current of a single MSB source is less than the sum of the LSB sources.
6.4 Calibration techniques
85
LSB
Output
1/8 LSB
Bias offset
Offset MSB1 CAL MSB2 Input code
REF
Figure 6.34 Principle of the calibration algorithm using digital predistortion.
sources, are biased so that the current of the MSB source is less than the sum of the LSB sources. This ensures, that the output value of the converter decreases as a new MSB current source is added to the output. Then the REFvalue in Fig. 6.34 is set to CAL1. While calibrating, the REF values are ﬁrst decreased in 4 LSB steps. When the output corresponding to the REF is less than that corresponding to the CAL, the REF value is increased by steps of 1/8 LSB as long as the output corresponding to REF is again greater than the output corresponding to the CALvalue. This is simply a successive approximation register (SAR) A/D conversion of the error value. The difference between the ﬁnal CAL and REF values is then stored to memory as an offset value. The CALvalue is then increased in order to add the next MSB current to output, and the SARcycle is repeated. After all of the offsets are measured and stored, the calibration cycle is completed and the offsets can be used in normal operation mode to predistort the input code in order to linearize the transfer function of the converter. The functionality of the calibration algorithm was veriﬁed with simulations. Figs. 6.35  6.39 represent the minmax envelope curves for DNL and INL uncalibrated and calibrated 16bit D/A converter with 6 thermometer coded MSB bits under various matching conditions for the LSB and MSB current sources. DNL and INL yield curves for various matching conditions are presented in Fig. 6.40. The number of converters in each of the yield simulations is 1000. In each of the presented cases DNL and INL yields for uncalibrated converters is 0%. In the curves for the uncalibrated converters, the effect of the bias offset on the yield is removed, so that the presented curves indicate directly the effect of the matching on the yield.
86
Currentsteering digitaltoanalog converter design
INL uncalibrated
5 4 3 2 1 0 −1 −2 −3 −4 −5 16k 32k 48k 0.6 0.4
INL calibrated
INL [LSB]
INL [LSB]
0.2 0 −0.2 −0.4 −0.6 16k 32k 48k
Input code DNL uncalibrated
1.5 1 0.1
Input code DNL calibrated
DNL [LSB]
DNL [LSB]
16k 32k 48k
0.5 0 −0.5 −1 −1.5
0.05 0 −0.05 −0.1 16k 32k 48k
Input code
Input code
1 √ I , 2×3 216 −1 LSB
Figure 6.35 Result of calibration, σLSB =
σMSB =
√ 16 210 √ I . 2×3 216 −1 LSB
INL uncalibrated
5 4 3 2 1 0 −1 −2 −3 −4 −5 16k 32k 48k 0.6 0.4
INL calibrated
INL [LSB]
INL [LSB]
0.2 0 −0.2 −0.4 −0.6 16k 32k 48k
Input code DNL uncalibrated
1.5 1 0.125
Input code DNL calibrated
DNL [LSB]
0.5 0 −0.5 −1 −1.5 16k 32k 48k
DNL [LSB]
0
−0.125 16k 32k 48k
Input code
Input code
2 √ I , 2×3 216 −1 LSB
Figure 6.36 Result of calibration, σLSB =
σMSB =
√ 16 210 √ I . 2×3 216 −1 LSB
6.4 Calibration techniques
87
INL uncalibrated
5 4 3 2 1 0 −1 −2 −3 −4 −5 16k 32k 48k 0.8 0.6
INL calibrated
INL [LSB]
INL [LSB]
0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 16k 32k 48k
Input code DNL uncalibrated
1.5 0.25 1
Input code DNL calibrated
DNL [LSB]
0.5 0 −0.5 −1
DNL [LSB]
16k 32k 48k
0
−0.25 −1.5 16k 32k 48k
Input code
Input code
4 √ I , 2×3 216 −1 LSB
Figure 6.37 Result of calibration, σLSB =
σMSB =
√ 16 210 √ I . 2×3 216 −1 LSB
INL uncalibrated
0.8 5 4 3 2 1 0 −1 −2 −3 −4 −5 16k 32k 48k 0.6 0.4
INL calibrated
INL [LSB]
INL [LSB]
0.2 0 −0.2 −0.4 −0.6 −0.8 16k 32k 48k
Input code DNL uncalibrated
1.5 0.5 1
Input code DNL calibrated
DNL [LSB]
DNL [LSB]
16k 32k 48k
0.5 0 −0.5 −1
0.25 0 −0.25 −0.5
−1.5 16k 32k 48k
Input code
Input code
8 √ I , 2×3 216 −1 LSB
Figure 6.38 Result of calibration, σLSB =
σMSB =
√ 16 210 √ I . 2×3 216 −1 LSB
88
Currentsteering digitaltoanalog converter design
INL uncalibrated
5 4 3 2 1 0 −1 −2 −3 −4 −5 16k 32k 48k 1.2 1 0.8 0.6 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1 −1.2
INL calibrated
INL [LSB]
INL [LSB]
16k
32k
48k
Input code DNL uncalibrated
1.5 1.25 1 0.75 0.5 0.25 0 −0.25 −0.5 −0.75 −1 −1.25
Input code DNL calibrated
DNL [LSB]
0.5 0 −0.5 −1 −1.5
16k
32k
48k
DNL [LSB]
1
16k
32k
48k
Input code
Input code
16 √ I , 2×3 216 −1 LSB
Figure 6.39 Result of calibration, σLSB =
σMSB =
√ 16 210 √ I . 2×3 216 −1 LSB
INL and DNL yields of 16−bit calibrated DACs
100
INL DNL
90
80
Yield
70
60
50
40 0 0.002 0.004
σLSB
0.006
0.008
0.01
0.012
Figure 6.40 DNL and INL yields of a calibrated 16b D/A converter as a function of σLSB .
6.5 Effects of output impedance variation
89
Simulation results indicate that DNL and INL yields are strongly dependent on the matching of the LSB current sources which determines the achievable DNL and INL yield. It can be seen that, when the matching of the LSB sources is deteriorated, it begins to dominate the DNL, and thus the INL yield. It is also demonstrated that acceptable yield levels can be achieved with very poor MSB matching, thus making it possible to effectively reduce the area required for the MSB sources. The amount of the error that can be calibrated with the algorithm is determined by the amount of additional MSB current sources. Assuming zero mean error in the sources, the maximum error that can be calibrated equals the bias offset of the MSB current sources, whereas the sum of the bias errors cannot exceed the additional code range obtained by adding the sources. In the presented case, the code range added is 4096 LSBs and the number of MSB sources is 67, resulting in a maximum correctable error of 61 LSBs.
6.5 Effects of output impedance variation
The ﬁnite impedance of the current sources causes codedependent variation on the output impedance of the currentsteering D/A converter, introducing nonlinearity to the output signal. In this section, Taylorseries approximations of the INL of a singleended and differential converter are presented in order to give equations of the nonlinearities, which are then used to compute the analytical result of maximum INL and SFDR as a function of output impedance. Nonlinearities due to impedance variation have been previously discussed in [140], [141], [142], and [143]. The secondorder nonlinearities due to impedance variation are discussed in [140], [141] and [142], thirdorder distortion is analyzed in [143], and the frequency dependency of the output impedance is discussed in [142]. Results presented in this section equal the results presented in [142] for a singleended case; however, results for the SFDR of differential converter differ from the results presented in [143]. The frequency dependency of the output impedance is analyzed mathematically in detail and the results are veriﬁed with simulations. Results differ slightly when compared to [142]. The limits of moving the poles and zeros of output impedance in frequency are determined. The analysis of the output impedance analysis is linked to implementation by analyzing the effect of transistor dimensions on the frequency response of the output impedance, demonstrating the effect of various design parameters, and the boundaries of the output impedance optimization.
90
Currentsteering digitaltoanalog converter design
Vout k I lsb Zu k Zl
Figure 6.41 Output impedance variation of the singleended D/A converter.
6.5.1
Distortion due to low frequency impedance variation
Let a single current source branch of a fully thermometer coded D/A converter have the impedance Zc when the switch is conducting, and impedance Zop when it is not. In this case, the change in the impedance due to switching can be modeled as an impedance in parallel with the impedance Zu of the open (not conducting) switch. Zu can be computed as Zc Zop . (6.42) Zu = Zop − Zc Since Zop is usually very large at low frequencies, the low frequency analysis can be performed by observing the value of the current branch in the conducting state; however, in highfrequency analysis it is important to isolate Zop , since it is constant and thus does not introduce any distortion. However, Zop may introduce some undesired phenomena such as frequencydependent attenuation and, in that sense, it should be taken into account. Frequency dependency is discussed in more detail in Section 6.5.2. The lowfrequency effects of the impedance variation can be analyzed as follows. In Fig. 6.41, the simpliﬁed circuit for a singleended D/A converter is presented. The single ended converter has the output voltage Vout (k) = kIlsb Zl 1 + kZl Zu , (6.43)
in which Zl is the load impedance and Zu is the impedance of the unit current source. INL caused by the ﬁnite output impedance of the current source can be written as
kZl 1+ Zul
kZ
−
INLzse (k) =
kZl Zl 2N −1 1+ Zu
(
) . (6.44)
Zl 2N −1 1+ Zu
(
Zl
)
By performing thirdorder Taylorseries expansion for INLzse with respect to k, k ≈
45) Zl + 2N − 1 Zu 4 If k is considered as a real number instead of an integer. the maximum value of INL due to ﬁnite impedance of the current source is Zl N N N 1 Zl 2 − 1 (16 + 16 2 − 1 Zu + 2 − 1 ≈ Z Z 32 Zu (2 + (2N − 1) Z l )(1 + (2N − 1) Z l ) u u 2 INLzsemax at 2 Zl2 2) Zu (6. (6.46) kmax N 2 + 2N − 1 2N − 1 1 Zl 2 − 1 − ≈ 2 16 Zu 1 + (2N − 1) Zl Zu 2 Zl Zu . 91 Eq.44) can be written as Zl Zu INLzse (k) ≈ 2 + (2N − 1) Zl Zu 3 − 8 1 + 2N − 1 2 Zl Zu 3 k2 Zl2 2 Zu + 8 2N − 1 + 6 2N − 1 + 2N − 1 3 Zl − 2N − 1 Zu Zl2 .5 Effects of output impedance variation 2N −1 2 .48) +16 2N − 1 with the maximum absolute value INLzdimax 1 + 2N − 1 Zl2 N 2 −1 2 Zu (6.47) For differential output.50) at Zl 2N − 1 2 + 2N − 1 Zu 2N − 1 ± √ 2 Zl 4 3 1 + (2N − 1) Zu kmax ≈ (6. (6.6. fourthorder Taylorseries approximation of INL with reN −1 spect to k. k ≈ 2 2 can be written as INLzdi (k) ≈ 1 Zl2 2 2 Zu 2N − 1 − 2k 2 + (2N − 1) Zl Zu 4 − 16 1 + 2N − 1 Zl Zu k+ Zl Zu 4 k2 (6. 2 Zu k (6.49) 2N − 1 Z2 ≈ l2 √ Zu 6 3 1 + zl (2N − 1) 2 + zl (2N − 1) Zu Zu 3 (6.51) .
Eq. . 2 from which the amplitudes of the second and the third harmonic components can be determined. Zl 1 ≪ .52) Zu Zl dB. INL equations. Zu whereas INLzdimax is dependent on It can therefore be assumed that the evenorder distortion generated in a singleended converter is much greater that the oddorder harmonics in a differential case. (6. In the singleended case. with a 14bit converter it requires approximately Zu to be Zl greater than 72. the spurious free dynamic range (SFDR) is determined by the second harmonic component. being approximately 16 + 16 2N − 1 Zl Zu SFDRzdi ≈ + 7 2N − 1 Z2 u 2 Zl2 2 Zu (2N − 1)2 Zl2 Zu Zl dB.45) is approximately SFDRzse ≈ 4 + 2 2N − 1 Zl Zu Zl (2N − 1) Zu (6. although the secondorder distortion is usually attenuated about 20 dB. (6. SFDR is determined by the third harmonic.52) to ﬁnd the required Zu ratio in order to have good Zl enough SFDR. If the load impedance Zl = 50Ω.92 Currentsteering digitaltoanalog converter design Zl Zu It can be observed that INLzsemax is linearly dependent on Zl2 2. SFDR computed from Eq. It can be observed that the accuracy of Zl Taylor approximations is exacerbated with large values of Zu .54) 1 Zl ≪ .9 × 106 (157. (6.02N + 20log10 In the differential case. in real design. For example. (6. (6. (6. However.42. the impedance of the unit current source has to be greater than 3. only attenuated.49).25 dB) in order to have SFDR better than 85 dB.55) N − 1) Zu 16 (2 SFDRzdi ≈ 28.49). (6.6 × 109 Ω. include all nonlinearities due to output impedance variation normalized to LSB.45) and Eq.54) are presented in Fig. (6. it is impossible to cancel all evenorder distortion with differential structure.04 − 6.53) Zu 2 (2N − 1) SFDRzse ≈ 12. Thus the harmonic distortion can be discov(2N −1)(1+sin(ωt)) ered by applying sinusoidal input k = Eq. 6. (6. It was stated that the evenorder harmonics cannot be canceled. It is therefore good to use Eq.52) and (6.04N + 40log10 Comparison of simulated accurate distortion values and approximations from Eqs.08 − 12.45) and Eq. (6.
since the impedance tends to decrease as the frequency increases.44 represents a single current branch of a D/A converter with two cascode transistors above the current source transistor.5. Fig. 6. .6.2 Frequency dependency of the output impedance The frequency behavior of the output impedance also affects the distortion.42 Comparison of simulated and approximated values of SFDR for a singleended and differential converter. 6. which are included in constant impedance Zop .43. By using a smallsignal equivalent circuit for a transistor and by discarding the capacitances on the drain node of M4. 6. as presented in Fig.5 Effects of output impedance variation 93 SFDR approximations 300 Single−ended accurate Single−ended Taylor series Differential accurate Differential Taylor series 250 200 SFDR [db] 150 100 50 0 −10 10 10 −9 10 −8 10 Zl/Zu −7 10 −6 10 −5 10 −4 Figure 6.
94
Currentsteering digitaltoanalog converter design
SFDR due to output impedance variation 200 180 160 140 SFDR [dBc] 120 100 80 60 40 20 0
1 2 3 4 5 6 7 8 9
Differential Single−ended
10
10
10
10 10 10 Frequency [Hz]
10
10
10
Figure 6.43 SFDR as a function of frequency.
RL o+
Zu M4
RL o−
C3
Vc2 Vc1 Vb
M3 M2 M1 C2
C1
Figure 6.44 Current source with two cascode transistors and switches.
6.5 Effects of output impedance variation
95
it is possible to write the equation for Zu in Sdomain as Zu (s) = N (s) D (s) +s2C3C2 (gm2 + gds2 + gds1 ) +s2C3C1 (gm3 + gds3 + gds2 ) +s2C2C1 (gm4 + gds4 + gds3 ) +sC3 ((gm3 + gds3 ) (gm2 + gds2 + gds1 ) + gds2 gds1 ) +sC2 (gm2 + gds2 + gds1 ) (gm4 + gds4 + gds3 ) +sC1 ((gm4 + gds4 ) (gm3 + gds3 + gds2 ) + gds3 gds2 ) + (gm4 + gds4 ) (gm3 + gds3 ) (gm2 + gds2 + gds1 ) + (gm4 + gds4 + gds3 ) gds2 gds1 D (s) = s3C1C2C3 gds4 +s2C3C2 (gm2 + gds2 + gds1 ) gds4 +s2C3C1 (gm3 + gds3 + gds2 ) gds4 +s2C2C1 gds4 gds3 +sC3 ((gm3 + gds3 ) (gm2 + gds2 + gds1 ) + gds2 gds1 ) gds4 +sC2 (gm2 + gds2 + gds1 ) gds3 gds4 +sC1 gds4 gds3 gds2 +gds4 gds3 gds2 gds1 . Because gm ≫ gds , Eq. (6.56) can be approximated with Zu (s) ≈ Na (s) Da (s) C1C2C3 + s2 gm4 gm3 gm2 +1 C3C2 C3C1 C2C1 + + gm4 gm3 gm4 gm2 gm3 gm2 (6.60) (6.59) (6.58) (6.57) (6.56)
N (s) = s3C1C2C3
Na (s) = gm4 gm3 gm2 s3 +s
C2 C1 C3 + + gm4 gm3 gm2
Da (s) = gds4 gds3 gds2 gds1 s3 +s2 +s
C1C2C3 gds3 gds2 gds1
C3C2 gm2 C3C1 gm3 C2C1 + + gds3 gds2 gds1 gds3 gds2 gds1 gds2 gds1 C2 gm2 C1 C3 gm3 gm2 + + gds3 gds2 gds1 gds2 gds1 gds1 +1 . (6.61)
96
Currentsteering digitaltoanalog converter design
It is possible to further simplify Eq. (6.61) with the following assumptions. Usually C1 is very large compared to C2 and C3 because its value is determined by the routing m2 of the current source matrix. If gC1 ≫ gC3 gm3 ggds1 , the factorization results in ds1 ds3 gds2
C3 C1 s gm2 + 1 s gm4 + 1 gm4 gm3 gm2 Zu (s) ≈ . gds4 gds3 gds2 gds1 s C1 + 1 s C3 gm3 + 1 gds1 gds3 gds2
(6.62)
On the other hand, if
C3 gm3 gm2 gds3 gds2 gds1
≫
C1 gds1
C3 s gm4 + 1 gm4 gm3 gm2 Zu (s) ≈ . gds4 gds3 gds2 gds1 s C3 gm3 gm2 + 1 gds3 gds2 gds1
(6.63)
Poles p1, p2, and p, and zeros z1 and z2 of Zu in the twocascode case are at frequencies ωz1 ≈ ωz2 ≈ ω p1 ≈ ω p2 ≈ ωp ≈ gm2 C1 gm4 C3 gds1 C1 C3 gm3 gm2 C1 gds3 gds2 ≫ , C3 gm3 gds1 gds3 gds2 gds1 C3 gm3 gm2 C1 gds3 gds2 gds1 , ≫ C3 gm3 gm2 gds3 gds2 gds1 gds1 (6.64) (6.65) (6.66) (6.67) (6.68)
Similarly, we may write the equations for the case of only one cascode and current source (Fig. 6.45) and current source only (Fig. 6.46). In the onecascode case, the output impedance can be written as
C2 s gm3 + 1 gm3 gm2 gds3 gds2 gds1 s C1 + 1 gds1 C1 s gm2 + 1
Zu (s) ≈
s gC2 ds2
,
+1
C2 gm2 C1 ≫ gds1 gds2 gds1
(6.69)
C2 s gm3 + 1 gm3 gm2 , Zu (s) ≈ gds3 gds2 gds1 s C2 gm2 + 1 gds2 gds1
C1 C2 gm2 ≫ , gds2 gds1 gds1
(6.70)
6.5 Effects of output impedance variation
97
RL
Zu
RL o−
M3
o+
Vc1 Vb
M2 M1
C2
C1
Figure 6.45 Current source with one cascode transistor.
RL o+
Zu M2
RL o−
Vb
M1
C1
Figure 6.46 Current source without cascode transistor.
98
Currentsteering digitaltoanalog converter design
resulting in poles p1, p2, and p, and zeros z1 and z2 on frequencies ωz1 ≈ ωz2 ≈ ω p1 ≈ ω p2 ≈ ωp ≈ gm2 C1 gm3 C2 gds1 C1 gds2 C1 C2 gm2 , ≫ C2 gds1 gds2 gds1 C1 C2 gm2 gds2 gds1 ≫ . , C2 gm2 gds2 gds1 gds1 (6.71) (6.72) (6.73) (6.74) (6.75)
Similarly for the case of current source only, the output impedance variation is
C1 s gm2 + 1 gm2 Zu (s) ≈ gds2 gds1 s C1 + 1 gds1
(6.76)
with pole p and zero z gm2 C1 gds1 . ωp ≈ C1 ωz ≈ (6.77) (6.78)
As analyzed in [142], it is obvious that the best frequency performance is obtained when routing capacitances C1 , C2 , and C3 are minimized. Next, whether it is possible to
gm improve the frequency behavior by adjusting the dimensions (i.e. gds ratio) of cascodes and switches will be analyzed. The assumed parameter dependencies are presented in
Eqs. (6.79)(6.83) gm ∼ kgm W /L kgds gds ∼ L C1 constant C2 ∼ AccW3 L3 C3 ∼ AccW4 L4 . (6.79) (6.80) (6.81) (6.82) (6.83)
Dependencies of the capacitances are made on the assumption that C1 is determined by the large routing capacitance from current sources to cascode transistors, whereas C2 , and C3 are determined by the channel capacitances of the transistors, and therefore they are dependent on the dimensions of the transistors. Dependencies of the gm and gds are generally known [144].
The zero z2 is unaffected. until it cancels the zero z1. the scaling of W4 and L4 does not affect its value. resulting in the behavior presented in Fig. ds2 ds1 The scaling of W2 and L2 affects Zu . The scaling of W3 and L3 in the 1cascode case of Fig. The zero z2 is moved down in frequency due to increasing C3 . Therefore. but its effect on zu is negligible.63). 6. as presented in Fig. (6.45 affects Zu as presented . (6.47 presents the behavior of Zu when both W4 and L4 are scaled by the same factor varying from 1 to 5. Frequency dependency of the impedance Zu can be analyzed with MATLAB.62) is moved towards lower frequencies due to increasing C3 . until it cancels the zero z1. Further increasing the dimensions makes pole p dominant. (6. resulting in Eq. The pole p2 in Eq. Scaling up W3 and L3 increases C2 .50. Further increasing the dimensions makes the pole p dominant. 6. pole p2 in Eq. C2 as long as ggm2gds1 ≪ gC1 . as presented in Fig.49. It can be observed that as the dimensions are increased. The pole p2 in Eq.47 Scaling W4 and L4 in 2cascode case. (6. (6.6.63).5 Effects of output impedance variation 99 Scaling of W4 and L4. resulting in Eq.62) is moved towards lower frequencies due to decreasing gds2 until it cancels the zero z1. 2 cascodes 180 Scale 1 Scale 2 Scale 3 Scale 4 Scale 5 160 140 20log10(Zu/Zl) 120 100 80 60 40 10 1 10 2 10 3 10 10 10 Frequency [Hz] 4 5 6 10 7 10 8 10 9 Figure 6. 6.48.62) is moved towards lower frequencies due to the decrease of gds3 . The scaling of W3 and L3 affects Zu .63). 6. (6. If C3 is determined by the routing. Fig. it really does not matter whether C2 is constant or not. 6. Further increasing the dimensions makes the pole p dominant resulting in Eq. The zero z2 is unaffected.
49 Scaling W3 and L3 in 2cascode case.48 Scaling W4 and L4 in 2cascode case with constant C3 . Scaling of W3 and L3. .100 Currentsteering digitaltoanalog converter design Scaling of W4 and L4. 2 cascodes 180 Scale 1 Scale 2 Scale 3 Scale 4 Scale 5 160 140 20log10(Zu/Zl) 120 100 80 60 40 10 1 10 2 10 3 10 10 10 Frequency [Hz] 4 5 6 10 7 10 8 10 9 Figure 6. 2 cascodes 180 Scale 1 Scale 2 Scale 3 Scale 4 Scale 5 160 140 20log10(Zu/Zl) 120 100 80 60 40 10 1 10 2 10 3 10 10 10 Frequency [Hz] 4 5 6 10 7 10 8 10 9 Figure 6.
The effects of the cascode transistors and scaling of the transistor dimensions can be concluded as follows. 2 cascodes 180 Scale 1 Scale 2 Scale 3 Scale 4 Scale 5 160 140 20log10(Zu/Zl) 120 100 80 60 40 10 1 10 2 10 3 10 10 10 Frequency [Hz] 4 5 6 10 7 10 8 10 9 Figure 6. (6. (6. 6. in general. 6. Since C1 is the only capacitance present and determined by routing.5 Effects of output impedance variation 101 Scaling of W2 and L2. in Fig. Further increasing the dimensions makes the pole p dominant.53. The zero z2 is moved down in frequency due to increasing C2 . The effect of scaling W2 and L2 is as presented in Fig. resulting in Eq.63). nor is the zero z. increase the output impedance. (6.69) is moved to lower frequencies due to decreasing of gds2 . (6. (6. Increasing the dimensions only scales the gain and thus increases the output impedance. it is beneﬁcial to increase the impedance by scaling gm . The pole p1 in Eq. Adding cascode transistors will. Output impedance at higher frequencies is absolutely limited by Eqs.51. 6.6. The pole p2 in Eq.70). once the dominant pole is not caused by the routing capacitance C1 . If C2 is determined by the routing.76) is not affected. until it cancels the zero z1. the pole p in Eq.50 Scaling W2 and L2 in 2cascode case.48. In any case. The zero z2 remains unaffected.70).70). (6.52. (6. Further increasing the dimensions makes the pole p dominant.76). The behavior of the output impedance of a current source without cascode transistors is presented in Fig. and (6. resulting in Eq. the scaling of W3 and L3 does not affect its value. and results in behavior similar to that shown in Fig. 6.69) is moved towards lower frequencies due to increasing C2 until it cancels the zero z1.
52 Scaling W2 and L2 in 1cascode case. 1 cascodes 180 Scale 1 Scale 2 Scale 3 Scale 4 Scale 5 160 140 20log10(Zu/Zl) 120 100 80 60 40 10 1 10 2 10 3 10 10 10 Frequency [Hz] 4 5 6 10 7 10 8 10 9 Figure 6.102 Currentsteering digitaltoanalog converter design Scaling of W3 and L3. 2 cascodes 180 Scale 1 Scale 2 Scale 3 Scale 4 Scale 5 160 140 20log10(Zu/Zl) 120 100 80 60 40 10 1 10 2 10 3 10 10 10 Frequency [Hz] 4 5 6 10 7 10 8 10 9 Figure 6. Scaling of W2 and L2.51 Scaling W3 and L3 in 1cascode case. .
however. no cascodes 180 Scale 1 Scale 2 Scale 3 Scale 4 Scale 5 160 140 20log10(Zu/Zl) 120 100 80 60 40 10 1 10 2 10 3 10 10 10 Frequency [Hz] 4 5 6 10 7 10 8 10 9 Figure 6. whereas scaling the cascodes seems to increase the impedance on the frequencies below the second pole. in this case.53 Current source with one cascode transistor. and gds of the switch. . the impedance on the lower frequencies can be further boosted by increasing the size of the cascode transistors if the pole due to the capacitor at the source node of the switch is not dominant. After that. since it would affect the operating point and drop the transistors out of the saturation.1. the large transistor would not reduce the switching speed. This kind of structure is used in the prototype described in Section 7. The impedance can also be increased by scaling only W of transistors. it would be probably beneﬁcial to use either transistor M2 or M3 as a switch and place additional cascodes above them. It should be noticed that it is not possible to increase L. From the output impedance pointofview. As a rule of thumb. the impedance should be increased ﬁrst by maximizing the gain of the switch (the topmost transistor) within the limits set by the driving capability of the switch driver and capacitive coupling from the switch gates. the impedance is more effectively increased if L is also scaled. since it increases the impedance at all frequencies.5 Effects of output impedance variation 103 Scaling of W2 and L2.6.
6. the conversion from the discretetime to continuoustime domain is analyzed by presenting the D/A converter as a system consisting of several subsystems each providing a response to the digital discretetime excitation signal. forming a sampledandheld nonreturntozero (NRZ) type output signal (Fig. An ideal D/A converter can be modeled with only one subsystem h1 (t). (6. (6. (6.87) A system diagram of a D/A converter is presented in Fig.55).84) in which Ts is the sampling interval.88) . Sampling of signal Xc (t) with the sampling signal S (t) results in a continuoustime model of the sampled signal x (t) = x (nTs ) = x (n) = xc (t) which has a spectrum X ( f ) = Fs ∞ n=−∞ ∑ δ (t − nTs ) . 6.54. The sampleandhold impulse response of the subsystem is deﬁned as h1 (t) = u (t) − u (t − τ) . which usually has the impulse response of a unit pulse of length Ts (τ = Ts ). In this section. The discretetime excitation signal can be modeled as a continuoustime signal sampled with a sequence of Dirac’s delta impulses (the effect of the quantization is not considered here) s (t) = s (nTs ) = s (n) = n=−∞ ∑ ∞ δ (t − nTs ) . the static nonlinearities were discussed and it was stated that INL sets the limit of the linearity of the converter. the signal is a train of impulses with certain values without any other nonideality but quantization noise. (6. When the signal is fed to the D/A converter. Observations on the nonidealities generated due to conversion are listed at the end of the section.to continuoustime domain In the digital domain. Typical subsystem impulse responses and their Fourier transforms are presented in Appendix D. In previous sections. (6. The time domain sampling signal has an frequency domain equivalent of S ( f ) = Fs n=−∞ ∑ ∞ δ ( f − nFs ) .86) n=−∞ ∑ ∞ X ( f − nFs ) .85) in which Fs is the sampling frequency. the converter adds nonidealities to the signal while converting it to the analog form.104 Currentsteering digitaltoanalog converter design 6.6 From discrete.
to continuoustime domain 105 h 1(t) y 1(t) x(n) f2(x(t)) w2(t) h 2(t) y 2(t) y(t) fn(x(t)) wn(t) h n(t) y n(t) Figure 6.54 System diagram of the D/A converter. .6. X(n) Y(t) n t τ Y(t) X(n) n Ts t Figure 6.6 From discrete.55 Sampleand hold response of the D/A converter.
90) −∞ ∑ x (nTs ) (u (t − nTs ) − u (t − nTs − τ)) . Ts π f τ n=−∞ which can be presented in the frequency domain as Y1 ( f ) = (6. models the ﬁnite rise/fall time during the transition (Fig. τ sin (π f τ) ∞ ∑ X ( f − nFs ) .89) If τ = Ts . The effect of the ﬁnite rise and fall times can be included in the model by adding a subsystem h2 (t) which provides an impulse response. 6.56). One of the simplest nonidealities to be included in the converter model is the effect of the ﬁnite rise and fall times and their asymmetry. there may exist several subsystems that may or may not provide nonlinearity to the output signal.95) . together with the sampleandhold impulse response of h1 (t). The sampleandhold system has a frequency response H1 ( f ) = τ sin (π f τ) . respectively. Tf − 1 (6. which.94) (6. The Fourier transforms of hr and h f are e− jωTr − 1 − 1 1 − ω2 Tr jω e− jωT f − 1 − 1 1 Hf ( f ) = − 2T ω f jω Hr ( f ) = (6. The response y1 (t) of the subsystem h1 (t) to excitation signal X (t) can now be determined as a convolution of the input and the impulse response y1 (t) = x (t) ⊗ h1 (t) = = Z ∞ −∞ ∞ x (t) h1 (t − τ) dt (6.106 Currentsteering digitaltoanalog converter design in which τ is the hold time.92) (6. πfτ (6.93) in which Tr and T f are the rise and fall time.91) In addition to the sampleandhold subsystem. The impulse responses corresponding to the linear rising and falling transitions can be written as hr (t) = h f (t) = t (u (t) − u (t − Tr )) Tr − 1 t (u (t) − u (t − T f )) . the system is an NRZ sample and hold.
The effect of the ﬁnite transition time can be modeled as follows. 2 (6. y2 (t) = w2 (t) ⊗ hr (t) . (6.97) n=−∞ ∑ ∞ X ( f − nFs ) . The effect of the difference of the rise and fall can be determined by decomposing the response of the subsystem h2 as follows.6. (6.to continuoustime domain 107 h 1(t) t h 2(t) t Figure 6.99) .96) in which w2 (t) is the discretetime derivative of the input signal w2 (t) = (xc (t) − xc (t − Ts )) The Fourier transform of w2 (t) is W2 ( f ) = 1 − e− 2π f Fs n=−∞ ∑ ∞ δ (t − nTs ) . corresponding to the Fourier transform of the continuoustime derivative of the signal xc (t) .6 From discrete. The average response common for both the rising and falling edges can be deﬁned as h2a (t) = hr (t) + h f (t) . w2 (t) ≥ 0 w2 (t) < 0 (6.56 Modeling the transition with subsystem h2 (t).98) which approaches jωX (F)as Fs approaches inﬁnity. w2 (t) ⊗ h f (t) .
108 Currentsteering digitaltoanalog converter design resulting in average transition response y2a (t) = w2 (t) ⊗ h2c (t) . the spectrum of w2b can be computed by using Eqs.103) and (6. (D. 2) Transitions can be modeled with a subsystem with discretetime derivative as an excitation signal.19) resulting in W2b ( f ) = A 1 − e j2π f0 Fs n=−∞ k=−∞. observing the glitches at the output of the converter does not necessarily give any information about the linearity of the converter. πk (6. (D. Differentiation is a linear operation and therefore ﬁnite transition speed does not generate distortion if the rising and falling transitions are symmetrical. .104) From Eq.100) The difference in the rise times can be included by adding a subsystem having an impulse response h2b (t) = with excitation signal w2b (t) = xc (t) − xc (t − Ts ) = w2 (t ) .104). the following observations are made: 1) The shape of the impulse response of a subsystem does not introduce any nonlinearity as long as it is independent from the excitation signal. When the transition shapes of the converter output are known.7). (6.104).101) n=−∞ ∑ ∞ δ (t − nTs ) (6. and (D. (6. the amount of distortion due to transition asymmetry can be easily computed with Eqs. This means that glitches at the output do no harm as long as they are a part of the signal independent impulse response of the subsystem.102) For the sine signal. (D. (6.odd ∑ ∞ ∑ ∞ 1 (δ ( f − (k + 1) fo − nFs ) − δ ( f − (k − 1) fo − nFs )) . it can be clearly seen that the absolute value of a sine signal contains evenorder harmonic components. Therefore. As a conclusion.6).8). (6.103) hr (t) − h f (t) 2 (6. resulting in response due to differences between rise and fall times y2b (t) = w2b (n) ⊗ h2b (t) .
7)). Absolute value is a nonlinear even function.7 Sampling jitter During the past few years. a jitter model for a fully thermometercoded D/A converter is developed. Total power of the harmonic component is deﬁned by the shapes of transitions according to Eq. Some sources of jitter in currentsteering D/A converters are identiﬁed and analyzed by design examples. (6. Special attention has been paid on timing and jitter issues in the design reported in [146]. In the following sections. The importance of the static timing mismatch has been demonstrated by Chen et al. Thermometer coding is chosen because it simpliﬁes the computation while not resulting in signiﬁcant inaccuracies. a brief introduction to the relations of the jitter on SNR of the converter is given. introducing evenorder harmonics.7. (D. . the performance is usually dominated by the thermometer coded part. [148]. a high oversampling ratio has to be used in order to be able to model the jitter.7 Sampling jitter 109 3) Asymmetry in transitionrelated nonidealities can be modeled with a subsystem with an absolute value of the discretetime derivative of the input signal as an excitation signal. resulting in increased distortion as the signal frequency increases. due to the rapid increase of the sampling rates. However. In this section. the amplitude of the derivative is linearly dependent on the signal frequency (Eq. as can be seen later in Section 6. including jitter. the effect of the subsystems for the binary weighted part should be analyzed on a per switch basis. and the reduction of the data dependent clock load (which is a source of jitter) was mentioned by Schoﬁeld et al. It is demonstrated by simulations how certain types of timing uncertainty are mapped to the output signal of a D/A converter. [145].104). as demonstrated in the case of the sine signal in Eq. Jitter analysis for the binaryweighted part has to be performed on a per switch basis and would result in very large signal matrices. Also. This holds for all transitionrelated nonidealities. 4) With sinusoidal signals. [149]. because. (6.103). since the effect of timing inaccuracy of the 1 1 binary weighted LSB bits is typically the order of 64 to 16 compared to the effect of thermometercoded MSB bits (6 to 4 thermometercoded MSB bits). various analyzes of timing and jitter have been published [147]. timing has become an important issue in the design of currentsteering D/A converters. in simulations. 5) As the converters are usually segmented.6. 6. [139].
and w (nT ) is the value of the timingjitter signal at the time instant nT (Fig.105) and Eq. (6. The output signal of a nonreturntozero (NRZ) D/A converter with sampling jitter can be deﬁned as the sum of the ideal sampledandheld signal and the timingjitterinduced error signal (Eq. 6. Eq.109) If a is small. For simplicity. (6. thus limiting SFDR. it is assumed here that the rise time of the signal is zero. u (t) is the unit step function x (nT ) is the digital discretetime input of a converter. (6.57).105) −u (t − (n + 1) T )] + e (t) .107) = n=−∞ ∑ e− jωw(nT ) − 1 e− jωnT jω . e (t) = ∆x (n) g (t) = n=−∞ ∑ ∞ [x (nT ) − x ((n − 1) T )] (6. 6.7. A block diagram of the jitter model is presented in Fig. The effect of the nonzero rise time is analyzed later in this section.106)) y (t) = n=−∞ ∑ ∞ x (nT ) [u (t − nT ) (6. in which T is the sampling interval.109 can be approximated with the Taylorseries expansion as G ( f ) ≈ Fs −a (σ ( f + f1 + nFs ) − σ ( f − f1 + nFs )) . (6.58 The effect of jitter on the output signal of the converter can be determined by computing the spectrum of the jitter signal g (t) as G( f ) = n=−∞ nT +w(n) ∑ ∞ ∞ Z ∞ e− jωt dt − Z ∞ nT e− jωt dt (6. 6.108) The spectrum of the error signal g (t) resulting from the sinusoidal jitter signal w (n) = a sin (ω1 nT ) is then G( f ) = n=−∞ ∑ ∞ e− jωa sin(ω1 nT ) − 1 e− jωnT jω .106) × [u (t − nT − w (nT ))) − u (t − nT )].1 Effects of sinusoidal timing jitter The jitter analysis in this book concentrates on the sinusoidal jitter signals because they are most likely to produce spurious or harmonic tones to the output of a converter.110 Currentsteering digitaltoanalog converter design 6.110) . n=−∞ j2 ∑ ∞ (6.
6.7 Sampling jitter 111 y(t) Ideal Actual ∆ x(n)=x(n)−x(n−1) w(n) g(t)=u(t−nT−w(n))−u(t−nT) e(t) Figure 6.57 Components of the output y (t). .
w (n) = 0. I p (M) σ ( f ± fk − p f1 − q fs )(6. Ak is the amplitude of the signal and its harmonic components and I p (M) is a pth order modiﬁed Bessel function of the 1st kind and σE is the standard deviation of the Gaussian noise.58 Block diagram of the jitter model. (6.114) (6. (6. It can be observed that. Fig.59 represents the eight ﬁrst pulses of the jitter error signal of g (t) = u (t − nT − w (n)) − u (t − nT ) .112) ω1 T 2 . Further analysis of the effects of jitter are made by simulations in order to gain some insight into the jitter behavior. as predicted by Eq.188Fs . indicating that the energy of the jitter is mainly concentrated on the frequency of the jitter signal. in which the power of the signal g (t) is presented relative to the power of sinusoid sin (ωnT ). The spectrum of g (t) with Tr = 0 is presented in Fig. 6.113) C ( f )2 = e−ω M = 8π2 f 2 σ2 A2 E 1 (2N − 1) where C ( f ) is the Fourier transform of the autocorrelation function of jitter. 6. (6. An analytical solution for the power spectrum of sinusoidal signals with the presence of sinusoidal jitter and Gaussian noise is presented in[150].60. T being the sampling interval. in the frequency range 0 to Fs .111) 4 p. and is given as S(f) = C ( f )2 2 σ2 E ∑ ∑ (π f T )2 sin A2 sin2 (π f T ) k .115) where the jitter signal w (n) has the frequency of 0.odd (6. the dominant frequency component is at 2 the frequency 0.110). 2 .188n) . It may also be observed that a signiﬁcant amount of energy lies at frequencies higher than Fs .q k=1.01T .01T sin (2π0.112 Currentsteering digitaltoanalog converter design Sample & Hold x(n) y(t) D −1 w(n) Time shift Transition Error pulse Figure 6.188Fs and amplitude of 0.
. Tr = 0.60 Spectrum of error pulse signal g (t).7 Sampling jitter 113 Error pulse sequence 1 Tr=0 0.4 0.2 −0.8 −1 0 1 2 3 4 5 Time [t/T] 6 7 8 9 Figure 6.6 −0.4 −0.6 0.2 g(t) 0 −0.6.8 0. Spectrum of jitter−generated error pulses 0 Tr=0 −20 Relative Power [dBc] −40 −60 −80 −100 −120 0 1 2 3 Relative Frequency [Fs] 4 5 Figure 6.59 Error pulse signal g (t).
as the rise time increases. 6.06 0 1 2 3 4 5 Time [t/T] 6 7 8 9 Figure 6. the energy at the higher frequencies is reduced. As the rise time increases. This is veriﬁed by simulations. 6. in the case when SFDR is determined by the jitter. 6. The signaltoerror power ratio is computed from the timedomain signal.06 Tr=0. SFDR can neither be . which represents the signaltoerror power ratio and SFDR as a function of rise time.04 −0. It is obvious that. because of the capacitive load at the output of the converter. and the result is presented 2 in Fig. it effects the duration and amplitude of the g (t) according to g (t) = t − nT − Tr − w (n) t − nT − w (n) u (t − nT − w (n)) − u (t − nT ) Tr Tr t − nT − Tr t − nT u (t − nT ) + u (t − nT − Tr) .8T 0. Spectra of error pulses under various risetime conditions are presented in Figs.62 and 6.61 Eight ﬁrst pulses of g (t) with various Tr . for example. (6.63.114 Currentsteering digitaltoanalog converter design Effect of the rise time 0.115).116) − Tr Tr The effect of ﬁnite rise and fall time on the timedomain error pulses can be seen from Fig.4T Tr=0.63. resulting in reduced total jitter energy. whereas energy in the frequency range of 0 to Fs is barely affected.02 −0. Simulation results indicate that.2T Tr=0. whereas SFDR is calculated from spectral components from 0 to Fs /2. w (n) is still deﬁned by Eq. It can be observed that the shape of the error pulse is an isosceles trapezoid with duration and amplitude dependent on w (n).02 g(t) 0 −0.61. (6.04 0.
63 Spectrum of g (t) with Tr = 0.8Ts −20 Relative Power [dBc] −40 −60 −80 −100 −120 0 1 2 3 Relative Frequency [Fs] 4 5 Figure 6.4Ts −20 Relative Power [dBc] −40 −60 −80 −100 −120 0 1 2 3 Relative Frequency [Fs] 4 5 Figure 6.4T . .62 Spectrum of g (t) with Tr = 0.6.8T .7 Sampling jitter 115 Spectrum of jitter−generated error pulses 0 Tr=0. Spectrum of jitter−generated error pulses 0 Tr=0.
6.8 0. the derivation for the jitter energy on a certain frequency band from −Fb to Fb resulting in SNR for a single sinusoid at the frequency Fsig sampled with the rate Fs . which has secondorder dependency on the input signal as x (nT ) = Q [sin (2π f nT )] (6. 6.2 Distortion due to signaldependent jitter Fig. 6.64 Signaltoerror power ratio and SFDR as a function of rise time.117) In the case of returntozero (RZ) type of signals. since shortening the signal pulse reduces signal energy linearly.2 0. is presented in Appendix C. SNR (Fb ) ≈ Fs2 2 4π2 Fsig Fb σ2 w (6. For Gaussian jitter.6 Relative Rise Time 0.65. Typical behavior of SFDR as a function of the jitter magnitude of sinusoidal jitter w (n) is presented in Fig. whereas the amount of jitter error energy remains constant.118) .4 0. meaning that SFDR is determined by only the standard deviation of w (n). jitterinduced SFDR decreases. increased by altering the rise time nor does there exist an optimal rise time in the SFDR sense.116 Currentsteering digitaltoanalog converter design Effect of the rise time 45 SFDR Signal−to−Error Power Ratio 40 Relative Power [dBc] 35 30 25 20 15 0 0.66 represents the spectra of a quantized sinusoidal signal x (nT ) and a jitter signal w (nT ).5 0.3 0.7 0.1 0.9 Figure 6.7.
w (n) = Kx (nT ) − x ((n − 1) T ) 2 . (6.119) is chosen to be dependent on the absolute value of the discrete time derivative of the input signal since it reﬂects the physical origin of the jitter.119) (6. Clock loading.119)). from which the ﬁrst one is usually the dominant source of jitter. (6. which is usually dependent on the number of changing thermometercoded bits.6. It can be observed that due to multiplication by the discrete time derivative (Eq. often the jitter is caused by activity of the circuitry.67. Examples of these two jitter sources .7 Sampling jitter 117 Jitter Effects 10 0 −10 Relative Power [dBc] −20 −30 −40 −50 −60 −70 −80 SFDR Jitter−to−signal power ratio 10 −3 10 Relative RMS jitter [T] −2 10 −1 Figure 6. In Fig. if not taken into account. (6. the spectrum of e (t) in the case of second order jitter w (nT ) is presented.120) w (n) in Eq. the resulting distortion is of odd order. The signaldependent jitter can originate from powerrail interference of the switch driver circuitry of the converter or from the digital circuitry due to the substrate coupling.65 Signaltoerror power ratio and SFDR as a function of jitter magnitude. 6.01T. may also result in jitter. As a conclusion it can be stated that evenorder dependency of the w (nT ) on the input signal x (nT ) results in oddorder distortion of the output signal y (t) and vice versa. in which K is chosen so that max K (x (nT ) − x ((n − 1) T )) 2 = 0.
2 0.2 0. Power spectrum 0 E(f) −20 Relative Power [dBc] −40 −60 −80 −100 −120 0 0.4 0.67 Spectrum of the error signal e (t) caused by second order jitter signal w (n).66 Spectra of the sinusoidal signal x (nT ) and second order jitter signal.8 1 Figure 6.118 Currentsteering digitaltoanalog converter design Power spectrum 0 X(f) W(f)/T −20 Relative Power [dBc] −40 −60 −80 −100 −120 0 0. .8 1 Figure 6.4 0.6 Relative Frequency [Fs] 0.6 Relative Frequency [Fs] 0.
the jitter extracted from the simulation is applied to the model described by Eqs.35 µm SiGe BiCMOS process. the jitter was extracted from the clock signal of the transistorlevel simulation. Distortion caused by codedependent clock loading can be reduced by. odd order distortion may be expected at the output as in Fig. in the cases in which relatively accurate synchronization is required. It can be observed that the jitter seems to be correlated with the output signal.68. for example.71 and 6.72. 6. This assumption can be validated by simulations as follows. adding a small buffer to drive the clock pin of each of the switch driver ﬂipﬂops (Fig. and that the dependency is secondorder.70.105) and (6.69 is due to jitter.6. In order to validate the assumption that the thirdorder distortion in Fig. 6. It can be observed that the spectral behavior due to jitter follows quite accurately the spectrum obtained from the transistorlevel simulation. 6. 6. and thus dependent on the input code.3 Jitter due to codedependent clock load Sometimes.68). This is because the load of the clock driver is dependent on the internal states of the switch driver ﬂipﬂops. and therefore it is justiﬁed to say that the distortion is due to the codedependent jitter. which are dependent on the data that is fed to them.73). As stated before.106). It can be assumed that codedependent clock load causes codedependent jitter. Fig. If the synchronizing elements driven are the latch/ﬂipﬂop stages of the switchdriver stage of the D/A converter.69 represents the output spectrum of a 16bit currentsteering D/A converter with the clock driving scheme of Fig. this may result in distortion of the output signal. 6. In order to verify the origin of the distortion to be jitter.7. 6. 6.7 Sampling jitter 119 D CLK D Figure 6. This spectrum is the result of the transistorlevel simulation of the converter implemented in a 0.68 Buffering of the switch drivers with single buffer. in the case of evenorder jitter. buffer (Fig. are given in following sections. In Fig.69. The simulation results for the D/A converter with modiﬁed clock buffering are . 6. the clock pins of the synchronizing elements may be driven by one. usually very large. the output signal and the relative timing error of the clock signal are presented. (6. The spectra of x (nT ) and w (n) from the jittermodel simulations are presented in Figs. 6.
5 x 10 4 −7 Figure 6.5 Vout [V] 0 −0.5 1 1. 4 Timing Error [T] 2 0 −2 x 10 −3 Relative variation of sampling period −4 0 1 0.5 1 1.5 −1 0 0.5 3 3.5 1 1.5 x 10 4 −7 0.69 Simulated spectrum obtained from the transistorlevel simulation.70 Relative timing error and the output signal of a 16bit D/A converter.5 2 2. .5 2 Time [s] 2.5 2 Time [s] Signal 2.5 3 3.120 Currentsteering digitaltoanalog converter design Power spectrum 0 −20 Relative Power [dBc] −40 −60 −80 −100 −120 0 0.5 x 10 4 8 Figure 6.5 Frequency [Hz] 3 3.
72 Spectra of the input signal x (nT ) and error signal e (t).4 0.2 0.8 1 Figure 6.8 1 Figure 6.6.6 Relative Frequency [Fs] 0. .2 0.71 Spectra of the input signal x (nT ) and w (nT ).7 Sampling jitter 121 Power spectrum 0 X(f) W(f)/T −20 Relative Power [dBc] −40 −60 −80 −100 −120 0 0.4 0. Power spectrum 0 X(f) E(f) −20 Relative Power [dBc] −40 −60 −80 −100 −120 0 0.6 Relative Frequency [Fs] 0.
6.5 1 1.74 Simulated spectrum of the D/A converter with modiﬁed clock buffering. in order to extract the proper jitter signal from the transistorlevel simulations. which may result in jitter. It can be observed that the jitterinduced distortion is effectively reduced with the altered buffering scheme. Power spectrum 0 −20 Relative Power [dBc] −40 −60 −80 −100 −120 0 0.5 2 2. Therefore.5 x 10 4 8 Figure 6.4 Jitter due to powerrail interference It can be assumed that the parasitic resistance of the power supply rails of the switch driver circuitry may cause codedependent interference during the transitions of the switch driving signals.122 Currentsteering digitaltoanalog converter design D CLK D Figure 6.75. the jitter is extracted from the switch driver signals instead of the clock signal. In order to reduce the code dependency of the supplyrail interference. presented in Figs. 6. a transition of the switch driver signal may be .5 Frequency [Hz] 3 3. The interference on the supply rails affects not only the clock signal (in those cases where the clock buffers share the same supply rails).7.73 Modiﬁed clock buffering. but also the switch driving signals.74 and 6.
6.6.7 Sampling jitter 123 Power spectrum 0 X(f) E(f) −20 Relative Power [dBc] −40 −60 −80 −100 −120 0 0.77 and 6. beyond the scope of this analysis. however. The beneﬁts of using the differentialquad switching scheme are discussed in more detail in Section 7. It can be observed that resistive supply rails can generate an excessive amount of jitter even though the differentialquad switching scheme [151] is used to reduce the code dependency of the power supply interference. which would be the case with a distributed resistance model. when a transition occurs.2. Two designrelated examples of the jitterinduced distortion are given by analyzing the jitter signal extracted from transistorlevel simu . ensuring that there is only one conducting transistor at that time instant. 6. the switch is opened before the other switch is closed.75 Effect of the jitter with modiﬁed clock buffering. The positiondependency of the jitter would further exacerbate the performance of the D/A converter.78 represent the reconstruction of the output spectrum with the mathematical jitter model. the effects of the jitter on the spectral performance are demonstrated by using a mathematical jitter model. and Figs. Switch drivers are designed so that. A lumped resistor model is used for the supplyrail resistance in order to avoid distortion being dependent on the position of the switch driver. Fig. Jitter is extracted by monitoring the time instants when Vgs − VT of the closing transistor is zero. it is. In this section. ensured on every clock cycle by using the differentialquad switching scheme [151].8 1 Figure 6.76 represents the output spectrum of the converter obtained from the transistorlevel simulation.2 0.4.6 Relative Frequency [Fs] 0.4 0.
77 Spectra of the input signal x (nT ) and w (n) due to supply rail interference.6 Relative Frequency [Fs] 0.5 Frequency [Hz] 3 3.5 x 10 4 8 Figure 6. Power spectrum 0 X(f) W(f)/T −20 Relative Power [dBc] −40 −60 −80 −100 −120 0 0.2 0.4 0.8 1 Figure 6.5 1 1.5 2 2. .76 Simulated output spectrum of the D/A converter with resistive supply rails.124 Currentsteering digitaltoanalog converter design Power spectrum 0 −20 Relative Power [dBc] −40 −60 −80 −100 −120 0 0.
SFDR on the Nyquist band increases 6 dB due to the fact that increasing jitter amplitude transfers jitter energy from higher to lower frequencies.6. However.8 1 Figure 6. the increase in transition time mainly reduces the frequency component above thus indicating that SFDR due to jitter can not be optimized by altering the transition times. Even though the total jittertosignal energy ratio is affected by the transition of the signal. Fs 2 .6 Relative Frequency [Fs] 0.2 0. This model can be used to determine whether the distortion at the output of the converter is due to jitter or not. It is demonstrated by simulations that the jittertosignal power ratio increases 3 dB if the amplitude of the jitter is doubled. As a summary.7 Sampling jitter 125 Power spectrum 0 X(f) E(f) −20 Relative Power [dBc] −40 −60 −80 −100 −120 0 0.78 Effect of the jitter due to supply rail interference. the following observations can be made of these analyzes: spectral components due to jitter are deﬁned by the discretetime derivative of the input signal and the jitter signal w (n) The jitter signal that has an oddorder dependency on the output signal of the converter will generate evenorder harmonics due to multiplication by the discretetime derivative of the signal and vice versa.4 0. lations with the developed mathematical model.
introducing the ”hierarchical symmetrical switching” scheme (Fig. 6. [155]. [157] .2 is also discussed since it differs slightly from the previously published methods. which is stated to have a linear dependency on the distance between devices [125]. the cancellation of the gradient effect is based purely on the geometrical aspects without any knowledge of the relations between linear and quadratic (odd. if the errors do not correlate. The methods can be divided in two categories. the quadratic errors ere accumulated. the current sources are selected in the order they appear in the matrix in such a manner that.8 Layout techniques for current source mismatch reduction In addition to random variation of the process parameters that was discussed in Section 6. [126].81). the gradient errors are an additional source of static nonlinearity. which is designed to reduce the effect of the quadratic error gradient. This method results in the accumulation of the error in both X and Y directions. There have been several proposals for the layout techniques (also called ”Switching schemes”) for the reduction of nonlinearity caused by process gradients. On the other hand. The simplest possible sequence for ordering the current sources is presented in Fig.81. then the ﬁrst source of the second row is selected and so on.and evenorder) gradients. [159]. [154]. These methods require a priori knowledge about the relations of the linear and quadratic gradients. however. In this ”sequential switching” scheme. The symmetrical switching scheme is further improved in [154]. which has been reported to have a quadratic behavior over the device matrix [152]. In heuristic methods [153]. 6.80. A symmetrical switching scheme ensures the cancellation of the linear gradient errors. the optimal switching sequence) in the INL sense is evaluated by numerical methods. after all the sources in the ﬁrst row are selected.79. The ﬁrst improvement is the ”symmetrical switching” presented in [153]. The layout method used in the prototype circuit presented in Section 7. the switching order has no statistical effect on the INL. and die stress gradients. the switching sequence in X . The principle of symmetrical switching is presented in Fig. resulting in a large INL.126 Currentsteering digitaltoanalog converter design 6. 6. In the analytical methods presented in [158]. In the following paragraphs.3. the layout techniques are presented in the order of publication to demonstrate the evolution of the layout techniques. 6. The gradient errors are mainly due to the variation of the oxide thickness on the wafer. In Fig. [156]. The gradient errors have a signiﬁcant effect on the static linearity of the converter. since the error due to gradients correlate with each other and therefore the errors may accumulate. the optimal placement of the current sources (i.e. The effect of accumulation can be reduced by choosing the switching order so that the gradient errors of current sources corresponding to the subsequent code values cancel each other.
.8 Layout techniques for current source mismatch reduction 127 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 0 0 Figure 6.80 Symmetrical switching.79 Sequential switching.6. 0 0 0 7 5 3 1 2 4 6 8 1 2 3 4 5 6 7 8 0 0 0 Figure 6.
84). The solid lines represent gradient. 6. For simplicity it is assumed that the oddorder mismatch has only the ﬁrst order (linear) component and the evenorder 0 0 . 6. meaning that all the current sources on the row are selected before the row is changed. Let us begin with the plain current source matrix without any of the mirror symmetry presented in Fig.82. The effect of using mirror symmetric matrices can be analyzed in the following way. Mirroring is also exploited in [126]. however. [156]. dashed lines represent canceled gradient. and Y direction is ordered according to ”Type B” hierarchical symmetrical switching. 6. Hierarchical symmetrical switching is further improved in [155].128 Currentsteering digitaltoanalog converter design 6 2 1 5 7 3 4 8 7 3 1 5 6 2 4 8 0 0 Figure 6.83. The theory can be generalized as follows. This problem is avoided in [155] by using four identical current source matrices mirrored with respect to X and Y axis.81 Hierarchical symmetrical switching. The second (and even) order mismatch can be reduced by further splitting the unity current source and by using the mirror symmetric submatrices (Fig. All introduced switching schemes so far exploit ”RowColumn Decoding”. since the error builds up columnwise while the error in the direction of rows is canceled. does not necessarily cancel or reduce the second. Again. as in Fig. It is correctly stated in [155] that this results in an accumulation of the error.(and even) order gradient effects. direction is ordered according to ”Type A” hierarchical symmetrical switching. This kind of structure. It is well known that the linear (and oddorder) gradient can be canceled by using common centroid matrices of unity current source transistors. the dashed line represents the canceled gradient.
8 Layout techniques for current source mismatch reduction 129 Matrix dimension Figure 6. Matrix dimension Figure 6.6.82 Current source matrix with even and odd order error gradient. . Matrix dimension Figure 6.84 Reduction of second (and even order) error gradient by further splitting the matrix.83 Compensation of linear (and odd order) gradient with mirror symmetry.
121) the residual error can be written as E2 (x) = M (x − p1 ) x − (p2 + p1 ) . Gradients are modeled as Gx (x) = gx1 x cos (θ) + gx2 x2 .n and gy1 are the gain factor for linear and quadratic gradients in x and . This extreme has the value Ee1 = M (p1 − p2 ) (p2 − p1 ) .124) This linear mismatch is again canceled if the current source is further split and divided into the common centroid matrices that are mirror symmetric relative to the centerline of the original matrix. −1 ≤ y ≤ 1. 16 (6. (6. 2 (6. In addition. and the residual second order mismatch in Xdimension is deﬁned by the parabola with its extreme at the middle of the chip and zeros at the edges of the chip.126) that the ratio of these extreme values is Ee1 Re = Ee2 = 4. gx2 . Figure 6. 4 (6.123) The line that goes through the point (p1 . (6. the residual error in that dimension is divided by four. This is a parabola with zeros at p1 and p1 +p2 and the extreme at xe2 = 2 The extreme value is M (p2 − p1 ) (p1 − p2 ) Ee2 = . gx1 .124) is subtracted from Eq. (6. we may assume that any constant error has no effect.123) and Eq. Ee1 ) has the equation S11 (x) = M (p1 − p2 ) (x − p1 ) . −1 ≤ x ≤ 1 Gy (y) = gy1 y sin (θ) + gy2 y .127) (6.83. (6. After Eq. 6.122) which is exactly in the middle of the zero points. so every time the unity source is halved and mirrored in one dimension. gy1 . The equation for this parabola can be written as E1 (x) = M (x − p1 ) (x − p2 ) .126) It can be seen from Eq. 0) and (xe1 . 2 3p1 +p2 4 (6. 2 (6.85 represents the cancellation of linear and quadratic gradients by using mirror symmetry.130 Currentsteering digitaltoanalog converter design mismatch has only the secondorder component.125) = xe1 +p1 2 . (6. 2 (6.128) in which x and y ranges have been normalized to be ±1 at the matrix boundary. The linear dependency can be removed as in Fig. since it is the same for all the units.121) It has its extreme at xe1 = (p1 + p2 ) .
In [157]. Additional splitting further reduces the INL due to quadratic gradient by a factor of 4. The effectiveness of the mirror symmetry in removing the linear gradient can be clearly seen. 6. the plain ”sequential switching” scheme was used. and if these elements are arranged so that a current source has an element on every row and every column. it was presented that if the current sources are divided into 2 2 N elements. . To overcome this problem.8 Layout techniques for current source mismatch reduction 131 Cancellation of gradient effect with mirror symmetry 7 No mirroring Split to 4 Split to 16 6 5 MAX ABS INL [LSB] 4 3 2 1 0 0 50 100 150 200 250 Plane angle θ [deg] 300 350 Figure 6. and θ is the plane angle of the linear gradient.6. The principle of this switching scheme is to translate the positions of 22N elements to positions of unit current sources of 2N thermometercoded bits with a simple algorithm developed with numerical optimization to minimize the effect of the quadratic gradient. as calculated. The main shortcoming of this method is the large number of unit elements. the splitting of the current source into smaller units can be used to very effectively reduce the gradient error.85 Reduction of INL of 16 current sources with mirror symmetry. and the main advantage of this method is that it does not need any kind of a priori knowledge about the gradients. y direction. In the simulation result presented in Fig. The effect of the residual error can be further reduced by using some of the switching schemes discussed before. This algorithm seems to be a very promising solution for the gradient cancellation. In addition to mirror symmetry. a new switching scheme was developed for larger numbers of thermometercoded bits providing very promising results.85. both linear and quadratic errors are canceled.
On the other hand. 6.86. Let us call this an “”optimal sequence”. As mentioned earlier. The number sequences around the matrices indicate the order of selection and the numbers inside the matrices indicate the number of the source. and therefore it may become difﬁcult to ﬁnd the optimal sequences. 6.86 Reduction of INL with optimal rowcolumn sequencing. so suboptimal sequences have to be used.1 of sequences etc. as in the case of the 4x5 matrix of Fig. there are too few optimal sequences. It can be seen that in 4x4 case. i.86. This problem can be alleviated by applying optimal sequences in the both dimensions simultaneously (this kind of result is also obtained by applying the technique presented in [157]). If. since 2N cannot be presented as the product of relatively prime numbers.e. there is no problem if the number of rows and columns are relatively prime. for some reason. if the number of rows and columns are not relatively prime. the number of positions selectable with one sequence pair is deﬁned by the length of the longer sequence. the number of current sources (including biasing) is 2N in the matrix. such as in . A rather similar method was developed by the author and used in the prototype presented in this book. First. after which a new optimal sequence has to be selected as was done in the case of 4x4 matrix in Fig. This technique has at least two shortcomings. Two examples are given in Fig. The newly selected optimal sequence should also be valid in such a manner that alreadyoccupied positions are not selected again. the problem with the ”RowColumn Decoding” is the accumulation of the error in one dimension while it is canceled in the other. The principle of ﬁnding optimal sequences was presented in [159]. 6. It is possible to minimize the maximum value of accumulated linear error of the unit elements in dimension (X or X) by selecting them in certain order. Usually.132 Currentsteering digitaltoanalog converter design 3 3 2 2 1 3 2 4 3 1 4 2 3 1 4 2 1 3 2 4 7 3 1 1 4 4 4 4 1 1 2 2 3 3 4 2 1 5 3 3 4 1 12 11 5 9 15 2 6 19 7 11 15 3 9 17 1 14 2 4 12 16 20 8 5 13 1 14 12 8 10 16 4 6 10 18 2 Figure 6. The method is based on the ideas of switching sequences presented in [159].86. source number 1 is placed ﬁrst into the position indicated by numbers 1.
the key features and design methods of the recently published current steering D/A converters are brieﬂy introduced.6. The same holds for the sources of different weights. starting from the opposite corners of the matrix simultaneously.4 0.3. The ﬁlling of a row is started from side opposite the previous row was started. or due to including the LSB sources into the matrix. the case of digital calibration. the principle of symmetrical switching was introduced and used to alleviate the processgradientrelated mismatch of the current sources. Its effectiveness can be veriﬁed by comparing Fig. The basic principle is to ﬁll every other empty position. 6.6 0. Simulation results for this sequence in the case of 4x4 matrix is presented in Fig.87.2 0 0 50 100 150 200 250 Plane angle θ [deg] 300 350 Figure 6. the number of sources differ from 2 N .9 Survey of published D/A converters In this section. 6. . 6.88. Two examples are given in Fig.9 Survey of published D/A converters 133 Cancellation of gradient effect with mirror symmetry 1.87 INL and effect of splitting with developed switching sequence. the situation can be easier to handle. resulting in almost automatic cancellation of gradient errors. In [153]. The methods of the layout design of binaryweighted converters are seldom discussed in the papers. Due to the binary weighting.8 0. 6.85.87 to Fig. The ﬁgures of merit of the converters are listed in Table 6. 6.2 No mirroring Split to 4 Split to 16 1 MAX ABS INL [LSB] 0. the number of unit sources is large for currents of larger weight.
In [160]. a switch structure is introduced to improve the switch driver timing. the switching method was further improved from symmetrical switching to hierarchical symmetrical switching. and the segmentation level is optimized in order to optimize DNL. codedependent settling and timing skew between current sources. . The effect of segmentation is emphasized. and the estimates of the standard deviations of INL and DNL are given based on MonteCarlo simulations. The effect of linear and quadratic gradients are analyzed. In [161] the returntozero output stage is used to reduce the effect of glitches. the development of the switching schemes continued with four quadrant randomization technique. INL and DNL are analyzed as a function of the segmentation. a selftrimming D/A converter with a trackandattenuate output stage is presented.88 Two possible current source matrices for 4bit binary weighted D/A converter. The cascode current sources are also used. the switching sequence optimization is continued by the introduction of a hierarchical symmetrical switching scheme using common centroid matrices. Segmentation is mentioned as a technique for glitch reduction. In [155]. SFDR and area. and the error is measured with a Σ∆ analogtodigital converter (ADC) over the resistance in series with the current source transistor. In [162]. reduce the switching asymmetry and code dependent glitching at the output. A dynamic latch is used for the switch driver synchronization and the crossing point of the switch driver signals is optimized. Glitches due to switch driver feedthrough are minimized. It is mentioned that glitches that are linearly dependent on the code transition do not introduce distortion. the linearity errors due to current source mismatches are further optimized with the Q2 random walk switching scheme. Selftrimming is based on the error value stored on the gate capacitance of the current source. Linear and quadratic error gradients are discussed. Segmentation in two thermometercoded segments with different weights is also used. In [126]. In [158].134 Currentsteering digitaltoanalog converter design 3 2 2 1 3 3 3 0 1 2 3 2 3 D 3 D 3 1 3 2 3 2 3 0 1 3 D 2 3 D 3 M 3 2 M 3 Figure 6. In [154]. A Gaussian distribution is used as an approximation for INL. INL.
A triple centroid switching scheme (16 units in one current source + mirror symmetry) is used to improve the static matching. the importance of the switching dynamics is emphasized. In [139]. In [168]. Also.6. which are divided into 16 current source arrays in order to reduce the effect of process gradients. The effect of output impedance is taken into account. which are adjusted with an additional calibration DAC. and thus the charge ﬂow from the supply lines. The static nonlinearity is measured with a 16bit Σ∆ calibration ADC. The effect of the nonlinear capacitance at the source node of the switches is emphasized. as in the previous design. attention is paid to the reduction of timing errors. An RZ stage is used at the output to improve the dynamic performance. The dynamic performance is also compared to case in which the RZstage is disabled. An additional calibration DAC is used to adjust the currents of the MSB sources. In addition. indicating that with this particular converter. better highfrequency operation is obtained with the RZ output stage. 7bit segmentation is used in order to improve dynamic performance and MSB current sources are composed of 16 unit cells. In [167]. and the timing inaccuracies in switching are reduced by using a local voltage generator that follows the source voltage of the switches. dynamic element matching is used to average the current source array errors. values are stored in the memory and addressed with the 6 MSB bits. a successive approximation calibration routine is used to trim the MSB current sources to 18b accuracy. the static accuracy is improved by calibration based on trimmable current sources. In [164]. the effort is put on the switch driver optimization and signal symmetry in order to achieve highspeed operation. trimming of the ﬂoatinggate current source transistors is used to improve the static nonlinearity. Switch driver timing is also emphasized. In [165]. A doublecentroid switching scheme (mirror symmetry) is used to reduce gradient effects. a converter capable of 1 GS/s operation is presented. a differentialquad switching scheme [151] is applied in order to equalize the switching activity. capacitive current memory type of calibration is used to trim the MSB current sources. In [146]. a returntozero output stage is used to improve dynamic performance.9 Survey of published D/A converters 135 In [163]. and backgatebuffering (bulkbootstrapping of the switches) is used to reduce the effect of the nonlinear capacitance. and power supply and bias disturbances targeting the elimination of the nonlinearity instead of removing it . and the effort is put on the design of the highspeed switch driver. The differentialquad switching scheme is applied and kickback (variation of the source node voltage of the switch) is minimized with switchdriver crossingpoint control. In [138]. the static performance is improved with calibration. In [166]. In [137].
The timing of the switch drivers is equalized with a replica structure similar to as the prototype presented in Section 7.2. . Currentmode logic is used to reduce the supplyrail and substrate cross talk.136 Currentsteering digitaltoanalog converter design from the output.
3 Survey of published D/A converter implementations.18µm CMOS 0.5µm CMOS 0.35µm CMOS 0.6.2 @ 490 62 @ 125 64 @ 1 50 @ 63 73 @ 190 71 @ 120 60 60 60 90 43 90 67 260 60 220 @ @ @ @ @ Area [mm2 ] Power Comment [mW] 3.13µm CMOS 0.83 0. core area .42 13.18µm CMOS 0.35µm CMOS 0. Publication Process Bits Sampl.9 Survey of published D/A converters 137 Table 6.5µm CMOS 0.18µm CMOS 0.18µm CMOS 0.18µm CMOS 0.44 1.7 Power @100MS/s.78 8.25 0.44 400 53 Power @250MS/s.13 82 97 97 400 216 Core area RZmode.23 51 @ 240 40 @ 60 74 @ 8.18µm CMOS 0.0 1.5µm CMOS 0. core area 12 14 14 14 12 320 200 200 1400 500 0. [MHz] 8 10 16 10 12 14 14 14 10 80 70 40 500 300 100 150 100 1000 Miki [153] Nakamura [154] Mercer [160] Lin [126] Bastos [155] Bugeja1 [161] Van der Plas [158] Bugeja2 [162] Van den Bosch1 [164] Van den Bosch2 [163] Tiilikainen [137] Cong [138] Schoﬁeld [139] Hyde [165] O’Sullivan [166] Huang1 [167] Huang2 [167] Schafferer [168] Doris [146] 2µm CMOS 1µm CMOS 2µm BiCMOS 0.0 0.35 145 170 500 125 320 750 300 180 110 Core area SFDR @ 10MS/s 12 500 7. freq.5 61.35µm CMOS 0.25µm CMOS 0. core area NRZmode.6 3. core area 16 14 400 300 ? 0.25 1.25µm CMOS 0.14 102 14 14 100 180 1.1 20 16.2 14.10 11.0 6.18µm CMOS SFDR [dBc] @ [MHz] ? ? 80 @ 1.79 3.5 61 @ 5 72 @ 42.
.
Chapter 7
Prototypes and experimental results
In this chapter, the methods used in the WCDMA prototype circuit design are described and the measurement arrangements and the experimental results obtained from the fabricated transmitter chip are reported. The target of the design process was to advance our knowledge of the efﬁcient realization of the DSP algorithms, discover the system limitations set by the digitaltoanalog converter, learn more about the D/A converter design and apply the knowledge gained to the design of the IF DSP part of the transmitter to see how the different parameters affect the transmitter performance. The performance of the transmitter is characterized by EV M and ACLR.
7.1 Prototype of WCDMA transmitter
The principle of the designed WCDMA transmitter is presented in Fig. 7.1. The transmitter consists of pulse shaping ﬁltering and interpolator blocks for four independent I and Q data streams in order to alter the sampling rate from the input symbol rate to the sampling rate used in the CORDIC vectorrotationalgorithmbased quadrature modulators. After the modulation, the modulated carriers are summed and fed to the inverse SINC predistortion ﬁlter [169]. The purpose of the ﬁlter is to eliminate the SINC attenuation caused by the sampleandhold function of the D/A converter. Two constant scalers are used to maximize the signal dynamics before feeding it to the D/A converter. The values of the scalers are discovered with simulations. Finally, the data is fed to the D/A converter. A 14bit current steering architecture is chosen because of its capability in terms of highspeed operation and good static linearity. The design of
140
Pulse shaping I L Q L COS(Wt) SIN(Wt) −1 Quadrature Modulation COS(Wt)
Baseband DSP Baseband DSP Baseband DSP Baseband DSP
Prototypes and experimental results
Pulse shaping I L Q L
Quadrature Modulation COS(Wt)
SIN(Wt) −1 Analog IF COS(Wt) DAC
IF 2
RF
Pulse shaping
Quadrature Modulation COS(Wt)
Inverse Scaler SINC
Scaler
LO1
LO2
L
I SIN(Wt) −1
L
Q COS(Wt)
Pulse shaping I L Q L
Quadrature Modulation COS(Wt)
SIN(Wt) −1
COS(Wt)
Figure 7.1 Multicarrier transmitter.
Table 7.1 Design parameters of the system.
Symbol rate Pulse shaping ﬁlter Number of carriers Assumed input signal statistics Signal bandwidth Carrier spacing EV M ACLR1 2 3 Number of input bits
3.84 Msymbols/s Rootraised cosine α = 0.22 4 Normally distributed and truncated with crest factor 10 dB 3.84MHz 5MHz Tested with 4QAM signal with symbol magnitude 40dB below maximum Simulated with channel separation of 5, 10 and 15 MHz respectively 13
the IF ﬁlters, mixers and PA are beyond of the scope of this work. The parameters and signal conditions used in the transmitter design are listed in Table 7.1.
7.1 Prototype of WCDMA transmitter
141
7.1.1
Frequency planning
The design begins with the frequency planning. The number of carriers and carrier spacing of 5MHz deﬁnes the total bandwidth that needs to be 19.68MHz. However, in order to make the image ﬁltering possible after the D/A conversion and after the upconversion to the second IF, the frequency band used is 5.1624.84MHz. To get the ﬁrst image far enough to be ﬁltered, the sampling frequency should be selected high enough. The lowest integer multiple of the input symbol frequency 3.84MHz that is high enough to make the ﬁltering possible is 61.44MHz, which is selected to be the clock frequency of the CORDIC rotator, resulting in the total interpolation ratio of 16 for the input data.
7.1.2
Interpolation strategy
In order to be able to select the most effective strategy for the interpolation, the total number of ﬁlter coefﬁcients must be determined. The number of FIR ﬁlter coefﬁcients required for the PSF with certain stopband and passband ripples and relative transition bandwidth can be approximated with the equation that holds for the equiripple lowpass FIR ﬁlter [58] N1 ≈ √ −20 log10 σ p σs − 13 L1 Fs +1 = K + 1 L1 > 1 14.6∆ f fs − f p (7.1)
√ in which K = −20 log10 σ p σs − 13, Fs is the sampling rate at the input of the PSF, L1 is the oversampling ratio of the PSF, σ p and σs are the passband and stopband fs − f ripples, respectively, ∆ f = L1 Fsp is the width of the transition band relative to the out sampling frequency of the PSF, and fs and f p are the stop and passband edge frequencies, respectively. When a chain of interpolation ﬁlters is used to perform the possible residual interpolation after the PSF, the number of taps required for each of these interpolation stages may be calculated as Nk ≈ K Lk L pk Fs Lk + 1 Lk > 1, k > 1 +1 = K L pk Fs − 2 fs 1 − 2 fs
L pk Fs
(7.2)
k−1 in which Lk is the interpolation ratio of the current stage, and L pk = ∏i=1 Li . With equations (7.1) and (7.2), the total number of coefﬁcients for each interpolation strat
egy can be calculated. It can be observed that the total number of ﬁlter coefﬁcients is minimized either when the interpolation is made in four cascaded stages, each interpolating by factor two, or with the cascaded interpolation stages with interpolation factors 2, 2, and 4, respectively. Comparison of the efﬁciency of the interpolation strategies is
142
Prototypes and experimental results
2 Channel filter
2 1st Half band
2 2nd Half band
2 3rd Half band
Figure 7.2 Interpolation chain.
presented in Table 7.2. The four cascaded ﬁlter stages with an interpolation factor of 2
Table 7.2 Comparison of interpolation strategies
Order of interpolators 16 8, 2 4, 4 4, 2, 2 2, 8 2, 4, 2 2, 2, 4 2, 2, 2, 2
Number of coefﬁcients per stage 297 149, 11 74, 25 74, 13 ,11 38, 84 38, 43, 11 38, 22, 24 38, 22, 13, 11
Total number of coefﬁcients 297 160 100 99 122 92 84 84
is chosen because it facilitates the use of halfhand (HB) ﬁlters after the PSF. The use of the HB ﬁlters further reduces the amount of hardware because approximately half of their coefﬁcients are zero valued. The structure of the interpolation chain is presented in Fig. 7.2.
7.1.3
Digital FIR ﬁlter and interpolator design
The multistep interpolation with an interpolation factor of 2 was chosen as an interpolation strategy because of its hardware efﬁciency, After the decision on the interpolation strategy, the ﬂoating point prototypes of the channel ﬁlters and the half band interpolation ﬁlters were designed. The channel ﬁlter was designed with the Lagrange algorithm described in Section 4.1.1. The half band ﬁlters were designed with the least square error algorithm and with the “trick”method described in [62]. With this method, an evenorder prototype ﬁlter with desired passband characteristics and a transmission zero at half of the sampling frequency is converted to an oddorder halfband ﬁlter by inserting a zero between the coefﬁcients of the prototype and changing the centermost zero to 1. In this design phase, some margin was left for the degradation of the performance caused by CSD presentation and ﬁnite word length effects in order to ensure that the performance of the transmitter can be designed to be limited by the D/A converter.
7.1 Prototype of WCDMA transmitter
143
Frequency responses of the filters
0
−20
Relative power [dB]
−40
−60
−80
−100
1.92
5.76
9.6
13.44
17.28
21.12
24.96
28.8
Frequency [MHz]
Figure 7.3 Frequency responses of the ﬁlters.
Once the coefﬁcients of the prototype ﬁlters were discovered, the coefﬁcients were converted to CSD format with the modiﬁcation of the algorithm presented in [67]. The algorithm was modiﬁed in order to maximize ACLR rather than to minimize the peak ripple on the stopband. The frequency responses of the designed ﬁlters are presented in Fig. 7.3 and the frequency response of the interpolation chain is presented in Fig. 7.4. ISIrms of the designed CSD interpolation ﬁlter chain is 45.022dB (0.561%) and ACLR values for the ﬁrst, second and the third adjacent channel are 85.89dB, 99.13dB and 92.15dB, respectively. The quantization noise due to the D/A conversion or ﬁnite word length effects is not included at this point. The lower limit of EV M is set by ISI of the channel ﬁlter. The ﬁnite accuracy of the computation in the ﬁlters and CORDIC modulator, and the quantization in the D/A converter adds noise to the signal thus increasing EV M. Similarly, the limit of ACLR is set by the D/A converter, the stopband attenuation of the ﬁlters and the noise added by the ﬁlters and CORDIC modulator. Since the 14bit D/A converter sets the ACLR value approximately to 75dB, the objective of the design was to obtain EV Mrms performance better than 40dB (1%) and ACLR to be limited by the D/A converter. After the CSD coefﬁcients were discovered, the analysis of the ﬁnite word length effects was performed. The simulation script was written in Matlab that modeled the
In addition to the area reduction. the effects of the one single ﬁlter to ACLR and EV M were discovered.28 21.5. The internal word length of one ﬁlter was swept from 10 to 20 bits when the internal word lengths of the other ﬁlters were kept at 20 bits.2. the effects of the internal word lengths and the effect of the D/A converter on ACLR1 are presented. 18. 75. second and third halfband ﬁlters are 17. In EV M simulations. The effects on EV M are presented in Fig.8 Frequency [MHz] Figure 7. Similar simulations were carried out for ACLR2 and ACLR3 . and the EV Mrms is 40. The internal word lengths chosen for the channel ﬁlter (pulse shaping ﬁlter) and for the ﬁrst.3. the interleaving technique described in Section 4. respectively.44 17.62dB and 73.3.5398dB (0. the single 4 QAM modulated signal with a symbol magnitude of 40dB below the maximum was used. 7. The D/A converter was modeled as a quantization at the transmitter output. The simulated ACLR1 2 3 values with the ﬁnite word length effects included in the ﬁlters are 73.94%).70dB.4 Frequency response of the interpolation ﬁlter chain.6. The effects of the CORDIC and inverse SINC ﬁlter were left out at this point. . 18.92 5.76 9. 7. In order to further reduce the area used by the ﬁlters. behavior of the transmitter. With this method.12 24. and an ideal upconversion and reception was used.96 28.3 was used [71]. In Fig. and 18 respectively.92dB.1 was used in the realization of the ﬁlters. The polyphase structure that was described in section 4. A normally distributed and truncated data stream with the crest factor of 10dB was used as the input in ACLR simulations in order to model the sum of 4 QAM data of 100 code channels (central limit theorem [19]).6 13.144 Prototypes and experimental results Frequency responses of the cascaded filters 0 −20 Relative power [dB] −40 −60 −80 −100 −120 1.
.7. Error vector magnitude −10 −15 −20 PSF HB1 HB2 HB3 D/A D/A− limit Relative power [dB] −25 −30 −35 −40 −45 −50 11 12 13 14 15 16 17 18 19 20 Number of bits Figure 7.5 ACLR1 as a function of the internal word lengths.6 EV Mrms as a function of internal word lengths and D/A converter resolution.1 Prototype of WCDMA transmitter 145 Adjacent channel power ratio −45 −50 −55 PSF HB1 HB2 HB3 D/A D/A− limit Relative power [dB] −60 −65 −70 −75 −80 −85 −90 11 12 13 14 15 16 17 18 19 20 Number of bits Figure 7.
however. Number of coefﬁcients Maximum number of terms in CSD coefﬁcient Maximum shift in CSD coefﬁcient Number of realized coefﬁcients in polyphase composition (subﬁlter 1/subﬁlter 2) Internal word length 1st Channel halfﬁlter band 37 23 6 5 13 9/10 13 6/1 2nd halfband 11 4 12 3/1 3rd halfband 11 4 12 3/1 17 18 18 18 the advantage of using the interleaving technique is that all the clock frequencies used in the ﬁlters are above the desired signal frequency band. uses a clock of only 30.7 Pipelined/Interleaved interpolation ﬁlter chain. The clock frequencies were selected so that the maximum clock frequency equals the one used in the CORDIC rotator. The structure of the interleaved interpolation ﬁlter chain is presented in Fig. 7. 61. reducing the possible spurs generated by substrate coupling.3.4. The ﬁrst ﬁlter. The number of ﬁlter coefﬁcients and realized ﬁlter coefﬁcients in the polyphase composition are listed in Table 7.7. The simulated ACLR and ISIrms and EV Mrms values for the CSDﬁlters without and with the ﬁnite word length effects are listed in Table 7. . Table 7.3 Number of ﬁlter coefﬁcients and the number of realized coefﬁcients in polyphase decomposition.72MHz because there are only 8 data streams to interleave and because the polyphase structure allows the computation at half of the sampling frequency (sampling frequency after the interpolation).146 16*F 16*F Prototypes and experimental results 16*F 2 F 2 16*F 2 2 2 8 pcs 2 2 2 I1 Q1 I2 To CORDICs Q2 I3 Q3 I4 Q4 Figure 7.44MHz.
The simulated probability density of the sum of 1. since the internal .1 CORDIC and inverseSINC ﬁlter design CORDIC design The word lengths of the CORDIC and the inverse SINC ﬁlter were determined in a manner similar to that in the interpolation ﬁlter chain. assuming the input values to be 1. 3. Also. that the I/Q modulated signal with Gaussian distributed I and Q data values and standard deviation σ is also Gaussian distributed with standard deviation σ. number of bits in the amplitude path (a = 20) and the number of bits on the phase calculation path (p = 17) were discovered. approximately 6dB of the dynamic range is lost when the signal is truncated.7. 7. thus increasing EV M and ACLR. the saturating scaler is added to the output of the CORDIC. power) and maximum amplitude does not change as the number of carrier increases.1 Prototype of WCDMA transmitter 147 Table 7.1.3281. 5. N = Number of carriers) instead of theoretical maximum amplitude.92dB ACLR2 99.4).022dB (0. and the probability density function of the Gaussian distribution with corresponding standard deviations are presented in Fig.e.4. This also minimizes the amount of hardware needed in the inverse SINC ﬁlter.4 7.5398dB (0.13dB 75. it is very unlikely that the signal has the value 4Aoutmax .561%) 40.70dB ISIrms and EV Mrms 45. However. the number of bits should be increased as √ a function of standard deviation ( N. 7.94%) 7. It can be calculated as in [170].15dB 73. To clip the large values of the multicarrier signal. when summing up four modulated wide band signals. and 4 wideband signals are presented in Fig. the consequence is that the power of a single carrier is reduced relative to quantization noise. 2.89dB 73.9 Since the ratio of the variance (i.1. and thus the multicarrier signal also has a Gaussian distribution with variance linearly dependent on the number of carriers. because the probability of overﬂow in the case of a limited number of bits is relative to the standard deviation of the signal. The output of the interpolation ﬁlter chain was used as the input of the CORDIC rotator and the number of stages (N = 15) (Fig. According to the theory presented in Section 5.4 ACLR and ISIrms /EV Mrms values. in order to maintain the probability of overﬂows.8. In the case when the peak value of the signal is just slightly above the half of the full scale. the maximum output value of the √ CORDIC rotator is Aoutmax = 1.62dB ACLR3 92. Scaler maximizes the dynamic range of the signal and saturates the output in the cases of overﬂow. One method to handle the occasional overﬂows and reduce the overﬂow originated signal degradation is clipping.6468 2 = 2. Without internal word length effects With internal word length effects ACLR1 85.2.
012 Probability 0.8 −0.012 Probability 0.002 0 −1 −0.4 −0.006 0.1080 2 carriers.01 0.1542 3 carriers.4 −0.8 1 Normalized output value Figure 7.014 0.01 0.008 0.2 0 0.8 1 Normalized output value Figure 7.148 Prototypes and experimental results Probability density function of the output 0.9 Probability density functions of normal distribution with standard deviations of simulated multicarrier signals.6 0.6 −0. .1884 4 carriers. σ=0. σ=0.002 0 −1 −0.2183 0.1884 σ=0.016 σ=0.2 0 0.004 0.6 0.004 0. Probability density function of the normal distribution 0. σ=0.4 0.2 0.8 −0.006 0.2183 0.6 −0.2 0.016 1 carrier.8 Probability density function of simulated multicarrier signals.014 0.1542 σ=0.1080 σ=0.008 0.4 0. σ=0.
Tools that was used for the synthesis were Synopsys Design Analyzer for the logic synthesis and static timing veriﬁcation. and 73. the signal is rounded to 14 bits and fed to the D/A converter.10.converter.84MHz which is not acceptable. This droop is 2.16 to 24.65dB.58dB. The simulated spectrum of the multicarrier signal at the transmitter output is presented in Fig. The effects of the clipping and various algorithms for clipping the wide band signals are discussed in more detail for example in [171].11. the gain ripple at the band from 5.2 InverseSINC ﬁlter design The inverseSINC predistortion ﬁlter is used to compensate the droop in the frequency response of the transmitter caused by the sample and hold operation of the D/A.38dB (0. Cadence Envisia PBopt and CTgen for placementbased optimization and clocktree generation and Mentor Graphics ICStation for toplevel manual editing. 7. After correction. The synthesis ﬂow is presented in Fig.1 Prototype of WCDMA transmitter 149 wordlength of the ﬁlter is reduced.12. After scaling. the overall performance of the multicarrier QAM modulator was determined by simulation. and the ﬁnal ACLR1 2 3 values are 73. respectively. Cadence Envisia Silicon Ensemble for place and route.476dB at 24. 7. 7. 75. Synopsys VSS for VHDL simulations. The single carrier case is presented in Fig.4. . 7. The inverseSINC ﬁlter was designed by the method described in [169].6 Digital ASIC synthesis ﬂow The digital part of the QAM modulator was realized with logic synthesis based on high level description language. It has 7 coefﬁcients which are symmetric relative to the center coefﬁcient.5 Simulated QAM performance After the internal resolution and the values of the scalers had been deﬁned. The transposed direct form is used in the realization of the ﬁlter. layout versus schematic checking and designrule checking. The value of the scaler is determined by simulations.96%). A scaler similar to one after the CORDIC is used at the output of the ﬁlter in order to maximize the signal dynamics.1. 7. The ﬁnal EV M value is 40. 7.1. The simulated internal word length for the correction ﬁlter is 18 bits.1.0895dB.7.58dB. Synopsys Formality for static functional veriﬁcation. Cadence Envisia Design Planner and Silicon Ensemble for ﬂoorplanning.84MHz is 0.
10 Spectrum of the multicarrier WCDMA signal at the output of the transmitter.5 12.5 27.5 Frequency [MHz] Figure 7.5 12.5 Frequency [MHz] Figure 7.5 17.5 27.5 22.11 Spectrum of the single carrier WCDMA signal. Power spectrum of modulator output 0 −10 −20 Relative power [dB] −30 −40 −50 −60 −70 −80 −90 2.150 Prototypes and experimental results Power spectrum of modulator output 0 −10 −20 Relative power [dB] −30 −40 −50 −60 −70 −80 −90 2. .5 17.5 7.5 22.5 7.
12 Logic synthesis ﬂow .7.1 Prototype of WCDMA transmitter 151 Matlab simulations Floorplanning OK? Yes No Timing driven Placement VHDL description Placement optimization Clock tree generation OK? Yes No Logic synthesis Timing driven routing OK? Yes No Placement optimization Static timing verification Final routing Foorplanning OK? Yes No Static timing verification Static functional Verification or functional simulation OK? No Yes Top level manual layout editing Is the failure in the floorplanning or in the logic synthesis? Logic synthesis OK? Yes No LVS and DRC OK? No Yes To fabrication Figure 7.
The topology of the D/A converter is presented in Fig.13 Block diagram of the D/Aconverter. The matrix of 8 LSBs is binary weighted and the matrix for the 6 MSBs is partially weighted. only the theory applied to this particular design is discussed. The D/A converter designed for the transmitter is a segmented current steering type converter.13. It has two current source matrices.1 Static matching It was assumed as a coarse approximation that INL follows the normal distribution with variance σINLmax = 2N − 1 σlsb . In case a more accurate analysis of the design methods is performed after the design of this prototype.1. 7.1. Ilsb (7. Two least signiﬁcant bits of the MSB matrix are binary weighted and four MSB bits are thermometer coded (unweighted). Each of the ﬁfteen MSB current sources corresponding to the four thermometer coded MSB bits provides a current of four times the least signiﬁcant bit of the MSB matrix.152 Prototypes and experimental results Vdd Vout+ Vb Vout− Vb Control logic Data in Current switches Cascade transistors clk 8 LSBs Binary Weighted 6 MSBs 2 Weighted 4 Unweighted Figure 7. 7. references are given.7 14bit 70MHz Digitaltoanalog converter In this section.3) .7. 7.
4) where Avt . the switches are also of different size.4). VT is the threshold voltage of the transistor.2. Analysis of the behavior of the output impedance is presented in more detail in Sections 6.3 reveals that this assumption is not absolutely accurate.2 Enhancement of dynamic properties In order to minimize the capacitive coupling. Method for ﬁnding the dimensions of the current sources is presented in Section 7. The area of the LSB current source is obtained by using the matching equations presented in [125]. Abeta and Bbeta are process dependent constants given by the silicon vendor. the sources of the switch transistors would be driven to Vss . Cascode transistors are also used between the current switch and the current source transistor to further increase the output impedance of the current sources.1.2. It is also ensured that both of the switches are not closed at the same time. additional cascode transistors were added between the load and the current switches. (7.5 and 7. This would cause a spike at the output. 7. as determined by equations Eq. The topology of the one current source.7. [124] σ2 4A2 Abeta vt id + Bbeta + √ = 2 2 Id WL W L (Vgs −VT ) 2 . was too large to be realized. swing as small as possible is used to drive the switches. which minimizes the difference between bias points and thus improves the static matching.16).15. These transistors were made common to all of the switches connected to the particular signal branch. In order to increase output impedance of a single current branch. 7. Therefore the area used for the current source was determined in order to obtain 12bit linearity (INL and DNL < 2LSB). In this case. but gives a good starting point for the dimensioning of the current sources. 7. Because the currents in LSB and MSB matrices are different. Inaccuracies in synchronization of the switch drivers may cause harmonic distortion. which would lead to the situation where no current ﬂows through the current source. The synchronization of switching is enhanced by adding dummy transistors in parallel with the gates of the smaller LSB switches in order to equalize the load seen by the switch driver (Fig. 7. The area of the LSB current source required for 14bit matching. (7.14. .1 Prototype of WCDMA transmitter 153 The analysis of INL presented in Section 6. W is the channel width and L is the channel length. Vgs is the gatesource voltage of the transistor. and the current sources would require a relative long time to recover from the bounce. The switch driving principle is presented in Fig.7. (7.3) and Eq.1. switch and output cascode set is presented in Fig.
. V s Optimal swing V s Figure 7. switches and cascode transistors.15 The switching waveform.154 Prototypes and experimental results V dd V c2 I bias V s V c2 V s V c1 V ss V ss Figure 7.14 One set of current source.
.1 Prototype of WCDMA transmitter 155 I out V s I out V s V ss V ss V ss Figure 7.7.16 Dummy transistor as additional load.
7.156 Prototypes and experimental results d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d 24 11 22 13 20 15 18 16 19 14 21 12 23 10 8 10 24 d 17 16 19 14 21 12 23 d 13 18 15 20 17 22 11 d d d d 9 11 22 17 20 15 18 13 9 24 10 m 23 12 21 14 19 16 17 d d d d d 10 23 12 21 14 19 16 18 15 20 13 22 11 24 d d d d d d d d d d d d d d d Figure 7. This means that. The rest of the current sources have 4 transistors each.1. guard lines are used wherever possible.1.17. It can . another two are near the center.3. It is also preferable to use the common centroid approach when drawing the matrices in order to minimize the effect of the lineargradienttype processing parameter variation as the function of position on the wafer. The transistor marked with ”m” is for current mirroring. The sampling frequency used for the simulation was 66. 7.17 The common centroid MSB current source matrix.2.7. 7.4 D/A converter simulations The simulations for the spectral purity of the D/A converter were carried out with sinusoidal signals of different frequencies. The best way to do this is to put the current sources in matrices and add some dummy transistors around the current source transistors. respectively. The sources are numbered from 8 to 24.67MHz. It is also preferable that the transistors are arranged so that all of the transistors of one source are not. The common centroid matrix approach has also been used in the bias generation. In addition to the static matching optimization by common centroid matrices.3 Layout issues In order to achieve the best possible static matching. for example. A better way is to balance the location so that the mean distance from the center of the matrix is constant. on the periphery of the matrix. In Fig.8 and 7. if two transistors of the single current source are at the edge of the matrix.7. The layout techniques for improving the static matching are analyzed more thoroughly in Sections 6. Also. Ground planes are also added to decrease the capacitive coupling between the digital and analog signals. it is preferable to make the environment of each current source identical to each other. The transistors labeled with 8 and 9 are the weighted sources consisting of 1 and 2 transistors. switch drivers and digital logic. The method used for the MSB current source matrix is presented in Fig. the dynamic performance is enhanced by using different supply voltage sources for the analog part and bias.18 a spectrum of a 5. 7.43MHz sine signal is presented.
7. The control program. Now the dominant components of SFDR are the 2nd and the 3rd harmonic component.1. is written in C programming language [172].8.35µm BiCMOS process. 7.5 7.1 Prototype of WCDMA transmitter 157 Power spectrum 0 −20 Frequency [MHz] −40 −60 −80 −100 −120 2. 7. be seen that the third and the ﬁfth harmonic component dominates SFDR and that the level of the even harmonics is low. but only CMOS transistors were used. Isolation between the digital part of the chip and the D/A converter is achieved by the usage of isolation rings.19 the signal frequency of the sine is increased to 28. respectively. Such features are.7. In Fig.8 Experimental results The chip was fabricated in a 5 metal 2 poly 0. The parallel port of the PC is used to control the functionality of the chip. for example.5 22. The same kind of isolation is also available in triple well CMOS processes.1 Measurement setup The measurement setup for the circuit is shown in Fig.5 12.5 Relative power [dBc] Figure 7. which controls the parallel port.5 17.32dB and 89. The design features that are not available in conventional CMOS processes are also used.20. With the program.5MHz. it .5 27. The values for the 3rd and 5th harmonic components are 80.92dB.18 Spectrum of 5.43MHz sine signal.1. 7. isolated NMOS transistors.
5 22.19 Spectrum of 28.5MHz sine signal. is possible to set the carrier frequencies and select which part of the chip is tested. It is possible to test each of the ﬁlters separately and also to test the CORDICs by selecting either one or all of them to be used.5 17.converter can be measured either as connected to the digital transmitter or in a standalone mode. Clock Signal Generator Voltmeter Pattern Generator Measurement PCB Spectrum Analyzer PC DC power supply with current meter Figure 7.5 12.5 27.5 7.20 Measurement setup for the circuit.5 Relative power [dBc] Figure 7. The D/A.158 Prototypes and experimental results Power spectrum 0 −10 −20 −30 Frequency [MHz] −40 −50 −60 −70 −80 −90 −100 2. Manufacturers .
27.8.8.1. The bias current of the current source matrices was 200µA. .44MHz and the static performance with the sample frequency of 1Hz. 7.5. The maximum absolute values of DNL and INL are 1.31.7.11 HewlettPackard 3457A RohdeSchwartz 1088.87LSB and 2.1. It is assumed that this enhances the dynamic performance of the D/A converter because the switches stay better in the saturation region when they are open. signal frequency is presented in Fig. 7.5 and 30MHz are presented. 12. 7. as designed.1. respectively.5. however. 3. resulting in a reduced level of the 2nd harmonic component.5502. It can be seen that the static nonlinearities limits the spurious free dynamic range to be about 83dB. The second harmonic increases as the signal frequency is increased and becomes dominant at the signal frequencies near half of the sampling frequency. the bias current for the switching level setting were increased from 100µA to 450 µA in order to lower the switching voltage levels at the input of the switches. It can be seen that the third harmonic dominates at the low frequencies.1 Prototype of WCDMA transmitter 159 Table 7. 7.23 .3 Static performance of the D/Aconverter The static performance of the D/Aconverter is characterized by the differential nonlinearity and integral nonlinearity.5.5 Types of the measurement equipment Pattern generator Clock signal generator Voltmeter Spectrum/Vector analyzer DCsupply Tektronix TLA 720 RohdeSchwartz 1062.7. 7.30 the spectra of the sine signals of frequencies 1. The measured DNL and INL are presented in Fig.5.3494. In Fig. 7. which is the typical operation condition for the converter used in the transmitter. These are measured by feeding the ramp signal with 1 LSB step to the D/Aconverter operating with a 1Hz sampling frequency.30/FSIQ HewlettPackard E3631A and models of the measurement equipment are listed in the Table 7. 22.165LSB.5. 7. 17.4 Dynamic performance of the D/Aconverter In Figs 7.2 D/Aconverter performance The dynamic performance of the D/Aconverter was measured with the sample frequency of 61. The spurious free dynamic range of the converter vs. The supply voltage was 3V.21.22 the ideal sine signal is fed to the Matlab function that distorts the signal with the static nonlinearities of the D/Aconverter.8.
160 Prototypes and experimental results Static nonlinearities relative to LSB 2 DNL [LSB’s] 1 0 −1 −2 2000 4000 6000 8000 10000 12000 14000 16000 Number of sample 2 1 0 −1 −2 2000 4000 6000 8000 10000 12000 14000 16000 INL [LSB’s] Number of sample Figure 7.5 17.5 27. .5 22.5 Frequency [MHz] Figure 7.22 Sine signal distorted with the static nonlinearities.5 7. Sine signal under influence of static nonlinearities 0 −20 Relative power [dBc] −40 −60 −80 −100 −120 2.21 Differential and integral nonlinearities of the D/Aconverter.5 12.
Figure 7. .24 Spectrum of the 3MHz sine signal.23 Spectrum of the 1MHz sine signal.1 Prototype of WCDMA transmitter 161 Figure 7.7.
5MHz sine signal. . Figure 7.5MHz sine signal.25 Spectrum of the 7.162 Prototypes and experimental results Figure 7.26 Spectrum of the 12.
.27 Spectrum of the 17.1 Prototype of WCDMA transmitter 163 Figure 7.5MHz sine signal. Figure 7.5MHz sine signal.7.28 Spectrum of the 22.
Figure 7.5MHz sine signal.30 Spectrum of the 30MHz sine signal. .164 Prototypes and experimental results Figure 7.29 Spectrum of the 27.
5.5.32 Spectrum of multiple carriers. signal frequency.5MHz is presented. 12. Figure 7. In Fig.1 Prototype of WCDMA transmitter 165 Spurious Free Dynamic Range 85 80 75 70 SFDR [dB] 65 60 55 50 45 0 5 10 15 20 25 30 Frequency [MHz] Figure 7.32 the spectrum of the sum of four carrier signals of frequencies 7.5. 7.7. and 22. . 17.31 Spurious free dynamic range vs.
1. the signal is no longer saturated. If the two signals saturates the adder and the third signal has the opposite sign. 7. However. The total power dissipation of the D/A converter was measured to be 141mW.8. with the regulator outside the chip.5 QAM Performance The QAM performance was measured with normally distributed and truncated data with the crest factor of 10dB.166 Prototypes and experimental results Figure 7. The power consumption can be reduced if an invertertype driver is used to drive the switch. resulting in spurs generated on the sidebands. The measured constel . In the multicarrier case. The static current is used to set the level of the switch driving voltage. the data had to be scaled with the factor of 0. for example. There was saturating adders at the output of the CORDIC. and the step type error is generated. EV M was measured with the single and four carriers each modulated with 4 QAM signals with the symbol magnitude 40dB below the maximum.33 Wideband signal at 7. The system clock frequency was 61.33 . The high power dissipation is mostly due to the static current ﬂowing through the switch drivers.37. The contribution of the switch drivers to the power consumption is 93mW.7.44MHz.9 before the transmission because of a slight bug in the system.45 mm2 . The spectra of the WCDMA signal with different combinations of the carrier frequencies are presented in Figs 7. then the voltage level has to be generated by other means.5MHz. The area of the D/A converter is 3. The data was fed to the transmitter with the pattern generator which was synchronized to the system clock. ACLR was measured with the spectrum analyzer.
Figure 7.35 Wideband signal at 17. .7.34 Wideband signal at 12.5MHz.5MHz.1 Prototype of WCDMA transmitter 167 Figure 7.
168 Prototypes and experimental results Figure 7. Figure 7. .37 Multicarrier WCDMA signal.5MHz.36 Wideband signal at 22.
5MHz carrier and the corresponding EV M.3 . 1 6 6 6 6 6 7 S y m b o l / E r r o r s D e m o d Q P S K S y m 4 0 8 0 0 1 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 0 1 0 V e c t o r E r r o r 0 1 0 1 0 0 1 0 1 1 1 1 1 1 0 1 0 1 1 1 0 1 1 1 b o l T a b l e 0 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 0 1 1 1 0 1 1 0 1 1 1 0 1 1 1 1 1 0 1 1 0 6 * 0 1 0 1 1 0 0 1 1 0 1 0 1 1 0 0 1 0 0 1 1 1 1 1 E r r o r S u m m a r y . 8 4 M H z M H z M e a s S i g n a l C o n s t e l l a t i o nC o n s t e l l a t i o n D e m o d Q P S K 169 1 . The minimum supply voltage that the digital transmitter operated with was 2. 5 3 . 7. 6 6 R h o I Q 1 . . 9 9 8 2 0 . 6 6 0 .39. 3 6 7 m 1 3 4 . 0 4 d B / s y m % H z r m s . 8 4 M H z M H z 4 .1 Prototype of WCDMA transmitter M a r k e r 1 [ T 1 ] M a g n i t u d e P h a s e 4 2 1 . 4 7 r m s 0 . D E C . 0 6 3 . 7. 2 7 0 . 0 0 s y m 9 9 9 . There is also some margin left for the signal degradation in the analog signal processing part. 4 8 I m b a l a n c e F a c t o r H z P k P k a t s y m 1 0 6 0 . 0 5 % D a t e : 4 . ACLR speciﬁcation of the WCDMA base station transmitter [20] is 45 and 50dB for ACLR1 2 and 17. 2 0 d e g C F S R 1 2 .3 . 1 6 6 6 6 6 7 R e f . 5 .1 .38. 3 3 1 .6. 2 0 0 0 1 6 : 0 6 : 5 5 Figure 7. The dependence of the power consumption and the supply voltage is presented in Fig. 5 I M A G R e f .7.4 0 L v l d B m ) 1 T 1 .165V and the maximum clock frequency that the transmitter operated with a 3V supply voltage was 73MHz. phase error and amplitude error are presented in Fig.4 . It can be said that this digital IF part of the multicarrier WCDMA base station transmitter is applicable to the 3rd generation wireless communications systems. The lowest possible supply voltage for the digital part was determined by measurement. 5 3 .3 . The supply voltage of the digital signal processing part has a huge effect on the total power consumption of the transmitter.5% for EV M.38 Signal constellation and statistics of EV M measurement. The measured performance metrics are listed in Table 7. 0 5 % % r m s d e g A m p l i t u d e E r r o r O f f s e t D r o o p .4 0 L v l d B m M a r k e r V a l u e 1 [ T 2 ] 0 R E A L 2 s y m C F S R 1 2 . lation for the 22. 0 9 % % P k d e g P k a t a t s y m s y m 2 6 8 E r r o r M a g n i t u d e P h a s e F r e q I Q E r r o r M a g 1 .
5 dB (1.76 dB 57.165 V) power supply Maximum operation frequency Area die/core/D/A converter 3.09/62.75/19.170 Prototypes and experimental results Power dissipation of the DSP 1400 1300 1200 Power [mW] 1100 1000 900 800 700 600 2.1 2.5MHz carrier) ACLR in multicarrier case Worst case EV Mrms Power dissipation with nominal (3V) digital power supply Power dissipation with optimal (2.80/58.8 2.33W+141mW=1.14dB 37.84MHz 3.44MHz 62.47W 660mW+141mW=801mW 73MHz 25.7 2.39 Power dissipation of the digital transmitter as a function of the supply voltage.6 Measured performance characteristics of the transmitter.33%) 1.6 2.4 2.3 2.84MHz 5MHz 61. Table 7.9 3 Supply voltage [V] Figure 7.5 2.2 2.45mm2 . Symbol rate Channel bandwidth Carrier spacing Nominal clock frequency Worst case ACLR1 2 in single carrier case (22.18/3.
2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 171 Vdd Off chip R Out+ Out− Vdd R DNL Measurement D1 20 2−to 1 MUX Switches 10 (+3) Cascode transistors 10 (+3) 10 Binary weighted LSB bits (+0. are added in order to have adequate resolution for the calibration.41 represents the single current branch and switch set used in the converter. digital calibration circuitry. An additional set of switches is used to enable the differential quadrature switching scheme [151] [168].25 &0. Fig. and 0.3V 0. Redundancy is required by the calibration algorithm as described in Section 6.25.125 sources for calibration 63 (+4) 6 thermometer coded MSB bits (+4 sources for calibration) 63 (+4) Switch driver flip−flops Thermometer coder +digital calibration D2 20 Serial controlregister Analog bias circuitry Figure 7. the design and experimental results of a 16bit 400 MS/s D/A converter prototype fabricated in a 3.5. Two cascode transistors are used to increase the output impedance and reduce the distortion due to output impedance variation.35 µm SiGe BiCMOS process are presented.7. The architecture is a segmented currentsteering converter with 6 thermometercoded and 10 binaryweighted bits. 7. in order to be able to achieve 400MS/s input data rate. Four thermometercoded current sources are added to MSB sources in order to introduce redundancy in the transfer function.125 LSB.40.40 Block diagram of the prototype 7.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration In this section. control registers. 7. . respectively. 0. The designed converter consists of converter core. 0. The block diagram of the converter is presented in Fig.5. and measurement circuitry for the current source mismatch. The converter is designed with CMOS transistors only. which will be discussed later in this section. The 2to1 multiplexer (MUX) is used at the input.4. Three additional binaryweighted current sources with weights 0.
the dimensions for the current source transistors were determined in order to have adequate matching.172 Prototypes and experimental results RL o+ RL o− DT Ibias Vc2 Vc1 DT DT DT Figure 7. Even though the usage of calibration alleviates the matching requirement of the MSB current sources.1 Current source dimensions and DC matching Once the DC operation point of a current branch was deﬁned in order to have adequate output swing and large enough Vds for all the transistor in order to keep them in the saturation region. Assuming the standard deviation of the maximum value of the INL is related to the standard deviation of the current source as σINLmax = C1 2N − 1 σlsb .7) = P (−C2 σINLmax ≤ MAX (INL) ≤ C2 σINLmax ) . the matching of the LSB sources is important since it will deﬁne the quality of the calibration and thus the static linearity of the converter.5) as presented in Section 6.3.2.3. Ilsb (7.6) (7. 7.3. The methods for analyzing the INL and DNL behavior as a function of matching were discussed in detail in Section 6.41 Single current branch of the converter. and by deﬁning the INL yield to be YieldINL = P (−INLlimit ≤ MAX (INL) ≤ INLlimit ) (7.
and. it was assumed as a coarse simpliﬁcation that the maximum absolute value of the INL follows the normal distribution. On the other hand.10).9) (7. (7. (6.3. assuming the effect of increased distance between sources is negligible. C = 2) is 113.8) (7. nearly 100% of converters should have INL ≤ 5. which corresponds to the linearity requirement of a 12bit converter. the YieldINL = 99. with the used current source area. Combining the transistor matching equation Eq. in the 16bit case.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 173 we obtain σINLmax ≤ σLSB ILSB INLlimit . C2 INLlimit √ ≤ C1C2 2N − 1 INLlimit . by selecting C = 3. Therefore the dimensions of the current sources are determined by the maximum area that can be used for the converter. indicating that. for the MOS transistor in saturation holds W 2Ilsb ≈ .7.12) Together these two equations determine the dimensions of the LSB current source tran . = √ C 2N − 1 (7. It can be observed from the MonteCarlo simulation curves presented in Section 6. However. On the other hand.3 that.3.33. The area required for 16bit matching (INLlimit = 0.7 times the current area. Referring to research results presented in Section 6. the same area of the current sources is obtained with C = 2 and INLlimit ≈ 5. L µoCox (Vgs −VT )2 sistor.7 should be obtained. In the early phase of the design process. by choosing C ≈ 2 .5. as presented in (7.33 instead of INL ≤ 8. it can be stated that.5) and Eq. there exists an optimum area of the current source that gives the best matching for a certain number of bits. YieldINL very close to 100% should be achieved. Due to the limited area available.10) in which the product of constants C1 and C2 can be combined in a single constant C. 2 2 4Svt D2 (7. the product of channel width and length of the current source transistor are obtained as 4A2 vt 2 WL = C2 2 INLlimit (2N −1) (Vgs −VT ) − + A2 β . it was decided to increase the error limit to be INLlimit = 8. the total area required would become very large. when comparing the above mentioned approximation method and MonteCarlo simulation results.11) (Vgs −VT ) 2 − Sβ D2 In which D is the average separation of two current sources.
which is as desired. In order to demonstrate the frequency behavior of the Zu in the presence of the routing capacitance of current source matrices. Moving down the zero also improves the impedance performance from 100MHz to 200MHz. however. Simulation results for simultaneously stepping the W and L of the MSB switch from minimum to 5 times the minimum is presented in Fig. 7. Also.42 indicates that the pole p with ω p ≈ gC3 gm3 ggds1 of Eq.2. Increasing the W and L rapidly increases the Zu . The impedance value is 20 log 2 ×Zumsb corresponding to the effect of 50 MSB current source referred to the value of LSB unit impedance.5. the accurate information of the transistor matching as a function of distance between transistor was not known.44) is determined by the transistor area. (6.e. which is already large enough.10 can be calculated to be W Lopt = 2 4Svt (2N − 1) + 2Sβ (2N − 1) (Vgs −VT )2 4A2 + 2A2 (Vgs −VT )2 vt β (7.43). near the Nyquist frequency of the converter.42. since the frequency of the zero z2 with ωz2 ≈ gm4 scales down according C3 to transistor scaling. i. Further increasing the scaling factor will move the dominant pole to lower frequencies and increase the DC impedance. However. 7.2 Output impedance As analyzed in Section 6. ds3 gds2 Fig. Increasing the W and L of the switches instead of using minimum L increases the switching impedance.5. σLSB ILSB (7. at the time of designing the prototype.174 Prototypes and experimental results [173].13) in Eq.14) Increasing the area beyond this limit will. The practical scaling range is from 1 to 5 times the minimum due to the fact that the area of the switches can not be further increased due to the ﬁnite driving capability of the switch drivers. 7. It can also be observed that the capacitance of the source node of the switches (C3 in Fig. 6. 7. capacitive coupling may introduce undesired behavior if the area of the switches becomes large. the value of the current source capacitor . exacerbate the matching. the variation of the output impedance may have a significant effect on the harmonic distortion of a current steering D/A converter.68) dominates m2 when the scaling factor is larger than 2. 7. as presented in Section 6. and therefore the impedance on the frequency 10 range from 10kHz to about 100MHz cannot be further improved by scaling the switch transistor dimensions (in contrast to the situation presented in Fig. Assuming that the average distance between the current sources is D= the area W L that results minimizes the 2 (2N − 1)W L.
However. (C1 in 6.44) is increased to C1 = 1. which is not present in the smallsignal analysis. This ensures the C1 causes the dominant pole. the scaling of the switch effectively improves Zu on the frequency range from 10KHz to gm4 1MHz according to scaling of gds3 . The true SFDR performance due to ﬁnite output impedance lies somewhere between the lines presented in Fig.43.7.44. since the pole due to C3 is not dominant. There also seems to exist an additional zero around 1GHz. due to the fact that perfect differentiality can not be achieved. A greater improvement is achieved if C1 initially causes the dominant pole.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 175 Z of the LSB source u 240 Scale 1 Scale 2 Scale 3 Scale 4 Scale 5 220 Relative impedance to 50Ω [dB] 200 180 160 140 120 10 0 10 2 10 4 10 Frequency [Hz] 6 10 8 10 10 Figure 7. 7. thus not affecting the performance of the converter.42 Effective Zu of MSB current source reduced to LSB unit switch.44 represents the theoretical SFDR values obtained with current switch dimensions. 7. The result of the simulation is presented in Fig. it is above the Nyquist frequency.2nF. In both cases. In this case. which corresponds to an about 800x800µm2 metalmetal capacitor in a typical CMOS process. the usage of the scaling factor 3 is justiﬁed due to improvement of the impedance within the frequency ranges from 10KHz to 1MHz and from 100MHz to 200MHz. . The zero z2 is moved down in frequency according to scaling of C3 . Figure 7.
43 Effective Zu of MSB current source reduced to LSB unit switch when routing capacitance C1 is very large.44 Effect of the output impedance on SFDR of the converter. .176 Prototypes and experimental results Z of the LSB source u 240 Scale 1 Scale 2 Scale 3 Scale 4 Scale 5 220 Relative impedance to 50Ω [dB] 200 180 160 140 120 10 0 10 2 10 4 10 Frequency [Hz] 6 10 8 10 10 Figure 7. SFDR as a function of output impedance 300 Differential Single−ended Differential−C1 large Single−ended−C1 large 250 SFDR [dBc] 200 150 100 50 0 2 4 6 8 10 10 10 10 10 Frequency [Hz] 10 10 Figure 7.
and y.4].or both directions in order to produce one commoncentroid current source matrix that effectively reduces the effect of both even. since the residual gradient not canceled by symmetry will be of even order.46. Suitable shape of the matrix is obtained by using 8x9 grid with four dummies in the corners.47 and 7. The principle of the mirroring is presented in Fig. 7. Therefore source ”3” is not in the corner [3.8.48 represents the comparison between the maximum absolute value of INL as a function of the plane angle θ in the case where the submatrices are placed in a 4x4 matrix with no mirroring in any direction.3].45 The submatrix Q in Fig. Fig.47 represents the comparison between the maximum absolute value of INL as a function of the plane angle θ (see Eq. which is the next available position.2. The matrix of 67 MSB current sources and a mirroring transistor are presented in Fig. Fig. 7.7. 7. 6. Comparison between the Figs 7. since it cancels out the residual evenorder error more effectively than the linear sequence. but in the xyposition [4. as presented in 6.45 was designed by applying the optimal sequences both in x. whereas the sequence has a large effect when no mirroring is used.and oddorder gradients. Sequences were chosen in order to minimize the effect of evenorder gradient. When a dummy transistor is encountered while placing the current sources according to the sequences presented in Fig. It can be seen that the evenorder optimal sequence results in a smaller error. 7.45 MSB current source matrix.128).direction simultaneously. 7. 7. 7.48 reveals that most of the beneﬁt is achieved by using mirror symmetry.3 Current source matrices The current source matrices were designed by using 16 submatrices mirrored in X. .46. the current source is placed in the next available position.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 177 Q MX MXY MY MY MXY MX Q MXY MY Q MX MX Q MY MXY Figure 7. X.
05 0 0 50 100 150 200 250 Plane angle θ [deg] 300 350 Figure 7. .2 0.15 0. mirroring 0.25 MAX ABS INL [LSB] 0.46 MSB submatrix and the optimal sequences used for evenorder gradient cancellation. mirroring Odd−order.47 Maximum absolute INL with various plane angles.178 Prototypes and experimental results 0 0 3 5 8 6 2 4 9 1 7 D 53 19 36 62 11 44 D 55 38 4 21 46 64 29 13 32 M 49 66 24 40 7 58 47 30 65 14 39 56 22 5 10 61 27 43 2 18 52 35 63 45 12 28 54 3 37 20 25 8 41 59 16 33 67 50 17 1 34 51 9 26 60 42 D 23 57 6 31 48 15 D 3 1 5 7 2 4 8 6 Figure 7.1 0. INL obtained by optimal sequence sub−matrices Even−order.
jitter and timing differences between signal paths to and from the switches.4 Dynamic performance In addition to codedependent output impedance variation. The differential quad switching scheme ensures that the actual and ”toggle” switch drivers have equal capacitive loading. The distortion due to codedependent jitter can be effectively reduced by using the differential quad switching scheme (Fig. The layout of the binaryweighted LSB matrix was designed by using principles presented in Section 6. and thus the powerrail interference.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 179 INL obtained by optimal sequence sub−matrices 12 Even−order no mirroring Odd−order.7. for example. This reduces the effect of the gain error of bias current mirroring.2. the current sources are biased with current mirroring ratio 1:2.48 Maximum absolute INL with various plane angles. The toggle signal changes its state on those clock cycles on which the actual data bit does not change its state. and therefore the currents . 7. which would multiply also the gain error. In order to reduce the error between the MSB and LSB matrices.7. resulting in the bias current of the LSB sources to be half of the bias of the MSB sources. and thus codeindependent. is constant. This ensures that the circuit activity. the dynamic performance (SFDR) of the converter is determined by.8. no mirroring 10 MAX ABS INL [LSB] 8 6 4 2 0 0 50 100 150 200 250 Plane angle θ [deg] 300 350 Figure 7. since the bias current in the LSB matrix is divided when the actual currents are formed.41) [151] and duplicated ”toggle”signal path [168] [139]. instead of being multiplied.
a symmetrical NORstage (marked with ”4”) is used to produce the combinations of data and ”toggle” signals required to steer the switches. The switch driver signals are generated from the digital data and ”toggle” bits with the switch driver presented in Fig.3. Finally. .180 Prototypes and experimental results Analog supply 4 Digital supply Intermediate supply 3 D DT 2 DT CLK 1 DT T DT Figure 7. The additional buffering (marked with ”2”) is used to ensure symmetry in both the signal and its inversion.49 Switch driver for differentialquad switching. The clock buffers (marked with ”1”) are added in order to remove the data dependent clock load variation. The differential latch stage (marked with ”3”) is used to produce a differential switch driver signal and determine the crossing point of those signals. drawn from supply rails should not vary between clock cycles.7. the effect of which was analyzed in Section 6.49. It also equalizes the voltage variation on the source node of the switches. 7. which is not guaranteed when a true singlephase clocked input latch is used.
7. Dedicated power supplies are used for the different stages in the driver in order to reduce the distortion due to power supplyinterference.52.3 dB in the Nyquist band.5 2 2. The simulated SFDR is 78. and is limited by the 3rd harmonic (DC component not taken into account).50. 7. In addition.50 Simulated output spectrum of the converter when the differentialquad switching disabled. it can be assumed that the source node follows the output voltage of the conducting current branch attenuated by gds of the switch.04 dB on the Nyquist band. The increase of the third harmonic component can be explained as follows by considering a fully thermometercoded D/A converter for simplicity. The simulated SFDR is 62. The simulated spectrum when the differentialquad switching is disabled is presented in Fig.5 Frequency [Hz] 3 3. as presented in Fig. The simulated spectrum when the differentialquad switching is enabled is presented in Fig. The bounce can be either due to capacitive coupling or due to simultaneously conducting switches. 7.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 181 Power spectrum 0 −20 Relative Power [dBc] −40 −60 −80 −100 −120 0 0.5 x 10 4 8 Figure 7. and is limited by the 2nd harmonic (DC component not taken into account).51. 7.5 1 1. gm . The transition on the switch driver signals causes a bounce on the source node of the switches.
RL o+ RL o− DT DT DT DT Vc2 Vc1 Vb DT DT Figure 7.5 1 1.52 Switch driver coupling in differentialquad switching.5 2 2.51 Simulated output spectrum of the converter when the differentialquad switching is enabled.182 Prototypes and experimental results Power spectrum 0 −20 Relative Power [dBc] −40 −60 −80 −100 −120 0 0. .5 x 10 4 8 Figure 7.5 Frequency [Hz] 3 3.
2 (7.21) (7.16) (7.18) (7.23) ∆sn (n) = sn (n) − sn (n − 1) = −∆s (n) 1 s p (n) + (∆s p (n) − ∆s p (n)) 2 1 sn (n) + (∆sn (n) − ∆sn (n)) 2 gds M p (n) s p (n) ⊗ p (t) K gm gds K Mn (n) sn (n) ⊗ p (t) gm in which s (n) = s (nT ) is the smallsignal equivalent of the output for a sinusoidal input (the ”p” and ”n” subscripts stands for positive and negative output. gm and gds are the transconductance and output conductance of the switch. K is a constant that is used to model the attenuation of error from the source of the switches to the output.25) (7.26) .17) (7.22) (7. and e (n) is the error seen at the output due to differentialquad switching.7.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 183 Next. respectively). M (n) is the number of unit currents in the thermometercoded converter that does not change the output branch during the clock period.15) (7. let us deﬁne signals 1 1 + sin (∆φn) 2 2 1 1 sn (n) = 2N − 1 − sin (∆φn) 2 2 ∆s p (n) = s p (n) − s p (n − 1) = ∆s (n) s p (n) = 2N − 1 ∆sn (n) = ∆s p (n) M p (n) = Mn (n) = e p (t) = en (t) = (7. p (t) is the pulse at the source node caused by the transition.24) (7. ∆s (n) corresponds to the discrete time derivative of the output.19) (7. Now it is possible to write an equation for the error signal seen at the differential output as e (t)di f f = e p (t) − en (t) gds =K s p (n)2 − sn (n)2 gm 1 + (s p (n) + sn (n)) ∆s (n) 2 1 − (s p (n) − sn (n)) ∆s (n) ⊗ p (t) 2 gds N 2 =K sin (∆φn) 2 −1 gm 1 + (sin (∆φn) − sin (∆φ (n − 1))) 2 1 − sin (∆φn) − sin (∆φ (n − 1)) sin (∆φn) ⊗ p (t) .20) (7.
The main drawback of the presented method is (in this particular case) the 12. are resolved faster than smaller differences. as in Fig. 7. of the dummy and the MSB switches. In addition to load equalization.7. . The state machine sets the CAL input code and steps down the REF input codes starting from CAL with steps of 4 LSB. This speeds up the calibration. and from the simulation results presented in Section 6. and the ﬁrst calibration cycle starts.184 Prototypes and experimental results which means that instability on the source node of the switches may cause oddorder harmonic distortion when differentialquad switching is used. The method results in an almost identical operating point. There is also the possibility of using a tunable threshold level for comparison in such a manner that. 7. connects the comparator to the output of the converter. the state machine shuts down all the digital blocks that are not needed in calibration. 7. However.79% increase in static power consumption. In order to avoid these imbalances. since the large differences in which the noise does not play an important role. 7. that it is beneﬁcial to use the differentialquad switching scheme even though it seems to reduce the SFDR when the converter is simulated without the powersupplyrail parasitics.55. which takes care of the execution of the calibration algorithm as described in Fig. the timing imbalance was reduced by using a treelike clock and output signaling.51. After the calibration request. 7. Each comparison is repeated a maximum of N times in order to average out the effect of noise. the load of the switch drivers is equalized with dummy structures as presented in Fig. 7.4.5 Logic for digital calibration The principle of the digital calibration method used in this prototype is described in Section 6.50 and Fig. ensuring that the path length from root to leaf is equal for each signal branch. The ”calibration request signal” resets the state machine.54 The functionality of the logic is as follows. The static timing errors due to clock and signal path imbalances may introduce timingrelated harmonic distortion as presented in [145].4. A similar method is also used in [146]. The block diagram of the required DSP for the digital calibration is presented in Fig. if the value of the result counter exceeds the positive or negative threshold. since the distortion is proportional to the output signal as is also the distortion due to the output impedance variation. even though the number of comparisons performed is less than N (N is also programmable from 1 to 2 30 ). and thus in the Cgs . these two sources of distortion are very difﬁcult to distinguish from each other in any other way than disabling the differentialquad switching. the decision is made.2. It can be seen from the experimental results presented later in this chapter.53.
2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 185 o+ o− 1 o+ o− 2 o+ o− 4 o+ o− 8 o+ o− 16 16/16 32/16 64/16 128/16 Vb 16 MSB VDD_dum 15 VDD_dum 14 VDD_dum 12 VDD_dum 8 15 14 12 8 o+ o− 1 8 1/16 o+ o− 1 8 2/16 o+ o− 1 4 4/16 o+ o− 1 2 8/16 VDD_dum 8 VDD_dum 8 VDD_dum 12 VDD_dum 14 8 8 12 14 o+ o− 1 8 1/16 1 32 o+ o− 1 8 1/16 1 16 o+ o− 1 8 1/16 1 8 o+ o− 1 8 1/16 1 4 o+ o− 1 8 1/16 1 2 VDD_dum 8 VDD_dum 8 VDD_dum 8 VDD_dum 8 VDD_dum 8 8 1/8LSB 8 8 8 8 Figure 7.7. .53 Switch driver load balancing with biased dummy structures.
Compare Incr/Decr Res. Load REF val. REF No STEP= 4 LSB IS REF < CAL? Yes Incr. Figure 7. Final CAL val. ? Yes Calc. offset Store cum. Count. Load REF val.186 Prototypes and experimental results Calibration request D/A CORE State− machine Offset Computer Offset selection & Addition Digital Comparator When−to−use Computer Offset MUX Cumulative Offset Memory Load Read Constant offset adder Input Data Constant offset Calc. . Load CAL val. & store const. No Compute cum. REF STEP= 1/8 LSB No IS REF > CAL? Yes Figure 7. Count. offset Set next CAL val.55 State diagram of the calibration. offset No Repeated N times? Yes No Repeated N times? Yes Decr. Compare Incr/Decr Res. Init state No Calibration request? Yes Load CAL val. & mem.54 Block diagram of the calibration logic.
For each of the CAL values corresponding to the MSB current source. the state machine returns to initial state to wait for the calibration request. The constant offset is used to align the input code range to the center of the analog output range.27) where O67 is the cumulative offset for the last MSB current source. The linearization of the conversion is performed in the normal operation mode as follows. 2 (7. since the whole analog output range is not necessarily used. and the usage of the registers and multiplexers enabled the usage of pipelining and parallelism more freely. as presented in Fig.56 . which consists of 67 12bit registers in series. When the output corresponding to the REF value exceeds the output corresponding to the CAL. but the speed requirements could not be met with the memory elements provided by the silicon vendor. the offset is found with 1/8 LSB resolution.7.56 Offset possibilities for the 10bit LSB segment. and the comparison is performed in a manner mentioned above. and the cumulative offset is computed by accumulating the current offsets with the previous ones. the cumulative offset is stored to cumulative offset memory. This is due to the fact that the cumulative offset can be as large as 4x210 LSB = 4MSB.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration Output value 187 O4 O3 O2 O1 O0 Input code T1 T2T3T4 Figure 7. the 67to5 offset MUX selects ﬁve possible offset values. while the converter is in its normal operation mode. For every input data value. the REF code is increased in steps of 1/8LSB. 7. so for each 10bit LSB segments there are ﬁve possible offset values.875 LSB − O67 . Once the output corresponding to the REFcode is less than the output corresponding to the CAL code. After the calibration algorithm is executed. RAMmemories could also be used. a constant offset is computed and stored as Oc = 216 − 1 + 4 ∗ 210 + 0. using stored cumulative offset values for the linearization. After the offset for the last MSB source is found.
6.56) is selected. The chainofampliﬁers type of structure enables the offset voltage cancellation and ampliﬁcation of the signal before the comparison in such a manner that the signal is ampliﬁed. and the key component in the realization of the SAR A/D converter is the comparator.188 S1 S2 S3 Sr In+ Cal/ref from DAC In− Prototypes and experimental results S4 + − − + + − − + + − − + Sr C C + V ref − − + J K C Q Q J K R Q Q OUT S1 S2 S3 S4 S_cal (dac) S1 S2 S3 S_ref(dac) Sr S4 C R Figure 7.3V output with a differential input voltage of 1. the digital comparator is used to compare the input to the whentouse values.6 DNL measurement for calibration The key function of the digital calibration is the successive approximation A/D conversion of the error of the MSB current source. it is justiﬁed to compute the whentouse values separately for each input code rather than use memories. 7.2µV. and the corresponding offset (O0O4 in Fig. 7. and the offset value is selected according to Fig. What is required is a comparator that is able to provide a 3. 7.2. The whentouse computer block is used to calculate the threshold values (T1T4 in Fig.39. Finally. Thus.57) In the design of this comparator chain. The comparator is realized as a chain of singlestage ampliﬁers with offsetcompensation feedback (Fig. but since the memory is the speed bottleneck of the calibration system. since the computation of whentouse value requires only ﬁve subtracters and some registers for pipelining. 7. It would be possible to also store the whentouse values to memory. The simulation result demonstrating the effect of the calibration was presented in Fig. the following aspects are taken into account.56. but only the charge injection of the third ampliﬁer stage in Fig.57 Comparator chain.57 affects the result of the comparison (offset and charge injection of the ﬁrst and second stage . The input code is compared to the whentouse value. a gain of 128dB is needed. half of the minimum step used in calibration. 7.56). which corresponds to 1/16 LSB. 7.
Decoupling capacitors were placed between the supplies and ground in order to stabilize the supply voltages. The measurement board was a 4layer FR4 PCB.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 189 are canceled by the feedback of the third ampliﬁer) [174]. If the REFvalue is larger than the CALvalue the output of the third comparator is positive. and S3 . S2 .57 ) is applied at the input of the comparator chain (i. no compensation is required. whereas the positive supply voltages were distributed with separate supply planes.35µm BiCMOS SiGE process with metalinsulatormetal capacitors. The latchcomparator at the end of the chain is used to further boost the result of the comparison in order to ensure full railtorail signal to be read to digital calibration circuitry. 7. The one comparison cycle is performed as follows. the differential output of the latchcomparator is read to JKﬂipﬂop with signal R.7 Experimental results The circuit was fabricated on a 5 metal 0. 7. the ﬁrst three feedback loops are opened by opening the switches S1 . the CAL value corresponding to the MSB current source to be calibrated (see Section 6. Thermal noise is reduced by maximizing the gm of the input stage of the ampliﬁer which also increases the gain.2.7.59. 7. Increasing the dimensions of the input transistors above a certain point results in attenuation of the signal due to capacitive voltage division between the series capacitors and Cgs of the input stage of the ampliﬁer. After sampling. which also enables the latching comparator. The output of the third comparator is sampled with the signal Sr . Two inner layers were dedicated to ground and supply in such a manner that the ground plane was common to all analog and digital parts.4 and Figs 7. After that. since it introduces a transmission zero on the noise transfer function at the zero frequency [175]. Finally. Circuit diagrams of the ampliﬁer and the latchcomparator are presented in Fig.e. Furthermore the noise bandwidth is reduced by parallel capacitors at the ampliﬁer outputs. output of the D/A converter) by triggering signal S CAL . Since the singlestage ampliﬁers are inherently stable.55 7. Sampling of the difference of CAL and REF will alleviate the 1/fnoise requirements of the ampliﬁers. The chip was packed into a 160pin TQFP package. Using multiple stages makes it also possible to use a simple singlestage differential ampliﬁer as a comparator and obtain the required gain simultaneously.58 and Fig. Then the REFvalue is applied to the input. First. Tunable regulators were used to produce the supply voltages from a single . the feedback of the fourth comparator is opened. otherwise it is negative. The photomicrograph of the circuit is presented in Appendix B. and the bottomplate sampling is completed by closing the switch controlled by the signal C. which would otherwise be the case due to the offsetcancellation unity feedback. triggered with signal SREF .
.190 Prototypes and experimental results Vdd Out− In+ Vbc Out+ In− Vb Vss Figure 7. Q Q C C1D J C1 C1 K Ib C1 C CD C1D Figure 7.58 Singlestage differential ampliﬁer.59 Comparatorlatch.
29 LSB.62 LSB. 7. INL varies between 5. It seems that. .8.51 LSB. the absolute accuracy of the calibration cannot be determined.61.62. The effect of the calibration on the DNL can be clearly seen in Fig. Area and power dissipation characteristics of the converter are presented in Tables 7. due to the limited resolution of the measurement.1 Static linearity The static linearity of the uncalibrated converter was ﬁrst measured in order to discover the linearity achieved by transistor dimensioning and layout techniques.60.26 LSB and 18. respectively.79 LSB to 10. respectively.32 LSB and 7.7 and 7. The DNL and INL curves in the uncalibrated case are presented in Fig.73 LSB and 15.83mm2 D/Acore 5.2.7 Area characteristics Area Calibration logic 5. the prototype seems to function as designed. The static linearity of the uncalibrated D/A converter with 14 LSB offset between the LSB matrix and MSB matrix is presented in Fig.47 LSB to 1.7. The variation of DNL is reduced to vary from 1. In order to discover the effect of calibration. this does not happen. 7. This is due to fact that DNL errors in Fig. 7.62.77mm2 Total 14. Table 7.96 LSB. The maximum and minimum of the DNL are 2.93 LSB. and INL between 4. whereas in Fig.60.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 191 supply voltage input.7. however. DNL varies between 1. even though DNL is reduced due to calibration. 7.60 seem to compensate the accumulation of the DNL from the LSB matrix. while INL varies from 3.8 Power characteristics Power dissipation: Digital@65MS/s D/A core@65MS/s Total 65MS/s Digital@400MS/s D/A core@400MS/s Total 400MS/s Logic bypassed 142mW 95mW 237mW 320mW 306mW 626mW Logic active 406mW 95mW 501mW 1449mW 306mW 1755mW 7. In this case. 7. offset is applied between the binaryweighted LSB and thermometercoded MSB current source matrices. the INL is increased when compared to the results shown in Fig. When it comes to the reduction of DNL.41 LSB.018 LSB and 1. 7.40mm2 Table 7.
60 Static linearity of the uncalibrated D/A converter. Static nonlinearities relative to LSB DNL [LSB’s] 10 0 −10 1 2 3 4 5 Number of sample 6 4 x 10 INL [LSB’s] 10 0 −10 1 2 3 4 5 6 4 x 10 Number of sample Figure 7.192 Prototypes and experimental results Static nonlinearities relative to LSB 2 DNL [LSB’s] 0 −2 1 2 3 4 5 Number of sample 6 4 x 10 INL [LSB’s] 5 0 −5 1 2 3 4 5 Number of sample 6 4 x 10 Figure 7.61 Static linearity of the uncalibrated D/A converter with 14 LSB offset between current source matrices. .
The effect of the powersupplyrail interferenceinduced jitter was analyzed in Section 6. Enabling the toggler also increases the other spurious tones. 7.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 193 Static nonlinearities relative to LSB DNL [LSB’s] 1 0 −1 1 10 2 3 4 5 Number of sample 6 4 x 10 INL [LSB’s] 0 −10 1 2 3 4 5 Number of sample 6 4 x 10 Figure 7. It can be observed that the level image of the third harmonic component is reduced 23. It can be observed that the effect of the differentialquad switching on the third harmonic is less than in the case of the 65Ms/s sample rate. causes an increase in the powerrail interference. whereas the level of the second harmonic component remains the same.75MHz with the differentialquad switching disabled and enabled.64 represents the output spectrum of the converter at sample rate 65Ms/s and signal frequency 22.7. which.67 and Fig.68 represent the output spectrum of the 140MHz sine signal with the differentialquad switching disabled and enabled. respectively.63 and Fig. 7.2 Dynamic performance Fig. 7. Parasitic resistance of the power supply rails explains a large part of the degradation of the SFDR as can be observed from the simulation results with estimated parasitic resistances presented in . together with the toonarrow power supply rails. respectively.65 and 7. Fig.7. Similar measurements were carried out at a 400Ms/s sample rate.7. 7.2. Spurious free dynamic range at a sample rate of 65MS/s as a function of signal frequency are presented in Figs 7. 7.65.18dB .4. This is mainly due to the increased activity of the switch driver circuitry.62 Static linearity of the calibrated D/A converter.
75MHz sine signal with sampling frequency of 65MS/s and differential quad switching enabled. Power Spectrum 0 −10 −20 Relative Power [dB] −30 −40 −50 −60 −70 −80 −90 −100 0 5 10 15 20 25 30 Frequency [MHz] Figure 7.63 Output spectrum of a 22.64 Output spectrum of a 22.194 Prototypes and experimental results Power Spectrum 0 −10 −20 Relative Power [dB] −30 −40 −50 −60 −70 −80 −90 −100 0 5 10 15 20 25 30 Frequency [MHz] Figure 7.75MHz sine signal with sampling frequency of 65MS/s and differentialquad switching disabled. .
70.7. Therefore the digital calibration may become an interesting option with the deep submicron silicon processes. whereas the area required for the current sources will scale down slower. Also scaling down the supply voltages along the scaling of the device size will make it more complicated to implement high performance analog circuitry.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 195 SFDR and Harmonic Distortion 90 SFDR 2nd Harmonic 3rd Harmonic 85 80 75 70 [dBc] 65 60 55 50 45 40 0 5 10 15 20 25 30 Frequency [MHz] Figure 7.2.65 Spurious free dynamic range of the converter sampling frequency of 65MS/s and differential quad switching disabled. even though the matching of the MSB current sources is initially poor. Extensive parallelism. the scaling of the silicon processes will increase the speed and decrease the size of the digital circuitry. 7. 7. in the future.7. in which fast and small memories and digital circuitry are available.71 and Fig. which increases the power dissipation of the circuit. This work reveals that the proposed digital calibration algorithm .72. 7. had to be used. Fig. whereas it alleviates the implementation of the digital part. However.69 and Fig. 7. The measured SFDR curves at 400MS/s sample rate are presented in Fig. the speed requirement of 400MHz is hard to achieve. 7. Parallelism also increases the area required for the calibration.3 Summary The measured performance of the digital calibration algorithm demonstrates that relatively good static performance can be achieved by digital predistortion. With the process used.
66 Spurious free dynamic range of the converter with sampling frequency of 65MS/s and differential quad switching enabled.67 Output spectrum of 140MHz sine signal with sampling frequency of 400MS/s and differentialquad switching disabled. Power Spectrum 0 −10 −20 Relative Power [dB] −30 −40 −50 −60 −70 −80 −90 −100 0 20 40 60 80 100 120 140 160 180 200 Frequency [MHz] Figure 7.196 Prototypes and experimental results SFDR and Harmonic Distortion 90 SFDR 2nd Harmonic with toggler 3rd Harmonic with toggler 85 80 75 70 [dBc] 65 60 55 50 45 40 0 5 10 15 20 25 30 Frequency [MHz] Figure 7. .
7. Power spectrum 0 −20 Relative Power [dBc] −40 −60 −80 −100 −120 0 0.5 2 2.5 Frequency [Hz] 3 3.5 x 10 4 8 Figure 7.5 1 1. .69 Simulated spectrum with estimated parasitic power supply resistances and differentialquad switching disabled.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 197 Power Spectrum 0 −10 −20 Relative Power [dB] −30 −40 −50 −60 −70 −80 −90 −100 0 20 40 60 80 100 120 140 160 180 200 Frequency [MHz] Figure 7.68 Output spectrum of 140MHz sine signal with sampling frequency of 400MS/s and differential quad switching enabled.
.5 2 2.5 Frequency [Hz] 3 3.71 Spurious free dynamic range of the converter with sampling frequency of 400MS/s and differential quad switching disabled.198 Prototypes and experimental results Power spectrum 0 −20 Relative Power [dBc] −40 −60 −80 −100 −120 0 0. SFDR and Harmonic Distortion 70 SFDR 2nd Harmonic 3rd Harmonic 65 60 55 [dBc] 50 45 40 35 30 25 0 20 40 60 80 100 120 140 160 180 200 Frequency [MHz] Figure 7.70 Simulated spectrum with estimated parasitic power supply resistances and differentialquad switching enabled.5 x 10 4 8 Figure 7.5 1 1.
The main shortcoming of the prototype is the poor SFDR with a 400MS/s sampling rate.72 Spurious free dynamic range of the converter with sampling frequency of 400MS/s and differential quad switching enabled. An adequate level of SFDR is achieved with 65 MS/s. indicating that the parasitics are the source of the degradation. The performance degradation was analyzed with simulations including estimates of postlayout parasitic resistances and capacitances.9.2 Prototype of the 16bit 400 MS/s D/A converter with digital calibration 199 SFDR and Harmonic Distortion 70 SFDR 2nd Harmonic with toggler 3rd Harmonic with toggler 65 60 55 [dBc] 50 45 40 35 30 25 0 20 40 60 80 100 120 140 160 180 200 Frequency [MHz] Figure 7. the effect of differentialquad switching was also veriﬁed with simulations and measurements revealing its effectiveness in reducing oddorder harmonic distortion. The measured dynamic performance of the converter differs from the simulated initial performance (Fig. Also. 7.7. . is a feasible way to perform the calibration of a current steering D/A converter.50) quite a lot due to the fact that the parasitic resistances were underestimated in the layout design phase. The postmeasurement simulations and simulation results match quite well. resulting in an excessive amount of signaldependent jitter. 7.51 and Fig. The quality of performance of the implemented prototype and the recently published converters are presented in Table 7.
18µm CMOS 0.41 2.5 61.73/ 15.32/ 7.2/ 0.5/ 0.35µm CMOS Bits Sampl.6 1.05/ 0.18µm CMOS 0.62 1.2/ 0.6 0.4 0.18µm CMOS 0.6 1.5µm CMOS 0.5 0.6/ 0.5/ 0.15/ 0.25µm CMOS 0.5 61 @ 5 72 @ 42.3/ 0.96 5.35µm CMOS 0.2/ 0.5 3/ 3 0.13µm CMOS 0.5 0.5/ 0.3/ 0.5 0.3/ ? 0.7 0.18/ 0.35 0.1 0.5µm CMOS 0.1 0.15 0.18µm CMOS 0.4 0.2 0.6/ 0.5/ 0.5/ 0.4/ 0.93 Comment SFDR @ 10MS/s No minmax DNL 12 500 14 14 16 14 12 14 14 12 16 100 180 400 300 320 200 1400 500 65 RZmode No minmax DNL/INL Calibrated DNL/INL Uncalibrated DNL/INL Worst case DNL/INL This work This work 16 400 .25 0.5 4/ 4 0.200 Prototypes and experimental results Table 7.14/ 0.6/ 0.3 0.35µm CMOS 0.02/ 1.11 @ 195 DNL max/ min 0.68 41.5 0.5/ 0.2 0.2/ 0.25 0.35µm CMOS 0.23 51 @ 240 40 @ 60 74 @ 8.08 0.3/ 0.25 0.35µm CMOS 0.25/ 0.3 0.89 INL max/ min 0.8 0.3 0.25µm CMOS 0.47/ 1.26/ 18.3 0.5µm CMOS 0.79/ 10.5/ 0.3 0.18µm CMOS 0.35/ 0.9 @ 31.9 Comparison of the prototype and recently published D/A converters Publication Process Nakamura [154] Mercer [160] Lin [126] Bastos [155] Bugeja1 [161] Van der Plas [158] Bugeja2 [162] Van den Bosch1 [164] Van den Bosch2 [163] Tiilikainen [137] Cong [138] Schoﬁeld [139] Hyde [165] O’Sullivan [166] Huang1 [167] Schafferer [168] Doris [146] This work 1µm CMOS 2µm BiCMOS 0.51 4.3/ 0.25 0.4/ 0.3/ 0.8 1/ 1 3.18µm CMOS 0. [dBc] [MHz] @ [MHz] 10 70 ? 16 10 12 14 14 14 10 40 500 300 100 150 100 1000 80 @ 1.2/ 0.2 @ 490 62 @ 125 64 @ 1 50 @ 63 73 @ 190 71 @ 120 60 @ 60 60 @ 90 67 @ 260 60 @ 220 62. SFDR freq.
which is very suitable for VLSI implementation and performs the modulation without digital multipliers. which are usually considered area consuming. In the world of multiple standards. was studied. or if the system is reconﬁgurable. The root raised cosine ﬁlter was designed with the Langrangeoptimization algorithm in order to achieve adequate EV M and ALCR for the 3G WCDMA system. the multicarrier signal was formed by summation of eight independent datapaths on four carrier frequencies. the research of digital signal processing and D/A converters for digitalIF transmitters is presented. In this book. Polyphase structures. making way for 3G systems. The theory of the transmitters and the signal processing. The wireless digital communications have evolved through services such as GPRS and EDGE towards the WCDMA and 3G. The trend has been to move from analog to digital signal processing and increase the bandwidth. The transmitter prototype consists of an interpolateby16 interpolation ﬁlter chain including a rootraised cosine pulse shaping ﬁlter and three halfband ﬁlters. Simultaneously. Upconversion to the digital IF frequency was performed with a digital modulator based on a CORDIC vector rotation algorithm. and the result was converted to the analog domain with a 14bit currentsteering D/A converter. The ﬁrst part of the book represents the research results obtained during the design of the multicarrier digital IF transmitter prototype for a WCDMA basestation transmitter. common subexpression sharing and time interleaving was used in order to reduce the amount of hardware in the ﬁlters. . while nowadays the ﬁrst digital wireless systems like GSM are at the end of the trail. it is beneﬁcial if a single system is capable of handling multiple standards.Conclusions Wireless communications have been the driving force of the development of the integrated circuits during the last decade. and efﬁcient DSP realizations. and ﬁnally the experimental results were presented. The knowledge gained was then applied to the practical design. which is capable of handling both the narrow voice band and wide data bands. CSDmultipliers. After upconversion. the wireless data transmission systems such as WLAN/WiFi and Wimax have gained popularity. This kind of ﬂexibility can be obtained by using digital signal processing in transmitters and receivers. It started with analog.
and that the quality requirements of the 3G WCDMA transmitter can be met. and published in [176]. the size of the digital part will scale down and the speed will increase. The model for the static linearity was developed and the effect of the output impedance was analyzed. The currentsteering D/A converter is a complex entity composed of various details. It was demonstrated with the prototype that digital predistortion is one possible way to realize the calibration of the currentsteering D/A converter. since moreandmore signal processing will be performed digitally. whereas the requirements for the matching (and thus area) of the MSB sources are alleviated. In the future. all of which have to be considered and designed carefully in order to achieve good performance. . The future of the IC’s seems to be mainly digital. dynamic linearity and timing jitter. However. the real world is analog and the conversion between the two worlds cannot be avoided. In the future. due to the decreasing cost of digital signal processing.202 Prototypes and experimental results The SINCattenuation due to the sampleandhold function of the D/A converter is canceled with an inverseSINC predistortion ﬁlter. This will increase the demand for the various digital enhancement algorithms of analogsignal processing. the requirement for highquality highspeed D/A converters will increase. The second part of the book is about the design of the currentsteering D/A converters. Further research into sophisticated signal clipping methods has been carried out at ECDL by Olli Väänänen. The main difﬁculty is the measurement of the nonlinearity and the realization of the DSP required for the predistortion. A digital calibration method based on predistortion was developed and implemented. Optimization of the dynamic range of the signal was also considered brieﬂy. Experimental results from the transmitter prototype indicate that the selected architecture is suitable for integrated digital IF multicarrier modulator. whereas the analog signal processing will become moreandmore challenging making digital predistortion technique moreandmore attractive. The performance of the transmitter is limited by the D/A converter. resulting in reasonable area and power dissipation. as is the case when a dedicated calibration DAC is used to tune the values of the MSB current source. This method has the advantage of having practically no matching requirement for the additional analog current sources. The theory part of this book represents the problem scope related to static linearity.
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1 Photomicrograph of the circuit. .Appendix A Photomicrograph of the WCDMA transmitter Figure A.
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Appendix B Photomicrograph of the D/A converter with digital calibration Figure B.1 Photomicrograph of the circuit. .
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in which ∆x (n) = x (n) − x (n − 1) and u (t) is a unit step function. (C. therefore not affecting the energy of the signals.Appendix C Jitter energy as a function of signal frequency and jitter amplitude The continuous time error signal e (t) due to timing jitter is deﬁned by the jitter signal w (n) and the discretetime derivative ∆x (n) of the signal x (n) as e (t) = = n=−∞ ∞ n=−∞ ∑ ∞ ∆x (n) g (t) [x (nT ) − x ((n − 1) T )] (C. E [w (n)] = 0 E [w (n) − w (n − 1)] = 0.3) equal to change in sampling period T . The power of the error signal due to jitter can be computed as Pj = lim 1 C→∞ C Z C since E [w (n)] = 0 results in time shift of the signal and E [w (n) − w (n − 1)] = 0 is 0 n=−∞ ∑ ∞ ∆x (n)2 × (u (t − nT − w (n)) − u (t − nT ))2 dt (C.4) . w (n) has the following properties.1) ∑ × [u (t − nT − w (n))) − u (t − nT )].2) (C.
5) (C. that x (n) is a sinusoidal signal x (n) = A sin (∆φn) 2πFsig ∆φ = . in which µd = E ∆x (n)2 and µa = E [w (n)].10) (C.9) (C.224 N Jitter energy as a function of signal frequency and jitter amplitude = lim = ∑ NT ∆x (n)2 N→∞ n=0 1 Z nT +w(n) nT (u (t − nT − w (n)) − u (t − nT )) dt (C. E [yz] ρ= . By substituting y = ∆x (n)2 − µd z = w (n) − µa .13) and w (n) is an arbitrary jitter signal independent of x (n) In this case the power of the error signal due to jitter can be computed as Pj = E ∆x2 E [x] = A2 (1 − cos (∆φ)) E = A2 1 − cos 2πFsig Fs w (n) T E w (n) . T (C.16) in which the value of the E w(n) is deﬁned by the probability distribution and is T linearly dependent on the standard deviation.14) (C.6 can be written as Pj = ρσy σz + µd µa . Eq. ∆x (n)2 and w (n) are independent resulting in Pj = µd µa = E ∆x (n)2 E [w (n)] .6) 1 E ∆x (n)2 w (n) T in which E [] means expectation. Fsig ≤ Fs /2. . (C.11) Let us assume. σy σz (C.8) In case correlation factor ρ = 0. It is possible to calculate E For sine signal E a sin (2πnT j ) = 2a . C. Fs (C.7) (C.17) w(n) T for some typical jitter signals.12) (C. π (C.15) (C.
σ))] = a For uniformly distributed noise − 2 ≥ w (n) ≤ 2 σ. the only combination of n − k resulting in nonzero value is when n = k. π a 2 (C. 0) Gaussian jitter can be derived as follows. Since the expectation of cos (ωw (nT )) with Gaussian N (σw .21) and E ( jω)2 = Re {E ( jω)}2 + Im {E ( jω)}2 ∞ ∞ ∆x (n) ∆x (k) − jωnT jωkT = ∑ ∑ 1 − e jωw(nT ) e e ω2 n=−∞ k=−∞ = ∆x (n) ∆x (k) cos (ω (n − k) T ) ω2 n=−∞ k=−∞ (C. cos (ω (n − k) T ) and w (nT ). and E ( jω)2 becomes ∆x (n)2 (2 − 2 cos (ωw (nT ))) .22) 1 − e− jωw(kT ) ∑ ∑ ∞ ∞ × (1 − cos (ωw (nT )) − cos (ωw (kT )) + cos (ω (w (nT ) − w (kT )))) Assuming that there is no correlation between ∆x (n). ∑ 2 n=−∞ ω ∞ E ( jω)2 = (C.25) and E ∆x (n)2 = VAR [∆x (n)] (C. (C.26) . 0) distributed w (nT ) is −ω2 σ2 w 2 E [cos (ωw (nT ))] = e .225 For Gaussian white noise E [N (0. 4 2 2 3 (C.23) The PSD function of the error signal is obtained by computing the expectation of E ( jω)2 .19) The power spectral density (PSD) function of error signal due to N (σw .σ = √ .18) √ 3 a a E [w (n)] = = σ .24) (C.20) (C. The Fourier transform of the jitter signal can be written as E ( jω) = ∆x (n) − jωnT 1 − e jω(nT ) e − jω −∞ ∑ ∞ (C.
(C. (C. thus following Parceval’s theorem.226 Jitter energy as a function of signal frequency and jitter amplitude (C. the PSD function can be expressed as 2 − 2e− 2 S ( f ) = VAR [∆x (n)] 4 ∗ π2 ∗ f 2 4π2 f 2 σ2 w .27) when ∆x (n) has zero mean.29) The power of the error signal on a certain frequency band −Fb to Fb can be obtained by integrating S ( f ) resulting in Pj (Fb ) = A2 1 − cos 2π × where √ erf 2πFb σw = Z √2πFb σw 0 Fsig Fs √ √ √ 2 F 2 s2 e−2π b + π 2πFb σw erf 2πFb σw − 1 π2 Fb (C.32) The ﬁrstorder Taylor series approximation of Pj (Fb ) is Pj (Fb ) ≈ 2A2 1 − cos 2π The total error power is obtained by lim Pj (Fb ) = A2 1 − cos 2π Fsig Fs 2 σw .31) e−x dx. (C. the PSD function is 2 S(f) = A Fsig 1 − cos 2π Fs 2 − 2e− 2 4 ∗ π2 ∗ f 2 (2π f )2 σ2 w . 2 (C.34) Fsig Fs Fb σ2 w (C. π (C.28) For a sinusoidal signal x (n) at frequency Fsig . .30) . (C.16) with Gaussian jitter.33) Fb →∞ which is equal to Eq.
3) D. Fs = 1 Ts (D.5) .1 Elementary relations Notation for transformation F {x (t)} = X ( f ) Time shift (D.Appendix D Fourier transforms of some functions used in this book D.2 Elementary functions and operations Sampling function F n=−∞ ∑ ∞ δ (t − nTs ) = n=−∞ ∑ ∞ e− jωnTs (D.2) F x′ (t) = jωX ( f ) (D.1) F {x (t + τ)} = X ( f ) e− jωτ Derivative (D.4) According to Poisson’s sum formula n=−∞ ∑ ∞ e− jωnTs ↔ Fs n=−∞ ∑ ∞ δ ( f − nFs ) .
(D. f0 = 2 2π (D. f0 = j2 2π (D. Fs = F {A sin (ω0t)} = Cosine ω0 A (δ ( f − f0 ) − δ ( f + f0 )) .7) = 1 − e j2π Fs Fs Sine n=−∞ ∑ ∞ X ( f − nFs ) .1 Trapezoid pulse. A t (u (t) − u (t − Tr )) Tr +Tc (u (t − Tr ) − u (t − (Tr + Tc ))) (t − Tr − Tc ) Tc + Tc − Tf × (u (t − (Tr + Tc )) − u (t − (Tr + Tc + T f ))) A A e− jωTt − 1 e− jω(Tr +T c) F {x (t)} = 2 e− jωTr − 1 − 2 ω Tr ω Tf x (t) = Tr Tr 2 jA − jω 2 jA − 2 e− jω 2 sin ω + 2 e ω Tr 2 ω Tf T Tr +T c+ 2f (D.1) A ω0 (δ ( f − f0 ) + δ ( f + f0 )) . Fs = 1 Ts (D.8) F {A cos (ω0t)} = Trapezoidal pulse (Figure D.9) A 0 Tr Tc Tf Figure D.228 Fourier transforms of some functions used in this book Sampling F x (t) n=−∞ ∑ ∞ δ (t − nTs ) = Fs n=−∞ ∑ ∞ X ( f − nFs ) .10) sin ω Tf .6) Discrete time derivative F (x (t) − x (t − Ts )) f n=−∞ ∑ ∞ δ (t − nTs ) 1 Ts (D.11) 2 .
D.14) (D. .13) A 0 Tr Figure D.D.2 Elementary functions and operations 229 If Tr = T f = TT we get F {x (t)} = 4A − jω(TT + Tc ) ω (TT + Tc ) ωTT 2 sin e sin 2T ω T 2 2 (D.2 Ramp pulse.3) (D.12) The Fourier transform of a triangular pulse with equal rise and fall times is obtained by setting Tc = 0 in Eq.2) sin2 π f TT (π f TT )2 (D.15) A 0 Tc Figure D. A t (u (t) − u (t − Tr )) Tr A A F {x (t)} = 2 e− jωTr − 1 − e− jωTr ω Tr jω x (t) = Rectangular pulse (Figure D.3 Rectangular pulse.12 resulting in F {x (t)} = 4ATT e− jωTT Ramp pulse (Figure D.
17) (D.230 Fourier transforms of some functions used in this book x (t) = A (u (t) − u (t − Tc )) A 1 − e− jωTc F {x (t)} = jω sin π f Tc = Tc Ae jωTc π f Tc (D.19) Absolute value function of a zeromean periodic signal x (t) with 50% duty cycle −sgn (0+ ) e− jωτ f0 sin2 jπ f π 2 f0 F {x (t)} = n=−∞ ∑ ∞ δ ( f − n f0 ) ⊗ X ( f ) (D. F {sgn (x (t))} = −sgn (0+ ) e− jωτ f0 sin2 jπ f π 2 f0 n=−∞ ∑ ∞ δ ( f − n f0 ) (D.4 Signum function of signal with 50% duty cycle and time shift τ.16) (D.20) .18) Signum function of a zeromean periodic signal x (t) with 50% duty cycle (Figure D.4) +1 τ sgn(0+) t −1 T0 Figure D.
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