Contents

General Details of 8086 Microprocessor
Overview or Features of 8086 Pin Diagram of 8086 and Pin description of 8086 Pin description of 8086 -(contd..) Architechture of 8086 or Functional Block diagram of 8086 Explanation of Architechture of 8086 General Bus Operation Definition and Explanation of Minimum Mode 8086 System

Internal Registers of 8086
General purpose registers(4) of 8086 Index/Pointer registers(4) Segment registers(4) Other registers(2)

Addressing Modes of 8086
Addressing Modes - an overview and classification of 8086 Immediate addressing

Register addressing Memory addressingand its classification (i)Direct , (ii)Register indirect (iii)Based , (iv)Indexed (v)Based-indexed ,(vi)Based-indexed with displacement

Instruction Set of 8086
Classification of 8086 Instruction set Complete 8086 Instruction set with clear Explanation and sample Programs

Interrupts of 8086
Definition, Types of Interrupts of 8086 Performance of Software Interrupts of 8086 Performance of Hardware Interrupts of 8086

Timing Diagram
Write Cycle Timing Diagram for Minimum Mode Bus Request and Bus Grant Timings in Minimum Mode System of 8086 Definition and Explanation Maximum Mode 8086 System Memory Read Timing Diagram in Maximum Mode of 8086

Memory Write Timing Diagram in Maximum Mode of 8086 RQ/GT Timings in Maximum Mode

Interfacing
Minimum Mode Interface Maximum Mode Interface

Example Programs of 8086
Write an 8086 Program to add two packed BCD numbers entered through keyboard

Frequency range of 8086 is 6-10 MHz It has multiplexed address and data bus AD0. 16 -bit registers. 8086 has a 20 bit address bus can access up to 220= 1 MB memory locations.General Details of 8086 Microprocessor Overview or Features of 8086 · · · · · · · · · · · · It is a 16-bit Microprocessor(µp). 8086 is designed to operate in two modes. It can support up to 64K I/O ports. A 40 pin dual in line package. It requires +5V power supply. o The minimum mode is selected by applying logic 1 to the MN / MX# input pin. It requires single phase clock with 33% duty cycle to provide internal timing. Minimum mode and Maximum mode. It can read or write data to a memory/port either 16bits or 8 bit at a time. internal registers works with 16bit binary word. . o The maximum mode is selected by applying logic 0 to the MN / MX# input pin. This is a multi micro processors configuration.AD15 and A16 – A19.It’s ALU. It can prefetch upto 6 instruction bytes from memory and queues them in order to speed up instruction execution. This is a single microprocessor configuration. 8086 has a 16bit data bus. It provides 14.

. The 8086 signals can be categorised in three groups. The 8086 operates in single processor or multiprocessor configuration to achieve high performance.Pin Diagram of 8086 and Pin description of 8086 Figure shows the Pin diagram of 8086. o The first are the signal having common functions in minimum as well as maximum mode. o The second are the signals which have special functions for minimum mode o The third are the signals having special functions for maximum mode. The pins serve a particular function in minimum mode (single processor mode ) and other function in maximum mode configuration (multiprocessor mode ). · · · · The Microprocessor 8086 is a 16-bit CPU available in different clock rates and packaged in a 40 pin CERDIP or plastic package. The description follows it. The following signal descriptions are common for both modes.

A16/S3 : These are the time multiplexed address and status lines. T3. It goes low for the data transfer over D15-D8 and is used to derive chip selects of odd address memory bank or peripherals. S4 S3 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Indication Alternate Data Stack Code or None Data Whole word Upper byte from or to even address Lower byte from or to even address · BHE/S7 : The bus high enable is used to indicate the transfer of data over the higher order ( D15-D8 ) data bus as shown in table. o During memory or I/O operations. o The S4 and S3 combinely indicate which segment register is presently being used for memory accesses as in below fig.A17/S4.Tw and T4. o During T1 these are the most significant address lines for memory operations. o During I/O operations. while the data is available on the data bus during T2. these lines are low. BHE is low during T1 for read. write and interrupt . A19/S6. o The address bit are separated from the status bit using latches controlled by the ALE signal. Tw and T4. The status line S6 is always low.A18/S5. o The status of the interrupt enable flag bit is updated at the beginning of each clock cycle.· · AD15-AD0 : These are the time multiplexed memory I/O address and data lines. These lines are active high and float to a tristate during interrupt acknowledge and local bus hold acknowledge cycles. o These lines float to tri-state off during the local bus hold acknowledge.T3. status information is available on those lines for T2. o Address remains on the lines during T1 state.

the signal is active high. T3 and T4. If the TEST pin goes low. else the processor remains in an idle state. INTR-Interrupt Request : This is a triggered input. · RD – Read : This signal on low indicates the peripheral that the processor is performing memory or I/O read operation.Clock Input : The clock input provides the basic timing for processor operation and bus control activity. RD is active low and shows the state for T2. The signal is active low and tristated during hold. If any interrupt request is pending.acknowledge cycles. This is sampled during the last clock cycles of each instruction to determine the availability of the request. This can be internally masked by resulting the interrupt enable flag. TEST : This input is examined by a ‘WAIT’ instruction. · · · · . Its an asymmetric square wave with 33% duty cycle. The status information is available during T2. whenever a byte is to be transferred on higher byte of data bus. Tw of any read cycle. CLK. T3. the processor enters the interrupt acknowledge cycle. It is low during T1 for the first pulse of the interrupt acknowledge cycle. READY : This is the acknowledgement from the slow device or memory that they have completed the data transfer. execution will continue. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086. The signal remains tristated during the hold acknowledge. This signal is active high and internally synchronized. The input is synchronized internally during each clock cycle on leading edge of clock.

When it is low. · .Figure shows the Pin functions of 8086. INTA – Interrupt Acknowledge : This signal is used as a read strobe for interrupt acknowledge cycles. · functions are for the minimum mode M/IO – Memory/IO : This is a status line logically equivalent to S2 in maximum mode. the processor has accepted the interrupt. This line becomes active high in the previous T4 and remains active till final T4 of the current cycle. and when it is high. it indicates that the CPU is having a memory operation. i. The following pin operation of 8086. when it goes low. it indicates the CPU is having an I/O operation.e. It is tristated during local bus “hold acknowledge “.

The current cycle is not operating over the lower byte of a word. S0 – Status Lines : These are the status lines which reflect the type of operation. this signal is low. A Lock instruction is not being executed. it lowers the HLDA signal. When the processor detects the HOLD line low. and is should be externally synchronized. · S2. It is used to enable the transreceivers ( bidirectional buffers ) to separate the data from the multiplexed address/data signal. HOLD. in the middle of the next clock cycle after completing the current bus cycle. it will release the local bus during T4 provided : · · · · 1. this signal is high and when the processor is receiving data. 2. the processor floats the local bus and control lines. It is active from the middle of T2 until the middle of T4. 4. HLDA. 3. . The processor. and is connected to latch enable input of latches. issues the hold acknowledge signal on HLDA pin. At the same time.Acknowledge : When the HOLD line goes high. it indicates to the processor that another master is requesting the bus access. When the processor sends out data. These become activity during T4 of the previous cycle and active during T1 and T2 of the current bus cycles. If the DMA request is made while the CPU is performing a memory or I/O cycle. S1. HOLD is an asynchronous input. after receiving the HOLD request. DT/R – Data Transmit/Receive: This output is used to decide the direction of data flow through the transreceivers (bidirectional buffers). This is tristated during ‘ hold acknowledge’ cycle.· ALE – Address Latch Enable : This output signal indicates the availability of the valid address on the address/data lines. The following pin functions are applicable for maximum mode operation of 8086. being carried out by the processor. This signal is active high and is never tristated. DEN – Data Enable : This signal indicates the availability of valid data over the address/data lines.The request occurs on or before T2 state of the current cycle.The current cycle is not the first acknowledge of an interrupt acknowledge sequence.

there is a considerable speeding up in instruction execution in 8086. The LOCK signal is activated by the ‘LOCK’ prefix instruction and remains active until the completion of the next instruction. By prefetching the instruction. the queue will be empty an the microprocessor starts a fetch operation to bring one byte (the first byte) of instruction code. while the LOCK signal is low. which may be connected to an external bus controller.· LOCK : This output pin indicates that other system bus master will be prevented fromgaining the system bus. · . if the CS:IP address is odd or two bytes at a time. the LOCK prefix instruction ensures that other processors connected in the system will not gain the control of the bus. The first byte is a complete opcode in case of some instruction (one byte opcode instruction) and is a part of opcode. Initially. in case of some instructions ( two byte opcode instructions). asserts the bus lock signal output. The 8086. if the CS:IP address is even. the remaining part of code lie in second byte. while executing the prefixed instruction. When the CPU is executing a critical instruction which requires the system bus. S2 0 0 0 0 1 1 1 1 · S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Indication Interrupt Acknowledge Read I/O port Write I/O port Halt Code Access Read Memory Write Memory Passive At the starting the CS:IP is loaded with the required address from which the execution is to be started. This is known as instruction pipelining.

Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1. namely Execution unit and Bus interface unit. QS1 QS0 0 0 1 1 0 1 0 1 Indication No Operation First Byte of the opcode from the queue Empty Queue Subsequent Byte from the Queue · · · RQ/GT0. RQ/GT pins have internal pull-up resistors and may be left unconnected. RQ/GT1 – Request/Grant : These pins are used by the other local bus master in maximum mode. As in the architecture. 2. the bus interface unit may be fetching the bytes of the next instruction from memory. While the execution unit is busy in executing an instruction.· The second byte is then decoded in continuation with the first byte to decide the instruction length and the number of subsequent bytes to be treated as instruction data. a pulse one clock wide from 8086 to the requesting master. The queue is updated after every byte is read from the queue but the fetch cycle is initiated by BIU only if at least two bytes of the queue are empty and the EU may be concurrently executing the fetched instructions.During T4(current) or T1(next) clock cycle. The fetch operation of the next instruction is overlapped with the execution of the current instruction. A similar procedure is repeated till the complete execution of the program. indicates that the 8086 has allowed the local bus to float and that it will enter the ‘hold . after it is completely decoded. to force the processor to release the local bus at the end of the processor current bus cycle. The next byte after the instruction is completed is again the first opcode byte of the next instruction. Request/Grant sequence is as follows: · 1. there are two separate units. depending upon the queue status.A pulse of one clock wide from another bus master requests the bus access to 8086.

reading and writing operands for memory and calculating the addresses of the memory operands. The BIU performs all bus operations such as instruction fetching. Instruction decoder. There must be at least one dead clock cycle after each bus exchange. · · · · · .For the bus request those are received while 8086 is performing memory or I/O cycle. Thus each master to master exchange of the local bus is a sequence of 3 pulses. The request and grant pulses are active low. ALU. The CPU bus interface unit is likely to be disconnected from the local bus of the system. EU contains Control circuitry. Instruction pointer. Architechture of 8086 or Functional Block diagram of 8086 · 8086 has two blocks Bus Interfacing Unit(BIU) and Execution Unit(EU). Pointer and Index register. Segment registers. EU executes instructions from the instruction system byte queue. 3.Flag register. Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining.acknowledge’ state at next cycle. This results in efficient use of the system bus and system performance. BIU contains Instruction queue. Address adder.A one clock wide pulse from the another master indicates to the 8086 that the hold request is about to end and the 8086 may regain control of the local bus at the next clock cycle. The instruction bytes are transferred to the instruction queue. the granting of the bus is governed by the rules as in case of HOLD and HLDA in minimum mode.

Explanation of Architechture of 8086 BUS INTERFACE UNIT: · It provides a full 16 bit bidirectional data bus and 20 bit address bus. Specifically it has the following functions: · · · Instruction fetch. Instruction queuing. . Address relocation and Bus control. Operand fetch and storage. The bus interface unit is responsible for performing all external bus operations.

For example: The physical address of the next instruction to be fetched is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register.· The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture. These intervals of no bus activity. It reads one instruction byte after the other from the output of the queue. the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle. The BIU also contains a dedicated adder which is used to generate the 20bit physical address that is output on the address bus. If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O. the BIU is free to look ahead in the program by prefetching the next sequential instruction. After a byte is loaded at the input end of the queue. The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write. If the queue is full and the EU is not requesting access to operand in memory. it automatically shifts up through the FIFO to the empty location nearest the output. With its 16 bit data bus. These prefetching instructions are held in its FIFO queue. which may occur between bus cycles are known as Idle state. it has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory. When ever the queue of the BIU is not full. The EU accesses the queue from the output end. This queue permits prefetch of up to six bytes of instruction code. the BIU fetches two instruction bytes in a single memory cycle. · · · · · · · · · . This address is formed by adding an appended 16 bit segment address and a 16 bit offset address.

T2. passes them to the BIU and requests it to perform the read or write bys cycles to memory or I/O and perform the operation specified by the instruction on the operands. The main reason behind multiplexing address and data over the same pins is the maximum utilisation of processor pins and it facilitates the use of 40 pin standard DIP package. the BIU automatically resets the queue and then begins to fetch instructions from this new location to refill the queue. · · · · · General Bus Operation · · · · · The 8086 has a combined address and data bus commonly referred as a time multiplexed address and data bus. . Whenever this happens. when ever required. T4. generates operands if necessary. The EU extracts instructions from the top of the queue in the BIU. During the execution of the instruction. Basically. It is present on the bus only for one cycle.EXECUTION UNIT · The Execution unit is responsible for decoding and executing all instructions. the status lines S0. The negative edge of this ALE pulse is used to separate the address and the data or status information. it transfers control to a location corresponding to another set of sequential instructions. The bus can be demultiplexed using a few latches and transreceivers. S1 and S2 are used to indicate the type of operation. If the queue is empty. all the processor bus cycles consist of at least four clock cycles. When the EU executes a branch or jump instruction. decodes them. the EU waits for the next instruction byte to be fetched and shifted to top of the queue. the EU tests the status and control flags and updates them based on the results of executing the instruction. In maximum mode. These are referred to as T1. The address is transmitted by the processor during T1. T3.

the processor derives the status signal S2. In this mode. In the maximum mode. Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4. Minimum mode · · In a minimum mode 8086 system. S0. S1. the 8086 is operated by strapping the MN/MX pin to ground.· Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal. the microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1. In this mode. there may be more than one microprocessor in the system configuration. Maximum mode · · · In the maximum mode. Another chip called bus controller derives the control signal using this status information . . all the control signals are given out by the microprocessor chip itself.

using the information by the processor on the status lines. AMWC. The AEN. These inputs to 8288 are driven by CPU. ALE etc. there may be more than one microprocessor in the system configuration. DEN. S0 and CLK. IOWC and AIOWC. S1. the processor derives the status signal S2. The basic function of the bus controller chip IC8288. the 8086 is operated by strapping the MN/MX pin to ground. The components in the system are same as in the minimum mode system. The bus controller chip has input lines S2. In the maximum mode. is to derive control signals like RD and WR ( for memory and I/O devices). S0.· There is a single microprocessor in the minimum mode system. Another chip called bus controller derives the control signal using this status information . S1. MRDC. It derives the outputs ALE. DEN. DT/R. . IOB and CEN pins are specially useful for multiprocessor systems. DT/R. IORC. Maximum Mode 8086 System · · · · · · · In the maximum mode. In this mode. MWTC.

MWTC are memory read command and memory write command signals respectively and may be used as memory read or write signals. CEN pin is usually tied to +5V. the advanced signals namely AIOWC and AMWTC are available.· · · · · · · · AEN and IOB are generally grounded. For both of these write command signals. it acts as master cascade enable to control cascade 8259A. IOWC are I/O read command and I/O write command signals respectively. . These signals enable an IO interface to read or write the data from or to the address port. INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting device. IORC. All these command signals instructs the memory to accept or send data from or to the bus. If IOB is grounded. The MRDC. The significance of the MCE/PDEN output depends upon the status of the IOB pin. else it acts as peripheral data enable used in the multiple bus configurations.

DEN and DT/R. They are used for separating the valid address from the multiplexed address/data signals and are controlled by the ALE signal generated by 8086. The remaining components in the system are latches. depending upon the address map of the system. clock generator. 8288 will set DEN=1 thus enabling transceivers.There is a single microprocessor in the minimum mode system. Some type of chip selection logic may be required for selecting memory or I/O devices. transreceivers. Transreceivers are the bidirectional buffers and some times they are called as data amplifiers.· · · · · Here the only difference between in timing diagram between minimum mode and maximum mode is the status signals used and the available control and advanced command signals. memory and I/O devices. the microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1. wait state will be inserted between T3 and T4. · · · · · . all the control signals are given out by the microprocessor chip itself. They are required to separate the valid data from the time multiplexed address/data signals. Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. S2 are set at the beginning of bus cycle. For an output. the AMWC or AIOWC is activated from T2 to T4 and MWTC or IOWC is activated from T3 to T4. In this mode.8288 bus controller will output a pulse as on the ALE and apply a required signal to its DT / R pin during T1. They are controlled by two signals namely. and for an input it will activate MRDC or IORC. Minimum Mode 8086 System · In a minimum mode 8086 system. These signals are activated until T4. The status bit S0 to S2 remains active until T3 and become passive during T3 and T4. In T2. R0. If reader input is not activated before T3. S1.

The system contains memory for the monitor and users program storage. A system may contain I/O devices. Accumulator can be used for I/O operations and string manipulation. while RAM for users program storage. BX register usually contains a data pointer used for based. and AH contains the highorder byte.e. from or to the processor. Usually. which can be combined together and used as a 16-bit register BX. It is divided into four groups. AL in this case contains the loworder byte of the word. Base register consists of two 8-bit registers BL and BH. EPROM are used for monitor storage. i. · Internal Registers of 8086 General purpose registers The 8086 microprocessor has a total of fourteen registers that are accessible to the programmer. and BH contains the highorder byte. They are: · · · · Four Four Four Two General purpose registers Index/Pointer registers Segment registers Other registers General purpose registers : Accumulator register consists of two 8-bit registers AL and AH.· The DEN signal indicates the direction of data. BL in this case contains the low-order byte of the word. which can be combined together and used as a 16-bit register AX. based indexed or register indirect addressing. .

Unlike the SP register. and DH contains the high-order byte. ie it is used to hold the address of the top of stack. SI is used for indexed. When combined. When combined. The stack is maintained as a LIFO with its bottom at the start of the stack segment (specified by the SS segment register). BP register is usually used for based. CL register contains the loworder byte of the word. based indexed or register indirect addressing.Count register consists of two 8-bit registers CL and CH. which can be combined together and used as a 16-bit register DX. Count register can be used in Loop. DL register contains the low order byte of the word. It is usually used by subroutines to locate variables that were passed on the stack by a calling program. Stack Pointer (SP) is a 16-bit register pointing to program stack. based indexed and register indirect addressing. shift/rotate instructions and as a counter in string manipulation Data register consists of two 8-bit registers DL and DH. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number. Used in conjunction with the DS register to point to data locations in the data segment. Source Index (SI) is a 16-bit register. Data register can be used as a port number in I/O operations. Index or Pointer Registers These registers can also be called as Special Purpose registers. Base Pointer (BP) is a 16-bit register pointing to data in stack segment. the BP can be used to specify the offset of other program segments. which can be combined together and used as a 16-bit register CX. . as well as a source data address in string manipulation instructions. and CH contains the high-order byte.

Destination Index and SI Source Index registers are used to hold address. Used in conjunction with the ES register in string operations. Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. far call and far return instructions. The CS register is automatically updated during far jump. Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. CS register cannot be changed directly. DI) is located in the data segment. Segment registers cannot be used in arithmetic operations. based indexed and register indirect addressing. the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. There are four different 64 KB segments for instructions. By default. stack. By default. . DI is used for indexed. DS register can be changed directly using POP and LDS instructions. CX.Destination Index (DI) is a 16-bit register. DX) and index register (SI. Extra segment (ES) used to hold the starting address of Extra segment. To specify where in 1 MB of processor memory these 4 segments are located the processor uses four segment registers. the processor assumes that all data referenced by general registers (AX. data and extra data. Segment Registers Most of the registers contain data/instruction offsets within 64 KB memory segment. Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. SS register can be changed directly using POP instruction. as well as a destination data address in string manipulation instructions. Extra segment is provided for programs that need to access a second data segment. In short. BX.

The CPU checks the program counter to ascertain which instruction to carry out next. The programmer cannot set/reset these flags directly.The remaining 7 are not used. The ip. This is a crucially important register which is used to control which instruction the CPU executes.The status flags are used to record specific characteristics of arithmetic and of logical instructions. A flag can only take on the values 0 and 1. Flag Register contains a group of status bits called flags that indicate the status of the CPU or the result of arithmetic operations. It then updates the program counter to point to the next instruction. The status flags which reflect the result of executing an instruction. Nine individual bits of the status register are used as control flags (3 of them) and status flags (6 of them). The control flags enable or disable certain CPU operations. There are two types of flags: 1. 2. Thus the program counter will always point to the next instruction to be executed. . The programmer can set/reset these bits to control the CPU's operation. We say a flag is set if it has the value 1.Other registers of 8086 Instruction Pointer (IP) is a 16-bit register. is used to store the memory location of the next instruction to be executed. or program counter.

both positive or both negative). Interrupts are actions initiated by hardware block such as input devices that will interrupt the normal execution of programs. This flag can be set by the INT 3 instruction. The Direction Flag (D): Affects the direction of moving data blocks by such instructions as MOVS. The flag values are 0 = disable interrupts or 1 = enable interrupts and can be manipulated by the CLI (clear I) and STI (set I) instructions. Status Flags: There are six status flags 1. When this flag is set (i. the sign bit). The Overflow Flag (O): This flag is set when the result of a signed arithmetic operation is too large to fit in the destination register (i. 3. when an overflow occurs). the programmer can single step through his program to debug any errors. Overflow can occur when adding two numbers with the same sign (i.e. The flag values are 0 = up and 1 = down and can be set/reset by the STD (set D) and CLD (clear D) instructions. A value of 1 = carry and 0 = no carry.e. This happens when there is an end carry in an addition operation or there an end borrows in a subtraction operation. CMPS and SCAS.e. This flag is a copy of the MSB of the result (i.e. The Trap Flag (T): Determines whether or not the CPU is halted after the execution of each instruction. 2. The Sign Flag (S): This flag is set when the result of an arithmetic or logic operation is negative.Control Flags: There are three control flags 1. . A value of 1 means negative and 0 = positive. When this flag = 0 this feature is off. = 1). The Carry Flag (C): This flag is set when the result of an unsigned arithmetic operation is too large to fit in the destination register. A value of 1 = overflow and 0 = no overflow. 3. 2. The Interrupt Flag (I): Dictates whether or not system interrupts can occur.

Operands may be of three types : · o o o Implicit Explicit Both Implicit and Explicit. Addressing Modes of 8086 Addressing Modes of 8086 – An overview… Definition: An instruction acts on any number of operands. 5. If the number of 1s is even its value = 1 and if the number of 1s is odd then its value = 0. Implicit operands mean that the instruction by definition has some specific operands.The way an instruction accesses its operands is called its Addressing modes. it takes AX and BX as operands XCHG SI. Example: Explicit operands MOV AX. 6.4. Explicit operands mean the instruction operates on the operands specified by the programmer. automatically takes AL and BX as operands AAM . A value of 1 means the result is zero and a value of 0 means the result is not zero. it takes SI and DI as operands . BX. The programmers do NOT select these operands. A value of 1 = carry and 0 = no carry. The Parity Flag (P): This flags reflects the number of 1s in the result of an operation. The Zero Flag (Z): This flag is set when the result of an arithmetic or logic operation is equal to zero. The Auxiliary Carry Flag (A): This flag is set when an operation causes a carry from bit 3 to bit 4 (or a borrow from bit 4 to bit 3) of an operand. it operates on the contents of AX. Example: Implicit operands XLAT . DI.

Implicit and explicit operands Example: Implicit/Explicit operands MUL BX; automatically multiply BX explicitly times AX The location of an operand value in memory space is called the Effective Address (EA) We can classify the addressing modes of 8086 into four groups:
· · · ·

Immediate addressing Register addressing Memory addressing I/O port addressing

The first three Addresssing modes are clearly explained. Immediate Addressing Mode In this addressing mode, the operand is stored as part of the instruction. The immediate operand, which is stored along with the instruction, resides in the code segment -- not in the data segment. This addressing mode is also faster to execute an instruction because the operand is read with the instruction from memory. Here are some examples: Example: Immediate Operands MOV AL, 20 ; move the constant 20 into register AL ADD AX, 5 ; add constant 5 to register EAX MOV DX, offset msg ; move the address of message to register DX Register addressing mode In this addressing mode, the operands may be:
· · ·

reg16: 16-bit general registers: AX, BX, CX, DX, SI, DI, SP or BP. reg8 : 8-bit general registers: AH, BH, CH, DH, AL, BL, CL, or DL. Sreg : segment registers: CS, DS, ES, or SS. There is an exception: CS cannot be a destination.

For register addressing modes, there is no need to compute the effective address. The operand is in a register and to get the operand there is no memory access involved. Example: Register Operands MOV AX, BX ; mov reg16, reg16

ADD AX, SI ; add reg16, reg16 MOV DS, AX ; mov Sreg, reg16 Some rules in register addressing modes: 1. You may not specify CS as the destination operand. Example: mov CS, 02h –> wrong 2. Only one of the operands can be a segment register. You cannot move data from one segment register to another with a single mov instruction. To copy the value of cs to ds, you would have to use some sequence like: mov ds,cs -> wrong mov ax, cs mov ds, ax -> the way we do it You should never use the segment registers as data registers to hold arbitrary values. They should only contain segment addresses.

Immediate addressing mode & Register addressing mode
Immediate Addressing Mode In this addressing mode, the operand is stored as part of the instruction. The immediate operand, which is stored along with the instruction, resides in the code segment -- not in the data segment. This addressing mode is also faster to execute an instruction because the operand is read with the instruction from memory. Here are some examples: Example: Immediate Operands MOV AL, 20 ; move the constant 20 into register AL ADD AX, 5 ; add constant 5 to register EAX MOV DX, offset msg ; move the address of message to register DX Register addressing mode In this addressing mode, the operands may be:
· ·

reg16: 16-bit general registers: AX, BX, CX, DX, SI, DI, SP or BP. reg8 : 8-bit general registers: AH, BH, CH, DH, AL, BL, CL, or DL.

·

Sreg : segment registers: CS, DS, ES, or SS. There is an exception: CS cannot be a destination.

For register addressing modes, there is no need to compute the effective address. The operand is in a register and to get the operand there is no memory access involved. Example: Register Operands MOV AX, BX ; mov reg16, reg16 ADD AX, SI ; add reg16, reg16 MOV DS, AX ; mov Sreg, reg16 Some rules in register addressing modes: 1. You may not specify CS as the destination operand. Example: mov CS, 02h –> wrong 2. Only one of the operands can be a segment register. You cannot move data from one segment register to another with a single mov instruction. To copy the value of cs to ds, you would have to use some sequence like: mov ds,cs -> wrong mov ax, cs mov ds, ax -> the way we do it You should never use the segment registers as data registers to hold arbitrary values. They should only contain segment addresses.

Memory Addressing Modes
Memory (RAM) is the main component of a computer to store temporary data and machine instructions. In a program, programmers many times need to read from and write into memory locations. There are different forms of memory addressing modes 1. Direct Addressing 2. Register indirect addressing 3. Based addressing 4. Indexed addressing 5. Based indexed addressing 6. Based indexed with displacement

[bp] . If you want to provide an offset into a different segment. The ds: prefix in the previous examples is not a segment override. By default. If not mentioned DS register is taken by default. you must use a segment override prefix before your address. the instruction mov ds:[1234h]. Likewise.ds:[8088h] loads the AL register with a copy of the byte at memory location 8088h. [bx] mov al. to access location 1234h in the extra segment (es) you would use an instruction of the form mov ax. to access this location in the code segment you would use the instruction mov ax. [8088h].dl stores the value in the dl register to memory location 1234h.Direct Addressing Mode & Register Indirect Addressing Mode Direct Addressing Mode The instruction mov al. The instruction mov al. For example. There are four forms of this addressing mode on the 8086.ds:[8088h] is same as mov al. best demonstrated by the following instructions: mov al. Register Indirect Addressing Mode The 80x86 CPUs let you access memory indirectly through a register using the register indirect addressing modes. Likewise. all displacement-only values provide offsets into the data segment.es:[1234h]. cs:[1234h].

[si]. Intel refers to the [si] and [di] addressing modes as indexed addressing modes (si stands for source index. and [di] modes use the ds segment by default. 100H MOV AL. [di] Code Example MOV BX. The [bp] addressing mode uses the stack segment (ss) by default. ss:[si] mov al. these addressing modes are functionally equivalent. cs:[bx] mov al. bp stands for base pointer). di stands for destination index).mov al. [si] mov al. This text will call these forms register indirect modes to be consistent. es:[di] Intel refers to [bx] and [bp] as base addressing modes and bx and bp as base registers (in fact. . The following instructions demonstrate the use of these overrides: mov al. [BX] The [bx]. ds:[bp] mov al. You can use the segment override prefix symbols if you wish to access data in different segments. However. the resulting value is a pointer to location where data resides. Based Addressing Mode and Indexed Addressing Modes Based Addressing Mode 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP).

Mov al.[1880] Indexed Addressing Modes The indexed addressing modes use the following syntax: mov al. [bp+disp] mov al. [di+disp] Code Example MOV BX. ss:[di+disp] Example: MOV AX. [DI + 100] . 100H MOV AL. the [bp+disp] addressing mode uses the stack segment by default. The offsets generated by these addressing modes are the sum of the constant and the specified register. mov dh. The addressing modes involving bx. [bx+disp] mov al.[si] Mov bl . [bx+20h] will load cl from memory location ds:1020h. Likewise. then the instruction mov cl. si. cs:[si+disp] mov al. [BX + 15] MOV AL.[di] Code Example If bx=1000h si=0880h Mov AL. [si+disp] mov al. [1000+880] Mov AL. As with the register indirect addressing modes. [bp+1000h] will load dh from location ss:3020.[di] Mov cl . and di all use the data segment. es:[bp+disp] mov al. you can use the segment override prefixes to specify a different segment: mov al. [bp]. [bx]. ss:[bx+disp] mov al. if bp contains 2020h. [bp]. [BX + 16] If bx contains 1000h.

[bp+di] Code Example MOV BX. 200H MOV AL. The allowable forms for these addressing modes are: mov al. These addressing modes form the offset by adding together a base register (bx or bp) and an index register (si or di). [bx+si] mov al. 100H MOV SI. [BX + SI] INC BX INC SI . [bx+di] mov al. [bp+si] mov al.Based Indexed Addressing Modes & Based Indexed Plus Displacement Addressing Mode Based Indexed Addressing Modes The based indexed addressing modes are simply combinations of the register indirect addressing modes.

[bp+si+disp] mov al. Those that have bp as an operand use the stack segment by default. Likewise. mov ax. Then the instruction mov al.Suppose that bx contains 1000h and si contains 880h. disp[bx][si] mov al. The addressing modes that do not involve bp use the data segment by default. disp[bx+di] mov al. 200H MOV AL.[bp+di] will load the 16 bits in ax from locations SS:259C and SS:259D. if bp contains 1598h and di contains 1004. The following are some examples of these addressing modes mov al. 100H MOV SI.[bx][si] would load al from location DS:1880h. Based Indexed Plus Displacement Addressing Mode These addressing modes are a slight modification of the base/indexed addressing modes with the addition of an eight bit or sixteen bit constant. [BX + SI +100H] . [bp][di][disp] Code Example MOV BX.

5.They are again classified into four groups.ARITHMETIC INSTRUCTIONS These instructions are those which are useful to perform Arithmetic calculations. 4.They are: GENERAL – PURPOSE BYTE OR WORD TRANSFER INSTRUCTIONS MOV PUSH POP XCHG XLAT SIMPLE INPUT AND OUTPUT PORT TRANSFER INSTRUCTION SPECIAL ADDRESS FLAG TRANSFER TRANSFER INSTRUCTION INSTRUCTIONS LEA LDS LES LAHF SAHF PUSHF POPF IN OUT 2. subtraction.INC BX INC SI Instruction Set of 8086 8086 Instruction Set and its Classification The instructions of 8086 are classified into SIX groups. They are again classified into four groups.DATA TRANSFER INSTRUCTIONS The DATA TRANSFER INSTRUCTIONS are those. They are: 1. such as addition. 3. which transfers the DATA from any one source to any one destination. 6. multiplication and division. DATA TRANSFER INSTRUCTIONS ARITHMETIC INSTRUCTIONS BIT MANIPULATION INSTRUCTIONS STRING INSTRUCTIONS PROGRAM EXECUTION TRANSFER INSTRUCTIONS PROCESS CONTROL INSTRUCTIONS 1.The datas may be of any type. 2.They are: ADDITION INSTRUCTIONS ADD ADC SUBTRACTION INSTRUCTIONS SUB SBB MULTIPLICATION INSTRUCTIONS MUL IMUL DIVISION INSTRUCTIONS DIV IDIV .

LOGICAL INSTRUCTIONS NOT AND OR XOR TEST 4. They are again classified into four groups. ( Not in a sequence). STRING INSTRUCTIONS The string instructions function easily on blocks of memory.They are user friendly instructions.PROGRAM EXECUTION TRANSFER INSTRUCTIONS These instructions transfer the program control from one address to other address.BIT MANIPULATION INSTRUCTIONS These instructions are used to perform Bit wise operations.INC AAA DAA DEC NEG CMP AAS DAS AAM AAD CBW CWD 3. STRING INSTRUCTIONS REP REPE / REPZ REPNE / REPNZ MOVS / MOVSB / MOVSW COMPS / COMPSB / COMPSW SCAS / SCASB / SCASW LODS / LODSB / LODSW STOS / STOSB / STOSW 5.They are: UNCONDITIONAL TRANSFER INSTRUCTIONS CALL CONDITIONAL TRANSFER INSTRUCTIONS JA / JNBE JLE / JNG ITERATION CONTROL INSTRUCTIONS LOOP INTERRUPT INSTRUCTIONS INT SHIFT INSTRUCTIONS SHL / SAL SHR SAR ROTATE INSTRUCTIONS ROL ROR RCL RCR .They are useful in array handling. which help for easy program writing and execution. They can speed up the manipulating code. tables and records.

RET JMP JAE / JNB JB / JNAE JBE / JNA JC JE / JZ JG / JNLE JGE / JNL JL / JNGE JNC JNE / JNZ JNO JNP / JPO JNS JO JP / JPE JS LOOPE / LOOPZ LOOPNE / LOOPNZ JCXZ INTO IRET 6. They are again classified into Two groups.DATA TRANSFER INSTRUCTIONS GENERAL – PURPOSE BYTE OR WORD TRANSFER INSTRUCTIONS MOV PUSH POP XCHG XLAT/XLATB SIMPLE INPUT AND OUTPUT PORT TRANSFER INSTRUCTION SPECIAL ADDRESS TRANSFER INSTRUCTION LEA LDS LES FLAG TRANSFER INSTRUCTIONS IN OUT LAHF SAHF PUSHF POPF .PROCESS CONTROL INSTRUCTIONS These instructions are used to change the process of the Microprocessor. They change the process with the stored information.They are: FLAG SET / CLEAR INSTRUCTIONS STC CLC CMC STD CLD STI CLI EXTERNAL HARDWARE SYNCHRONIZATION INSTRUCTIONS HLT WAIT ESC LOCK NOP Complete 8086 Instruction set with clear Explanation and sample Programs .

ARITHMETIC INSTRUCTIONS ADDITION INSTRUCTIONS ADD ADC INC AAA DAA SUBTRACTION INSTRUCTIONS SUB SBB DEC NEG CMP AAS DAS MULTIPLICATION INSTRUCTIONS MUL IMUL AAM DIVISION INSTRUCTIONS DIV IDIV AAD CBW CWD BIT MANIPULATION INSTRUCTIONS LOGICAL INSTRUCTIONS NOT AND OR XOR TEST SHIFT INSTRUCTIONS SHL / SAL SHR SAR ROTATE INSTRUCTIONS ROL ROR RCL RCR STRING INSTRUCTIONS STRING INSTRUCTIONS REP REPE / REPZ REPNE / REPNZ MOVS / MOVSB / MOVSW COMPS / COMPSB / COMPSW SCAS / SCASB / SCASW LODS / LODSB / LODSW STOS / STOSB / STOSW PROGRAM EXECUTION TRANSFER INSTRUCTIONS .

Copy the contents of register BX to AX . BX MOV DL. source The MOV instruction copies a word or a byte of data from a specified source to a specified destination .MOV destination. MOV 037AH into the CX.PUSH source . 037AH MOV AX. BX contains the offset PUSH Instruction . MOV op1.Copy byte from memory at BX to DL . · . op2 Example: MOV CX. .UNCONDITIONAL TRANSFER INSTRUCTIONS CALL RET JMP CONDITIONAL TRANSFER INSTRUCTIONS JA / JNBE JAE / JNB JB / JNAE JBE / JNA JC JE / JZ JG / JNLE JGE / JNL JL / JNGE JLE / JNG JNC JNE / JNZ JNO JNP / JPO JNS JO JP / JPE JS ITERATION CONTROL INSTRUCTIONS LOOP LOOPE / LOOPZ LOOPNE / LOOPNZ JCXZ INTERRUPT INSTRUCTIONS INT INTO IRET PROCESS CONTROL INSTRUCTIONS FLAG SET / CLEAR INSTRUCTIONS STC CLC CMC STD CLD STI CLI EXTERNAL HARDWARE SYNCHRONIZATION INSTRUCTIONS HLT WAIT ESC LOCK NOP GENERAL – PURPOSE BYTE OR WORD TRANSFER INSTRUCTIONS · MOV Instruction .[BX] of byte in DS.

PUSH instruction decrements the stack pointer by 2 and copies a word from a specified source to the location in the stack segment where the stack pointer pointes. Money [BX] · . source The Exchange instruction exchanges the contents of the register with the contents of another register (or) the contents of the register with the contents of the memory location. · POP Instruction . Example:MOV AL. Example: XCHG AX. [BX+AL] . It transfers 16 bit information at a time.Decrement SP by 2 and copy DS to stack PUSH TABLE[BX] .Translate a byte in AL XLAT exchanges the byte in AL register from the user table index to the table entry.Copy a word from top of stack to memory in DS with EA = TABLE + [BX]. Copy a word from top of the stack to DS and increments SP by 2. · XCHG Instruction .Exchange word in AX with word in DX . Example: POP DX . POP TABLE [BX] . Example: PUSH BX . XLAT/XLATB Instruction . Syntax: XCHG op1.Decrement SP by 2 and copy BX to stack PUSH DS .Exchange byte in AL with byte in memory at EA. DX XCHG BL.Copy a word from top of the stack to DX and increments SP by 2. Direct memory to memory exchange are not supported. POP DS . The no-operands form (XLATB) provides a "short form" of the XLAT instructions. op2 . CH XCHG AL.The both operands must be the same size and one of the operand must always be a register .Exchange byte in BL with byte in CH . addressed by BX.Decrement SP by 2 and copy word from memory in DS at EA = TABLE + [BX] to stack .POP destination POP instruction copies the word at the current top of the stack to the operand specified by op then increments the stack pointer to point to the next stack.Exchange XCHG destination.

Copy the contents of the AL to port 3Bh . DX · . Port address range from 0000H – FFFFH.255 ). the port address is loaded in DX register before IN instruction. AL OUT 2CH. OUT Instruction . accumulator AL or AX.SIMPLE INPUT AND OUTPUT PORT TRANSFER INSTRUCTION · IN Instruction .Copy the contents of the AX to port 2Ch . DX is 16 bit. DX IN AX. AL OUT DX.AX Example: (b) MOV DX.Output a byte or word to a port – OUT port. 0FFF8H OUT DX. port This IN instruction will copy data from a port to the AL or AX register. 0FF78H IN AL.Input a word from 16 bit port to 0FF78H to AX. Example: IN AL.It is also called as fixed port form. Copy the contents of AL to FFF8h . AX . The OUT instruction copies a byte from AL or a word from AX or a double from the accumulator to I/O port specified by op.Load desired port address in DX .Input a word from port 4AH to AX For a variable port IN instruction. ( 0 .0C8H IN AX.Initialize DX point to port . A_TO_D . Two forms of OUT instruction are available : (a) Port number is specified by an immediate byte constant.Input a byte from port 0C8H to AL . 34H A_TO_D EQU 4AH IN AX.Copy content of AX to port FFF8H .Input a byte from a 8 bit port 0FF78H to AL .Copy data from a port IN accumulator.Input a word from port 34H to AX . For the Fixed port IN instruction type the 8 – bit port address of a port is specified directly in the instruction. (b) Port number is provided in the DX register ( 0 – 65535 ) Example: (a) OUT 3BH. Example: MOV DX.

4. This LAHF instruction was provided to make conversion of assembly language programs written for 8080 and 8085 to 8086 easier. into bits of 7. Copy contents of 4328H and 4329H in DS to DS register.This instruction loads a far pointer from the memory address specified by op2 into the DS segment register and the op1 to the register.Load Register AH From Flags LAHF instruction copies the value of SF. op2 Example: LDS BX. Using this instruction. contents of the 4327H to BH.Load register and ES with words from memory This instruction loads a 32.Load BP with offset of STACK in SS .Load Effective Address LEA Instruction . copy the contents of the memory at displacement 4326H in DS to BL. 0 respectively of AH register. · LES Instruction . memory address of first word or LDS op1.Load BX with offset of PRICE in DS . source Example: LEA BX.This instruction indicates the offset of the variable or memory location named as the source and put this offset in the indicated 16 – bit register. PRICE LEA BP. Syntax – LES register.Load register and Ds with words from memory LDS Instruction . ZF. Syntax – LEA register. 2. 6. and CF.Load CX with EA=BX + DI LDS Instruction . · SAHF instruction . PF.Store AH Register into FLAGS .SPECIAL ADDRESS TRANSFER INSTRUCTION · LEA Instruction . the loading of far pointers may be simplified. SS:STAK LEA CX. memory address of first word FLAG TRANSFER INSTRUCTIONS · LAHF Instruction . AF. Syntax – LDS register. [4326] . The offset is placed in the destination register and the segment is placed in Extra Segment.bit pointer from the memory address specified to destination register and Extra Segment. [BX][DI] · .

· PUSHF Instruction .CL = 01110011 = + 115 decimal + BL = 01001111 = +79 decimal Result in CL = 11000010 = .Add word from memory at offset [SI] in DS to contents of DX . [SI] . Incorrect because result is too large to fit in 7 bits.register. into the Flag register. BL .Add immediate number 74H to content of AL . Addition of Un Signed numbers ADD CL. means they must be a byte location or a word location. · INC Instruction .INC destination . you must copy the byte to a word location and fill the upper byte of the word with zeroes before adding. This instruction copies a word from the two memory location at the top of the stack to flag register and increments the stack pointer by 2. source These instructions add a number from source to a number from some destination and put the result in the specified destination.SAHF instruction transfers the bits 0-7 of AH of SF.BL CL ADD DX.62 decimal .74H ADC CL. PF. Arithmetic Instructions · ADD Instruction . · POPF Instruction . ZF. If you want to add a byte to a word.Add contents of BX to contents of DX . BX ADD DX. AF.Pop word from top of stack to flag .Increment . The source and destination must be of same type .Push flag register on the stack This instruction decrements the SP by 2 and copies the word in flag register to the memory location pointed to by SP. Addition of Signed numbers ADD CL.Add with carry After performing the addition. the add with carry instruction ADC. · ADC Instruction . EXAMPLE: ADD AL. and CF.Add contents of BL plus carry status to contents of CL Results in . adds the status of the carry flag into the result.ADD destination.CL = 01110011 =115 decimal + BL = 01001111 = 79 decimal Result in CL = 11000010 = 194 decimal . BL .

Example: MOV AH. Add 1 to the contents of BL register . INC AX INC BL INC CL · AAA Instruction .After this instruction AX = 8000h . AL=1 representing BCD 11.The result of addition is not a ASCII character but it is a BCD digit. AAA will adjust the result of the two ASCII characters that were in the range from 30h (“0”) to 39h(“9”). In both cases the higher 4 bits of AL are cleared to 0. P. CF and AF are cleared to 0 and AH is not altered. the instruction adds 6 to the high-order four bits. If the addition produce carry (AF=1).Add BCD 5 to digit in AL . Z. the AH register is incremented and the carry CF and auxiliary carry AF flags are set to 1. AX = 7FFFh . DAA Instruction . If the addition did not produce a decimal carry.6 ADD AL. AC. S. the instruction adds 6 to the low-order four bits.BCD 6 in AL .INC instruction adds one to the operand and sets the flag according to the result.This is because the lower 4 bits of those character fall in the range of 09. CY flags are altered to reflect the results of the operation. Example: . Two operands of the addition must have its lower 4 bits contain a number in the range from 0-9. Example: . If the value of the high-order 4-bits in the accumulator is greater than 9 or if the Carry flag is set. Add 1 to the contents of CX register.0 MOV AL.Clear AH for MSD . If the value of the low-order 4-bits in the accumulator is greater than 9 or if AC flag is set.5 AAA · . INC instruction is treated as an unsigned binary number.The AAA instruction then adjust AL so that it contains a correct BCD digit.AH=1.ASCII Adjust after Addition AAA converts the result of the addition of two valid unpacked BCD digits to a valid 2digit BCD number and takes the AL register as its implicit operand.Decimal Adjust after Addition The contents after addition are changed from a binary value to two 4-bit binary coded decimal (BCD) digits.

. OF. Subtract contents of AL and contents CF from . BH . AL contents of CH . The source and destination must be of same type . AF.CF = 1. CL = 00101110 = + 46 decimal BH = 01001010= + 74 decimal SUB CL. ZF = 0.Subtract with borrow SBB destination.Decrement destination register or memory DEC destination..CL = 11100100 = .CX – BX . DEC instruction is treated as an unsigned binary number. AF.Subtracting unsigned number . 3427H Example: . BX SUBB CH. AL = 15h SUBTRACTION INSTRUCTIONS · SUB Instruction .Subtracting signed number . DEC instruction subtracts one from the operand and sets the flag according to the result. ZF =0. .MOV AL. · SBB Instruction . ie. Result in CX .28 decimal. CL = 01100101 = 101 decimal CF.Subtract two numbers These instructions subtract the source number from destination number destination and put the result in the specified destination. BH . PF = 1 . AL = 0Fh (15) . 0Fh DAA RET . SF.Result in CH SUBB AX. means they must be a byte location or a word location. source SBB instruction subtracts source from destination.Subtract immediate number from AX DEC Instruction . and then subtracts 1 from source if CF flag is set and result is stored destination and it is used to set the flag.destination = destination -(source + CF) Example: SUB CX.SF = 1 result negative · . CL = 10011100 = 156 decimal BH = 00110111 = 55 decimal SUB CL.

From 2’s complement – NEG destination NEG performs the two’s complement subtraction of the operand from zero and sets the flags according to the result.Compare byte or word -CMP destination. 5 CMP AL. .0901H SUB AL. Subtract 1 from the contents of BL register DEC AX DEC BL · NEG Instruction .AX = 2CBh .The AAS instruction then adjust AL so that it contain a correct BCD digit. The two operands of the subtraction must have its lower 4 bit contain number in the range from 0 to 9 .after executing NEG result AX =FD35h.Minus 9 . ZF = 1 (so equal!) AAS Instruction . 5 MOV BL. AL = 5. NEG AX Example: NEG AL NEG BX NEG BYTE PTR[BX] complement · .After this instruction AX = 7999h .The result is not stored anywhere. Example: MOV AL.BCD 91 . 9 AAS .. Replace byte at offset BX in DS with its 2’s CMP Instruction . It neglects the results. MOV AX. The CMP instruction compares the destination and source ie.it subtracts the source from destination. but sets the flags accordingly. AX =8000h . BL RET · .Example: .Replace word in BX with its 2’s complement .Replace number in AL with its 2’s complement . source.ASCII Adjust for Subtraction AAS converts the result of the subtraction of two valid unpacked BCD digits to a single valid BCD number and takes the AL register as an implicit operand.This instruction is usually used before a conditional jump instruction. Give AX =0802 h (BCD 82) .

CF = 1 Example: MOV AL.(9 .AL = 0011 0101 =ASCII 5 .This instruction multiplies an unsigned multiplication of the accumulator by the operand specified by op.Results :AL = 0000 0100 =BCD 04.AL =0011 1001 =ASCII 9 . CF. PF. The size of op may be a register or memory operand .BL = 0011 1001 = ASCII 9 .5) Result : . BL CF = 1 AAS · .AL = AL – 6 .Result : AL=00000100 =BCD 04 . SF. CF = 1 MULTIPLICATION INSTRUCTIONS · MUL Instruction .( 5 . ZF if low nibble of AL > 9 or AF = 1 then: .Decimal Adjust after Subtraction This instruction corrects the result (in AL) of subtraction of two packed BCD values. CF = 0 NO Borrow SUB AL. AL = 99h.BL=0011 0101 =ASCII 5 . AL = 0FFh (-1) .CF = 0 . .AL = AL .Example:( a ) . CF = 1 borrow needed DAS Instruction . 0FFh DAS RET .AL = 00000100 = BCD 04. BL AAS required Example:( b ) SUB AL.AF = 1 if AL > 9Fh or CF = 1 then: .Multiply unsigned bytes or words-MUL source MUL Instruction .9 ) Result : AL = 1111 1100 = – 4 in 2’s complement . The flags which modify are AF.60h .

AX times CX. .Signed byte in AL times multiplied by signed byte in BH IMUL BL result . IMUL op1. Example: .Syntax: MUL op Example: . To give a valid result the digits that have been multiplied must be in the range of 0 – 9 and the result should have been placed in the AX register. AAM unpacks the result by dividing AX by 10.MSB = 0 because positive .28 * 59 IMUL BL result · AAM Instruction .ASCII adjust after Multiplication AAM Instruction . MUL BL set to 1.AX = 03C6H = + 966 decimal .AL = 21h (33 decimal). They are: IMUL op .AX = F98Ch = . CF and OF will .AAM converts the result of the multiplication of two valid unpacked BCD digits into a valid 2-digit unpacked BCD number and takes AX as an implicit operand. result in AX .BL = 00001110 = 14 decimal . Example: IMUL BH and result in AX . .BL = A1h(161 decimal ) . op2 . AL times BH. result high word in DX.28 decimal . Because both operands of multiply are required to be 9 or less. AL = 11100100 = . MSB = 1 because negative . BL = 00001110 = 14 decimal .There are two types of syntax for this instruction. 69 * 14 . the result must be less than 81 and thus is completely contained in AL.In this form the accumulator is the multiplicand and op is the multiplier.In this form op1 is always be a register operand and op2 may be a register or a memory operand. op may be a register or a memory operand. AL = 01000101 = 69 decimal . placing the quotient (MSD) in AH and the remainder (LSD) in AL.low word in AX.AX =14C1h (5313 decimal) since AH≠0.1652 decimal. MUL BH MUL CX · IMUL Instruction .Multiply signed number-IMUL source This instruction performs a signed multiplication.

AX = Quotient = 5EH = 94 decimal and AH = Remainder = IDIV Instruction . AX = 37D7H = 14.Unsigned divide-Div source When a double word is divided by a word. 7 MUL BL AAM . If source is a word value.AH instruction is a quick way to do.Divide by signed byte or word IDIV source This instruction is used to divide a signed word by a signed byte or to divide a signed double word by a signed word. DX:AX is divided by register. if an attempt is made to divide by zero or quotient is too large to fit in AX ( greater than FFFFH ) the 8086 will do a type of 0 interrupt . Example: DIV CX . Again . If you want to divide a byte by a byte. the most significant word of the double word must be in DX and the least significant word of the double word must be in AX.DX instruction does this quickly. 295 decimal and BH = 97H = 151 decimal DIV BH 65H = 101 decimal. but the source of the divisor can be a register or a memory location specified by one of the 24 addressing modes. The SUB AH. Example: . AX =0305h (BCD 35) DIVISION INSTRUCTIONS · DIV Instruction .and the quotient is stored in AL and the remainder in DX. result in AX . . AX is divided by register and the quotient is stored in AL and the remainder in AH.Multiply AL by BL . If source is a byte value.After AAM. · . you must first put the dividend byte in AL and fill AH with all 0’s .AX / BH . The SUB DX. 5 MOV BL. put the dividend word in AX and fill DX with all 0’s. If you want to divide a word by a word. (Quotient) AX= (DX:AX)/CX . (Reminder) DX=(DX:AX)%CX For DIV the dividend must always be in AX or DX and AX. After the division AX will contain the 16 –bit result (quotient ) and DX will contain a 16 bit remainder.Example: MOV AL.

Before executing AAD. AH = remainder = 04 unpacked BCD · CBW Instruction . AH is then said to be the sign extension of AL.Divide AX by unpacked BCD in CH.Convert signed Byte to signed word CBW converts the signed value in the AL register into an equivalent 16 bit signed value in the AX register by duplicating the sign bit to the left.Example: IDIV BL · . Convert signed byte in AL to signed word in AX. This instruction copies the sign of a byte in AL to all the bits in AH.Convert Signed Word to . Example: MOV AX. Example: .The unpacked BCD number 25 . place the Most significant BCD digit in the AH register and Last significant in the AL register. AAD .Signed Double word CBW · CWD converts the 16 bit signed value in the AX register into an equivalent 32 bit signed value in DX: AX register pair by duplicating the sign bit to the left. .155 decimal . The CWD instruction sets all the bits in the DX register to the same sign bit of the AX .0205h AAD . After the division AL will then contain the unpacked BCD quotient and AH will contain the unpacked BCD remainder. AH=0 and AL=19h (25). DIV CH .Signed word in AX is divided by signed byte in BL AAD Instruction . AL = quotient = 07 unpacked BCD. AX = 00000000 10011011 = . the two BCD digits are combined into a single binary number by setting AL=(AH*10)+AL and clearing AH to 0.ASCII adjust before Division ADD converts unpacked BCD digits in the AH and AL register into a single binary number in the AX register in preparation for a division operation. Example: . Result in AX = 11111111 10011011 and = .AX=0607 unpacked BCD for 67 decimal CH=09H.155 decimal CWD Instruction .Adjust to binary before division AX=0043 = 43H =67 decimal.After AAD . When AAD is executed.

DX =F038h . Both the original value of AX (C435h) and resulting value of DX : AX (FFFFC435h) represents the same signed number.result in BH AND BX.bit signed result that has same integer value as the original 16 bit operand.AND corresponding bits of two operands This Performs a bitwise Logical AND of two operands. The result of the operation is stored in the op1 and used to set the flags.AND byte in CL with byte in BH .after the instruction DX = 0FC7h AND Instruction . leave lower unchanged . CL . Example: .00FFh . .register.AND word in BX with immediate 00FFH. AND op1. Mask upper byte. otherwise the bit in the result I cleared to 0 .Result DX = 11111111 11111111 and AX = 11110000 11000111 BIT MANIPULATION INSTRUCTIONS LOGICAL INSTRUCTIONS · NOT Instruction .DX = 00000000 00000000 and AX = 11110000 11000111 = 3897 decimal CWD = -3897 decimal. each bit of the result is set to 1 if and only if the corresponding bit in both of the operands is 1.Complement contents of BX register. op2 To perform a bitwise AND of the two operands. Example : AND BH.Invert each bit of operand NOT perform the bitwise complement of operand and stores the result back into operand itself. .Convert signed word in AX to signed double word in DX:AX . If the CWD instruction is executed. DX will contain FFFFh since bit 15 (MSB) of AX was 1. Example: Assume AX contains C435h. Syntax–NOT destination Example : NOT BX NOT DX · . The effect is to create a 32.

Update PF.FF00h 10100101 · .AND CX with immediate number .Exclusive OR CX with BX and Result BX = 00111101 10010110 · TEST Instruction – AND operand to update flags TEST Instruction . AND word at offset [SI] in data segment with word in CX register .Exclusive XOR destination. OF = 0. source.Each bit of the result is cleared to 0 if and only if both corresponding bits in each operand are 0.Result BX = 00000000 01011110 and CF =0 . XOR Instruction . · OR Instruction . other wise the bit in the result is set to 1.OR instruction perform the bit wise logical OR of two operands . CX . ZF TEST CX. Examples : OR AH. Syntax–.Logically OR corresponding of two operands OR Instruction .AND BH with AL. 0001H . source XOR Instruction . result in AH.Mask out upper 8 bits of BX. TEST instruction is often used to set flags before a condition jump instruction Examples: TEST AL. The result of the operand is stored in op1 and is used to set the flag.Upper byte are all 1’s lower bytes are unchanged. SF = 0 . .00FFh .[SI] . no result is stored . Syntax–. Flags are updated but neither operand is changed .no result is stored. PF = 0. CL OR CX. BX = 00111101 01101001 and CX = 00000000 11111111 XOR BX.OR destination.OR CX with immediate FF00h result in CX = 11111111 .AND CX.CX = 00111110 10100101 . SF. Example : ( Numerical ) . BH . source.CL is OR’ed with AH.XOR performs a bit wise logical XOR of the operands specified by op1 and op2.SF Example : .ZF = 0. .XOR destination.This instruction ANDs the contents of a source byte or word with the contents of specified destination word. Result in CX register and BX = 10110011 01011110 AND BX. Update PF.

ZF = 1 if MSB of AL = 0 and AL = 01010001 (unchanged). SF = . CF will contain MSB bit.Shift bytes in DS at offset BX and rotate 3 bits to right . 1 · SHR Instruction .Shift operand bits right. BX = 11001011 1010011 SAL BX.SI = 10010011 10101101 .SAL/AHL destination.AL = 01010001 . 03H SHR BYTE PYR[BX] and keep 3 0’s in MSB Example:( 3 ) . Example:( 1 ) SHR BP. BX = 11100101 11010011 . ZF = 0 · SAR Instruction . As a bit is shifted out of LSB position a 0 is kept in LSB position.CF = 1.Load desired number of shifts into CL . count Example: . . Shift word in BP by 1 bit position to right and 0 is kept to SHR SI. put zero in MSB SHR instruction shifts the bits in op1 to right by the number of times specified by op2 . SF = 0. put zero in LSB(s) SAL instruction shifts the bits in the operand specified by op1 to its left by the count specified in op2. Syntax .Shift operand bits right.ZF = 1 because ANDing produced is 00 SHIFT INSTRUCTIONS · SAL/SHL Instruction . new MAB = old MSB . OF = 1.CF = 0. Result: SI = 01001001 11010110 and CF = 1. CF = 0 .Shift BX register contents by 1 bit position towards left . 1 MSB Example:( 2 ) MOV CL.AND immediate 80H with AL to test f MSB of AL is 1 or 0 . 1 0. 80H 0 .Shift operand bits left.TEST Al.PF = .

CF = 1 . .CF = 1. CF = 0 . put zero in LSB(s) SAL instruction shifts the bits in the operand specified by op1 to its left by the count specified in op2. count Example: . AL = 00011101 = +29 decimal.SAL/AHL destination. 1 Example: ( 2 ) SAR BH. 03H SHR BYTE PYR[BX] and keep 3 0’s in MSB .Shift BX register contents by 1 bit position towards left . Syntax .Shift signed byte in AL towards right ( divide by 2 ) . MSB position and LSB is shifted to CF. 1 MSB Example:( 2 ) MOV CL.Load desired number of shifts into CL . Syntax . put zero in MSB SHR instruction shifts the bits in op1 to right by the number of times specified by op2 .Shift operand bits left. 1 · SHR Instruction . CF will contain MSB bit. Example: ( 1 ) SAR AL. Shift word in BP by 1 bit position to right and 0 is kept to .SAR destination.Shift operand bits right.BH = 11110011 = . Example:( 1 ) SHR BP. BX = 11001011 1010011 SAL BX.Shift bytes in DS at offset BX and rotate 3 bits to right .7 . CF = 1 SHIFT INSTRUCTIONS · SAL/SHL Instruction .13 decimal.Shifted signed byte in BH to right and BH = 11111001 = . CF = 1.As bit is shifted out a copy of old MSB is taken in MSB. count.SAR instruction shifts the bits in the operand specified by op1 towards right by count specified in op2. BX = 11100101 11010011 . 1 decimal.CF = 0.AL = 00001110 = + 14 decimal. As a bit is shifted out of LSB position a 0 is kept in LSB position.

AL = 00011101 = +29 decimal. diverts its execution to some other program called Interrupt Service Routine (ISR). ZF = 0 · SAR Instruction . .13 decimal. count.Example:( 3 ) . SF = SHR SI. CF = 1 . CF = 1 Interrupts of 8086 Definition: The meaning of ‘interrupts’ is to break the sequence of operation. 1 Example: ( 2 ) SAR BH.on ‘interrupt’ breaks the normal sequence of execution of instructions. OF = 1.Shift signed byte in AL towards right ( divide by 2 ) . CF = 0 . . MSB position and LSB is shifted to CF. They are: (i)Hardware Interrupts and (ii)Software Interrupts (i) Hardware Interrupts (External Interrupts). that provide or require data at relatively low data transfer rate. CF = 1.BH = 11110011 = . Syntax . Types of Interrupts: There are two types of Interrupts in 8086. 1 0. new MAB = old MSB SAR instruction shifts the bits in the operand specified by op1 towards right by count specified in op2.SAR destination.After executing ISR .Shifted signed byte in BH to right and BH = 11111001 = .AL = 00001110 = + 14 decimal. Result: SI = 01001001 11010110 and CF = 1. The Intel microprocessors support hardware interrupts through: · · Two pins that allow interrupt requests. the control is transferred back again to the main program. Need for Interrupt: Interrupts are particularly useful when interfacing I/O devices. INTA. 1 decimal.As bit is shifted out a copy of old MSB is taken in MSB.7 . Example: ( 1 ) SAR AL. the interrupt requested on INTR.While the cpu is executing a program.Interrupt processing is an alternative to polling. INTR and NMI One pin that acknowledges. CF = 0 .SI = 10010011 10101101 .Shift operand bits right.

(ii) Software Interrupts (Internal Interrupts and Instructions) .e. . NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR interrupt. This is a type 1 interrupt.interrupt on overflow Single-step interrupt . This interrupt has higher priority than the maskable interrupt.Software interrupts can be caused by: · · · · · · · · INT instruction . When the CPU processes this interrupt it clears TF flag before calling the interrupt processing routine. the processor stores FLAGS register into stack.generated if the TF flag is set. Software interrupt processing is the same as for the hardware interrupts. When an interrupt occurs. This is a type 3 interrupt.Ex: INT n (Software Instructions) Control is provided through: o IF and TF flag bits o IRET and IRETD .breakpoint interrupt. Processor exceptions: Divide Error (Type 0). INTR. The interrupt can be enabled/disabled using STI/CLI instructions or using more complicated method of updating the FLAGS register with the help of the POPF instruction. – Ex: NMI. disables further interrupts. INT <interrupt number> instruction . Unused Opcode (type 6) and Escape opcode (type 7). i. and jumps to interrupt processing routine address of which is stored in location 4 * <interrupt type>. Interrupt type of the NMI is 2. the address of the NMI processing routine is stored in location 0008h.any one interrupt from available 256 interrupts.INTR and NMI · · · · INTR is a maskable hardware interrupt. fetches from the bus one byte representing interrupt type. Interrupt processing routine should return with the IRET instruction. INTO instruction .

Interrupt Vector Table (Click the picture for full view) . 6.Performance of Software Interrupts 1. It decrements SP by 2 and pushes CS on the stack. 6. It resets the TF in the flag Register. It decrements SP by 2 and pushes the flag register on the stack. 3. 2. Fetch the ISR address from the interrupt vector table. 5. Disables INTR by clearing the IF. It decrements SP by 2 and pushes IP on the stack.

The job of ISR is to dump the registers on to the screen .Functions associated with INT00 to INT04 INT 00 (divide error) · · INT00 is invoked by the microprocessor whenever there is an attempt to divide a number by zero. ISR is responsible for displaying the message “Divide Error” on the screen INT 01 · · · For single stepping the trap flag must be 1 After execution of each instruction. 8086 automatically jumps to 00004H to fetch 4 bytes for CS: IP of the ISR.

Between 20H and FFH . If INT 0 is placed after a signed number arithmetic as IMUL or ADD the CPU will activate INT 04 if 0F = 1. It is one byte instruction whereas other instructions of the form “INT nn” are 2 byte instructions.INT 02 (Non maskable Interrupt) · When ever NMI pin of the 8086 is activated by a high signal (5v). the INT 0 is not executed but is bypassed and acts as a NOP. Performance of Hardware Interrupts · · NMI : Non maskable interrupts . In case where 0F = 0 . the CPU Jumps to physical memory location 00008 to fetch CS:IP of the ISR assocaiated with NMI. INT 03 (break point) · · A break point is used to examine the cpu and memory after the execution of a group of Instructions.TYPE 2 Interrupt INTR : Interrupt request . INT 04 ( Signed number overflow) · · · There is an instruction associated with this INT 0 (interrupt on overflow).

· · · · · . The read (RD) signal causes the address device to enable its data bus drivers. The read (RD) control signal is also activated in T2. the first is the timing diagram for read cycle and the second is the timing diagram for write cycle. During the negative going edge of this signal.Interrupt Priority Structure Timing Diagram Write Cycle Timing Diagram for Minimum Mode · The working of the minimum mode configuration system can be better described in terms of the timing diagrams rather than qualitatively describing the operations. high or both bytes. The BHE and A0 signals address low. From T1 to T4 . Hence the timing diagram can be categorized in two parts. The bus is then tristated. the M/IO signal indicates a memory or I/O operation. the valid data is available on the data bus. At T2. the valid address is latched on the local bus. the address is removed from the local bus and is sent to the output. After RD goes low. The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also M / IO signal. The opcode fetch and read cycles are similar.

the processor sends the data to be written to the addressed location. When the processor returns the read signal to high level. In T2.· The addressed device will drive the READY line high. The data remains on the bus until middle of T4 state. after sending the address in T1. The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be read or write. the addressed device will again tristate its bus drivers. The WR becomes active at the beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating). The M/IO signal is again asserted to indicate a memory or I/O operation. · · · . A write cycle also begins with the assertion of ALE and the emission of the address.

the CPU activates HLDA in the next clock cycle and for succeeding bus cycles. When the request is dropped by the requesting master. Bus Request and Bus Grant Timings in Minimum Mode System of 8086 · Hold Response sequence: The HOLD pin is checked at leading edge of each clock pulse. RD and WR signals indicate the type of data transfer as specified in table below. · . the HLDA is dropped by the processor at the trailing edge of the next clock. The control of the bus is not regained by the processor until the requesting master does not drop the HOLD pin low. If it is received active by the processor before T4 of the previous cycle or during T1 state of the current cycle.· The M/IO. the bus will be given to another requesting master.

Memory Read Timing Diagram in Maximum Mode of 8086 .

Memory Write Timing in Maximum mode of 8086 RQ/GT Timings in Maximum Mode .

By multiplexed · . 3. The minimum mode signal can be divided into the following basic groups : 1. the 8086 provides all control signals needed to implement the memory and I/O interface. it accepts the control of the bus. A 20bit address gives the 8086 a 1Mbyte memory address space. 5. the processor issues a grant pulse over the RQ/GT pin immediately during T4 (current) or T1 (next) state. · · Interfacing Minimum Mode Interface · When the Minimum mode operation is selected. it sends a release pulse to the processor using RQ/GT pin. Address/data bus Status Control Interrupt and DMA. Address/Data Bus : · These lines serve two functions. The request/grant pins are checked at each rising pulse of clock input. A19 represents the MSB and A0 LSB. More over it has an independent I/O address space which is 64K bytes in length. When a request is detected and if the condition for HOLD request are satisfied. 4. 2. When the requesting master receives this pulse. · Each and every group is explained clearly. As an address bus is 20 bits long and consists of signal lines A0 through A19. The 16 data bus lines D0 through D15 are actually multiplexed with address lines A0 through A15 respectively.· The request/grant response sequence contains a series of three pulses.

These status bits are output on the bus at the same time that data are transferred over the other bus lines.· we mean that the bus work as an address bus during first machine cycle and as a data bus during next machine cycles. Status line S5 reflects the status of another internal characteristic of the 8086. Bit S4 and S3 together from a 2 bit binary code that identifies which of the 8086 internal segment registers are used to generate the physical address that was output on the address bus during the current bus cycle. Status signal: · · · The four most significant address lines A19 through A16 are also multiplexed but in this case with status signals S6 through S3. and interrupt type codes from an interrupt controller. S4 S3 Segment Register . It is the logic level of the internal enable flag.Code S4S3 = 00 identifies a register known as extra segment register as the source of the segment address. input/output data for I/O devices. they carry read/write data for memory. When acting as a data bus. The last status bit S6 is always at the logic 0 level. D15 is the MSB and D0 LSB.

They control functions such as when the bus is to carry a valid address in which direction data are to be transferred over the bus. · · · · . data are either written into memory or output to an I/O device. This corresponds to reading data from memory or input of data from an input port. Another control signal that is produced during the bus cycle is BHE bank high enable. When this line is logic 1 during the data transfer part of a bus cycle. the bus is in the transmit mode. when valid write data are on the bus and when to put read data on the system bus. Logic 1 at this output signals a memory operation and logic 0 an I/O operation. Using the M/IO and DT/R lines. These lines also serves a second function. which is as the S7 status line.0 0 1 1 0 1 0 1 Extra Stack Code / none Data Memory segment status codes Control Signals : · The control signals are provided to support the 8086 memory I/O interfaces. This address must be latched in external circuitry on the 1-to-0 edge of the pulse at ALE. logic 0 at DT/R signals that the bus is in the receive mode. Therefore. The direction of data transfer over the bus is signaled by the logic level output at DT/R. On the other hand. ALE is a pulse to logic 1 that signals external circuitry when a valid address word is on the bus. Logic 0 on this used as a memory enable signal for the most significant byte half of the data bus D8 through D1. the 8086 signals which type of bus cycle is in progress and in which direction data are to be transferred over the bus. The logic level of M/IO tells external circuitry whether a memory or I/O transfer is taking place over the bus.

There is one other control signal that is involved with the memory and I/O interface. This signal is provided by an external clock generator device and can be supplied by the memory or I/O sub-system to signal the 8086 when they are ready to permit the data transfer to be completed. As TEST switches to 0. Execution of a WAIT instruction causes the 8086 to check the logic level at the TEST input. During read operations. execution resume with the next instruction in the program. the MPU suspend operation and goes into the idle state. The TEST input is also related to the external interrupt interface. it indicates this fact to external circuit with pulse to logic 0 at the INTA output. There are two more inputs in the interrupt interface: the nonmaskable interrupt NMI and the reset interrupt RESET. On the 0-to-1 transition of NMI control is passed to a nonmaskable interrupt service routine. INTR is an input to the 8086 that can be used by an external device to signal that it need to be serviced. On the other hand. instead it repeatedly checks the logic level of the TEST input waiting for its transition back to logic 0. This is the READY signal.· The signal read RD and write WR indicates that a read bus cycle or a write bus cycle is in progress. Logic 1 at INTR represents an active interrupt request. RD indicates that the 8086 is performing a read of data of the bus. READY signal is used to insert wait states into the bus cycle such that it is extended by a number of clock periods. The 8086 switches WR to logic 0 to signal external device that valid write or output data are on the bus. This feature can be used to synchronize the operation of the 8086 to an event in external hardware. This is DEN ( data enable) and it signals external devices when they should put data on the bus. When an interrupt request has been recognized by the 8086. The RESET input is used . If the logic 1 is found. · · Interrupt signals : · · · · · · · · The key interrupt interface signals are interrupt request (INTR) and interrupt acknowledge ( INTA). one other control signal is also supplied. The 8086 no longer executes instructions.

WR. facilities are provided for implementing allocation of global resources and passing bus control to other microprocessor or coprocessor. DEN and INTR are all in the high Z state. the 8086 enters the hold state. . At the completion of the current bus cycle. When an external device wants to take control of the system bus. A16/S3 through A19/S6. By multiprocessor environment we mean that one microprocessor exists in the system and that each processor is executing its own program. signal lines AD0 through AD15. BHE. In the hold state. DMA Interface signals : · · · The direct memory access DMA interface of the 8086 minimum mode consist of the HOLD and HLDA signals. it provides signals for implementing a multiprocessor / coprocessor system environment. One passes the control of the system bus to the other and then may suspend its operation. Usually in this type of system environment.They are called as global resources. M/IO. These are known as local or private resources. The 8086 signals external device that it is in this state by switching its HLDA output to logic 1 level. In this two processor does not access the bus at the same time. Switching RESET to logic 0 initializes the internal register of the 8086 and initiates a reset service routine. DT/R. There are also other resources that are assigned to specific processors. it signals to the 8086 by switching HOLD to the logic 1 level. In the maximum-mode 8086 system. there are some system resources that are common to all processors. Coprocessor also means that there is a second processor in the system. RD.to provide a hardware reset for the 8086. Maximum Mode Interface · · · · · When the 8086 is set for the maximum-mode configuration.

the bus controller generates the appropriately timed command and control signals. S1.8288 Bus Controller – Bus Command and Control Signals: · 8086 does not directly provide all the signals that are required to control the memory. S2 prior to the initiation of each bus cycle. DT/R.bit bus status code identifies which type of bus cycle is to follow. ALE and INTA. I/O and interrupt interfaces. S2S1S0 are input to the external bus controller device. Specially the WR. S2 S1 S0 Indication 8288 Command · · . Instead it outputs three status signals S0. DEN. signals are no longer produced by the 8086. M/IO. This 3.

In the code 111 is output by the 8086. . it is signaling that no bus activity is to take place. · · · They correspond to the bus exchange signals of the Multibus and are used to lock other processor off the system bus during the execution of an instruction by the 8086. it indicates that an I/O read cycle is to be performed. This set of bus commands and control signals is compatible with the Multibus and industry standard for interfacing microprocessor systems. bus priority out (BPRO). AMWC None · · · · The 8288 produces one or two of these eight command signals for each bus cycles. These 3 signals provide the same functions as those described for the minimum system mode. bus priority in (BPRN). The output of 8289 are bus arbitration signals: Bus busy (BUSY). In this way the processor can be assured of uninterrupted access to common system resources such as global memory. Queue Status Signals : Two new signals that are produced by the 8086 in the maximum-mode system are queue status outputs QS0 and QS1. when the 8086 outputs the code S2S1S0 equals 001. QS1QS0. DT/R and ALE. The control outputs produced by the 8288 are DEN. For instance. common bus request (CBRQ). AIOWC None MRDC MRDC MWTC. bus request (BREQ) and bus clock (BCLK). Together they form a 2-bit ueue status code.0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Interrupt Acknowledge Read I/O port Write I/O port Halt Instruction Fetch Read Memory Write Memory Passive INTA IORC IOWC .

Queue status codes 0 (low) 0 0 1 1 0 1 1 · Local Bus Control Signal – Request / Grant Signals: In a maximum mode configuration. The queue has been reinitialized as a result of the execution of a transfer instruction.· Following table shows the four different queue status.0eh . buffer address Mov ah. Queue Empty. Table . The queue has been reinitialized as a result of the execution of a transfer instruction. First Byte. Subsequent Byte. The byte taken from the queue was a subsequent byte of the instruction. HLDA interface is also changed. The byte taken from the queue was the first byte of the instruction.dx Mov byte ptr [si]. respectively. They provide a prioritized bus access mechanism for accessing the local bus. Program: Mov dx. 8 Int 21 Mov ah.0a Mov si. the minimum mode HOLD. Example Programs of 8086 · · Write an 8086 program that adds two packed BCD numbers input from the keyboard and computes and displays the result on the system video monitor Data should be in the form 64+89= The answer 153 should appear in the next line. These two are replaced by request/grant lines RQ/ GT0 and RQ/ GT1. QS1 QS0 Queue Status Queue Empty.

[si+6] Daa Mov bh. cl Mov al.cl Rol byte ptr [si+6]. 30h sub byte ptr[si+5].4 Rol byte ptr [si+3].bh Call display Int 20 Display Subroutine: mov bl.f0 . cl Ror word ptr [si+2].al Jnc display Mov al. Save original number and al.cl Ror word ptr [si+2]. 30h sub byte ptr[si+6].Mov al. [si+3] Add al.Force bits 0-3 low BIOS service 0e line feed position cursor .1 Call display Mov al. 30h sub byte ptr[si+3].0ah Int 10 . 30h Mov cl. sub byte ptr[si+2].al .

mov cl. Four rotates Rotate MSD into LSD Convert to ASCII BIOS video service 0E Display character Recover original number Force bits 4-7 low Convert to ASCII Display character Return to calling program .4 . int 10 . add al. and al.0e .cl . . int 10 . mov ah.30 .bl . mov al.Input buffer begins here Source : http://www. ret . ror al.info/page/8086-details.8085projects.0f . add al.30 .aspx .

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