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Effects of process variation in VLSI

interconnects – a technical review

K.G. Verma
Shobhit University, Meerut, India
B.K. Kaushik
Department of Electronics & Electrical Engineering, G.B. Pant Engineering College, Pauri Garhwal, India, and
R. Singh
Shobhit University, Meerut, India

Purpose – Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The purpose of
this paper is to provide a comprehensive overview of types and sources of all aspects of interconnect process variations.
Design/methodology/approach – The impacts of these interconnect process variations on circuit delay and cross-talk noises along with the two
major sources of delays – parametric delay variations and global interconnect delays – have been discussed.
Findings – Parametric delay evaluation under process variation method avoids multiple parasitic extractions and multiple delay evaluations as is done
in the traditional response surface method. This results in significant speedup. Furthermore, both systematic and random process variations have been
contemplated. The systematic variations need to be experimentally modeled and calibrated while the random variations are inherent fluctuations in
process parameters due to any reason in manufacturing and hence are non-deterministic.
Originality/value – This paper usefully reviews process variation effects on very large-scale integration (VLSI) interconnect.

Keywords Integrated circuit technology, Operations and production management

Paper type Technical paper

1. Introduction the design stage, which ultimately translates to a parametric

yield loss. Due to the high complexity of design and the
The performance of very large-scale integration (VLSI)/ultra presence of a large number of correlated parameters that
large-scale integration density (ULSI) chip is becoming less exhibit significant variations within a chip and between chips,
predictable as device dimensions shrink below the sub- fast and efficient methods are needed to compute an accurate
100 nm scale. The reduced predictability can be attributed to statistical description of the response.
poor control of the physical features of devices and Process variations are not completely random. It can be
interconnects during the manufacturing process. Variations divided into deterministic part and nondeterministic part.
in these quantities result in variations in the electrical behavior Random variations are inherent fluctuations in process
of circuits. These variations have interdie and intradie parameters such as dopant fluctuations from wafer to wafer,
components, as well as layout pattern dependencies. The lot to lot. On the other hand, systematic variations depend on
device material variations in geometry (tox, Leff , W), and the layout pattern and are therefore predictable for the
variations in doping levels and profiles have a direct impact on systematic part, the variations need to be experimentally
the behavior of a metal-oxide semiconductor field-effect modeled and calibrated, in order to either compensate hiring
transistor (MOSFET). Variations in the line width affect the the design phase or captured in the analysis phase. These
resistance and the interlayer capacitance. Variations in effects, which include optical proximity correction (OPC),
the interwire spacing may cause a significant degradation in residual error and chemical mechanical planarization (CMP)
the signal integrity. Layout pattern dependent variations dishing (Orshansky et al., 2000) have a substantial but
within the interlayer oxide and the chip multiprocessing deterministic impact on the critical dimension (CD) of a
process also have a significant impact on the interconnect transistor gate or the width and thickness of an interconnect
parasitics. The disparate sources of variations in the IC wire. By accounting for systematic part of process variation in
fabrication process lead to both random and systematic effects timing analysis, uncertainty can be reduced, thereby achieving
on circuit performance. All of these make it increasingly closer bound for circuit performance. With the shrinking
difficult to accurately predict the performance of a circuit at feature size in VLSI technology, the impact of process
variation is increasingly felt. To address the effect, great
The current issue and full text archive of this journal is available at amount of research has been done recently, such as the clock skew analysis under process variation (Liu et al., 2000;
Mehrotra et al., 2000; Malavasi et al. 2002), statistical
performance analysis (Brawhear et al., 1994; Chang and
Microelectronics International Sapatnekar, 2003; Agarwal et al., 2003) worst case
26/3 (2009) 49– 55
q Emerald Group Publishing Limited [ISSN 1356-5362]
performance analysis (Orshansky et al., 2000; Acar et al.,
[DOI 10.1108/13565360910981562] 2001), parametric yield estimation (Borkar et al., 2003),

Effects of process variation in VLSI interconnects Microelectronics International
K.G. Verma, B.K. Kaushik and R. Singh Volume 26 · Number 3 · 2009 · 49 –55

impact analysis on micro architecture (Borkar et al., 2003) Errors in deep-submicron (DSM):
and delay fault (Gattiker et al., 2001) test under process The number of transient errors is expected to increase in
variation (Luong and Walker 1996; Liou et al., 2002; Krstic future technology generations:
et al., 2003; Lu et al., 2004a). Since the width, thickness and .
Interconnects will be longer.
spacing of interconnects are each scaled by 1/a .
Smaller feature size brings new error sources (like
(scaling factor), cross-section areas must scale by 1/a2. The radiation).
length of short distance interconnections is scaled by 1/a, so .
The physical implementation of circuits and interconnects
that resistance is increased by a. With decreasing device is expected to function erroneously from time to time.
dimensions, we see increase in the levels of integration and .
Designs cannot be considered nearly 100 per cent reliable
consequent increase in die size. This lengthens the anymore.
interconnections from one side of the chip to the other end
Sources of DSM errors:
and, therefore, both resistance and capacitance of .
interconnects are increased, producing much larger time .
electro-magnetic interference;
constants. Thus, the effects of increased propagation delays, .
signal decay, and clock skew will reduce the maximum .
process variations; and
achievable operating frequency, even though the smaller .
transistors produce gates with less delay. One solution to this
problem has been to make use of multilayer interconnections Given the perspective of different categories of variation, we
with thicker, wider conductors and thicker separating layers. can now briefly survey some of the specific process variations
Other method is to use cascaded drivers and repeaters to typically of concern in evaluating devices and interconnect in
reduce the effects of long interconnect. A further option is to integrated circuit design.
use optical interconnection techniques where a very high level
of interconnection methodology is required (Fabbro et al., 2.1 Device geometry variations
1995). The first set of process variations of concern relate to the
Figure 1 shows a typical interconnect geometry in a custom physical geometric structure of MOSFET and other devices
design layout (Liu et al., 2000). Interconnects on adjacent (resistors and capacitors) in the circuit. These typically
layers are orthogonal to each other, which is a special case of include.
the general configuration. The top interconnect has larger Film thickness variations. The gate oxide thickness is a
width and smaller length compared to lower interconnects. critical but usually relatively well controlled parameter.
The capacitance at any metal line or node consists of the Variation tends to occur primarily from one wafer to
following three components: another with good across wafer and across die control.
1 overlap capacitance Cov due to the overlap between two Other intermediate process thickness variations (e.g. poly or
interconnects in different metal layers; spacer thickness) can impact channel length, but are rarely
2 lateral capacitance C lat between two intra-layer directly modeled.
interconnects; and Lateral dimension variations. Lateral dimensions (length and
3 fringe capacitance Cfr between two interconnects in width) typically arise due to photolithography proximity
different metal layers; this fringe capacitance is between effects (a systematic pattern dependency), mask, lens, or
the sidewall of one interconnect and the top (or bottom) photo system deviations (a repeated die dependent variation,
of another interconnects in a different layer (Pucknell and though not directly a function of the layout density or other
Eshraghian, 1988). layout parameters); or plasma etch dependencies (which can
have both wafer scale etch rate dependencies, as well as layout
2. Nanometer process variation density, aspect ratio, or other dependencies). MOSFETS are
well known to be particularly sensitive to effective channel
As the technology reaches deep submicron or nanometer
length (and thus to poly gate length and spacer width), as well
regime, the errors due process variations becomes prominent.
as gate oxide thickness and to some degree the channel width.
The errors are briefly enumerated as follows.
Of these, channel length variation often is singled out for
particular attention. This is due to the fact that such
Figure 1 Schematic of a typical interconnect structure variations have direct impact on device output current
characteristics (Yu et al., 1996).

2.2 Device material parameter variations

Cfr4 The device material variations are also prominent sources of
variations. The variations can be accounted for doping,
Cfr3 Cfr1 deposition and anneal variations.
Cfr2 Doping variations. Deviations arising due to dose, energy,
Cov2 Clat angle, or other ion implant dependencies can affect junction
depth and dopant profiles (and thus may also impact effective
channel length), as well as affect other electrical parameters
Cov1 Cfr5 such as threshold voltage. Variations in thermal anneal and
gate doping can also change the degree of gate depletion in an
active device, and cause variation in the effective gate oxide
thickness. Depending on the gate technology used,
Source: Pucknell and Eshraghian (1988) these deviations can lead to some loss in the matching of

Effects of process variation in VLSI interconnects Microelectronics International
K.G. Verma, B.K. Kaushik and R. Singh Volume 26 · Number 3 · 2009 · 49 –55

Negative-Channel Metal Oxide Semiconductor (NMOS) 4. On-chip interconnect variations

versus Positive-Channel Metal Oxide Semiconductor
(PMOS) devices even in the case where within wafer and The source for on-chip variations (OCV) is related to
within die variation is very small. variation in interconnects height and width, resulting in
Deposition and anneal. Additional material parameter variation in both resistance and capacitance. Since the delays
attributed to interconnect are becoming more dominant as
deviations are observed in silicide formation, and in the
geometries shrink, particular attention should be paid to
grain structure of poly or metal lines. These variations may
accurate modeling of interconnect variations. In advanced
depend on the deposition and anneal processes. These
interconnect processes, which could involve use of multiple
material parameter deviations can contribute to appreciable
dielectrics, use of different metallization on different layers
contact and line resistance variation.
could result in significant variations. Depending on material
properties of low-k dielectrics, “dishing” could be observed
2.3 Device electrical parameter variations on metal lines spaced wide apart. Erosion is the other
In many cases, the underlying geometry distribution is not mechanism and is a function of line space and density.
characterized, but instead the key electrical parameters are Examples are shown in Figure 3.
directly extracted and modeled for device electrical parameter Two additional sources of variation are the CMP process
variations. and proximity effects in the photolithography and etch
Vt variation. A key concern is threshold voltage (Vt) processes. Variation in the CMP process results from the
variation. Threshold voltage of a MOSFET varies due to: difference of hardness of the interconnect material and that of
Changes in oxide thickness. the dielectric. Ideally the CMP process will remove the
Substrate, polysilicon and implant impurity level. unwanted copper, leaving only lines and vias. The
Surface charge. photolithography and etch proximity effects are shown in
micro loading effects as the etch process step tends to over-
Process variation may increase or decrease the aspect ratio
etch isolated lines. Diffraction effects and local scattering in
(W/L). Variation in W and L is caused by lithographic process.
photolithography may tend to over expose densely spaced
These variation are not correlated because W is determined in
lines and under expose isolated lines. Tiling and metal slotting
the field oxide step while L is defined in the polysilicon and
have been added as design rule requirements to mitigate these
source/drain diffusion steps. While many elements of Vt may
effects by minimizing the density gradient. Different tiling
be due to oxide thickness or other geometric deviations, algorithms will give varying results, but the smaller the density
additional sources of variation are often encountered. In gradient, the smaller the variations that will be seen on the die
particular, mobile charge in the gate oxide can introduce a (Jarrar and Taylor, 2006).
bias dependent variation; this is sometimes approximated as
being about 10 percent of the Vt of the smallest device in a 4.1 Cross-talk noise
given technology. Another source of Vt variation that is just Cross-talk noise is the main source of noise in static
beginning to become important in static random access complementary metal-oxide semiconductor (CMOS)
memory (SRAM) and other circuits related to random dopant designs (Nagaraj et al., 2001; Narasimha et al., 2006; and
fluctuations. In particular, as scaling of metal-oxide Demircan, 2006). The cross-talk noise increases the signal
semiconductor (MOS) devices continues into the deep settling time. Among several factors that affect the cross-talk
submicron regime, concern has been raised about the noise, key factors include aggressor/victim drive strengths,
random placement and concentration fluctuations due to parasitic resistance, inductance, capacitance (RLC) of the
discrete location of dopant atoms in the channel and source/ interconnect network, aggressor signal switching times,
drain regions. transistor device models and victim receiver noise margins.
Leakage currents. Sub threshold leakage currents may vary Unless cross-talk noise occurs on asynchronous signals such
substantially, and can be affected by shallow trench isolation as reset clear signals or on clock signals, cross-talk noise has to
structure and stress (Boning and Nassif, 2000). be strong enough to propagate through logic before it could
be detected. The glitch in the victim net from aggressor net
causes the victim net to take longer time to settle to its final
3. Interconnect characterization value. In static combinational logic, cross-talk increases the
Owing to the process variation, interconnect technology delay across a net; in dynamic logic cross-talk can cause the
parameters (ITP) are varying substantially. For simplicity, the state of a node to flip, causing a permanent error. The cross-
researchers consider variations in metal width (W), metal talk-induced delay is in fact the cross-talk-induced glitch
thickness (T), and inter-layer dielectric (ILD) thickness (H). plus the original response of the affected victim line. In simple
The typical distribution of ITP can be observed for terms the amplitude of the noise induced in a victim line scales
permittivity, ILD thickness, metal height and metal width with Cc/Ctot. Cross-talk noise verification could be classified
(Figure 2) (Boning and Nassif, 2000). The variation is into four major steps:
especially large in the ILD thickness and metal line width. 1 coupled network extraction;
Their variations have a definite impact to the total line 2 victim aggressor selection;
3 cluster network generation; and
capacitance and interline coupling capacitance and result in
4 cross-talk noise computation.
variation of the signal delay and cross-talk noise. The effect of
the process variation should be modeled, because its impact Process variations impact signal-integrity issues such as cross-
on the signal delay and cross-talk is substantial. The talk noise, coupling induced delay, electromigration, current
conventional skew corner worst-case modeling is too multiplied by resistance (IR) drop, etc. When process
conservative (Boning and Nassif, 2000). variations impact these parameters significantly,

Effects of process variation in VLSI interconnects Microelectronics International
K.G. Verma, B.K. Kaushik and R. Singh Volume 26 · Number 3 · 2009 · 49 –55

Figure 2 Typical distribution of Interconnect technology parameters

Permittivity IMD2 thickness IMD3 thickness
30 25
160 s/m = 0.2 s/m = 5.8 s/m = 7.1
×100 25 ×100 20 ×100
120 20
80 15
40 5
0 0 0
2.94 3.57 4.20 4.83 0.04 1.02 1.20 1.30 (mm) 0.04 1.02 1.20 1.30 (mm)

M3 height M3 width
60 40
s/m = 3.0 s/m = 4.6
50 ×100 ×100
30 20
0 0
0.02 1.12 1.32 1.52 (mm) 0.75 0.91 1.07 1.22 (mm)
Source: Boning and Nassif (2000)

Figure 3 CMP induced OCV on interconnects

the isolated victim (Sato et al., 2003; Bhardwaj et al., 2002).
Dielectric level before CMP These superposition-based approaches require accurate
Erosion modeling of static noise and nominal victim waveforms.
Dielectric level after CMP These waveforms must then be properly aligned to obtain
worst case delay change.
Static noise is defined as the noise pulse induced on a quiet
Dishing victim net due to the switching of neighboring aggressors.
Agarwal et al. (2006) discussed the impact of process variation
on static cross-talk noise in coupled RC-interconnects. Static
Copper noise can result in functional failures due to false switching of
Dielectric the victim line. For the first order, the magnitude of static
noise is directly proportional to the ratio of coupling
manufactured products may experience unexpected reliability capacitance to total ground capacitance. This causes the
failures. Therefore, it is extremely important to include noise magnitude to be very sensitive to variations in metal
variability during reliability analysis and optimization – this width and interwire spacing, and small variations in these
will minimize yield loss due to reliability failures caused by dimensions can result in large fluctuations in the noise peak.
process variation and ensure a robust design across the entire To prove this fact, consider a simple coupled RC-interconnect
process spread. test case. The width (W), thickness (T), spacing (S), and ILD
The impact of interconnect variations on signalintegrity layer thickness (H) for the interconnect lines are randomly
issues, such as cross-talk noise and coupling induced-delay chosen to be 0.4, 0.75, 0.45, and 0.3mm, respectively.
degradation (i.e. dynamic delay) is one of actively researched Moreover, the variation in W, T, and H are assumed to be 25,
area. Accurate statistical modeling of interconnect coupling 21, and 17 percent of the nominal values, respectively, (W and
requires accurate nominal models for cross-talk noise and S to be perfectly inversely correlated) (Agarwal et al., 2006).
coupling-induced-delay change caused by the simultaneous The spread of noise waveforms can be obtained using
switching of aggressor and victim wires. Simulation Program With Integrated Circuit Emphasis
Modeling static noise has been a rigorously studied topic (SPICE) Monte Carlo simulations.
and various static-noise models have been proposed time to Using simulations it is shown that for this test case, the
time that exhibit a high degree of accuracy (Sakurai, 1993; noise peak varies from approximately 160 to 235 mV, thereby
Vittal et al., 1999; Devgan, 1997; Acar et al., 1999; Ding et al., implying that variation in noise due to process variation can
2003; Chen and Marek-Sadowska, 2002). However, accurate be significant and should be modeled accurately. The noise-
estimation of cross-talk-induced delay remains a challenging peak distribution is Gaussian and the mean and variance of
task. Typically, dynamic delay is modeled by replacing the this distribution is obtained using the Monte Carlo results.
coupling capacitance between two wires by an equivalent The impact of noise on functional failures is typically
ground capacitance based on the Miller effect. A few other characterized by noise-immunity curves.
approaches model dynamic delay by the superposition of Dynamic delay is defined as the signal delay on the victim
a static-noise waveform on the nominal switching waveform of line when both the aggressor and the victim switch

Effects of process variation in VLSI interconnects Microelectronics International
K.G. Verma, B.K. Kaushik and R. Singh Volume 26 · Number 3 · 2009 · 49 –55

simultaneously. It is well known that an adjacent switching Surface and grain boundary scattering of electrons increases
aggressor can either slow down or speed up a victim the resistance for narrow width wires. As technology
depending on its switching polarity with respect to the continues to scale, the tail would become more prominent
victim. The victim becomes slower in the case of out-of-phase due to increased electron scattering effect. The delay
switching and faster due to in-phase switching. The delay distribution using Monte Carlo simulations shows that, even
push-out during out-of-phase switching is a major concern with large variations in geometric dimensions, the delay
due to the possibility of setup-time failures, and hence, must distribution remains Gaussian.
be accounted for in order to ensure correct operation of the Characterizing and managing process variations of
circuit. The dynamic-delay modeling with and without interconnect geometry is becoming critical for 0.13 m and
process variations can ascertain the effect of process below. Delay analysis can no longer ignore process variations
variations. for 0.13 m and below technologies. Individual parameter
Cross-talk noise is relatively less Gaussian than cross-talk sensitivity analysis show that the delays are most influenced by
delay. The propagated noise is even less Gaussian. This can the interconnect resistance and capacitance (Lu et al., 2004b).
be attributed to non-linear nature of the transfer functions of
the CMOS gates. 4.3 Parametric delay evaluation under process variation
In order to address the effect of process variation, the various
4.2 Delays due to interconnect variation methods are:
Interconnects have turned out to be most crucial factor of .
clock skew analysis under process variation;
signal delays, especially, in deep and very deep submicron .
statistical performance analysis;
designs. Timing margin have become so small as frequencies .
worst case performance analysis parametric yield
increase that even pico-second variations can no longer estimation;
be ignored, in particular for high-speed clock design. Global
impact analysis on micro architecture; and
interconnect delay increases as technology scales down. To
. delay fault test under process variation.
mitigate the global interconnect delay problem metal wires In all the above research, one important task is to compute
have been scaled in a selective fashion. Optimal buffer variational path delay under process variation, either as
insertion methods, which reduce delay from quadratic to functions of process variables or as random variables of
linear, become difficult as the number of buffers increase at a certain distribution. However, the conventional methods to
fast rate. The proliferation of buffers also leads to increased compute path delay are either slow or inaccurate. The
power in designs. Alternatives to buffer insertion have been response surface method (RSM) performs multiple
proposed, some of which include static source-follower driver simulations to obtain high accuracy; the RSM method must
(Kil et al., 2006), differential current sensing, and multilevel perform multiple parasitic extractions under different process
signaling. In multilevel signaling approach, matching conditions (Brawhear et al., 1994; Acar et al., 2001; Gattiker
and proper sizing of the driver and receiver transistors is et al., 2001; Fabbro et al., 1995). Since, there are a large,
done and it is thus prone to process variations, resulting in number of metal layers in the modern technology, there are
doubled bandwidth and delay comparable to buffer insertion. many interconnect process variables. For example, for a
Simply scaling down the supply voltage, undesirable k-layer technology, there are 3 k process variables,
characteristics of scaled CMOS, such as drain induced corresponding to the metal width, metal thickness and
barrier lowering, quantum mechanical gate tunneling, and inter-layer dialectic thickness of each layer. Thus, the
punch through can also be alleviated. In the sub-threshold traditional RSM becomes prohibitive for large circuits.
region, the MOS gate capacitance is significantly less than Another method Parametric Delay Evaluation (PARADE)
that in the super-threshold region due to the channel for fast using analytical formulae and pre-characterized
depletion capacitance that appears in series with the oxide lookup tables is used to estimate for the interconnect delays.
capacitance Kil et al. (2006). Unlike MOS gate capacitance, In this method variational path delays is evaluated efficiently,
the wire capacitance value is independent of the supply based on the lumped C delay model and based on the effective
voltage. As a result, the CV/I delay of wires increase more capacitance delay model, respectively. No multiple parasitic
steeply than that of logic gates in subthreshold circuits, extractions and multiple delay evaluations are needed
exacerbating the global interconnect delay problem. (Lu et al., 2004b). The efficiency of this method makes it
To first order, delay through an interconnect can be possible to comprehensively analyze circuit performance on all
expressed as the RC product of its resistance and capacitance. interconnect and device process variables for large circuits.
With any change in the physical dimensions of the wire, its Compared to the traditional RSM, the delay error is within
resistance and capacitance also change, causing interconnect 7 per cent using analytical methods, and is within 1 per cent
delay to fluctuate. In order to model the impact of variability using the table lookup method in PARADE (Lu et al., 2004b.
on wire delay, one needs to capture the effect of geometric Thus, PARADE method avoids multiple parasitic extractions
variations on the electrical parameters. The change in and multiple delay evaluations as did in the traditional RSM,
electrical parameters due to variations in geometric and results in significant speedup. Since this method is based
dimensions can be captured by the simple linear on effective capacitance delay model it achieves higher
approximation. accuracy (Lu et al., 2004b).
The thickness of metal lines can vary at the bottom due to
etch effects. CMP effect influences the thickness variation
5. Interconnect analysis
from the top of the metal, varying the interwire resistance and
capacitance. Though the distribution of resistance is fairly By accounting for systematic part of process variation in
Gaussian, the tail of the distribution can be attributed to non- timing analysis, uncertainty in interconnects analysis can be
linear increase in resistance due to electron scattering effects. reduced, thereby achieving closer bound for circuit

Effects of process variation in VLSI interconnects Microelectronics International
K.G. Verma, B.K. Kaushik and R. Singh Volume 26 · Number 3 · 2009 · 49 –55

performance. One way of random analysis is to use OPERA reduction in the parametric yield. Thus, determining an
technique that models the stochastic response in an infinite accurate statistical description (e.g. moments, distribution,
dimensional Hilbert space in terms of orthogonal polynomials etc.) of the interconnect’s response is critical for designers. In
expansions (Vrudhula et al., 2006). It is the prototype the presence of significant variations, device or interconnect
software that has the capability to carry out a SPICE Monte model parameters such as wire resistance, capacitance, etc.
Carlo analysis. Using such a polynomial representation, need to be modeled as random variables or as spatial random
there is no need to repeatedly generate samples of the random processes. Furthermore, in addition to metal thickness and
parameters, and solve the system as required in Monte Carlo width variation, damaged dielectric regions on the side of the
approach. The accuracy in obtaining the variance by OPERA metal lines are important contributions to cross-talk and
can be increased further by increasing the order of the delays. It has also been comprehended that process variations
expansion. This provides an attractive alternative to the are not completely random data. The systematic part of
computationally expensive Monte Carlo simulations (Wang variations plays an important role in deviating electrical
et al., 2004). parameters.
Typically, ITP are fixed by parasitic extractors and a single
fixed value is used for the ILD or metal thickness of each
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Corresponding author
Malavasi, E., Zanella, S., Min, C., Uschersohn, J., Misheloff, M.
and Guardiani, C. (2002), “Impact analysis of process B.K. Kaushik can be contacted at:

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