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TCL L42M61S2

SERVICE MANUAL

MT02

1ǃCautionĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂ2
2ǃSpecification of Chassis ĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂ6
3ǃTheory of circuits ĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂ7
4ǃAlignment Procedure ĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂ16
5ǃBlock Diagram ĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂ 28
6ǃSchematic Diagram ĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂ30
7ǃTrouble shooting ĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂ 49
0DLQRI,&ĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂ53
8ǃ0
9ǃBOM list ĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂĂ 

This manual is the latest at the time of printing, and does not include the modification which
may be made after the printing, by the constant improvement of product


CAUTION:
Use of controls, adjustments or procedures other than those specified herein may result in
hazardous radiation exposure.

CA UTION: TO REDUCE THE RISK OF


CAUTION ELECTRICAL SHOCK, DO NOT REMOVE
RISK OF ELECTRIC COVER (OR BACK). NO USER SERVICEABLE
SHOCK DO NOT OPEN. PARTS INSIDE. REFER SER VICING TO
QUALIFIED SERVICE PERSONNEL.

The lighting flash with arrowhead symbol, with an equilateral triangle is intended to
alert the user to the presence of uninsulated voltage within the products
enclosure that may be of sufficient magnitude to constitute a risk of electric shock to
the person.

The exclamation point within an equilateral triangle is intended to alert the user to the
presence of important operating and maintenance (servicing) instructions in the
literature accompanying the appliance.

WARNING: TO REDUCE RISK OF FIRE OR ELECTRIC SHOCK, DO NOT


EXPOSE THIS APPLIANCE TO RAIN OR MOISTURE.


IMPORTANT SAFETY INSTRUCTIONS
CAUTION:
Read all of these instructions. Save these instructions for later use. Follow all Warnings and
Instructions marked on the audio equipment.
1. Read Instructions- All the safety and operating instructions should be read before the product is operated.
2. Retain Instructions- The safety and operating instructions should be retained for future reference.
3. Heed Warnings- All warnings on the product and in the operating instructions should be adhered to.
4. Follow Instructions- All operating and use instructions should be followed.

FOR YOUR PERSONAL SAFETY


1. When the power cord or plug is damaged or frayed, unplug this television set from the wall outlet and refer servicing to
qualified service personnel.
2. Do not overload wall outlets and extension cords as this can result in fire or electric shock.
3. Do not allow anything to rest on or roll over the power cord, and do not place the TV where power cord is subject to
traffic or abuse. This may result in a shock or fire hazard.
4. Do not attempt to service this television set yourself as opening or removing covers may expose you to dangerous
voltage or other hazards. Refer all servicing to qualified service personnel.
5. Never push objects of any kind into this television set through cabinet slots as they may touch dangerous voltage
points or short out parts that could result in a fire or electric shock. Never spill liquid of any kind on the television set.
6. If the television set has been dropped or the cabinet has been damaged, unplug this television set from the wall outlet
and refer servicing to qualified service personnel.
7. If liquid has been spilled into the television set, unplug this television set from the wall outlet and refer servicing to
qualified service personnel.
8. Do not subject your television set to impact of any kind. Be particularly careful not to damage the picture tube surface.
9. Unplug this television set from the wall outlet before cleaning. Do not use liquid cleaners or aerosol cleaners. Use a
damp cloth for cleaning.
10.1. Do not place this television set on an unstable cart, stand, or table. The television set may fall, causing serious injury
to a child or an adult, and serious damage to the appliance. Use only with a cart or stand recommended by the
manufacturer, or sold with the television set. Wall or shelf mounting should follow the manufacturer s instructions, and
should use a mounting kit approved by the manufacturer.
10.2. An appliance and cart combination should be moved with care. Quick stops, excessive force, and uneven surfaces
may cause the appliance and cart combination to overturn.


PROTECTION AND LOCATION OF YOUR SET
11. Do not use this television set near water ... for example, near a bathtub, washbowl, kitchen sink, or laundry tub, in a
wet basement, or near a swimming pool, etc.
Never expose the set to rain or water. If the set has been exposed to rain or water, unplug the set from the wall
outlet and refer servicing to qualified service personnel.
12. Choose a place where light (artificial or sunlight) does not shine directly on the screen.
13. Avoid dusty places, since piling up of dust inside TV chassis may cause failure of the set when high humidity persists.
14. The set has slots, or openings in the cabinet for ventilation purposes, to provide reliable operation of the receiver, to
protect it from overheating. These openings must not be blocked or covered.
Never cover the slots or openings with cloth or other material.
Never block the bottom ventilation slots of the set by placing it on a bed, sofa, rug, etc.
Never place the set near or over a radiator or heat register.
Never place the set in a built-in enclosure, unless proper ventilation is provided.

PROTECTION AND LOCATION OF YOUR SET


15.1. If an outside antenna is connected to the television set, be sure the antenna system is grounded so as to provide some
protection against voltage surges and built up static charges, Section 810 of the National Electrical Code, NFPA No.
70-1975, provides information with respect to proper grounding of the mast and supporting structure, grounding of the
lead-in wire to an antenna discharge unit, size of grounding conductors, location of antenna discharge unit, connection
to grounding electrode, and requirements for the grounding electrode.

EXAMPLE OF ANTENNA GROUNDING AS PER NATIONAL ELECTRICAL CODE INSTRUCTIONS

EXAMPLE OF ANTENNA GROUNDING AS PER


NATIONAL ELECTRICAL CODE

ANTENNA
LEAD- IN WIRE

GROUND CLAMP

ANTENNA DISCHARGE
UNIT (NEC SECTION
810-20)

GROUNDING
CONDUCTORS
ELECTRIC SERVICE (NEC SECTION 810-21)
EQUIPMENT

GROUND CLAMPS

POWER SERVICE GROUNDING


NEC-NATIONAL ELECTRICAL CODE ELECTRODE SYSTEM
(NEC ART 250. PART H)

15.2. Note to CATV system installer : (Only for the television set with CATV reception)
This reminder is provided to call the CATV system installer s attention to Article 820-40 of the NEC that provides
guidelines for proper grounding and, in particular, specifies that the cable ground shall be connected to the grounding
system of the building, as close to the point of cable entry as practical.
16. An outside antenna system should not be located in the vicinity of overhead power lines or other electric lights or power
circuits, or where it can fall into such power lines or circuits. When installing an outside antenna system, extreme care
should be taken to keep from touching such power lines or circuits as contact with them might be fatal.
17. For added protection for this television set during a lightning storm, or when it is left unattended and unused for long
periods of time, unplug it from the wall outlet and disconnect the antenna. This will prevent damage due to lightning
and power-line surges.


OPERATION OF YOUR SET
18. This television set should be operated only from the type of power source indicated on the marking label.If you are not
sure of the type of power supply at your home, consult your television dealer or local power company. For television
sets designed to operate from battery power, refer to the operating instructions.
19. If the television set does not operate normally by following the operating instructions, unplug this television set from the
wall outlet and refer servicing to qualified service personnel. Adjust only those controls that are covered in the operating
instructions as improper adjustment of other controls may result in damage and will often require extensive work by a
qualified technician to restore the television set to normal operation.
20. When going on a holiday : If your television set is to remain unused for a period of time, for instance, when you go on
a holiday, turn the television set and unplug the television set from the wall outlet.

IF THE SET DOES NOT OPERATE PROPERLY


21. If you are unable to restore normal operation by following the detailed procedure in your operating instructions,
do not attempt any further adjustment. Unplug the set and call your dealer or service technician.
22. Whenever the television set is damaged or fails, or a distinct change in performance indicates a need for
service, unplug the set and have it checked by a professional service technician.
23. It is normal for some TV sets to make occasional snapping or popping sounds, particularly when being
turned on or off. If the snapping or popping is continuous or frequent, unplug the set and consult your
dealer or service technician.

FOR SERVICE AND MODIFICATION


24. Do not use attachments not recommended by the television set manufacturer as they may cause hazards.
25. When replacement parts are required, be sure the service technician has used replacement parts specified
by the manufacturer that have the same characteristics as the original part. Unauthorized substitutions
may result in fire, electric shock, or other hazards.
26. Upon completion of any service or repairs to the television set, ask the service technician to perform
routine safety checks to determine that the television is in safe operating condition.f


EM BUSINESS CENTER
FTV PRODUCT PLANNING DEPT.
SPECIFICATION RELEASE
Version: V1.0 Issued Date: 2007.06.25

Model: L42M61S2
PICTURE
Panel Size (inch) 42
Category LCDTV
Aspect Ratio 16:9
Color Temperature Adjustable(Cold,Warm,Standard) SIGNAL FORMAT CAPABILITY
Backlight Adjustable Yes Component Video Format Y,Pb/Cb,Pr/Cr: up to 720p,1080i@50Hz/60Hz
Scaler Mode 16:9,16:9 subtitles,4:3,Cinema DVI Video Format -
Picture Effect 4 (Bright,Standard,Soft,Personal) HDMI Video Format (720p,1080i)@50Hz/60Hz
Film Mode (3:2 pull down) Yes PC Compatibility VGA/HDMI: Up to SXGA (1280*1024 @75Hz)
Picture Enhancement TERMINALS
Comb Filter 3D Audio/CVBS Input (Composite) 3 Video + 3 R/L :AV1 and AV2 rear,AV3(side)
Gamma Correction Yes S-Video Input 1
3D+ Engine (Advanced flesh tone and color processing) Audio Input for S-Video Share with AV2
Core Technology
MDDi Engine (2nd generation proprietary de-interlacing technology) YPbPr Input 1
Blue Stretch - Audio Input for YPbPr 1 R/L
Black Stretch Yes YCbCr Input Share with "YPbPr"
Automatic Luma/Chroma Gain Control Yes Audio Input for YCbCr Share with Audio Input for "YPbPr"
DLTI Yes VGA Input(RGB) 1 (D-Sub,15-Pin)
DCTI Yes Audio Input for RGB 1 (ž3.5mm)
Dynamic Skin Correction Yes DVI -
DNR Yes (Motion-adaptive 3D Noise Reduction) Audio Input for DVI -
Panel Specification HDMI 1
Panel supplier LPL Audio/CVBS Output (Composite) 1 (R/L+CVBS) (RCA)
Viewing Technology SIPS Woofer Output 1
Display Resolution WXGA (1366*768) Headphone Output 1 (ĭ3.5mm )
Brightness (cd/m2) 500 RF Input(Antenna) 1 (F Type)
Contrast Ratio 1000:1 USB -
Response Time 5ms (G to G) BASIC INFO.
Viewing Angle (H/V) 178°/178° TV System NTSC M,PAL M/N
Life Time 50,000hrs (min) AV System NTSC/PAL
Color 16.7M Channels 125(CATV)+68(Antenna) free program presets
SOUND Chassis MT02
Speakers 2 Integrated (bottom side) Certification CB
Audio Power Output 8W*2 Power Supply AC 110V-240V 50/60Hz
Sound Processing MTS Stereo(BTSC-SAP) Power Consumption-TV on 220W
DVSS(Dolby Virtual Surround) - Power Consumption-Standby Less than 3W
AVC(Auto Volume Control) Yes Default Color of Front Cabinet Black
BBE - Keyboard Position Top
SRS - Base Stand Detachable Yes
Sound Effects (Stereo,Music,News,Movie,Personal), Unpackaged Dimension for Main Body (L*H*D) (mm)
Sound Features
AVL,Treble,Bass,Woofer With Base Stand (mm) 1058*765*270
Sound Control Volume,Balance,Sound Effects etc.. Without Base Stand (mm) 1058*711*116
FUNCTION Packaged Dimension (L*H*D)
V-Chip Yes Main Body (mm) 1211*889*364
CCD(Closed Caption) Yes Speaker Box (mm) --
Teletext - Base Stand (mm) Packaged with Main Body
PIP/POP - Net Weight (Kg) 27.5 (Main Body and Base Stand)
Macro Vision Yes Gross Weight (Kg) 33 (main body and base stand)
Calendar - Container Loading
Clock/Timers 24h Timer turn ON/OFF;Sleep timer 20 feet 56˄With base stand˅
Lock Yes (parental lock) 40 feet 118˄With base stand˅
OSD language English/Spanish/Portuguese/French 40 feet high 177˄With base stand˅
OSD Features - ACCESSORIES
Card Reader - Operation Manual English(Default)
DVD Combo - Remote Control For TV control (with two 5# batteries)
USB Connection - Base Stand Yes
Game - Speaker Box Integrated
Screen Saver - Wall Mount Optional (WMB400)
Demo Function - Others AC Power cord
Favourite Channels Yes (6)

Drafted by:
Approved by:

Design and specifications are subject to change without notice! Page 1 of 1


This manual just used for experienced technician, not for any public people. There is not any caution
and mention in this manual for one whom unqualified technician attempt to service this product. This
product should be serviced by special technician, only other persons attempt to service it might have heavy
hurt even have life hazard.

Theory of circuits
Chassis MT02 adopt MT8202 of MTK Company. MT8202 is configured with video decoder, audio
decoder, CPU, decoder, and picture quality processor. Power supply unit is JSK4338. This chassis is
high picture performance and fully integrated IC, matching circuit and alignment is very simple.
Refer to LCD42K73/MT02 as representative, the power consumption is 240W˄Max.˅, the standby

consumption is less than 1W. The Sound speaker’s power is 2x8W.The PSU(power supply unit) has 3
part voltage output: 5v for standby, 24v for inverter, 12v for signal process.

This chassis compose of 7 boards, they are main board, tuner board ,AV board, side AV board, keypad
board, USB board, power board.
The unit supports 1x RF in, 2XAV,1x S-video and common AV audio input. 2xUSB input , one way has
print function, the another way connect with high definition signal source ,it supports SDTV, HDTV, The
highest signal format reaches 1920h1080@60IDŽ1xVGA input, supports the signal format have VGA,
SVGAˈXGAˈSXGADŽ1xheadphone output ,1x AV output. 1xHDMI input , supports most of HDMI format
of video and audio input.

Chapter I Signal Flowing Introduction

There are 7 boards for signal process: main board, tuner board, AV board, side AV board, keypad board,
USB board, power board.
Section I Tuner board signal flowing introduction

Turner board mostly assemble are turner and I2C bus control TDA9886 and audio .video SAW filter circuit.

TV signal flow:
75OMH antenna received high frequency TV signal input to tuner U601A disposal. U601A is a common
tuner .through tuner inside circuit disposal: high frequency amplifier, mixing, filtering, IF amplifier, detection,
pre-video amplifier, AGC, AFT, PLL etc. From U601A output IF signal through Z610,Z611 disposal, PIF and AIF
signal send to Pin1,Pin2,Pin23,Pin24 of IC601, after TDA9886 IF amplifier disposal, from pin17 output color full TV
signal into audio disposal circuit process .
TDA9886 is multi system video and audio IF signal PLL demodulator without adjustment, using for positive
and negative modulator and AM/FM processor.
Characters as follow:
1. Power supply voltage of 5V
2. Gain controlling broad band PIF amplifier AC coupling
3. Multi standard synchronization demodulation, linearity demodulation
4. Multi system PIF
5. Audio IF disposal IC


6. Audio apart circuit
7. Reducing the picture interference from audio
8. Full integrated VCC
9. 4M norm frequency input
10. Accurate fully digital AFC detector, 4 bit ADC, through IIC BUS exchange AFC data.
11. Through IIC adjusts receive point
12. SIF-AGC, gain control SIF amplifierˈsingle norm QSS
13. AM demodulation without outside reference circuit
14. Choose FM-PLL demodulation without adjustment ,high linearity and low noise
Pin function
OSD NO FUNCTION
VIF1 1 VIF difference input
1
VIF2 2 VIF difference input
2
NC ˉ Empty pin
OP1 3 Output port 1
FMPLL 4 Loop filter FM-PLL
DEEM 5 Get rid of aggravate
output
AFD 6 AF demodulation
coupled
DGND 7 Figure grounding
NC ˉ Empty pin
AUD 8 Audio input
TOP 9 Tuner received point
SDA 10 IIC data input and
output
SCL 11 IIC clock input
SIOMAD 12 Inside carrier
frequency audio
output MAD option
NC ˉ Empty
NC 13 Empty
NC ˉ Empty
TAGC 14 Tuner AGC output
REF 15 4M crystal or norm
signal output
VAGC 16 VIF_AGC
NC Empty pin
CVBS 17 Complex video
signal output
NC Empty pin
AGND 18 Analog grounding
VPLL 19 Loop filter FM-PLL
VP 20 Power supply
AFC 21 AFC output
OP2 22 Output port 2
NC Empty pin
SIF1 23 SIF difference input
1
SIF2 24 SIF difference input
2
NC ˉ Empty
NC ˉ Empty


Section II Digital board signal flowing introduction

LCD42K73/MT02 digital board chassis adopted ICs are U27-DC change DC disposal circuit, makes the 12v
changed to 5v, U21ǃU23ǃU24ǃU37-AZ1117 are three-terminal voltage regulator, it makes 3.3v changed to 1.8v;
U3-MT8202 IC include CPU, audio/video decoder, picture tone disposal etc functions; U4ǃU5-M13S128168 8M
picture ,audio memory, U7-29LV160 saves CPU programs; U36-CM2021 HDMI socket prevent static regulator;
U8-MT8293 HDMI decode regulator; U11-EEPROM 24C02; U12-CS5340 audio A/D change input ; U13-HEF4052
audio change switch˗U14-P15V330 video change switch.;
Signal input:
Signal input include:one way RF signal,three ways AV signal, VGA,HDMI,YUV.
1ǃRF input
From high frequency board sends CVBS connected to digital board through JP6.
Video signal: from pin5 of the JP6 sends CVBS signal, through R354 limiting current, coupled by CE197 signal
sent to Q3 and video signal amplify , from emitter of Q3 sent video signal to D25pin of 8202 IC, process TV video
signal decode disposal.
Audio signal: audio signal from pin7 of JP6 sent out and separate two paths TUMPX1ǃTUMPX2 signal. They
are through filter which compose of R212ǃC48ǃC139 and R215ǃC143ǃR216ǃC144, the audio signal after filter
input to C26pin B26pin of U3 process audio signal decode.
2ǃAV signal input
From CN2ǃCN5ǃCN7 input AV1ǃAV2ǃAV3 signal, each through D11ǃD12ǃD13 prevent static protection
IC process disposal.
Video signal:
Video signal AV1_ V/AV2_ V/AV3_ VǃA1/A2/C1 sent to U3 process picture signal disposal.

AV1ǃAV2ǃAV3 video signal:


From JP603ǃJP604ǃJP605 sent AV1ǃAV2ǃAV3 video signal through D11ǃD12ǃD13 prevent static
protection IC process disposal. Video signal after filtering by filter which compose of C11ǃR118ǃC13ǃR119ˈ
C7ǃC8ǃR96ǃR101, then input U3’s PinD26, PinE26, PinE25 and disposal video signal.

Audio signal:
Audio signal of AV1ǃAV2ǃAV3 from JP603ǃJP604ǃJP605 output L/R audio signal, through filter circuitry
which compose of CE15ǃR26ǃCE18ǃR34ǃCE17ǃR28ǃCE20ǃR36 and input audio switch IC U2, through U2
to change the audio signal for corresponding signal channel and output L/R audio signal from Pin13 and Pin3, then
send to digital audio disposal IC U3. The digital audio signal from U3’s P1~P4 pin output, through U15
digital/simulative change ,output L/R simulative audio signal send to audio power amplifier U17A.

3ǃS-video signal input


video channels:
S-video signal from JP607 input, the YǃC signal separate two ways to process.
First channel signal :pin1 of JP607 output Y signal through R46 limiting current and coupled by C14 get
AVSY0 signal connected to Pin F25 of U3 to process video disposal.
Second channel signal; pin2 of JP607 output Y signal through R44 reduced voltage, FB10ǃC16ǃC17 restrain
noise signal interference and filter , coupled by C17 and get AVSC0 input PinF26 of U3 to process video disposal.
Audio channel: share with the channel of AV3.

4ǃYUV˄HDTV˅input
From CN1 input YǃUǃV signal, through L53ǃL54ǃL55 filtering , CN2 connected audio signal.
Video channel: YǃUǃV signal separate through R199/R55ǃR203/R206ǃR207/R210 limiting current, coupled
by C112/C115ǃC119/C122ǃC129/C133. The signal of YO+/YO-ǃPBO+/PBO-ǃPRO+/PRO-ˈconnected to U3’s
PinP25ǃP26ǃN25ǃN26ǃI25ǃI26 process video disposal.

Audio signal:
Pin4 and pin2 of the CN2 output YUV_AUDIO_LǃYUV_AUDIO__R audio signals separate through CE192ǃCE193
coupled, then filter by R350/R351ǃR352/R353. Direct input PinA25/A26 of U3 to proceed audio decode disposal.
5ǃVGA signal input
From P2 input VGA’s RǃGǃBǃhorizontal and vertical signal.
Video channel: From P2 output VGA’s RǃGǃBǃsignal through R131/R137/R145 limiting current, coupled by
C88/C92/C97 and get RED+/RED-ǃGREEN+/GREEN-ǃBLUE+/BLUE- signalˈseparate connected with U3’s


PinR26/R25ǃPinT26/T25ǃPinU26/U25, pin14 and pin13 of P2 output H/V signals separate through R332ǃR333ǃ
C100ǃC102 coupled to PinV25 and PinV26 of U3 to proceed video signal disposal.

6ǃHDMI signal input


P1 input HDMI signal, dispart as one couple of clock signals and three couples of data signal. Pin12 and pin10
of P1 output R1XC-ǃR1XC+ clock signal through IC U36 disposal then connected to pin50 and pin51 of
U8(MT8293),pin9/pin7/pin6/pin4/pin3/pin1 output DATA0-/DATA0+ǃDATA1-/DATA1+ǃDATA2-/DATA2+dates
through U36 disposal then connect to pin54 /pin55/pin58/pin59/pin62/pin63 of U8,after U8 disposal then dispart as
two paths output.
Video channel: pin95 –pin92/pin99-pin105/pin108-pin111, pin114- pin117/pin121-pin124/pin110-pin113 of U8,
output 24 bits date signal VI[0Ă23],through RN26~RN32 connected to U3’s AF20ǃAE20ǃAD20ǃAD21ǃAC21ǃ
AF22ǃAE22ǃAD22ǃAF23ǃAD23ǃAF24ǃAE24ǃAD24ǃAF25ǃAF26ǃAE25ǃAE26ǃAD25ǃAD26ǃ
AC25ǃAC26˗pin1 and pin128 of U8 output HDMI-HS H/V synchronization signals; process video processing...
Pin71-pin74 of U8 output four paths digital audio signal separate connected to pin AA23~AA26 of U3 to process
digital audio decode processing..

Video signal processing:


ķThrough first channel input U3’s CVBS signal, AV signal, S-VIDEO signal, YUV signal, through inside
option switch control output analog signals, after analog to digital conversion module makes the analog signal change
to digital signal.
Under U3’s memory controller controlling, the built-in video decoder, format converter and external flash
U4,U5(M13S128168 8M), the signal through 3D comb filtering, color decoder, synchronization signal disposal, VBI
amplitude limitation, diagonal angle disposal, noise reducer, progressive converter, format zoom converter, picture
quality enhance and so on disposal, and generate main picture’s display matrix.

ĸThrough second channel input U3 digital signal, under the MCU controlling, to improve picture quality of
sub-picture, and generate display matrix of sub-picture. the two pictures’ signal will be processed picture cover
disposal, r correction, LCD speedup drive. OSD display cover disposal, then process output format conversion ,
changed to LVDS format. Under LVDS transport controller controlling and output display signal to LCD screen
interface.
Audio signal processing˖
There were two kinds of signal input to U3:
ķSound IF signals, chose by switch inside IC, after gain enlarge, after analog to digital converter change to
digital signal. Then send to NICAM decoder, and demodulated audio signal;
ĸL/F channels of audio signal chose by switch inside IC after analog to digital converter change to digital
signal.
The audio signal which chose by sound switch output from one disposal channel.

Speaker channel: After sound effect disposal, through ADC modulus changed to analog signal. It out from
PinA18/A17 of U3, separate input sound disposal circuit, then output to speaker to restore the sound.

Signal output:
AV channel output:
Video signal: Pin B25 of U3 output simulation complex video signal, after coupled by R181ǃCE67 and sent to
base of Q7, output from emitter of Q7, then through capacitor CE68 coupling output complex video signal.

LCD display signal output:


ķFrom pin C12ǃD12ǃC11ǃD11ǃC10ǃD10ǃC9ǃD9ǃC8ǃD8ǃA12ǃB12ǃA11ǃB11ǃA10ǃB10ǃ
A9ǃB9ǃA8ǃB8 of U3 output RǃGǃB LVDS signal separate connected to pin1~6\10~13\15~16\18~19/22~23 of
JP11;P25 pin R26 pin of U3 output DHS HǃDVS V synchronization signals connected to pin9 and pin8 of JP11,from
U3 output CLK+/CLK-display synchronization clock signals connected to pin21 and pin20 of JP11;From U3 output
controlling signal connected to pin28 and pin29,pin30 of JP11,then from the cable output to display circuit of LCD,
LCD display the picture.
ĸFrom pinAC18 of U3 output controlling signal PPWR connected to R156 and base of Q31,mixed with
+5V,output to pin26 and pin27 of JP11,supply the working power to screen of LCD.

OCM signal controlling:


EPROM controlling:
U3 through fllowing connection to control the U7:
From pinA5 of U3 output signal to control EPROM operation, pinB5 of U3 output signal to control EPROM of


read operation, pinJ2 of U3 output signal to control EPROM of writing operation.

U3 and U7 through following connection to exchange the date.


Pin+?+?+?*?*?*?*?)?)?)?)?'?'?'?'?(?(?(?(?& and U7’s
pin10\9\1617\48\1\2\3\4\5\6\7\8\18\19\20\21\22\23\24\25 connected was address line˗
3LQ$?$?$?%?%?%?& and pin44\42\40\38\35\33\31\29 of U7 connected were data linesDŽ

Turn on/off controlling


Turn off: through standby turn off,makes the ON/OFF signal output low level ,power board detected ON/OFF
signal output low leve and makes the 12v and 24v shut down, so that into standby state, follow two ways enter
standby situation:
ķwhen OCM received standby signal, remove control receiver connected to pin7 of JP9, MCU identified the
standby order and makes ON/OFF output low level.
ĸreal time clock setting controlling, when the timing off is out , then MCU makes ON/OFF output low level.
Turn on: ON/OFF signal makes MCU output high level that can turn on the TV, power board detected ON/OFF
signal output high level and the 12v and 24v output. Follow three ways can turn on the TV:
ķWhen the remove control send out turn on order.
ĸ detected PRG+/PRG- button on local control board be pressed.
ĹReal time setting control, the turn on time is outing.

Mute circuit controlling:


ķTurn on/off mute
Turn on: when the power booting, at first point, +12v voltage through R59ˈQ14 charges to C283.makes Q14
turnon, thus output high level pulse, then through Q21 reverse phase output low level pulse ,makes sound power
amplifier U16 in standby model, thus it was mute when turn it on.
Turn off :after cut off the power supply, as the 12v voltage was disappear ,but C283 still has voltage,Q15 turn
on, makes C283 discharge from Q15,thus output high level pulse , then through Q21 reverse phase output low level
pulse ,makes power amplifier U16 in standby model, thus it is muting when turn it off.

ĸMCU controlling mute


Controller U3’s Pinw4 send high level pulse signal, it through R336ǃQ21ˈmakes the sound power amplifier
U16 in standby state ,so that can control turn off in mute state.

Section III Power board signal flow introduction

&KDVVLV07XVLQJSURMHFWRISRZHUVXSSO\ZDV-6.DŽ
Input characteristics:
,QSXWYROWDJHUDQJHWR9$&
,QSXWIUHTXHQF\UDQJHWR+]
,QSXWFXUUHQW$LQSXWIXOOORDG
(IILFLHQF\GaPLQPD[
Surge current :100A max when input 220vac

Output characteristics:
7KUHHZD\VRXWSXWYROWDJH˖967%˄$˅ǃ9GF $ ǃ9GF $ ǃ9GF $ DŽ
9VWDUWXSGHOD\WLPH˖OHVVRUHTXDOWKUHHVHFRQGVDŽ
7XUQRQFRQWUROOHYHORYHU9KLJKOHYHO
Output protection characteristics:
ķRYHUYROWDJH—™–›ŒŠ›GŠ–•›™–““•Ž


9RXWSXWFLUFXLW˖9DŽ
9RXWSXWFLUFXLW˖9DŽ
9RXWSXWFLUFXLW˖9DŽ
9RXWSXWFLUFXLW˖9DŽ
ĸRYHUFXUUHQW—™–›ŒŠ›GŠ–•›™–““•Ž
9RXWSXWFLUFXLW˖a$DŽ
9RXWSXWFLUFXLW˖a$DŽ
9RXWSXWFLUFXLW˖a$DŽ
9RXWSXWFLUFXLW˖a$DŽ
Protect controlling:
Short circuit protection, while there is short circuit in output path, the power supply unit entered short circuit protect,
it is can start up again while short circuit is removed. 

Over voltage protection: while voltage output is over voltage, the circuit entered protection situation, it
means no voltage output. G
Over temperature protection, while the temperature rise to abnormal, the circuit entered protection situation, when
the temperature decrease to normal, the power supply unit restore normal.

6LJQDOIORZLQJDQGFLUFXLWDQDO\VLV
1ǃchoose project
ljANJ˖Main IC
Using regulated power supply controlling IC L6563 and L6599 of SANTE company.
Basic characteristics:
ķˊ$YHUDJHFXUUHQWPRGHO
ĸˊ(UURUDFWLRQDXWRORFNSURWHFWLRQIXQFWLRQ
Ĺˊ6\QFKURQL]DWLRQDGMXVWDEOHZRUNLQJIUHTXHQF\UHDFKHV.+=
ĺˊ(QGXUH9KLJKYROWDJHVWDUWXSYROWDJH
ĻˊTwo levels over current protection
ljBNJStandby IC
Using VIPER22 power supply standby controlling IC of SANTE company, input voltage range:180v-264v,max
rising temperature 40ºCDŽ
Basic characteristics:
ķˊ5HDG\UHVRQDQFHPRGHFRQWUROOLQJUHGXFHWKHWXUQRQGLVVLSDWLRQRIWUDQVLVWRU
ĸˊ'\QDPLFDXWRVXSSO\SRZHU
Ĺˊ2YHUORDGSURWHFWLRQLQWREHOFKPRGHO


2ǃpower supply specification:
OUTPUT CROSS
TOLERANCE OUTPUT CURRENT
VOLTAGE REGULATION

(ACCURACY) 10%~90% LOAD MIN MAX


+24Vdc
Œ5.0% Œ5.0% 0.5A 14A

(ACCURACY) 10%~90% LOAD MIN MAX


+18Vdc
-10.0%~5.0% Œ5.0% 0.0A 2.0A

(ACCURACY) 10%~90% LOAD MIN MAX


+12Vdc
Œ5.0% Œ5.0% 0.5A 7.0A

(ACCURACY) 10%~90% LOAD MIN MAX


+5VSTB
Œ5.0% Œ5.0% 0.0A 2.0A















3ǃFLUFXLWDQDO\VLV

After filter circuit and bridge rectifier BD1 commuted output DC, from point1 to diode D9, connect primary coil pin1 of transformer T2, at the same time

through IC1 power regulated controlling , pin10 of T2 secondary coil output +5v standby voltage, under standby and turn on situation ,the circuit can work

normally.

ljANJstandby controlling

While PS-ON signal is low level, TV entering standby mode.

7KHRU\RIFRQWUROOLQJDVIROORZZKLOH3621VLJQDOLVORZOHYHOWKURXJK'656FRQQHFWWRWKHEDVHRI46WKH
ORZOHYHOPDNHV46FXWRIIVRWKDW,&FXWRII

Secondary of IC3 was high resistance, in cause of Q3 of VCC unit cut-off, it makes Q2 cut-off, VCC stop supply power, it meant that there was no power

voltage supply to the L6599, main power shut down.

ljBNJ{œ™•G–•GŠ–•›™–““•Ž
While entered turn on mode, PS-ON signal is high level (Y.5V estimate)U
7KHRU\RIFRQWUROOLQJLVWKDWZKLOH3621VLJQDOLVKLJKOHYHOWKURXJK'656WKHORZOHYHOFRQQHFWWRWKHEDVH
RI46PDNHVWKH46WXUQRQ,&WXUQRQ7KHVHFRQGDU\RIOLJKWFRXSOLQJLVORZUHVLVWDQFHDWWLWXGHWKH4LQ9&&FRQWURO
XQLWLVWXUQRQLWPDNHVWKH46WXUQRQ9&&VXSSO\SRZHUWKHYROWDJHRXWSXWVHQGWRWKH/SPDLQSRZHUVXSSO\XQLW

LVZRUNLQJ

ljCNJw™–›ŒŠ›GŠ–•›™–““•Ž

˄1˅vŒ™GŠœ™™Œ•›G—™–›ŒŠ›–•

From +18Vǃ+24Vǃ+12V output loop, separate sampling on point A, point B, point C, connect to negative voltage terminal of voltage comparator those are


Pin6 of ICS1B and pin5 of ICS1A and pin9 of ICS1C.

Under regular working conditions, due to the voltage of Pin 7 of ICS1B, Pin 5 of ICS1B,Pin9 of ICS1C higher than Pin6 of ICS1B, Pin4 of ICS1A and Pin8 of

ICS1C corresponding, so the output terminal of voltage comparator which whose Pin1 of ICS1B, pin2 of ICS1A, pin14 of ICS1C output low level.

Each low level through DS14,DS8,DS7 connected to emitter of QS4, QS4, QS1 and QS2 all cut-off ,the voltage of 1C didn’t change, the power supply circuit

was working in regular.

while output circuit in over current, due to voltage comparator’s pin7 of ICS1B, pin5 of ICS1A,pin9 of ICS1C output voltage less than voltage comparator’s

pin6 of ICS1B, pin4 of ICS1A, pin8 of ICS1C, so pin1 of voltage comparator’s ICS1B, pin2 of ICS1A, pin14 of ICS1C output high level.

Each level through DS14,DS8,DS7 connected to emitter of QS4,also through RS40 connected to Gate pole of QS5,it makes QS5 delay turn on, then QS4 turn

on, after that the high level send to base of QS2,so that QS2 turn on, collector of QS2 connected to base of QS1,makes the QS1 turn on, in cause of the voltage of

IC3 reduction. After that , it equal reduced the +5v voltage of IC3 ,IC3 stopped working, the secondary of IC3 was high resistance ,makes the Q3 of VCC cut-off,Q2

cut-off, VCC stopped supply power, it means no power to L6599,the main power shut down.

˄2˅vŒ™G–“›ˆŽŒG—™–›ŒŠ›–•a

+24Vǃ+18Vǃ+12V output loop separate connected to ZS1ǃZS2ǃZS3,through DS9.DS10ǃDS11 connected to RS18,


:KLOHWKH99ǃ9RXWSXWYROWDJHRYHUWKHUDWHYROWDJH

LWWKURXJK56FRQQHFWHGWKHEDVHRI46VRWKDW46DQG46WXUQRQVRWKDWWKHYROWDJHRI,&ZLOOEHUHGXFHG
$IWHUWKDWLWHTXDOUHGXFHGWKHYYROWDJHRI,&,&VWRSSHGZRUNLQJWKHVHFRQGDU\RI,&ZDVKLJKUHVLVWDQFHPDNHV
WKH4RI9&&FXWRII4FXWRII9&&VWRSSHGVXSSO\SRZHULWPHDQVQRSRZHUWR/WKHPDLQSRZHUVKXWGRZQ




Alignment Procedure



)DFWRU\0HQX

DŽEnter the Field Service mode(can use the IR and press the remote key “vol-”to “0’, press mute

remote key then press 9,7,3,5 remote key. Press right key to enter the sub-menu and press MENU

key to return the main-menu)) 

)DFWRU\0HQXGHILQLWLRQWKHOHIWGDWHLVGHIDXOWDIHUUHVHW

)DFWRU\ VRIWZDUHGDWH 079 

6\VWHP 3RZHU0RGH 2II5HPHPEHU 

%DODQFH )DFWRU\.H\ 2Q2II 

79*HR 7XQHU$*&  

1LFDP .H\%RDUG/RF 2II2Q 

N

0RQR /2*2 2II/RJR/RJR 

6RXQG 3DWWHUQ  EODQNVFUHHQ

ˉORZEULJKWQHVV˗ˉUHG˗ˉ

KLJKEULJKWQHVV˗ˉJUHHQ˗ˉ


EOXH˗ˉFLUFOHFKDQJHDERYH

SDWWHUQ

2WKHU %DFN/LJKW  

,QIR 5HVHW  

(Remember: Keep the lately Power on state; OFF: Standby after Power on)

)DFWRU\.H\˖ 6KRUWFXWNH\21WKH”%OXH” NH\LVWKHIDFWRU\0HQXNH\2IIGLVDEOHG 

.H\%RDUG/RFN2Q˖ 2QWKHNH\SDGERDUGLVORFNHGRQO\WKH5&8LVDYDLODEO\2II

GLVDEOHG 

/2*2/2*2˖/2*2˖2))

3DWWHUQ

7KHFKLSZLOOVHQGYDULRXVSDWWHUQVE\LWVHOIWKHPRGHFDQDXWRFKDQJHYDULRXV

SDWWHUQVLWLVXVHGIRUOLIHWHVWRQO\WKHNH\ERDUGEXWWRQKDVIXQFWLRQWKHUHPRYHFRQWURO

GRHVQÿWZRUN

%DFNOLJKW˄LWLVXVHGIRUWKHDGMXVWRIWKH/&'SDQHO˅

5HVHW˄it is used for going back the default ˅

)DFWRU\ VRIWZDUHGDWH 079 

6\VWHP 6RXUFH $99*$&03


%DODQFH :KLWH5 

79*HR :KLWH* 

1LFDP :KLWH% 

0RQR *UD\5 

6RXQG *UD\* 

2WKHU *UD\% 

,QIR 5*% 

&DOLEUDWH

6RXUFH(it is the source of white balance adjust that are TV,VGA,CMP)

:KLWH5*%5*%˄it is used for the adjust of white balance˅

*UD\5*%˖5*%˄it is used for the adjust of gray balance˅

5*%&DOLEUDWH˄it is used for the software adjust in VGA mode˅

)DFWRU\ VRIHZDUHGDWH 079 

6\VWHP &RORUV\VWHP 3$/

%DODQFH +326 

79*HR +6,=( 


1LFDP 9326 

0RQR 96,=( 

6RXQG 

2WKHU 

,QIR 

+9326˄it is used for the position of the horizontal and vertical.˅H/V

+96,=(˖˄it is used for the size of the horizontal and vertical.˅

)DFWRU\ VRIWZDUHGDWH 079 

6\VWHP 92/B  

%DODQFH 92/B  

79*HR 92/B  

1LFDP 92/B  

0RQR 92/B  

6RXQG 793UH  79adjust the level of volume

2WKHU $93UH  $9adjust the level of volume

,QIR 6:)UHT  '()$8/7

92/B˄it is used for the adjust the Volume curve˅TV/AV


79$93UH˄it is used for the adjust the level of volume˅

)DFWRU\ VRIWZDUHGDWH 079 

6\VWHP %OXH0XWH 21 21

%DODQFH &7, 0LGGOH '()$8/7

79*HR )OHVK7RQH 21 '()$8/7 :KHQ DGMXVW ZKLWH


EDODQFHVHW2))
1LFDP $GDSWLYH/XPDFRQWURO 21 '()$8/7 :KHQ DGMXVW ZKLWH
EDODQFHVHW2))
0RQR 'HLQWHUODFH0RGH $XWRPDWLF '()$8/7

6RXQG :KLWH3HDNOLPLWDWRU 21 '()$8/7

2WKHU 0''L(GJH3UHVHUYLQJ +LJK '()$8/7

,QIR 77;&RQWUDVW  '()$8/7

 %ODFN/HYHO  '()$8/7

 6HDPOHVV 2II '()$8/7

˄it is only used for design˅

)DFWRU\ VRIWZDUHGDWH 079 

6\VWHP 3URMHFW /&'07<


%DODQFH 9HUVLRQ 

79*HR 'DWH 

1LFDP 

0RQR 

6RXQG 

WKHU 

,QIR 

(It is the information of the product model, the software version and the date)

)DFWRU\ VRIWZDUHGDWH 079 

6\VWHP &RUUHVW7KUHV  'HIDXOW

%DODQFH 6\QF/RRS  'HIDXOW

79*HR (UURU7KUH  'HIDXOW

1LFDP 3DULW\(UURU7KUH  'HIDXOW

0RQR (YHU\1XP)UDPHV  'HIDXOW

6RXQG  

2WKHU  


,QIR  

)DFWRU\ VRIWZDUHGDWH 079 

6\VWHP +LJK'(9, 2II 

%DODQFH $00XWH 2Q 

79*HR $00XWH+LJK  

1LFDP $00XWH/RZ  

0RQR &DUULHU6KLIW 2II 

6RXQG 6DWXUDWLRQ0XWH 2II 

2WKHU )00XWH 2Q 

,QIR )00XWH+LJK  

)00XWH/RZ 
 

ǃ˄factory alignment process˅

It is the source of ADC channel adjust (need to adjust Ypb,pr and VGA state)

)LUVWWXUQRIIWKHĀFRPSOH[LRQDGMXVWāDQGĀG\QDPLFEULJKWQHVVDGMXVWāLQ

ĀRWKHUāRIIDFWRU\PHQXWXUQRIIĀEODFNOHYHOāLQĀSLFWXUHā RIXVHUPHQX

<SESUPRGHO


,QSXW 6'79L += ˈ VDWXUDWLRQ LV HLJKW JUDGHV JUD\ RI  SHUFHQW HQWHU
ĀEODQFHāPHQXVRXUFHVHWV+'79FKRRVH5*%&DOLEUDWHLWHPSUHVVĀHQWHUāERWWRQRQ
UHPRYHNH\XQLWZLOODGMXVWWKH$'&FKDQQHORI+'79VWDWHXQWLOWKHVFUHHQDSSHDU
ĀRNā

5HIHUHQFHLQVWUXPHQW3DWWHUQˈ7LPLQJˈRU%6*$7LPLQJˈ3DWWHUQRU
SDWWHUQ

9*$PRGHO

,QSXWh+=RI&RORUWHPSFURVVLQJVLJQDODQGFKHVVERDUGVLJQDO
:KLWHEDODQFHDGMXVWPHQW RQO\IRU9*$79+'79 

$IWHU$'&DGMXVWPHQWLWFDQSURFHVVHVZKLWHEDODQFHDGMXVWPHQW

)LUVWVHWVWKHSLFWXUHLQĀVWDQGDUGāVWDWH WXUQRIIWKHĀFRPSOH[LRQDGMXVWāDQG

ĀG\QDPLF EULJKWQHVV DGMXVWāLQ ĀRWKHUā RI IDFWRU\ PHQX WXUQ RII ĀZKLWH

OHYHOāDQGĀEODFNOHYHOāLQXVHUPHQX 

$GMXVW9*$ZKLWHEDODQFHDQGFRORUWHPSHUDWXUH

˅,Q9*$PRGHHQWHUĀEDODQFHāLWHPRIIDFWRU\PHQX

˅LQSXW JUD\VLJQDO8VLQJDFRORUDQDO\]HUWRPHDVXUHWKHFRORUFRRUGLQDWH

$ǃ,QKLJKEULJKWQHVVWKLUGJUD\DGMXVWWKH5*DLQǃ**DLQǃ%*DLQ YDOXHPDNHVWKHFRORU

WHPSHUDWXUHPHHWZLWK[ fˈ< fDQGEULJKWQHVVYDOXHPRUHWKDQQLW

%ǃ,QORZEULJKWQHVVWKLUGJUD\DGMXVWWKH5RIIVHWǃ*RIIVHWǃ%RIIVHWYDOXHPDNHV

WKHFRORUWHPSHUDWXUHPHHWZLWK[ fˈ< fDQGEULJKWQHVVYDOXHOHVVWKDQ

QLW


$GMXVW79$9ZKLWHEDODQFHDQGFRORUWHPSHUDWXUH

˅,Q$9PRGHOHQWHUĀEDODQFHāVXGPHQXRIIDFWRU\PHQX

 ˅ ,QSXW HLJKW JUDGHV JUD\ VLJQDO 8VLQJ D FRORU DQDO\]HU WR PHDVXUH WKH FRORU

FRRUGLQDWH

$ǃ,QKLJKEULJKWQHVVWKLUGJUD\DGMXVWWKH5*DLQǃ**DLQǃ%*DLQ YDOXHPDNHVWKHFRORU

WHPSHUDWXUHPHHWZLWK[ fˈ< fDQGEULJKWQHVVYDOXHPRUHWKDQQLW

%ǃ,QORZEULJKWQHVVWKLUGJUD\DGMXVWWKH5RIIVHWǃ*RIIVHWǃ%RIIVHW YDOXHPDNHV

WKHFRORUWHPSHUDWXUHPHHWZLWK[ fˈ< fDQGEULJKWQHVVYDOXHOHVVWKDQQLW

&ǃ5HSHDWDGMXVWWKHKLJKORZEULJKWQHVVXQWLOERWK$DQG%UHDFKWKHVSHFLILFDWLRQ

$GMXVW79$9ZKLWHEDODQFHDQGFRORUWHPSHUDWXUH

˅,Q+'79PRGHOHQWHUĀEDODQFHāVXGPHQXRIIDFWRU\PHQX

˅,QSXWL+=VLJQDOHLJKWJUDGHVJUD\VLJQDO8VLQJDFRORUDQDO\]HUWRPHDVXUH

WKHFRORUFRRUGLQDWH

$ǃ,QKLJKEULJKWQHVVWKLUGJUD\DGMXVWWKH5*DLQǃ**DLQǃ%*DLQYDOXHPDNHVWKHFRORU

WHPSHUDWXUHPHHWZLWK[ fˈ< fDQGEULJKWQHVVYDOXHPRUHWKDQQLW


%ǃ,QORZEULJKWQHVVWKLUGJUD\DGMXVWWKH5RIIVHWǃ*RIIVHWǃ%RIIVHW YDOXHPDNHVWKH

FRORUWHPSHUDWXUHPHHWZLWK[ fˈ< fDQGEULJKWQHVVYDOXHOHVVWKDQQLW

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$WWHQWLRQ  $IWHU $'& DQG ZKLWH EODQFH DGMXVWPHQW WXUQ RQ WKH ĀFRPSOH[LRQ
DGMXVWāDQGĀG\QDPLFEULJKWQHVVDGMXVWāLQĀRWKHUā RIIDFWRU\PHQX

WXUQRQĀEODFNOHYHOāLQXVHUPHQX 

ˊ XSGDWHWKH6: 

˄The SW can be updated on board and also update through the VGA portˈdo not need to open the

cabinet˅

(please install the MT8202 driver and Parallel driver first. Need to prepare a special
cable and R&D will supply a cable sample and the software drivers. )

>@(First time download on board)

˅ǃ(connect by cable [the tool and the cable] between the PC and the XPA5 on the board )

˅ǃ VXSSO\YWRWKHPDLQERDUGE\-3$2532:(521 

˅ǃ (open the MT8202 driver as below) 




˅ǃ(then select “Browse” open the attached file (MT02.bin) in the location. In order to ensure it

can be better updated you can set the “baud rate” be “115200”.)


ǃ˄select “Upgrade”, if the rate of progress get to 100%,the update is finished.˅





ǃ˄after finished update,power off the TV,then power onˈat the first time that you power on

the TV set ,the display will be later than normal˅.

>@ update through the VGA port˅

˅DŽ(connect by cable [the tool and the cable] between the PC and the VGA port ) 

˅DŽ(power on the set, press the key of the factory remote controller 

After that repeat the process 3,4,5,6, above ,please note when doing the
process 6, must erase flash first: Press “ERASE FLASH”)

ˊ(The DDC data should be program before SMT, and it also can be update 

through P2˄VGA˅when finished SMT . )

ˊ (After download the SW, it need about 30 sec to initialize the EEprom, so must write the data

to U2 before SMT )





Block Diagram

Power board signal flow

commutate
EMC isolating
AC IN Bridge PFC control PWM filter of output Main power supply
Filter transformer
rectifier circuit circuit voltage +24V/+12V
circuit

Control IC L6563ǃ
L6599 PS-ON
Over current and over
insulated by
voltage protection ˈ
photo-coupler
VCC control cell standby control circuit

Standby circuit isolati


ng commutate Standby voltage
transfo filter of +5VSB
rmer output
Control IC
VIPER22


Digital board block diagram

TCL TUNER KEY IR

(SDRAM)
U7
/SLG 3
TU_MON

REMOTE
KEY
O CVBS

SIF
SCART1

SDA\SCL
Q2\25
Audio
2N3904
output
SCART1 TU_CVBS0 SDA\SCL U2 M24C32
PIN20 (user data)
Video Q1 2N3904
output
U7 29AL016M90TFI02
(FLASH)
RGB YUV/RGB
SCART1 U14 LED indicator light
JP9 PIN4
RGB input PI5V330

DTV D200 TESTP2


AV_CVBS SCART2
Q7 2N3904 PIN20
Video output
CVBS
SCART1\2(AV1\AV2)ǃAV3
AR/AL
Video input AVR/L_OUT
U18 SCART2
YPbPr RC4558 Audio output
Y cb cr input.

Audio L\R
M24C08
U10(DDC)

AT24C08
U9(HDCP)

8
YDA142
U001
signal

MT8202
HDMI
᥹ষ

DDC
341A
TMDS
TI

MT8293E
U8(Receiver)

Headphone R/L
AT24C02
U11(DDC)

DDC
VGA
᥹ষ

LVDS
HV+RGB LCD Panel

SCART1 Audio input 24V/(PANNEL)


GND
U2(SCART)4
SCART2 Audio input
052
Audio switch Standby control POWER
AV3 Audio input SB-5V(JP12A)
MODEL
12V/AMP12V
HD\VGA Audio input U13(4052) GND(JP12)
Audio switch

U27(DC-DC) 9583
U12 (A/D)
CS5340 Audio +5V


A B C D E

MT8202M1V2 MT8202E (PBGA388) CRT/LCDTV DEMO/VERFICATION BOARD 4 LAYERS


+5V
+5V [1,2,4,6,8,9,10,11,12,13,14]
+12V
+12V [1,2,9,10,11,12,14]
"GND Need Very Strong"
GNDA
GNDA [3,4,8,9,11,12,14]
Rev History P# Date
2005/09/30 JP7
TCL_V1.0 Modified
1. INDEX / POWER / RESET 2006/05/25
TCL_V1.4 Modified 1
4 2006/08/17 2 4
2. LDO TCL_V1.5 Modified
DIP12/WH/P2.0/R
3. MT8202E PBGA388 JP12A

4. MT8202 ANALOG DECOUPLING SB+5V SB+5V 1


GNDP 2
C0402/SMD C70 ON/OFF 3
0.1uF
5. MT8202 DIGITAL DECOUPLING GNDP
3x1 W/HOUSING R.A
6. DDR MEMORY & FLASH +12V DIP12/WH/P2.0/R

7. HDMI INPUT -SiI9011 / MT8293


C196
470uF/16V L58 FB
8. CCIR656 / MT5351 INTERFACE JP12
AMP_GND AMP_GND 1 1
CB202 CB201 L59 FB
9. VGA IN & PC AUDIO IN R504 R505 U27 CE194 AMP_+12V
0.1U 0.1uF 2 2
6.5K 10 470uF/25V AMP_+12V
R526 L60 FB C71 +12V 3
10. CS5340 ADC & AV BOARD I/F +12V 3
1K 1 14 C0402/SMD 0.1uF
VCC GND CB203 GNDP 4 4
CB196 C12 AMP_GND
11. AUDIO / VIDEO IN CIRCUIT 0.1U 0.1 D30 GNDP 0.1uF SB+5V
2 13 CB205 LL4148 C0402/SMD
R507 PWRGD SS/SHUT 0.1U GNDP
12. CS4334 / WM8766(8768) ADAC 2.2K C225
R506 5.1K
3 12 NC
13. LVDS / CRT / TTL OUT OVP VREF
R508 1K R519
14. BACK LIGHT / KEYPAD 2.2K
3 4 11 Sensitive R57 3
OCSET SENSE 10K ON/OFF
2

R509 8202UP3_0 R518 10K


15. CARD I/F & DEBUG PORT & GPIO LIST 270 8202UP3_0 1 Q24
5 PHASE BSTH 10 2N3904
C230
SOT23/SMD
3

OPEN
R510
6 9 680
HOLE/GND HOLE/GND DRVH BSTL R511
H8 H7 HOLE/GND CB204 OPEN GNDP
H4 CB4 D31 0.1UF C226 L69
9 2 9 2 U29
9 2 9 2 NC STPS2L40U R512 1.0uF/16V BCK-4235 ( 10UH )
8 8 3 3 8 8 3 3 9 9 2 2 7 PGND DRVL 8 1 S1 D1 8
7 4 7 4 8 3 C0402/SMD GNDP 2.2 2 7
7 4 7 4 8 3 G1 D1 GNDP
6 6 5 5 6 6 5 5 7 7 4 4 3 S2 D2 6
6 5 2.2 4 5

1
1
6 5 G2 D2

1
2

1
GNDP R513 PHKD13N03LT(N-MOS) D32 C207

1
1
SC2602 STPS2L40U NC

1
MOS fET and T1 in the same side R514 CE195 CB207 CB206 +5V
1/2 Iout NC 1000uF/10V 0.1U 0.1U L61 FB

HOLE/GND >=15mil
H1 HOLE/GND L62 FB
H3 +5V
9 9 2 2
8 3 9 2 >=15mil
8 3 9 2 HOLE/GND L63 FB
7 7 4 4 8 8 3 3 H6
6 5 7 4
GNDP
6 5 7 4
6 5 9 2

1
6 5 9 2 C36
8 3

1
7
8 3
4
Vin-R1*200uA=Vin-Rds(on)*Ilimite 0.1uF
7 4

1
6 5 C0402/SMD
6 5 GNDP

1
1
L64 FB
R1=Rds(on)max*Ilimite/200uA = 0.023 * 2A *1.25 /200uA = 184

1
2 R1=Rds(on)max*Ilimite/200uA = 0.023 * 4A *1.25/200uA = 368 2
HOLE/GND HOLE/GND L65 FB
H2 H5
9 2 9 2 SC1104 BOM
9 2 9 2 L66 FB SC1102 BOM
8 3 8 3 D1 LL4148 *1
8 3 8 3
7 4 7 4 R1 184(2A)/368(5A) *1 D2 MBRA130L *1
7 4 7 4 GNDP
6 6 5 5 6 6 5 5 D1 MBRA130 *1 Q1A,Q2B STP40NE *2
L67 FB
D2 MBR0520 *1

1
1
C1 10uF/16V *1
D3 MBRD1035 *1 C2,3,4 270uF/16V *3

1
1
L68 FB Q1A,Q2B STP40NE *2 C6 ? *1
C1 10uF/16V *1 C8 1uF *1
C2,3,4 270uF/16V *3 C9 ? *1
GND
C5 0.1uF *1 C15 ? *1
C7,8 1uF *2 C16 ? *1
C10,11,12,13,14 180uF/6V *5 C10,11,12,13,14 180uF/6V *5
GNDA T1 4uH *1 T1 4uH *1
GND R2 10 0805 *1 R6 508 0603 *1
R3,5 1K 0603 *2 R7 127 0603 *1
R4 2K 0603 *1 R8 ? *1
R6 475 0603 *1 R9 2.2 0603 *1
AUIO IN/OUT GND R7 127 0603 *1 R10 2.2 0603 *1
DIGITAL GND R9 3.9 0603 *1 R11 ? *1
R10 2.2 0603 *1 R12 ? *1
U1 SC1102 *1 R13 ? *1
5VSB U2 SC1104 *1

Remark:
Option RESET# CIRCUIT The components which did not marked the value in

3
+12V
CB2 U1 the circuit are all using in SC1104 solution.

VCC
0.1uF LM809M3-4.38V
SOT-23/SMD R324

GND
RESET
1 4.38V Threshold 10K/NC + CE4 1
C84 4.7uF/10v/NC

1
2
1u
R9 C0805/SMD/NC
URST#

2
R10
1k 1
R11 V2
SW1
Q19 4.7K/NC

2=4
100k 2 4 2N3904
1 3 SOT23/SMD/NC D1 R8

1=3
1N4148/SMD/NC 47k/NC TTE SHENZHEN R&D CENTER
SW4P/DIP/FLAT/NC Title
MT8202

URST# URST# [1,3,6,9] Size Document Number Rev


C 2006-5-26 YWX

Date: Wednesday, December 27, 2006 Sheet 1 of 14


A B C  D E
A B C D E

DV33B
4 DV33B [7,8,9,12,13,14] 4

LVDS_GND
LVDS_GND [3,4,14]
SB+5V
VFE_GND
VFE_GND [3,4,10,11]
SB33B
L4 FB VFE_GND1
VFE_GND1 [2,4,8,9,10,12]
Power ON alive source +12V
+12V [1,2,9,10,11,12,14]
5VSB +5V
+5V [1,2,4,6,8,9,10,11,12,13,14]
+ CE7 CB8 FB FB2
4.7uF / 0805 0.1uF DV18A
L2
FB U20 AZ1117/adj SB33 SB33A U21 AZ1117/adj SB18A
L6 FB L5 FB
5VSB 3 2 SB33A 3 2 SB18 SB18A
IN OUT IN OUT
+ CE1 C167 C101 R99 C168

ADJ/GND
ADJ/GND
100uF/16v 100Uf/10v 4.7uF/10v 270 1% 100Uf/10v
CB7 C0805/SMD CE8 + + CE9

1
1
0.1uF CB9 4.7uF / 0805 CB10
SOT223/SMD 4.7uF / 0805 0.1uF SOT223/SMD 0.1uF

ASB33A R102
150 1% ASB18A
Q6 L7 FB
+12V 2 ASB33A L8 FB
S 1.25x(1+150/270)=1.944V ASB18A
D 3
R51 10K + CE10 Modified by Bin_wang.2006/01/20
1 4.7uF / 0805 + CE11
G 4.7uF / 0805
CB3 R38
3 0.1uF 100K SI2307DS LVDS_GND 3
C0603/SMD SOT-23/SMD LVDS_GND

೼STANBY⢊ᗕϟˈ⬅SB+5㒭DV33AǃDV18AǃAV18AǃAV33Aᦤկ⬉⑤ ADCV33A AV33A

U22 AZ1117/adj U23 AZ1117/adj ADCV18A AV18A


FB18 FB19
3 2 ADCV33A 3 2 ADCV18A
IN OUT IN OUT
0 0

ADJ/GND
ADJ/GND
CB11 + CE13

1
1
0.1uF + CE14 CB13 100Uf/10v
SOT223/SMD 100uF/16v 0.1uF SOT223/SMD

VFE_GND
VFE_GND

VFE_GND VFE_GND

1.25x(1+180/110)=3.3V
+5V DV33A
U30 AZ1117/adj U24 AZ1117/adj/NC
DV18A
3 2 3 2 DV18A
2 IN OUT IN OUT 2

CB15 R88

ADJ/GND
+ CE103 0.1uF + CE3 ADJ/GND 270 1%
100uF/16v 100uF/16v CE15 + CE17

1
1

4.7uF/10v CB17 100Uf/10v CB18


SOT223/SMD C0805/SMD 0.1uF SOT223/SMD 0.1uF

R89
150 1%

ADCV33A
1.25x(1+150/270)=1.944V
Modified by Bin_wang.2006/01/20

DV33B U37 AZ1117/adj DACVDD


+5V U31 AZ1117/adj L42
AV33A 3 2 DACVDD
IN OUT
3 IN OUT 2 FB ADJ/GND

ADJ/GND
+ CE108 R325 + CE109 CB187
1

+ CE104 CB23 + CE21 CB24 100Uf/10v CB197 270 1%

1
100uF/16v 0.1uF 100Uf/10v 0.1uF SOT223/SMD 100Uf/10v 0.1uF
SOT223/SMD 0.1uF C0603/SMD

LVDS_GND

1 R326 1
1.25x(1+180/110)=3.3V 150 1% 1.25x(1+64.9/110)=1.99V
LVDS_GND

TTE SHENZHEN R&D CENTER


Title
MT8202

Size Document Number Rev


C 2006-5-26 YWX

Date: Wednesday, December 27, 2006 Sheet 2 of 14


A B C  D E
A B C D E
SB33B
R34 SB33B
TP23
TP2 TP3 TP4 TP5 TP94 TP95 TP6 TP7 SCART_FB
SCART_FB [11]
100k R13
X1 Modified by Bin_wang.2006/01/20 20K
CCIR_VCLK
U2 CCIR_VCLK [9]
XTALI XTALO

GND
GND
CB5 1 8 CCIR_V[0..7] CCIR_V[0..7] [9]
27MHz NC VCC

SC0
SC1
PB1-
Y1+
PB0-
PB0+
SYSROMWP Q4

PB1+
Y1-
SOY1
Y0-
Y0+

SY0
SY1
PR1-
PR0-
DV18A

PR1+
PR0+
DV33A
2 NC WP 7

MPX2
MPX1
SOY0
GREEN-
GREEN+
0.1uF SCL 2N3904 27MHZ

REFP
REFN
CVBS1
CVBS0
CVBS3
CVBS2
RED-
RED+
VGASOG
BLUE-
BLUE+
3 NC SCL 6 27MHZ [8]

LVDS_GND
VFE_GND
VFE_GND

VFE_GND1
VFE_GND1

TESTN3
AUDIO_GND
AVICM
AVDD_VAD1

ACENT
ADACVDD
TESTN2
AADCVSS
AADCVDD
AVDD_VFE0
TESTN1
AVDD_VFE1
VGAVSYNC#
VGAHSYNC#
SDA0
CCIR_V7
CCIR_V6
CCIR_V3

CCIR_V5
CCIR_V2

CCIR_V4
CCIR_V1
CCIR_V0
SDA1
HDMILRCK
HDMIBCLK
HDMIMCLK
AADCVSS
VFE_GND
VFE_GND
C1 C2 SDA SOT23/SMD

TESTP3
AL
AR
TESTP2
AVDD_VAD0
TESTP1
SCART_FB
SCL0
CCIR_VCLK
VI23
VI22
VI19

SCL1
HDMISD3
HDMISD2
HDMISD1
HDMISD0
VI21
VI20
VI18
VI17
VFE_GND1
VFE_GND1
VFE_GND1
VFE_GND1
4 5

2
V2 GND SDA
16pF 16pF 10K HDMIMCLK
HDMIMCLK [8,9]
1 R14 GPIO4 HDMIBCLK
EEPROM 24C32 HDMIBCLK [8,9]
LVDS_GND HDMILRCK

B23
D22
C23
D23
A25
A26
A24
B24
C24
B25
C25
D24
C26
B26
E24
F23
F24
G24
G23
D26
D25
E25
E26
J23
H23
F25
F26
G25
G26
L23
J26
J25
K26
K25
L26
L25
L24
M26
M25
N26
N25
P26
P25
P24
M24
P23
R24
R23
R26
R25
T26
T25
T24
U26
U25
N24
V25
V26
U24
U23
V23
V24
W24
W25
W26
R16
Y23
Y24
Y25
Y26
W23
T16
AB24
AB23
AA24
AA23
AA26
AA25
AC24
AB25
AB26
AC26
AC25
AD26
AC23
AD25
AC20
AE26
AE25
AF26
E23
H24
H25
H26
K23
M23
N23
SOP8/SMD HDMILRCK [8,9]
U3 R15

3
10K/NC HDMISD0
HDMISD0 [8,9]

AF
BP

RP
BN

RN
GP
GN

SIF
AUDIO_GND HDMISD1

TP3
TP2
TP1

TN3
TN2
SY0
SY1
Y1P
Y0P
TN1

SC0
SC1
Y1N
Y0N
VI23
VI22
VI21
VI20
VI19
VI18
VI17
SYSTEM EEPROM

SOG
AUDIO_GND [1,4,10,11,12,13] HDMISD1 [8,9]

SCL0
SCL1

PB1P
PB0P

PR1P
PB1N
PR0P
PB0N
SDA0
SDA1

REFP
PR1N
SOY1
PR0N
SOY0

REFN
AADCVSS HDMISD2

AVICM
CVBS0
CVBS1
CVBS2
CVBS3
4 AADCVSS [1,4,8,9,10,11,12,14] HDMISD2 [8,9] 4

VSYNC
HSYNC
DVSS18
DVSS33
LVDS_GND HDMISD3

DVDD18
DVDD33

PLLVSS1
LVDS_GND [2,4,14] HDMISD3 [8,9]

VFE_GND
VFE_GND

ADACVSS
AADCVSS
AADCVSS

ADACVDD
AADCVDD
VFE_GND

VFE_GND1
VFE_GND1
VFE_GND1
VFE_GND1
VFE_GND [2,4,8,9,10,11,12,14]

AVSS_VFE0
AVSS_VFE1

AVSS_VAD0
AVDD_VFE0
AVSS_VAD1
AVDD_VFE1

AVDD_VAD0
AVDD_VAD1
PLLVDD1

AL/AOSDAT0
C22 J24

AR/AOSDAT1
FAST_BLANK
PLLVDD1 NC BALL

CCIR_V7/GPIO
CCIR_V6/GPIO
CCIR_V5/GPIO
CCIR_V4/GPIO
CCIR_V3/GPIO
CCIR_V2/GPIO
CCIR_V1/GPIO
CCIR_V0/GPIO
VFE_GND1 LVDS_GND VI[0..23]

HDMISD3/GPIO
HDMISD2/GPIO
HDMISD1/GPIO
HDMISD0/GPIO
VFE_GND1 [2,4,8,9,10,12] B22 PLLVSS2 NC BALL K24 VI[0..23] [8,9]

HDMIBCLK/GPIO
HDMILRCK/GPIO
HDMIMCLK/GPIO

ACENT/AOSDAT2
PLLVDD2

CCIR_VCLK/GPIO
C21 PLLVDD2 NC BALL T23
AVDD_VAD1 LVDS_GND A23 HDMIODCK
AVDD_VAD1 [4] PLLVSS3 HDMIODCK [8,9]
PLLVDD3 B21 HDMIDE
PLLVDD3 HDMIDE [8,9]
AVDD_VFE1 XTALVDD A22 AF25 VI16 HDMIHSYNC
AVDD_VFE1 [4] XTALVDD VI16 HDMIHSYNC [8,9]
XTALO A20 AD24 VI15 HDMIVSYNC
XTALO VI15 HDMIVSYNC [8,9]
XTALI A21 AE24 VI14 HDMICEN
XTALI VI14 HDMICEN [8]
PLLVDD1 LVDS_GND A19 AF24 VI13
PLLVDD1 [4] XTALVSS VI13 SB33B
LVDS_GND D21 AD23 VI12 DE_SOG
ADCVSS VI12 DE_SOG [8]
PLLVDD2 ADC_IN4 D20 AE23 VI11
PLLVDD2 [4] TP10 ADIN4/GPIO VI11
TP11 ADC_IN3 C20 T15 GND A_DQS[0..3] A_DQS[0..3] [7]
PLLVDD3 ADC_IN2 ADIN3/GPIO DVSS18 VI10 A_RA[0..11]
PLLVDD3 [4] TP12 B20 ADIN2/GPIO VI10 AF23 A_RA[0..11] [7]
TP13 ADC_IN1 C19 R15 GND A_BA[0..1] A_BA[0..1] [7]
XTALVDD ADC_IN0 ADIN1/GPIO DVSS33I VI9 R35 R36 A_DQM[0..1]
XTALVDD [4] TP14 B19 ADIN0/GPIO VI9 AD22 A_DQM[0..1] [7]
ADCVDD D18 AE22 VI8 10K 10K JP1 A_DQ[0..31] A_DQ[0..31] [7]
VPLLVDD1 PWM2VREF ADCVDD VI8 VI7 A_CLK
VPLLVDD1 [4] C18 PWM2VREF VI7 AF22 A_CLK [7]
B18 AC21 VI6 1 A_CLK# A_CLK# [7]
DACVDDA TP79 SVM VI6 VI5 RXD A_CKE
DACVDDA [4] A18 B VI5 AD21 2 A_CKE [7]
LVDS_GND D19 AE21 VI4 TXD 3 A_CS# A_CS# [7]
DACVDDB DACVSSA VI4 HDMIODCK A_RAS#
DACVDDB [4] A17 G VCLK_DVI AE19 4 A_RAS# [7]
TP80 DACVDDA C16 AF21 VI3 A_CAS# A_CAS# [7]
DACVDDC LVDS_GND DACVDDA VI3 VI2 A_WE#
DACVDDC [4] C17 DACVSSB VI2 AD20 A_WE# [7]
DACVDDB D16 AC22 DV18A RS-232 4x1 W/HOUSING
AVDD_VFE0 TP81 DACVDDB DVDD18 VI1 DIP4/W/H/P2.0 VREF
AVDD_VFE0 [4] B17 R VI1 AE20 VREF [7]
LVDS_GND D17 AF20 VI0 DV25A
DACVSSC VI0 DV25A [7]
AVDD_VAD0 DACFS A16 AC19 HDMIDE
AVDD_VAD0 [4] FS DE_DVI
TP31 DACVREF B16 AD19 HDMIHSYNC SB33B SDV25A
VREF HSYNC_DVI SDV25A [7]
AADCVDD DACVDDC C15 AF19 HDMIVSYNC
AADCVDD [4] DACVDDC VSYNC_DVI
TESTP4 A15 AF18 HDMICEN IR
TP4 CEN_DVI/GPIO IR [3,10,13]
ADACVDD TESTN4 B15 AE18 DE_SOG
ADACVDD [4] TN4 DE_SOG/GPIO
VPLLVDD1 D15 AD18 27MHZ R26
ADCVDD LVDS_GND VPLLVDD1 OUT_27MHZ/GPIO PWM1 4.7K INT0#
ADCVDD [4] D14 VPLLVSS GPIO/PWM1 AC18 INT0# [6,8]
VPLLVDD2 A13 AD17 PWM0
VPLLVDD2 LVDDA VPLLVDD2 GPIO/PWM0 DV33A
VPLLVDD2 [4] D13 LVDDA DVDD33I AC17
3 AP7 C12 AE17 A_DQ31 INT0# 3
LVDDA AN7 A7P DQ31 A_DQ30
LVDDA [4] D12 A7N DQ30 AF17
CLK2+ C11 AC16 A_DQ29 IOCE#
CK2P DQ29 IOCE# [6]
LVDDB CLK2- D11 AC15 SDV25A IOWR#
LVDDB [4] CK2N DVDD25OPT IOWR# [6]
LVDS_GND C14 AD16 A_DQ28 F_OE# F_OE# [7]
LVDDC AP6 LVSSA DQ28 A_DQ27
LVDDC [4] C10 A6P DQ27 AE16
AN6 D10 T14 GND F_A[8..21] F_A[8..21] [6,7]
AP5 A6N DVSS25 A_DQ26
C9 A5P DQ26 AF16
TESTP2 AN5 D9 AE15 A_DQ25 F_D[0..7] F_D[0..7] [6,7]
TESTP2 [11] A5N DQ25
LVDDB C13 AD14 A_DQ24
TESTP3 AP4 LVDDB DQ24 A_DQS3 IOA[0..7] IOA[0..7] [3,6]
TESTP3 [4] C8 A4P DQS3 AF15
TESTN3 AN4 D8 AD15 SDV25A
TESTN3 [4] A4N DVDD25OPT
AP3 A12 AE14 A_DQM1 URST# URST# [1,6,9,15]
TESTP4 AN3 A3P DQM1 GND
TESTP4 [4] B12 A3N DVSS18 R14
TESTN4 LVDS_GND B14 AF14 A_DQS2
TESTN4 [4] LVSSB DQS2
CLK1+ A11 AF13 A_DQ23
CLK1- CK1P DQ23 A_DQ22
ADC_IN0
ADC_IN0 [11]
AP2
AN2
B11
A10
B10
CK1N
A2P
A2N
MT8202 DQ22
DVSS25
DQ21
AE13
T13
AD13 A_DQ21
GND AL
AR
AL
AR
[13]
[13]
SCL
SCL [1,6,11]
ADC_IN1 LVDDC B13 AC13 A_DQ20 ACENT SDA
ADC_IN1 [11] LVDDC DQ20 ACENT SDA [1,6,11]
AP1 A9 AC9 DV18A
ADC_IN2 AN1 A1P DVDD18 A_DQ19 PWM0
ADC_IN2 [11,15] B9 A1N DQ19 AF12 PWM0 [15]
AP0 A8 AC14 SDV25A MPX1 PWM1
[12] A0P DVDD25OPT MPX1 [12] PWM1 [15]
ADC_IN3 AN0 B8 AE12 A_DQ18 MPX2
ADC_IN3 A0N DQ18 MPX2 [12]
ADC_IN4 LVDS_GND A14 AD12 A_DQ17
ADC_IN4 [12] LVSSC DQ17
SB18A K4 AC12 A_DQ16
TP99 DVDD18A DQ16 A_RA4
D7 AF11

AVICM
AVICM [4]
TP85
SB33A
8202UP3_5
8202UP3_1
D5
C7
B7
GPIO
DVDD33A
UP3_5
SOCKET RA4
RA5
DVSS25
AE11
R13
AD11
A_RA5

A_RA6
GND
CVBS0
CVBS1
CVBS2
CVBS0
CVBS1
CVBS2
[12]
[12]
[12]
IOSCL
IOSDA
IOSCL
IOSDA
[6]
[6]
PWM2VREF 8202UP3_0 UP3_1 RA6 A_RA7 CVBS3 CVBS3 [12]
PWM2VREF [4] A7 UP3_0 RA7 AC11
TP100 VSYNC B6 AF10 A_RA8 SCL0 SCL0 [11,16]
DACFS TP101 HSYNC VSYNCO RA8 GND SY0 SY0 [12] SDA0 SDA0 [9,16]
DACFS [4] A6 HSYNCO DVSS18 T12
TP102 C6 C6 AE10 A_RA9 SC0 SC0 [12] SCL1 SCL1 [9,16]
REFP TP103 GPIO RA9 A_RA11 SDA1 SDA1 [9,16]
REFP [4] D6 GPIO RA11 AD10
REFN F_A17 C3 AC10 A_CKE GPIO5
REFN [4] A17 CKE GPIO5
SY1 IOA0 C2 AC7 DV25A GPIO2
SY1 [10,14] IOA0 DVDD25_CLK GPIO2 [14]
SC1 F_D7 C4 AE9 A_CLK GPIO3
2 SC1 [10,14] AD7 RCLK GPIO3 [13] 2
GPIO12 GND L12 AF9 A_CLK#
GPIO12 [3,9] DVSS18 RCLKB
C6 F_D6 B1 T11 GND RED+ RED+ [10] FCLK
C6 [3,12] AD6 DVSS25 FCLK [11]
F_D5 B2 AD9 A_RA3 RED- RED- [10] FCMD
AD5 RA3 FCMD [11]
F_D4 A2 AF8 A_RA2 GREEN+ GREEN+ [10] FDAT
AD4 RA2 FDAT [11]
GND L11 AE8 A_RA1 GREEN- GREEN- [10] GPIO10
DVSS33 RA1 GPIO10 [11]
F_D3 B3 AD8 A_RA0 BLUE+ BLUE+ [10]
F_D2 AD3 RA0 A_RA10 BLUE- BLUE- [10] 8202UP3_1
A3 AD2 RA10 AF7 8202UP3_1 [1]
F_D1 B4 AD6 DV25A GPIO13
AD1 DVDD25 GPIO13
F_D0 A4 AE7 A_BA1 VGASOG VGASOG [10] GPIO14
AD0 BA1 GPIO14
F_OE# B5 AC8 DV18A GPIO15
IOOE# DVDD18 GPIO15
IOCE# A5 AD7 A_BA0 VGAHSYNC# VGAHSYNC# [10] GPIO16
IOCS# BA0 GPIO16
IOA1 C1 AF6 A_CS# VGAVSYNC# VGAVSYNC# [10] GPIO17
IOA1 RCS# GPIO17 [8]
SB18A K3 AE6 A_RAS# GPIO18
DVDD18A RAS# GPIO18 [8]
F_A16 D2 R11 GND Y0+ GPIO6
A16 DVSS25 Y0+ [12] GPIO6
F_A15 D1 AF5 A_CAS# Y0-
HIGHA7 CAS# Y0- [12]
F_A14 E4 AE5 A_WE# PB0+
HIGHA6 RWE# PB0+ [12]
F_A13 E3 AF4 A_DQ15 PB0-
HIGHA5 DQ15 PB0- [12]
AE4 A_DQ14 PR0+ TXD TXD [9]
DQ14 PR0+ [12]
A1 AD4 A_DQ13 PR0- RXD RXD [9]
NC BALL DQ13 PR0- [12]
C5 AC6 DV25A SOY0
NC BALL DVDD25 SOY0 [12]
J3 AOMCLK AOMCLK [11,13]
NC BALL GND Y1+ AOBCLK AOBCLK [11,13]
J4 NC BALL DGND/BALL P16 Y1+ [12]
N2 P15 GND Y1- AOLRCK AOLRCK [11,13]
NC BALL DGND/BALL Y1- [12]
AA3 P14 GND PB1+
NC BALL DGND/BALL PB1+ [12]
P13 GND PB1- ADIN ADIN [11,16]
DGND/BALL PB1- [12]
N16 GND PR1+
DGND/BALL PR1+ [12]
N15 GND PR1-
DGND/BALL PR1- [12]
N14 GND SOY1 AOSDATA1 AOSDATA1 [13]
DGND/BALL SOY1 [12]
VFE_GND1 N13 GND
VFE_GND1 [2,4,8,9,10,12] DGND/BALL
M16 GND
DGND/BALL USB_IR_EN

HIGHA4
HIGHA3
HIGHA2
HIGHA1
IOA20
IOA21
IOWR#
IOA19
DVSS18
IOA18
HIGHA0
IOA7
IOA6
IOA5
IOA4
DVDD33A
IOA3
IOA2
IOALE
WR#
RD#
INT0
PRST#
UP3_4
IR
ICE
DVDD18
RXD
TXD
AOMCLK
AOLRCK
AOBCK
LIN
DVSS18
AOSDATA0/GPIO
AOSDATA1/GPIO
AOSDATA2/GPIO
AOSDATA3/GPIO
DVSS33
GPIO0/AOSDATA4
GPIO1/AOSDATA5
GPIO2
GPIO3
FCICLK/GPIO
FCICMD/GPIO
FCIDAT/GPIO
GPIO4
GPIO5/TXD
GPIO6/RXD
DVDD18
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
SDA
SCL
DVDD33
DQ0
DQ1
DQ2
DVDD25
DQ3
DQ4
DQ5
DQ6
DVSS25
DQ7
DQS0
DQM0
DVDD25
DQS1
DQ8
DVSS18
RVREF
DQ9
DVSS25
DQ10
DQ11
DVSS18
DQ12
DGND/BALL
DGND/BALL
DGND/BALL
DGND/BALL
DGND/BALL
DGND/BALL
DGND/BALL

USB_IR_EN [3,10]

E2
E1
F4
F3
F2
F1
J2
G4
M12
G3
G2
H1
H2
H3
G1
H4
D3
D4
J1
K1
K2
L1
L2
L3
L4
M2
U4
M3
M4
M1
N3
N1
N4
M11
P1
P2
P3
P4
N12
R1
R2
R3
R4
T1
T2
T3
T4
U1
U2
U3
V1
V2
V3
V4
W1
W2
W3
W4
Y1
Y2
Y3
Y4
AA1
AA2
AA4
AB1
AB2
AB3
AC5
AB4
AC1
AC2
AC3
N11
AC4
AD1
AD2
AD5
AE1
AF1
P12
AD3
AE2
P11
AF2
AE3
R12
AF3
L13
L14
L15
L16
M13
M14
M15

AP[0..7] AP[0..7] [14] GPIO11


GPIO11 [3,8]
AOSDATA3
AOSDATA3 [3,11]
AN[0..7] AN[0..7] [14] AOMCLK-GPIO9
AOMCLK-GPIO9[3,11]
BGA388/SOCKET AOBCK-GPIO8
AOBCK-GPIO8 [3,11]
1 MT8202 CLK1+ CLK1+ [14] LRCK-GPIO7 1
LRCK-GPIO7 [3,11]
GPIO16

8202UP3_0
GPIO14

CLK1- CLK1- [14]


8202UP3_0

F_A9

F_A12
F_A11
F_A10
F_A8
UWR#
INT0#
IR
ICE
UTXD
GPIO2
GPIO3
FCLK
FCMD
GPIO4
GPIO5
GPIO6
LRCK-GPIO7
IOSCL

CLK2+ CLK2+ [14]

F_A20
F_A21
IOWR#
F_A19
F_A18
IOA7
IOA6
IOA5
IOA4
IOA3
IOA2
URST#
URXD
FDAT
GPIO10
GPIO11
GPIO12
GPIO13
GPIO15
GPIO17
GPIO18
IOSDA

SB33A
8202UP3_4
AOLRCK
AOBCK-GPIO8
A_DQ0
A_DQ1
A_DQ2
A_DQ3
A_DQ4
A_DQ5
A_DQ6
A_DQ7
A_DQS0
A_DQM0
A_DQS1
A_DQ8
A_DQ9

CLK2- CLK2- [14]

GND
DV18A
AOMCLK
AOBCLK
ADIN
GND
AOSDATA1
GND
DV18A
DV33A
DV25A
GND
DV25A
GND
VREF
GND
A_DQ10
A_DQ11
GND
A_DQ12
GND
GND
GND
GND
GND
GND
GND

USB_IR_EN
AOMCLK-GPIO9

AOSDATA3
8202UP3_5 TP104 TP83 TP90
8202UP3_5 8202UP3_4 TP88 TP168
8202UP3_4 TP105

V2
TP89 TP91
DV18A DV33A TP200 R6 TTE SHENZHEN R&D CENTER
SB33A SB33B SB18A TP92 TP93
ICE Title
R39 0 MT8202
SB33A SB33B SB18A DV18A DV33A VFE_GND GND UTXD TXD
1K Size Document Number Rev
URXD RXD C 2006-5-25 YWX
R40 0
Date: Monday, March 19, 2007 Sheet 3 of 14
A B C  D E
A B C D E

STANDBY ANALOG POWER NORMAL ANALOG POWER CLOSE TO 8202 PIN

XTALVDD ASB18A ASB18A V2 AVICM


XTALVDD [3]
L12 FB
XTALVDD FB1 FB PLLVDD1
ADCVDD CB25 C3
ADCVDD [3] 0.1uF 10uF/10v
AVICM + CE23 C4 C5 CB26 + CE24 C6 C7 CB27 C0805/SMD
AVICM [3] 4.7uF/10V 4.7uF/10V
1uF 4.7uF 0.1uF 1uF 4.7uF 0.1uF AUDIO_GND
PWM2VREF C0402/SMD C0402/SMD
PWM2VREF [3]
LVDS_GND LVDS_GND DACFS
LVDS_GND LVDS_GND PWM2VREF

DACFS C8 R42
4 DACFS [3] 4
PLLVDD2 + CE25 0.1uF 820
4.7uF/16V C0402/SMD V2
LVDDA
LVDDA [3]
ASB33A C9 CB28 LVDS_GND LVDS_GND
LVDDB L13 FB 4.7uF 0.1uF
LVDDB [3]
ADCVDD C0402/SMD
LVDDC LVDS_GND
LVDDC [3]
+ CE26 C10 C11 CB29
4.7uF/10V 1uF 4.7uF 0.1uF
AVDD_VFE0 C0402/SMD PLLVDD3
AVDD_VFE0 [3]
LVDS_GND
AVDD_VAD0 LVDS_GND
AVDD_VAD0 [3]
CB30 VFE_GND1
AADCVDD 0.1uF
AADCVDD [3]
C0402/SMD
ADACVDD LVDS_GND C51
ADACVDD [3]
4.7uF/10v
C0805/SMD
VPLLVDD1 NORMAL VIDEO DAC POWER AV18A REFP
VPLLVDD1 [3]
VPLLVDD2 FB4 FB VPLLVDD1
VPLLVDD2 [3]
DACVDD C49 C173 C174
10uF/10v 0.1uF 0.01uF
FB5 FB DACVDDA + CE27 CB31 C13 CB32 C0805/SMD C0402/SMD C0402/SMD
AVDD_VAD1 BEAD/SMD/0603 4.7uF/10V 1uF 4.7uF 0.1uF
AVDD_VAD1 [3]
C0402/SMD REFN
AVDD_VFE1 + CE28 C14 C15 CB33 LVDS_GND
AVDD_VFE1 [3] 4.7uF/10V 1uF 4.7uF 0.1uF LVDS_GND C50
C0402/SMD 4.7uF/10v
PLLVDD1 LVDS_GND C0805/SMD
PLLVDD1 [3]
PLLVDD2 LVDS_GND
PLLVDD2 [3]
AV33A VFE_GND1
PLLVDD3 FB6 FB DACVDDB
PLLVDD3 [3]
BEAD/SMD/0603 FB7 FB VPLLVDD2

3 DACVDDA C16 CB34 3


DACVDDA [3]
4.7uF 0.1uF + CE29 CB35 C17 CB36
DACVDDB C0402/SMD 4.7uF/10V 1uF 4.7uF 0.1uF
DACVDDB [3]
LVDS_GND C0402/SMD
DACVDDC LVDS_GND
DACVDDC [3]
LVDS_GND

FB8 FB DACVDDC
TESTP3 BEAD/SMD/0603
TESTP3 [3]
TESTN3
TESTN3 [3]
C18 CB37
TESTP4 4.7uF 0.1uF
TESTP4 [3]
TESTN4 C0402/SMD NORMAL VIDEO ADC POWER
TESTN4 [3]
LVDS_GND
TESTP3 R43 49.9 1% PLLVDD1
ADCV33A
AUDIO_GND FB9 FB AVDD_VFE0
AUDIO_GND [1,3,10,11,12,13]
LVDS_GND
LVDS_GND [2,3,14]
+ CE30 CB38 C19 CB39
VFE_GND NORMAL VIDEO DAC POWER 4.7uF/10V 1uF 4.7uF 0.1uF TESTN3 R44 49.9 1% PLLVDD1
VFE_GND [2,3,10,11]
C0402/SMD
AADCVSS VFE_GND1
AADCVSS [1,3,10,11,12,13]
AV33A TESTP4 R45 49.9 1% VPLLVDD1
VFE_GND1 VFE_GND1
VFE_GND1 [2,3,11,12]
FB10 FB LVDDA
BEAD/SMD/0603 FB11 FB AVDD_VAD0
REFP
REFP [3]
REFN + CE31 C20 C21 CB40
REFN [3] 4.7uF/10V 1uF 4.7uF 0.1uF C22 CB41
GNDA C0402/SMD 4.7uF 0.1uF TESTN4 R46 49.9 1% VPLLVDD1
GNDA [1,3,10,11,12,13]
LVDS_GND C0402/SMD
LVDS_GND VFE_GND1

AADCVSS LVDDB
AADCVSS [1,3,8,9,10,11,12,14]
VFE_GND ADCV18A
2 VFE_GND [2,3,8,9,10,11,12,14] 2

+5V C23 CB42 FB13 FB AVDD_VFE1


+5V [1,2,4,6,8,9,10,11,12,13,14]
4.7uF 0.1uF
C0402/SMD
LVDS_GND + CE32 CB43 C24 CB44
4.7uF/10V 1uF 4.7uF 0.1uF
C0402/SMD
VFE_GND TP27
LVDDC VFE_GND
VFE_GND

C25 CB45 FB15 FB AVDD_VAD1 TP8


4.7uF 0.1uF VFE_GND
C0402/SMD
LVDS_GND C26 CB46
4.7uF 0.1uF TP9
C0402/SMD VFE_GND
VFE_GND
TP15
VFE_GND1

TP17
NORMAL AUDIO ADC / DAC POWER VFE_GND1

ADCV33A TP24 TP18


AADCVSS GNDA LVDS_GND
L14 150uH AADCVDD TP26
L/IND/DIP/P10.0 AUDIO_GND
TP19
+ CE33 C27 + CE34 CB47 LVDS_GND LVDS_GND
4.7uF/10V 1uF 220uF/16V 0.1uF
C0402/SMD VFE_GND VFE_GND1
AADCVSS +5V
AADCVSS
1 1

ADCV33A CE12 + + CE16


4.7uF/16v
L15 150uH ADACVDD 10uF/25v
L/IND/DIP/P10.0

+ CE35 C28 + CE36 CB48


4.7uF/10V 1uF 220uF/16V 0.1uF AADCVSS
C0402/SMD TTE SHENZHEN R&D CENTER
AUDIO_GND Title
AUDIO_GND MT8202

Size Document Number Rev


C 2006-5-26 YWX

Date: Wednesday, December 27, 2006 Sheet 4 of 14


A B C  D E
A B C D E

MT8202 DIGITAL POWER & DECOUPLING

4 4

DV18A
SB33A SB18A
0402 PUT ON NEARLY BGA
SB18A

CB49 CB50 C31 CB51 CB52 CB53 CB54


0.1uF 0.1uF 3300pF 0.1uF 0.1uF 0.1uF 0.1uF
C0402/SMD C0402/SMD C0402/SMD C0402/SMD C0402/SMD

0402 PUT ON NEARLY BGA


0402 PUT ON NEARLY BGA
C32 C33 C34
CB55 C29 C30 3300pF 3300pF 3300pF
0.1uF 0.01uF 3300pF C0402/SMD C0402/SMD C0402/SMD
3 3
C0402/SMD C0402/SMD C0402/SMD

5VSB DV33A

2 2

+ CE37 + CE38
4.7uF/0805 4.7uF/0805 CB56 CB57 CB58 CB59 CB60 CB61
0.1uF 0.1uF 0.01uF 0.1uF 0.1uF 0.01uF
C0402/SMD C0402/SMD C0402/SMD

1 1

TTE SHENZHEN R&D CENTER


Title
MT8202

Size Document Number Rev


B 2005-5-26 YWX

Date: Wednesday, December 27, 2006 Sheet 5 of 14


A B C D E


A B C D E

DV25B DV25B U7
IOA1 25 29 F_D0
RN2 U4 D1V25 IOA2 A0 D0 F_D1
24 A1 D1 31
A_RA3 7 8 D_RA3 1 66 IOA3 23 33 F_D2
A_RA2 D_RA2 D_DQ0 VDD VSS D_DQ15 RN3 IOA4 A2 D2 F_D3
5 6 2 DQ0 DQ15 65 22 A3 D3 35
A_RA1 3 4 D_RA1 3 64 D_RA3 7 8 IOA5 21 38 F_D4
A_RA0 D_RA0 D_DQ1 VDDQ VSSQ D_DQ14 D_RA2 IOA6 A4 D4 F_D5
1 2 4 DQ1 DQ14 63 5 6 20 A5 D5 40
D_DQ2 5 62 D_DQ13 D_RA1 3 4 IOA7 19 42 F_D6
RN4 22x4 DQ2 DQ13 D_RA0 F_A8 A6 D6 F_D7
6 VSSQ VDDQ 61 1 2 18 A7 D7 44
A_RA6 7 8 D_RA6 D_DQ3 7 60 D_DQ12 F_A9 8 30
A_RA7 D_RA7 D_DQ4 DQ3 DQ12 D_DQ11 75x4 F_A10 A8 D8
5 6 8 DQ4 DQ11 59 7 A9 D9 32
A_RA4 3 4 D_RA4 9 58 RN5 F_A11 6 34 SB33B
A_RA5 D_RA5 D_DQ5 VDDQ VSSQ D_DQ10 D_RA5 F_A12 A10 D10
1 2 10 DQ5 DQ10 57 8 7 5 A11 D11 36
D_DQ6 11 56 D_DQ9 D_RA4 6 5 F_A13 4 39
RN6 22x4 DQ6 DQ9 D_RA7 F_A14 A12 D12 SB33B
12 VSSQ VDDQ 55 4 3 3 A13 D13 41
A_RA8 7 8 D_RA8 D_DQ7 13 54 D_DQ8 D_RA6 2 1 F_A15 2 43 R61
A_RA9 D_RA9 DQ7 DQ8 F_A16 A14 D14 IOA0
4
5 6 14 NC NC 53 1 A15 D15 45 4
A_RA11 3 4 D_RA11 15 52 75x4 SB33B F_A17 48 16 F_A19
A_DQS[0..3] A_DQS[0..3] [3] D_DQS0 VDDQ VSSQ D_DQS1 RN7 F_A18 A16 A18 10k R62
1 2 16 LDQS UDQS 51 17 A17 NC 13
A_RA[0..11] A_RA[0..11] [3] 17 50 2 1 15 14 0
A_BA[0..1] A_BA[0..1] [3] 22x4 NC NC VREF D_RA8 R63 F_A20 RY/BY WP/ACC
18 VDD VREF 49 4 3 9 A19 BYTE 47
A_DQM[0..1] A_DQM[0..1] [3] A_RA10 R64 22 D_RA10 19 48 D_RA9 6 5 10k F_A21 10
A_DQ[0..31] A_DQ[0..31] [3] D_DQM0 DNU VSS D_DQM0 CB64 D_RA11 PCE# A20 FLASHVCC
20 LDM UDM 47 8 7 IOCE# 26 CE VCC 37
D_WE# 21 46 D_CLK# F_OE# 28
A_CLK A_CLK [3] RN8 D_CAS# WE CK D_CLK 75x4 PWR# OE C108
22 CAS CK 45 IOWR# 11 WE GND1 27
A_CLK# A_CLK# [3] A_DQ0 7 8 D_DQ0 D_RAS# 23 44 D_CKE 0.1uF 46 4.7uF/10v CB65
A_CKE A_CKE [3] A_DQ1 D_DQ1 D_CS# RAS CKE D_BA1 R65 75 GND2 C0805/SMD 0.1uF
5 6 24 CS NC 43 SB33B 12 RESET
A_CS# A_CS# [3] A_DQ2 3 4 D_DQ2 25 42
A_RAS# A_RAS# [3] A_DQ3 D_DQ3 D_BA0 NC A12 D_RA11
1 2 26 BA0 A11 41
A_CAS# A_CAS# [3] D_BA1 27 40 D_RA9 RN9 29LV160
A_WE# A_WE# [3] RN10 47x4 D_RA10 BA1 A9 D_RA8 D_DQ0
28 A10/AP A8 39 7 8 TSOP 48 pin
A_DQ4 7 8 D_DQ4 D_RA0 29 38 D_RA7 D_DQ1 5 6
A_DQ5 D_DQ5 D_RA1 A0 A7 D_RA6 D_DQ2 D1V25
5 6 30 A1 A6 37 3 4
A_DQ6 3 4 D_DQ6 D_RA2 31 36 D_RA5 D_DQ3 1 2
VREF A_DQ7 D_DQ7 D_RA3 A2 8M x 16 A5 D_RA4 D1V25
VREF [3] 1 2 32 A3 DDR A4 35
33 34 75x4
RN11 47x4 VDD VSS RN12
A_DQ8 7 8 D_DQ8 M13S128168 8Mx16-5 D_DQ4 7 8
A_DQ9 5 6 D_DQ9 D_DQ5 5 6 CB66 CB67 CB68 CB69 CB70 CB71 CB72 CB73
A_DQ10 3 4 D_DQ10 D_DQ6 3 4 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
A_DQ11 1 2 D_DQ11 D_DQ7 1 2

RN13 47x4 75x4


A_DQ12 7 8 D_DQ12 RN14
A_DQ13 5 6 D_DQ13 D_DQ8 7 8
A_DQ14 3 4 D_DQ14 D_DQ9 5 6 D1V25
A_DQ15 1 2 D_DQ15 D_DQ10 3 4
D_DQ11 1 2
47x4
DV25B DV25B 75x4 CB74 CB75 CB76 CB77 CB78 CB79 CB80 CB81
RN15 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
RN16 U5 D_DQ12 7 8
A_DQ16 7 8 D_DQ16 1 66 D_DQ13 5 6
A_DQ17 D_DQ17 D_DQ16 VDD VSS D_DQ31
5 6 2 DQ0 DQ15 65 D_DQ14 3 4
3 A_DQ18 3 4 D_DQ18 3 64 D_DQ15 1 2 3
F_A[8..21] F_A[8..21] [3,6] A_DQ19 D_DQ19 D_DQ17 VDDQ VSSQ D_DQ30
1 2 4 DQ1 DQ14 63
D_DQ18 5 62 D_DQ29 75x4 D1V25
RN17 47x4 DQ2 DQ13 RN18
6 VSSQ VDDQ 61
IOA[0..7] IOA[0..7] [3,6] A_DQ20 7 8 D_DQ20 D_DQ19 7 60 D_DQ28 D_DQ16 2 1
A_DQ21 D_DQ21 D_DQ20 DQ3 DQ12 D_DQ27
5 6 8 DQ4 DQ11 59 D_DQ17 4 3
A_DQ22 3 4 D_DQ22 9 58 D_DQ18 6 5 CB82 CB83 CB84 CB85 CB86 CB87 CB88 CB89 CB90 CB91 CB92
F_D[0..7] F_D[0..7] [3,6] A_DQ23 D_DQ23 D_DQ21 VDDQ VSSQ D_DQ26 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
1 2 10 DQ5 DQ10 57 D_DQ19 8 7
D_DQ22 11 56 D_DQ25
RN19 47x4 DQ6 DQ9 75x4
12 VSSQ VDDQ 55
F_OE# F_OE# [3] A_DQ24 7 8 D_DQ24 D_DQ23 13 54 D_DQ24 RN20
A_DQ25 D_DQ25 DQ7 DQ8
5 6 14 NC NC 53 D_DQ20 2 1
A_DQ26 3 4 D_DQ26 15 52 D_DQ21 4 3 D1V25
A_DQ27 D_DQ27 D_DQS2 VDDQ VSSQ D_DQS3
1 2 16 LDQS UDQS 51 D_DQ22 6 5
F_A[8..21] F_A[8..21] [3,6] 17 50 D_DQ23 8 7
RN21 47x4 NC NC VREF
18 VDD VREF 49
A_DQ28 7 8 D_DQ28 19 48 75x4 C40 C41 C42 C43 C44 C45 C46 C47
A_DQ29 D_DQ29 D_DQM1 DNU VSS D_DQM1 CB93 RN22 3300pF 3300pF 3300pF 3300pF 3300pF 3300pF 3300pF 3300pF
5 6 20 LDM UDM 47
A_DQ30 3 4 D_DQ30 D_WE# 21 46 D_CLK# D_DQ27 1 2
A_DQ31 D_DQ31 D_CAS# WE CK D_CLK
1 2 22 CAS CK 45 D_DQ26 3 4
D_RAS# 23 44 D_CKE 0.1uF D_DQ25 5 6
47x4 D_CS# RAS CKE D1V25
24 CS NC 43 D_DQ24 7 8
25 NC A12 42
D_BA0 26 41 D_RA11 75x4
A_DQS0 R66 47 D_DQS0 D_BA1 BA0 A11 D_RA9 RN23 + CE39 + CE40
27 BA1 A9 40
D_RA10 28 39 D_RA8 D_DQ31 1 2
A_DQS1 R67 47 D_DQS1 D_RA0 A10/AP A8 D_RA7 33uF/16v OS-CON/NC 100uF/16v
29 A0 A7 38 D_DQ30 3 4
D_RA1 30 37 D_RA6 D_DQ29 5 6 C270UF16V/D10H12
A_DQS2 R68 47 D_DQS2 D_RA2 A1 A6 D_RA5
31 A2 8M x 16 A5 36 D_DQ28 7 8
D_RA3 32 35 D_RA4
A_DQS3 R69 47 D_DQS3 A3 DDR A4 75x4
33 VDD VSS 34

RN24 DV25B
M13S128168 8Mx16-5
+5V D_CS# 7 8
+5V [1,2,4,6,8,9,10,11,12,13,14]
D_RAS# 5 6 DV25B
RN25 D_BA0 3 4
A_CAS# 7 8 D_CAS# D_RA10 1 2
A_WE# 5 6 D_WE#
2 2
A_CS# 3 4 D_CS# 75x4 CB94 CB95 CB96 CB97 CB98 CB99 CB100 CB101
A_RAS# 1 2 D_RAS# 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

22x4 D1V25 DV25B DV33B D_DQS2 R70 75


A_BA1 R71 22 D_BA1
DV25A D_DQS3 R72 75
DV25A [3]
A_BA0 R73 22 D_BA0
SDV25A D_CAS# R75 75
SDV25A [3]
A_DQM0 R76 22 D_DQM0
DV33B R169 U6 D_WE# R77 75
DV33B [3]
A_DQM1 R78 22 D_DQM1 100K 1 8 CB102 CB103 CB104 CB105 CB106 CB107 CB108 CB109
VIN VCNTL D_DQM1 R79 75 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
2 GND VCNTL 7
A_CKE R80 22 D_CKE 3 6
VREF REFEN VCNTL D_DQS1 R81 75
4 VOUT VCNTL 5
A_CLK R82 22 D_CLK C183 R74
100PF CB110 CB111 + CE42 C172 D_DQS0 R83 75
A_CLK# R84 22 D_CLK# C0402/SMD 100K 100Uf/10v 10uF/10v
0.1uF 0.1uF SP2996B DDR Termination 8 PIN NSOIC C0805/SMD D_DQM0 R85 75 DV25A
D_CLK R327 100/NC D_CLK# + CE41 0402 PUT ON NEARLY BGA
47Uf/10v DV25A
D_CLK R328 100/NC D_CLK#

D_CLK R329 100/NC D_CLK# CB116 CB117 CB118 CB119


C54 C55
3300pF 3300pF 0.1uF 0.1uF 0.1uF 0.1uF
C0402/SMD C0402/SMD C0402/SMD C0402/SMD C0402/SMD C0402/SMD
DV25B V2
SDV25 SDV25A
L16 FB SDV25A

CB120 CB121 CB122 CB123 CB124


VREF
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF CB112 CB113 CB114

VREF DV25B 0.1uF 0.1uF 0.1uF


C0402/SMD C0402/SMD C0402/SMD
1 1
VREF
VREF DECOUPLING
VREF DV25A DV25A DV25B
+5V U25
DV25B
CB125 CB126 CB127 CB128 CB129
3 2 L17 FB CLOSE TO 8202 PIN
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF IN OUT + CE45 + CE47 + CE48
DV25A

ADJ/GND
33uF/16v 33uF/16v 33uF/16v TTE SHENZHEN R&D CENTER
+ CE44 + CE46 Title

1
Tan C56 CB130 2006-5-26
100Uf/10v REGULATOR LT1084 TO-252-3 100Uf/10v 10uF/10v 0.1uF
C0805/SMD Size Document Number Rev
TO-252-3/SMD C <Doc> YWX

Date: Wednesday, December 27, 2006 Sheet 6 of 14


A B C  D E
A B C D E

U36
VI[0..23] AVCC
VI[0..23] [3] DV33B PLUGPWR 1 5V_SUPPLY NC 38
L20 C99
HDMICEN AVCC 2 37
HDMICEN [3] LV_SUPPLY NC
HDMIODCK FB CE49 3 36
HDMIODCK [3] GND GND
HDMIDE + CB131 10uF/10v
HDMIDE [3]
+ CE50 C57 DATA2+ 4 35 DATA2+ C0805/SMD
HDMIHSYNC 4.7uF/16v 0.1uF 1000pF TMDS_D2+ TMDS_D2+
HDMIHSYNC [3]
HDMIVSYNC 33uF/16v 5 34

23
22
HDMIVSYNC [3] TMDS_GND TMDS_GND
DE_SOG DATA2- 6 33 DATA2- DATA2+ 1 P1
DE_SOG [3] TMDS_D2- TMDS_D2-
2 HDMI TYPE-A
GPIO17 L22 DATA1+ DATA1+ DATA2-
GPIO17 [3] 7 TMDS_D1+ TMDS_D1+ 32 3 HDMI/SMD/CON/A
GPIO18 IOVCC DATA1+4
GPIO18 [3]
8 TMDS_GND TMDS_GND 31 5
SCL FB CE53 DATA1- 6
4 SCL [1,6,11] 4
SDA + CB133 DATA1- 9 30 DATA1- DATA0+ 7
SDA [1,6,11] TMDS_D1- TMDS_D1-
C58 8
4.7uF/16v 0.1uF 1000pF DATA0+ 10 29 DATA0+ DATA0- 9
TMDS_D0+ TMDS_D0+ CLOCK+
CM2021 10
11 TMDS_GND TMDS_GND 28 11
CLOCK- 12
INT0# L23 DATA0- DATA0- R90 R/NC
INT0# [3,6] 12 TMDS_D0- TMDS_D0- 27 V2 13
PVCC TP41 14
27MHZ CLOCK+ 13 26 CLOCK+ HDMI_DDC_SCL 15
27MHZ [3] TMDS_CK+ TMDS_CK+
FB CE54 HDMI_DDC_SDA 16
+ CB134 14 25 HDMI_PLUGPWR 17
HDMIMCLK C59 TMDS_GND TMDS_GND HDMI_PLUGPWR PLUGPWR
HDMIMCLK [3] 18
HDMIBCLK 4.7uF/16v 0.1uF 1000pF CLOCK- 15 24 CLOCK- HDMICAB_OUT 19
HDMIBCLK [3] TMDS_CK- TMDS_CK-
HDMILRCK R93 0
HDMILRCK [3]
16 23 R94 R52
CE_REMOTE_IN CE_REMOTE_OUT
20
HDMISD0 NC 21
HDMISD0 [3] HDMI_DDC_SCL
HDMISD1 DDC_SCL R91 0 17 22 1K
HDMISD1 [3] L24 DDC_CLK_IN DDC_CLK_OUT
HDMISD2 V2 HDMICAB_IN
HDMISD2 [3] HDMI_DDC_SDA
HDMISD3 REGVCC DDC_SDA R92 0 18 21
HDMISD3 [3] DDC_DAT_IN DDC_DAT_OUT
DV33B
DV33B [7,8,9,12,13,14]
FB CB138 HDMICAB_IN 19 20 HDMICAB_OUT
HOTPLUG_DET_IN HOTPLUG_DET_OUT
0.1uF

2
R105
GPIO18 1 Q20
2N3904
DV33B DV33B 4.7K SOT23/SMD

3
R95 0
27MHZ
IOVCC
TP42 R96
CB139 U9 4.7k
1 8 R97
0.1uF NC VCC KWP 4.7K R98
2 NC WP 7
3 6 HDCP_SCL TP44 TP43 HDMIRST# DE_SOG U26 AZ1117/adj L70 FB AVCC18
NC SCL HDCP_SDA TP46 TP45 DV33B
4 GND SDA 5
CI2CA 0
3 TP47 3 2 L21 FB VCC18 3
EEPROM 24C08/CODE TP48 IN OUT
TP49 R100
ADJ/GND

IOVCC
TP50

VCC18
IOVCC
VCC18
IOVCC
TP51 TP52 TP53 TP54 TP55 TP56 4.7K/NC + CE51 + CE52
1

HDCP_SCL
CB132

HDCP_SDA
KWP
OSC_IN
HDMICEN
AVCC 4.7uF/16v 0.1uF SOT223/SMD 4.7uF/16v

CB135 C60 CB136 C61 CB137 C62


U8

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0.1uF 1000PF 0.1uF 1000PF 0.1uF 1000PF MT8293

NC
NC
CM2021

CEN

KWP

KSCL
KSDA
RN26 33x4

GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
VSYNC

GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
OSC_IN
SOG_IN
HDMIVSYNC

CVCC18
CVCC18

CGND18
CGND18
8 7

IOVCC33
IOVCC33
IOVCC33

IOGND33
IOGND33
IOGND33
G1 6 5 HDMIODCK VCC18
ePad/GND HDMIHSYNC
33 GPIO2 HSYNC 128 4 3
34 127 2 1 HDMIDE
GPIO1 DE CB140 C63 CB141 C64 CB142 C65 CB143 C66 CB144 C67
35 GPIO0 CGND18 126
V2 VCC18 36 125 VCC18 RN27 33x4
CVCC18 CVCC18 VI0 0.1uF 1000PF 0.1uF 1000PF 0.1uF 1000PF 0.1uF 1000PF 0.1uF 1000PF
37 CGND18 QE0 124 8 7
CI2CA 38 123 6 5 VI1
SDA R106 0 CI2CA QE1 VI2
39 CSDA QE2 122 4 3
SCL R107 0 40 121 2 1 VI3
9993_SDA R108 0 CSCL QE3 IOVCC
41 DSDA IOVCC33 120
9993_SCL R109 0 42 119
DSCL ODCK RN28 33x4
43 CEC IOGND33 118
PLUGPWR 44 117 8 7 VI4
VCC18 R110 0 AVCC18 L25 FB PWR5V QE4 VI5 CB145 C68 CB146 C69
45 CVCC18 QE5 116 6 5
46 115 4 3 VI6
C109 PVCC PGND QE6 VI7 0.1uF 1000PF 0.1uF 1000PF
47 PVCC QE7 114 2 1
NC if AVCC18 from regulator 0.1uF TP1 48 113
C0402/SMD AVCC EXT_RES CGND18 VCC18 RN29 33x4
49 AVCC CVCC18 112
CLOCK- 50 111 8 7 VI8
CLOCK+ RXC- QE8 VI9
51 RXC+ QE9 110 6 5
52 109 4 3 VI10 IOVCC
2
AVCC
DATA0-
53
54
AGND
AVCC
MT8293 QE10
QE11 108
107 IOVCC
2 1 VI11
2

DATA0+ RX0- IOVCC33 RN30 33x4 CB149 C72 CB150 C73 CB151 C74 CB152 C75
55 RX0+ IOGND33 106
HDMI_PLUGPWR 56 105 8 7 VI12
HDMI_PLUGPWR AVCC AGND QE12 VI13 0.1uF 1000PF 0.1uF 1000PF 0.1uF 1000PF 0.1uF 1000PF
57 AVCC QE13 104 6 5
DATA1- 58 103 4 3 VI14
DATA1+ RX1- QE14 VI15
59 RX1+ QE15 102 2 1
60 101 8 7 VI16
AVCC AGND QE16 VI17
61 AVCC QE17 100 6 5
DATA2- 62 99 4 3 VI18
R117 R118 DATA2+ RX2- QE18 IOVCC VI19
63 RX2+ IOVCC33 98 2 1
C80 U10 47k 47k 64 AGND IOGND33 97
1 8 RN31 33x4 CB153 C76 CB154 C77 CB155 C78 CB156 C79
0.1uF NC VCC
2 NC WP 7
3 6 HDMI_DDC_SCL 0.1uF 1000PF 0.1uF 1000PF 0.1uF 1000PF 0.1uF 1000PF
NC SCL HDMI_DDC_SDA
4 GND SDA 5

CGND18
CVCC18
MUTE
IOVCC33
IOGND33
SPDIF
SD3
SD2
SD1
SD0
WS
SCK
IOVCC33
IOGND33
MCLK
CGND18
CVCC18
AUDPVCC18
AUDPGND
XTALOUT
XTALIN
XTALVCC
REGVCC
TEST
RESET#
SCDT
INT
QE23
QE22
QE21
QE20
QE19
EEPROM 24C02/CODE LQFP128/SMD/8293

65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
R113 C81
V2 RN32 33x4 COAXOUT
8 7 VI20
6 5 VI21
4 3 VI22 100 0.1uF
2 1 VI23 R114 C82
AVCC V2 SPDIF OUTOUT
33pF

VCC18
IOVCC
SPDIF
HDMILRCK
IOVCC
VCC18
XTLO
XTLI
REGVCC
R253 0 100

HDMISD3
HDMISD2
HDMISD1
HDMISD0
HDMIBCLK
HDMIMCLK
HDMIRST#
GPIO17
INT0#

R112 NC R119 R120 1


47k 47k TP61 COAXOUT 1
QF1 2 2
TP62 R115 SPDIF 3 3
DDC_SCL 2 3 9993_SCL DV33B
L26 R116 33
MOSFET N 2N7002/NC 1M/NC JP13
AVCC SOT23/SMD
L27 S/PDIF OUT/NC

1
1 FB Modified by Bin_wang.2006/01/20 1
AVCC18 CB157 C83 X3
FB C125 0.1uF 0.01uF XTLI XTLO
0.1uF
R152 NC C0402/SMD 27MHz/NC
CRYS/49US/P4.88
C85 C86
QF2 18pF/NC 18pF/NC
DDC_SDA 2 3 9993_SDA

MOSFET N 2N7002/NC TTE SHENZHEN R&D CENTER


SOT23/SMD Title

1
AVCC MT8202

Size Document Number Rev


C 2006-5-26 <RevCode>

Date: Wednesday, December 27, 2006 Sheet 7 of 14


A B C  D E
A B C D E

VGA IN NEARLY VGA CON NEARLY IC


V2
RED+ RED+ [3]
RED- RED- [3] P2 RED R131 0 R132 68 C87 10nF RED+
GREEN+ GREEN+ [3] D-SUB15 FEMALE +5V

16
GREEN- GREEN- [3] DSUB15/DIP/F
BLUE+ BLUE+ [3]
BLUE- BLUE- [3] 6 RED_GND R133 C88
11 1 RED D13 82 5pF
VGASOG VGASOG [3] 7 GRN_GND 1N4148
VGASDA_IN 12 2 GREEN
VGAHSYNC# VGAHSYNC# [3] 8 BLU_GND RED_GND R134 100 C89 10nF RED-
VGAVSYNC# VGAVSYNC# [3] HSYNC# 13 3 BLUE
9 PIN9 D14 1N4148 VGA_PLUGPWR
VSYNC# 14 4 FB17
10 R135 NC 0
4 4
GPIO11 VGASCL_IN 15 5
GPIO11 [3,8]
VFE_GND
VFE_GND [2,3,4,9,10,11,12,14]
R136 0 C90 4.7nF VGASOG

17
GNDA GREEN R137 0 R138 68 C91 10nF GREEN+
GNDA [1,3,4,11,12,13]

R139 C92 V2
+5V
NEAR CONNECTOR 82 5pF
+5V [1,2,4,6,8,9,10,11,12,13,14]
A-YUV-R
A-YUV-R [10]
GRN_GND R140 100 C93 10nF GREEN-
A-YUV-L
A-YUV-L [10]
DV33B FB20
DV33B [7,8,9,12,13,14] U32 0
RED 1 5 BLUE
A D
2 GND
3 4 GREEN V2
+5V +5V B C

PESD3V3L4UG BLUE R145 0 R146 68 C94 10nF BLUE+

R28 R29
NC NC R147
U33 C97
R37 QF5 R49 QF6 VGASCL_IN VGASDA_IN 82 5pF
1 A D 5
VGASCL_IN 2 3 TXD VGASDA_IN 2 3 RXD 2
TXD RXD GND
3 4 HSYNC#
2N7002 2N7002 B C BLU_GND R148 100 C98 10nF BLUE-
1K N-MOSFET 1K N-MOSFET

1
1
PESD3V3L4UG
SB33B FB21
0
3 3
R172 U34
4.7K VGA_PLUGPWR Y-R1 1 5 Y-L
A D
2 GND V2
3 B C 4

R141
3.3K PESD3V3L4UG R332 510

2
HSYNC# L29 2.2uH VGAHSYNC#
GPIO11 1 Q29
VGASCL_IN R143 100 VGASCL
R528 U35
4.7K PDTC143ZT Y0_IN 1 5 PB0_IN R150 C100
SOT23/SMD A D 5pF
2 GND
C95 3 4 PR0_IN 2K
0.1uF/NC B C

PESD3V3L4UG

3
R333 510
VGA_PLUGPWR VSYNC# L30 2.2uH VGAVSYNC#

R142 R154 C102


3.3K 5pF
2K

VGASDA_IN R144 100 VGASDA

VGA_PLUGPWR
C96
VGA_PLUGPWR 0.1uF/NC

NEARLY IC C112 4.7nF SOY0


2 SOY0 2
H : WP ENABLE R151
CB162 L : WP DISABLE 20K Y0_IN R126 0 AVY0P
0.1uF U11 R55 0
1 NC VCC 8
2 7 VGAROMWP
NC WP VGASCL R495
3 NC SCL 6
4 5 VGASDA 82 AVY0P R199 68 C115 100nF Y0+
GND SDA Y0+
EEPROM 24C02 R155
10K/NC Y_GND AVY0N C116
15pF

FB27
0 AVY0N R202 100 C119 100nF Y0-
Y0-

CN1

COMPONENT AVPB0P R203 68 C122 100nF PB0+


PB0+
L53 FB PB0_IN R128 0 AVPB0P
+5V Y_GND 9 10 Y0_IN
GND5 SIG5 C123
15pF
R350 L54 FB R496
PB_GND 7 8 PB0_IN 82
R4 CE192 22uF/35V 47K GND4 SIG4 AVPB0N R206 100 C126 100nF PB0-
PB0-

+
Y-R Y-R1 A-YUV-R
L55 FB PB_GND AVPB0N
R86 PR_GND 5 6 PR0_IN
15K NC R351 GND3 SIG3
R0603/SMD 47K FB28 AVPR0P R207 68 C129 100nF PR0+
PR0+
0
C130
15pF

1 PR0_IN R130 0 AVPR0P AVPR0N R210 100 C133 100nF PR0- 1


PR0-

+5V
CN2 COMPONENT_AUDIO R497
82
R352 L56 FB
GNDA 3 4 Y-R
R7 CE193 22uF/35V 47K GND5 SIG5 PR_GND AVPR0N

+
Y-L A-YUV-L
L57 FB
R87 GNDA 1 2 Y-L FB29 GNDA VFE_GND TTE SHENZHEN R&D CENTER
15K NC GND4 SIG4 Title
0
R0603/SMD R353 MT8202
47K
Size Document Number Rev
C 2006-5-26 YWX

Date: Wednesday, December 27, 2006 Sheet 8 of 14


A B C  D E
A B C D E

AUDIO ADC +5V

R156
10K

QF3
SCL_V50 2 3 SCL

DV33B 2N7002
+5V ADCVA ADCVD DV33B ADCVL N-MOSFET

1
FB23 FB ADCVA R157 5.1 ADCVD FB24 FB ADCVL
4 4

+ CE59 + CE60 CB163 C103 CB164 + CE61 C104 CB165


4.7uF/25V 4.7uF/25V 0.1uF 1uF 0.1uF 4.7uF/25V 1uF 0.1uF

+5V

R158
10K

QF4
ADCVL SDA_V50 2 3 SDA
ADCVL ADCVL
DV33B 2N7002
R159 N-MOSFET

1
10K
R160 R161
10K 10K
ADCRST#

2
ADCM0 ADCM1
GPIO121 Q30

R164 R165 SCL


SCL [1,6,8,9]
PDTC143ZT 10K/NC 10K/NC SDA
SDA [1,6,8,9]
SOT23/SMD

SCL_V50
SCL_V50 [1,6,8,9]
SDA_V50
SDA_V50 [1,6,8,9]

3
+12V
+12V [1,2,9,10,11,12,14]

3 3
ADCVA ADCVA ADCVL ADCVL ADCVL

CB167 CB168
0.1uF 0.1uF R166 R167 R168
10K/NC 10K/NC 10K/NC

AOMCLK AOBCLK AOLRCK VFE_GND


VFE_GND [2,3,4,8,10,11,12,14]

TESTP2
TESTP2 [3]
U12 VFE_GND1
VFE_GND1 [2,3,4,8,10,12]
ADCM0 1 16 ADCM1
AOMCLK R174 33 M0 M1
2 MCLK FILT+ 15
ADCVL 3 14
ADIN R176 33 VL REF_GND ADCVA CB170 + CE64
4 SDOUT VA 13
5 12 A_IN_R 0.1uF 47uF/16V
ADCVD GND AINR
6 VD VQ 11
AOBCLK R177 33 7 10 A_IN_L
AOLRCK R178 33 SCLK AINL ADCRST# GNDA
8 LRCK RST# 9 GNDA [1,3,4,10,12,13]
CB171 C105
CS5340 ADC 0.1uF 1uF
R179 TSSOP16/SMD V2
PULL DOWN FOR LJ 10K AUDIO ADC
AOMCLK AOMCLK [3,13
AOBCLK AOBCLK [3,13]
AOLRCK AOLRCK [3,13]
+5V
ADIN ADIN [3]

+5V
2 +5V [1,2,4,6,8,9,10,11,12,13,14] 2

BYPASS VIDEO OUTPUT CVBS_OUT


CVBS_OUT [9,14]
C106 C107
4.7uF/16V 0.1uF DV33B
C0603/SMD DV33B [7,8,9,12,13,14]
+12V +5V
GPIO12
U13 GPIO12 [3,9]
+12V +5V
1 16 FB32 FB33
FB34 R122 0 C165 A-YUV-L Y0B VDD
A-DTV-L 2 Y2B Y2A 15 A-DTV-R NC FB
A_IN_L C166 R125 0 FB35 FB30 FB31
3 ZB Y1A 14 AU_IN_R
10uF/10v 4 13 A_IN_R
1uF/10v R123 Y3B ZA NC FB
AU_IN_L 5 Y1B Y0A 12 A-YUV-R
NC C179 6 11 R124 1uF/10v CB173
0.01uF /E Y3A SW1 10uF/10v C180 NC + CE2
7 VEE A0 10
8 9 SW2 0.01uF R187 0.1uF 4.7uF/16v
VSS A1 24K V2
HEF4052
TSSOP16/SMD
2

CE67 R58
CE68 NC NC
+

TESTP2 R181 0 1 Q7
+

2SD2653K
+5V
33uF/10v
3

R188 75
CVBS_OUT
R498
27K
R190 R191
SW1 47K 330 1%

2
R500
FCLK 1 Q23
FCLK 2N3904
SOT23/SMD
R104

3
10K NC

+5V
1 1

R499
27K

SW2

2
R501
FCMD 1 Q26 +5V DV33B
FCMD 2N3904
SOT23/SMD

3
10K +5V DV33B
TTE SHENZHEN R&D CENTER
Title
GNDA VFE_GND MT8202

Size Document Number Rev


C 2006-5-26 YWX

Date: Wednesday, December 27, 2006 Sheet 9 of 14


A B C  D E
A B C D E

CVBS0
CVBS0 [3]
CVBS1 THIS PAGE NEARLY IC
CVBS1 [3]
CVBS2
CVBS2 [3]
CVBS3
CVBS3 [3]
R41 0
AVCVBS1 C136 4.7nF SOY1
SY0
SY0 [3]
SC0 AVCVBS0 R197 0 C110 47nF CVBS0 AVSY0 R198 0 C111 47nF SY0
SC0 [3]
R56 NC

C113 C114
330pF 330pF
R/AVY1P R211 68 C137 100nF Y1+
4 4
VFE_GND1 VFE_GND1
C138
15pF

AVCVBS1 R200 0 C117 47nF CVBS1 AVSC0 R201 0 C118 47nF SC0 AVY1N R213 100 C140 100nF Y1-

Y1+
Y1+ [3]
Y1- C120 C121
Y1- [3] 330pF 330pF
PB1+
PB1+ [3]
PB1- G/AVPB1P R214 68 C141 100nF PB1+
PB1- [3]
PR1+
PR1+ [3]
PR1- VFE_GND1 VFE_GND1
PR1- [3]
SOY1 C142
SOY1 [3] 15pF

R54 C164
AVCVBS2 R204 0 C124 47nF CVBS2 AVSY1 SY1 AVPB1N R217 100 C145 100nF PB1-

C127 0 47nF
TO MT8202 330pF C128 C0402/SMD
330pF B/AVPR1P R218 68 C146 100nF PR1+
C0402/SMD
VFE_GND1 VFE_GND1
C147
15pF

AVCVBS3 R208 0 C131 47nF CVBS3 R53 C132 AVPR1N R219 100 C148 100nF PR1-
AVCVBS0 AVSC1 SC1
AVCVBS0 [11]
AVCVBS1
AVCVBS1 [11]
AVCVBS2 C134
AVCVBS2 [11] 330pF
AVCVBS3 0 47nF
AVCVBS3 [11]
C135 C0402/SMD
330pF
AVSY0 VFE_GND1 C0402/SMD
AVSY0 [11]
3 AVSC0 3
AVSC0 [11]
VFE_GND1
AVPB1N 2006-1-4
AVPB1N
AVY1N
AVY1N
AVPR1N
AVPR1N

+5V
+5V
L28
TVDPWR

R349 33 U14 FB
1 16 + CE58
GPIO16 Y1P IN VCC 4.7uF/16v CB158 CB161
2 SA1 EN 15
R 3 14 0.1uF 0.01uF
R/AVY1P SA2 SD1
4 DA SD2 13
PB1P 5 12
C149 G SB1 DD
6 SB2 SC1 11 PR1P
22pF R227 G/AVPB1P 7 10 B CE190 CB198
NC DB SC2 B/AVPR1P 4.7uF/16V 0.1uF
8 GND DC 9
R226 C0603/SMD
NC PI5V330 R220 C150
C156 NC 22pF
22pF

FROM AV BOARD

FOR EXTERNAL TVD


USB_IR_EN
USB_IR_EN [3,10]
IR
IR [3,10,13]

VFE_GND1
VFE_GND1 [2,3,4,11]
JP2
2 2
R
R [2,3,4,11]
TVDPWR 1 2 TVDPWR
G JP5 JP8-PD SDA 3 4 SCL
G [2,3,4,11]
5 6 TP70
B Y1P 1 2 Y1N AVY1N SCL_V50 1 TP71 7 8 TP72
B [2,3,4,11]
PB1P 3 4 PB1N AVPB1N GND 2 CCIR_VCLK 9 10
SCL0 PR1P 5 6 PR1N AVPR1N SDA_V50 3 CCIR_V0 11 12 CCIR_V1
SCL0 [3,10] A-DTV-R
SDA0 7 8 4 CCIR_V2 13 14 CCIR_V3
SDA0 [3,10] USB_IR_EN USB_MP_ON A-DTV-L GPIO13
9 10 GND 5 15 16 CCIR_V4
GPIO3
SCL R375 NC IR 11 12 GND R347 10K 6 CCIR_V5 17 18 CCIR_V6
SCL [1,6,8,11]
SDA SCL0 USB_REV 13 14 USB_RST SDA0 CCIR_V7 19 20 TVD_CE R321 0
SDA [1,6,8,11] SDA1
R376 NC 15 16 GND R377 NC 6x1/NC

+5V 16x2 10x2


CCIR_VCLK DIP10X2/W/H/P2.0/4504/NC
CCIR_VCLK [3]
DIP10X2/W/H/P2.0/4504/NC

CCIR_V[0..7] CCIR_V[0..7] [3]


C231
0.1uF
SCL_V50 C0402/SMD
SCL_V50 [1,6,8,9]
SDA_V50
SDA_V50 [1,6,8,9]
AADCVSS
AADCVSS [1,3,8,9,10,11,12,14]
VFE_GND
VFE_GND [2,3,4,8,10,11,12,14]

VFE_GND1
VFE_GND1 [2,3,4,8,9,12]
+12V AVCVBS3
+12V [1,2,9,10,11,12,14] AVCVBS3 [10,14]
AVSY0
AVSY0 [10,14]
+5V AVSY1
+5V [1,2,4,6,8,9,10,11,12,13,14] AVSY1 [10,14]
AVSC1
AVSC1 [10,14]
1 1
SY1
SY1 [10,14]
SC1
SC1 [10,14]

TTE SHENZHEN R&D CENTER


Title
MT8202

Size Document Number Rev


C 2006-5-26 YWX

Date: Wednesday, December 27, 2006 Sheet 10 of 14


A B C  D E
A B C D E

AL
AL [3] AMP_+12V SPEAKER/HEADPHONE OUTPUT
AR
AR [3]
R233 20K

AOMCLK AOMCLK [3,11] R221 C152


AOBCLK AOBCLK [3,11] 47K 1000pF
AOLRCK AOLRCK [3,11] OPVREF

4
CE74 10uF/10V R234 10K R235 5.1K U17A

+
FB25 FB OPVREF CS4334 AUDIO DAC SPEAKER/HEADPHONE OUT AUSPR 2 - CE75 10uF/10V R239 51

+
AOSDATA1 AOSDATA1 [3] 1 SPOUTR
OPVREF 3 +
R231 + CE102 C151 C154 NJM4558 OPA C239
AVL_OUT 47K 22uF/16v 0.1uF + CE73 U15 2200pF 4.7uF/10v
AVL_OUT [11,14]

8
AVR_OUT 4.7uF AOSDATA1 R224 33 1 8 AUSPL OPVREF OPAV120 C0805/SMD
AVR_OUT [11,14] SDATA AOUTL
AOBCLK R225 33 2 7 DACVA
GNDA AOLRCK R228 33 DEM#/SCLK VA
GNDA [1,3,4,10,11,12] 3 LRCK AGND 6
AOMCLK R230 33 4 5 AUSPR +5V

2
4 MCLK AOUTR 4
+12V R240 10K Q9
+12V [1,2,9,10,11,12,14]
CS4334 2-CH AUDIO DAC A_MUTE 1 2SD2653K
SOP8/SMD
AMP_+12V R248 20K

3
RN38 U38
AMP_+12V AMP_+12V OPAV120 AOBCK-GPIO8 2 1 1 8 AV1OUPUT_L C157
R237 0 AOSDATA3 SDATA AOUTL 1000pF
4 3 2 DEM#/SCLK VA 7
LRCK-GPIO7 6 5 3 6

4
+5V AOMCLK-GPIO9 LRCK AGND AV1OUPUT_R C194 C193 CE85 10uF/10V R249 10K R250 5.1K U17B
8 7 4 MCLK AOUTR 5

+
0.1uuF 10uF/10v AUSPL 6 - CE86 10uF/10V R251 51

+
FB26 FB DACVA CS4334 2-CH AUDIO DAC C0402 C0805 7 SPOUTL
+ CE78 33x4 SOP8/SMD OPVREF 5 +
22uF/16V C232 C158 NJM4558 OPA C240
+ CE76 C153 CB175 0.1uF 2200pF 4.7uF/10v

8
4.7uF/25V 4.7uF 0.1uF C0402/SMD OPVREF OPAV120 C0805/SMD

R254 10K Q11


5VSB A_MUTE 1 2SD2653K
R59 0 Q14 R281
3

3 2

2N3906 4.7k
CB180

1
0.1uF R282 R283

R261 39K
4.7k 100 +5V AV2 BYPASS AUDIO OUTPUT

3
+ CE93
1 Q15 470uF/25v C159
2N3906 C330UF25V/D8H14 R31
HEADPHONE CONNECTOR 150pF
C NC
4

2
P4 R265 0 CE87 10uF/10V R266 12K R267 5.1K U18A

+
3 B E AR 2 - CE88 10uF/10V R268 51 3
+

HEADPHONE_L 1 1 AVR_OUT
R30 100 AMP_GND OP1VREF
3906 2 3 +
A_MUTE HEADPHONE_R 3 C160 NJM4558 OPA
AMP_GND 4 820pF

2
8

MUTE_CIRCUIT R149 NC R162 0 +5V 5 OP1VREF OPAV120


GPIO15 1 Q27 HP_DETECT 6
R286 2N3904 AMP_GND 7 12x1 W/HOUSING R.A
1k SOT23/SMD/NC R32 8202UP3_5 8

3
20K

DIP12/WH/P2.0/R
R272 39K
+5V AMP_+12V AMP_+12V
+5V [1,2,4,6,8,9,10,11,12,13,14]
GPIO15 C162
GPIO15
150pF
8202UP3_5 U16
4

8202UP3_5
R276 0 CE90 10uF/10V R277 12K R278 5.1K U18B

+
A_MUTE AL 6 - CE91 10uF/10V R279 51
A_MUTE [10,14]
+

GPIO11 HEADPHONE_R 1 42 HEADPHONE_L 7 AVL_OUT


AOSDATA3 GPIO11 [3,8] HPOR HPOL OP1VREF 5 +
AOMCLK-GPIO9 AOSDATA3 [3,11]
R127 2 41 CB192 R129 C163 NJM4558 OPA
AOBCK-GPIO8 AOMCLK-GPIO9[3,11] AVSS REFA
NC AMP_GND 10uF/10v NC 820pF
AOBCK-GPIO8 [3,11]
8

LRCK-GPIO7 3 40 C0805/SMD OP1VREF OPAV120


LRCK-GPIO7 [3,11] VSSBGR PVDDREG
TU_AURO C0603/SMD
TU_AURO [11,12,14]
TU_AULO CB188 4 39 CB194 CB193
TU_AULO [11,12,14] VREFR VREFL
4.7uF/10v 4.7uF/10v
SPOUTR C0805/SMD C0805/SMD SPOUTL 0.1uF
5 INR INL 38

C237 6 37 HP_DETECT C238


0.01uF MUTEN HP 0.01uF AMP_GND
7 PVDDPR PVDDPL 36
R275
CE111 CB191 OUTR+ 8 35 OUTL+ CB195 CE113 AV1 BYPASS AUDIO OUTPUT
220uF/25v 0.1uF OUTPR OUTPL 0.1uF 220uF/25V
C0603/SMD 9 34 C0603/SMD
2 PVSSR PVSSL 2
20K C186
10 33 150pF
4

PVSSR PVSSL R273 C189 R274 R280 5.1K U40A


AV1OUPUT_R C190 R284
11 PVSSR PVSSL 32 2 -
1 TU_AURO
12 31 +5V 10K OP1VREF 3 +
PVSSR PVSSL AMP_GND 0 10uF/10v NJM4558 OPA
13 30 C0805/SMD C185 10uF/10v 51
೼ICᑩ䚼ৠֵোഄ䖲᥹ PVSSR PVSSL
8

820pF OP1VREF OPAV120 C0805/SMD


OUTR- 14 29 OUTL-
AMP_GND OUTMR OUTML R337 R338
15 28 NC NC
+5V D24 1N4148 PVDDMR PVDDML
16 PROTN VOL1 27

17 SLEEPN VOL0 26
R527 R288
10K 18 25
DVSS MODE2
19 24

2
R336 10K CKIO MODE1 R340 20K C188
GPIO14 A_MUTE 1 Q21 20 23 0 150pF
4

GPIO14 2N3904 XO MODE0 R339 R285 0 C191 R287 R289 5.1K U40B
SOT23/SMD CB208 0 AV1OUPUT_L C192 R290
21 XI DVDD 22 6 -

3
10uF/10v 7 TU_AULO
C0805/SMD 10K OP1VREF 5 +
10uF/10v NJM4558 OPA
C0805/SMD C187 10uF/10v 51
8

820pF OP1VREF OPAV120 C0805/SMD


C235 C236
L76
BCK-4235 ( 22UH ) C170
0.01uF 0.01uF JP4 0.33uF/50v
C0805/SMD
+5V OUTL+ AMP_GND1

1
2
+12V
OUTL- 2

1
2
1 R334 DIP12/WH/P2.5/R 1
10K L77 BCK-4235 ( 22UH ) 3
R404
4 12x1 W/HOUSING R.A 47K

2
R335 L75
8202UP3_5 1 Q22 OUTR- C233
8202UP3_5

1
2
2N3904 0.01uF FB3 FB OP1VREF
SOT23/SMD BCK-4235 ( 22UH )

3
10K CB190 OUTR+ R121 CE5 C177 C176

1
2
4.7uF/10v C169 AMP_+12V 47K 10U/16U 4.7uF 0.1uF
C0805/SMD 0.33uF/50v 0603/SMD
YDA138 C234 C0805/SMD + CE92 0402/SMD TTE SHENZHEN R&D CENTER
L74 0.01uF 220uF/16v Title
BCK-4235 ( 22UH ) MT8202

Size Document Number Rev


AMP_GND C 2006-5-26 YWX

Date: Wednesday, December 27, 2006 Sheet 11 of 14


A B C  D E
A B C D E

Panel_Power

RN33 33x4
AN0 8 7
R291 R292 AP0 JP11
6 5
AN1 4 3
10k 10k AP1 2 1 1
2

2
2
3
PWM1 1 Q31 GPIO5
1 Q32 RN34 33x4 4
PWM1 GPIO5 AN2 8 7 5
AP2 6 5 6
+12V +5V PDTC143ZT PDTC143ZT CLK1- 4 3 7
SOT23/SMD SOT23/SMD CLK1+ 2 1 8
RN35 33x4 9
AN3 8 7 10 TU_CVBS0
TU_CVBS0 [12,14]
AP3 6 5 11 TU_AURO
4 TU_AURO [11,12,14] 4
AN4 4 3 12 TU_AULO
L44 TU_AULO [11,12,14]

3
3
AP4 2 1 13 +12V
+12V [1,2,9,10,11,12,14]
RN36 33x4 14 GND
AN5 8 7 15
FB LVDS_GND AP5 6 5 16
BEAD/SMD/0805 AN6 4 3 17
5A/32v AP6 2 1 18
F1 RN37 33x4 19
L45 FUSE/SMD 0603 CLK2-
LVDS OUT 8 7 20
CLK2+ 6 5 21
AN7 4 3 22
NC CE95 + 乘⬭LG PANEL AP7 2 1 23
BEAD/SMD/0805 C175 24
220uF/16v 0.1uF 25
C0603/SMD 26
U19 PWM_PANEL R293 0 27
PWM_PANEL Panel_Power
1 S1 D1 8 28
LVDS_GND 2 7 29
G1 D1
3 S2 D2 6 30
4 G2 D2 5

SI4943 FI-SE30P-HF
R294 LVDS/30P/P1.25/S
22k

LO = > LVDS POWER OFF


LVDS_GND
LVDS_GND [2]
HI = > LVDS POWER ON

2
GNDA R296
GNDA [1,3,4,8,9,11,14]
GPIO2 1 Q16 CB181
AADCVSS GPIO2 2N3904 0.1uF
AADCVSS [1,3,8,9,10,11,12,14] SOT23/SMD
2k

3
VFE_GND1
VFE_GND1 [2,3,4,8,9,10]
DV33B LVDS_GND
DV33B [7,8,9,12,13,14]
3 LVDS_GND 3

+5V
+5V [1,2,4,6,8,9,10,11,12,13,14]

TUNER+5V TUNER+5V
CLK1+
CLK1+ [3]
CLK1-
CLK1- [3]
CLK2+ R3
CLK2+ [3]
CLK2- 3K

2
CLK2- [3] CE197
AP[0..7] AP[0..7] [3] TU_CVBS1 R5 47 Q1
To: SCART1
1

+
2N3904
AN[0..7] AN[0..7] [3] R354

3
NC 22uF/10v R521 51 TU_CVBS0
R0603/SMD TU_CVBS0
DV33B R520
DV33B [7,8,9,12,13,14]
C6 20K
C6 [3,12]
R522 R523
330 75/NC

L1 FB TU_CBO_GND Tuner CVBS Direct Output

TUNER+5V

SCL_V50

2
2 SCL_V50 2

SDA_V50 TUNER+5V R16 47 1 Q3


0418
SDA_V50 2N3904
To: 8202

3
R18 75/18 TU_CVBS_SW
AVCVBS0
R163
10K
ADC_IN3 R19 R20
ADC_IN3 [3] Tuner_Reset
ADC_IN4 330 75

2
ADC_IN4 [3]
C6 1 Q33

Tuner CVBS Switching Output


PDTC143ZT
TP59 SOT23/SMD R60 0

ADC_IN3 R2 100

3
C38
0.1uF
C0402/SMD
TP60

ADC_IN4 R1 100 FROM Tuner


C39 V2
0.1uF
C0402/SMD
TUMPX1 R212 0 C139 10nF MPX1
MPX1

C48
Tuner Interface 1.8pF

JP6 AADCVSS
1 1
SCL_V50 1
+5V +12V SDA_V50 2
TUNER+5V 3
+

VFE_GND1 4 TUMPX2 R215 39K R216 39K CE70 47uF/16V MPX2


MPX2
L11 NC BEAD/SMD/0805 TU_CVBS1 5
TUNER+5V VFE_GND1 6
SIF1 TUMPX1 7
L9 FB C52 C53 TU1_MONO TUMPX2 8 C143 C144
BEAD/SMD/0805 0.1uF 4.7uF/10v VFE_GND1 9 15pF 15pF
C0402/SMD C0805/SMD Tuner_Reset 10
AADCVSS TTE SHENZHEN R&D CENTER
AADCVSS 10x2 Title
DIP10X2/W/H/P2.0/4504 MT8202
2006-1-4
Size Document Number Rev
C 2006-5-26 YWX

Date: Wednesday, December 27, 2006 Sheet 12 of 14


A B C  D E
A B C D E

ADC_IN2
ADC_IN2 [3,11]

4 4

IR
IR [3,10,13]
PWM0
PWM0 [3]
PWM1
PWM1 [3] DV33B V2
PWM_PANEL FOR CHI-MEI INVERTER
PWM_PANEL +5V
DV33B
DV33B [7,8,9,12,13,14]
CONNECTOR
R303 0/NC
+5V
+5V [1,2,4,6,8,9,10,11,12,13,14]
R304 0

R305
1k
TP78 J7

1
R306 2 +5V
BRIGHTNESS 3
BL_ON/OFF 4

2
R308 10k 5
PWM0 PWM_PANEL 1 Q17 CB185 R309
2N3904 1uF 0/NC
4.7k SOT23/SMD

3
SELECT Hi For External
12x1 W/HOUSING
SELECT R.A
SELECT Low For Internal
CB184 DIP12/WH/P2.0/R
0.1uF R311
0
3 3
GND

L39 L40
FB FB

BEAD/SMD/1206 BEAD/SMD/1206
V2
+5V
+5V

R315
10k R33
R111 NC
10K

2
R316
GPIO6 1 Q18
GPIO6 2N3904 C37
4.7k C241 SOT23/SMD 0.1uF

3
1uF/10v C0603/SMD
C0603/SMD
Inital pull up 9.26

Back Light circuit


2 2

ADC KEYPAD 8 KEY

5VSB
C0603/SMD

CB200
L46 FB 0.1uF JP9
1
ADC_IN2 R317 0 L47 FB ADCKEY 2
3
8202UP3_1 L3 FB LED 4
8202UP3_1
5
6
C171 IR L48 FB 7
0.1uF
C35
0.001uF FB12 7x1W/HOUSING
C0402/SMD DIP7/W/H/P2.0
FB
C178
0.01uF
C0402/SMD

1 1

TTE SHENZHEN R&D CENTER


Title
MT8202

Size Document Number Rev


C 2006-5-26 YWX

Date: Friday, March 30, 2007 Sheet 13 of 14


A B C  D E
A B C D E

AU_IN_L
GPIO DECRIPTION
AU_IN_L [9,14] ERO3/GPIO : LVDS GPIO
+12V
+12V [1,2,9,10,11,12,14] ERO2/UP3_5 : SDA
AVCVBS1
AVCVBS1 [11] ERO1/UP3_1 : LED1
TU_CVBS0
TU_CVBS0 [12,14] ERO0/UP3_0 : MAIN POWER SWITCH
ADC_IN0
ADC_IN0 [3,14] DE/GPIO : LVDS GPIO
CVBS_OUT DV33B
CVBS_OUT [9,14] VCLK/GPIO : LVDS GPIO
TU_AURO
TU_AURO [12,14] UP3_4 : SCL
TU_AULO R532
TU_AULO [12,14] AOSDATA5/GPIO1 : AUDIO AMPLIFIER CONTROL
NC
4 4

U39 GPIO2 : LVDS POWER SW


SCART1_FB 1 6 VCC Need 3V ~ 3.3V
B C GPIO3 : DTV_CE
2 GND VCC 5
3 4 SCARTFB
A Y GPIO4 : EEPROM WRITE PROTECT
SN74AUP1T97/NC
+5V GPIO5/TXD :TO PANEL ENABLE
+5V [1,2,4,6,8,9,10,11,12,13,14]
R533 + CE203 CB209
SCL NC 0.1uF/NC GPIO6/RXD : BACK LIGHT ON/OFF
SCL [1,6,11]
SDA 4.7uF/10V/NC
SDA [1,6,11] GPIO7 : SWITCH HEF4052
GPIO8 : SWITCH HEF4052
R345 33 GPIO9 : SWITCH AV BOARD HEF4052
FDAT AUSW0S0
FDAT GPIO10 :SWITCH AV BOARD HEF4052
GPIO10 R346 33 AUSW0S1 GPIO11 : +12V POWER CONTROL
GPIO10 R534
R27 SCART1_FB SCARTFB GPIO12 : NONE USE
SCL1 SCARTSEL
SCL1 GPIO13 : FOR PDP CONTROL
0
SCART_FB R348 R 33 SCARTFB GPIO14 : AUDIO AMP SLEEP
SCART_FB
GPIO15 : AUDIO AMP MUTE
R50 GPIO16 : RGB/YUV SWITCH
ACENT SUBWOOFER
ACENT GPIO17 : HDMI SCDT
CB1 C184 SB33B
0.1uF R NC GPIO18 : HDMI CABLE DETECT

2
C0603/SMD R153 C0402/SMD
A_MUTE 1
SDA : SDA (TTL MODE)
Q28
3 NC SCL : SCL (TTL MODE) 3

3
NC R101 R103
4.7K 4.7K GPIO/PWM0 : DIMMING
GPIO/PWM1 :TO PANEL EXTERNAL PWM
IOSDA R47 22 SDA OUT_27Mhz/GPIO : 27Mhz TO MT8293
GNDA IOSDA IOSCL R48 22 SCL
GNDA [1,3,4,8,9,11,12] IOSCL DE_SOG/GPIO : HDMI RESET
8202UP3_5 R530 0/NC
DV33B 8202UP3_5 8202UP3_4 R531 0/NC
DV33B [7,8,9,12,13,14] 8202UP3_4 CEN_DVI/GPIO : HDMI_CEN
A_MUTE JP3
A_MUTE [10,14] SDA0 : EXTERNAL DTV TXD
1 AVCVBS1/AVSY11 2 GNDV
1 2 SCL0 : EXTERNAL DTV RXD
2
AVCVBS2 3 4 GNDV
3 4 SDA1 : TVB_CE
DIP12/WH/P2.0/R AVCVBS3 5 6 GNDV
5 6 SCL1 : SCARTSEL
AVSY0 7 8 GNDV
7 8 ADCIN0 : SCART
AVSC0 9 10 GNDV
9 10 ADCIN1 : SCART
G 11 12 AVPR1N
11 12 ADCIN2 : ADCKEY
TUNER+5V R/AVSC1 13 14 AVPB1N
TUNER+5V 13 14 ADCIN3 : TUNER1
B 15 16 AVY1N
15 16 ADCIN4 : TUNER2
TU_CVBS0 17 18 SCARTSEL
17 18 P1: NO USE
CVBS_OUT 19 20 SCART1_FB
19 20 P3: NO USE
R357 AVR_OUT 21 22 AVL_OUT
10K R365 21 22 P4: NO USE

2
C155 R356 10K GNDA GNDA
23 24

2
R/AVSC1 Q8 C161 R367 23 24 R1: NO USE
1
3904 AVCVBS1/AVSY1 1 Q12 TU_AURO 25 26 TU_AULO
2 SOT23/SMD 3904 25 26 R2: FOR USB 2
22uF/10v R355
R358

3
10K 47 R366 SOT23/SMD GNDA 27 28 GNDA
27 28

3
R 22uF/10V 10K 47
R370 0 AVCVBS1 AU_IN_R 29 30 AU_IN_L AVSY1
29 30 AVSY1 [10,14]
R359 R360
1K 75 75/NC R368 R369 GNDA 31 32 GNDA AVSC1
31 32 AVSC1 [10,14]
330 75/NC
ADC_IN0 33 34 ADC_IN1 SY1
33 34 SY1 [10,14]
+5V 35 36 GNDV SC1
35 36 SC1 [10,14]
AUSW0S0 37 38 AUSW0S1 AVY1N
37 38 AVY1N [10,14]
SUBWOOFER 39 40 +12V AVPB1N
39 40 AVPB1N [10,14]
AVPR1N
AVPR1N [10,14]
TUNER+5V TUNER+5V
AVSY0
AVSY0 [10,14]
AVCVBS3
AVCVBS3 [10,14]
JP14

2
2
R362 R371 AVCVBS2
AVCVBS2 [10,14]
1 Q10 1 Q13
3904 TRANSISTOR NPN SMD(B-C-E) R
SOT23/SMD SOT23/SMD R [10,14]

3
3
47 47 G
R364 G [10,14]
AVSC1 R374 75 B
B [10,14]
AVSY1
AVL_OUT
AVL_OUT [11,14]
75 R372 R373 AVR_OUT
AVR_OUT [11,14]
R361 R363 330 75/NC
1K 75/NC +5V
+5V [1,2,4,6,8,9,10,11,12,13,14]
ADC_IN1
ADC_IN1 [3,14]
AVSC0
AVSC0 [10,14]
1 1
AU_IN_R
AU_IN_R [9,14]

2006-1-4

TTE SHENZHEN R&D CENTER


Title
MT8202

Size Document Number Rev


C 2006-5-26 YWX

Date: Wednesday, December 27, 2006 Sheet 14 of 14


A B C  D E
5 4 3 2 1

JP603

1 AV1_IN

6 AV1_IN_GND
Ouput Signal
Yellow

AV CVBS(Out)
3 AV1L_IN1
CVBS_OUT CVBS_OUT [1]
AVR_OUT AVR_OUT [1]
5 FB8 AVL_OUT
D11 100´ÅÖé AVL_OUT [1]
AV1_IN R118 18 AVCVBS1
D D
White AV1_IN 1 5 AV1L_IN 1 2 1 2
A D

1
2 AV1R_IN1 2
GND

1
1
AV1R_IN 3 4 AV1_IN_GND R119
B C C11 C13 56
NC/47pF NC/47pF

2
2
4
Red PESD3V3L4UG

2
AV1_IN_GND
3RCA_JACKAV

Input Signal
D12

AV2_IN 1 5 AV2R_IN
A D CVBS IN
2
JP604 GND
AV2L_IN 3 4 AV2_IN_GND
B C
AVCVBS1 AVCVBS1 [1]
1 AV2_IN
PESD3V3L4UG AVCVBS2 AVCVBS2 [1]
FB7
100´ÅÖéR96 18
AV2_IN AVCVBS2
6 AV2_IN_GND 1 2 1 2
Yellow

1
D9

1
1
3 AV2L_IN1 C7 C8 R101
AV_OUT 1 5 AVL_OUT NC/47pF NC/47pF 56 S-Video IN
A D

2
2
2
GND
AVR_OUT

2
5 3 4 AVSY0 AVSY0 [1]
B C
AV2_IN_GND AVSC0 AVSC0 [1]
White
2 AV2R_IN1 PESD3V3L4UG

4
Red
D10 Audio I/F
SY_IN 1 5 SUBWOOFER
3RCA_JACKAV A D
2 SCART-1 Audio(IN)
C GND C
SC_IN 3 4 SCT2_SC0_GND
B C
AV1R_IN AV1R_IN [2]
AV1L_IN AV1L_IN [2]
PESD3V3L4UG

JP605 SCART-2 Audio(IN)


SY_IN FB9 100´ÅÖé R46 18 AVSY0
1 AV_OUT 1 2 1 2 AV2R_IN AV2R_IN [2]

1
AV2L_IN AV2L_IN [2]

1
1
R42
6 C14 C15 56
Yellow NC/47pF NC/47pF SUBWOOFER

2
2
SUBWOOFER [1]

2
3 AVL_OUT
SCT2_SC0_GND
D13

5 PCR_IN 1 5
PC AUDIO(IN)
A D
2
White GND
PCL_IN 3 4 PCR_IN
B C PCR_IN [1]
2 AVR_OUT PCL_IN PCL_IN [1]

PESD3V3L4UG
4
Red

SC_IN FB10 100´ÅÖé R44 18 AVSC0


3RCA_JACKAV 1 2 1 2

1
1
R45 GNDA GNDV
C16 C17 56 SWV120
NC/47pF NC/47pF

2
2
2
SWV120
SCT2_SC0_GND

P3
B B
2 SUB_WOOFER
1

RCA1X1

Audio ( IN )

AV1L_IN1 FB2 100´ÅÖé R125 18 AV1L_IN


JP607 1 2 1 2 AV2L_IN1 FB16 100´ÅÖé R124 18 AV2L_IN PCR_IN1 FB3 100´ÅÖé R143 18 PCR_IN

1
1 2 1 2 1 2 1 2

1
1
1
1

3 R121

2
1
1
1
1

1 SY_IN C19 C18 10K/NC R98 R144

4
NC/47pF NC/47pF C20 C12 10K/NC C23 C24 10K/NC

2
2
NC/47pF NC/47pF NC/47pF NC/47pF

3
2
2
2
2
2

2 SC_IN
SCT2_SC0_GND
2
2

1
CONN-DIN4

AV2R_IN1 FB18 100´ÅÖé R122 18 AV2R_IN


1 2 1 2 PCL_IN1 FB5 100´ÅÖé R145 18 PCL_IN
1

1 2 1 2
1
1
1

P4 AV1R_IN1 FB17 100´ÅÖé R120 18 AV1R_IN R97


1
1

MSJ-035-12D 1 2 1 2 C21 C22 10K/NC R146


1

NC/47pF NC/47pF C25 C26 10K/NC


2
2

1
1

A PCL_IN1 R43 NC/47pF NC/47pF A


2
2
2

2
L C9 C10 10K/NC
2

PCR_IN1 NC/47pF NC/47pF


2
2

3
R
2

1
GND

Title

Size Document Number Rev


C

Date: Thursday, May 18, 2006 Sheet 0 of 0


5 4 3 2 1


1
1
5 4 3 R2 R3 2 1

1
1
22K R17 R16
22K
22K 22K

2
2
2
2

R4
Audio Switch

47K
R15
AV1R
1 2

47K
SWV120
AV2L
1 2
U2

R5
SWV120 SWV120

R14
1 16
B0 VCC

47K
AV2R 2 15
B2 A2

47K
1 2 PCL
D AUINR 3 14 1 2
BN A1 D

1
1
4 13 AUINL
R26 R27 B3 AN

R6
5 12
B1 A0

R13
47K 47K 6 11
INH A3

47K
AV3R

47K
1 2 7 10 SW0S0 AV1L
CE15 22uF/35V CE16 22uF/35V VEE S0 1 2

2
2
8 9 SW0S1
GND S1

+
+
R12
AV1R_IN 2 1 AV1R AV2R_IN 2 1 AV2R

R7
CD4052

47K
AV3L

1
1
SOP16/SMD

47K
PCR 1 2
R30 R31 1 2
22K 22K

1
1
1
1
R8 R9 R10 R11
Audio Input

2
2
22K 22K 22K
22K

2
2
2
2
SWV120

1
SWV120 SWV120
R147
47K SCART

1
1
R34 R35 CE21 22uF/35V

2
SCART-1

+
47K 47K PCR_IN 2 1 PCR
C AV1R_IN AV1R_IN [3] C

1
CE18 22uF/35V CE19 22uF/35V

2
2
AV1L_IN AV1L_IN [3]

+
+
AV1L_IN 2 1 AV1L AV2L_IN 2 1 AV2L R148
22K

1
1
SCART-2
R39 R40

2
22K 22K AV2R_IN AV2R_IN [3]
AV2L_IN AV2L_IN [3]

2
2
SCART-3
SWV120 AV3R_IN AV3R_IN [1]
AV3L_IN AV3L_IN [1]

1
SWV120 R149
SWV120 47K PC

1
CE22 22uF/35V

2
PCR_IN PCR_IN [1]

1
+
R29 PCL_IN 2 1 PCL PCL_IN PCL_IN [1]
R28 47K

1
47K
R150

2
CE17 22uF/35V

2
SW0S0 22K Audio S.W
B

+
AV3R_IN 2 1 AV3R B
2 AUSW0S0 AUSW0S0 [1]

1
AUSW0S1 AUSW0S1 [1]

2
R32 Q6
22K AUSW0S0 R33 10K 1 2N3904
1 2 SOT23/SMD

2
3
SWV120

Audio S.W Out


SWV120 AUINR AUINR [1]
SWV120 AUINL AUINL [1]
SWV120

1
R36

1
47K
R37 GNDA GNDV
CE20 22uF/35V

2
47K

+
AV3L_IN 2 1 AV3L

1
SW0S1
R38
A A
22K

2
Q7

2
AUSW0S1 R41 10K 1 2N3904
1 2 SOT23/SMD

3
Title

Size Document Number Rev


5 4 3 2 B 1

Date: Thursday, May 18, 2006 Sheet 0 of 0


4 3 2
5 1
SWV120

SWV120 OUTPUT SIGNAL I/F


AVCVBS1 1 2 GNDA

1
MT8202_EU_AV_Board_V1.1 1 2 GNDA

1
+ CE4 CB3
AVCVBS2 3 4 GNDA 47uF/16V 0.1uF
3 4

2
2
AVCVBS3 5 6 GNDA AV CVBS OUT
5 6
( 2 Layers ) CVBS_OUT CVBS_OUT [3]
AVSY0 7 8 GNDA AVR_OUT AVR_OUT [3]
7 8
D AVL_OUT AVL_OUT [3]
GNDA D
AVSC0 9 10 GNDA
9 10

11 12
CONNECT TO MAIN_BOARD 11 12 VIDEO I/F
13 14 AVV50
13 14
CVBS IN
15 16
15 16 AVV50

17 18 AVCVBS1

1
17 18 AVCVBS1 [3]

1
+ CE2 CB2
CVBS_OUT 19 20 47uF/16V 0.1uF AVCVBS2 AVCVBS2 [3]
19 20

2
2
AVR_OUT 21 22 AVL_OUT
21 22

GNDA 23 24 GNDA
23 24
S-Video IN
25 26 AVSY0 AVSY0 [3]
25 26
AVSC0 AVSC0 [3]
GNDA 27 28 GNDA
27 28

AUINR 29 30 AUINL
29 30

GNDA 31 32 GNDA
31 32
C VCC5_SW AUDIO I/F C
33 34 FB151
33 34
R141 220 AUINR AUINR [2]
AVV50 35 36 GNDA 1 2 10/0805 AUINL AUINL [2]
35 36

AUSW0S0 37 38 AUSW0S1 C204


37 38
100/0603 R142 75